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Bug 26161 - [GlobalISel] Value to vreg during IR to MachineInstr translation for aggregate type
Summary: [GlobalISel] Value to vreg during IR to MachineInstr translation for aggregat...
Status: RESOLVED FIXED
Alias: None
Product: libraries
Classification: Unclassified
Component: GlobalISel (show other bugs)
Version: trunk
Hardware: PC All
: P normal
Assignee: Amara Emerson
URL:
Keywords:
Depends on:
Blocks: 35360 35361 35359
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Reported: 2016-01-15 13:31 PST by Quentin Colombet
Modified: 2018-05-18 06:34 PDT (History)
5 users (show)

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Description Quentin Colombet 2016-01-15 13:31:40 PST
The design to handle aggregate types during IR translation in GlobalISel will need to be revisited to at least acknowledge that we choose the right approach.

At first, this is not critical that we don’t support aggregate types, thus a simple mapping one Value* to one Vreg is perfectly fine.

When we would add the support for such types, we have basically two options:
1. Replicate SDAG solution, i.e., more or less map one Value* to a list of Vregs (one Vreg per component).
2. Keep the mapping simple, i.e., one Value* to one (big) Vreg.

The pros and cons are discussed in the following thread:
http://lists.llvm.org/pipermail/llvm-dev/2016-January/094049.html

Although #2 seems preferable, we don’t have any actual experience on how well we would be to optimize this representation.
Comment 1 Amara Emerson 2018-05-18 06:34:19 PDT
We now split aggregates into multiple Regs as of r332449.