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Bug 33743 - DAG combiner asserts due to extend in-register size mismatch for shufflevector
Summary: DAG combiner asserts due to extend in-register size mismatch for shufflevector
Status: RESOLVED FIXED
Alias: None
Product: libraries
Classification: Unclassified
Component: Common Code Generator Code (show other bugs)
Version: trunk
Hardware: PC All
: P normal
Assignee: Unassigned LLVM Bugs
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2017-07-11 03:10 PDT by David Stuttard
Modified: 2017-11-18 15:59 PST (History)
3 users (show)

See Also:
Fixed By Commit(s): 315307

Attachments
Reproducer for shufflevec issue in DAGCombine (2.31 KB, text/plain)
2017-07-11 03:10 PDT, David Stuttard 		Details
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Description David Stuttard 2017-07-11 03:10:59 PDT 
Created attachment 18775 [details]
Reproducer for shufflevec issue in DAGCombine

This issue has been seen when compiling for the AMDGPU backend

llc -march=amdgcn shufflevec-dagcombine-issue.ll

This results in the following assert:

Assertion failed: VT.getSizeInBits() == Op.getValueSizeInBits() && "The sizes of the input and result must match in order to perform the " "extend in-register.", file ~\llvm\lib\CodeGen\SelectionDAG\SelectionDAG.cpp, line 1012

This looks like an issue in combineShuffleToVectorExtend
Comment 1 David Stuttard 2017-07-11 03:28:50 PDT 
I've got a potential fix for this issue

See https://reviews.llvm.org/D35241
Comment 2 Simon Pilgrim 2017-11-18 15:59:47 PST 
rL315307