LLVM Bugzilla is read-only and represents the historical archive of all LLVM issues filled before November 26, 2021. Use github to submit LLVM bugs

Bug 51566 - Missing transformation rotate(x) == 0 to x == 0
Summary: Missing transformation rotate(x) == 0 to x == 0
Status: RESOLVED FIXED
Alias: None
Product: libraries
Classification: Unclassified
Component: Scalar Optimizations (show other bugs)
Version: trunk
Hardware: PC Linux
: P enhancement
Assignee: Unassigned LLVM Bugs
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2021-08-20 14:51 PDT by David Bolvansky
Modified: 2021-09-03 12:36 PDT (History)
3 users (show)

See Also:
Fixed By Commit(s): fd807601a784


Attachments

Note You need to log in before you can comment on or make changes to this bug.
Description David Bolvansky 2021-08-20 14:51:09 PDT
bool test1(unsigned long long x)
{
  unsigned long long r = (x << 32) | (x >> 32);
  return r != 0;

}

bool test2(unsigned long long x)
{
  unsigned long long r = (x << 32) | (x >> 32);
  return r == ~0ULL;
}

Trunk -O3:
test1(unsigned long long):                              # @test1(unsigned long long)
        rol     rdi, 32
        test    rdi, rdi
        setne   al
        ret
test2(unsigned long long):                              # @test2(unsigned long long)
        rol     rdi, 32
        cmp     rdi, -1
        sete    al
        ret
test3(unsigned long long):                              # @test3(unsigned long long)
        rol     rdi, 32
        test    rdi, rdi
        setne   al
        ret


Current codegen:
https://godbolt.org/z/q78xxhWe4


----------------------------------------
define i1 @src(i64 %0) {
%1:
  %2 = fshr i64 %0, i64 %0, i64 32
  %3 = icmp ne i64 %2, 0
  ret i1 %3
}
=>
define i1 @tgt(i64 %0) {
%1:
  %2 = icmp ne i64 %0, 0
  ret i1 %2
}
Transformation seems to be correct!



----------------------------------------
define i1 @src(i64 %0) {
%1:
  %2 = fshr i64 %0, i64 %0, i64 32
  %3 = icmp ne i64 %2, -1
  ret i1 %3
}
=>
define i1 @tgt(i64 %0) {
%1:
  %2 = icmp ne i64 %0, -1
  ret i1 %2
}
Transformation seems to be correct!

Alive:
https://alive2.llvm.org/ce/z/kmrBvv
Comment 1 Sanjay Patel 2021-09-03 09:38:52 PDT
(In reply to David Bolvansky from comment #0)
> https://alive2.llvm.org/ce/z/kmrBvv

To generalize, the rotate amount can be anything if the result is checking if all bits are set/clear. 

So I think there are 8 cases to test:
1. Either fshl or fshr
2. Either eq or ne predicate
3. Either 0 or -1 icmp constant

So something like this (and we can substitute fshr/fshl):
https://alive2.llvm.org/ce/z/V-sEy9
Comment 2 Sanjay Patel 2021-09-03 12:36:00 PDT
Should be fixed with:
https://reviews.llvm.org/rGfd807601a784