According to the design in the language reference manual, the LLVM readio and writeio intrinsics should strongly order I/O memory accesses. However, the current implementation lowers these intrinsics to volatile loads and stores on ix86. These loads and stores may or may not be properly ordered, depending on the processor on which they run. The correct solution is not obvious. Certain fencing instructions are not found on older Pentium processors, and we will need a general fencing model for SMP systems anyway. Such a design has not been discussed, though, as far as I know.
This bug is obsolete.