I'm not sure this is technically a register allocator to-do, but we need a way to scavenge registers during frame index elimination and spilling for targets that need additional registers for creating large offsets, or cannot use immediate offsets in addresses during spilling. Examples of this in the PPC backend include using r0 as a scratch register during frame index elimination for creating constant offsets larger than 32k, and using r0 as an index register for saving and restoring vector registers, which can only use reg+reg addressing. Once this is done, all use of r0 should be removed from the PPC backend.
ARM backend now happily makes use of register scavenger. Nate is doing the work to move PPC over.
Evan, is this done?
No, PPC still needs this.
We have a register scavenger now, targets can switch over to using it as they please.