LLVM 20.0.0git
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This is the complete list of members for llvm::AMDGPULegalizerInfo, including all inherited members.
aliasActionDefinitions(unsigned OpcodeTo, unsigned OpcodeFrom) | llvm::LegalizerInfo | |
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM) | llvm::AMDGPULegalizerInfo | |
buildAbsGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, MachineRegisterInfo &MRI) const | llvm::AMDGPULegalizerInfo | |
buildMultiply(LegalizerHelper &Helper, MutableArrayRef< Register > Accum, ArrayRef< Register > Src0, ArrayRef< Register > Src1, bool UsePartialMad64_32, bool SeparateOddAlignedProducts) const | llvm::AMDGPULegalizerInfo | |
buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const | llvm::AMDGPULegalizerInfo | |
fixStoreSourceType(MachineIRBuilder &B, Register VData, LLT MemTy, bool IsFormat) const | llvm::AMDGPULegalizerInfo | |
getAction(const LegalityQuery &Query) const | llvm::LegalizerInfo | |
getAction(const MachineInstr &MI, const MachineRegisterInfo &MRI) const | llvm::LegalizerInfo | |
getActionDefinitions(unsigned Opcode) const | llvm::LegalizerInfo | |
getActionDefinitionsBuilder(unsigned Opcode) | llvm::LegalizerInfo | |
getActionDefinitionsBuilder(std::initializer_list< unsigned > Opcodes) | llvm::LegalizerInfo | |
getActionDefinitionsIdx(unsigned Opcode) const | llvm::LegalizerInfo | |
getExtOpcodeForWideningConstant(LLT SmallTy) const | llvm::LegalizerInfo | virtual |
getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const | llvm::AMDGPULegalizerInfo | |
getLDSKernelId(Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
getLegacyLegalizerInfo() const | llvm::LegalizerInfo | inline |
getLegacyLegalizerInfo() | llvm::LegalizerInfo | inline |
getOpcodeIdxForOpcode(unsigned Opcode) const | llvm::LegalizerInfo | |
getScaledLogInput(MachineIRBuilder &B, Register Src, unsigned Flags) const | llvm::AMDGPULegalizerInfo | |
getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg, bool ImageStore=false) const | llvm::AMDGPULegalizerInfo | |
isLegal(const LegalityQuery &Query) const | llvm::LegalizerInfo | inline |
isLegal(const MachineInstr &MI, const MachineRegisterInfo &MRI) const | llvm::LegalizerInfo | |
isLegalOrCustom(const LegalityQuery &Query) const | llvm::LegalizerInfo | inline |
isLegalOrCustom(const MachineInstr &MI, const MachineRegisterInfo &MRI) const | llvm::LegalizerInfo | |
legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const | llvm::AMDGPULegalizerInfo | |
legalizeBufferLoad(MachineInstr &MI, LegalizerHelper &Helper, bool IsFormat, bool IsTyped) const | llvm::AMDGPULegalizerInfo | |
legalizeBufferStore(MachineInstr &MI, LegalizerHelper &Helper, bool IsTyped, bool IsFormat) const | llvm::AMDGPULegalizerInfo | |
legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeCTLZ_ZERO_UNDEF(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override | llvm::AMDGPULegalizerInfo | virtual |
legalizeDebugTrap(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFExp2(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, Register Src, unsigned Flags) const | llvm::AMDGPULegalizerInfo | |
legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFFREXP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFlog2(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFlogCommon(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, Register Src, bool IsLog10, unsigned Flags) const | llvm::AMDGPULegalizerInfo | |
legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const | llvm::AMDGPULegalizerInfo | |
legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFSQRT(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFSQRTF16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFSQRTF32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeFSQRTF64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeGetFPEnv(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeImageIntrinsic(MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const | llvm::AMDGPULegalizerInfo | |
legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override | llvm::AMDGPULegalizerInfo | virtual |
legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const | llvm::AMDGPULegalizerInfo | |
legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const | llvm::AMDGPULegalizerInfo | |
legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B, uint64_t Offset, Align Alignment=Align(4)) const | llvm::AMDGPULegalizerInfo | |
legalizeLaneOp(LegalizerHelper &Helper, MachineInstr &MI, Intrinsic::ID IID) const | llvm::AMDGPULegalizerInfo | |
legalizeLDSKernelId(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const | llvm::AMDGPULegalizerInfo | |
legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const | llvm::AMDGPULegalizerInfo | |
legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const | llvm::AMDGPULegalizerInfo | |
legalizePointerAsRsrcIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const | llvm::AMDGPULegalizerInfo | |
legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const | llvm::AMDGPULegalizerInfo | |
legalizeSBufferPrefetch(LegalizerHelper &Helper, MachineInstr &MI) const | llvm::AMDGPULegalizerInfo | |
legalizeSetFPEnv(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeStackSave(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeStore(LegalizerHelper &Helper, MachineInstr &MI) const | llvm::AMDGPULegalizerInfo | |
legalizeTrap(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const | llvm::AMDGPULegalizerInfo | |
legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const | llvm::AMDGPULegalizerInfo | |
legalizeWaveID(MachineInstr &MI, MachineIRBuilder &B) const | llvm::AMDGPULegalizerInfo | |
legalizeWorkitemIDIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const | llvm::AMDGPULegalizerInfo | |
loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg, const TargetRegisterClass *ArgRC, LLT ArgTy) const | llvm::AMDGPULegalizerInfo | |
loadInputValue(Register DstReg, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const | llvm::AMDGPULegalizerInfo | |
splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const | llvm::AMDGPULegalizerInfo | |
verify(const MCInstrInfo &MII) const | llvm::LegalizerInfo | |
~LegalizerInfo()=default | llvm::LegalizerInfo | virtual |