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LLVM 20.0.0git
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This is the complete list of members for llvm::CSEMIRBuilder, including all inherited members.
| buildAbs(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) | llvm::MachineIRBuilder | inline |
| buildAnyExt(const DstOp &Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal) | llvm::MachineIRBuilder | inline |
| buildAssertInstr(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val) | llvm::MachineIRBuilder | inline |
| buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size) | llvm::MachineIRBuilder | inline |
| buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size) | llvm::MachineIRBuilder | inline |
| buildAtomicCmpXchg(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildBitcast(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildBitReverse(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildBlockAddress(Register Res, const BlockAddress *BA) | llvm::MachineIRBuilder | |
| buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP) | llvm::MachineIRBuilder | |
| buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP) | llvm::MachineIRBuilder | |
| buildBr(MachineBasicBlock &Dest) | llvm::MachineIRBuilder | |
| buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest) | llvm::MachineIRBuilder | |
| buildBrIndirect(Register Tgt) | llvm::MachineIRBuilder | |
| buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg) | llvm::MachineIRBuilder | |
| buildBSwap(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops) | llvm::MachineIRBuilder | |
| buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops) | llvm::MachineIRBuilder | |
| buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops) | llvm::MachineIRBuilder | |
| buildCast(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | |
| buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops) | llvm::MachineIRBuilder | |
| buildConstant(const DstOp &Res, const ConstantInt &Val) override | llvm::CSEMIRBuilder | virtual |
| buildConstant(const DstOp &Res, const ConstantInt &Val) | llvm::CSEMIRBuilder | virtual |
| buildConstant(const DstOp &Res, int64_t Val) | llvm::CSEMIRBuilder | |
| buildConstant(const DstOp &Res, const APInt &Val) | llvm::CSEMIRBuilder | |
| buildConstantPool(const DstOp &Res, unsigned Idx) | llvm::MachineIRBuilder | |
| buildConstantPtrAuth(const DstOp &Res, const ConstantPtrAuth *CPA, Register Addr, Register AddrDisc) | llvm::MachineIRBuilder | |
| buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr) | llvm::MachineIRBuilder | |
| buildCopy(const DstOp &Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildCTLZ(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildCTPOP(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildCTTZ(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildDbgLabel(const MDNode *Label) | llvm::MachineIRBuilder | |
| buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0) | llvm::MachineIRBuilder | |
| buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr) | llvm::MachineIRBuilder | |
| buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment) | llvm::MachineIRBuilder | |
| buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index) | llvm::MachineIRBuilder | |
| buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Index) | llvm::MachineIRBuilder | |
| buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx) | llvm::MachineIRBuilder | |
| buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx) | llvm::MachineIRBuilder | inline |
| buildFAbs(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | |
| buildFConstant(const DstOp &Res, const ConstantFP &Val) override | llvm::CSEMIRBuilder | virtual |
| buildFConstant(const DstOp &Res, const ConstantFP &Val) | llvm::CSEMIRBuilder | virtual |
| buildFConstant(const DstOp &Res, double Val) | llvm::CSEMIRBuilder | |
| buildFConstant(const DstOp &Res, const APFloat &Val) | llvm::CSEMIRBuilder | |
| buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) | llvm::MachineIRBuilder | inline |
| buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFence(unsigned Ordering, unsigned Scope) | llvm::MachineIRBuilder | |
| buildFExp2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFFloor(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr) | llvm::MachineIRBuilder | |
| buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFLog(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFLog2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFNeg(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | |
| buildFrameIndex(const DstOp &Res, int Idx) | llvm::MachineIRBuilder | |
| buildFreeze(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildGetFPEnv(const DstOp &Dst) | llvm::MachineIRBuilder | inline |
| buildGetFPMode(const DstOp &Dst) | llvm::MachineIRBuilder | inline |
| buildGlobalValue(const DstOp &Res, const GlobalValue *GV) | llvm::MachineIRBuilder | |
| buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | |
| buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr) | llvm::MachineIRBuilder | |
| buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index) | llvm::MachineIRBuilder | |
| buildInsertSubvector(const DstOp &Res, const SrcOp &Src0, const SrcOp &Src1, unsigned Index) | llvm::MachineIRBuilder | |
| buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx) | llvm::MachineIRBuilder | |
| buildInstr(unsigned Opc, ArrayRef< DstOp > DstOps, ArrayRef< SrcOp > SrcOps, std::optional< unsigned > Flag=std::nullopt) override | llvm::CSEMIRBuilder | virtual |
| llvm::MachineIRBuilder::buildInstr(unsigned Opcode) | llvm::MachineIRBuilder | inline |
| buildInstrNoInsert(unsigned Opcode) | llvm::MachineIRBuilder | |
| buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent) | llvm::MachineIRBuilder | |
| buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res) | llvm::MachineIRBuilder | |
| buildIntrinsic(Intrinsic::ID ID, ArrayRef< DstOp > Res, bool HasSideEffects, bool isConvergent) | llvm::MachineIRBuilder | |
| buildIntrinsic(Intrinsic::ID ID, ArrayRef< DstOp > Res) | llvm::MachineIRBuilder | |
| buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildIntToPtr(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildIsFPClass(const DstOp &Res, const SrcOp &Src, unsigned Mask) | llvm::MachineIRBuilder | inline |
| buildJumpTable(const LLT PtrTy, unsigned JTI) | llvm::MachineIRBuilder | |
| buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO) | llvm::MachineIRBuilder | inline |
| buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) | llvm::MachineIRBuilder | |
| buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset) | llvm::MachineIRBuilder | |
| buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits) | llvm::MachineIRBuilder | |
| buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO) | llvm::MachineIRBuilder | inline |
| buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO) | llvm::MachineIRBuilder | inline |
| buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops) | llvm::MachineIRBuilder | |
| buildMergeLikeInstr(const DstOp &Res, std::initializer_list< SrcOp > Ops) | llvm::MachineIRBuilder | |
| buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops) | llvm::MachineIRBuilder | |
| buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildNeg(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildNot(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0) | llvm::MachineIRBuilder | |
| buildPrefetch(const SrcOp &Addr, unsigned RW, unsigned Locality, unsigned CacheType, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | |
| buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | inline |
| buildPtrToInt(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildResetFPEnv() | llvm::MachineIRBuilder | inline |
| buildResetFPMode() | llvm::MachineIRBuilder | inline |
| buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt) | llvm::MachineIRBuilder | inline |
| buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt) | llvm::MachineIRBuilder | inline |
| buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn) | llvm::MachineIRBuilder | inline |
| buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | inline |
| buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width) | llvm::MachineIRBuilder | inline |
| buildSCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | |
| buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | |
| buildSetFPEnv(const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildSetFPMode(const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildSExt(const DstOp &Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) | llvm::MachineIRBuilder | inline |
| buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildShuffleSplat(const DstOp &Res, const SrcOp &Src) | llvm::MachineIRBuilder | |
| buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask) | llvm::MachineIRBuilder | |
| buildSITOFP(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) | llvm::MachineIRBuilder | inline |
| buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) | llvm::MachineIRBuilder | inline |
| buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildSplatBuildVector(const DstOp &Res, const SrcOp &Src) | llvm::MachineIRBuilder | |
| buildSplatVector(const DstOp &Res, const SrcOp &Val) | llvm::MachineIRBuilder | |
| buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn) | llvm::MachineIRBuilder | inline |
| buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | inline |
| buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO) | llvm::MachineIRBuilder | |
| buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) | llvm::MachineIRBuilder | |
| buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildTrap(bool Debug=false) | llvm::MachineIRBuilder | inline |
| buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | |
| buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn) | llvm::MachineIRBuilder | inline |
| buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | inline |
| buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width) | llvm::MachineIRBuilder | inline |
| buildUCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | |
| buildUITOFP(const DstOp &Dst, const SrcOp &Src0) | llvm::MachineIRBuilder | inline |
| buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) | llvm::MachineIRBuilder | inline |
| buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) | llvm::MachineIRBuilder | inline |
| buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildUndef(const DstOp &Res) | llvm::MachineIRBuilder | |
| buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildUnmerge(ArrayRef< Register > Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildUnmerge(LLT Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | inline |
| buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn) | llvm::MachineIRBuilder | inline |
| buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1) | llvm::MachineIRBuilder | inline |
| buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn) | llvm::MachineIRBuilder | inline |
| buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceFMaximum(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceFMinimum(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn) | llvm::MachineIRBuilder | inline |
| buildVecReduceMul(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceOr(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn) | llvm::MachineIRBuilder | inline |
| buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn) | llvm::MachineIRBuilder | inline |
| buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVecReduceXor(const DstOp &Dst, const SrcOp &Src) | llvm::MachineIRBuilder | inline |
| buildVScale(const DstOp &Res, unsigned MinElts) | llvm::MachineIRBuilder | |
| buildVScale(const DstOp &Res, const ConstantInt &MinElts) | llvm::MachineIRBuilder | |
| buildVScale(const DstOp &Res, const APInt &MinElts) | llvm::MachineIRBuilder | |
| buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1) | llvm::MachineIRBuilder | inline |
| buildZExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt) | llvm::MachineIRBuilder | |
| buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) | llvm::MachineIRBuilder | |
| buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op) | llvm::MachineIRBuilder | |
| getBoolExtOp(bool IsVec, bool IsFP) const | llvm::MachineIRBuilder | |
| getContext() const | llvm::MachineIRBuilder | inline |
| getCSEInfo() | llvm::MachineIRBuilder | inline |
| getCSEInfo() const | llvm::MachineIRBuilder | inline |
| getDataLayout() const | llvm::MachineIRBuilder | inline |
| getDebugLoc() | llvm::MachineIRBuilder | inline |
| getDL() | llvm::MachineIRBuilder | inline |
| getInsertPt() | llvm::MachineIRBuilder | inline |
| getMBB() const | llvm::MachineIRBuilder | inline |
| getMBB() | llvm::MachineIRBuilder | inline |
| getMF() | llvm::MachineIRBuilder | inline |
| getMF() const | llvm::MachineIRBuilder | inline |
| getMMRAMetadata() | llvm::MachineIRBuilder | inline |
| getMRI() | llvm::MachineIRBuilder | inline |
| getMRI() const | llvm::MachineIRBuilder | inline |
| getObserver() | llvm::MachineIRBuilder | inline |
| getPCSections() | llvm::MachineIRBuilder | inline |
| getState() | llvm::MachineIRBuilder | inline |
| getTII() | llvm::MachineIRBuilder | inline |
| insertInstr(MachineInstrBuilder MIB) | llvm::MachineIRBuilder | |
| isObservingChanges() const | llvm::MachineIRBuilder | inline |
| MachineIRBuilder()=default | llvm::CSEMIRBuilder | |
| MachineIRBuilder(MachineFunction &MF) | llvm::CSEMIRBuilder | inline |
| MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) | llvm::CSEMIRBuilder | inline |
| MachineIRBuilder(MachineInstr &MI) | llvm::CSEMIRBuilder | inline |
| MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) | llvm::CSEMIRBuilder | inline |
| MachineIRBuilder(const MachineIRBuilderState &BState) | llvm::CSEMIRBuilder | inline |
| materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value) | llvm::MachineIRBuilder | |
| recordInsertion(MachineInstr *InsertedInstr) const | llvm::MachineIRBuilder | inlineprotected |
| setChangeObserver(GISelChangeObserver &Observer) | llvm::MachineIRBuilder | inline |
| setCSEInfo(GISelCSEInfo *Info) | llvm::MachineIRBuilder | inline |
| setDebugLoc(const DebugLoc &DL) | llvm::MachineIRBuilder | inline |
| setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) | llvm::MachineIRBuilder | inline |
| setInstr(MachineInstr &MI) | llvm::MachineIRBuilder | inline |
| setInstrAndDebugLoc(MachineInstr &MI) | llvm::MachineIRBuilder | inline |
| setMBB(MachineBasicBlock &MBB) | llvm::MachineIRBuilder | inline |
| setMF(MachineFunction &MF) | llvm::MachineIRBuilder | |
| setMMRAMetadata(MDNode *MMRA) | llvm::MachineIRBuilder | inline |
| setPCSections(MDNode *MD) | llvm::MachineIRBuilder | inline |
| setState(const MachineIRBuilderState &NewState) | llvm::MachineIRBuilder | inline |
| stopObservingChanges() | llvm::MachineIRBuilder | inline |
| validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1) | llvm::MachineIRBuilder | protected |
| validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty) | llvm::MachineIRBuilder | protected |
| validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1) | llvm::MachineIRBuilder | protected |
| validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend) | llvm::MachineIRBuilder | protected |
| validateUnaryOp(const LLT Res, const LLT Op0) | llvm::MachineIRBuilder | protected |
| ~MachineIRBuilder()=default | llvm::MachineIRBuilder | virtual |
1.9.6