| addDelegate(Delegate *delegate) | llvm::MachineRegisterInfo | inline |
| addLiveIn(MCRegister Reg, Register vreg=Register()) | llvm::MachineRegisterInfo | inline |
| addPhysRegsUsedFromRegMask(const uint32_t *RegMask) | llvm::MachineRegisterInfo | inline |
| addRegAllocationHint(Register VReg, Register PrefReg) | llvm::MachineRegisterInfo | inline |
| addRegOperandToUseList(MachineOperand *MO) | llvm::MachineRegisterInfo | |
| canReserveReg(MCRegister PhysReg) const | llvm::MachineRegisterInfo | inline |
| clearKillFlags(Register Reg) const | llvm::MachineRegisterInfo | |
| clearSimpleHint(Register VReg) | llvm::MachineRegisterInfo | inline |
| clearVirtRegs() | llvm::MachineRegisterInfo | |
| clearVirtRegTypes() | llvm::MachineRegisterInfo | |
| cloneVirtualRegister(Register VReg, StringRef Name="") | llvm::MachineRegisterInfo | |
| constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0) | llvm::MachineRegisterInfo | |
| constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0) | llvm::MachineRegisterInfo | |
| createGenericVirtualRegister(LLT Ty, StringRef Name="") | llvm::MachineRegisterInfo | |
| createIncompleteVirtualRegister(StringRef Name="") | llvm::MachineRegisterInfo | |
| createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="") | llvm::MachineRegisterInfo | |
| createVirtualRegister(VRegAttrs RegAttr, StringRef Name="") | llvm::MachineRegisterInfo | |
| def_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| def_bundle_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| def_bundle_end() | llvm::MachineRegisterInfo | inlinestatic |
| def_bundle_iterator typedef | llvm::MachineRegisterInfo | |
| def_bundles(Register Reg) const | llvm::MachineRegisterInfo | inline |
| def_empty(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| def_end() | llvm::MachineRegisterInfo | inlinestatic |
| def_instr_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| def_instr_end() | llvm::MachineRegisterInfo | inlinestatic |
| def_instr_iterator typedef | llvm::MachineRegisterInfo | |
| def_instructions(Register Reg) const | llvm::MachineRegisterInfo | inline |
| def_iterator typedef | llvm::MachineRegisterInfo | |
| def_operands(Register Reg) const | llvm::MachineRegisterInfo | inline |
| defusechain_instr_iterator | llvm::MachineRegisterInfo | friend |
| defusechain_iterator | llvm::MachineRegisterInfo | friend |
| disableCalleeSavedRegister(MCRegister Reg) | llvm::MachineRegisterInfo | |
| dumpUses(Register RegNo) const | llvm::MachineRegisterInfo | |
| EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) | llvm::MachineRegisterInfo | |
| freezeReservedRegs() | llvm::MachineRegisterInfo | |
| getCalleeSavedRegs() const | llvm::MachineRegisterInfo | |
| getLiveInPhysReg(Register VReg) const | llvm::MachineRegisterInfo | |
| getLiveInVirtReg(MCRegister PReg) const | llvm::MachineRegisterInfo | |
| getMaxLaneMaskForVReg(Register Reg) const | llvm::MachineRegisterInfo | |
| getMF() const | llvm::MachineRegisterInfo | inline |
| getNumVirtRegs() const | llvm::MachineRegisterInfo | inline |
| getOneDef(Register Reg) const | llvm::MachineRegisterInfo | inline |
| getPressureSets(Register RegUnit) const | llvm::MachineRegisterInfo | inline |
| getRegAllocationHint(Register VReg) const | llvm::MachineRegisterInfo | inline |
| getRegAllocationHints(Register VReg) const | llvm::MachineRegisterInfo | inline |
| getRegBankOrNull(Register Reg) const | llvm::MachineRegisterInfo | inline |
| getRegClass(Register Reg) const | llvm::MachineRegisterInfo | inline |
| getRegClassOrNull(Register Reg) const | llvm::MachineRegisterInfo | inline |
| getRegClassOrRegBank(Register Reg) const | llvm::MachineRegisterInfo | inline |
| getReservedRegs() const | llvm::MachineRegisterInfo | inline |
| getSimpleHint(Register VReg) const | llvm::MachineRegisterInfo | inline |
| getTargetRegisterInfo() const | llvm::MachineRegisterInfo | inline |
| getType(Register Reg) const | llvm::MachineRegisterInfo | inline |
| getUniqueVRegDef(Register Reg) const | llvm::MachineRegisterInfo | |
| getUsedPhysRegsMask() const | llvm::MachineRegisterInfo | inline |
| getVRegAttrs(Register Reg) const | llvm::MachineRegisterInfo | inline |
| getVRegDef(Register Reg) const | llvm::MachineRegisterInfo | |
| getVRegName(Register Reg) const | llvm::MachineRegisterInfo | inline |
| hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const | llvm::MachineRegisterInfo | |
| hasOneDef(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| hasOneNonDBGUse(Register RegNo) const | llvm::MachineRegisterInfo | |
| hasOneNonDBGUser(Register RegNo) const | llvm::MachineRegisterInfo | |
| hasOneUse(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| insertVRegByName(StringRef Name, Register Reg) | llvm::MachineRegisterInfo | inline |
| invalidateLiveness() | llvm::MachineRegisterInfo | inline |
| isAllocatable(MCRegister PhysReg) const | llvm::MachineRegisterInfo | inline |
| isConstantPhysReg(MCRegister PhysReg) const | llvm::MachineRegisterInfo | |
| isLiveIn(Register Reg) const | llvm::MachineRegisterInfo | |
| isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const | llvm::MachineRegisterInfo | |
| isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const | llvm::MachineRegisterInfo | |
| isReserved(MCRegister PhysReg) const | llvm::MachineRegisterInfo | inline |
| isReservedRegUnit(unsigned Unit) const | llvm::MachineRegisterInfo | |
| isSSA() const | llvm::MachineRegisterInfo | inline |
| isUpdatedCSRsInitialized() const | llvm::MachineRegisterInfo | inline |
| leaveSSA() | llvm::MachineRegisterInfo | inline |
| livein_begin() const | llvm::MachineRegisterInfo | inline |
| livein_empty() const | llvm::MachineRegisterInfo | inline |
| livein_end() const | llvm::MachineRegisterInfo | inline |
| livein_iterator typedef | llvm::MachineRegisterInfo | |
| liveins() const | llvm::MachineRegisterInfo | inline |
| MachineRegisterInfo(MachineFunction *MF) | llvm::MachineRegisterInfo | explicit |
| MachineRegisterInfo(const MachineRegisterInfo &)=delete | llvm::MachineRegisterInfo | |
| markUsesInDebugValueAsUndef(Register Reg) const | llvm::MachineRegisterInfo | |
| moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps) | llvm::MachineRegisterInfo | |
| noteCloneVirtualRegister(Register NewReg, Register SrcReg) | llvm::MachineRegisterInfo | inline |
| noteNewVirtualRegister(Register Reg) | llvm::MachineRegisterInfo | inline |
| operator=(const MachineRegisterInfo &)=delete | llvm::MachineRegisterInfo | |
| recomputeRegClass(Register Reg) | llvm::MachineRegisterInfo | |
| reg_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_bundle_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_bundle_end() | llvm::MachineRegisterInfo | inlinestatic |
| reg_bundle_iterator typedef | llvm::MachineRegisterInfo | |
| reg_bundle_nodbg_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_bundle_nodbg_end() | llvm::MachineRegisterInfo | inlinestatic |
| reg_bundle_nodbg_iterator typedef | llvm::MachineRegisterInfo | |
| reg_bundles(Register Reg) const | llvm::MachineRegisterInfo | inline |
| reg_empty(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_end() | llvm::MachineRegisterInfo | inlinestatic |
| reg_instr_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_instr_end() | llvm::MachineRegisterInfo | inlinestatic |
| reg_instr_iterator typedef | llvm::MachineRegisterInfo | |
| reg_instr_nodbg_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_instr_nodbg_end() | llvm::MachineRegisterInfo | inlinestatic |
| reg_instr_nodbg_iterator typedef | llvm::MachineRegisterInfo | |
| reg_instructions(Register Reg) const | llvm::MachineRegisterInfo | inline |
| reg_iterator typedef | llvm::MachineRegisterInfo | |
| reg_nodbg_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_nodbg_bundles(Register Reg) const | llvm::MachineRegisterInfo | inline |
| reg_nodbg_empty(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| reg_nodbg_end() | llvm::MachineRegisterInfo | inlinestatic |
| reg_nodbg_instructions(Register Reg) const | llvm::MachineRegisterInfo | inline |
| reg_nodbg_iterator typedef | llvm::MachineRegisterInfo | |
| reg_nodbg_operands(Register Reg) const | llvm::MachineRegisterInfo | inline |
| reg_operands(Register Reg) const | llvm::MachineRegisterInfo | inline |
| removeRegOperandFromUseList(MachineOperand *MO) | llvm::MachineRegisterInfo | |
| replaceRegWith(Register FromReg, Register ToReg) | llvm::MachineRegisterInfo | |
| reservedRegsFrozen() const | llvm::MachineRegisterInfo | inline |
| reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) | llvm::MachineRegisterInfo | inline |
| resetDelegate(Delegate *delegate) | llvm::MachineRegisterInfo | inline |
| setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs) | llvm::MachineRegisterInfo | |
| setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) | llvm::MachineRegisterInfo | inline |
| setRegBank(Register Reg, const RegisterBank &RegBank) | llvm::MachineRegisterInfo | |
| setRegClass(Register Reg, const TargetRegisterClass *RC) | llvm::MachineRegisterInfo | |
| setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB) | llvm::MachineRegisterInfo | inline |
| setSimpleHint(Register VReg, Register PrefReg) | llvm::MachineRegisterInfo | inline |
| setType(Register VReg, LLT Ty) | llvm::MachineRegisterInfo | |
| shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const | llvm::MachineRegisterInfo | inline |
| shouldTrackSubRegLiveness(Register VReg) const | llvm::MachineRegisterInfo | inline |
| subRegLivenessEnabled() const | llvm::MachineRegisterInfo | inline |
| tracksLiveness() const | llvm::MachineRegisterInfo | inline |
| updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const | llvm::MachineRegisterInfo | inline |
| use_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_bundle_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_bundle_end() | llvm::MachineRegisterInfo | inlinestatic |
| use_bundle_iterator typedef | llvm::MachineRegisterInfo | |
| use_bundle_nodbg_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_bundle_nodbg_end() | llvm::MachineRegisterInfo | inlinestatic |
| use_bundle_nodbg_iterator typedef | llvm::MachineRegisterInfo | |
| use_bundles(Register Reg) const | llvm::MachineRegisterInfo | inline |
| use_empty(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_end() | llvm::MachineRegisterInfo | inlinestatic |
| use_instr_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_instr_end() | llvm::MachineRegisterInfo | inlinestatic |
| use_instr_iterator typedef | llvm::MachineRegisterInfo | |
| use_instr_nodbg_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_instr_nodbg_end() | llvm::MachineRegisterInfo | inlinestatic |
| use_instr_nodbg_iterator typedef | llvm::MachineRegisterInfo | |
| use_instructions(Register Reg) const | llvm::MachineRegisterInfo | inline |
| use_iterator typedef | llvm::MachineRegisterInfo | |
| use_nodbg_begin(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_nodbg_bundles(Register Reg) const | llvm::MachineRegisterInfo | inline |
| use_nodbg_empty(Register RegNo) const | llvm::MachineRegisterInfo | inline |
| use_nodbg_end() | llvm::MachineRegisterInfo | inlinestatic |
| use_nodbg_instructions(Register Reg) const | llvm::MachineRegisterInfo | inline |
| use_nodbg_iterator typedef | llvm::MachineRegisterInfo | |
| use_nodbg_operands(Register Reg) const | llvm::MachineRegisterInfo | inline |
| use_operands(Register Reg) const | llvm::MachineRegisterInfo | inline |
| verifyUseList(Register Reg) const | llvm::MachineRegisterInfo | |
| verifyUseLists() const | llvm::MachineRegisterInfo | |
