|
LLVM 20.0.0git
|
This is the complete list of members for llvm::R600InstrInfo, including all inherited members.
| addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const | llvm::R600InstrInfo | |
| ALU_VEC_012_SCL_210 enum value | llvm::R600InstrInfo | |
| ALU_VEC_021_SCL_122 enum value | llvm::R600InstrInfo | |
| ALU_VEC_102_SCL_221 enum value | llvm::R600InstrInfo | |
| ALU_VEC_120_SCL_212 enum value | llvm::R600InstrInfo | |
| ALU_VEC_201 enum value | llvm::R600InstrInfo | |
| ALU_VEC_210 enum value | llvm::R600InstrInfo | |
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::R600InstrInfo | |
| BankSwizzle enum name | llvm::R600InstrInfo | |
| buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const | llvm::R600InstrInfo | |
| buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const | llvm::R600InstrInfo | |
| buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const | llvm::R600InstrInfo | |
| buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const | llvm::R600InstrInfo | |
| buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const | llvm::R600InstrInfo | |
| buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const | llvm::R600InstrInfo | |
| calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const | llvm::R600InstrInfo | |
| canBeConsideredALU(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const | llvm::R600InstrInfo | |
| ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override | llvm::R600InstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override | llvm::R600InstrInfo | |
| CreateTargetScheduleState(const TargetSubtargetInfo &) const override | llvm::R600InstrInfo | |
| definesAddressRegister(MachineInstr &MI) const | llvm::R600InstrInfo | |
| expandPostRAPseudo(MachineInstr &MI) const override | llvm::R600InstrInfo | |
| FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const | llvm::R600InstrInfo | |
| fitsConstReadLimitations(const std::vector< MachineInstr * > &) const | llvm::R600InstrInfo | |
| fitsConstReadLimitations(const std::vector< unsigned > &) const | llvm::R600InstrInfo | |
| fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const | llvm::R600InstrInfo | |
| getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const | llvm::R600InstrInfo | |
| getIndirectAddrRegClass() const | llvm::R600InstrInfo | |
| getIndirectIndexBegin(const MachineFunction &MF) const | llvm::R600InstrInfo | |
| getIndirectIndexEnd(const MachineFunction &MF) const | llvm::R600InstrInfo | |
| getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override | llvm::R600InstrInfo | |
| getMaxAlusPerClause() const | llvm::R600InstrInfo | |
| getOperandIdx(const MachineInstr &MI, unsigned Op) const | llvm::R600InstrInfo | |
| getOperandIdx(unsigned Opcode, unsigned Op) const | llvm::R600InstrInfo | |
| getPredicationCost(const MachineInstr &) const override | llvm::R600InstrInfo | |
| getRegisterInfo() const | llvm::R600InstrInfo | inline |
| getSelIdx(unsigned Opcode, unsigned SrcIdx) const | llvm::R600InstrInfo | |
| getSrcs(MachineInstr &MI) const | llvm::R600InstrInfo | |
| hasInstrModifiers(unsigned Opcode) const | llvm::R600InstrInfo | |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::R600InstrInfo | |
| isALUInstr(unsigned Opcode) const | llvm::R600InstrInfo | |
| isCubeOp(unsigned opcode) const | llvm::R600InstrInfo | |
| isExport(unsigned Opcode) const | llvm::R600InstrInfo | |
| isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const | llvm::R600InstrInfo | |
| isLDSInstr(unsigned Opcode) const | llvm::R600InstrInfo | |
| isLDSRetInstr(unsigned Opcode) const | llvm::R600InstrInfo | |
| isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override | llvm::R600InstrInfo | |
| isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const | llvm::R600InstrInfo | |
| isMov(unsigned Opcode) const | llvm::R600InstrInfo | |
| isPredicable(const MachineInstr &MI) const override | llvm::R600InstrInfo | |
| isPredicated(const MachineInstr &MI) const override | llvm::R600InstrInfo | |
| isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override | llvm::R600InstrInfo | |
| isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override | llvm::R600InstrInfo | |
| isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override | llvm::R600InstrInfo | |
| isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override | llvm::R600InstrInfo | |
| isReductionOp(unsigned opcode) const | llvm::R600InstrInfo | |
| isRegisterLoad(const MachineInstr &MI) const | llvm::R600InstrInfo | inline |
| isRegisterStore(const MachineInstr &MI) const | llvm::R600InstrInfo | inline |
| isTransOnly(unsigned Opcode) const | llvm::R600InstrInfo | |
| isTransOnly(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| isVector(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| isVectorOnly(unsigned Opcode) const | llvm::R600InstrInfo | |
| isVectorOnly(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| mustBeLastInClause(unsigned Opcode) const | llvm::R600InstrInfo | |
| PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override | llvm::R600InstrInfo | |
| R600InstrInfo(const R600Subtarget &) | llvm::R600InstrInfo | explicit |
| readsLDSSrcReg(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::R600InstrInfo | |
| reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const | llvm::R600InstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::R600InstrInfo | |
| setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const | llvm::R600InstrInfo | |
| usesAddressRegister(MachineInstr &MI) const | llvm::R600InstrInfo | |
| usesTextureCache(unsigned Opcode) const | llvm::R600InstrInfo | |
| usesTextureCache(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| usesVertexCache(unsigned Opcode) const | llvm::R600InstrInfo | |
| usesVertexCache(const MachineInstr &MI) const | llvm::R600InstrInfo |
1.9.6