LLVM 20.0.0git
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This is the complete list of members for llvm::R600TargetLowering, including all inherited members.
ABS enum value | llvm::TargetLoweringBase | |
AddAnd enum value | llvm::TargetLoweringBase | |
addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) | llvm::TargetLoweringBase | inlineprotected |
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
addRegisterClass(MVT VT, const TargetRegisterClass *RC) | llvm::TargetLoweringBase | inlineprotected |
addressingModeSupportsTLS(const GlobalValue &) const | llvm::TargetLoweringBase | inlinevirtual |
addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const | llvm::AMDGPUTargetLowering | |
AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const | llvm::TargetLowering | virtual |
aggressivelyPreferBuildVectorSources(EVT VecVT) const override | llvm::AMDGPUTargetLowering | virtual |
alignLoopsWithOptSize() const | llvm::TargetLoweringBase | inlinevirtual |
allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags) | llvm::AMDGPUTargetLowering | protectedstatic |
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | virtual |
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const | llvm::TargetLoweringBase | |
allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const override | llvm::R600TargetLowering | virtual |
llvm::AMDGPUTargetLowering::allowsMisalignedMemoryAccesses(LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const | llvm::TargetLoweringBase | inlinevirtual |
allowTruncateForTailCall(Type *FromTy, Type *ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4) | llvm::AMDGPUTargetLowering | static |
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI) | llvm::AMDGPUTargetLowering | |
analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const | llvm::AMDGPUTargetLowering | protected |
AndOrSETCCFoldKind enum name | llvm::TargetLoweringBase | |
areJTsAllowed(const Function *Fn) const | llvm::TargetLoweringBase | inlinevirtual |
areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const | llvm::TargetLoweringBase | inlinevirtual |
ArgListTy typedef | llvm::TargetLoweringBase | |
AsmOperandInfoVector typedef | llvm::TargetLowering | |
AtomicExpansionKind enum name | llvm::TargetLoweringBase | |
BooleanContent enum name | llvm::TargetLoweringBase | |
buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) const | llvm::TargetLowering | |
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | |
BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | virtual |
buildSDIVPow2WithCMov(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | |
BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | virtual |
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) const | llvm::TargetLowering | |
C_Address enum value | llvm::TargetLowering | |
C_Immediate enum value | llvm::TargetLowering | |
C_Memory enum value | llvm::TargetLowering | |
C_Other enum value | llvm::TargetLowering | |
C_Register enum value | llvm::TargetLowering | |
C_RegisterClass enum value | llvm::TargetLowering | |
C_Unknown enum value | llvm::TargetLowering | |
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const | llvm::TargetLoweringBase | inlinevirtual |
canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOperations) const override | llvm::R600TargetLowering | inlinevirtual |
canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const | llvm::TargetLowering | virtual |
CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const | llvm::TargetLowering | inlinevirtual |
canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override | llvm::R600TargetLowering | virtual |
canOpTrap(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | virtual |
CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const | llvm::R600TargetLowering | |
llvm::AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) | llvm::AMDGPUTargetLowering | static |
CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg) | llvm::AMDGPUTargetLowering | static |
checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const | llvm::TargetLowering | inlinevirtual |
CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | |
combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | |
combineRepeatedFPDivisors() const | llvm::TargetLowering | inlinevirtual |
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const | llvm::TargetLowering | virtual |
computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const | llvm::TargetLowering | virtual |
computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const | llvm::TargetLowering | virtual |
computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const | llvm::TargetLowering | virtual |
computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override | llvm::AMDGPUTargetLowering | virtual |
computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override | llvm::AMDGPUTargetLowering | virtual |
ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override | llvm::AMDGPUTargetLowering | virtual |
computeRegisterProperties(const TargetRegisterInfo *TRI) | llvm::TargetLoweringBase | protected |
ConstraintGroup typedef | llvm::TargetLowering | |
ConstraintPair typedef | llvm::TargetLowering | |
ConstraintType enum name | llvm::TargetLowering | |
ConstraintWeight enum name | llvm::TargetLowering | |
convertSelectOfConstantsToMath(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
convertSetCCLogicToBitwiseLogic(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) const | llvm::TargetLoweringBase | inlinevirtual |
createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const | llvm::TargetLowering | inlinevirtual |
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const | llvm::AMDGPUTargetLowering | |
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const | llvm::AMDGPUTargetLowering | inline |
CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const | llvm::AMDGPUTargetLowering | inline |
createSelectForFMINNUM_FMAXNUM(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned NumBitsPerElt) const | llvm::TargetLowering | |
Custom enum value | llvm::TargetLoweringBase | |
CW_Best enum value | llvm::TargetLowering | |
CW_Better enum value | llvm::TargetLowering | |
CW_Constant enum value | llvm::TargetLowering | |
CW_Default enum value | llvm::TargetLowering | |
CW_Good enum value | llvm::TargetLowering | |
CW_Invalid enum value | llvm::TargetLowering | |
CW_Memory enum value | llvm::TargetLowering | |
CW_Okay enum value | llvm::TargetLowering | |
CW_Register enum value | llvm::TargetLowering | |
CW_SpecificReg enum value | llvm::TargetLowering | |
decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const | llvm::TargetLoweringBase | inlinevirtual |
Disabled enum value | llvm::TargetLoweringBase | |
emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const | llvm::TargetLoweringBase | inlinevirtual |
emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const | llvm::TargetLoweringBase | inlinevirtual |
emitExpandAtomicRMW(AtomicRMWInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override | llvm::R600TargetLowering | virtual |
EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const | llvm::TargetLoweringBase | inlinevirtual |
emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const | llvm::TargetLoweringBase | virtual |
emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | protected |
emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const | llvm::TargetLowering | inlinevirtual |
emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const | llvm::TargetLoweringBase | inlinevirtual |
emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const | llvm::TargetLoweringBase | virtual |
enableAggressiveFMAFusion(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
enableAggressiveFMAFusion(LLT Ty) const | llvm::TargetLoweringBase | inlinevirtual |
Enabled enum value | llvm::TargetLoweringBase | |
enableExtLdPromotion() const | llvm::TargetLoweringBase | inline |
EnableExtLdPromotion | llvm::TargetLoweringBase | protected |
Expand enum value | llvm::TargetLoweringBase | |
expandABD(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative=false) const | llvm::TargetLowering | |
expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandAVG(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandBSWAP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandCMP(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandCTLZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandCTPOP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandCTTZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandDIVREMByConstant(SDNode *N, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue()) const | llvm::TargetLowering | |
expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandFunnelShift(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
ExpandInlineAsm(CallInst *) const | llvm::TargetLowering | inlinevirtual |
expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const | llvm::TargetLowering | |
expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const | llvm::TargetLowering | |
expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandRoundInexactToOdd(EVT ResultVT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandShlSat(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVecReduce(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVECTOR_COMPRESS(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVectorNaryOpBySplitting(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVectorSplice(SDNode *Node, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
expandVPCTTZElements(SDNode *N, SelectionDAG &DAG) const | llvm::TargetLowering | |
fallBackToDAGISel(const Instruction &Inst) const | llvm::TargetLoweringBase | inlinevirtual |
finalizeLowering(MachineFunction &MF) const | llvm::TargetLoweringBase | virtual |
findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const | llvm::TargetLowering | virtual |
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const | llvm::TargetLoweringBase | protectedvirtual |
FIRST_IMPLICIT enum value | llvm::AMDGPUTargetLowering | |
foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI, SDValue N) const | llvm::AMDGPUTargetLowering | protected |
forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, EVT WideVT, const SDValue LL, const SDValue LH, const SDValue RL, const SDValue RH, SDValue &Lo, SDValue &Hi) const | llvm::TargetLowering | |
forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, const SDValue LHS, const SDValue RHS, SDValue &Lo, SDValue &Hi) const | llvm::TargetLowering | |
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const | llvm::TargetLowering | inlinevirtual |
GatherAllAliasesMaxDepth | llvm::TargetLoweringBase | protected |
generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) const | llvm::TargetLoweringBase | inlinevirtual |
getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const | llvm::TargetLoweringBase | inlinevirtual |
getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inlinevirtual |
getAtomicLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const | llvm::TargetLoweringBase | |
getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const | llvm::TargetLoweringBase | |
getBooleanContents(bool isVec, bool isFloat) const | llvm::TargetLoweringBase | inline |
getBooleanContents(EVT Type) const | llvm::TargetLoweringBase | inline |
getBypassSlowDivWidths() const | llvm::TargetLoweringBase | inline |
getByValTypeAlignment(Type *Ty, const DataLayout &DL) const | llvm::TargetLoweringBase | virtual |
getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const | llvm::TargetLowering | inline |
getCheaperOrNeutralNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) const | llvm::TargetLowering | inline |
getCmpLibcallCC(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
getCmpLibcallReturnType() const | llvm::TargetLoweringBase | virtual |
getCondCodeAction(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
getConstantNegateCost(const ConstantFPSDNode *C) const | llvm::AMDGPUTargetLowering | protected |
getConstraintPreferences(AsmOperandInfo &OpInfo) const | llvm::TargetLowering | |
getConstraintType(StringRef Constraint) const | llvm::TargetLowering | virtual |
getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const | llvm::TargetLoweringBase | inlinevirtual |
getCustomOperationAction(SDNode &Op) const | llvm::TargetLoweringBase | inlinevirtual |
getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const | llvm::TargetLoweringBase | protected |
getDivRefinementSteps(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
getEquivalentMemType(LLVMContext &Context, EVT VT) | llvm::AMDGPUTargetLowering | protectedstatic |
getExceptionPointerRegister(const Constant *PersonalityFn) const | llvm::TargetLoweringBase | inlinevirtual |
getExceptionSelectorRegister(const Constant *PersonalityFn) const | llvm::TargetLoweringBase | inlinevirtual |
getExtendForAtomicCmpSwapArg() const | llvm::TargetLoweringBase | inlinevirtual |
getExtendForAtomicOps() const | llvm::TargetLoweringBase | inlinevirtual |
getExtendForContent(BooleanContent Content) | llvm::TargetLoweringBase | inlinestatic |
getFenceOperandTy(const DataLayout &DL) const override | llvm::AMDGPUTargetLowering | inlinevirtual |
getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const | llvm::TargetLoweringBase | inline |
getFrameIndexTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
getGatherAllAliasesMaxDepth() const | llvm::TargetLoweringBase | inline |
getHiHalf64(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const | llvm::AMDGPUTargetLowering | |
getImplicitParameterOffset(const uint64_t ExplicitKernArgSize, const ImplicitParameter Param) const | llvm::AMDGPUTargetLowering | |
getIndexedLoadAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
getIndexedStoreAction(unsigned IdxMode, MVT VT) const | llvm::TargetLoweringBase | inline |
getInlineAsmMemConstraint(StringRef ConstraintCode) const | llvm::TargetLowering | inlinevirtual |
getIRStackGuard(IRBuilderBase &IRB) const | llvm::TargetLoweringBase | virtual |
getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const | llvm::AMDGPUTargetLowering | protected |
getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const | llvm::AMDGPUTargetLowering | protected |
getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) const | llvm::TargetLoweringBase | inlinevirtual |
getJumpTableEncoding() const | llvm::TargetLowering | virtual |
getJumpTableRegTy(const DataLayout &DL) const | llvm::TargetLowering | inlinevirtual |
getLibcallCallingConv(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
getLibcallName(RTLIB::Libcall Call) const | llvm::TargetLoweringBase | inline |
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const | llvm::TargetLoweringBase | |
getLoHalf64(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
getMaxAtomicSizeInBitsSupported() const | llvm::TargetLoweringBase | inline |
getMaxDivRemBitWidthSupported() const | llvm::TargetLoweringBase | inline |
getMaxExpandSizeMemcmp(bool OptSize) const | llvm::TargetLoweringBase | inline |
getMaxGluedStoresPerMemcpy() const | llvm::TargetLoweringBase | inlinevirtual |
getMaximumJumpTableSize() const | llvm::TargetLoweringBase | |
getMaxLargeFPConvertBitWidthSupported() const | llvm::TargetLoweringBase | inline |
getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const | llvm::TargetLoweringBase | virtual |
getMaxStoresPerMemcpy(bool OptSize) const | llvm::TargetLoweringBase | inline |
getMaxStoresPerMemmove(bool OptSize) const | llvm::TargetLoweringBase | inline |
getMaxStoresPerMemset(bool OptSize) const | llvm::TargetLoweringBase | inline |
getMaxSupportedInterleaveFactor() const | llvm::TargetLoweringBase | inlinevirtual |
getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
getMinCmpXchgSizeInBits() const | llvm::TargetLoweringBase | inline |
getMinFunctionAlignment() const | llvm::TargetLoweringBase | inline |
getMinimumJumpTableDensity(bool OptForSize) const | llvm::TargetLoweringBase | |
getMinimumJumpTableEntries() const | llvm::TargetLoweringBase | virtual |
getMinStackArgumentAlignment() const | llvm::TargetLoweringBase | inline |
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const | llvm::TargetLowering | virtual |
getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override | llvm::AMDGPUTargetLowering | virtual |
llvm::TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const | llvm::TargetLowering | inline |
getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const | llvm::TargetLoweringBase | inlinevirtual |
getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
getOperationAction(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
getOptimalMemOpLLT(const MemOp &Op, const AttributeList &) const | llvm::TargetLoweringBase | inlinevirtual |
getOptimalMemOpType(const MemOp &Op, const AttributeList &) const | llvm::TargetLoweringBase | inlinevirtual |
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const | llvm::TargetLowering | virtual |
getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const | llvm::TargetLoweringBase | inlinevirtual |
getPointerTy(const DataLayout &DL, uint32_t AS=0) const | llvm::TargetLoweringBase | inlinevirtual |
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const | llvm::TargetLowering | inlinevirtual |
getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) const | llvm::TargetLoweringBase | inlinevirtual |
getPreferredShiftAmountTy(LLT ShiftValueTy) const | llvm::TargetLoweringBase | inlinevirtual |
getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const | llvm::TargetLoweringBase | virtual |
getPreferredVectorAction(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
getPrefFunctionAlignment() const | llvm::TargetLoweringBase | inline |
getPrefLoopAlignment(MachineLoop *ML=nullptr) const | llvm::TargetLoweringBase | virtual |
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const | llvm::TargetLowering | inlinevirtual |
getProgramPointerTy(const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override | llvm::AMDGPUTargetLowering | virtual |
getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
getRegClassFor(MVT VT, bool isDivergent=false) const | llvm::TargetLoweringBase | inlinevirtual |
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const | llvm::TargetLowering | virtual |
getRegisterByName(const char *RegName, LLT Ty, const MachineFunction &MF) const | llvm::TargetLowering | inlinevirtual |
getRegisterType(MVT VT) const | llvm::TargetLoweringBase | inline |
getRegisterType(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
getRepRegClassCostFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
getRepRegClassFor(MVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
getRoundingControlRegisters() const | llvm::TargetLowering | inlinevirtual |
getSafeStackPointerLocation(IRBuilderBase &IRB) const | llvm::TargetLoweringBase | virtual |
getScalarShiftAmountTy(const DataLayout &, EVT) const | llvm::TargetLoweringBase | virtual |
getScaledLogInput(SelectionDAG &DAG, const SDLoc SL, SDValue Op, SDNodeFlags Flags) const | llvm::AMDGPUTargetLowering | protected |
getSchedulingPreference() const | llvm::TargetLoweringBase | inline |
getSchedulingPreference(SDNode *) const | llvm::TargetLoweringBase | inlinevirtual |
getScratchRegisters(CallingConv::ID CC) const | llvm::TargetLowering | inlinevirtual |
getSDagStackGuard(const Module &M) const | llvm::TargetLoweringBase | virtual |
getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override | llvm::R600TargetLowering | virtual |
getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const | llvm::TargetLoweringBase | |
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const | llvm::TargetLowering | virtual |
getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override | llvm::AMDGPUTargetLowering | virtual |
getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, const DenormalMode &Mode) const | llvm::TargetLowering | virtual |
getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const | llvm::TargetLoweringBase | |
getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
getSSPStackGuardCheck(const Module &M) const | llvm::TargetLoweringBase | virtual |
getStackPointerRegisterToSaveRestore() const | llvm::TargetLoweringBase | inline |
getStackProbeSymbolName(const MachineFunction &MF) const | llvm::TargetLoweringBase | inlinevirtual |
getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const | llvm::TargetLoweringBase | |
getStrictFPOperationAction(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
getSubtarget() const | llvm::R600TargetLowering | |
getTargetConstantFromLoad(LoadSDNode *LD) const | llvm::TargetLowering | virtual |
getTargetMachine() const | llvm::TargetLoweringBase | inline |
getTargetMMOFlags(const Instruction &I) const | llvm::TargetLoweringBase | inlinevirtual |
getTargetMMOFlags(const MemSDNode &Node) const | llvm::TargetLoweringBase | inlinevirtual |
getTargetNodeName(unsigned Opcode) const override | llvm::AMDGPUTargetLowering | virtual |
getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const | llvm::TargetLoweringBase | inlinevirtual |
getTruncStoreAction(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
getTypeAction(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
getTypeAction(MVT VT) const | llvm::TargetLoweringBase | inline |
getTypeConversion(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | |
getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override | llvm::AMDGPUTargetLowering | virtual |
getTypeToExpandTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inline |
getTypeToPromoteTo(unsigned Op, MVT VT) const | llvm::TargetLoweringBase | inline |
getTypeToTransformTo(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
getVaListSizeInBits(const DataLayout &DL) const | llvm::TargetLoweringBase | inlinevirtual |
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const | llvm::TargetLoweringBase | inline |
getValueTypeActions() const | llvm::TargetLoweringBase | inline |
getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const | llvm::TargetLowering | |
getVectorIdxTy(const DataLayout &) const override | llvm::AMDGPUTargetLowering | virtual |
getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) const | llvm::TargetLowering | |
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const | llvm::TargetLoweringBase | |
getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const | llvm::TargetLoweringBase | inlinevirtual |
getVPExplicitVectorLengthTy() const | llvm::TargetLoweringBase | inlinevirtual |
HandleByVal(CCState *, unsigned &, Align) const | llvm::TargetLowering | inlinevirtual |
hasAndNot(SDValue X) const | llvm::TargetLoweringBase | inlinevirtual |
hasAndNotCompare(SDValue Y) const | llvm::TargetLoweringBase | inlinevirtual |
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
hasBitTest(SDValue X, SDValue Y) const | llvm::TargetLoweringBase | inlinevirtual |
hasExtractBitsInsn() const | llvm::TargetLoweringBase | inline |
hasFastEqualityCompare(unsigned NumBits) const | llvm::TargetLoweringBase | inlinevirtual |
hasInlineStackProbe(const MachineFunction &MF) const | llvm::TargetLoweringBase | inlinevirtual |
hasMultipleConditionRegisters() const | llvm::TargetLoweringBase | inline |
hasPairedLoad(EVT, Align &) const | llvm::TargetLoweringBase | inlinevirtual |
hasStackProbeSymbol(const MachineFunction &MF) const | llvm::TargetLoweringBase | inlinevirtual |
hasStandaloneRem(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
hasTargetDAGCombine(ISD::NodeType NT) const | llvm::TargetLoweringBase | inline |
hasVectorBlend() const | llvm::TargetLoweringBase | inlinevirtual |
ImplicitParameter enum name | llvm::AMDGPUTargetLowering | |
IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const | llvm::TargetLowering | |
initActions() | llvm::TargetLoweringBase | protected |
initializeSplitCSR(MachineBasicBlock *Entry) const | llvm::TargetLowering | inlinevirtual |
insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const | llvm::TargetLowering | inlinevirtual |
insertSSPDeclarations(Module &M) const | llvm::TargetLoweringBase | virtual |
InstructionOpcodeToISD(unsigned Opcode) const | llvm::TargetLoweringBase | |
isAtomicLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) const | llvm::TargetLoweringBase | inline |
isBinOp(unsigned Opcode) const | llvm::TargetLoweringBase | inlinevirtual |
isCheapToSpeculateCtlz(Type *Ty) const override | llvm::AMDGPUTargetLowering | virtual |
isCheapToSpeculateCttz(Type *Ty) const override | llvm::AMDGPUTargetLowering | virtual |
isCommutativeBinOp(unsigned Opcode) const | llvm::TargetLoweringBase | inlinevirtual |
isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) const | llvm::TargetLoweringBase | inlinevirtual |
isComplexDeinterleavingSupported() const | llvm::TargetLoweringBase | inlinevirtual |
isCondCodeLegal(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const | llvm::TargetLoweringBase | inline |
isConstantCheaperToNegate(SDValue N) const | llvm::AMDGPUTargetLowering | protected |
isConstantCostlierToNegate(SDValue N) const | llvm::AMDGPUTargetLowering | protected |
isConstFalseVal(SDValue N) const | llvm::TargetLowering | |
isConstTrueVal(SDValue N) const | llvm::TargetLowering | |
isCtlzFast() const | llvm::TargetLoweringBase | inlinevirtual |
isCtpopFast(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) const | llvm::TargetLowering | inlinevirtual |
isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override | llvm::AMDGPUTargetLowering | virtual |
llvm::TargetLowering::isDesirableToCommuteWithShift(const MachineInstr &MI, bool IsAfterLegal) const | llvm::TargetLowering | inlinevirtual |
isDesirableToCommuteXorWithShift(const SDNode *N) const | llvm::TargetLowering | inlinevirtual |
IsDesirableToPromoteOp(SDValue, EVT &) const | llvm::TargetLowering | inlinevirtual |
isDesirableToPullExtFromShl(const MachineInstr &MI) const | llvm::TargetLowering | inlinevirtual |
isDesirableToTransformToIntegerOp(unsigned, EVT) const | llvm::TargetLowering | inlinevirtual |
isEqualityCmpFoldedWithSignedCmp() const | llvm::TargetLoweringBase | inlinevirtual |
isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const | llvm::TargetLowering | |
isExtFree(const Instruction *I) const | llvm::TargetLoweringBase | inline |
isExtFreeImpl(const Instruction *I) const | llvm::TargetLoweringBase | inlineprotectedvirtual |
isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const | llvm::TargetLoweringBase | inlinevirtual |
isExtractVecEltCheap(EVT VT, unsigned Index) const | llvm::TargetLoweringBase | inlinevirtual |
isFAbsFree(EVT VT) const override | llvm::AMDGPUTargetLowering | virtual |
isFMADLegal(const MachineInstr &MI, LLT Ty) const | llvm::TargetLoweringBase | inlinevirtual |
isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const | llvm::TargetLoweringBase | inlinevirtual |
isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, LLT) const | llvm::TargetLoweringBase | inlinevirtual |
isFMAFasterThanFMulAndFAdd(const Function &F, Type *) const | llvm::TargetLoweringBase | inlinevirtual |
isFNegFree(EVT VT) const override | llvm::AMDGPUTargetLowering | virtual |
isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const | llvm::TargetLoweringBase | inlinevirtual |
isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const | llvm::TargetLoweringBase | inlinevirtual |
isFPExtFree(EVT DestVT, EVT SrcVT) const | llvm::TargetLoweringBase | inlinevirtual |
isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override | llvm::AMDGPUTargetLowering | virtual |
isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const | llvm::TargetLoweringBase | virtual |
isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override | llvm::AMDGPUTargetLowering | inlinevirtual |
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const | llvm::TargetLowering | virtual |
isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const | llvm::TargetLowering | virtual |
isIndexedLoadLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
isIndexedStoreLegal(unsigned IdxMode, EVT VT) const | llvm::TargetLoweringBase | inline |
isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) const | llvm::TargetLowering | inlinevirtual |
isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const | llvm::TargetLowering | inlinevirtual |
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const | llvm::TargetLowering | |
isIntDivCheap(EVT VT, AttributeList Attr) const | llvm::TargetLoweringBase | inlinevirtual |
isJumpExpensive() const | llvm::TargetLoweringBase | inline |
isJumpTableRelative() const | llvm::TargetLoweringBase | virtual |
isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override | llvm::AMDGPUTargetLowering | virtual |
isLegalAddImmediate(int64_t) const | llvm::TargetLoweringBase | inlinevirtual |
isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const | llvm::TargetLoweringBase | virtual |
isLegalAddScalableImmediate(int64_t) const | llvm::TargetLoweringBase | inlinevirtual |
isLegalICmpImmediate(int64_t) const | llvm::TargetLoweringBase | inlinevirtual |
isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const | llvm::TargetLoweringBase | protected |
isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const | llvm::TargetLoweringBase | inlinevirtual |
isLegalStoreImmediate(int64_t Value) const | llvm::TargetLoweringBase | inlinevirtual |
isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const final | llvm::AMDGPUTargetLowering | virtual |
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const | llvm::TargetLoweringBase | inlinevirtual |
isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const | llvm::TargetLoweringBase | inlinevirtual |
isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const | llvm::TargetLoweringBase | inlinevirtual |
isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override | llvm::AMDGPUTargetLowering | virtual |
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const | llvm::TargetLowering | virtual |
isOperationCustom(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
isOperationExpand(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
isOperationLegal(unsigned Op, EVT VT) const | llvm::TargetLoweringBase | inline |
isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const | llvm::TargetLoweringBase | inline |
isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const | llvm::TargetLoweringBase | inline |
isOperationLegalOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const | llvm::TargetLoweringBase | inline |
isPaddedAtMostSignificantBitsWhenStored(EVT VT) const | llvm::TargetLoweringBase | inline |
isPositionIndependent() const | llvm::TargetLowering | |
isPredictableSelectExpensive() const | llvm::TargetLoweringBase | inline |
isProfitableToCombineMinNumMaxNum(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
isProfitableToHoist(Instruction *I) const | llvm::TargetLoweringBase | inlinevirtual |
isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) const override | llvm::AMDGPUTargetLowering | virtual |
llvm::TargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const | llvm::TargetLowering | inlinevirtual |
isSafeMemOpType(MVT) const | llvm::TargetLoweringBase | inlinevirtual |
isSDNodeAlwaysUniform(const SDNode *N) const override | llvm::AMDGPUTargetLowering | virtual |
isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const | llvm::TargetLowering | inlinevirtual |
isSelectSupported(SelectSupportKind) const override | llvm::AMDGPUTargetLowering | virtual |
isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const | llvm::TargetLoweringBase | inlinevirtual |
isShuffleMaskLegal(ArrayRef< int >, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
isSlowDivBypassed() const | llvm::TargetLoweringBase | inline |
isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | virtual |
isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const | llvm::TargetLoweringBase | inlinevirtual |
IsStrictFPEnabled | llvm::TargetLoweringBase | protected |
isStrictFPEnabled() const | llvm::TargetLoweringBase | inline |
isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const | llvm::TargetLoweringBase | virtual |
isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const | llvm::TargetLoweringBase | inlinevirtual |
isTargetCanonicalConstantNode(SDValue Op) const | llvm::TargetLowering | inlinevirtual |
isTruncateFree(EVT Src, EVT Dest) const override | llvm::AMDGPUTargetLowering | virtual |
isTruncateFree(Type *Src, Type *Dest) const override | llvm::AMDGPUTargetLowering | virtual |
llvm::TargetLowering::isTruncateFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const | llvm::TargetLoweringBase | inlinevirtual |
llvm::TargetLowering::isTruncateFree(SDValue Val, EVT VT2) const | llvm::TargetLoweringBase | inlinevirtual |
isTruncStoreLegal(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const | llvm::TargetLoweringBase | inline |
isTypeDesirableForOp(unsigned, EVT VT) const | llvm::TargetLowering | inlinevirtual |
isTypeLegal(EVT VT) const | llvm::TargetLoweringBase | inline |
isUsedByReturnOnly(SDNode *, SDValue &) const | llvm::TargetLowering | inlinevirtual |
isVectorClearMaskLegal(ArrayRef< int >, EVT) const | llvm::TargetLoweringBase | inlinevirtual |
isVectorLoadExtDesirable(SDValue ExtVal) const | llvm::TargetLoweringBase | inlinevirtual |
isVScaleKnownToBeAPowerOfTwo() const | llvm::TargetLoweringBase | inlinevirtual |
isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode, EVT) const | llvm::TargetLowering | inlinevirtual |
isZExtFree(Type *Src, Type *Dest) const override | llvm::AMDGPUTargetLowering | virtual |
isZExtFree(EVT Src, EVT Dest) const override | llvm::AMDGPUTargetLowering | virtual |
llvm::TargetLowering::isZExtFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) const | llvm::TargetLoweringBase | inlinevirtual |
llvm::TargetLowering::isZExtFree(SDValue Val, EVT VT2) const | llvm::TargetLoweringBase | inlinevirtual |
joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const | llvm::TargetLowering | inlinevirtual |
Legal enum value | llvm::TargetLoweringBase | |
LegalizeAction enum name | llvm::TargetLoweringBase | |
LegalizeKind typedef | llvm::TargetLoweringBase | |
LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) const | llvm::TargetLowering | |
LegalizeTypeAction enum name | llvm::TargetLoweringBase | |
LibCall enum value | llvm::TargetLoweringBase | |
loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const | llvm::AMDGPUTargetLowering | |
loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const | llvm::AMDGPUTargetLowering | |
LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override | llvm::AMDGPUTargetLowering | virtual |
LowerCallTo(CallLoweringInfo &CLI) const | llvm::TargetLowering | |
lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const | llvm::TargetLowering | |
LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const | llvm::TargetLowering | inlinevirtual |
lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl< Instruction * > &DeadInsts) const | llvm::TargetLoweringBase | inlinevirtual |
LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const | llvm::AMDGPUTargetLowering | protected |
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | |
LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFCEIL(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
lowerFEXP(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) const | llvm::AMDGPUTargetLowering | protected |
lowerFEXP2(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) const | llvm::AMDGPUTargetLowering | protected |
LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFLOG10(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFLOG2(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, bool IsLog10, SDNodeFlags Flags) const | llvm::AMDGPUTargetLowering | protected |
LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override | llvm::R600TargetLowering | virtual |
LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const | llvm::AMDGPUTargetLowering | protected |
LowerFREM(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFRINT(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFROUND(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const | llvm::TargetLoweringBase | inlinevirtual |
LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const | llvm::AMDGPUTargetLowering | protected |
LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const | llvm::AMDGPUTargetLowering | protected |
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const | llvm::TargetLoweringBase | inlinevirtual |
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const | llvm::TargetLoweringBase | inlinevirtual |
lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI, SmallVectorImpl< Instruction * > &DeadInsts) const | llvm::TargetLoweringBase | inlinevirtual |
LowerOperation(SDValue Op, SelectionDAG &DAG) const override | llvm::R600TargetLowering | virtual |
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override | llvm::AMDGPUTargetLowering | virtual |
LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const | llvm::TargetLowering | virtual |
LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const | llvm::AMDGPUTargetLowering | protected |
LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const | llvm::AMDGPUTargetLowering | |
LowerXConstraint(EVT ConstraintVT) const | llvm::TargetLowering | virtual |
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const | llvm::TargetLowering | |
markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const | llvm::TargetLoweringBase | inlinevirtual |
MaxGluedStoresPerMemcpy | llvm::TargetLoweringBase | protected |
MaxLoadsPerMemcmp | llvm::TargetLoweringBase | protected |
MaxLoadsPerMemcmpOptSize | llvm::TargetLoweringBase | protected |
MaxStoresPerMemcpy | llvm::TargetLoweringBase | protected |
MaxStoresPerMemcpyOptSize | llvm::TargetLoweringBase | protected |
MaxStoresPerMemmove | llvm::TargetLoweringBase | protected |
MaxStoresPerMemmoveOptSize | llvm::TargetLoweringBase | protected |
MaxStoresPerMemset | llvm::TargetLoweringBase | protected |
MaxStoresPerMemsetOptSize | llvm::TargetLoweringBase | protected |
mayBeEmittedAsTailCall(const CallInst *) const | llvm::TargetLowering | inlinevirtual |
mayIgnoreSignedZero(SDValue Op) const | llvm::AMDGPUTargetLowering | |
mergeStoresAfterLegalization(EVT) const override | llvm::AMDGPUTargetLowering | inlinevirtual |
MulExpansionKind enum name | llvm::TargetLoweringBase | |
needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src, SDNodeFlags Flags) | llvm::AMDGPUTargetLowering | protectedstatic |
needsFixedCatchObjects() const | llvm::TargetLoweringBase | inlinevirtual |
NegatibleCost enum name | llvm::TargetLoweringBase | |
None enum value | llvm::TargetLoweringBase | |
NotAnd enum value | llvm::TargetLoweringBase | |
numBitsSigned(SDValue Op, SelectionDAG &DAG) | llvm::AMDGPUTargetLowering | static |
numBitsUnsigned(SDValue Op, SelectionDAG &DAG) | llvm::AMDGPUTargetLowering | static |
operator=(const TargetLowering &)=delete | llvm::TargetLowering | |
llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=delete | llvm::TargetLoweringBase | |
optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) const | llvm::TargetLoweringBase | inlinevirtual |
optimizeFMulOrFDivAsShiftAddBitcast(SDNode *N, SDValue FPConst, SDValue IntPow2) const | llvm::TargetLoweringBase | inlinevirtual |
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const | llvm::TargetLowering | |
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const | llvm::TargetLowering | virtual |
performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override | llvm::R600TargetLowering | virtual |
performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const | llvm::AMDGPUTargetLowering | protected |
PredictableSelectIsExpensive | llvm::TargetLoweringBase | protected |
preferABDSToABSWithNSW(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const | llvm::TargetLoweringBase | inlinevirtual |
preferIncOfAddToSubOfNot(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const | llvm::TargetLoweringBase | inlinevirtual |
preferScalarizeSplat(SDNode *N) const | llvm::TargetLoweringBase | inlinevirtual |
preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const | llvm::TargetLoweringBase | inlinevirtual |
preferZeroCompareBranch() const | llvm::TargetLoweringBase | inlinevirtual |
prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const | llvm::TargetLowering | inlinevirtual |
PRIVATE_BASE enum value | llvm::AMDGPUTargetLowering | |
Promote enum value | llvm::TargetLoweringBase | |
promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool, EVT ValVT) const | llvm::TargetLoweringBase | inline |
QUEUE_PTR enum value | llvm::AMDGPUTargetLowering | |
R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI) | llvm::R600TargetLowering | |
rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) const | llvm::TargetLoweringBase | inline |
ReciprocalEstimate enum name | llvm::TargetLoweringBase | |
reduceSelectOfFPConstantLoads(EVT CmpOpVT) const | llvm::TargetLoweringBase | inlinevirtual |
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override | llvm::R600TargetLowering | virtual |
requiresUniformRegister(MachineFunction &MF, const Value *) const | llvm::TargetLoweringBase | inlinevirtual |
ScalarCondVectorVal enum value | llvm::TargetLoweringBase | |
scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const | llvm::TargetLowering | |
scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const | llvm::TargetLowering | |
ScalarValSelect enum value | llvm::TargetLoweringBase | |
SelectSupportKind enum name | llvm::TargetLoweringBase | |
setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setBooleanContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) | llvm::TargetLoweringBase | inlineprotected |
setBooleanVectorContents(BooleanContent Ty) | llvm::TargetLoweringBase | inlineprotected |
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) | llvm::TargetLoweringBase | inline |
setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setCondCodeAction(ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setHasExtractBitsInsn(bool hasExtractInsn=true) | llvm::TargetLoweringBase | inlineprotected |
setHasMultipleConditionRegisters(bool hasManyRegs=true) | llvm::TargetLoweringBase | inlineprotected |
setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setIndexedLoadAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setIndexedStoreAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setJumpIsExpensive(bool isExpensive=true) | llvm::TargetLoweringBase | protected |
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) | llvm::TargetLoweringBase | inline |
setLibcallName(RTLIB::Libcall Call, const char *Name) | llvm::TargetLoweringBase | inline |
setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name) | llvm::TargetLoweringBase | inline |
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
setMaxBytesForAlignment(unsigned MaxBytes) | llvm::TargetLoweringBase | inlineprotected |
setMaxDivRemBitWidthSupported(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
setMaximumJumpTableSize(unsigned) | llvm::TargetLoweringBase | protected |
setMaxLargeFPConvertBitWidthSupported(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
setMinCmpXchgSizeInBits(unsigned SizeInBits) | llvm::TargetLoweringBase | inlineprotected |
setMinFunctionAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
setMinimumJumpTableEntries(unsigned Val) | llvm::TargetLoweringBase | protected |
setMinStackArgumentAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setOperationAction(ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
setOperationPromotedToType(ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT) | llvm::TargetLoweringBase | inlineprotected |
setPrefFunctionAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
setPrefLoopAlignment(Align Alignment) | llvm::TargetLoweringBase | inlineprotected |
setSchedulingPreference(Sched::Preference Pref) | llvm::TargetLoweringBase | inlineprotected |
setStackPointerRegisterToSaveRestore(Register R) | llvm::TargetLoweringBase | inlineprotected |
setSupportsUnalignedAtomics(bool UnalignedSupported) | llvm::TargetLoweringBase | inlineprotected |
setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs) | llvm::TargetLoweringBase | inlineprotected |
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action) | llvm::TargetLoweringBase | inlineprotected |
shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const | llvm::TargetLoweringBase | inlinevirtual |
SHARED_BASE enum value | llvm::AMDGPUTargetLowering | |
ShiftLegalizationStrategy enum name | llvm::TargetLoweringBase | |
shouldAlignPointerArgs(CallInst *, unsigned &, Align &) const | llvm::TargetLoweringBase | inlinevirtual |
shouldAvoidTransformToShift(EVT VT, unsigned Amount) const | llvm::TargetLoweringBase | inlinevirtual |
shouldCastAtomicLoadInIR(LoadInst *LI) const override | llvm::AMDGPUTargetLowering | inlinevirtual |
shouldCastAtomicRMWIInIR(AtomicRMWInst *) const override | llvm::AMDGPUTargetLowering | inlinevirtual |
shouldCastAtomicStoreInIR(StoreInst *SI) const override | llvm::AMDGPUTargetLowering | inlinevirtual |
shouldCombineMemoryType(EVT VT) const | llvm::AMDGPUTargetLowering | protected |
shouldConsiderGEPOffsetSplit() const | llvm::TargetLoweringBase | inlinevirtual |
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const | llvm::TargetLoweringBase | inlinevirtual |
shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldConvertPhiType(Type *From, Type *To) const | llvm::TargetLoweringBase | inlinevirtual |
shouldConvertSplatType(ShuffleVectorInst *SVI) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandAtomicLoadInIR(LoadInst *LI) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandAtomicStoreInIR(StoreInst *SI) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandCmpUsingSelects(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandCttzElements(EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandPartialReductionIntrinsic(const IntrinsicInst *I) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExtendGSIndex(EVT VT, EVT &EltTy) const | llvm::TargetLoweringBase | inlinevirtual |
shouldExtendTypeInLibCall(EVT Type) const | llvm::TargetLoweringBase | inlinevirtual |
shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const | llvm::TargetLoweringBase | inlinevirtual |
shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc) | llvm::AMDGPUTargetLowering | static |
shouldFoldMaskToVariableShiftPair(SDValue X) const | llvm::TargetLoweringBase | inlinevirtual |
shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldFoldSelectWithSingleBitTest(EVT VT, const APInt &AndMask) const | llvm::TargetLoweringBase | inlinevirtual |
shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const | llvm::TargetLoweringBase | inlinevirtual |
shouldInsertFencesForAtomic(const Instruction *I) const | llvm::TargetLoweringBase | inlinevirtual |
shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const | llvm::TargetLoweringBase | inlinevirtual |
shouldKeepZExtForFP16Conv() const | llvm::TargetLoweringBase | inlinevirtual |
shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const | llvm::TargetLoweringBase | virtual |
shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const | llvm::TargetLoweringBase | inlinevirtual |
shouldReassociateReduction(unsigned RedOpc, EVT VT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override | llvm::AMDGPUTargetLowering | virtual |
shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldRemoveRedundantExtend(SDValue Op) const | llvm::TargetLoweringBase | inlinevirtual |
shouldScalarizeBinop(SDValue VecOp) const | llvm::TargetLoweringBase | inlinevirtual |
ShouldShrinkFPConstant(EVT VT) const override | llvm::AMDGPUTargetLowering | virtual |
shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const | llvm::TargetLoweringBase | inlinevirtual |
shouldSimplifyDemandedVectorElts(SDValue Op, const TargetLoweringOpt &TLO) const | llvm::TargetLowering | inlinevirtual |
shouldSplatInsEltVarIndex(EVT) const | llvm::TargetLoweringBase | inlinevirtual |
shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const | llvm::TargetLowering | inlinevirtual |
shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const | llvm::TargetLoweringBase | inlinevirtual |
shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const | llvm::TargetLoweringBase | inlinevirtual |
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &DemandedBits, TargetLoweringOpt &TLO) const | llvm::TargetLowering | |
signExtendConstant(const ConstantInt *C) const | llvm::TargetLoweringBase | inlinevirtual |
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const | llvm::TargetLowering | virtual |
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const | llvm::TargetLowering | |
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, DAGCombinerInfo &DCI) const | llvm::TargetLowering | |
SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const | llvm::TargetLowering | virtual |
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | |
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | |
SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const | llvm::TargetLowering | virtual |
SimplifyMultipleUseDemandedVectorElts(SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const | llvm::TargetLowering | |
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const | llvm::TargetLowering | |
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) const | llvm::TargetLowering | |
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling=false) const | llvm::TargetLowering | |
softPromoteHalfType() const | llvm::TargetLoweringBase | inlinevirtual |
split64BitValue(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const | llvm::AMDGPUTargetLowering | protected |
splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const | llvm::TargetLowering | inlinevirtual |
splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
SplitVectorStore(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AS) const override | llvm::AMDGPUTargetLowering | virtual |
storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const | llvm::AMDGPUTargetLowering | |
stripBitcast(SDValue Val) | llvm::AMDGPUTargetLowering | inlinestatic |
supportKCFIBundles() const | llvm::TargetLowering | inlinevirtual |
supportPtrAuthBundles() const | llvm::TargetLowering | inlinevirtual |
supportSplitCSR(MachineFunction *MF) const | llvm::TargetLowering | inlinevirtual |
supportsUnalignedAtomics() const | llvm::TargetLoweringBase | inline |
supportSwiftError() const | llvm::TargetLowering | inlinevirtual |
TargetLowering(const TargetLowering &)=delete | llvm::TargetLowering | |
TargetLowering(const TargetMachine &TM) | llvm::TargetLowering | explicit |
TargetLoweringBase(const TargetMachine &TM) | llvm::TargetLoweringBase | explicit |
TargetLoweringBase(const TargetLoweringBase &)=delete | llvm::TargetLoweringBase | |
targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const | llvm::TargetLowering | inlinevirtual |
TypeExpandFloat enum value | llvm::TargetLoweringBase | |
TypeExpandInteger enum value | llvm::TargetLoweringBase | |
TypeLegal enum value | llvm::TargetLoweringBase | |
TypePromoteFloat enum value | llvm::TargetLoweringBase | |
TypePromoteInteger enum value | llvm::TargetLoweringBase | |
TypeScalarizeScalableVector enum value | llvm::TargetLoweringBase | |
TypeScalarizeVector enum value | llvm::TargetLoweringBase | |
TypeSoftenFloat enum value | llvm::TargetLoweringBase | |
TypeSoftPromoteHalf enum value | llvm::TargetLoweringBase | |
TypeSplitVector enum value | llvm::TargetLoweringBase | |
TypeWidenVector enum value | llvm::TargetLoweringBase | |
UndefinedBooleanContent enum value | llvm::TargetLoweringBase | |
Unspecified enum value | llvm::TargetLoweringBase | |
unwrapAddress(SDValue N) const | llvm::TargetLowering | inlinevirtual |
useFPRegsForHalfType() const | llvm::TargetLoweringBase | inlinevirtual |
useLoadStackGuardNode(const Module &M) const | llvm::TargetLowering | inlinevirtual |
useSoftFloat() const | llvm::TargetLoweringBase | inlinevirtual |
useStackGuardXorFP() const | llvm::TargetLoweringBase | inlinevirtual |
VectorMaskSelect enum value | llvm::TargetLoweringBase | |
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const | llvm::TargetLowering | |
verifyTargetSDNode(const SDNode *N) const | llvm::TargetLowering | inlinevirtual |
visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const | llvm::TargetLowering | inlinevirtual |
visitMaskedStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const | llvm::TargetLowering | inlinevirtual |
WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const | llvm::AMDGPUTargetLowering | protected |
ZeroOrNegativeOneBooleanContent enum value | llvm::TargetLoweringBase | |
ZeroOrOneBooleanContent enum value | llvm::TargetLoweringBase | |
~TargetLoweringBase()=default | llvm::TargetLoweringBase | virtual |