LLVM 20.0.0git
llvm::RISCVInstrInfo Member List

This is the complete list of members for llvm::RISCVInstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::RISCVInstrInfo
analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const overridellvm::RISCVInstrInfo
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const overridellvm::RISCVInstrInfo
buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const overridellvm::RISCVInstrInfo
canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const overridellvm::RISCVInstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const overridellvm::RISCVInstrInfo
convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const overridellvm::RISCVInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const overridellvm::RISCVInstrInfo
copyPhysRegVector(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RegClass) constllvm::RISCVInstrInfo
createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const overridellvm::RISCVInstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::RISCVInstrInfo
emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const overridellvm::RISCVInstrInfo
finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const overridellvm::RISCVInstrInfo
findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::RISCVInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const overridellvm::RISCVInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) constllvm::RISCVInstrInfoinline
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) constllvm::RISCVInstrInfoinline
genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const overridellvm::RISCVInstrInfo
getBranchDestBlock(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
getBrCond(RISCVCC::CondCode CC, bool Imm=false) constllvm::RISCVInstrInfo
getCombinerObjective(unsigned Pattern) const overridellvm::RISCVInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
getInverseOpcode(unsigned Opcode) const overridellvm::RISCVInstrInfo
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const overridellvm::RISCVInstrInfo
getMachineCombinerTraceStrategy() const overridellvm::RISCVInstrInfo
getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const overridellvm::RISCVInstrInfo
getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) constllvm::RISCVInstrInfo
getNop() const overridellvm::RISCVInstrInfo
getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs) const overridellvm::RISCVInstrInfo
getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MBBI, unsigned Flags) const overridellvm::RISCVInstrInfovirtual
getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const overridellvm::RISCVInstrInfo
getSerializableDirectMachineOperandTargetFlags() const overridellvm::RISCVInstrInfo
getSerializableMachineMemOperandTargetFlags() const overridellvm::RISCVInstrInfo
getTailDuplicateSize(CodeGenOptLevel OptLevel) const overridellvm::RISCVInstrInfo
getUndefInitOpcode(unsigned RegClassID) const overridellvm::RISCVInstrInfoinline
hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const overridellvm::RISCVInstrInfo
hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const overridellvm::RISCVInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const overridellvm::RISCVInstrInfo
insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const overridellvm::RISCVInstrInfo
insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const overridellvm::RISCVInstrInfo
isAddImmediate(const MachineInstr &MI, Register Reg) const overridellvm::RISCVInstrInfo
isAsCheapAsAMove(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const overridellvm::RISCVInstrInfo
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const overridellvm::RISCVInstrInfo
isCopyInstrImpl(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const overridellvm::RISCVInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::RISCVInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const overridellvm::RISCVInstrInfo
isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const overridellvm::RISCVInstrInfo
isReallyTriviallyReMaterializable(const MachineInstr &MI) const overridellvm::RISCVInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::RISCVInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const overridellvm::RISCVInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const overridellvm::RISCVInstrInfo
movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) constllvm::RISCVInstrInfo
mulImm(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) constllvm::RISCVInstrInfo
optimizeCondBranch(MachineInstr &MI) const overridellvm::RISCVInstrInfo
optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const overridellvm::RISCVInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::RISCVInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::RISCVInstrInfo
RISCVInstrInfo(RISCVSubtarget &STI)llvm::RISCVInstrInfoexplicit
shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const overridellvm::RISCVInstrInfo
shouldOutlineFromFunctionByDefault(MachineFunction &MF) const overridellvm::RISCVInstrInfo
STIllvm::RISCVInstrInfoprotected
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const overridellvm::RISCVInstrInfo
useMachineCombiner() const overridellvm::RISCVInstrInfoinline
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const overridellvm::RISCVInstrInfo