LLVM 20.0.0git
llvm::SITargetLowering Member List

This is the complete list of members for llvm::SITargetLowering, including all inherited members.

ABS enum valuellvm::TargetLoweringBase
AddAnd enum valuellvm::TargetLoweringBase
addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddMemOpInit(MachineInstr &MI) constllvm::SITargetLowering
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
addressingModeSupportsTLS(const GlobalValue &) constllvm::TargetLoweringBaseinlinevirtual
addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) constllvm::AMDGPUTargetLowering
AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const overridellvm::SITargetLoweringvirtual
aggressivelyPreferBuildVectorSources(EVT VecVT) const overridellvm::AMDGPUTargetLoweringvirtual
alignLoopsWithOptSize() constllvm::TargetLoweringBaseinlinevirtual
allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) constllvm::SITargetLowering
allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) constllvm::SITargetLowering
allocatePreloadKernArgSGPRs(CCState &CCInfo, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ISD::InputArg > &Ins, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) constllvm::SITargetLowering
allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) constllvm::SITargetLowering
allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) constllvm::SITargetLowering
allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) constllvm::SITargetLowering
allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) constllvm::SITargetLowering
allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) constllvm::SITargetLowering
allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags)llvm::AMDGPUTargetLoweringprotectedstatic
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) constllvm::TargetLoweringBasevirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) constllvm::TargetLoweringBase
allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const overridellvm::SITargetLoweringinlinevirtual
allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const overridellvm::SITargetLoweringvirtual
allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) constllvm::SITargetLowering
allowTruncateForTailCall(Type *FromTy, Type *ToTy) constllvm::TargetLoweringBaseinlinevirtual
allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)llvm::AMDGPUTargetLoweringstatic
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)llvm::AMDGPUTargetLowering
analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) constllvm::AMDGPUTargetLoweringprotected
AndOrSETCCFoldKind enum namellvm::TargetLoweringBase
areJTsAllowed(const Function *Fn) constllvm::TargetLoweringBaseinlinevirtual
areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) constllvm::TargetLoweringBaseinlinevirtual
ArgListTy typedefllvm::TargetLoweringBase
AsmOperandInfoVector typedefllvm::TargetLowering
AtomicExpansionKind enum namellvm::TargetLoweringBase
BooleanContent enum namellvm::TargetLoweringBase
buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) constllvm::TargetLowering
buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) constllvm::SITargetLowering
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLoweringvirtual
buildSDIVPow2WithCMov(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLoweringvirtual
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode * > &Created) constllvm::TargetLowering
bundleInstWithWaitcnt(MachineInstr &MI) constllvm::SITargetLowering
C_Address enum valuellvm::TargetLowering
C_Immediate enum valuellvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) constllvm::TargetLoweringBaseinlinevirtual
canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOnly) constllvm::TargetLoweringBaseinlinevirtual
canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) constllvm::TargetLoweringvirtual
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const overridellvm::SITargetLoweringvirtual
canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const overridellvm::SITargetLoweringvirtual
canOpTrap(unsigned Op, EVT VT) constllvm::TargetLoweringBasevirtual
CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)llvm::AMDGPUTargetLoweringstatic
CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)llvm::AMDGPUTargetLoweringstatic
checkAsmConstraintVal(SDValue Op, StringRef Constraint, uint64_t Val) constllvm::SITargetLowering
checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) constllvm::SITargetLowering
checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const overridellvm::SITargetLoweringvirtual
CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const overridellvm::SITargetLoweringvirtual
combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLowering
combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLowering
combineRepeatedFPDivisors() const overridellvm::SITargetLoweringinlinevirtual
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) constllvm::TargetLoweringvirtual
computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const overridellvm::SITargetLoweringvirtual
computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const overridellvm::SITargetLoweringvirtual
computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const overridellvm::SITargetLoweringvirtual
computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::SITargetLoweringvirtual
computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const overridellvm::AMDGPUTargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::AMDGPUTargetLoweringvirtual
computeRegisterProperties(const TargetRegisterInfo *TRI)llvm::TargetLoweringBaseprotected
ConstraintGroup typedefllvm::TargetLowering
ConstraintPair typedefllvm::TargetLowering
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
convertSelectOfConstantsToMath(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
convertSetCCLogicToBitwiseLogic(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) constllvm::SITargetLowering
createComplexDeinterleavingIR(IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, Value *Accumulator=nullptr) constllvm::TargetLoweringBaseinlinevirtual
createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) constllvm::TargetLoweringinlinevirtual
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg=false) constllvm::AMDGPUTargetLowering
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) constllvm::AMDGPUTargetLoweringinline
CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) constllvm::AMDGPUTargetLoweringinline
createSelectForFMINNUM_FMAXNUM(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
CTTZTableLookup(SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned NumBitsPerElt) constllvm::TargetLowering
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) constllvm::TargetLoweringBaseinlinevirtual
denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) constllvm::SITargetLowering
denormalsEnabledForType(LLT Ty, const MachineFunction &MF) constllvm::SITargetLowering
Disabled enum valuellvm::TargetLoweringBase
emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) constllvm::TargetLoweringBaseinlinevirtual
emitBitTestAtomicRMWIntrinsic(AtomicRMWInst *AI) constllvm::TargetLoweringBaseinlinevirtual
emitCmpArithAtomicRMWIntrinsic(AtomicRMWInst *AI) constllvm::TargetLoweringBaseinlinevirtual
emitExpandAtomicAddrSpacePredicate(Instruction *AI) constllvm::SITargetLowering
emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const overridellvm::SITargetLoweringvirtual
emitExpandAtomicRMW(AtomicRMWInst *AI) const overridellvm::SITargetLoweringvirtual
emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) constllvm::SITargetLowering
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const overridellvm::SITargetLoweringvirtual
EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) constllvm::TargetLoweringBaseinlinevirtual
emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBasevirtual
emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) constllvm::TargetLoweringBaseprotected
emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) constllvm::TargetLoweringinlinevirtual
emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) constllvm::TargetLoweringBaseinlinevirtual
emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) constllvm::TargetLoweringBasevirtual
enableAggressiveFMAFusion(EVT VT) const overridellvm::SITargetLoweringvirtual
enableAggressiveFMAFusion(LLT Ty) const overridellvm::SITargetLoweringvirtual
Enabled enum valuellvm::TargetLoweringBase
enableExtLdPromotion() constllvm::TargetLoweringBaseinline
EnableExtLdPromotionllvm::TargetLoweringBaseprotected
Expand enum valuellvm::TargetLoweringBase
expandABD(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative=false) constllvm::TargetLowering
expandAddSubSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandAVG(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandBITREVERSE(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandBSWAP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCMP(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandCTLZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTPOP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandCTTZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandDIVREMByConstant(SDNode *N, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue()) constllvm::TargetLowering
expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) constllvm::TargetLowering
expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) constllvm::TargetLowering
expandFunnelShift(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
ExpandInlineAsm(CallInst *) constllvm::TargetLoweringinlinevirtual
expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLowering
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) constllvm::TargetLowering
expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) constllvm::TargetLowering
expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) constllvm::TargetLowering
expandRoundInexactToOdd(EVT ResultVT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLowering
expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) constllvm::TargetLowering
expandShlSat(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) constllvm::TargetLowering
expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduce(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVECTOR_COMPRESS(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVectorNaryOpBySplitting(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVectorSplice(SDNode *Node, SelectionDAG &DAG) constllvm::TargetLowering
expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPBSWAP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPCTLZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPCTPOP(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPCTTZ(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
expandVPCTTZElements(SDNode *N, SelectionDAG &DAG) constllvm::TargetLowering
fallBackToDAGISel(const Instruction &Inst) constllvm::TargetLoweringBaseinlinevirtual
finalizeLowering(MachineFunction &MF) const overridellvm::SITargetLoweringvirtual
findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) constllvm::TargetLoweringvirtual
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) constllvm::TargetLoweringBaseprotectedvirtual
FIRST_IMPLICIT enum valuellvm::AMDGPUTargetLowering
foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI, SDValue N) constllvm::AMDGPUTargetLoweringprotected
forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, EVT WideVT, const SDValue LL, const SDValue LH, const SDValue RL, const SDValue RH, SDValue &Lo, SDValue &Hi) constllvm::TargetLowering
forceExpandWideMUL(SelectionDAG &DAG, const SDLoc &dl, bool Signed, const SDValue LHS, const SDValue RHS, SDValue &Lo, SDValue &Hi) constllvm::TargetLowering
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) constllvm::TargetLoweringinlinevirtual
GatherAllAliasesMaxDepthllvm::TargetLoweringBaseprotected
generateFMAsInMachineCombiner(EVT VT, CodeGenOptLevel OptLevel) constllvm::TargetLoweringBaseinlinevirtual
getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const overridellvm::SITargetLoweringvirtual
getAsmOperandConstVal(SDValue Op, uint64_t &Val) constllvm::SITargetLowering
getAsmOperandValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinlinevirtual
getAtomicLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) constllvm::TargetLoweringBase
getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) constllvm::TargetLoweringBase
getBooleanContents(bool isVec, bool isFloat) constllvm::TargetLoweringBaseinline
getBooleanContents(EVT Type) constllvm::TargetLoweringBaseinline
getBypassSlowDivWidths() constllvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty, const DataLayout &DL) constllvm::TargetLoweringBasevirtual
getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) constllvm::TargetLoweringinline
getCheaperOrNeutralNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) constllvm::TargetLoweringinline
getCmpLibcallCC(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getCmpLibcallReturnType() constllvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
getConstantNegateCost(const ConstantFPSDNode *C) constllvm::AMDGPUTargetLoweringprotected
getConstraintPreferences(AsmOperandInfo &OpInfo) constllvm::TargetLowering
getConstraintType(StringRef Constraint) const overridellvm::SITargetLoweringvirtual
getCustomCtpopCost(EVT VT, ISD::CondCode Cond) constllvm::TargetLoweringBaseinlinevirtual
getCustomOperationAction(SDNode &Op) constllvm::TargetLoweringBaseinlinevirtual
getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) constllvm::TargetLoweringBaseprotected
getDivRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getEquivalentMemType(LLVMContext &Context, EVT VT)llvm::AMDGPUTargetLoweringprotectedstatic
getExceptionPointerRegister(const Constant *PersonalityFn) constllvm::TargetLoweringBaseinlinevirtual
getExceptionSelectorRegister(const Constant *PersonalityFn) constllvm::TargetLoweringBaseinlinevirtual
getExtendForAtomicCmpSwapArg() constllvm::TargetLoweringBaseinlinevirtual
getExtendForAtomicOps() constllvm::TargetLoweringBaseinlinevirtual
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getFenceOperandTy(const DataLayout &DL) const overridellvm::AMDGPUTargetLoweringinlinevirtual
getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinline
getFrameIndexTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getGatherAllAliasesMaxDepth() constllvm::TargetLoweringBaseinline
getHiHalf64(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) constllvm::AMDGPUTargetLowering
getImplicitParameterOffset(const uint64_t ExplicitKernArgSize, const ImplicitParameter Param) constllvm::AMDGPUTargetLowering
getIndexedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) constllvm::TargetLoweringBaseinline
getInlineAsmMemConstraint(StringRef ConstraintCode) constllvm::TargetLoweringinlinevirtual
getIRStackGuard(IRBuilderBase &IRB) constllvm::TargetLoweringBasevirtual
getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) constllvm::AMDGPUTargetLoweringprotected
getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) constllvm::AMDGPUTargetLoweringprotected
getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) constllvm::TargetLoweringBaseinlinevirtual
getJumpTableEncoding() constllvm::TargetLoweringvirtual
getJumpTableRegTy(const DataLayout &DL) constllvm::TargetLoweringinlinevirtual
getLibcallCallingConv(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) constllvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) constllvm::TargetLoweringBase
getLoHalf64(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
getMaxAtomicSizeInBitsSupported() constllvm::TargetLoweringBaseinline
getMaxDivRemBitWidthSupported() constllvm::TargetLoweringBaseinline
getMaxExpandSizeMemcmp(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxGluedStoresPerMemcpy() constllvm::TargetLoweringBaseinlinevirtual
getMaximumJumpTableSize() constllvm::TargetLoweringBase
getMaxLargeFPConvertBitWidthSupported() constllvm::TargetLoweringBaseinline
getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) constllvm::TargetLoweringBasevirtual
getMaxStoresPerMemcpy(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) constllvm::TargetLoweringBaseinline
getMaxSupportedInterleaveFactor() constllvm::TargetLoweringBaseinlinevirtual
getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getMinCmpXchgSizeInBits() constllvm::TargetLoweringBaseinline
getMinFunctionAlignment() constllvm::TargetLoweringBaseinline
getMinimumJumpTableDensity(bool OptForSize) constllvm::TargetLoweringBase
getMinimumJumpTableEntries() constllvm::TargetLoweringBasevirtual
getMinStackArgumentAlignment() constllvm::TargetLoweringBaseinline
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) constllvm::TargetLoweringvirtual
getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const overridellvm::AMDGPUTargetLoweringvirtual
llvm::TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) constllvm::TargetLoweringinline
getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) constllvm::TargetLoweringBaseinlinevirtual
getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const overridellvm::SITargetLoweringvirtual
getOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getOptimalMemOpLLT(const MemOp &Op, const AttributeList &) constllvm::TargetLoweringBaseinlinevirtual
getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const overridellvm::SITargetLoweringvirtual
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) constllvm::TargetLoweringvirtual
getPointerMemTy(const DataLayout &DL, unsigned AS) const overridellvm::SITargetLowering
llvm::AMDGPUTargetLowering::getPointerMemTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinlinevirtual
getPointerTy(const DataLayout &DL, unsigned AS) const overridellvm::SITargetLowering
llvm::AMDGPUTargetLowering::getPointerTy(const DataLayout &DL, uint32_t AS=0) constllvm::TargetLoweringBaseinlinevirtual
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) constllvm::TargetLoweringinlinevirtual
getPreferredLargeGEPBaseOffset(int64_t MinOffset, int64_t MaxOffset) constllvm::TargetLoweringBaseinlinevirtual
getPreferredShiftAmountTy(LLT Ty) const overridellvm::SITargetLoweringvirtual
getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) constllvm::TargetLoweringBasevirtual
getPreferredVectorAction(MVT VT) const overridellvm::SITargetLoweringvirtual
getPrefFunctionAlignment() constllvm::TargetLoweringBaseinline
getPrefLoopAlignment(MachineLoop *ML) const overridellvm::SITargetLoweringvirtual
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) constllvm::TargetLoweringinlinevirtual
getProgramPointerTy(const DataLayout &DL) constllvm::TargetLoweringBaseinline
getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const overridellvm::AMDGPUTargetLoweringvirtual
getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getRegClassFor(MVT VT, bool isDivergent) const overridellvm::SITargetLoweringvirtual
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const overridellvm::SITargetLoweringvirtual
getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const overridellvm::SITargetLoweringvirtual
getRegisterType(MVT VT) constllvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const overridellvm::SITargetLoweringvirtual
getRepRegClassCostFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) constllvm::TargetLoweringBaseinlinevirtual
getRoundingControlRegisters() const overridellvm::SITargetLoweringvirtual
getSafeStackPointerLocation(IRBuilderBase &IRB) constllvm::TargetLoweringBasevirtual
getScalarShiftAmountTy(const DataLayout &, EVT) const overridellvm::SITargetLoweringvirtual
getScaledLogInput(SelectionDAG &DAG, const SDLoc SL, SDValue Op, SDNodeFlags Flags) constllvm::AMDGPUTargetLoweringprotected
getSchedulingPreference() constllvm::TargetLoweringBaseinline
getSchedulingPreference(SDNode *) constllvm::TargetLoweringBaseinlinevirtual
getScratchRegisters(CallingConv::ID CC) constllvm::TargetLoweringinlinevirtual
getSDagStackGuard(const Module &M) constllvm::TargetLoweringBasevirtual
getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const overridellvm::SITargetLoweringvirtual
getShiftAmountTy(EVT LHSTy, const DataLayout &DL) constllvm::TargetLoweringBase
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) constllvm::TargetLoweringvirtual
getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const overridellvm::AMDGPUTargetLoweringvirtual
getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, const DenormalMode &Mode) constllvm::TargetLoweringvirtual
getSqrtRefinementSteps(EVT VT, MachineFunction &MF) constllvm::TargetLoweringBase
getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
getSSPStackGuardCheck(const Module &M) constllvm::TargetLoweringBasevirtual
getStackPointerRegisterToSaveRestore() constllvm::TargetLoweringBaseinline
getStackProbeSymbolName(const MachineFunction &MF) constllvm::TargetLoweringBaseinlinevirtual
getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) constllvm::TargetLoweringBase
getStrictFPOperationAction(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
getSubtarget() constllvm::SITargetLowering
getTargetConstantFromLoad(LoadSDNode *LD) constllvm::TargetLoweringvirtual
getTargetMachine() constllvm::TargetLoweringBaseinline
getTargetMMOFlags(const Instruction &I) const overridellvm::SITargetLoweringvirtual
llvm::AMDGPUTargetLowering::getTargetMMOFlags(const MemSDNode &Node) constllvm::TargetLoweringBaseinlinevirtual
getTargetNodeName(unsigned Opcode) const overridellvm::AMDGPUTargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const overridellvm::SITargetLoweringvirtual
getTruncStoreAction(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeAction(MVT VT) constllvm::TargetLoweringBaseinline
getTypeConversion(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBase
getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const overridellvm::AMDGPUTargetLoweringvirtual
getTypeToExpandTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) constllvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
getVaListSizeInBits(const DataLayout &DL) constllvm::TargetLoweringBaseinlinevirtual
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) constllvm::TargetLoweringBaseinline
getValueTypeActions() constllvm::TargetLoweringBaseinline
getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) constllvm::TargetLowering
getVectorIdxTy(const DataLayout &) const overridellvm::AMDGPUTargetLoweringvirtual
getVectorSubVecPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) constllvm::TargetLowering
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) constllvm::TargetLoweringBase
getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const overridellvm::SITargetLoweringvirtual
getVPExplicitVectorLengthTy() constllvm::TargetLoweringBaseinlinevirtual
HandleByVal(CCState *, unsigned &, Align) constllvm::TargetLoweringinlinevirtual
hasAndNot(SDValue X) constllvm::TargetLoweringBaseinlinevirtual
hasAndNotCompare(SDValue Y) constllvm::TargetLoweringBaseinlinevirtual
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) constllvm::TargetLoweringBaseinline
hasBitTest(SDValue X, SDValue Y) constllvm::TargetLoweringBaseinlinevirtual
hasExtractBitsInsn() constllvm::TargetLoweringBaseinline
hasFastEqualityCompare(unsigned NumBits) constllvm::TargetLoweringBaseinlinevirtual
hasInlineStackProbe(const MachineFunction &MF) constllvm::TargetLoweringBaseinlinevirtual
hasMemSDNodeUser(SDNode *N) constllvm::SITargetLowering
hasMultipleConditionRegisters() constllvm::TargetLoweringBaseinline
hasPairedLoad(EVT, Align &) constllvm::TargetLoweringBaseinlinevirtual
hasStackProbeSymbol(const MachineFunction &MF) constllvm::TargetLoweringBaseinlinevirtual
hasStandaloneRem(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) constllvm::TargetLoweringBaseinline
hasVectorBlend() constllvm::TargetLoweringBaseinlinevirtual
ImplicitParameter enum namellvm::AMDGPUTargetLowering
IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) constllvm::TargetLowering
initActions()llvm::TargetLoweringBaseprotected
initializeSplitCSR(MachineBasicBlock *Entry) const overridellvm::SITargetLoweringvirtual
insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const overridellvm::SITargetLoweringvirtual
insertSSPDeclarations(Module &M) constllvm::TargetLoweringBasevirtual
InstructionOpcodeToISD(unsigned Opcode) constllvm::TargetLoweringBase
isAtomicLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) constllvm::TargetLoweringBaseinline
isBinOp(unsigned Opcode) constllvm::TargetLoweringBaseinlinevirtual
isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) constllvm::SITargetLowering
isCanonicalized(Register Reg, const MachineFunction &MF, unsigned MaxDepth=5) constllvm::SITargetLowering
isCheapToSpeculateCtlz(Type *Ty) const overridellvm::AMDGPUTargetLoweringvirtual
isCheapToSpeculateCttz(Type *Ty) const overridellvm::AMDGPUTargetLoweringvirtual
isCommutativeBinOp(unsigned Opcode) constllvm::TargetLoweringBaseinlinevirtual
isComplexDeinterleavingOperationSupported(ComplexDeinterleavingOperation Operation, Type *Ty) constllvm::TargetLoweringBaseinlinevirtual
isComplexDeinterleavingSupported() constllvm::TargetLoweringBaseinlinevirtual
isCondCodeLegal(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) constllvm::TargetLoweringBaseinline
isConstantCheaperToNegate(SDValue N) constllvm::AMDGPUTargetLoweringprotected
isConstantCostlierToNegate(SDValue N) constllvm::AMDGPUTargetLoweringprotected
isConstFalseVal(SDValue N) constllvm::TargetLowering
isConstTrueVal(SDValue N) constllvm::TargetLowering
isCtlzFast() constllvm::TargetLoweringBaseinlinevirtual
isCtpopFast(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isDesirableToCombineLogicOpOfSETCC(const SDNode *LogicOp, const SDNode *SETCC0, const SDNode *SETCC1) constllvm::TargetLoweringinlinevirtual
isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const overridellvm::AMDGPUTargetLoweringvirtual
llvm::TargetLowering::isDesirableToCommuteWithShift(const MachineInstr &MI, bool IsAfterLegal) constllvm::TargetLoweringinlinevirtual
isDesirableToCommuteXorWithShift(const SDNode *N) constllvm::TargetLoweringinlinevirtual
IsDesirableToPromoteOp(SDValue, EVT &) constllvm::TargetLoweringinlinevirtual
isDesirableToPullExtFromShl(const MachineInstr &MI) constllvm::TargetLoweringinlinevirtual
isDesirableToTransformToIntegerOp(unsigned, EVT) constllvm::TargetLoweringinlinevirtual
isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) constllvm::SITargetLowering
isEqualityCmpFoldedWithSignedCmp() constllvm::TargetLoweringBaseinlinevirtual
isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) constllvm::TargetLowering
isExtFree(const Instruction *I) constllvm::TargetLoweringBaseinline
isExtFreeImpl(const Instruction *I) constllvm::TargetLoweringBaseinlineprotectedvirtual
isExtLoad(const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const overridellvm::SITargetLoweringvirtual
isExtractVecEltCheap(EVT VT, unsigned Index) constllvm::TargetLoweringBaseinlinevirtual
isFAbsFree(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const overridellvm::SITargetLoweringvirtual
isFMADLegal(const MachineInstr &MI, const LLT Ty) const overridellvm::SITargetLoweringvirtual
isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const overridellvm::SITargetLoweringvirtual
isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, const LLT Ty) const overridellvm::SITargetLoweringvirtual
llvm::AMDGPUTargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F, Type *) constllvm::TargetLoweringBaseinlinevirtual
isFNegFree(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const overridellvm::SITargetLoweringvirtual
isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const overridellvm::SITargetLoweringvirtual
isFPExtFree(EVT DestVT, EVT SrcVT) constllvm::TargetLoweringBaseinlinevirtual
isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const overridellvm::AMDGPUTargetLoweringvirtual
isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const overridellvm::SITargetLoweringvirtual
isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringinlinevirtual
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) constllvm::TargetLoweringvirtual
isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) constllvm::TargetLoweringvirtual
isIndexedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) constllvm::TargetLoweringBaseinline
isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) constllvm::TargetLoweringinlinevirtual
isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) constllvm::TargetLoweringinlinevirtual
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) constllvm::TargetLowering
isIntDivCheap(EVT VT, AttributeList Attr) constllvm::TargetLoweringBaseinlinevirtual
isJumpExpensive() constllvm::TargetLoweringBaseinline
isJumpTableRelative() constllvm::TargetLoweringBasevirtual
isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const overridellvm::SITargetLoweringvirtual
isLegalAddImmediate(int64_t) constllvm::TargetLoweringBaseinlinevirtual
isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const overridellvm::SITargetLoweringvirtual
isLegalAddScalableImmediate(int64_t) constllvm::TargetLoweringBaseinlinevirtual
isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) constllvm::SITargetLowering
isLegalGlobalAddressingMode(const AddrMode &AM) constllvm::SITargetLowering
isLegalICmpImmediate(int64_t) constllvm::TargetLoweringBaseinlinevirtual
isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) constllvm::TargetLoweringBaseprotected
isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) constllvm::TargetLoweringBaseinlinevirtual
isLegalStoreImmediate(int64_t Value) constllvm::TargetLoweringBaseinlinevirtual
isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const finalllvm::AMDGPUTargetLoweringvirtual
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) constllvm::TargetLoweringBaseinlinevirtual
isMemOpHasNoClobberedMemOperand(const SDNode *N) constllvm::SITargetLowering
isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) constllvm::TargetLoweringBaseinlinevirtual
isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) constllvm::TargetLoweringBaseinlinevirtual
isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const overridellvm::AMDGPUTargetLoweringvirtual
isNonGlobalAddrSpace(unsigned AS)llvm::SITargetLoweringstatic
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const overridellvm::SITargetLoweringvirtual
isOperationCustom(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationExpand(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) constllvm::TargetLoweringBaseinline
isPaddedAtMostSignificantBitsWhenStored(EVT VT) constllvm::TargetLoweringBaseinline
isPositionIndependent() constllvm::TargetLowering
isPredictableSelectExpensive() constllvm::TargetLoweringBaseinline
isProfitableToCombineMinNumMaxNum(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
isProfitableToHoist(Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const overridellvm::SITargetLoweringvirtual
isReassocProfitable(MachineRegisterInfo &MRI, Register N0, Register N1) const overridellvm::SITargetLoweringvirtual
isSafeMemOpType(MVT) constllvm::TargetLoweringBaseinlinevirtual
isSDNodeAlwaysUniform(const SDNode *N) const overridellvm::AMDGPUTargetLoweringvirtual
isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const overridellvm::SITargetLoweringvirtual
isSelectSupported(SelectSupportKind) const overridellvm::AMDGPUTargetLoweringvirtual
isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) constllvm::TargetLoweringBaseinlinevirtual
isShuffleMaskLegal(ArrayRef< int >, EVT) const overridellvm::SITargetLoweringvirtual
isSlowDivBypassed() constllvm::TargetLoweringBaseinline
isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLoweringvirtual
isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) constllvm::TargetLoweringBaseinlinevirtual
IsStrictFPEnabledllvm::TargetLoweringBaseprotected
isStrictFPEnabled() constllvm::TargetLoweringBaseinline
isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) constllvm::TargetLoweringBasevirtual
isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) constllvm::TargetLoweringBaseinlinevirtual
isTargetCanonicalConstantNode(SDValue Op) constllvm::TargetLoweringinlinevirtual
isTruncateFree(EVT Src, EVT Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isTruncateFree(Type *Src, Type *Dest) const overridellvm::AMDGPUTargetLoweringvirtual
llvm::TargetLowering::isTruncateFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) constllvm::TargetLoweringBaseinlinevirtual
llvm::TargetLowering::isTruncateFree(SDValue Val, EVT VT2) constllvm::TargetLoweringBaseinlinevirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) constllvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned Op, EVT VT) const overridellvm::SITargetLoweringvirtual
isTypeLegal(EVT VT) constllvm::TargetLoweringBaseinline
isUsedByReturnOnly(SDNode *, SDValue &) constllvm::TargetLoweringinlinevirtual
isVectorClearMaskLegal(ArrayRef< int >, EVT) constllvm::TargetLoweringBaseinlinevirtual
isVectorLoadExtDesirable(SDValue ExtVal) constllvm::TargetLoweringBaseinlinevirtual
isVScaleKnownToBeAPowerOfTwo() constllvm::TargetLoweringBaseinlinevirtual
isXAndYEqZeroPreferableToXAndYEqY(ISD::CondCode, EVT) constllvm::TargetLoweringinlinevirtual
isZExtFree(Type *Src, Type *Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isZExtFree(EVT Src, EVT Dest) const overridellvm::AMDGPUTargetLoweringvirtual
llvm::TargetLowering::isZExtFree(LLT FromTy, LLT ToTy, LLVMContext &Ctx) constllvm::TargetLoweringBaseinlinevirtual
llvm::TargetLowering::isZExtFree(SDValue Val, EVT VT2) constllvm::TargetLoweringBaseinlinevirtual
joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) constllvm::TargetLoweringinlinevirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) constllvm::TargetLowering
legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) constllvm::SITargetLowering
LegalizeTypeAction enum namellvm::TargetLoweringBase
LibCall enum valuellvm::TargetLoweringBase
loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) constllvm::AMDGPUTargetLowering
loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) constllvm::AMDGPUTargetLowering
LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const overridellvm::SITargetLoweringvirtual
LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const overridellvm::SITargetLoweringvirtual
LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) constllvm::SITargetLowering
LowerCallTo(CallLoweringInfo &CLI) constllvm::TargetLowering
lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerCTLZResults(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) constllvm::TargetLoweringinlinevirtual
lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl< Instruction * > &DeadInsts) constllvm::TargetLoweringBaseinlinevirtual
LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) constllvm::AMDGPUTargetLoweringprotected
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFCEIL(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerFEXP(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) constllvm::AMDGPUTargetLoweringprotected
lowerFEXP2(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, SDNodeFlags Flags) constllvm::AMDGPUTargetLoweringprotected
LowerFFLOOR(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFLOG10(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFLOG2(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG, bool IsLog10, SDNodeFlags Flags) constllvm::AMDGPUTargetLoweringprotected
LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const overridellvm::SITargetLoweringvirtual
lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) constllvm::AMDGPUTargetLoweringprotected
LowerFREM(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFRINT(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFROUND(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerFTRUNC(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const overridellvm::SITargetLoweringvirtual
LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) constllvm::AMDGPUTargetLoweringprotected
LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) constllvm::AMDGPUTargetLoweringprotected
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) constllvm::TargetLoweringBaseinlinevirtual
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) constllvm::TargetLoweringBaseinlinevirtual
lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI, SmallVectorImpl< Instruction * > &DeadInsts) constllvm::TargetLoweringBaseinlinevirtual
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::SITargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
lowerPREFETCH(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const overridellvm::SITargetLoweringvirtual
LowerSDIVREM(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) constllvm::TargetLoweringvirtual
LowerUDIVREM(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) constllvm::AMDGPUTargetLoweringprotected
LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) constllvm::AMDGPUTargetLowering
LowerXConstraint(EVT ConstraintVT) constllvm::TargetLoweringvirtual
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) constllvm::TargetLowering
markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) constllvm::TargetLoweringBaseinlinevirtual
MaxGluedStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpllvm::TargetLoweringBaseprotected
MaxLoadsPerMemcmpOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mayBeEmittedAsTailCall(const CallInst *) const overridellvm::SITargetLoweringvirtual
mayIgnoreSignedZero(SDValue Op) constllvm::AMDGPUTargetLowering
mergeStoresAfterLegalization(EVT) const overridellvm::AMDGPUTargetLoweringinlinevirtual
MulExpansionKind enum namellvm::TargetLoweringBase
needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src, SDNodeFlags Flags)llvm::AMDGPUTargetLoweringprotectedstatic
needsFixedCatchObjects() constllvm::TargetLoweringBaseinlinevirtual
NegatibleCost enum namellvm::TargetLoweringBase
None enum valuellvm::TargetLoweringBase
NotAnd enum valuellvm::TargetLoweringBase
numBitsSigned(SDValue Op, SelectionDAG &DAG)llvm::AMDGPUTargetLoweringstatic
numBitsUnsigned(SDValue Op, SelectionDAG &DAG)llvm::AMDGPUTargetLoweringstatic
operator=(const TargetLowering &)=deletellvm::TargetLowering
llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
optimizeExtendOrTruncateConversion(Instruction *I, Loop *L, const TargetTransformInfo &TTI) constllvm::TargetLoweringBaseinlinevirtual
optimizeFMulOrFDivAsShiftAddBitcast(SDNode *N, SDValue FPConst, SDValue IntPow2) constllvm::TargetLoweringBaseinlinevirtual
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) constllvm::TargetLowering
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) constllvm::TargetLoweringvirtual
passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue > > &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) constllvm::SITargetLowering
performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::SITargetLoweringvirtual
performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performShlCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performSraCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) constllvm::AMDGPUTargetLoweringprotected
PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const overridellvm::SITargetLoweringvirtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
preferABDSToABSWithNSW(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
preferedOpcodeForCmpEqPiecesOfOperand(EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) constllvm::TargetLoweringBaseinlinevirtual
preferIncOfAddToSubOfNot(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) constllvm::TargetLoweringBaseinlinevirtual
preferScalarizeSplat(SDNode *N) constllvm::TargetLoweringBaseinlinevirtual
preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) constllvm::TargetLoweringBaseinlinevirtual
preferZeroCompareBranch() constllvm::TargetLoweringBaseinlinevirtual
prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) constllvm::TargetLoweringinlinevirtual
PRIVATE_BASE enum valuellvm::AMDGPUTargetLowering
Promote enum valuellvm::TargetLoweringBase
promoteTargetBoolean(SelectionDAG &DAG, SDValue Bool, EVT ValVT) constllvm::TargetLoweringBaseinline
QUEUE_PTR enum valuellvm::AMDGPUTargetLowering
rangeFitsInWord(const APInt &Low, const APInt &High, const DataLayout &DL) constllvm::TargetLoweringBaseinline
ReciprocalEstimate enum namellvm::TargetLoweringBase
reduceSelectOfFPConstantLoads(EVT CmpOpVT) constllvm::TargetLoweringBaseinlinevirtual
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const overridellvm::SITargetLoweringvirtual
requiresUniformRegister(MachineFunction &MF, const Value *V) const overridellvm::SITargetLoweringvirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) constllvm::TargetLowering
scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) constllvm::TargetLowering
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setAtomicLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setCondCodeAction(ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBaseinlineprotected
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaxBytesForAlignment(unsigned MaxBytes)llvm::TargetLoweringBaseinlineprotected
setMaxDivRemBitWidthSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaximumJumpTableSize(unsigned)llvm::TargetLoweringBaseprotected
setMaxLargeFPConvertBitWidthSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinCmpXchgSizeInBits(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(unsigned Val)llvm::TargetLoweringBaseprotected
setMinStackArgumentAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationAction(ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(Align Alignment)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(Register R)llvm::TargetLoweringBaseinlineprotected
setSupportsUnalignedAtomics(bool UnalignedSupported)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) constllvm::TargetLoweringBaseinlinevirtual
SHARED_BASE enum valuellvm::AMDGPUTargetLowering
ShiftLegalizationStrategy enum namellvm::TargetLoweringBase
shouldAlignPointerArgs(CallInst *, unsigned &, Align &) constllvm::TargetLoweringBaseinlinevirtual
shouldAvoidTransformToShift(EVT VT, unsigned Amount) constllvm::TargetLoweringBaseinlinevirtual
shouldCastAtomicLoadInIR(LoadInst *LI) const overridellvm::AMDGPUTargetLoweringinlinevirtual
shouldCastAtomicRMWIInIR(AtomicRMWInst *) const overridellvm::AMDGPUTargetLoweringinlinevirtual
shouldCastAtomicStoreInIR(StoreInst *SI) const overridellvm::AMDGPUTargetLoweringinlinevirtual
shouldCombineMemoryType(EVT VT) constllvm::AMDGPUTargetLoweringprotected
shouldConsiderGEPOffsetSplit() constllvm::TargetLoweringBaseinlinevirtual
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const overridellvm::SITargetLoweringvirtual
shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldConvertPhiType(Type *From, Type *To) constllvm::TargetLoweringBaseinlinevirtual
shouldConvertSplatType(ShuffleVectorInst *SVI) constllvm::TargetLoweringBaseinlinevirtual
shouldEmitFixup(const GlobalValue *GV) constllvm::SITargetLowering
shouldEmitGOTReloc(const GlobalValue *GV) constllvm::SITargetLowering
shouldEmitPCReloc(const GlobalValue *GV) constllvm::SITargetLowering
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const overridellvm::SITargetLoweringvirtual
shouldExpandAtomicLoadInIR(LoadInst *LI) const overridellvm::SITargetLoweringvirtual
shouldExpandAtomicRMWInIR(AtomicRMWInst *) const overridellvm::SITargetLoweringvirtual
shouldExpandAtomicStoreInIR(StoreInst *SI) const overridellvm::SITargetLoweringvirtual
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandCmpUsingSelects(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandCttzElements(EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandPartialReductionIntrinsic(const IntrinsicInst *I) constllvm::TargetLoweringBaseinlinevirtual
shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx, const GCNSubtarget *Subtarget)llvm::SITargetLoweringstatic
shouldExpandVectorDynExt(SDNode *N) constllvm::SITargetLowering
shouldExpandVectorMatch(EVT VT, unsigned SearchSize) constllvm::TargetLoweringBaseinlinevirtual
shouldExtendGSIndex(EVT VT, EVT &EltTy) constllvm::TargetLoweringBaseinlinevirtual
shouldExtendTypeInLibCall(EVT Type) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc)llvm::AMDGPUTargetLoweringstatic
shouldFoldMaskToVariableShiftPair(SDValue X) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldFoldSelectWithSingleBitTest(EVT VT, const APInt &AndMask) constllvm::TargetLoweringBaseinlinevirtual
shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) constllvm::TargetLoweringBaseinlinevirtual
shouldInsertFencesForAtomic(const Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
shouldInsertTrailingFenceForAtomicStore(const Instruction *I) constllvm::TargetLoweringBaseinlinevirtual
shouldKeepZExtForFP16Conv() constllvm::TargetLoweringBaseinlinevirtual
shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) constllvm::TargetLoweringBasevirtual
shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) constllvm::TargetLoweringBaseinlinevirtual
shouldReassociateReduction(unsigned RedOpc, EVT VT) constllvm::TargetLoweringBaseinlinevirtual
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const overridellvm::AMDGPUTargetLoweringvirtual
shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) constllvm::TargetLoweringBaseinlinevirtual
shouldRemoveRedundantExtend(SDValue Op) constllvm::TargetLoweringBaseinlinevirtual
shouldScalarizeBinop(SDValue VecOp) constllvm::TargetLoweringBaseinlinevirtual
ShouldShrinkFPConstant(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
shouldSimplifyDemandedVectorElts(SDValue Op, const TargetLoweringOpt &TLO) constllvm::TargetLoweringinlinevirtual
shouldSplatInsEltVarIndex(EVT) constllvm::TargetLoweringBaseinlinevirtual
shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) constllvm::TargetLoweringinlinevirtual
shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) constllvm::TargetLoweringBaseinlinevirtual
shouldUseLDSConstAddress(const GlobalValue *GV) constllvm::SITargetLowering
shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) constllvm::TargetLoweringBaseinlinevirtual
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, TargetLoweringOpt &TLO) constllvm::TargetLowering
ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &DemandedBits, TargetLoweringOpt &TLO) constllvm::TargetLowering
signExtendConstant(const ConstantInt *C) constllvm::TargetLoweringBaseinlinevirtual
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) constllvm::TargetLoweringvirtual
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) constllvm::TargetLowering
SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, DAGCombinerInfo &DCI) constllvm::TargetLowering
SimplifyDemandedVectorEltsForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) constllvm::TargetLoweringvirtual
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifyMultipleUseDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) constllvm::TargetLoweringvirtual
SimplifyMultipleUseDemandedVectorElts(SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) constllvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) constllvm::TargetLowering
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)llvm::SITargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) constllvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling=false) constllvm::TargetLowering
softPromoteHalfType() constllvm::TargetLoweringBaseinlinevirtual
split64BitValue(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) constllvm::AMDGPUTargetLoweringprotected
splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) constllvm::SITargetLowering
splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) constllvm::SITargetLowering
splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) constllvm::TargetLoweringinlinevirtual
splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
SplitVectorLoad(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
SplitVectorStore(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AS) const overridellvm::AMDGPUTargetLoweringvirtual
storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) constllvm::AMDGPUTargetLowering
stripBitcast(SDValue Val)llvm::AMDGPUTargetLoweringinlinestatic
supportKCFIBundles() constllvm::TargetLoweringinlinevirtual
supportPtrAuthBundles() constllvm::TargetLoweringinlinevirtual
supportSplitCSR(MachineFunction *MF) const overridellvm::SITargetLoweringvirtual
supportsUnalignedAtomics() constllvm::TargetLoweringBaseinline
supportSwiftError() constllvm::TargetLoweringinlinevirtual
TargetLowering(const TargetLowering &)=deletellvm::TargetLowering
TargetLowering(const TargetMachine &TM)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM)llvm::TargetLoweringBaseexplicit
TargetLoweringBase(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) constllvm::TargetLoweringinlinevirtual
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteFloat enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeScalableVector enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSoftPromoteHalf enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
Unspecified enum valuellvm::TargetLoweringBase
unwrapAddress(SDValue N) constllvm::TargetLoweringinlinevirtual
useFPRegsForHalfType() constllvm::TargetLoweringBaseinlinevirtual
useLoadStackGuardNode(const Module &M) constllvm::TargetLoweringinlinevirtual
useSoftFloat() constllvm::TargetLoweringBaseinlinevirtual
useStackGuardXorFP() constllvm::TargetLoweringBaseinlinevirtual
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) constllvm::TargetLowering
verifyTargetSDNode(const SDNode *N) constllvm::TargetLoweringinlinevirtual
visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) constllvm::TargetLoweringinlinevirtual
visitMaskedStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) constllvm::TargetLoweringinlinevirtual
WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) constllvm::AMDGPUTargetLoweringprotected
wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) constllvm::SITargetLowering
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()=defaultllvm::TargetLoweringBasevirtual
Generated on Sun Dec 22 2024 08:53:31 for LLVM by doxygen 1.9.6