LLVM
20.0.0git
llvm
TargetRegisterClass
llvm::TargetRegisterClass Member List
This is the complete list of members for
llvm::TargetRegisterClass
, including all inherited members.
AllocationPriority
llvm::TargetRegisterClass
begin
() const
llvm::TargetRegisterClass
inline
const_iterator
typedef
llvm::TargetRegisterClass
contains
(Register Reg) const
llvm::TargetRegisterClass
inline
contains
(Register Reg1, Register Reg2) const
llvm::TargetRegisterClass
inline
CoveredBySubRegs
llvm::TargetRegisterClass
end
() const
llvm::TargetRegisterClass
inline
getCopyCost
() const
llvm::TargetRegisterClass
inline
getID
() const
llvm::TargetRegisterClass
inline
getLaneMask
() const
llvm::TargetRegisterClass
inline
getNumRegs
() const
llvm::TargetRegisterClass
inline
getRawAllocationOrder
(const MachineFunction &MF) const
llvm::TargetRegisterClass
inline
getRegister
(unsigned i) const
llvm::TargetRegisterClass
inline
getRegisters
() const
llvm::TargetRegisterClass
inline
getSubClassMask
() const
llvm::TargetRegisterClass
inline
getSuperRegIndices
() const
llvm::TargetRegisterClass
inline
GlobalPriority
llvm::TargetRegisterClass
HasDisjunctSubRegs
llvm::TargetRegisterClass
hasSubClass
(const TargetRegisterClass *RC) const
llvm::TargetRegisterClass
inline
hasSubClassEq
(const TargetRegisterClass *RC) const
llvm::TargetRegisterClass
inline
hasSuperClass
(const TargetRegisterClass *RC) const
llvm::TargetRegisterClass
inline
hasSuperClassEq
(const TargetRegisterClass *RC) const
llvm::TargetRegisterClass
inline
isAllocatable
() const
llvm::TargetRegisterClass
inline
isASubClass
() const
llvm::TargetRegisterClass
inline
isBaseClass
() const
llvm::TargetRegisterClass
inline
iterator
typedef
llvm::TargetRegisterClass
LaneMask
llvm::TargetRegisterClass
MC
llvm::TargetRegisterClass
OrderFunc
llvm::TargetRegisterClass
SubClassMask
llvm::TargetRegisterClass
superclasses
() const
llvm::TargetRegisterClass
inline
SuperClasses
llvm::TargetRegisterClass
SuperClassesSize
llvm::TargetRegisterClass
SuperRegIndices
llvm::TargetRegisterClass
TSFlags
llvm::TargetRegisterClass
Generated on Sun Dec 22 2024 08:56:25 for LLVM by
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