27#define DEBUG_TYPE "amdgpu-regbankselect"
30using namespace AMDGPU;
45 return "AMDGPU Register Bank Select";
59 MachineFunctionProperties::Property::RegBankSelected);
66 "AMDGPU Register Bank Select",
false,
false)
73char AMDGPURegBankSelect::
ID = 0;
78 return new AMDGPURegBankSelect();
95 : B(B),
MRI(*B.getMRI()), ILMA(ILMA), MUI(MUI),
96 SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),
97 VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
98 VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {}
123 LLT Ty =
MRI.getType(Reg);
124 Register NewReg =
MRI.createVirtualRegister({RB, Ty});
127 auto &
MBB = *
MI.getParent();
129 B.buildCopy(Reg, NewReg);
142 if (
UseMI.isPreISelOpcode()) {
144 if (
Op.isReg() &&
Op.getReg() == Reg)
159 LLT Ty =
MRI.getType(Reg);
160 Register NewReg =
MRI.createVirtualRegister({RB, Ty});
164 auto DefMI =
MRI.getVRegDef(Reg)->getIterator();
171 B.buildCopy(NewReg, Reg);
181 if (!Reg.isVirtual())
189 MachineFunctionProperties::Property::FailedISel))
195 getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
201 B.setCSEInfo(&CSEInfo);
202 B.setChangeObserver(Observer);
209 getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo();
223 if (!DefReg.
isValid() ||
MRI.getRegClassOrNull(DefReg))
227 MRI.setRegBank(DefReg, *RBSHelper.getRegBankToAssign(DefReg));
231 if (!
MI.isPreISelOpcode())
249 const RegisterBank *RB = RBSHelper.getRegBankToAssign(DefReg);
250 if (
MRI.getRegClassOrNull(DefReg))
251 RBSHelper.reAssignRegBankOnDef(
MI, DefOP, RB);
254 MRI.setRegBank(DefReg, *RB);
267 MRI.getVRegDef(
UseReg)->isPreISelOpcode())
272 RBSHelper.constrainRegBankUse(
MI, UseOP, RB);
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
AMDGPU Register Bank Select
static Register getVReg(MachineOperand &Op)
#define DEBUG_TYPE
Assign register banks to all register operands of G_ instructions using machine uniformity analysis.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Provides analysis for continuously CSEing during GISel passes.
This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.
AMD GCN specific subclass of TargetSubtarget.
static Register UseReg(const MachineOperand &MO)
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target-Independent Code Generator Pass Configuration Options pass.
const RegisterBank * getRegBankToAssign(Register Reg)
RegBankSelectHelper(MachineIRBuilder &B, AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA, const MachineUniformityInfo &MUI, const RegisterBankInfo &RBI)
void reAssignRegBankOnDef(MachineInstr &MI, MachineOperand &DefOP, const RegisterBank *RB)
void constrainRegBankUse(MachineInstr &MI, MachineOperand &UseOP, const RegisterBank *RB)
bool isS32S64LaneMask(Register Reg) const
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
Defines a builder that does CSE of MachineInstructions using GISelCSEInfo.
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
The actual analysis pass wrapper.
Simple wrapper that does the following.
Simple wrapper observer that takes several observers, and calls each one for each event.
void addObserver(GISelChangeObserver *O)
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual MachineFunctionProperties getSetProperties() const
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineFunctionProperties & getProperties() const
Get the function properties.
Helper class to build MachineInstr.
Representation of each machine instruction.
const MachineBasicBlock * getParent() const
MachineOperand class - Representation of each machine instruction operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
A simple RAII based Delegate installer.
A simple RAII based Observer installer.
Holds all the information related to register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
StringRef - Represent a constant reference to a string, i.e.
Target-Independent Code Generator Pass Configuration Options.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
char & AMDGPURegBankSelectID
FunctionPass * createAMDGPURegBankSelectPass()
void initializeAMDGPURegBankSelectPass(PassRegistry &)