84 if (&Subtarget == &NewSubtarget)
87 Names2InstrOpCodes.clear();
89 Names2RegMasks.clear();
90 Names2SubRegIndices.clear();
91 Names2TargetIndices.clear();
92 Names2DirectTargetFlags.clear();
93 Names2BitmaskTargetFlags.clear();
94 Names2MMOTargetFlags.clear();
96 initNames2RegClasses();
100void PerTargetMIParsingState::initNames2Regs() {
101 if (!Names2Regs.empty())
105 Names2Regs.insert(std::make_pair(
"noreg", 0));
107 assert(
TRI &&
"Expected target register info");
109 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
114 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
121 auto RegInfo = Names2Regs.find(
RegName);
122 if (RegInfo == Names2Regs.end())
124 Reg = RegInfo->getValue();
130 const auto *
TRI = Subtarget.getRegisterInfo();
131 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
138void PerTargetMIParsingState::initNames2InstrOpCodes() {
139 if (!Names2InstrOpCodes.
empty())
142 assert(
TII &&
"Expected target instruction info");
143 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
149 initNames2InstrOpCodes();
150 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
151 if (InstrInfo == Names2InstrOpCodes.end())
153 OpCode = InstrInfo->getValue();
157void PerTargetMIParsingState::initNames2RegMasks() {
158 if (!Names2RegMasks.
empty())
161 assert(
TRI &&
"Expected target register info");
165 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
167 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
171 initNames2RegMasks();
172 auto RegMaskInfo = Names2RegMasks.find(Identifier);
173 if (RegMaskInfo == Names2RegMasks.end())
175 return RegMaskInfo->getValue();
178void PerTargetMIParsingState::initNames2SubRegIndices() {
179 if (!Names2SubRegIndices.
empty())
182 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
183 Names2SubRegIndices.
insert(
184 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
188 initNames2SubRegIndices();
189 auto SubRegInfo = Names2SubRegIndices.find(Name);
190 if (SubRegInfo == Names2SubRegIndices.end())
192 return SubRegInfo->getValue();
195void PerTargetMIParsingState::initNames2TargetIndices() {
196 if (!Names2TargetIndices.
empty())
199 assert(
TII &&
"Expected target instruction info");
200 auto Indices =
TII->getSerializableTargetIndices();
201 for (
const auto &
I : Indices)
206 initNames2TargetIndices();
207 auto IndexInfo = Names2TargetIndices.find(Name);
208 if (IndexInfo == Names2TargetIndices.end())
210 Index = IndexInfo->second;
214void PerTargetMIParsingState::initNames2DirectTargetFlags() {
215 if (!Names2DirectTargetFlags.
empty())
219 assert(
TII &&
"Expected target instruction info");
220 auto Flags =
TII->getSerializableDirectMachineOperandTargetFlags();
221 for (
const auto &
I : Flags)
222 Names2DirectTargetFlags.
insert(
228 initNames2DirectTargetFlags();
229 auto FlagInfo = Names2DirectTargetFlags.find(Name);
230 if (FlagInfo == Names2DirectTargetFlags.end())
232 Flag = FlagInfo->second;
236void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
237 if (!Names2BitmaskTargetFlags.
empty())
241 assert(
TII &&
"Expected target instruction info");
242 auto Flags =
TII->getSerializableBitmaskMachineOperandTargetFlags();
243 for (
const auto &
I : Flags)
244 Names2BitmaskTargetFlags.
insert(
250 initNames2BitmaskTargetFlags();
251 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
252 if (FlagInfo == Names2BitmaskTargetFlags.end())
254 Flag = FlagInfo->second;
258void PerTargetMIParsingState::initNames2MMOTargetFlags() {
259 if (!Names2MMOTargetFlags.
empty())
263 assert(
TII &&
"Expected target instruction info");
264 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
265 for (
const auto &
I : Flags)
271 initNames2MMOTargetFlags();
272 auto FlagInfo = Names2MMOTargetFlags.find(Name);
273 if (FlagInfo == Names2MMOTargetFlags.end())
275 Flag = FlagInfo->second;
279void PerTargetMIParsingState::initNames2RegClasses() {
280 if (!Names2RegClasses.
empty())
284 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
285 const auto *RC =
TRI->getRegClass(
I);
291void PerTargetMIParsingState::initNames2RegBanks() {
292 if (!Names2RegBanks.empty())
295 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
303 Names2RegBanks.insert(
304 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
310 auto RegClassInfo = Names2RegClasses.find(Name);
311 if (RegClassInfo == Names2RegClasses.end())
313 return RegClassInfo->getValue();
317 auto RegBankInfo = Names2RegBanks.find(Name);
318 if (RegBankInfo == Names2RegBanks.end())
320 return RegBankInfo->getValue();
333 Info->
VReg =
MRI.createIncompleteVirtualRegister();
334 I.first->second = Info;
336 return *
I.first->second;
345 Info->
VReg =
MF.getRegInfo().createIncompleteVirtualRegister(
RegName);
346 I.first->second = Info;
348 return *
I.first->second;
356 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
364 for (
const auto &Arg :
F.args())
366 for (
const auto &BB :
F) {
368 for (
const auto &
I : BB)
383struct ParsedMachineOperand {
387 std::optional<unsigned> TiedDefIdx;
391 std::optional<unsigned> &TiedDefIdx)
392 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
395 "Only used register operands can be tied");
402 StringRef
Source, CurrentSource;
405 PerFunctionMIParsingState &PFS;
407 DenseMap<unsigned, const BasicBlock *> Slots2BasicBlocks;
410 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
412 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
413 StringRef Source, SMRange SourceRange);
417 void lex(
unsigned SkipChar = 0);
422 bool error(
const Twine &Msg);
430 parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
431 bool parseBasicBlocks();
433 bool parseStandaloneMBB(MachineBasicBlock *&
MBB);
435 bool parseStandaloneVirtualRegister(VRegInfo *&
Info);
437 bool parseStandaloneStackObject(
int &FI);
438 bool parseStandaloneMDNode(MDNode *&Node);
440 bool parseMDTuple(MDNode *&MD,
bool IsDistinct);
441 bool parseMDNodeVector(SmallVectorImpl<Metadata *> &Elts);
445 parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
446 bool parseBasicBlock(MachineBasicBlock &
MBB,
447 MachineBasicBlock *&AddFalthroughFrom);
448 bool parseBasicBlockLiveins(MachineBasicBlock &
MBB);
449 bool parseBasicBlockSuccessors(MachineBasicBlock &
MBB);
452 bool parseVirtualRegister(VRegInfo *&
Info);
453 bool parseNamedVirtualRegister(VRegInfo *&
Info);
454 bool parseRegister(
Register &
Reg, VRegInfo *&VRegInfo);
455 bool parseRegisterFlag(
unsigned &Flags);
456 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
457 bool parseSubRegisterIndex(
unsigned &
SubReg);
458 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
459 bool parseRegisterOperand(MachineOperand &Dest,
460 std::optional<unsigned> &TiedDefIdx,
462 bool parseImmediateOperand(MachineOperand &Dest);
467 bool parseTypedImmediateOperand(MachineOperand &Dest);
468 bool parseFPImmediateOperand(MachineOperand &Dest);
470 bool parseMBBOperand(MachineOperand &Dest);
471 bool parseStackFrameIndex(
int &FI);
472 bool parseStackObjectOperand(MachineOperand &Dest);
473 bool parseFixedStackFrameIndex(
int &FI);
474 bool parseFixedStackObjectOperand(MachineOperand &Dest);
476 bool parseGlobalAddressOperand(MachineOperand &Dest);
477 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
478 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
479 bool parseJumpTableIndexOperand(MachineOperand &Dest);
480 bool parseExternalSymbolOperand(MachineOperand &Dest);
481 bool parseMCSymbolOperand(MachineOperand &Dest);
483 bool parseDIExpression(MDNode *&Expr);
484 bool parseDILocation(MDNode *&Expr);
485 bool parseMetadataOperand(MachineOperand &Dest);
486 bool parseCFIOffset(
int &
Offset);
487 bool parseCFIRegister(
unsigned &
Reg);
489 bool parseCFIEscapeValues(std::string& Values);
490 bool parseCFIOperand(MachineOperand &Dest);
491 bool parseIRBlock(BasicBlock *&BB,
const Function &
F);
492 bool parseBlockAddressOperand(MachineOperand &Dest);
493 bool parseIntrinsicOperand(MachineOperand &Dest);
494 bool parsePredicateOperand(MachineOperand &Dest);
495 bool parseShuffleMaskOperand(MachineOperand &Dest);
496 bool parseTargetIndexOperand(MachineOperand &Dest);
497 bool parseDbgInstrRefOperand(MachineOperand &Dest);
498 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
499 bool parseLaneMaskOperand(MachineOperand &Dest);
500 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
501 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
502 MachineOperand &Dest,
503 std::optional<unsigned> &TiedDefIdx);
504 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
505 const unsigned OpIdx,
506 MachineOperand &Dest,
507 std::optional<unsigned> &TiedDefIdx);
508 bool parseOffset(int64_t &
Offset);
509 bool parseIRBlockAddressTaken(BasicBlock *&BB);
511 bool parseAddrspace(
unsigned &Addrspace);
512 bool parseSectionID(std::optional<MBBSectionID> &SID);
513 bool parseBBID(std::optional<UniqueBBID> &BBID);
514 bool parseCallFrameSize(
unsigned &CallFrameSize);
515 bool parseOperandsOffset(MachineOperand &
Op);
518 bool parseMemoryPseudoSourceValue(
const PseudoSourceValue *&PSV);
519 bool parseMachinePointerInfo(MachinePointerInfo &Dest);
522 bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
523 bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol);
524 bool parseHeapAllocMarker(MDNode *&Node);
525 bool parsePCSections(MDNode *&Node);
527 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
528 MachineOperand &Dest,
const MIRFormatter &MF);
539 bool getUint64(uint64_t &Result);
555 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
557 bool assignRegisterTies(MachineInstr &
MI,
561 const MCInstrDesc &MCID);
564 const BasicBlock *getIRBlock(
unsigned Slot,
const Function &
F);
567 MCSymbol *getOrCreateMCSymbol(StringRef Name);
571 bool parseStringConstant(std::string &Result);
588 SourceRange(SourceRange), PFS(PFS) {}
590void MIParser::lex(
unsigned SkipChar) {
592 CurrentSource.substr(SkipChar), Token,
596bool MIParser::error(
const Twine &Msg) {
return error(Token.location(), Msg); }
616 assert(SourceRange.isValid() &&
"Invalid source range");
638 return "<unknown token>";
643 if (Token.isNot(TokenKind))
650 if (Token.isNot(TokenKind))
657bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
663 return error(
"Unknown Section ID");
666 const StringRef &S = Token.stringValue();
667 if (S ==
"Exception")
669 else if (S ==
"Cold")
672 return error(
"Unknown Section ID");
679bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
683 unsigned CloneID = 0;
685 return error(
"Unknown BB ID");
689 return error(
"Unknown Clone ID");
692 BBID = {BaseID, CloneID};
697bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
702 return error(
"Unknown call frame size");
703 CallFrameSize =
Value;
708bool MIParser::parseBasicBlockDefinition(
714 auto Loc = Token.location();
715 auto Name = Token.stringValue();
717 bool MachineBlockAddressTaken =
false;
719 bool IsLandingPad =
false;
720 bool IsInlineAsmBrIndirectTarget =
false;
721 bool IsEHFuncletEntry =
false;
722 bool IsEHScopeEntry =
false;
723 std::optional<MBBSectionID> SectionID;
724 uint64_t Alignment = 0;
725 std::optional<UniqueBBID> BBID;
726 unsigned CallFrameSize = 0;
731 switch (Token.kind()) {
733 MachineBlockAddressTaken =
true;
737 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
745 IsInlineAsmBrIndirectTarget =
true;
749 IsEHFuncletEntry =
true;
753 IsEHScopeEntry =
true;
763 if (parseIRBlock(BB, MF.getFunction()))
768 if (parseSectionID(SectionID))
776 if (parseCallFrameSize(CallFrameSize))
791 MF.getFunction().getValueSymbolTable()->lookup(Name));
794 "' is not defined in the function '" +
797 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
799 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
801 return error(
Loc,
Twine(
"redefinition of machine basic block with id #") +
805 if (MachineBlockAddressTaken)
807 if (AddressTakenIRBlock)
821bool MIParser::parseBasicBlockDefinitions(
827 if (Token.isErrorOrEOF())
828 return Token.isError();
830 return error(
"expected a basic block definition before instructions");
831 unsigned BraceDepth = 0;
833 if (parseBasicBlockDefinition(MBBSlots))
835 bool IsAfterNewline =
false;
839 Token.isErrorOrEOF())
842 return error(
"basic block definition should be located at the start of "
845 IsAfterNewline =
true;
848 IsAfterNewline =
false;
853 return error(
"extraneous closing brace ('}')");
859 if (!Token.isError() && BraceDepth)
860 return error(
"expected '}'");
861 }
while (!Token.isErrorOrEOF());
862 return Token.isError();
870 if (Token.isNewlineOrEOF())
874 return error(
"expected a named register");
876 if (parseNamedRegister(
Reg))
884 return error(
"expected a lane mask");
886 "Use correct get-function for lane mask");
889 return error(
"invalid lane mask value");
903 if (Token.isNewlineOrEOF())
907 return error(
"expected a machine basic block reference");
916 return error(
"expected an integer literal after '('");
950 bool ExplicitSuccessors =
false;
953 if (parseBasicBlockSuccessors(
MBB))
955 ExplicitSuccessors =
true;
957 if (parseBasicBlockLiveins(
MBB))
963 if (!Token.isNewlineOrEOF())
964 return error(
"expected line break at the end of a list");
969 bool IsInBundle =
false;
993 return error(
"nested instruction bundles are not allowed");
1002 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1007 if (!ExplicitSuccessors) {
1014 if (IsFallthrough) {
1015 AddFalthroughFrom = &
MBB;
1024bool MIParser::parseBasicBlocks() {
1029 if (Token.isErrorOrEOF())
1030 return Token.isError();
1039 if (AddFalthroughFrom) {
1043 AddFalthroughFrom =
nullptr;
1045 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1058 while (Token.isRegister() || Token.isRegisterFlag()) {
1059 auto Loc = Token.location();
1060 std::optional<unsigned> TiedDefIdx;
1061 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1064 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1073 if (Token.isError() || parseInstruction(OpCode, Flags))
1086 auto Loc = Token.location();
1087 std::optional<unsigned> TiedDefIdx;
1088 if (parseMachineOperandAndTargetFlags(OpCode, Operands.
size(), MO, TiedDefIdx))
1091 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1096 return error(
"expected ',' before the next machine operand");
1100 MCSymbol *PreInstrSymbol =
nullptr;
1102 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1104 MCSymbol *PostInstrSymbol =
nullptr;
1106 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1108 MDNode *HeapAllocMarker =
nullptr;
1110 if (parseHeapAllocMarker(HeapAllocMarker))
1112 MDNode *PCSections =
nullptr;
1114 if (parsePCSections(PCSections))
1117 unsigned CFIType = 0;
1121 return error(
"expected an integer literal after 'cfi-type'");
1139 unsigned InstrNum = 0;
1143 return error(
"expected an integer literal after 'debug-instr-number'");
1160 if (parseDILocation(Node))
1163 return error(
"expected a metadata node after 'debug-location'");
1165 return error(
"referenced metadata is not a DILocation");
1173 while (!Token.isNewlineOrEOF()) {
1175 if (parseMachineMemoryOperand(
MemOp))
1178 if (Token.isNewlineOrEOF())
1183 return error(
"expected ',' before the next machine memory operand");
1188 const auto &
MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1189 if (!
MCID.isVariadic()) {
1191 if (verifyImplicitOperands(Operands,
MCID))
1195 MI = MF.CreateMachineInstr(
MCID, DebugLocation,
true);
1196 MI->setFlags(Flags);
1200 for (
const auto &Operand : Operands)
1201 MI->addOperand(MF, Operand.Operand);
1203 if (assignRegisterTies(*
MI, Operands))
1206 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1207 if (PostInstrSymbol)
1208 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1209 if (HeapAllocMarker)
1210 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1212 MI->setPCSections(MF, PCSections);
1214 MI->setCFIType(MF, CFIType);
1216 MI->setDeactivationSymbol(MF, DS);
1217 if (!MemOperands.
empty())
1218 MI->setMemRefs(MF, MemOperands);
1220 MI->setDebugInstrNum(InstrNum);
1227 return error(
"expected a machine basic block reference");
1233 "expected end of string after the machine basic block reference");
1237bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1240 return error(
"expected a named register");
1241 if (parseNamedRegister(
Reg))
1245 return error(
"expected end of string after the register reference");
1249bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&
Info) {
1252 return error(
"expected a virtual register");
1253 if (parseVirtualRegister(
Info))
1257 return error(
"expected end of string after the register reference");
1261bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1265 return error(
"expected either a named or virtual register");
1273 return error(
"expected end of string after the register reference");
1277bool MIParser::parseStandaloneStackObject(
int &FI) {
1280 return error(
"expected a stack object");
1281 if (parseStackFrameIndex(FI))
1284 return error(
"expected end of string after the stack object reference");
1288bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1294 if (parseDIExpression(Node))
1297 if (parseDILocation(Node))
1300 return error(
"expected a metadata node");
1302 return error(
"expected end of string after the metadata node");
1306bool MIParser::parseMachineMetadata() {
1309 return error(
"expected a metadata node");
1313 return error(
"expected metadata id after '!'");
1324 return error(
"expected a metadata node");
1328 if (parseMDTuple(MD, IsDistinct))
1331 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1332 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1333 FI->second.first->replaceAllUsesWith(MD);
1334 PFS.MachineForwardRefMDNodes.erase(FI);
1336 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1338 auto [It,
Inserted] = PFS.MachineMetadataNodes.try_emplace(
ID);
1340 return error(
"Metadata id is already used");
1341 It->second.reset(MD);
1347bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1349 if (parseMDNodeVector(Elts))
1358 return error(
"expected '{' here");
1379 return error(
"expected end of metadata node");
1387bool MIParser::parseMetadata(
Metadata *&MD) {
1389 return error(
"expected '!' here");
1394 if (parseStringConstant(Str))
1401 return error(
"expected metadata id after '!'");
1403 SMLoc Loc = mapSMLoc(Token.location());
1410 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1411 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1412 MD = NodeInfo->second.get();
1416 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1417 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1418 MD = NodeInfo->second.get();
1422 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1423 FwdRef = std::make_pair(
1425 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1426 MD = FwdRef.first.get();
1433 return MO.
isDef() ?
"implicit-def" :
"implicit";
1438 assert(
Reg.isPhysical() &&
"expected phys reg");
1445 for (
const auto &
I : Operands) {
1466 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1467 assert(
TRI &&
"Expected target register info");
1468 for (
const auto &
I : ImplicitOperands) {
1471 return error(Operands.
empty() ? Token.location() : Operands.
back().End,
1472 Twine(
"missing implicit register operand '") +
1479bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1548 return error(
"expected a machine instruction");
1549 StringRef InstrName = Token.stringValue();
1550 if (PFS.Target.parseInstrName(InstrName, OpCode))
1551 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1559 if (PFS.Target.getRegisterByName(Name,
Reg))
1560 return error(
Twine(
"unknown register name '") + Name +
"'");
1564bool MIParser::parseNamedVirtualRegister(
VRegInfo *&
Info) {
1569 Info = &PFS.getVRegInfoNamed(Name);
1575 return parseNamedVirtualRegister(
Info);
1580 Info = &PFS.getVRegInfo(
ID);
1585 switch (Token.kind()) {
1590 return parseNamedRegister(
Reg);
1593 if (parseVirtualRegister(
Info))
1603bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1605 return error(
"expected '_', register class, or register bank name");
1614 switch (RegInfo.
Kind) {
1620 return error(
Loc,
Twine(
"conflicting register classes, previously: ") +
1629 return error(
Loc,
"register class specification on generic register");
1637 RegBank = PFS.Target.getRegBank(Name);
1639 return error(
Loc,
"expected '_', register class, or register bank name");
1644 switch (RegInfo.
Kind) {
1650 return error(
Loc,
"conflicting generic register banks");
1656 return error(
Loc,
"register bank specification on normal register");
1661bool MIParser::parseRegisterFlag(
unsigned &Flags) {
1662 const unsigned OldFlags =
Flags;
1663 switch (Token.kind()) {
1697 if (OldFlags == Flags)
1700 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1705bool MIParser::parseSubRegisterIndex(
unsigned &
SubReg) {
1709 return error(
"expected a subregister index after '.'");
1710 auto Name = Token.stringValue();
1711 SubReg = PFS.Target.getSubRegIndex(Name);
1713 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
1718bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1722 return error(
"expected an integer literal after 'tied-def'");
1734 for (
unsigned I = 0,
E = Operands.
size();
I !=
E; ++
I) {
1735 if (!Operands[
I].TiedDefIdx)
1739 unsigned DefIdx = *Operands[
I].TiedDefIdx;
1741 return error(Operands[
I].Begin,
1742 Twine(
"use of invalid tied-def operand index '" +
1743 Twine(DefIdx) +
"'; instruction has only ") +
1745 const auto &DefOperand = Operands[DefIdx].Operand;
1746 if (!DefOperand.isReg() || !DefOperand.isDef())
1748 return error(Operands[
I].Begin,
1749 Twine(
"use of invalid tied-def operand index '") +
1750 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1751 " isn't a defined register");
1753 for (
const auto &TiedPair : TiedRegisterPairs) {
1754 if (TiedPair.first == DefIdx)
1755 return error(Operands[
I].Begin,
1756 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1757 " is already tied with another register operand");
1759 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1763 for (
const auto &TiedPair : TiedRegisterPairs)
1764 MI.tieOperands(TiedPair.first, TiedPair.second);
1769 std::optional<unsigned> &TiedDefIdx,
1772 while (Token.isRegisterFlag()) {
1773 if (parseRegisterFlag(Flags))
1776 if (!Token.isRegister())
1777 return error(
"expected a register after register flags");
1780 if (parseRegister(
Reg, RegInfo))
1785 if (parseSubRegisterIndex(
SubReg))
1788 return error(
"subregister index expects a virtual register");
1792 return error(
"register class specification expects a virtual register");
1794 if (parseRegisterClassOrBank(*RegInfo))
1801 if (!parseRegisterTiedDefIndex(Idx))
1806 if (parseLowLevelType(Token.location(), Ty))
1807 return error(
"expected tied-def or low-level type after '('");
1812 if (
MRI.getType(
Reg).isValid() &&
MRI.getType(
Reg) != Ty)
1813 return error(
"inconsistent type for generic virtual register");
1817 MRI.noteNewVirtualRegister(
Reg);
1823 return error(
"unexpected type on physical register");
1826 if (parseLowLevelType(Token.location(), Ty))
1832 if (
MRI.getType(
Reg).isValid() &&
MRI.getType(
Reg) != Ty)
1833 return error(
"inconsistent type for generic virtual register");
1843 return error(
"generic virtual registers must have a type");
1848 return error(
"cannot have a killed def operand");
1851 return error(
"cannot have a dead use operand");
1869 const APSInt &
Int = Token.integerValue();
1870 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1872 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1875 return error(
"integer literal is too large to be an immediate operand");
1880bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1881 const unsigned OpIdx,
1885 auto Loc = Token.location();
1891 Len += Token.range().size();
1900 Src =
StringRef(
Loc, Len + Token.stringValue().size());
1905 ->
bool { return error(Loc, Msg); }))
1917 auto Source = StringValue.
str();
1922 return ErrCB(
Loc + Err.getColumnNo(), Err.getMessage());
1928 return ::parseIRConstant(
1929 Loc, StringValue, PFS,
C,
1956 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
1959 return error(
"expected integers after 's'/'p' type character");
1962 if (Token.range().front() ==
's') {
1966 return error(
"invalid size for scalar type");
1973 }
else if (Token.range().front() ==
'p') {
1977 return error(
"invalid address space number");
1986 return error(
Loc,
"expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, "
1987 "or <vscale x M x pA> for GlobalISel type");
1995 return error(
"expected <vscale x M x sN> or <vscale x M x pA>");
1999 auto GetError = [
this, &HasVScale,
Loc]() {
2002 Loc,
"expected <vscale x M x sN> or <vscale M x pA> for vector type");
2003 return error(
Loc,
"expected <M x sN> or <M x pA> for vector type");
2008 uint64_t NumElements = Token.integerValue().getZExtValue();
2010 return error(
"invalid number of vector elements");
2018 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
2023 return error(
"expected integers after 's'/'p' type character");
2025 if (Token.range().front() ==
's') {
2028 return error(
"invalid size for scalar element in vector");
2030 }
else if (Token.range().front() ==
'p') {
2034 return error(
"invalid address space number");
2053 if (TypeStr.
front() !=
'i' && TypeStr.
front() !=
's' &&
2054 TypeStr.
front() !=
'p')
2056 "a typed immediate operand should start with one of 'i', 's', or 'p'");
2059 return error(
"expected integers after 'i'/'s'/'p' type character");
2061 auto Loc = Token.location();
2065 !(Token.range() ==
"true" || Token.range() ==
"false"))
2066 return error(
"expected an integer literal");
2076 auto Loc = Token.location();
2080 return error(
"expected a floating point literal");
2091 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2093 if (!isxdigit(S[2]))
2096 APInt A(V.size()*4, V, 16);
2100 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2111 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2119 if (
A.getBitWidth() > 32)
2120 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2121 Result =
A.getZExtValue();
2127bool MIParser::getUnsigned(
unsigned &Result) {
2128 return ::getUnsigned(
2140 auto MBBInfo = PFS.MBBSlots.find(
Number);
2141 if (MBBInfo == PFS.MBBSlots.end())
2142 return error(
Twine(
"use of undefined machine basic block #") +
2144 MBB = MBBInfo->second;
2147 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2149 " isn't '" + Token.stringValue() +
"'");
2162bool MIParser::parseStackFrameIndex(
int &FI) {
2167 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2168 if (ObjectInfo == PFS.StackObjectSlots.end())
2172 if (
const auto *Alloca =
2173 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2174 Name = Alloca->getName();
2175 if (!Token.stringValue().empty() && Token.stringValue() != Name)
2177 "' isn't '" + Token.stringValue() +
"'");
2179 FI = ObjectInfo->second;
2185 if (parseStackFrameIndex(FI))
2191bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2196 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2197 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2198 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2201 FI = ObjectInfo->second;
2205bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2207 if (parseFixedStackFrameIndex(FI))
2216 switch (Token.
kind()) {
2221 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2222 Token.
range() +
"'");
2231 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2232 Twine(GVIdx) +
"'");
2241bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2242 return ::parseGlobalValue(
2255 if (parseOperandsOffset(Dest))
2260bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2267 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2270 if (parseOperandsOffset(Dest))
2280 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2281 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2282 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2290 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2293 if (parseOperandsOffset(Dest))
2303 if (parseOperandsOffset(Dest))
2308bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2311 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2312 if (SubRegIndex == 0)
2313 return error(
Twine(
"unknown subregister index '") + Name +
"'");
2319bool MIParser::parseMDNode(
MDNode *&Node) {
2322 auto Loc = Token.location();
2325 return error(
"expected metadata id after '!'");
2329 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2330 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2331 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2332 if (NodeInfo == PFS.MachineMetadataNodes.end())
2336 Node = NodeInfo->second.get();
2340bool MIParser::parseDIExpression(
MDNode *&Expr) {
2343 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2345 CurrentSource = CurrentSource.substr(
Read);
2352bool MIParser::parseDILocation(
MDNode *&
Loc) {
2356 bool HaveLine =
false;
2358 unsigned Column = 0;
2360 MDNode *InlinedAt =
nullptr;
2361 bool ImplicitCode =
false;
2362 uint64_t AtomGroup = 0;
2363 uint64_t AtomRank = 0;
2371 if (Token.stringValue() ==
"line") {
2376 Token.integerValue().isSigned())
2377 return error(
"expected unsigned integer");
2378 Line = Token.integerValue().getZExtValue();
2383 if (Token.stringValue() ==
"column") {
2388 Token.integerValue().isSigned())
2389 return error(
"expected unsigned integer");
2390 Column = Token.integerValue().getZExtValue();
2394 if (Token.stringValue() ==
"scope") {
2399 return error(
"expected metadata node");
2401 return error(
"expected DIScope node");
2404 if (Token.stringValue() ==
"inlinedAt") {
2412 if (parseDILocation(InlinedAt))
2415 return error(
"expected metadata node");
2417 return error(
"expected DILocation node");
2420 if (Token.stringValue() ==
"isImplicitCode") {
2425 return error(
"expected true/false");
2429 if (Token.stringValue() ==
"true")
2430 ImplicitCode =
true;
2431 else if (Token.stringValue() ==
"false")
2432 ImplicitCode =
false;
2434 return error(
"expected true/false");
2438 if (Token.stringValue() ==
"atomGroup") {
2443 Token.integerValue().isSigned())
2444 return error(
"expected unsigned integer");
2445 AtomGroup = Token.integerValue().getZExtValue();
2449 if (Token.stringValue() ==
"atomRank") {
2454 Token.integerValue().isSigned())
2455 return error(
"expected unsigned integer");
2456 AtomRank = Token.integerValue().getZExtValue();
2461 return error(
Twine(
"invalid DILocation argument '") +
2462 Token.stringValue() +
"'");
2470 return error(
"DILocation requires line number");
2472 return error(
"DILocation requires a scope");
2475 InlinedAt, ImplicitCode, AtomGroup, AtomRank);
2485 if (parseDIExpression(Node))
2492bool MIParser::parseCFIOffset(
int &
Offset) {
2494 return error(
"expected a cfi offset");
2495 if (Token.integerValue().getSignificantBits() > 32)
2496 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2497 Offset = (int)Token.integerValue().getExtValue();
2502bool MIParser::parseCFIRegister(
unsigned &
Reg) {
2504 return error(
"expected a cfi register");
2506 if (parseNamedRegister(LLVMReg))
2508 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2509 assert(
TRI &&
"Expected target register info");
2510 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2512 return error(
"invalid DWARF register");
2513 Reg = (unsigned)DwarfReg;
2518bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2520 return error(
"expected a cfi address space literal");
2521 if (Token.integerValue().isSigned())
2522 return error(
"expected an unsigned integer (cfi address space)");
2528bool MIParser::parseCFIEscapeValues(std::string &Values) {
2531 return error(
"expected a hexadecimal literal");
2535 if (
Value > UINT8_MAX)
2536 return error(
"expected a 8-bit integer (too large)");
2537 Values.push_back(
static_cast<uint8_t
>(
Value));
2544 auto Kind = Token.kind();
2552 if (parseCFIRegister(
Reg))
2567 CFIIndex = MF.addFrameInst(
2571 if (parseCFIRegister(
Reg))
2577 if (parseCFIOffset(
Offset))
2583 if (parseCFIOffset(
Offset))
2585 CFIIndex = MF.addFrameInst(
2607 if (parseCFIRegister(
Reg))
2615 if (parseCFIRegister(
Reg))
2622 parseCFIRegister(Reg2))
2641 if (parseCFIEscapeValues(Values))
2655 switch (Token.kind()) {
2658 F.getValueSymbolTable()->lookup(Token.stringValue()));
2660 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2664 unsigned SlotNumber = 0;
2667 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2669 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2670 Twine(SlotNumber) +
"'");
2686 return error(
"expected a global value");
2692 return error(
"expected an IR function reference");
2698 return error(
"expected an IR block reference");
2699 if (parseIRBlock(BB, *
F))
2705 if (parseOperandsOffset(Dest))
2714 return error(
"expected syntax intrinsic(@llvm.whatever)");
2717 return error(
"expected syntax intrinsic(@llvm.whatever)");
2719 std::string
Name = std::string(Token.stringValue());
2723 return error(
"expected ')' to terminate intrinsic name");
2728 return error(
"unknown intrinsic name");
2740 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2743 return error(
"whatever");
2766 return error(
"invalid floating-point predicate");
2781 return error(
"invalid integer predicate");
2787 return error(
"predicate should be terminated by ')'.");
2797 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
2804 const APSInt &
Int = Token.integerValue();
2807 return error(
"expected integer constant");
2813 return error(
"shufflemask should be terminated by ')'.");
2815 if (ShufMask.
size() < 2)
2816 return error(
"shufflemask should have > 1 element");
2828 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2831 return error(
"expected unsigned integer for instruction index");
2832 uint64_t InstrIdx = Token.integerValue().getZExtValue();
2833 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
2834 "Instruction reference's instruction index is too large");
2838 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2841 return error(
"expected unsigned integer for operand index");
2842 uint64_t
OpIdx = Token.integerValue().getZExtValue();
2843 assert(
OpIdx <= std::numeric_limits<unsigned>::max() &&
2844 "Instruction reference's operand index is too large");
2848 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2860 return error(
"expected the name of the target index");
2862 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
2863 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
2868 if (parseOperandsOffset(Dest))
2873bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
2874 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
2879 uint32_t *
Mask = MF.allocateRegMask();
2883 return error(
"expected a named register");
2885 if (parseNamedRegister(
Reg))
2909 return error(
"expected a valid lane mask value");
2911 "Use correct get-function for lane mask.");
2925bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
2927 uint32_t *
Mask = MF.allocateRegMask();
2933 return error(
"expected a named register");
2935 if (parseNamedRegister(
Reg))
2950bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
2952 std::optional<unsigned> &TiedDefIdx) {
2953 switch (Token.kind()) {
2968 return parseRegisterOperand(Dest, TiedDefIdx);
2970 return parseImmediateOperand(Dest);
2978 return parseFPImmediateOperand(Dest);
2980 return parseMBBOperand(Dest);
2982 return parseStackObjectOperand(Dest);
2984 return parseFixedStackObjectOperand(Dest);
2987 return parseGlobalAddressOperand(Dest);
2989 return parseConstantPoolIndexOperand(Dest);
2991 return parseJumpTableIndexOperand(Dest);
2993 return parseExternalSymbolOperand(Dest);
2995 return parseMCSymbolOperand(Dest);
2997 return parseSubRegisterIndexOperand(Dest);
3000 return parseMetadataOperand(Dest);
3018 return parseCFIOperand(Dest);
3020 return parseBlockAddressOperand(Dest);
3022 return parseIntrinsicOperand(Dest);
3024 return parseTargetIndexOperand(Dest);
3026 return parseLaneMaskOperand(Dest);
3028 return parseLiveoutRegisterMaskOperand(Dest);
3031 return parsePredicateOperand(Dest);
3033 return parseShuffleMaskOperand(Dest);
3035 return parseDbgInstrRefOperand(Dest);
3039 if (
const auto *RegMask = PFS.Target.getRegMask(Token.stringValue())) {
3043 }
else if (Token.stringValue() ==
"CustomRegMask") {
3044 return parseCustomRegisterMaskOperand(Dest);
3046 return parseTypedImmediateOperand(Dest);
3048 const auto *
TII = MF.getSubtarget().getInstrInfo();
3049 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3050 return parseTargetImmMnemonic(OpCode,
OpIdx, Dest, *Formatter);
3056 return error(
"expected a machine operand");
3061bool MIParser::parseMachineOperandAndTargetFlags(
3063 std::optional<unsigned> &TiedDefIdx) {
3065 bool HasTargetFlags =
false;
3067 HasTargetFlags =
true;
3072 return error(
"expected the name of the target flag");
3073 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
3074 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
3075 return error(
"use of undefined target flag '" + Token.stringValue() +
3082 return error(
"expected the name of the target flag");
3083 unsigned BitFlag = 0;
3084 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3085 return error(
"use of undefined target flag '" + Token.stringValue() +
3094 auto Loc = Token.location();
3095 if (parseMachineOperand(OpCode,
OpIdx, Dest, TiedDefIdx))
3097 if (!HasTargetFlags)
3100 return error(
Loc,
"register operands can't have target flags");
3105bool MIParser::parseOffset(int64_t &
Offset) {
3112 return error(
"expected an integer literal after '" + Sign +
"'");
3113 if (Token.integerValue().getSignificantBits() > 64)
3114 return error(
"expected 64-bit integer (too large)");
3115 Offset = Token.integerValue().getExtValue();
3122bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3126 return error(
"expected basic block after 'ir_block_address_taken'");
3128 if (parseIRBlock(BB, MF.getFunction()))
3135bool MIParser::parseAlignment(uint64_t &Alignment) {
3139 return error(
"expected an integer literal after 'align'");
3140 if (getUint64(Alignment))
3145 return error(
"expected a power-of-2 literal after 'align'");
3150bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3154 return error(
"expected an integer literal after 'addrspace'");
3171 switch (Token.
kind()) {
3177 unsigned SlotNumber = 0;
3205 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3209bool MIParser::parseIRValue(
const Value *&V) {
3210 return ::parseIRValue(
3216bool MIParser::getUint64(uint64_t &Result) {
3217 if (Token.hasIntegerValue()) {
3218 if (Token.integerValue().getActiveBits() > 64)
3219 return error(
"expected 64-bit integer (too large)");
3220 Result = Token.integerValue().getZExtValue();
3227 if (
A.getBitWidth() > 64)
3228 return error(
"expected 64-bit integer (too large)");
3235bool MIParser::getHexUint(
APInt &Result) {
3236 return ::getHexUint(Token, Result);
3240 const auto OldFlags =
Flags;
3241 switch (Token.kind()) {
3256 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3257 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3265 if (OldFlags == Flags)
3268 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3274 switch (Token.kind()) {
3276 PSV = MF.getPSVManager().getStack();
3279 PSV = MF.getPSVManager().getGOT();
3282 PSV = MF.getPSVManager().getJumpTable();
3285 PSV = MF.getPSVManager().getConstantPool();
3289 if (parseFixedStackFrameIndex(FI))
3291 PSV = MF.getPSVManager().getFixedStack(FI);
3297 if (parseStackFrameIndex(FI))
3299 PSV = MF.getPSVManager().getFixedStack(FI);
3305 switch (Token.kind()) {
3311 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3315 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3316 MF.createExternalSymbolName(Token.stringValue()));
3320 "expected a global value or an external symbol after 'call-entry'");
3325 const auto *
TII = MF.getSubtarget().getInstrInfo();
3326 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3327 if (Formatter->parseCustomPseudoSourceValue(
3328 Token.stringValue(), MF, PFS, PSV,
3330 return error(Loc, Msg);
3334 return error(
"unable to parse target custom pseudo source value");
3350 if (parseMemoryPseudoSourceValue(PSV))
3363 return error(
"expected an IR value reference");
3364 const Value *
V =
nullptr;
3367 if (V && !
V->getType()->isPointerTy())
3368 return error(
"expected a pointer IR value");
3383 return error(
"expected '(' in syncscope");
3386 if (parseStringConstant(SSN))
3389 SSID =
Context.getOrInsertSyncScopeID(SSN);
3391 return error(
"expected ')' in syncscope");
3397bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3416 return error(
"expected an atomic scope, ordering or a size specification");
3423 while (Token.isMemoryOperandFlag()) {
3424 if (parseMemoryOperandFlag(Flags))
3428 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3429 return error(
"expected 'load' or 'store' memory operation");
3430 if (Token.stringValue() ==
"load")
3444 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3449 if (parseOptionalAtomicOrdering(Order))
3452 if (parseOptionalAtomicOrdering(FailureOrder))
3458 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3459 "memory operation");
3464 if (getUint64(
Size))
3475 if (parseLowLevelType(Token.location(), MemoryType))
3488 if (Token.stringValue() != Word)
3489 return error(
Twine(
"expected '") + Word +
"'");
3492 if (parseMachinePointerInfo(Ptr))
3495 uint64_t BaseAlignment =
3502 switch (Token.kind()) {
3508 if (Ptr.
Offset & (Alignment - 1)) {
3513 return error(
"specified alignment is more aligned than offset");
3515 BaseAlignment = Alignment;
3554 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3555 "'!noalias' or '!range' or '!noalias.addrspace'");
3560 Dest = MF.getMachineMemOperand(Ptr, Flags, MemoryType,
Align(BaseAlignment),
3561 AAInfo,
Range, SSID, Order, FailureOrder);
3565bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3568 "Invalid token for a pre- post-instruction symbol!");
3571 return error(
"expected a symbol after 'pre-instr-symbol'");
3572 Symbol = getOrCreateMCSymbol(Token.stringValue());
3578 return error(
"expected ',' before the next machine operand");
3583bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3585 "Invalid token for a heap alloc marker!");
3590 return error(
"expected a MDNode after 'heap-alloc-marker'");
3595 return error(
"expected ',' before the next machine operand");
3600bool MIParser::parsePCSections(
MDNode *&Node) {
3602 "Invalid token for a PC sections!");
3607 return error(
"expected a MDNode after 'pcsections'");
3612 return error(
"expected ',' before the next machine operand");
3622 for (
const auto &BB :
F) {
3628 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3635 return Slots2BasicBlocks.
lookup(Slot);
3638const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3639 if (Slots2BasicBlocks.empty())
3645 if (&
F == &MF.getFunction())
3646 return getIRBlock(Slot);
3658 return MF.getContext().getOrCreateSymbol(Name);
3661bool MIParser::parseStringConstant(std::string &Result) {
3663 return error(
"expected string constant");
3664 Result = std::string(Token.stringValue());
3672 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3677 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3683 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3689 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3695 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3701 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(Info);
3707 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3712 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(
Node);
3717 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
3725 ErrorCallback(
Loc, Msg);
3729 return ::parseIRValue(Token, PFS, V, ErrorCallback);
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
static llvm::Error parse(DataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static bool verifyVectorElementCount(uint64_t NumElts)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
MachineInstr unsigned OpIdx
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & back() const
back - Get the last element.
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
LLVM Basic Block Representation.
static LLVM_ABI BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
static bool isFPPredicate(Predicate P)
static bool isIntPredicate(Predicate P)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static LLVM_ABI MDString * get(LLVMContext &Context, StringRef Str)
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setAlignment(Align A)
Set alignment of the basic block.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
static MachineOperand CreateLaneMask(LaneBitmask LaneMask)
LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
Represents a range in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
unsigned getMainFileID() const
const MemoryBuffer * getMemoryBuffer(unsigned i) const
LLVM_ABI SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges={}, ArrayRef< SMFixIt > FixIts={}) const
Return an SMDiagnostic at the specified location with the specified string.
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
LLVM_ABI std::string lower() const
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM_ABI std::string str() const
Return the twine contents as a std::string.
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ BasicBlock
Various leaf nodes.
LLVM_ABI ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Debug
Register 'use' is for debugging purpose.
@ Renamable
Register that may be renamed.
@ Define
Register definition.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ System
Synchronized with respect to all concurrently executing threads.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
constexpr bool hasRegState(unsigned Value, unsigned Test)
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
LLVM_ABI void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
auto dyn_cast_or_null(const Y &Val)
LLVM_ABI DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
constexpr unsigned getDefRegState(bool B)
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
LLVM_ABI Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAliasAddrSpace
The tag specifying the noalias address spaces.
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
LLVM_ABI static const MBBSectionID ExceptionSectionID
LLVM_ABI static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_inlineasm_br_indirect_target
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
PerTargetMIParsingState & Target
DenseMap< Register, VRegInfo * > VRegInfos
VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues
const RegisterBank * RegBank
union llvm::VRegInfo::@127225073067155374133234315364317264041071000132 D
const TargetRegisterClass * RC
enum llvm::VRegInfo::@374354327266250320012227113300214031244227062232 Kind
bool Explicit
VReg was explicitly specified in the .mir file.