LLVM 20.0.0git
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This is the complete list of members for llvm::HexagonEvaluator, including all inherited members.
BranchTargetList typedef | llvm::HexagonEvaluator | |
CellMapType typedef | llvm::HexagonEvaluator | |
composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override | llvm::HexagonEvaluator | virtual |
eADD(const RegisterCell &A1, const RegisterCell &A2) const | llvm::BitTracker::MachineEvaluator | |
eAND(const RegisterCell &A1, const RegisterCell &A2) const | llvm::BitTracker::MachineEvaluator | |
eASL(const RegisterCell &A1, uint16_t Sh) const | llvm::BitTracker::MachineEvaluator | |
eASR(const RegisterCell &A1, uint16_t Sh) const | llvm::BitTracker::MachineEvaluator | |
eCLB(const RegisterCell &A1, bool B, uint16_t W) const | llvm::BitTracker::MachineEvaluator | |
eCLR(const RegisterCell &A1, uint16_t BitN) const | llvm::BitTracker::MachineEvaluator | |
eCTB(const RegisterCell &A1, bool B, uint16_t W) const | llvm::BitTracker::MachineEvaluator | |
eIMM(int64_t V, uint16_t W) const | llvm::BitTracker::MachineEvaluator | |
eIMM(const ConstantInt *CI) const | llvm::BitTracker::MachineEvaluator | |
eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const | llvm::BitTracker::MachineEvaluator | |
eLSR(const RegisterCell &A1, uint16_t Sh) const | llvm::BitTracker::MachineEvaluator | |
eMLS(const RegisterCell &A1, const RegisterCell &A2) const | llvm::BitTracker::MachineEvaluator | |
eMLU(const RegisterCell &A1, const RegisterCell &A2) const | llvm::BitTracker::MachineEvaluator | |
eNOT(const RegisterCell &A1) const | llvm::BitTracker::MachineEvaluator | |
eORL(const RegisterCell &A1, const RegisterCell &A2) const | llvm::BitTracker::MachineEvaluator | |
eSET(const RegisterCell &A1, uint16_t BitN) const | llvm::BitTracker::MachineEvaluator | |
eSUB(const RegisterCell &A1, const RegisterCell &A2) const | llvm::BitTracker::MachineEvaluator | |
eSXT(const RegisterCell &A1, uint16_t FromN) const | llvm::BitTracker::MachineEvaluator | |
evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override | llvm::HexagonEvaluator | virtual |
evaluate(const MachineInstr &BI, const CellMapType &Inputs, BranchTargetList &Targets, bool &FallsThru) const override | llvm::HexagonEvaluator | virtual |
eXOR(const RegisterCell &A1, const RegisterCell &A2) const | llvm::BitTracker::MachineEvaluator | |
eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const | llvm::BitTracker::MachineEvaluator | |
eZXT(const RegisterCell &A1, uint16_t FromN) const | llvm::BitTracker::MachineEvaluator | |
getCell(const RegisterRef &RR, const CellMapType &M) const | llvm::BitTracker::MachineEvaluator | |
getPhysRegBitWidth(MCRegister Reg) const override | llvm::HexagonEvaluator | virtual |
getRef(const RegisterRef &RR, const CellMapType &M) const | llvm::BitTracker::MachineEvaluator | inline |
getRegBitWidth(const RegisterRef &RR) const | llvm::BitTracker::MachineEvaluator | |
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf) | llvm::HexagonEvaluator | |
isInt(const RegisterCell &A) const | llvm::BitTracker::MachineEvaluator | |
MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M) | llvm::BitTracker::MachineEvaluator | inline |
mask(Register Reg, unsigned Sub) const override | llvm::HexagonEvaluator | virtual |
MF | llvm::HexagonEvaluator | |
MFI | llvm::HexagonEvaluator | |
MRI | llvm::BitTracker::MachineEvaluator | |
putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const | llvm::BitTracker::MachineEvaluator | |
RegisterCell typedef | llvm::HexagonEvaluator | |
RegisterRef typedef | llvm::HexagonEvaluator | |
TII | llvm::HexagonEvaluator | |
toInt(const RegisterCell &A) const | llvm::BitTracker::MachineEvaluator | |
track(const TargetRegisterClass *RC) const | llvm::BitTracker::MachineEvaluator | inlinevirtual |
TRI | llvm::BitTracker::MachineEvaluator | |
~MachineEvaluator()=default | llvm::BitTracker::MachineEvaluator | virtual |