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LLVM 20.0.0git
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This is the complete list of members for llvm::RISCVRegisterInfo, including all inherited members.
| adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const | llvm::RISCVRegisterInfo | |
| doesRegClassHavePseudoInitUndef(const TargetRegisterClass *RC) const override | llvm::RISCVRegisterInfo | inline |
| eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override | llvm::RISCVRegisterInfo | |
| getCalleeSavedRegs(const MachineFunction *MF) const override | llvm::RISCVRegisterInfo | |
| getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override | llvm::RISCVRegisterInfo | |
| getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override | llvm::RISCVRegisterInfo | |
| getFrameRegister(const MachineFunction &MF) const override | llvm::RISCVRegisterInfo | |
| getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const override | llvm::RISCVRegisterInfo | |
| getLargestSuperClass(const TargetRegisterClass *RC) const override | llvm::RISCVRegisterInfo | inline |
| getNoPreservedMask() const override | llvm::RISCVRegisterInfo | |
| getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override | llvm::RISCVRegisterInfo | |
| getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override | llvm::RISCVRegisterInfo | inline |
| getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override | llvm::RISCVRegisterInfo | |
| getRegisterCostTableIndex(const MachineFunction &MF) const override | llvm::RISCVRegisterInfo | |
| getReservedRegs(const MachineFunction &MF) const override | llvm::RISCVRegisterInfo | |
| isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override | llvm::RISCVRegisterInfo | |
| isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override | llvm::RISCVRegisterInfo | |
| isRVVRegClass(const TargetRegisterClass *RC) | llvm::RISCVRegisterInfo | inlinestatic |
| isVRNRegClass(const TargetRegisterClass *RC) | llvm::RISCVRegisterInfo | inlinestatic |
| isVRRegClass(const TargetRegisterClass *RC) | llvm::RISCVRegisterInfo | inlinestatic |
| lowerVRELOAD(MachineBasicBlock::iterator II) const | llvm::RISCVRegisterInfo | |
| lowerVSPILL(MachineBasicBlock::iterator II) const | llvm::RISCVRegisterInfo | |
| materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override | llvm::RISCVRegisterInfo | |
| needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override | llvm::RISCVRegisterInfo | |
| requiresFrameIndexScavenging(const MachineFunction &MF) const override | llvm::RISCVRegisterInfo | inline |
| requiresRegisterScavenging(const MachineFunction &MF) const override | llvm::RISCVRegisterInfo | inline |
| requiresVirtualBaseRegisters(const MachineFunction &MF) const override | llvm::RISCVRegisterInfo | |
| resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override | llvm::RISCVRegisterInfo | |
| RISCVRegisterInfo(unsigned HwMode) | llvm::RISCVRegisterInfo |
1.9.6