LLVM  16.0.0git
AMDGPUMCCodeEmitter.h
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1 //===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// CodeEmitter interface for SI codegen.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
15 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
16 
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 
20 namespace llvm {
21 
22 class MCInst;
23 class MCInstrInfo;
24 class MCOperand;
25 class MCSubtargetInfo;
26 
28  virtual void anchor();
29 
30 protected:
31  const MCInstrInfo &MCII;
32 
33  AMDGPUMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {}
34 
35 public:
37  APInt &Inst, APInt &Scratch,
38  const MCSubtargetInfo &STI) const;
39 
40  virtual void getMachineOpValue(const MCInst &MI, const MCOperand &MO,
42  const MCSubtargetInfo &STI) const = 0;
43 
44  virtual void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
46  const MCSubtargetInfo &STI) const = 0;
47 
48  virtual void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
50  const MCSubtargetInfo &STI) const = 0;
51 
52  virtual void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
54  const MCSubtargetInfo &STI) const = 0;
55 
56  virtual void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
57  APInt &Op,
59  const MCSubtargetInfo &STI) const = 0;
60 
61  virtual void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
63  const MCSubtargetInfo &STI) const = 0;
64 };
65 
66 } // End namespace llvm
67 
68 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter.h
llvm::AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding
virtual void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
APInt.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AMDGPUMCCodeEmitter::getSDWASrcEncoding
virtual void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
llvm::AMDGPUMCCodeEmitter::getBinaryCodeForInstr
void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, APInt &Inst, APInt &Scratch, const MCSubtargetInfo &STI) const
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::AMDGPUMCCodeEmitter::AMDGPUMCCodeEmitter
AMDGPUMCCodeEmitter(const MCInstrInfo &mcii)
Definition: AMDGPUMCCodeEmitter.h:33
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::AMDGPUMCCodeEmitter::MCII
const MCInstrInfo & MCII
Definition: AMDGPUMCCodeEmitter.h:31
llvm::AMDGPUMCCodeEmitter
Definition: AMDGPUMCCodeEmitter.h:27
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::AMDGPUMCCodeEmitter::getMachineOpValue
virtual void getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AMDGPUMCCodeEmitter::getAVOperandEncoding
virtual void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AMDGPUMCCodeEmitter::getSMEMOffsetEncoding
virtual void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
llvm::AMDGPUMCCodeEmitter::getSOPPBrEncoding
virtual void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77