LLVM  10.0.0svn
AMDGPURegisterInfo.cpp
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1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Parent TargetRegisterInfo class common to all hw codegen targets.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPURegisterInfo.h"
15 #include "AMDGPUTargetMachine.h"
16 #include "SIMachineFunctionInfo.h"
17 #include "SIRegisterInfo.h"
19 
20 using namespace llvm;
21 
23 
24 //===----------------------------------------------------------------------===//
25 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
26 // they are not supported at this time.
27 //===----------------------------------------------------------------------===//
28 
29 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
30  static const unsigned SubRegs[] = {
31  AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
32  AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
33  AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
34  AMDGPU::sub15, AMDGPU::sub16, AMDGPU::sub17, AMDGPU::sub18, AMDGPU::sub19,
35  AMDGPU::sub20, AMDGPU::sub21, AMDGPU::sub22, AMDGPU::sub23, AMDGPU::sub24,
36  AMDGPU::sub25, AMDGPU::sub26, AMDGPU::sub27, AMDGPU::sub28, AMDGPU::sub29,
37  AMDGPU::sub30, AMDGPU::sub31
38  };
39 
40  assert(Channel < array_lengthof(SubRegs));
41  return SubRegs[Channel];
42 }
43 
44 void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
45  MCRegAliasIterator R(Reg, this, true);
46 
47  for (; R.isValid(); ++R)
48  Reserved.set(*R);
49 }
50 
51 #define GET_REGINFO_TARGET_DESC
52 #include "AMDGPUGenRegisterInfo.inc"
53 
54 // Forced to be here by one .inc
56  const MachineFunction *MF) const {
58  switch (CC) {
59  case CallingConv::C:
60  case CallingConv::Fast:
61  case CallingConv::Cold:
62  return CSR_AMDGPU_HighRegs_SaveList;
63  default: {
64  // Dummy to not crash RegisterClassInfo.
65  static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
66  return &NoCalleeSavedReg;
67  }
68  }
69 }
70 
71 const MCPhysReg *
73  return nullptr;
74 }
75 
77  CallingConv::ID CC) const {
78  switch (CC) {
79  case CallingConv::C:
80  case CallingConv::Fast:
81  case CallingConv::Cold:
82  return CSR_AMDGPU_HighRegs_RegMask;
83  default:
84  return nullptr;
85  }
86 }
87 
89  const SIFrameLowering *TFI =
90  MF.getSubtarget<GCNSubtarget>().getFrameLowering();
91  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
92  return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
93  : FuncInfo->getStackPtrOffsetReg();
94 }
95 
97  return CSR_AMDGPU_AllVGPRs_RegMask;
98 }
99 
101  return CSR_AMDGPU_AllAllocatableSRegs_RegMask;
102 }
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
BitVector & set()
Definition: BitVector.h:397
Interface definition for SIRegisterInfo.
static unsigned getSubRegFromChannel(unsigned Channel)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned Reg
TargetRegisterInfo interface that is implemented by all hw codegen targets.
const uint32_t * getAllAllocatableSRegMask() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
The AMDGPU TargetMachine interface definition for hw codgen targets.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1023
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Provides AMDGPU specific target descriptions.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
void reserveRegisterTuples(BitVector &, unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Register getFrameRegister(const MachineFunction &MF) const override
const uint32_t * getAllVGPRRegMask() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19