LLVM 20.0.0git
ARMBuildAttributes.h
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1//===-- ARMBuildAttributes.h - ARM Build Attributes -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains enumerations and support routines for ARM build attributes
10// as defined in ARM ABI addenda document (ABI release 2.08).
11//
12// ELF for the ARM Architecture r2.09 - November 30, 2012
13//
14// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0044e/IHI0044E_aaelf.pdf
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_SUPPORT_ARMBUILDATTRIBUTES_H
19#define LLVM_SUPPORT_ARMBUILDATTRIBUTES_H
20
22
23namespace llvm {
24namespace ARMBuildAttrs {
25
27
29 // This is for the .cpu asm attr. It translates into one or more
30 // AttrType (below) entries in the .ARM.attributes section in the ELF.
32};
33
34enum AttrType : unsigned {
35 // Rest correspond to ELF/.ARM.attributes
36 File = 1,
43 FP_arch = 10,
69 MPextension_use = 42, // recoded from 70 (ABI r2.08)
70 DIV_use = 44,
78 BTI_use = 74,
80
81 /// Legacy Tags
82 Section = 2, // deprecated (ABI r2.09)
83 Symbol = 3, // deprecated (ABI r2.09)
84 ABI_align8_needed = 24, // renamed to ABI_align_needed (ABI r2.09)
85 ABI_align8_preserved = 25, // renamed to ABI_align_preserved (ABI r2.09)
86 nodefaults = 64, // deprecated (ABI r2.09)
87 T2EE_use = 66, // deprecated (ABI r2.09)
88 MPextension_use_old = 70 // recoded to MPextension_use (ABI r2.08)
89};
90
91// Legal Values for CPU_arch, (=6), uleb128
92enum CPUArch {
93 Pre_v4 = 0,
94 v4 = 1, // e.g. SA110
95 v4T = 2, // e.g. ARM7TDMI
96 v5T = 3, // e.g. ARM9TDMI
97 v5TE = 4, // e.g. ARM946E_S
98 v5TEJ = 5, // e.g. ARM926EJ_S
99 v6 = 6, // e.g. ARM1136J_S
100 v6KZ = 7, // e.g. ARM1176JZ_S
101 v6T2 = 8, // e.g. ARM1156T2_S
102 v6K = 9, // e.g. ARM1176JZ_S
103 v7 = 10, // e.g. Cortex A8, Cortex M3
104 v6_M = 11, // e.g. Cortex M1
105 v6S_M = 12, // v6_M with the System extensions
106 v7E_M = 13, // v7_M with DSP extensions
107 v8_A = 14, // v8_A AArch32
108 v8_R = 15, // e.g. Cortex R52
109 v8_M_Base = 16, // v8_M_Base AArch32
110 v8_M_Main = 17, // v8_M_Main AArch32
111 v8_1_M_Main = 21, // v8_1_M_Main AArch32
112 v9_A = 22, // v9_A AArch32
113};
114
115enum CPUArchProfile { // (=7), uleb128
116 Not_Applicable = 0, // pre v7, or cross-profile code
117 ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8)
118 RealTimeProfile = (0x52), // 'R' (e.g. for Cortex R4)
119 MicroControllerProfile = (0x4D), // 'M' (e.g. for Cortex M3)
120 SystemProfile = (0x53) // 'S' Application or real-time profile
122
123// The following have a lot of common use cases
124enum {
127
128 // Tag_ARM_ISA_use (=8), uleb128
129
130 // Tag_THUMB_ISA_use, (=9), uleb128
131 AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions)
132 AllowThumbDerived = 3, // Thumb allowed, derived from arch/profile
133
134 // Tag_FP_arch (=10), uleb128 (formerly Tag_VFP_arch = 10)
135 AllowFPv2 = 2, // v2 FP ISA permitted (implies use of the v1 FP ISA)
136 AllowFPv3A = 3, // v3 FP ISA permitted (implies use of the v2 FP ISA)
137 AllowFPv3B = 4, // v3 FP ISA permitted, but only D0-D15, S0-S31
138 AllowFPv4A = 5, // v4 FP ISA permitted (implies use of v3 FP ISA)
139 AllowFPv4B = 6, // v4 FP ISA was permitted, but only D0-D15, S0-S31
140 AllowFPARMv8A = 7, // Use of the ARM v8-A FP ISA was permitted
141 AllowFPARMv8B = 8, // Use of the ARM v8-A FP ISA was permitted, but only
142 // D0-D15, S0-S31
143
144 // Tag_WMMX_arch, (=11), uleb128
145 AllowWMMXv1 = 1, // The user permitted this entity to use WMMX v1
146 AllowWMMXv2 = 2, // The user permitted this entity to use WMMX v2
147
148 // Tag_Advanced_SIMD_arch, (=12), uleb128
149 AllowNeon = 1, // SIMDv1 was permitted
150 AllowNeon2 = 2, // SIMDv2 was permitted (Half-precision FP, MAC operations)
151 AllowNeonARMv8 = 3, // ARM v8-A SIMD was permitted
152 AllowNeonARMv8_1a = 4,// ARM v8.1-A SIMD was permitted (RDMA)
153
154 // Tag_MVE_arch, (=48), uleb128
155 AllowMVEInteger = 1, // integer-only MVE was permitted
156 AllowMVEIntegerAndFloat = 2, // both integer and floating point MVE were permitted
157
158 // Tag_ABI_PCS_R9_use, (=14), uleb128
159 R9IsGPR = 0, // R9 used as v6 (just another callee-saved register)
160 R9IsSB = 1, // R9 used as a global static base rgister
161 R9IsTLSPointer = 2, // R9 used as a thread local storage pointer
162 R9Reserved = 3, // R9 not used by code associated with attributed entity
163
164 // Tag_ABI_PCS_RW_data, (=15), uleb128
165 AddressRWPCRel = 1, // Address RW static data PC-relative
166 AddressRWSBRel = 2, // Address RW static data SB-relative
167 AddressRWNone = 3, // No RW static data permitted
168
169 // Tag_ABI_PCS_RO_data, (=14), uleb128
170 AddressROPCRel = 1, // Address RO static data PC-relative
171 AddressRONone = 2, // No RO static data permitted
172
173 // Tag_ABI_PCS_GOT_use, (=17), uleb128
174 AddressDirect = 1, // Address imported data directly
175 AddressGOT = 2, // Address imported data indirectly (via GOT)
176
177 // Tag_ABI_PCS_wchar_t, (=18), uleb128
178 WCharProhibited = 0, // wchar_t is not used
179 WCharWidth2Bytes = 2, // sizeof(wchar_t) == 2
180 WCharWidth4Bytes = 4, // sizeof(wchar_t) == 4
181
182 // Tag_ABI_align_needed, (=24), uleb128
186
187 // Tag_ABI_align_needed, (=25), uleb128
191
192 // Tag_ABI_FP_denormal, (=20), uleb128
195 PreserveFPSign = 2, // sign when flushed-to-zero is preserved
196
197 // Tag_ABI_FP_number_model, (=23), uleb128
199 AllowRTABI = 2, // numbers, infinities, and one quiet NaN (see [RTABI])
200 AllowIEEE754 = 3, // this code to use all the IEEE 754-defined FP encodings
201
202 // Tag_ABI_enum_size, (=26), uleb128
203 EnumProhibited = 0, // The user prohibited the use of enums when building
204 // this entity.
205 EnumSmallest = 1, // Enum is smallest container big enough to hold all
206 // values.
207 Enum32Bit = 2, // Enum is at least 32 bits.
208 Enum32BitABI = 3, // Every enumeration visible across an ABI-complying
209 // interface contains a value needing 32 bits to encode
210 // it; other enums can be containerized.
211
212 // Tag_ABI_HardFP_use, (=27), uleb128
213 HardFPImplied = 0, // FP use should be implied by Tag_FP_arch
214 HardFPSinglePrecision = 1, // Single-precision only
215
216 // Tag_ABI_VFP_args, (=28), uleb128
221
222 // Tag_FP_HP_extension, (=36), uleb128
223 AllowHPFP = 1, // Allow use of Half Precision FP
224
225 // Tag_FP_16bit_format, (=38), uleb128
228
229 // Tag_MPextension_use, (=42), uleb128
230 AllowMP = 1, // Allow use of MP extensions
231
232 // Tag_DIV_use, (=44), uleb128
233 // Note: AllowDIVExt must be emitted if and only if the permission to use
234 // hardware divide cannot be conveyed using AllowDIVIfExists or DisallowDIV
235 AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no
236 // info exists.
237 DisallowDIV = 1, // Hardware divide explicitly disallowed.
238 AllowDIVExt = 2, // Allow hardware divide as optional architecture
239 // extension above the base arch specified by
240 // Tag_CPU_arch and Tag_CPU_arch_profile.
241
242 // Tag_Virtualization_use, (=68), uleb128
246
247 // Tag_PAC_extension, (=50), uleb128
251
252 // Tag_BTI_extension, (=52), uleb128
256
257 // Tag_BTI_use, (=74), uleb128
260
261 // Tag_PACRET_use, (=76), uleb128
263 PACRETUsed = 1
265
266} // namespace ARMBuildAttrs
267} // namespace llvm
268
269#endif
const TagNameMap & getARMAttributeTags()
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18