LLVM  10.0.0svn
InstructionSelectorImpl.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
17 
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
20 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
21 #include "llvm/CodeGen/GlobalISel/Utils.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetInstrInfo.h"
26 #include "llvm/CodeGen/TargetOpcodes.h"
27 #include "llvm/CodeGen/TargetRegisterInfo.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <cassert>
33 #include <cstddef>
34 #include <cstdint>
35 
36 namespace llvm {
37 
38 /// GlobalISel PatFrag Predicates
39 enum {
40  GIPFP_I64_Invalid = 0,
41  GIPFP_APInt_Invalid = 0,
42  GIPFP_APFloat_Invalid = 0,
43  GIPFP_MI_Invalid = 0,
44 };
45 
46 template <class TgtInstructionSelector, class PredicateBitset,
47  class ComplexMatcherMemFn, class CustomRendererFn>
48 bool InstructionSelector::executeMatchTable(
49  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
50  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
51  &ISelInfo,
52  const int64_t *MatchTable, const TargetInstrInfo &TII,
53  MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
54  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
55  CodeGenCoverage &CoverageInfo) const {
56 
57  uint64_t CurrentIdx = 0;
58  SmallVector<uint64_t, 4> OnFailResumeAt;
59 
60  enum RejectAction { RejectAndGiveUp, RejectAndResume };
61  auto handleReject = [&]() -> RejectAction {
62  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
63  dbgs() << CurrentIdx << ": Rejected\n");
64  if (OnFailResumeAt.empty())
65  return RejectAndGiveUp;
66  CurrentIdx = OnFailResumeAt.pop_back_val();
67  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
68  dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " ("
69  << OnFailResumeAt.size() << " try-blocks remain)\n");
70  return RejectAndResume;
71  };
72 
73  while (true) {
74  assert(CurrentIdx != ~0u && "Invalid MatchTable index");
75  int64_t MatcherOpcode = MatchTable[CurrentIdx++];
76  switch (MatcherOpcode) {
77  case GIM_Try: {
78  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
79  dbgs() << CurrentIdx << ": Begin try-block\n");
80  OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
81  break;
82  }
83 
84  case GIM_RecordInsn: {
85  int64_t NewInsnID = MatchTable[CurrentIdx++];
86  int64_t InsnID = MatchTable[CurrentIdx++];
87  int64_t OpIdx = MatchTable[CurrentIdx++];
88 
89  // As an optimisation we require that MIs[0] is always the root. Refuse
90  // any attempt to modify it.
91  assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
92 
93  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
94  if (!MO.isReg()) {
95  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
96  dbgs() << CurrentIdx << ": Not a register\n");
97  if (handleReject() == RejectAndGiveUp)
98  return false;
99  break;
100  }
101  if (Register::isPhysicalRegister(MO.getReg())) {
102  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
103  dbgs() << CurrentIdx << ": Is a physical register\n");
104  if (handleReject() == RejectAndGiveUp)
105  return false;
106  break;
107  }
108 
109  MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());
110  if ((size_t)NewInsnID < State.MIs.size())
111  State.MIs[NewInsnID] = NewMI;
112  else {
113  assert((size_t)NewInsnID == State.MIs.size() &&
114  "Expected to store MIs in order");
115  State.MIs.push_back(NewMI);
116  }
117  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
118  dbgs() << CurrentIdx << ": MIs[" << NewInsnID
119  << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
120  << ")\n");
121  break;
122  }
123 
124  case GIM_CheckFeatures: {
125  int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
126  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
127  dbgs() << CurrentIdx
128  << ": GIM_CheckFeatures(ExpectedBitsetID="
129  << ExpectedBitsetID << ")\n");
130  if ((AvailableFeatures & ISelInfo.FeatureBitsets[ExpectedBitsetID]) !=
131  ISelInfo.FeatureBitsets[ExpectedBitsetID]) {
132  if (handleReject() == RejectAndGiveUp)
133  return false;
134  }
135  break;
136  }
137 
138  case GIM_CheckOpcode: {
139  int64_t InsnID = MatchTable[CurrentIdx++];
140  int64_t Expected = MatchTable[CurrentIdx++];
141 
142  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
143  unsigned Opcode = State.MIs[InsnID]->getOpcode();
144 
145  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
146  dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
147  << "], ExpectedOpcode=" << Expected
148  << ") // Got=" << Opcode << "\n");
149  if (Opcode != Expected) {
150  if (handleReject() == RejectAndGiveUp)
151  return false;
152  }
153  break;
154  }
155 
156  case GIM_SwitchOpcode: {
157  int64_t InsnID = MatchTable[CurrentIdx++];
158  int64_t LowerBound = MatchTable[CurrentIdx++];
159  int64_t UpperBound = MatchTable[CurrentIdx++];
160  int64_t Default = MatchTable[CurrentIdx++];
161 
162  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
163  const int64_t Opcode = State.MIs[InsnID]->getOpcode();
164 
165  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), {
166  dbgs() << CurrentIdx << ": GIM_SwitchOpcode(MIs[" << InsnID << "], ["
167  << LowerBound << ", " << UpperBound << "), Default=" << Default
168  << ", JumpTable...) // Got=" << Opcode << "\n";
169  });
170  if (Opcode < LowerBound || UpperBound <= Opcode) {
171  CurrentIdx = Default;
172  break;
173  }
174  CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
175  if (!CurrentIdx) {
176  CurrentIdx = Default;
177  break;
178  }
179  OnFailResumeAt.push_back(Default);
180  break;
181  }
182 
183  case GIM_SwitchType: {
184  int64_t InsnID = MatchTable[CurrentIdx++];
185  int64_t OpIdx = MatchTable[CurrentIdx++];
186  int64_t LowerBound = MatchTable[CurrentIdx++];
187  int64_t UpperBound = MatchTable[CurrentIdx++];
188  int64_t Default = MatchTable[CurrentIdx++];
189 
190  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
191  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
192 
193  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), {
194  dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
195  << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
196  << UpperBound << "), Default=" << Default
197  << ", JumpTable...) // Got=";
198  if (!MO.isReg())
199  dbgs() << "Not a VReg\n";
200  else
201  dbgs() << MRI.getType(MO.getReg()) << "\n";
202  });
203  if (!MO.isReg()) {
204  CurrentIdx = Default;
205  break;
206  }
207  const LLT Ty = MRI.getType(MO.getReg());
208  const auto TyI = ISelInfo.TypeIDMap.find(Ty);
209  if (TyI == ISelInfo.TypeIDMap.end()) {
210  CurrentIdx = Default;
211  break;
212  }
213  const int64_t TypeID = TyI->second;
214  if (TypeID < LowerBound || UpperBound <= TypeID) {
215  CurrentIdx = Default;
216  break;
217  }
218  CurrentIdx = MatchTable[CurrentIdx + (TypeID - LowerBound)];
219  if (!CurrentIdx) {
220  CurrentIdx = Default;
221  break;
222  }
223  OnFailResumeAt.push_back(Default);
224  break;
225  }
226 
227  case GIM_CheckNumOperands: {
228  int64_t InsnID = MatchTable[CurrentIdx++];
229  int64_t Expected = MatchTable[CurrentIdx++];
230  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
231  dbgs() << CurrentIdx << ": GIM_CheckNumOperands(MIs["
232  << InsnID << "], Expected=" << Expected << ")\n");
233  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
234  if (State.MIs[InsnID]->getNumOperands() != Expected) {
235  if (handleReject() == RejectAndGiveUp)
236  return false;
237  }
238  break;
239  }
240  case GIM_CheckI64ImmPredicate: {
241  int64_t InsnID = MatchTable[CurrentIdx++];
242  int64_t Predicate = MatchTable[CurrentIdx++];
243  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
244  dbgs()
245  << CurrentIdx << ": GIM_CheckI64ImmPredicate(MIs["
246  << InsnID << "], Predicate=" << Predicate << ")\n");
247  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
248  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
249  "Expected G_CONSTANT");
250  assert(Predicate > GIPFP_I64_Invalid && "Expected a valid predicate");
251  int64_t Value = 0;
252  if (State.MIs[InsnID]->getOperand(1).isCImm())
253  Value = State.MIs[InsnID]->getOperand(1).getCImm()->getSExtValue();
254  else if (State.MIs[InsnID]->getOperand(1).isImm())
255  Value = State.MIs[InsnID]->getOperand(1).getImm();
256  else
257  llvm_unreachable("Expected Imm or CImm operand");
258 
259  if (!testImmPredicate_I64(Predicate, Value))
260  if (handleReject() == RejectAndGiveUp)
261  return false;
262  break;
263  }
264  case GIM_CheckAPIntImmPredicate: {
265  int64_t InsnID = MatchTable[CurrentIdx++];
266  int64_t Predicate = MatchTable[CurrentIdx++];
267  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
268  dbgs()
269  << CurrentIdx << ": GIM_CheckAPIntImmPredicate(MIs["
270  << InsnID << "], Predicate=" << Predicate << ")\n");
271  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
272  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
273  "Expected G_CONSTANT");
274  assert(Predicate > GIPFP_APInt_Invalid && "Expected a valid predicate");
275  APInt Value;
276  if (State.MIs[InsnID]->getOperand(1).isCImm())
277  Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
278  else
279  llvm_unreachable("Expected Imm or CImm operand");
280 
281  if (!testImmPredicate_APInt(Predicate, Value))
282  if (handleReject() == RejectAndGiveUp)
283  return false;
284  break;
285  }
286  case GIM_CheckAPFloatImmPredicate: {
287  int64_t InsnID = MatchTable[CurrentIdx++];
288  int64_t Predicate = MatchTable[CurrentIdx++];
289  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
290  dbgs()
291  << CurrentIdx << ": GIM_CheckAPFloatImmPredicate(MIs["
292  << InsnID << "], Predicate=" << Predicate << ")\n");
293  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
294  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
295  "Expected G_FCONSTANT");
296  assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand");
297  assert(Predicate > GIPFP_APFloat_Invalid && "Expected a valid predicate");
298  APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
299 
300  if (!testImmPredicate_APFloat(Predicate, Value))
301  if (handleReject() == RejectAndGiveUp)
302  return false;
303  break;
304  }
305  case GIM_CheckCxxInsnPredicate: {
306  int64_t InsnID = MatchTable[CurrentIdx++];
307  int64_t Predicate = MatchTable[CurrentIdx++];
308  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
309  dbgs()
310  << CurrentIdx << ": GIM_CheckCxxPredicate(MIs["
311  << InsnID << "], Predicate=" << Predicate << ")\n");
312  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
313  assert(Predicate > GIPFP_MI_Invalid && "Expected a valid predicate");
314 
315  if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID]))
316  if (handleReject() == RejectAndGiveUp)
317  return false;
318  break;
319  }
320  case GIM_CheckAtomicOrdering: {
321  int64_t InsnID = MatchTable[CurrentIdx++];
322  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
323  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
324  dbgs() << CurrentIdx << ": GIM_CheckAtomicOrdering(MIs["
325  << InsnID << "], " << (uint64_t)Ordering << ")\n");
326  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
327  if (!State.MIs[InsnID]->hasOneMemOperand())
328  if (handleReject() == RejectAndGiveUp)
329  return false;
330 
331  for (const auto &MMO : State.MIs[InsnID]->memoperands())
332  if (MMO->getOrdering() != Ordering)
333  if (handleReject() == RejectAndGiveUp)
334  return false;
335  break;
336  }
337  case GIM_CheckAtomicOrderingOrStrongerThan: {
338  int64_t InsnID = MatchTable[CurrentIdx++];
339  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
340  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
341  dbgs() << CurrentIdx
342  << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
343  << InsnID << "], " << (uint64_t)Ordering << ")\n");
344  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
345  if (!State.MIs[InsnID]->hasOneMemOperand())
346  if (handleReject() == RejectAndGiveUp)
347  return false;
348 
349  for (const auto &MMO : State.MIs[InsnID]->memoperands())
350  if (!isAtLeastOrStrongerThan(MMO->getOrdering(), Ordering))
351  if (handleReject() == RejectAndGiveUp)
352  return false;
353  break;
354  }
355  case GIM_CheckAtomicOrderingWeakerThan: {
356  int64_t InsnID = MatchTable[CurrentIdx++];
357  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
358  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
359  dbgs() << CurrentIdx
360  << ": GIM_CheckAtomicOrderingWeakerThan(MIs["
361  << InsnID << "], " << (uint64_t)Ordering << ")\n");
362  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
363  if (!State.MIs[InsnID]->hasOneMemOperand())
364  if (handleReject() == RejectAndGiveUp)
365  return false;
366 
367  for (const auto &MMO : State.MIs[InsnID]->memoperands())
368  if (!isStrongerThan(Ordering, MMO->getOrdering()))
369  if (handleReject() == RejectAndGiveUp)
370  return false;
371  break;
372  }
373  case GIM_CheckMemoryAddressSpace: {
374  int64_t InsnID = MatchTable[CurrentIdx++];
375  int64_t MMOIdx = MatchTable[CurrentIdx++];
376  // This accepts a list of possible address spaces.
377  const int NumAddrSpace = MatchTable[CurrentIdx++];
378 
379  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
380  if (handleReject() == RejectAndGiveUp)
381  return false;
382  break;
383  }
384 
385  // Need to still jump to the end of the list of address spaces if we find
386  // a match earlier.
387  const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
388 
389  const MachineMemOperand *MMO
390  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
391  const unsigned MMOAddrSpace = MMO->getAddrSpace();
392 
393  bool Success = false;
394  for (int I = 0; I != NumAddrSpace; ++I) {
395  unsigned AddrSpace = MatchTable[CurrentIdx++];
396  DEBUG_WITH_TYPE(
397  TgtInstructionSelector::getName(),
398  dbgs() << "addrspace(" << MMOAddrSpace << ") vs "
399  << AddrSpace << '\n');
400 
401  if (AddrSpace == MMOAddrSpace) {
402  Success = true;
403  break;
404  }
405  }
406 
407  CurrentIdx = LastIdx;
408  if (!Success && handleReject() == RejectAndGiveUp)
409  return false;
410  break;
411  }
412  case GIM_CheckMemoryAlignment: {
413  int64_t InsnID = MatchTable[CurrentIdx++];
414  int64_t MMOIdx = MatchTable[CurrentIdx++];
415  unsigned MinAlign = MatchTable[CurrentIdx++];
416 
417  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
418 
419  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
420  if (handleReject() == RejectAndGiveUp)
421  return false;
422  break;
423  }
424 
425  MachineMemOperand *MMO
426  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
427  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
428  dbgs() << CurrentIdx << ": GIM_CheckMemoryAlignment"
429  << "(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
430  << ")->getAlignment() >= " << MinAlign << ")\n");
431  if (MMO->getAlignment() < MinAlign && handleReject() == RejectAndGiveUp)
432  return false;
433 
434  break;
435  }
436  case GIM_CheckMemorySizeEqualTo: {
437  int64_t InsnID = MatchTable[CurrentIdx++];
438  int64_t MMOIdx = MatchTable[CurrentIdx++];
439  uint64_t Size = MatchTable[CurrentIdx++];
440 
441  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
442  dbgs() << CurrentIdx
443  << ": GIM_CheckMemorySizeEqual(MIs[" << InsnID
444  << "]->memoperands() + " << MMOIdx
445  << ", Size=" << Size << ")\n");
446  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
447 
448  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
449  if (handleReject() == RejectAndGiveUp)
450  return false;
451  break;
452  }
453 
454  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
455 
456  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
457  dbgs() << MMO->getSize() << " bytes vs " << Size
458  << " bytes\n");
459  if (MMO->getSize() != Size)
460  if (handleReject() == RejectAndGiveUp)
461  return false;
462 
463  break;
464  }
465  case GIM_CheckMemorySizeEqualToLLT:
466  case GIM_CheckMemorySizeLessThanLLT:
467  case GIM_CheckMemorySizeGreaterThanLLT: {
468  int64_t InsnID = MatchTable[CurrentIdx++];
469  int64_t MMOIdx = MatchTable[CurrentIdx++];
470  int64_t OpIdx = MatchTable[CurrentIdx++];
471 
472  DEBUG_WITH_TYPE(
473  TgtInstructionSelector::getName(),
474  dbgs() << CurrentIdx << ": GIM_CheckMemorySize"
475  << (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT
476  ? "EqualTo"
477  : MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT
478  ? "GreaterThan"
479  : "LessThan")
480  << "LLT(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
481  << ", OpIdx=" << OpIdx << ")\n");
482  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
483 
484  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
485  if (!MO.isReg()) {
486  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
487  dbgs() << CurrentIdx << ": Not a register\n");
488  if (handleReject() == RejectAndGiveUp)
489  return false;
490  break;
491  }
492 
493  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
494  if (handleReject() == RejectAndGiveUp)
495  return false;
496  break;
497  }
498 
499  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
500 
501  unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
502  if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
503  MMO->getSizeInBits() != Size) {
504  if (handleReject() == RejectAndGiveUp)
505  return false;
506  } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
507  MMO->getSizeInBits() >= Size) {
508  if (handleReject() == RejectAndGiveUp)
509  return false;
510  } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
511  MMO->getSizeInBits() <= Size)
512  if (handleReject() == RejectAndGiveUp)
513  return false;
514 
515  break;
516  }
517  case GIM_CheckType: {
518  int64_t InsnID = MatchTable[CurrentIdx++];
519  int64_t OpIdx = MatchTable[CurrentIdx++];
520  int64_t TypeID = MatchTable[CurrentIdx++];
521  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
522  dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
523  << "]->getOperand(" << OpIdx
524  << "), TypeID=" << TypeID << ")\n");
525  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
526  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
527  if (!MO.isReg() ||
528  MRI.getType(MO.getReg()) != ISelInfo.TypeObjects[TypeID]) {
529  if (handleReject() == RejectAndGiveUp)
530  return false;
531  }
532  break;
533  }
534  case GIM_CheckPointerToAny: {
535  int64_t InsnID = MatchTable[CurrentIdx++];
536  int64_t OpIdx = MatchTable[CurrentIdx++];
537  int64_t SizeInBits = MatchTable[CurrentIdx++];
538 
539  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
540  dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs["
541  << InsnID << "]->getOperand(" << OpIdx
542  << "), SizeInBits=" << SizeInBits << ")\n");
543  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
544  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
545  const LLT Ty = MRI.getType(MO.getReg());
546 
547  // iPTR must be looked up in the target.
548  if (SizeInBits == 0) {
549  MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
550  const unsigned AddrSpace = Ty.getAddressSpace();
551  SizeInBits = MF->getDataLayout().getPointerSizeInBits(AddrSpace);
552  }
553 
554  assert(SizeInBits != 0 && "Pointer size must be known");
555 
556  if (MO.isReg()) {
557  if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits)
558  if (handleReject() == RejectAndGiveUp)
559  return false;
560  } else if (handleReject() == RejectAndGiveUp)
561  return false;
562 
563  break;
564  }
565  case GIM_CheckRegBankForClass: {
566  int64_t InsnID = MatchTable[CurrentIdx++];
567  int64_t OpIdx = MatchTable[CurrentIdx++];
568  int64_t RCEnum = MatchTable[CurrentIdx++];
569  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
570  dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
571  << InsnID << "]->getOperand(" << OpIdx
572  << "), RCEnum=" << RCEnum << ")\n");
573  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
574  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
575  if (!MO.isReg() ||
576  &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum)) !=
577  RBI.getRegBank(MO.getReg(), MRI, TRI)) {
578  if (handleReject() == RejectAndGiveUp)
579  return false;
580  }
581  break;
582  }
583 
584  case GIM_CheckComplexPattern: {
585  int64_t InsnID = MatchTable[CurrentIdx++];
586  int64_t OpIdx = MatchTable[CurrentIdx++];
587  int64_t RendererID = MatchTable[CurrentIdx++];
588  int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
589  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
590  dbgs() << CurrentIdx << ": State.Renderers[" << RendererID
591  << "] = GIM_CheckComplexPattern(MIs[" << InsnID
592  << "]->getOperand(" << OpIdx
593  << "), ComplexPredicateID=" << ComplexPredicateID
594  << ")\n");
595  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
596  // FIXME: Use std::invoke() when it's available.
597  ComplexRendererFns Renderer =
598  (ISel.*ISelInfo.ComplexPredicates[ComplexPredicateID])(
599  State.MIs[InsnID]->getOperand(OpIdx));
600  if (Renderer.hasValue())
601  State.Renderers[RendererID] = Renderer.getValue();
602  else
603  if (handleReject() == RejectAndGiveUp)
604  return false;
605  break;
606  }
607 
608  case GIM_CheckConstantInt: {
609  int64_t InsnID = MatchTable[CurrentIdx++];
610  int64_t OpIdx = MatchTable[CurrentIdx++];
611  int64_t Value = MatchTable[CurrentIdx++];
612  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
613  dbgs() << CurrentIdx << ": GIM_CheckConstantInt(MIs["
614  << InsnID << "]->getOperand(" << OpIdx
615  << "), Value=" << Value << ")\n");
616  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
617  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
618  if (MO.isReg()) {
619  // isOperandImmEqual() will sign-extend to 64-bits, so should we.
620  LLT Ty = MRI.getType(MO.getReg());
621  Value = SignExtend64(Value, Ty.getSizeInBits());
622 
623  if (!isOperandImmEqual(MO, Value, MRI)) {
624  if (handleReject() == RejectAndGiveUp)
625  return false;
626  }
627  } else if (handleReject() == RejectAndGiveUp)
628  return false;
629 
630  break;
631  }
632 
633  case GIM_CheckLiteralInt: {
634  int64_t InsnID = MatchTable[CurrentIdx++];
635  int64_t OpIdx = MatchTable[CurrentIdx++];
636  int64_t Value = MatchTable[CurrentIdx++];
637  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
638  dbgs() << CurrentIdx << ": GIM_CheckLiteralInt(MIs["
639  << InsnID << "]->getOperand(" << OpIdx
640  << "), Value=" << Value << ")\n");
641  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
642  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
643  if (!MO.isCImm() || !MO.getCImm()->equalsInt(Value)) {
644  if (handleReject() == RejectAndGiveUp)
645  return false;
646  }
647  break;
648  }
649 
650  case GIM_CheckIntrinsicID: {
651  int64_t InsnID = MatchTable[CurrentIdx++];
652  int64_t OpIdx = MatchTable[CurrentIdx++];
653  int64_t Value = MatchTable[CurrentIdx++];
654  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
655  dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs["
656  << InsnID << "]->getOperand(" << OpIdx
657  << "), Value=" << Value << ")\n");
658  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
659  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
660  if (!MO.isIntrinsicID() || MO.getIntrinsicID() != Value)
661  if (handleReject() == RejectAndGiveUp)
662  return false;
663  break;
664  }
665 
666  case GIM_CheckIsMBB: {
667  int64_t InsnID = MatchTable[CurrentIdx++];
668  int64_t OpIdx = MatchTable[CurrentIdx++];
669  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
670  dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID
671  << "]->getOperand(" << OpIdx << "))\n");
672  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
673  if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
674  if (handleReject() == RejectAndGiveUp)
675  return false;
676  }
677  break;
678  }
679 
680  case GIM_CheckIsSafeToFold: {
681  int64_t InsnID = MatchTable[CurrentIdx++];
682  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
683  dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs["
684  << InsnID << "])\n");
685  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
686  if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) {
687  if (handleReject() == RejectAndGiveUp)
688  return false;
689  }
690  break;
691  }
692  case GIM_CheckIsSameOperand: {
693  int64_t InsnID = MatchTable[CurrentIdx++];
694  int64_t OpIdx = MatchTable[CurrentIdx++];
695  int64_t OtherInsnID = MatchTable[CurrentIdx++];
696  int64_t OtherOpIdx = MatchTable[CurrentIdx++];
697  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
698  dbgs() << CurrentIdx << ": GIM_CheckIsSameOperand(MIs["
699  << InsnID << "][" << OpIdx << "], MIs["
700  << OtherInsnID << "][" << OtherOpIdx << "])\n");
701  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
702  assert(State.MIs[OtherInsnID] != nullptr && "Used insn before defined");
703  if (!State.MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
704  State.MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
705  if (handleReject() == RejectAndGiveUp)
706  return false;
707  }
708  break;
709  }
710  case GIM_Reject:
711  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
712  dbgs() << CurrentIdx << ": GIM_Reject\n");
713  if (handleReject() == RejectAndGiveUp)
714  return false;
715  break;
716 
717  case GIR_MutateOpcode: {
718  int64_t OldInsnID = MatchTable[CurrentIdx++];
719  uint64_t NewInsnID = MatchTable[CurrentIdx++];
720  int64_t NewOpcode = MatchTable[CurrentIdx++];
721  if (NewInsnID >= OutMIs.size())
722  OutMIs.resize(NewInsnID + 1);
723 
724  OutMIs[NewInsnID] = MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(),
725  State.MIs[OldInsnID]);
726  OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
727  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
728  dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs["
729  << NewInsnID << "], MIs[" << OldInsnID << "], "
730  << NewOpcode << ")\n");
731  break;
732  }
733 
734  case GIR_BuildMI: {
735  uint64_t NewInsnID = MatchTable[CurrentIdx++];
736  int64_t Opcode = MatchTable[CurrentIdx++];
737  if (NewInsnID >= OutMIs.size())
738  OutMIs.resize(NewInsnID + 1);
739 
740  OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
741  State.MIs[0]->getDebugLoc(), TII.get(Opcode));
742  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
743  dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
744  << NewInsnID << "], " << Opcode << ")\n");
745  break;
746  }
747 
748  case GIR_Copy: {
749  int64_t NewInsnID = MatchTable[CurrentIdx++];
750  int64_t OldInsnID = MatchTable[CurrentIdx++];
751  int64_t OpIdx = MatchTable[CurrentIdx++];
752  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
753  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
754  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
755  dbgs()
756  << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
757  << "], MIs[" << OldInsnID << "], " << OpIdx << ")\n");
758  break;
759  }
760 
761  case GIR_CopyOrAddZeroReg: {
762  int64_t NewInsnID = MatchTable[CurrentIdx++];
763  int64_t OldInsnID = MatchTable[CurrentIdx++];
764  int64_t OpIdx = MatchTable[CurrentIdx++];
765  int64_t ZeroReg = MatchTable[CurrentIdx++];
766  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
767  MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
768  if (isOperandImmEqual(MO, 0, MRI))
769  OutMIs[NewInsnID].addReg(ZeroReg);
770  else
771  OutMIs[NewInsnID].add(MO);
772  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
773  dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs["
774  << NewInsnID << "], MIs[" << OldInsnID << "], "
775  << OpIdx << ", " << ZeroReg << ")\n");
776  break;
777  }
778 
779  case GIR_CopySubReg: {
780  int64_t NewInsnID = MatchTable[CurrentIdx++];
781  int64_t OldInsnID = MatchTable[CurrentIdx++];
782  int64_t OpIdx = MatchTable[CurrentIdx++];
783  int64_t SubRegIdx = MatchTable[CurrentIdx++];
784  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
785  OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
786  0, SubRegIdx);
787  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
788  dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
789  << NewInsnID << "], MIs[" << OldInsnID << "], "
790  << OpIdx << ", " << SubRegIdx << ")\n");
791  break;
792  }
793 
794  case GIR_AddImplicitDef: {
795  int64_t InsnID = MatchTable[CurrentIdx++];
796  int64_t RegNum = MatchTable[CurrentIdx++];
797  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
798  OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
799  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
800  dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
801  << InsnID << "], " << RegNum << ")\n");
802  break;
803  }
804 
805  case GIR_AddImplicitUse: {
806  int64_t InsnID = MatchTable[CurrentIdx++];
807  int64_t RegNum = MatchTable[CurrentIdx++];
808  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
809  OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
810  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
811  dbgs() << CurrentIdx << ": GIR_AddImplicitUse(OutMIs["
812  << InsnID << "], " << RegNum << ")\n");
813  break;
814  }
815 
816  case GIR_AddRegister: {
817  int64_t InsnID = MatchTable[CurrentIdx++];
818  int64_t RegNum = MatchTable[CurrentIdx++];
819  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
820  OutMIs[InsnID].addReg(RegNum);
821  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
822  dbgs() << CurrentIdx << ": GIR_AddRegister(OutMIs["
823  << InsnID << "], " << RegNum << ")\n");
824  break;
825  }
826 
827  case GIR_AddTempRegister: {
828  int64_t InsnID = MatchTable[CurrentIdx++];
829  int64_t TempRegID = MatchTable[CurrentIdx++];
830  uint64_t TempRegFlags = MatchTable[CurrentIdx++];
831  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
832  OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags);
833  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
834  dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs["
835  << InsnID << "], TempRegisters[" << TempRegID
836  << "], " << TempRegFlags << ")\n");
837  break;
838  }
839 
840  case GIR_AddImm: {
841  int64_t InsnID = MatchTable[CurrentIdx++];
842  int64_t Imm = MatchTable[CurrentIdx++];
843  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
844  OutMIs[InsnID].addImm(Imm);
845  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
846  dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
847  << "], " << Imm << ")\n");
848  break;
849  }
850 
851  case GIR_ComplexRenderer: {
852  int64_t InsnID = MatchTable[CurrentIdx++];
853  int64_t RendererID = MatchTable[CurrentIdx++];
854  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
855  for (const auto &RenderOpFn : State.Renderers[RendererID])
856  RenderOpFn(OutMIs[InsnID]);
857  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
858  dbgs() << CurrentIdx << ": GIR_ComplexRenderer(OutMIs["
859  << InsnID << "], " << RendererID << ")\n");
860  break;
861  }
862  case GIR_ComplexSubOperandRenderer: {
863  int64_t InsnID = MatchTable[CurrentIdx++];
864  int64_t RendererID = MatchTable[CurrentIdx++];
865  int64_t RenderOpID = MatchTable[CurrentIdx++];
866  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
867  State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
868  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
869  dbgs() << CurrentIdx
870  << ": GIR_ComplexSubOperandRenderer(OutMIs["
871  << InsnID << "], " << RendererID << ", "
872  << RenderOpID << ")\n");
873  break;
874  }
875 
876  case GIR_CopyConstantAsSImm: {
877  int64_t NewInsnID = MatchTable[CurrentIdx++];
878  int64_t OldInsnID = MatchTable[CurrentIdx++];
879  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
880  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
881  if (State.MIs[OldInsnID]->getOperand(1).isCImm()) {
882  OutMIs[NewInsnID].addImm(
883  State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
884  } else if (State.MIs[OldInsnID]->getOperand(1).isImm())
885  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
886  else
887  llvm_unreachable("Expected Imm or CImm operand");
888  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
889  dbgs() << CurrentIdx << ": GIR_CopyConstantAsSImm(OutMIs["
890  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
891  break;
892  }
893 
894  // TODO: Needs a test case once we have a pattern that uses this.
895  case GIR_CopyFConstantAsFPImm: {
896  int64_t NewInsnID = MatchTable[CurrentIdx++];
897  int64_t OldInsnID = MatchTable[CurrentIdx++];
898  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
899  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT");
900  if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
901  OutMIs[NewInsnID].addFPImm(
902  State.MIs[OldInsnID]->getOperand(1).getFPImm());
903  else
904  llvm_unreachable("Expected FPImm operand");
905  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
906  dbgs() << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
907  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
908  break;
909  }
910 
911  case GIR_CustomRenderer: {
912  int64_t InsnID = MatchTable[CurrentIdx++];
913  int64_t OldInsnID = MatchTable[CurrentIdx++];
914  int64_t RendererFnID = MatchTable[CurrentIdx++];
915  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
916  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
917  dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs["
918  << InsnID << "], MIs[" << OldInsnID << "], "
919  << RendererFnID << ")\n");
920  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(OutMIs[InsnID],
921  *State.MIs[OldInsnID]);
922  break;
923  }
924  case GIR_ConstrainOperandRC: {
925  int64_t InsnID = MatchTable[CurrentIdx++];
926  int64_t OpIdx = MatchTable[CurrentIdx++];
927  int64_t RCEnum = MatchTable[CurrentIdx++];
928  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
929  constrainOperandRegToRegClass(*OutMIs[InsnID].getInstr(), OpIdx,
930  *TRI.getRegClass(RCEnum), TII, TRI, RBI);
931  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
932  dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
933  << InsnID << "], " << OpIdx << ", " << RCEnum
934  << ")\n");
935  break;
936  }
937 
938  case GIR_ConstrainSelectedInstOperands: {
939  int64_t InsnID = MatchTable[CurrentIdx++];
940  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
941  constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
942  RBI);
943  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
944  dbgs() << CurrentIdx
945  << ": GIR_ConstrainSelectedInstOperands(OutMIs["
946  << InsnID << "])\n");
947  break;
948  }
949 
950  case GIR_MergeMemOperands: {
951  int64_t InsnID = MatchTable[CurrentIdx++];
952  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
953 
954  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
955  dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs["
956  << InsnID << "]");
957  int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList;
958  while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
959  GIU_MergeMemOperands_EndOfList) {
960  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
961  dbgs() << ", MIs[" << MergeInsnID << "]");
962  for (const auto &MMO : State.MIs[MergeInsnID]->memoperands())
963  OutMIs[InsnID].addMemOperand(MMO);
964  }
965  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), dbgs() << ")\n");
966  break;
967  }
968 
969  case GIR_EraseFromParent: {
970  int64_t InsnID = MatchTable[CurrentIdx++];
971  assert(State.MIs[InsnID] &&
972  "Attempted to erase an undefined instruction");
973  State.MIs[InsnID]->eraseFromParent();
974  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
975  dbgs() << CurrentIdx << ": GIR_EraseFromParent(MIs["
976  << InsnID << "])\n");
977  break;
978  }
979 
980  case GIR_MakeTempReg: {
981  int64_t TempRegID = MatchTable[CurrentIdx++];
982  int64_t TypeID = MatchTable[CurrentIdx++];
983 
984  State.TempRegisters[TempRegID] =
985  MRI.createGenericVirtualRegister(ISelInfo.TypeObjects[TypeID]);
986  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
987  dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
988  << "] = GIR_MakeTempReg(" << TypeID << ")\n");
989  break;
990  }
991 
992  case GIR_Coverage: {
993  int64_t RuleID = MatchTable[CurrentIdx++];
994  CoverageInfo.setCovered(RuleID);
995 
996  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
997  dbgs()
998  << CurrentIdx << ": GIR_Coverage(" << RuleID << ")");
999  break;
1000  }
1001 
1002  case GIR_Done:
1003  DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
1004  dbgs() << CurrentIdx << ": GIR_Done\n");
1005  return true;
1006 
1007  default:
1008  llvm_unreachable("Unexpected command");
1009  }
1010  }
1011 }
1012 
1013 } // end namespace llvm
1014 
1015 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
llvm::GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:320
llvm::GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:125
llvm::GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:104
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:218
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:393
llvm::getSizeInBits
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition: SmallVector.h:211
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
llvm::GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:272
llvm::InstructionSelector::constrainOperandRegToRegClass
bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Constrain a register operand of an instruction I to a specified register class.
Definition: InstructionSelector.cpp:36
llvm::GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:204
llvm::GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:348
llvm::MachineRegisterInfo::getType
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
Definition: MachineRegisterInfo.h:729
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:221
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:389
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:979
llvm::ConstantInt::equalsInt
bool equalsInt(uint64_t V) const
A helper method that can be used to determine if the constant contained within is equal to a constant...
Definition: Constants.h:164
llvm::GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:209
llvm::GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:113
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:418
llvm::GIR_Done
A successful emission.
Definition: InstructionSelector.h:344
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:671
llvm::GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:121
DEBUG_WITH_TYPE
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:345
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:38
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:214
llvm::GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:175
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::isStrongerThan
bool isStrongerThan(AtomicOrdering ao, AtomicOrdering other)
Returns true if ao is stronger than other as defined by the AtomicOrdering lattice, which is based on C++&#39;s definition.
Definition: AtomicOrdering.h:89
llvm::GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:297
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:40
llvm::GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:169
llvm::GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:98
llvm::Expected
Tagged union holding either a T or a Error.
Definition: yaml2obj.h:21
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:395
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:421
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
Definition: AtomicOrdering.h:56
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:108
llvm::GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:163
llvm::GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:249
llvm::GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:243
llvm::Optional::getValue
const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:255
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:224
llvm::GIR_MakeTempReg
Create a new temporary register that&#39;s not constrained.
Definition: InstructionSelector.h:341
llvm::GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:149
llvm::GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:129
llvm::GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:276
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:257
llvm::GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:117
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:69
llvm::isAtLeastOrStrongerThan
bool isAtLeastOrStrongerThan(AtomicOrdering ao, AtomicOrdering other)
Definition: AtomicOrdering.h:104
llvm::MinAlign
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:614
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:316
llvm::GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:332
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &) const
Definition: InstructionSelector.h:456
llvm::GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:308
llvm::GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode...
Definition: InstructionSelector.h:357
llvm::GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:263
Constants.h
This file contains the declarations for the subclasses of Constant, which represent the different fla...
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:318
llvm::GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:156
TypeID
Type::TypeID TypeID
Definition: Mips16HardFloat.cpp:102
llvm::GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:140
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise...
Definition: InstructionSelectorImpl.h:48
llvm::GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:302
llvm::GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:185
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:155
llvm::CodeGenCoverage::setCovered
void setCovered(uint64_t RuleID)
Definition: CodeGenCoverage.cpp:34
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:228
llvm::GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:314
llvm::SmallVectorBase::size
size_t size() const
Definition: SmallVector.h:52
llvm::GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:226
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:135
llvm::MachineMemOperand::getAlignment
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1066
llvm::GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:282
llvm::GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:180
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:48
add
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:243
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:430
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:50
llvm::SmallVector
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:576
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:108
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
llvm::GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:257
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:111
llvm::GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:287
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:69
llvm::GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:268
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:93
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Definition: MachineRegisterInfo.h:52
Success
#define Success
Definition: AArch64Disassembler.cpp:241
llvm::GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:238
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Optional::hasValue
bool hasValue() const
Definition: Optional.h:259
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:444
llvm::SmallVectorBase::empty
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
llvm::GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:89
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
llvm::GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:198
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:325
Size
uint32_t Size
Definition: Profile.cpp:46
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:753
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:314
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:81
llvm::Value
LLVM Value Representation.
Definition: Value.h:73
llvm::GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:219
llvm::GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:291
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:448
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:452
raw_ostream.h
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:353
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:535
llvm::GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:230
llvm::GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:192
llvm::GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:133
llvm::RegisterBankInfo::getRegBankFromRegClass
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.
Definition: RegisterBankInfo.h:602
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:74
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:344
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