15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
48 template <
class TgtInstructionSelector,
class PredicateBitset,
49 class ComplexMatcherMemFn,
class CustomRendererFn>
63 bool NoFPException = !State.
MIs[0]->getDesc().mayRaiseFPException();
67 enum RejectAction { RejectAndGiveUp, RejectAndResume };
68 auto handleReject = [&]() -> RejectAction {
70 dbgs() << CurrentIdx <<
": Rejected\n");
71 if (OnFailResumeAt.empty())
72 return RejectAndGiveUp;
75 dbgs() << CurrentIdx <<
": Resume at " << CurrentIdx <<
" ("
76 << OnFailResumeAt.size() <<
" try-blocks remain)\n");
77 return RejectAndResume;
81 for (
auto MIB : OutMIs) {
85 if (NoFPException && MIB->mayRaiseFPException())
87 MIB.setMIFlags(MIBFlags);
94 assert(CurrentIdx != ~0u &&
"Invalid MatchTable index");
95 int64_t MatcherOpcode = MatchTable[CurrentIdx++];
96 switch (MatcherOpcode) {
99 dbgs() << CurrentIdx <<
": Begin try-block\n");
100 OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
105 int64_t NewInsnID = MatchTable[CurrentIdx++];
106 int64_t InsnID = MatchTable[CurrentIdx++];
107 int64_t OpIdx = MatchTable[CurrentIdx++];
111 assert(NewInsnID != 0 &&
"Refusing to modify MIs[0]");
116 dbgs() << CurrentIdx <<
": Not a register\n");
117 if (handleReject() == RejectAndGiveUp)
123 dbgs() << CurrentIdx <<
": Is a physical register\n");
124 if (handleReject() == RejectAndGiveUp)
130 if ((
size_t)NewInsnID < State.
MIs.size())
131 State.
MIs[NewInsnID] = NewMI;
133 assert((
size_t)NewInsnID == State.
MIs.size() &&
134 "Expected to store MIs in order");
135 State.
MIs.push_back(NewMI);
138 dbgs() << CurrentIdx <<
": MIs[" << NewInsnID
139 <<
"] = GIM_RecordInsn(" << InsnID <<
", " << OpIdx
145 int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
148 <<
": GIM_CheckFeatures(ExpectedBitsetID="
149 << ExpectedBitsetID <<
")\n");
150 if ((AvailableFeatures & ISelInfo.
FeatureBitsets[ExpectedBitsetID]) !=
152 if (handleReject() == RejectAndGiveUp)
160 int64_t InsnID = MatchTable[CurrentIdx++];
161 int64_t Expected0 = MatchTable[CurrentIdx++];
162 int64_t Expected1 = -1;
164 Expected1 = MatchTable[CurrentIdx++];
166 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
167 unsigned Opcode = State.
MIs[InsnID]->getOpcode();
170 dbgs() << CurrentIdx <<
": GIM_CheckOpcode(MIs[" << InsnID
171 <<
"], ExpectedOpcode=" << Expected0;
173 dbgs() <<
" || " << Expected1;
174 dbgs() <<
") // Got=" << Opcode <<
"\n";
177 if (Opcode != Expected0 && Opcode != Expected1) {
178 if (handleReject() == RejectAndGiveUp)
184 int64_t InsnID = MatchTable[CurrentIdx++];
185 int64_t LowerBound = MatchTable[CurrentIdx++];
186 int64_t UpperBound = MatchTable[CurrentIdx++];
187 int64_t Default = MatchTable[CurrentIdx++];
189 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
190 const int64_t Opcode = State.
MIs[InsnID]->getOpcode();
193 dbgs() << CurrentIdx <<
": GIM_SwitchOpcode(MIs[" << InsnID <<
"], ["
194 << LowerBound <<
", " << UpperBound <<
"), Default=" << Default
195 <<
", JumpTable...) // Got=" << Opcode <<
"\n";
197 if (Opcode < LowerBound || UpperBound <= Opcode) {
198 CurrentIdx = Default;
201 CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
203 CurrentIdx = Default;
206 OnFailResumeAt.push_back(Default);
211 int64_t InsnID = MatchTable[CurrentIdx++];
212 int64_t OpIdx = MatchTable[CurrentIdx++];
213 int64_t LowerBound = MatchTable[CurrentIdx++];
214 int64_t UpperBound = MatchTable[CurrentIdx++];
215 int64_t Default = MatchTable[CurrentIdx++];
217 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
221 dbgs() << CurrentIdx <<
": GIM_SwitchType(MIs[" << InsnID
222 <<
"]->getOperand(" << OpIdx <<
"), [" << LowerBound <<
", "
223 << UpperBound <<
"), Default=" << Default
224 <<
", JumpTable...) // Got=";
226 dbgs() <<
"Not a VReg\n";
231 CurrentIdx = Default;
235 const auto TyI = ISelInfo.
TypeIDMap.find(Ty);
237 CurrentIdx = Default;
240 const int64_t
TypeID = TyI->second;
242 CurrentIdx = Default;
245 CurrentIdx = MatchTable[CurrentIdx + (
TypeID - LowerBound)];
247 CurrentIdx = Default;
250 OnFailResumeAt.push_back(Default);
255 int64_t InsnID = MatchTable[CurrentIdx++];
256 int64_t
Expected = MatchTable[CurrentIdx++];
258 dbgs() << CurrentIdx <<
": GIM_CheckNumOperands(MIs["
259 << InsnID <<
"], Expected=" <<
Expected <<
")\n");
260 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
261 if (State.
MIs[InsnID]->getNumOperands() !=
Expected) {
262 if (handleReject() == RejectAndGiveUp)
269 int64_t InsnID = MatchTable[CurrentIdx++];
271 ? MatchTable[CurrentIdx++]
273 int64_t
Predicate = MatchTable[CurrentIdx++];
275 dbgs() << CurrentIdx <<
": GIM_CheckImmPredicate(MIs["
276 << InsnID <<
"]->getOperand(" << OpIdx
277 <<
"), Predicate=" <<
Predicate <<
")\n");
278 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
279 assert((State.
MIs[InsnID]->getOperand(OpIdx).isImm() ||
280 State.
MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
281 "Expected immediate operand");
284 if (State.
MIs[InsnID]->getOperand(OpIdx).isCImm())
285 Value = State.
MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
286 else if (State.
MIs[InsnID]->getOperand(OpIdx).isImm())
287 Value = State.
MIs[InsnID]->getOperand(OpIdx).getImm();
292 if (handleReject() == RejectAndGiveUp)
297 int64_t InsnID = MatchTable[CurrentIdx++];
298 int64_t
Predicate = MatchTable[CurrentIdx++];
301 << CurrentIdx <<
": GIM_CheckAPIntImmPredicate(MIs["
302 << InsnID <<
"], Predicate=" <<
Predicate <<
")\n");
303 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
304 assert(State.
MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
305 "Expected G_CONSTANT");
308 if (State.
MIs[InsnID]->getOperand(1).isCImm())
309 Value = State.
MIs[InsnID]->getOperand(1).getCImm()->getValue();
314 if (handleReject() == RejectAndGiveUp)
319 int64_t InsnID = MatchTable[CurrentIdx++];
320 int64_t
Predicate = MatchTable[CurrentIdx++];
323 << CurrentIdx <<
": GIM_CheckAPFloatImmPredicate(MIs["
324 << InsnID <<
"], Predicate=" <<
Predicate <<
")\n");
325 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
326 assert(State.
MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
327 "Expected G_FCONSTANT");
328 assert(State.
MIs[InsnID]->getOperand(1).isFPImm() &&
"Expected FPImm operand");
330 APFloat Value = State.
MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
333 if (handleReject() == RejectAndGiveUp)
339 int64_t InsnID = MatchTable[CurrentIdx++];
343 <<
": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
344 << InsnID <<
"])\n");
345 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
348 assert((
MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
349 MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
350 "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
354 if (handleReject() == RejectAndGiveUp)
359 if (handleReject() == RejectAndGiveUp)
367 int64_t InsnID = MatchTable[CurrentIdx++];
368 int64_t
Predicate = MatchTable[CurrentIdx++];
371 << CurrentIdx <<
": GIM_CheckCxxPredicate(MIs["
372 << InsnID <<
"], Predicate=" <<
Predicate <<
")\n");
373 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
378 if (handleReject() == RejectAndGiveUp)
383 int64_t InsnID = MatchTable[CurrentIdx++];
386 dbgs() << CurrentIdx <<
": GIM_CheckHasNoUse(MIs["
390 assert(
MI &&
"Used insn before defined");
391 assert(
MI->getNumDefs() > 0 &&
"No defs");
392 const Register Res =
MI->getOperand(0).getReg();
394 if (!
MRI.use_nodbg_empty(Res)) {
395 if (handleReject() == RejectAndGiveUp)
402 int64_t InsnID = MatchTable[CurrentIdx++];
405 dbgs() << CurrentIdx <<
": GIM_CheckAtomicOrdering(MIs["
406 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
407 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
408 if (!State.
MIs[InsnID]->hasOneMemOperand())
409 if (handleReject() == RejectAndGiveUp)
412 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
413 if (MMO->getMergedOrdering() != Ordering)
414 if (handleReject() == RejectAndGiveUp)
419 int64_t InsnID = MatchTable[CurrentIdx++];
423 <<
": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
424 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
425 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
426 if (!State.
MIs[InsnID]->hasOneMemOperand())
427 if (handleReject() == RejectAndGiveUp)
430 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
432 if (handleReject() == RejectAndGiveUp)
437 int64_t InsnID = MatchTable[CurrentIdx++];
441 <<
": GIM_CheckAtomicOrderingWeakerThan(MIs["
442 << InsnID <<
"], " << (
uint64_t)Ordering <<
")\n");
443 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
444 if (!State.
MIs[InsnID]->hasOneMemOperand())
445 if (handleReject() == RejectAndGiveUp)
448 for (
const auto &MMO : State.
MIs[InsnID]->memoperands())
450 if (handleReject() == RejectAndGiveUp)
455 int64_t InsnID = MatchTable[CurrentIdx++];
456 int64_t MMOIdx = MatchTable[CurrentIdx++];
458 const int NumAddrSpace = MatchTable[CurrentIdx++];
460 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
461 if (handleReject() == RejectAndGiveUp)
468 const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
471 = *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
475 for (
int I = 0;
I != NumAddrSpace; ++
I) {
476 unsigned AddrSpace = MatchTable[CurrentIdx++];
479 dbgs() <<
"addrspace(" << MMOAddrSpace <<
") vs "
480 << AddrSpace <<
'\n');
482 if (AddrSpace == MMOAddrSpace) {
488 CurrentIdx = LastIdx;
489 if (!
Success && handleReject() == RejectAndGiveUp)
494 int64_t InsnID = MatchTable[CurrentIdx++];
495 int64_t MMOIdx = MatchTable[CurrentIdx++];
496 unsigned MinAlign = MatchTable[CurrentIdx++];
498 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
500 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
501 if (handleReject() == RejectAndGiveUp)
507 = *(State.
MIs[InsnID]->memoperands_begin() + MMOIdx);
509 dbgs() << CurrentIdx <<
": GIM_CheckMemoryAlignment"
510 <<
"(MIs[" << InsnID <<
"]->memoperands() + " << MMOIdx
511 <<
")->getAlignment() >= " <<
MinAlign <<
")\n");
518 int64_t InsnID = MatchTable[CurrentIdx++];
519 int64_t MMOIdx = MatchTable[CurrentIdx++];
520 uint64_t Size = MatchTable[CurrentIdx++];
524 <<
": GIM_CheckMemorySizeEqual(MIs[" << InsnID
525 <<
"]->memoperands() + " << MMOIdx
526 <<
", Size=" << Size <<
")\n");
527 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
529 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
530 if (handleReject() == RejectAndGiveUp)
541 if (handleReject() == RejectAndGiveUp)
549 int64_t InsnID = MatchTable[CurrentIdx++];
550 int64_t MMOIdx = MatchTable[CurrentIdx++];
551 int64_t OpIdx = MatchTable[CurrentIdx++];
555 dbgs() << CurrentIdx <<
": GIM_CheckMemorySize"
561 <<
"LLT(MIs[" << InsnID <<
"]->memoperands() + " << MMOIdx
562 <<
", OpIdx=" << OpIdx <<
")\n");
563 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
568 dbgs() << CurrentIdx <<
": Not a register\n");
569 if (handleReject() == RejectAndGiveUp)
574 if (State.
MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
575 if (handleReject() == RejectAndGiveUp)
582 unsigned Size =
MRI.getType(MO.
getReg()).getSizeInBits();
585 if (handleReject() == RejectAndGiveUp)
589 if (handleReject() == RejectAndGiveUp)
593 if (handleReject() == RejectAndGiveUp)
599 int64_t InsnID = MatchTable[CurrentIdx++];
600 int64_t OpIdx = MatchTable[CurrentIdx++];
601 int64_t
TypeID = MatchTable[CurrentIdx++];
603 dbgs() << CurrentIdx <<
": GIM_CheckType(MIs[" << InsnID
604 <<
"]->getOperand(" << OpIdx
605 <<
"), TypeID=" <<
TypeID <<
")\n");
606 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
610 if (handleReject() == RejectAndGiveUp)
616 int64_t InsnID = MatchTable[CurrentIdx++];
617 int64_t OpIdx = MatchTable[CurrentIdx++];
618 uint64_t SizeInBits = MatchTable[CurrentIdx++];
621 dbgs() << CurrentIdx <<
": GIM_CheckPointerToAny(MIs["
622 << InsnID <<
"]->getOperand(" << OpIdx
623 <<
"), SizeInBits=" << SizeInBits <<
")\n");
624 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
629 if (SizeInBits == 0) {
635 assert(SizeInBits != 0 &&
"Pointer size must be known");
639 if (handleReject() == RejectAndGiveUp)
641 }
else if (handleReject() == RejectAndGiveUp)
647 int64_t InsnID = MatchTable[CurrentIdx++];
648 int64_t OpIdx = MatchTable[CurrentIdx++];
649 uint64_t StoreIdx = MatchTable[CurrentIdx++];
652 dbgs() << CurrentIdx <<
": GIM_RecordNamedOperand(MIs["
653 << InsnID <<
"]->getOperand(" << OpIdx
654 <<
"), StoreIdx=" << StoreIdx <<
")\n");
655 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
661 int64_t InsnID = MatchTable[CurrentIdx++];
662 int64_t OpIdx = MatchTable[CurrentIdx++];
663 int64_t RCEnum = MatchTable[CurrentIdx++];
665 dbgs() << CurrentIdx <<
": GIM_CheckRegBankForClass(MIs["
666 << InsnID <<
"]->getOperand(" << OpIdx
667 <<
"), RCEnum=" << RCEnum <<
")\n");
668 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
674 if (handleReject() == RejectAndGiveUp)
681 int64_t InsnID = MatchTable[CurrentIdx++];
682 int64_t OpIdx = MatchTable[CurrentIdx++];
683 int64_t RendererID = MatchTable[CurrentIdx++];
684 int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
686 dbgs() << CurrentIdx <<
": State.Renderers[" << RendererID
687 <<
"] = GIM_CheckComplexPattern(MIs[" << InsnID
688 <<
"]->getOperand(" << OpIdx
689 <<
"), ComplexPredicateID=" << ComplexPredicateID
691 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
695 State.
MIs[InsnID]->getOperand(OpIdx));
699 if (handleReject() == RejectAndGiveUp)
705 int64_t InsnID = MatchTable[CurrentIdx++];
706 int64_t OpIdx = MatchTable[CurrentIdx++];
707 int64_t
Value = MatchTable[CurrentIdx++];
709 dbgs() << CurrentIdx <<
": GIM_CheckConstantInt(MIs["
710 << InsnID <<
"]->getOperand(" << OpIdx
711 <<
"), Value=" <<
Value <<
")\n");
712 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
720 if (handleReject() == RejectAndGiveUp)
723 }
else if (handleReject() == RejectAndGiveUp)
730 int64_t InsnID = MatchTable[CurrentIdx++];
731 int64_t OpIdx = MatchTable[CurrentIdx++];
732 int64_t
Value = MatchTable[CurrentIdx++];
734 dbgs() << CurrentIdx <<
": GIM_CheckLiteralInt(MIs["
735 << InsnID <<
"]->getOperand(" << OpIdx
736 <<
"), Value=" <<
Value <<
")\n");
737 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
745 if (handleReject() == RejectAndGiveUp)
752 int64_t InsnID = MatchTable[CurrentIdx++];
753 int64_t OpIdx = MatchTable[CurrentIdx++];
754 int64_t
Value = MatchTable[CurrentIdx++];
756 dbgs() << CurrentIdx <<
": GIM_CheckIntrinsicID(MIs["
757 << InsnID <<
"]->getOperand(" << OpIdx
758 <<
"), Value=" <<
Value <<
")\n");
759 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
762 if (handleReject() == RejectAndGiveUp)
767 int64_t InsnID = MatchTable[CurrentIdx++];
768 int64_t OpIdx = MatchTable[CurrentIdx++];
769 int64_t
Value = MatchTable[CurrentIdx++];
771 dbgs() << CurrentIdx <<
": GIM_CheckCmpPredicate(MIs["
772 << InsnID <<
"]->getOperand(" << OpIdx
773 <<
"), Value=" <<
Value <<
")\n");
774 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
777 if (handleReject() == RejectAndGiveUp)
782 int64_t InsnID = MatchTable[CurrentIdx++];
783 int64_t OpIdx = MatchTable[CurrentIdx++];
785 dbgs() << CurrentIdx <<
": GIM_CheckIsMBB(MIs[" << InsnID
786 <<
"]->getOperand(" << OpIdx <<
"))\n");
787 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
788 if (!State.
MIs[InsnID]->getOperand(OpIdx).isMBB()) {
789 if (handleReject() == RejectAndGiveUp)
795 int64_t InsnID = MatchTable[CurrentIdx++];
796 int64_t OpIdx = MatchTable[CurrentIdx++];
798 dbgs() << CurrentIdx <<
": GIM_CheckIsImm(MIs[" << InsnID
799 <<
"]->getOperand(" << OpIdx <<
"))\n");
800 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
801 if (!State.
MIs[InsnID]->getOperand(OpIdx).isImm()) {
802 if (handleReject() == RejectAndGiveUp)
808 int64_t InsnID = MatchTable[CurrentIdx++];
810 dbgs() << CurrentIdx <<
": GIM_CheckIsSafeToFold(MIs["
811 << InsnID <<
"])\n");
812 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
814 if (handleReject() == RejectAndGiveUp)
820 int64_t InsnID = MatchTable[CurrentIdx++];
821 int64_t OpIdx = MatchTable[CurrentIdx++];
822 int64_t OtherInsnID = MatchTable[CurrentIdx++];
823 int64_t OtherOpIdx = MatchTable[CurrentIdx++];
825 dbgs() << CurrentIdx <<
": GIM_CheckIsSameOperand(MIs["
826 << InsnID <<
"][" << OpIdx <<
"], MIs["
827 << OtherInsnID <<
"][" << OtherOpIdx <<
"])\n");
828 assert(State.
MIs[InsnID] !=
nullptr &&
"Used insn before defined");
829 assert(State.
MIs[OtherInsnID] !=
nullptr &&
"Used insn before defined");
830 if (!State.
MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
831 State.
MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
832 if (handleReject() == RejectAndGiveUp)
839 dbgs() << CurrentIdx <<
": GIM_Reject\n");
840 if (handleReject() == RejectAndGiveUp)
845 int64_t OldInsnID = MatchTable[CurrentIdx++];
846 uint64_t NewInsnID = MatchTable[CurrentIdx++];
847 int64_t NewOpcode = MatchTable[CurrentIdx++];
848 if (NewInsnID >= OutMIs.size())
849 OutMIs.
resize(NewInsnID + 1);
852 State.
MIs[OldInsnID]);
853 OutMIs[NewInsnID]->setDesc(
TII.get(NewOpcode));
855 dbgs() << CurrentIdx <<
": GIR_MutateOpcode(OutMIs["
856 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
857 << NewOpcode <<
")\n");
862 uint64_t NewInsnID = MatchTable[CurrentIdx++];
863 int64_t Opcode = MatchTable[CurrentIdx++];
864 if (NewInsnID >= OutMIs.size())
865 OutMIs.
resize(NewInsnID + 1);
867 OutMIs[NewInsnID] =
BuildMI(*State.
MIs[0]->getParent(), State.
MIs[0],
870 dbgs() << CurrentIdx <<
": GIR_BuildMI(OutMIs["
871 << NewInsnID <<
"], " << Opcode <<
")\n");
876 int64_t NewInsnID = MatchTable[CurrentIdx++];
877 int64_t OldInsnID = MatchTable[CurrentIdx++];
878 int64_t OpIdx = MatchTable[CurrentIdx++];
879 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
880 OutMIs[NewInsnID].add(State.
MIs[OldInsnID]->getOperand(OpIdx));
883 << CurrentIdx <<
": GIR_Copy(OutMIs[" << NewInsnID
884 <<
"], MIs[" << OldInsnID <<
"], " << OpIdx <<
")\n");
889 int64_t NewInsnID = MatchTable[CurrentIdx++];
890 int64_t OldInsnID = MatchTable[CurrentIdx++];
891 int64_t OpIdx = MatchTable[CurrentIdx++];
892 int64_t ZeroReg = MatchTable[CurrentIdx++];
893 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
896 OutMIs[NewInsnID].addReg(ZeroReg);
898 OutMIs[NewInsnID].add(MO);
900 dbgs() << CurrentIdx <<
": GIR_CopyOrAddZeroReg(OutMIs["
901 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
902 << OpIdx <<
", " << ZeroReg <<
")\n");
907 int64_t NewInsnID = MatchTable[CurrentIdx++];
908 int64_t OldInsnID = MatchTable[CurrentIdx++];
909 int64_t OpIdx = MatchTable[CurrentIdx++];
910 int64_t SubRegIdx = MatchTable[CurrentIdx++];
911 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
912 OutMIs[NewInsnID].addReg(State.
MIs[OldInsnID]->getOperand(OpIdx).getReg(),
915 dbgs() << CurrentIdx <<
": GIR_CopySubReg(OutMIs["
916 << NewInsnID <<
"], MIs[" << OldInsnID <<
"], "
917 << OpIdx <<
", " << SubRegIdx <<
")\n");
922 int64_t InsnID = MatchTable[CurrentIdx++];
923 int64_t RegNum = MatchTable[CurrentIdx++];
924 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
927 dbgs() << CurrentIdx <<
": GIR_AddImplicitDef(OutMIs["
928 << InsnID <<
"], " << RegNum <<
")\n");
933 int64_t InsnID = MatchTable[CurrentIdx++];
934 int64_t RegNum = MatchTable[CurrentIdx++];
935 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
938 dbgs() << CurrentIdx <<
": GIR_AddImplicitUse(OutMIs["
939 << InsnID <<
"], " << RegNum <<
")\n");
944 int64_t InsnID = MatchTable[CurrentIdx++];
945 int64_t RegNum = MatchTable[CurrentIdx++];
946 uint64_t RegFlags = MatchTable[CurrentIdx++];
947 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
948 OutMIs[InsnID].addReg(RegNum, RegFlags);
951 dbgs() << CurrentIdx <<
": GIR_AddRegister(OutMIs["
952 << InsnID <<
"], " << RegNum <<
", " << RegFlags <<
")\n");
958 int64_t InsnID = MatchTable[CurrentIdx++];
959 int64_t TempRegID = MatchTable[CurrentIdx++];
960 uint64_t TempRegFlags = MatchTable[CurrentIdx++];
963 SubReg = MatchTable[CurrentIdx++];
965 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
969 dbgs() << CurrentIdx <<
": GIR_AddTempRegister(OutMIs["
970 << InsnID <<
"], TempRegisters[" << TempRegID
974 dbgs() <<
", " << TempRegFlags <<
")\n");
979 int64_t InsnID = MatchTable[CurrentIdx++];
980 int64_t
Imm = MatchTable[CurrentIdx++];
981 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
982 OutMIs[InsnID].addImm(
Imm);
984 dbgs() << CurrentIdx <<
": GIR_AddImm(OutMIs[" << InsnID
985 <<
"], " <<
Imm <<
")\n");
990 int64_t InsnID = MatchTable[CurrentIdx++];
991 int64_t RendererID = MatchTable[CurrentIdx++];
992 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
993 for (
const auto &RenderOpFn : State.
Renderers[RendererID])
994 RenderOpFn(OutMIs[InsnID]);
996 dbgs() << CurrentIdx <<
": GIR_ComplexRenderer(OutMIs["
997 << InsnID <<
"], " << RendererID <<
")\n");
1001 int64_t InsnID = MatchTable[CurrentIdx++];
1002 int64_t RendererID = MatchTable[CurrentIdx++];
1003 int64_t RenderOpID = MatchTable[CurrentIdx++];
1004 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1005 State.
Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
1007 dbgs() << CurrentIdx
1008 <<
": GIR_ComplexSubOperandRenderer(OutMIs["
1009 << InsnID <<
"], " << RendererID <<
", "
1010 << RenderOpID <<
")\n");
1015 int64_t NewInsnID = MatchTable[CurrentIdx++];
1016 int64_t OldInsnID = MatchTable[CurrentIdx++];
1017 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1018 assert(State.
MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
"Expected G_CONSTANT");
1019 if (State.
MIs[OldInsnID]->getOperand(1).isCImm()) {
1020 OutMIs[NewInsnID].addImm(
1021 State.
MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
1022 }
else if (State.
MIs[OldInsnID]->getOperand(1).isImm())
1023 OutMIs[NewInsnID].add(State.
MIs[OldInsnID]->getOperand(1));
1027 dbgs() << CurrentIdx <<
": GIR_CopyConstantAsSImm(OutMIs["
1028 << NewInsnID <<
"], MIs[" << OldInsnID <<
"])\n");
1034 int64_t NewInsnID = MatchTable[CurrentIdx++];
1035 int64_t OldInsnID = MatchTable[CurrentIdx++];
1036 assert(OutMIs[NewInsnID] &&
"Attempted to add to undefined instruction");
1037 assert(State.
MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
"Expected G_FCONSTANT");
1038 if (State.
MIs[OldInsnID]->getOperand(1).isFPImm())
1039 OutMIs[NewInsnID].addFPImm(
1040 State.
MIs[OldInsnID]->getOperand(1).getFPImm());
1044 dbgs() << CurrentIdx <<
": GIR_CopyFPConstantAsFPImm(OutMIs["
1045 << NewInsnID <<
"], MIs[" << OldInsnID <<
"])\n");
1050 int64_t InsnID = MatchTable[CurrentIdx++];
1051 int64_t OldInsnID = MatchTable[CurrentIdx++];
1052 int64_t RendererFnID = MatchTable[CurrentIdx++];
1053 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1055 dbgs() << CurrentIdx <<
": GIR_CustomRenderer(OutMIs["
1056 << InsnID <<
"], MIs[" << OldInsnID <<
"], "
1057 << RendererFnID <<
")\n");
1059 OutMIs[InsnID], *State.
MIs[OldInsnID],
1064 int64_t InsnID = MatchTable[CurrentIdx++];
1065 int64_t OldInsnID = MatchTable[CurrentIdx++];
1066 int64_t OpIdx = MatchTable[CurrentIdx++];
1067 int64_t RendererFnID = MatchTable[CurrentIdx++];
1068 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1072 dbgs() << CurrentIdx <<
": GIR_CustomOperandRenderer(OutMIs["
1073 << InsnID <<
"], MIs[" << OldInsnID <<
"]->getOperand("
1075 << RendererFnID <<
")\n");
1077 *State.
MIs[OldInsnID],
1082 int64_t InsnID = MatchTable[CurrentIdx++];
1083 int64_t OpIdx = MatchTable[CurrentIdx++];
1084 int64_t RCEnum = MatchTable[CurrentIdx++];
1085 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1093 dbgs() << CurrentIdx <<
": GIR_ConstrainOperandRC(OutMIs["
1094 << InsnID <<
"], " << OpIdx <<
", " << RCEnum
1100 int64_t InsnID = MatchTable[CurrentIdx++];
1101 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1105 dbgs() << CurrentIdx
1106 <<
": GIR_ConstrainSelectedInstOperands(OutMIs["
1107 << InsnID <<
"])\n");
1112 int64_t InsnID = MatchTable[CurrentIdx++];
1113 assert(OutMIs[InsnID] &&
"Attempted to add to undefined instruction");
1116 dbgs() << CurrentIdx <<
": GIR_MergeMemOperands(OutMIs["
1119 while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
1122 dbgs() <<
", MIs[" << MergeInsnID <<
"]");
1123 for (
const auto &MMO : State.
MIs[MergeInsnID]->memoperands())
1124 OutMIs[InsnID].addMemOperand(MMO);
1131 int64_t InsnID = MatchTable[CurrentIdx++];
1133 "Attempted to erase an undefined instruction");
1134 State.
MIs[InsnID]->eraseFromParent();
1136 dbgs() << CurrentIdx <<
": GIR_EraseFromParent(MIs["
1137 << InsnID <<
"])\n");
1142 int64_t TempRegID = MatchTable[CurrentIdx++];
1143 int64_t
TypeID = MatchTable[CurrentIdx++];
1148 dbgs() << CurrentIdx <<
": TempRegs[" << TempRegID
1149 <<
"] = GIR_MakeTempReg(" <<
TypeID <<
")\n");
1154 int64_t RuleID = MatchTable[CurrentIdx++];
1159 << CurrentIdx <<
": GIR_Coverage(" << RuleID <<
")");
1165 dbgs() << CurrentIdx <<
": GIR_Done\n");
1166 propagateFlags(OutMIs);
1177 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H