LLVM  15.0.0git
InstructionSelectorImpl.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
17 
18 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DataLayout.h"
31 #include "llvm/Support/Debug.h"
34 #include <cassert>
35 #include <cstddef>
36 #include <cstdint>
37 
38 namespace llvm {
39 
40 /// GlobalISel PatFrag Predicates
41 enum {
46 };
47 
48 template <class TgtInstructionSelector, class PredicateBitset,
49  class ComplexMatcherMemFn, class CustomRendererFn>
51  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
53  &ISelInfo,
54  const int64_t *MatchTable, const TargetInstrInfo &TII,
56  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
57  CodeGenCoverage &CoverageInfo) const {
58 
59  uint64_t CurrentIdx = 0;
60  SmallVector<uint64_t, 4> OnFailResumeAt;
61 
62  // Bypass the flag check on the instruction, and only look at the MCInstrDesc.
63  bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
64 
65  const uint16_t Flags = State.MIs[0]->getFlags();
66 
67  enum RejectAction { RejectAndGiveUp, RejectAndResume };
68  auto handleReject = [&]() -> RejectAction {
70  dbgs() << CurrentIdx << ": Rejected\n");
71  if (OnFailResumeAt.empty())
72  return RejectAndGiveUp;
73  CurrentIdx = OnFailResumeAt.pop_back_val();
75  dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " ("
76  << OnFailResumeAt.size() << " try-blocks remain)\n");
77  return RejectAndResume;
78  };
79 
80  auto propagateFlags = [=](NewMIVector &OutMIs) {
81  for (auto MIB : OutMIs) {
82  // Set the NoFPExcept flag when no original matched instruction could
83  // raise an FP exception, but the new instruction potentially might.
84  uint16_t MIBFlags = Flags;
85  if (NoFPException && MIB->mayRaiseFPException())
86  MIBFlags |= MachineInstr::NoFPExcept;
87  MIB.setMIFlags(MIBFlags);
88  }
89 
90  return true;
91  };
92 
93  while (true) {
94  assert(CurrentIdx != ~0u && "Invalid MatchTable index");
95  int64_t MatcherOpcode = MatchTable[CurrentIdx++];
96  switch (MatcherOpcode) {
97  case GIM_Try: {
99  dbgs() << CurrentIdx << ": Begin try-block\n");
100  OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
101  break;
102  }
103 
104  case GIM_RecordInsn: {
105  int64_t NewInsnID = MatchTable[CurrentIdx++];
106  int64_t InsnID = MatchTable[CurrentIdx++];
107  int64_t OpIdx = MatchTable[CurrentIdx++];
108 
109  // As an optimisation we require that MIs[0] is always the root. Refuse
110  // any attempt to modify it.
111  assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
112 
113  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
114  if (!MO.isReg()) {
116  dbgs() << CurrentIdx << ": Not a register\n");
117  if (handleReject() == RejectAndGiveUp)
118  return false;
119  break;
120  }
123  dbgs() << CurrentIdx << ": Is a physical register\n");
124  if (handleReject() == RejectAndGiveUp)
125  return false;
126  break;
127  }
128 
129  MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());
130  if ((size_t)NewInsnID < State.MIs.size())
131  State.MIs[NewInsnID] = NewMI;
132  else {
133  assert((size_t)NewInsnID == State.MIs.size() &&
134  "Expected to store MIs in order");
135  State.MIs.push_back(NewMI);
136  }
138  dbgs() << CurrentIdx << ": MIs[" << NewInsnID
139  << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
140  << ")\n");
141  break;
142  }
143 
144  case GIM_CheckFeatures: {
145  int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
147  dbgs() << CurrentIdx
148  << ": GIM_CheckFeatures(ExpectedBitsetID="
149  << ExpectedBitsetID << ")\n");
150  if ((AvailableFeatures & ISelInfo.FeatureBitsets[ExpectedBitsetID]) !=
151  ISelInfo.FeatureBitsets[ExpectedBitsetID]) {
152  if (handleReject() == RejectAndGiveUp)
153  return false;
154  }
155  break;
156  }
157 
158  case GIM_CheckOpcode:
160  int64_t InsnID = MatchTable[CurrentIdx++];
161  int64_t Expected0 = MatchTable[CurrentIdx++];
162  int64_t Expected1 = -1;
163  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
164  Expected1 = MatchTable[CurrentIdx++];
165 
166  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
167  unsigned Opcode = State.MIs[InsnID]->getOpcode();
168 
170  dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
171  << "], ExpectedOpcode=" << Expected0;
172  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
173  dbgs() << " || " << Expected1;
174  dbgs() << ") // Got=" << Opcode << "\n";
175  );
176 
177  if (Opcode != Expected0 && Opcode != Expected1) {
178  if (handleReject() == RejectAndGiveUp)
179  return false;
180  }
181  break;
182  }
183  case GIM_SwitchOpcode: {
184  int64_t InsnID = MatchTable[CurrentIdx++];
185  int64_t LowerBound = MatchTable[CurrentIdx++];
186  int64_t UpperBound = MatchTable[CurrentIdx++];
187  int64_t Default = MatchTable[CurrentIdx++];
188 
189  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
190  const int64_t Opcode = State.MIs[InsnID]->getOpcode();
191 
193  dbgs() << CurrentIdx << ": GIM_SwitchOpcode(MIs[" << InsnID << "], ["
194  << LowerBound << ", " << UpperBound << "), Default=" << Default
195  << ", JumpTable...) // Got=" << Opcode << "\n";
196  });
197  if (Opcode < LowerBound || UpperBound <= Opcode) {
198  CurrentIdx = Default;
199  break;
200  }
201  CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
202  if (!CurrentIdx) {
203  CurrentIdx = Default;
204  break;
205  }
206  OnFailResumeAt.push_back(Default);
207  break;
208  }
209 
210  case GIM_SwitchType: {
211  int64_t InsnID = MatchTable[CurrentIdx++];
212  int64_t OpIdx = MatchTable[CurrentIdx++];
213  int64_t LowerBound = MatchTable[CurrentIdx++];
214  int64_t UpperBound = MatchTable[CurrentIdx++];
215  int64_t Default = MatchTable[CurrentIdx++];
216 
217  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
218  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
219 
221  dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
222  << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
223  << UpperBound << "), Default=" << Default
224  << ", JumpTable...) // Got=";
225  if (!MO.isReg())
226  dbgs() << "Not a VReg\n";
227  else
228  dbgs() << MRI.getType(MO.getReg()) << "\n";
229  });
230  if (!MO.isReg()) {
231  CurrentIdx = Default;
232  break;
233  }
234  const LLT Ty = MRI.getType(MO.getReg());
235  const auto TyI = ISelInfo.TypeIDMap.find(Ty);
236  if (TyI == ISelInfo.TypeIDMap.end()) {
237  CurrentIdx = Default;
238  break;
239  }
240  const int64_t TypeID = TyI->second;
241  if (TypeID < LowerBound || UpperBound <= TypeID) {
242  CurrentIdx = Default;
243  break;
244  }
245  CurrentIdx = MatchTable[CurrentIdx + (TypeID - LowerBound)];
246  if (!CurrentIdx) {
247  CurrentIdx = Default;
248  break;
249  }
250  OnFailResumeAt.push_back(Default);
251  break;
252  }
253 
254  case GIM_CheckNumOperands: {
255  int64_t InsnID = MatchTable[CurrentIdx++];
256  int64_t Expected = MatchTable[CurrentIdx++];
258  dbgs() << CurrentIdx << ": GIM_CheckNumOperands(MIs["
259  << InsnID << "], Expected=" << Expected << ")\n");
260  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
261  if (State.MIs[InsnID]->getNumOperands() != Expected) {
262  if (handleReject() == RejectAndGiveUp)
263  return false;
264  }
265  break;
266  }
269  int64_t InsnID = MatchTable[CurrentIdx++];
270  int64_t OpIdx = MatcherOpcode == GIM_CheckImmOperandPredicate
271  ? MatchTable[CurrentIdx++]
272  : 1;
273  int64_t Predicate = MatchTable[CurrentIdx++];
275  dbgs() << CurrentIdx << ": GIM_CheckImmPredicate(MIs["
276  << InsnID << "]->getOperand(" << OpIdx
277  << "), Predicate=" << Predicate << ")\n");
278  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
279  assert((State.MIs[InsnID]->getOperand(OpIdx).isImm() ||
280  State.MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
281  "Expected immediate operand");
282  assert(Predicate > GIPFP_I64_Invalid && "Expected a valid predicate");
283  int64_t Value = 0;
284  if (State.MIs[InsnID]->getOperand(OpIdx).isCImm())
285  Value = State.MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
286  else if (State.MIs[InsnID]->getOperand(OpIdx).isImm())
287  Value = State.MIs[InsnID]->getOperand(OpIdx).getImm();
288  else
289  llvm_unreachable("Expected Imm or CImm operand");
290 
292  if (handleReject() == RejectAndGiveUp)
293  return false;
294  break;
295  }
297  int64_t InsnID = MatchTable[CurrentIdx++];
298  int64_t Predicate = MatchTable[CurrentIdx++];
300  dbgs()
301  << CurrentIdx << ": GIM_CheckAPIntImmPredicate(MIs["
302  << InsnID << "], Predicate=" << Predicate << ")\n");
303  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
304  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
305  "Expected G_CONSTANT");
306  assert(Predicate > GIPFP_APInt_Invalid && "Expected a valid predicate");
307  APInt Value;
308  if (State.MIs[InsnID]->getOperand(1).isCImm())
309  Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
310  else
311  llvm_unreachable("Expected Imm or CImm operand");
312 
314  if (handleReject() == RejectAndGiveUp)
315  return false;
316  break;
317  }
319  int64_t InsnID = MatchTable[CurrentIdx++];
320  int64_t Predicate = MatchTable[CurrentIdx++];
322  dbgs()
323  << CurrentIdx << ": GIM_CheckAPFloatImmPredicate(MIs["
324  << InsnID << "], Predicate=" << Predicate << ")\n");
325  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
326  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
327  "Expected G_FCONSTANT");
328  assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand");
329  assert(Predicate > GIPFP_APFloat_Invalid && "Expected a valid predicate");
330  APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
331 
333  if (handleReject() == RejectAndGiveUp)
334  return false;
335  break;
336  }
339  int64_t InsnID = MatchTable[CurrentIdx++];
340 
342  dbgs() << CurrentIdx
343  << ": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
344  << InsnID << "])\n");
345  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
346 
347  const MachineInstr *MI = State.MIs[InsnID];
348  assert((MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
349  MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
350  "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
351 
352  if (MatcherOpcode == GIM_CheckIsBuildVectorAllOnes) {
353  if (!isBuildVectorAllOnes(*MI, MRI)) {
354  if (handleReject() == RejectAndGiveUp)
355  return false;
356  }
357  } else {
358  if (!isBuildVectorAllZeros(*MI, MRI)) {
359  if (handleReject() == RejectAndGiveUp)
360  return false;
361  }
362  }
363 
364  break;
365  }
367  int64_t InsnID = MatchTable[CurrentIdx++];
368  int64_t Predicate = MatchTable[CurrentIdx++];
370  dbgs()
371  << CurrentIdx << ": GIM_CheckCxxPredicate(MIs["
372  << InsnID << "], Predicate=" << Predicate << ")\n");
373  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
374  assert(Predicate > GIPFP_MI_Invalid && "Expected a valid predicate");
375 
376  if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID],
377  State.RecordedOperands))
378  if (handleReject() == RejectAndGiveUp)
379  return false;
380  break;
381  }
383  int64_t InsnID = MatchTable[CurrentIdx++];
384  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
386  dbgs() << CurrentIdx << ": GIM_CheckAtomicOrdering(MIs["
387  << InsnID << "], " << (uint64_t)Ordering << ")\n");
388  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
389  if (!State.MIs[InsnID]->hasOneMemOperand())
390  if (handleReject() == RejectAndGiveUp)
391  return false;
392 
393  for (const auto &MMO : State.MIs[InsnID]->memoperands())
394  if (MMO->getMergedOrdering() != Ordering)
395  if (handleReject() == RejectAndGiveUp)
396  return false;
397  break;
398  }
400  int64_t InsnID = MatchTable[CurrentIdx++];
401  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
403  dbgs() << CurrentIdx
404  << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
405  << InsnID << "], " << (uint64_t)Ordering << ")\n");
406  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
407  if (!State.MIs[InsnID]->hasOneMemOperand())
408  if (handleReject() == RejectAndGiveUp)
409  return false;
410 
411  for (const auto &MMO : State.MIs[InsnID]->memoperands())
412  if (!isAtLeastOrStrongerThan(MMO->getMergedOrdering(), Ordering))
413  if (handleReject() == RejectAndGiveUp)
414  return false;
415  break;
416  }
418  int64_t InsnID = MatchTable[CurrentIdx++];
419  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
421  dbgs() << CurrentIdx
422  << ": GIM_CheckAtomicOrderingWeakerThan(MIs["
423  << InsnID << "], " << (uint64_t)Ordering << ")\n");
424  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
425  if (!State.MIs[InsnID]->hasOneMemOperand())
426  if (handleReject() == RejectAndGiveUp)
427  return false;
428 
429  for (const auto &MMO : State.MIs[InsnID]->memoperands())
430  if (!isStrongerThan(Ordering, MMO->getMergedOrdering()))
431  if (handleReject() == RejectAndGiveUp)
432  return false;
433  break;
434  }
436  int64_t InsnID = MatchTable[CurrentIdx++];
437  int64_t MMOIdx = MatchTable[CurrentIdx++];
438  // This accepts a list of possible address spaces.
439  const int NumAddrSpace = MatchTable[CurrentIdx++];
440 
441  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
442  if (handleReject() == RejectAndGiveUp)
443  return false;
444  break;
445  }
446 
447  // Need to still jump to the end of the list of address spaces if we find
448  // a match earlier.
449  const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
450 
451  const MachineMemOperand *MMO
452  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
453  const unsigned MMOAddrSpace = MMO->getAddrSpace();
454 
455  bool Success = false;
456  for (int I = 0; I != NumAddrSpace; ++I) {
457  unsigned AddrSpace = MatchTable[CurrentIdx++];
460  dbgs() << "addrspace(" << MMOAddrSpace << ") vs "
461  << AddrSpace << '\n');
462 
463  if (AddrSpace == MMOAddrSpace) {
464  Success = true;
465  break;
466  }
467  }
468 
469  CurrentIdx = LastIdx;
470  if (!Success && handleReject() == RejectAndGiveUp)
471  return false;
472  break;
473  }
475  int64_t InsnID = MatchTable[CurrentIdx++];
476  int64_t MMOIdx = MatchTable[CurrentIdx++];
477  unsigned MinAlign = MatchTable[CurrentIdx++];
478 
479  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
480 
481  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
482  if (handleReject() == RejectAndGiveUp)
483  return false;
484  break;
485  }
486 
487  MachineMemOperand *MMO
488  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
490  dbgs() << CurrentIdx << ": GIM_CheckMemoryAlignment"
491  << "(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
492  << ")->getAlignment() >= " << MinAlign << ")\n");
493  if (MMO->getAlign() < MinAlign && handleReject() == RejectAndGiveUp)
494  return false;
495 
496  break;
497  }
499  int64_t InsnID = MatchTable[CurrentIdx++];
500  int64_t MMOIdx = MatchTable[CurrentIdx++];
501  uint64_t Size = MatchTable[CurrentIdx++];
502 
504  dbgs() << CurrentIdx
505  << ": GIM_CheckMemorySizeEqual(MIs[" << InsnID
506  << "]->memoperands() + " << MMOIdx
507  << ", Size=" << Size << ")\n");
508  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
509 
510  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
511  if (handleReject() == RejectAndGiveUp)
512  return false;
513  break;
514  }
515 
516  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
517 
519  dbgs() << MMO->getSize() << " bytes vs " << Size
520  << " bytes\n");
521  if (MMO->getSize() != Size)
522  if (handleReject() == RejectAndGiveUp)
523  return false;
524 
525  break;
526  }
530  int64_t InsnID = MatchTable[CurrentIdx++];
531  int64_t MMOIdx = MatchTable[CurrentIdx++];
532  int64_t OpIdx = MatchTable[CurrentIdx++];
533 
536  dbgs() << CurrentIdx << ": GIM_CheckMemorySize"
537  << (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT
538  ? "EqualTo"
539  : MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT
540  ? "GreaterThan"
541  : "LessThan")
542  << "LLT(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
543  << ", OpIdx=" << OpIdx << ")\n");
544  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
545 
546  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
547  if (!MO.isReg()) {
549  dbgs() << CurrentIdx << ": Not a register\n");
550  if (handleReject() == RejectAndGiveUp)
551  return false;
552  break;
553  }
554 
555  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
556  if (handleReject() == RejectAndGiveUp)
557  return false;
558  break;
559  }
560 
561  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
562 
563  unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
564  if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
565  MMO->getSizeInBits() != Size) {
566  if (handleReject() == RejectAndGiveUp)
567  return false;
568  } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
569  MMO->getSizeInBits() >= Size) {
570  if (handleReject() == RejectAndGiveUp)
571  return false;
572  } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
573  MMO->getSizeInBits() <= Size)
574  if (handleReject() == RejectAndGiveUp)
575  return false;
576 
577  break;
578  }
579  case GIM_CheckType: {
580  int64_t InsnID = MatchTable[CurrentIdx++];
581  int64_t OpIdx = MatchTable[CurrentIdx++];
582  int64_t TypeID = MatchTable[CurrentIdx++];
584  dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
585  << "]->getOperand(" << OpIdx
586  << "), TypeID=" << TypeID << ")\n");
587  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
588  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
589  if (!MO.isReg() ||
590  MRI.getType(MO.getReg()) != ISelInfo.TypeObjects[TypeID]) {
591  if (handleReject() == RejectAndGiveUp)
592  return false;
593  }
594  break;
595  }
596  case GIM_CheckPointerToAny: {
597  int64_t InsnID = MatchTable[CurrentIdx++];
598  int64_t OpIdx = MatchTable[CurrentIdx++];
599  uint64_t SizeInBits = MatchTable[CurrentIdx++];
600 
602  dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs["
603  << InsnID << "]->getOperand(" << OpIdx
604  << "), SizeInBits=" << SizeInBits << ")\n");
605  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
606  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
607  const LLT Ty = MRI.getType(MO.getReg());
608 
609  // iPTR must be looked up in the target.
610  if (SizeInBits == 0) {
611  MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
612  const unsigned AddrSpace = Ty.getAddressSpace();
613  SizeInBits = MF->getDataLayout().getPointerSizeInBits(AddrSpace);
614  }
615 
616  assert(SizeInBits != 0 && "Pointer size must be known");
617 
618  if (MO.isReg()) {
619  if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits)
620  if (handleReject() == RejectAndGiveUp)
621  return false;
622  } else if (handleReject() == RejectAndGiveUp)
623  return false;
624 
625  break;
626  }
627  case GIM_RecordNamedOperand: {
628  int64_t InsnID = MatchTable[CurrentIdx++];
629  int64_t OpIdx = MatchTable[CurrentIdx++];
630  uint64_t StoreIdx = MatchTable[CurrentIdx++];
631 
633  dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs["
634  << InsnID << "]->getOperand(" << OpIdx
635  << "), StoreIdx=" << StoreIdx << ")\n");
636  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
637  assert(StoreIdx < State.RecordedOperands.size() && "Index out of range");
638  State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx);
639  break;
640  }
642  int64_t InsnID = MatchTable[CurrentIdx++];
643  int64_t OpIdx = MatchTable[CurrentIdx++];
644  int64_t RCEnum = MatchTable[CurrentIdx++];
646  dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
647  << InsnID << "]->getOperand(" << OpIdx
648  << "), RCEnum=" << RCEnum << ")\n");
649  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
650  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
651  if (!MO.isReg() ||
652  &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum),
653  MRI.getType(MO.getReg())) !=
654  RBI.getRegBank(MO.getReg(), MRI, TRI)) {
655  if (handleReject() == RejectAndGiveUp)
656  return false;
657  }
658  break;
659  }
660 
662  int64_t InsnID = MatchTable[CurrentIdx++];
663  int64_t OpIdx = MatchTable[CurrentIdx++];
664  int64_t RendererID = MatchTable[CurrentIdx++];
665  int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
667  dbgs() << CurrentIdx << ": State.Renderers[" << RendererID
668  << "] = GIM_CheckComplexPattern(MIs[" << InsnID
669  << "]->getOperand(" << OpIdx
670  << "), ComplexPredicateID=" << ComplexPredicateID
671  << ")\n");
672  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
673  // FIXME: Use std::invoke() when it's available.
674  ComplexRendererFns Renderer =
675  (ISel.*ISelInfo.ComplexPredicates[ComplexPredicateID])(
676  State.MIs[InsnID]->getOperand(OpIdx));
677  if (Renderer)
678  State.Renderers[RendererID] = Renderer.getValue();
679  else
680  if (handleReject() == RejectAndGiveUp)
681  return false;
682  break;
683  }
684 
685  case GIM_CheckConstantInt: {
686  int64_t InsnID = MatchTable[CurrentIdx++];
687  int64_t OpIdx = MatchTable[CurrentIdx++];
688  int64_t Value = MatchTable[CurrentIdx++];
690  dbgs() << CurrentIdx << ": GIM_CheckConstantInt(MIs["
691  << InsnID << "]->getOperand(" << OpIdx
692  << "), Value=" << Value << ")\n");
693  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
694  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
695  if (MO.isReg()) {
696  // isOperandImmEqual() will sign-extend to 64-bits, so should we.
697  LLT Ty = MRI.getType(MO.getReg());
699 
700  if (!isOperandImmEqual(MO, Value, MRI)) {
701  if (handleReject() == RejectAndGiveUp)
702  return false;
703  }
704  } else if (handleReject() == RejectAndGiveUp)
705  return false;
706 
707  break;
708  }
709 
710  case GIM_CheckLiteralInt: {
711  int64_t InsnID = MatchTable[CurrentIdx++];
712  int64_t OpIdx = MatchTable[CurrentIdx++];
713  int64_t Value = MatchTable[CurrentIdx++];
715  dbgs() << CurrentIdx << ": GIM_CheckLiteralInt(MIs["
716  << InsnID << "]->getOperand(" << OpIdx
717  << "), Value=" << Value << ")\n");
718  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
719  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
720  if (MO.isImm() && MO.getImm() == Value)
721  break;
722 
723  if (MO.isCImm() && MO.getCImm()->equalsInt(Value))
724  break;
725 
726  if (handleReject() == RejectAndGiveUp)
727  return false;
728 
729  break;
730  }
731 
732  case GIM_CheckIntrinsicID: {
733  int64_t InsnID = MatchTable[CurrentIdx++];
734  int64_t OpIdx = MatchTable[CurrentIdx++];
735  int64_t Value = MatchTable[CurrentIdx++];
737  dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs["
738  << InsnID << "]->getOperand(" << OpIdx
739  << "), Value=" << Value << ")\n");
740  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
741  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
742  if (!MO.isIntrinsicID() || MO.getIntrinsicID() != Value)
743  if (handleReject() == RejectAndGiveUp)
744  return false;
745  break;
746  }
747  case GIM_CheckCmpPredicate: {
748  int64_t InsnID = MatchTable[CurrentIdx++];
749  int64_t OpIdx = MatchTable[CurrentIdx++];
750  int64_t Value = MatchTable[CurrentIdx++];
752  dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs["
753  << InsnID << "]->getOperand(" << OpIdx
754  << "), Value=" << Value << ")\n");
755  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
756  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
757  if (!MO.isPredicate() || MO.getPredicate() != Value)
758  if (handleReject() == RejectAndGiveUp)
759  return false;
760  break;
761  }
762  case GIM_CheckIsMBB: {
763  int64_t InsnID = MatchTable[CurrentIdx++];
764  int64_t OpIdx = MatchTable[CurrentIdx++];
766  dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID
767  << "]->getOperand(" << OpIdx << "))\n");
768  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
769  if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
770  if (handleReject() == RejectAndGiveUp)
771  return false;
772  }
773  break;
774  }
775  case GIM_CheckIsImm: {
776  int64_t InsnID = MatchTable[CurrentIdx++];
777  int64_t OpIdx = MatchTable[CurrentIdx++];
779  dbgs() << CurrentIdx << ": GIM_CheckIsImm(MIs[" << InsnID
780  << "]->getOperand(" << OpIdx << "))\n");
781  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
782  if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) {
783  if (handleReject() == RejectAndGiveUp)
784  return false;
785  }
786  break;
787  }
788  case GIM_CheckIsSafeToFold: {
789  int64_t InsnID = MatchTable[CurrentIdx++];
791  dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs["
792  << InsnID << "])\n");
793  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
794  if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) {
795  if (handleReject() == RejectAndGiveUp)
796  return false;
797  }
798  break;
799  }
800  case GIM_CheckIsSameOperand: {
801  int64_t InsnID = MatchTable[CurrentIdx++];
802  int64_t OpIdx = MatchTable[CurrentIdx++];
803  int64_t OtherInsnID = MatchTable[CurrentIdx++];
804  int64_t OtherOpIdx = MatchTable[CurrentIdx++];
806  dbgs() << CurrentIdx << ": GIM_CheckIsSameOperand(MIs["
807  << InsnID << "][" << OpIdx << "], MIs["
808  << OtherInsnID << "][" << OtherOpIdx << "])\n");
809  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
810  assert(State.MIs[OtherInsnID] != nullptr && "Used insn before defined");
811  if (!State.MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
812  State.MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
813  if (handleReject() == RejectAndGiveUp)
814  return false;
815  }
816  break;
817  }
818  case GIM_Reject:
820  dbgs() << CurrentIdx << ": GIM_Reject\n");
821  if (handleReject() == RejectAndGiveUp)
822  return false;
823  break;
824 
825  case GIR_MutateOpcode: {
826  int64_t OldInsnID = MatchTable[CurrentIdx++];
827  uint64_t NewInsnID = MatchTable[CurrentIdx++];
828  int64_t NewOpcode = MatchTable[CurrentIdx++];
829  if (NewInsnID >= OutMIs.size())
830  OutMIs.resize(NewInsnID + 1);
831 
832  OutMIs[NewInsnID] = MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(),
833  State.MIs[OldInsnID]);
834  OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
836  dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs["
837  << NewInsnID << "], MIs[" << OldInsnID << "], "
838  << NewOpcode << ")\n");
839  break;
840  }
841 
842  case GIR_BuildMI: {
843  uint64_t NewInsnID = MatchTable[CurrentIdx++];
844  int64_t Opcode = MatchTable[CurrentIdx++];
845  if (NewInsnID >= OutMIs.size())
846  OutMIs.resize(NewInsnID + 1);
847 
848  OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
849  State.MIs[0]->getDebugLoc(), TII.get(Opcode));
851  dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
852  << NewInsnID << "], " << Opcode << ")\n");
853  break;
854  }
855 
856  case GIR_Copy: {
857  int64_t NewInsnID = MatchTable[CurrentIdx++];
858  int64_t OldInsnID = MatchTable[CurrentIdx++];
859  int64_t OpIdx = MatchTable[CurrentIdx++];
860  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
861  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
863  dbgs()
864  << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
865  << "], MIs[" << OldInsnID << "], " << OpIdx << ")\n");
866  break;
867  }
868 
869  case GIR_CopyOrAddZeroReg: {
870  int64_t NewInsnID = MatchTable[CurrentIdx++];
871  int64_t OldInsnID = MatchTable[CurrentIdx++];
872  int64_t OpIdx = MatchTable[CurrentIdx++];
873  int64_t ZeroReg = MatchTable[CurrentIdx++];
874  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
875  MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
876  if (isOperandImmEqual(MO, 0, MRI))
877  OutMIs[NewInsnID].addReg(ZeroReg);
878  else
879  OutMIs[NewInsnID].add(MO);
881  dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs["
882  << NewInsnID << "], MIs[" << OldInsnID << "], "
883  << OpIdx << ", " << ZeroReg << ")\n");
884  break;
885  }
886 
887  case GIR_CopySubReg: {
888  int64_t NewInsnID = MatchTable[CurrentIdx++];
889  int64_t OldInsnID = MatchTable[CurrentIdx++];
890  int64_t OpIdx = MatchTable[CurrentIdx++];
891  int64_t SubRegIdx = MatchTable[CurrentIdx++];
892  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
893  OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
894  0, SubRegIdx);
896  dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
897  << NewInsnID << "], MIs[" << OldInsnID << "], "
898  << OpIdx << ", " << SubRegIdx << ")\n");
899  break;
900  }
901 
902  case GIR_AddImplicitDef: {
903  int64_t InsnID = MatchTable[CurrentIdx++];
904  int64_t RegNum = MatchTable[CurrentIdx++];
905  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
906  OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
908  dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
909  << InsnID << "], " << RegNum << ")\n");
910  break;
911  }
912 
913  case GIR_AddImplicitUse: {
914  int64_t InsnID = MatchTable[CurrentIdx++];
915  int64_t RegNum = MatchTable[CurrentIdx++];
916  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
917  OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
919  dbgs() << CurrentIdx << ": GIR_AddImplicitUse(OutMIs["
920  << InsnID << "], " << RegNum << ")\n");
921  break;
922  }
923 
924  case GIR_AddRegister: {
925  int64_t InsnID = MatchTable[CurrentIdx++];
926  int64_t RegNum = MatchTable[CurrentIdx++];
927  uint64_t RegFlags = MatchTable[CurrentIdx++];
928  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
929  OutMIs[InsnID].addReg(RegNum, RegFlags);
932  dbgs() << CurrentIdx << ": GIR_AddRegister(OutMIs["
933  << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
934  break;
935  }
936 
937  case GIR_AddTempRegister:
938  case GIR_AddTempSubRegister: {
939  int64_t InsnID = MatchTable[CurrentIdx++];
940  int64_t TempRegID = MatchTable[CurrentIdx++];
941  uint64_t TempRegFlags = MatchTable[CurrentIdx++];
942  unsigned SubReg = 0;
943  if (MatcherOpcode == GIR_AddTempSubRegister)
944  SubReg = MatchTable[CurrentIdx++];
945 
946  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
947 
948  OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg);
950  dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs["
951  << InsnID << "], TempRegisters[" << TempRegID
952  << "]";
953  if (SubReg)
954  dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
955  dbgs() << ", " << TempRegFlags << ")\n");
956  break;
957  }
958 
959  case GIR_AddImm: {
960  int64_t InsnID = MatchTable[CurrentIdx++];
961  int64_t Imm = MatchTable[CurrentIdx++];
962  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
963  OutMIs[InsnID].addImm(Imm);
965  dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
966  << "], " << Imm << ")\n");
967  break;
968  }
969 
970  case GIR_ComplexRenderer: {
971  int64_t InsnID = MatchTable[CurrentIdx++];
972  int64_t RendererID = MatchTable[CurrentIdx++];
973  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
974  for (const auto &RenderOpFn : State.Renderers[RendererID])
975  RenderOpFn(OutMIs[InsnID]);
977  dbgs() << CurrentIdx << ": GIR_ComplexRenderer(OutMIs["
978  << InsnID << "], " << RendererID << ")\n");
979  break;
980  }
982  int64_t InsnID = MatchTable[CurrentIdx++];
983  int64_t RendererID = MatchTable[CurrentIdx++];
984  int64_t RenderOpID = MatchTable[CurrentIdx++];
985  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
986  State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
988  dbgs() << CurrentIdx
989  << ": GIR_ComplexSubOperandRenderer(OutMIs["
990  << InsnID << "], " << RendererID << ", "
991  << RenderOpID << ")\n");
992  break;
993  }
994 
995  case GIR_CopyConstantAsSImm: {
996  int64_t NewInsnID = MatchTable[CurrentIdx++];
997  int64_t OldInsnID = MatchTable[CurrentIdx++];
998  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
999  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
1000  if (State.MIs[OldInsnID]->getOperand(1).isCImm()) {
1001  OutMIs[NewInsnID].addImm(
1002  State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
1003  } else if (State.MIs[OldInsnID]->getOperand(1).isImm())
1004  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
1005  else
1006  llvm_unreachable("Expected Imm or CImm operand");
1008  dbgs() << CurrentIdx << ": GIR_CopyConstantAsSImm(OutMIs["
1009  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1010  break;
1011  }
1012 
1013  // TODO: Needs a test case once we have a pattern that uses this.
1014  case GIR_CopyFConstantAsFPImm: {
1015  int64_t NewInsnID = MatchTable[CurrentIdx++];
1016  int64_t OldInsnID = MatchTable[CurrentIdx++];
1017  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1018  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT");
1019  if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
1020  OutMIs[NewInsnID].addFPImm(
1021  State.MIs[OldInsnID]->getOperand(1).getFPImm());
1022  else
1023  llvm_unreachable("Expected FPImm operand");
1025  dbgs() << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
1026  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1027  break;
1028  }
1029 
1030  case GIR_CustomRenderer: {
1031  int64_t InsnID = MatchTable[CurrentIdx++];
1032  int64_t OldInsnID = MatchTable[CurrentIdx++];
1033  int64_t RendererFnID = MatchTable[CurrentIdx++];
1034  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1036  dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs["
1037  << InsnID << "], MIs[" << OldInsnID << "], "
1038  << RendererFnID << ")\n");
1039  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(
1040  OutMIs[InsnID], *State.MIs[OldInsnID],
1041  -1); // Not a source operand of the old instruction.
1042  break;
1043  }
1045  int64_t InsnID = MatchTable[CurrentIdx++];
1046  int64_t OldInsnID = MatchTable[CurrentIdx++];
1047  int64_t OpIdx = MatchTable[CurrentIdx++];
1048  int64_t RendererFnID = MatchTable[CurrentIdx++];
1049  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1050 
1053  dbgs() << CurrentIdx << ": GIR_CustomOperandRenderer(OutMIs["
1054  << InsnID << "], MIs[" << OldInsnID << "]->getOperand("
1055  << OpIdx << "), "
1056  << RendererFnID << ")\n");
1057  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(OutMIs[InsnID],
1058  *State.MIs[OldInsnID],
1059  OpIdx);
1060  break;
1061  }
1062  case GIR_ConstrainOperandRC: {
1063  int64_t InsnID = MatchTable[CurrentIdx++];
1064  int64_t OpIdx = MatchTable[CurrentIdx++];
1065  int64_t RCEnum = MatchTable[CurrentIdx++];
1066  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1067  MachineInstr &I = *OutMIs[InsnID].getInstr();
1068  MachineFunction &MF = *I.getParent()->getParent();
1070  const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum);
1071  MachineOperand &MO = I.getOperand(OpIdx);
1072  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO);
1074  dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
1075  << InsnID << "], " << OpIdx << ", " << RCEnum
1076  << ")\n");
1077  break;
1078  }
1079 
1081  int64_t InsnID = MatchTable[CurrentIdx++];
1082  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1083  constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
1084  RBI);
1086  dbgs() << CurrentIdx
1087  << ": GIR_ConstrainSelectedInstOperands(OutMIs["
1088  << InsnID << "])\n");
1089  break;
1090  }
1091 
1092  case GIR_MergeMemOperands: {
1093  int64_t InsnID = MatchTable[CurrentIdx++];
1094  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1095 
1097  dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs["
1098  << InsnID << "]");
1099  int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList;
1100  while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
1103  dbgs() << ", MIs[" << MergeInsnID << "]");
1104  for (const auto &MMO : State.MIs[MergeInsnID]->memoperands())
1105  OutMIs[InsnID].addMemOperand(MMO);
1106  }
1108  break;
1109  }
1110 
1111  case GIR_EraseFromParent: {
1112  int64_t InsnID = MatchTable[CurrentIdx++];
1113  assert(State.MIs[InsnID] &&
1114  "Attempted to erase an undefined instruction");
1115  State.MIs[InsnID]->eraseFromParent();
1117  dbgs() << CurrentIdx << ": GIR_EraseFromParent(MIs["
1118  << InsnID << "])\n");
1119  break;
1120  }
1121 
1122  case GIR_MakeTempReg: {
1123  int64_t TempRegID = MatchTable[CurrentIdx++];
1124  int64_t TypeID = MatchTable[CurrentIdx++];
1125 
1126  State.TempRegisters[TempRegID] =
1127  MRI.createGenericVirtualRegister(ISelInfo.TypeObjects[TypeID]);
1129  dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
1130  << "] = GIR_MakeTempReg(" << TypeID << ")\n");
1131  break;
1132  }
1133 
1134  case GIR_Coverage: {
1135  int64_t RuleID = MatchTable[CurrentIdx++];
1136  CoverageInfo.setCovered(RuleID);
1137 
1139  dbgs()
1140  << CurrentIdx << ": GIR_Coverage(" << RuleID << ")");
1141  break;
1142  }
1143 
1144  case GIR_Done:
1146  dbgs() << CurrentIdx << ": GIR_Done\n");
1147  propagateFlags(OutMIs);
1148  return true;
1149 
1150  default:
1151  llvm_unreachable("Unexpected command");
1152  }
1153  }
1154 }
1155 
1156 } // end namespace llvm
1157 
1158 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:472
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
llvm::GIM_CheckMemorySizeLessThanLLT
@ GIM_CheckMemorySizeLessThanLLT
Definition: InstructionSelector.h:183
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::GIR_CopyOrAddZeroReg
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:305
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1087
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
Definition: InstructionSelector.h:546
llvm::GIM_RecordNamedOperand
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
Definition: InstructionSelector.h:274
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::GIM_CheckAPFloatImmPredicate
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:143
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::GIR_Copy
@ GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:297
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::GIR_MakeTempReg
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
Definition: InstructionSelector.h:404
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:431
ErrorHandling.h
RegisterBankInfo.h
llvm::GIR_ComplexRenderer
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:346
llvm::InstructionSelector::MatcherState
Definition: InstructionSelector.h:471
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:240
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::GIM_CheckIsSafeToFold
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:258
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:324
llvm::InstructionSelector::MatcherState::MIs
RecordedMIVector MIs
Definition: InstructionSelector.h:473
llvm::Optional
Definition: APInt.h:33
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:534
llvm::GIM_CheckLiteralInt
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:232
llvm::GIM_SwitchType
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:104
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:41
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:654
llvm::CodeGenCoverage::setCovered
void setCovered(uint64_t RuleID)
Definition: CodeGenCoverage.cpp:28
llvm::GIM_CheckMemoryAlignment
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:175
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:474
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:150
llvm::GIM_CheckComplexPattern
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:220
MachineRegisterInfo.h
llvm::GIM_CheckFeatures
@ GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:114
llvm::GIR_AddImm
@ GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:342
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::isAtLeastOrStrongerThan
bool isAtLeastOrStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Definition: AtomicOrdering.h:105
llvm::GIM_CheckPointerToAny
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:208
llvm::MinAlign
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:699
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
DEBUG_WITH_TYPE
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
llvm::InstructionSelector::ISelInfoTy::CustomRenderers
const CustomRendererFn * CustomRenderers
Definition: InstructionSelector.h:509
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::GIM_Reject
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:278
Constants.h
llvm::GIM_CheckMemorySizeEqualToLLT
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:182
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::GIM_CheckOpcodeIsEither
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
Definition: InstructionSelector.h:126
llvm::GIR_CopyFConstantAsFPImm
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:377
llvm::GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckMemorySizeGreaterThanLLT
Definition: InstructionSelector.h:184
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:440
Utils.h
llvm::GIM_CheckIntrinsicID
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:237
llvm::GIM_CheckIsMBB
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:248
llvm::ConstantInt::equalsInt
bool equalsInt(uint64_t V) const
A helper method that can be used to determine if the constant contained within is equal to a constant...
Definition: Constants.h:168
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::GIM_CheckType
@ GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:203
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::GIR_CustomOperandRenderer
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
Definition: InstructionSelector.h:365
llvm::InstructionSelector::MatcherState::RecordedOperands
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
Definition: InstructionSelector.h:479
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:619
llvm::GIM_CheckAtomicOrderingOrStrongerThan
@ GIM_CheckAtomicOrderingOrStrongerThan
Definition: InstructionSelector.h:153
llvm::GIPFP_APFloat_Invalid
@ GIPFP_APFloat_Invalid
Definition: InstructionSelectorImpl.h:44
llvm::GIU_MergeMemOperands_EndOfList
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
Definition: InstructionSelector.h:420
llvm::GIR_AddTempSubRegister
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:337
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:110
llvm::GIM_CheckConstantInt
@ GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:226
llvm::GIM_CheckCxxInsnPredicate
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:197
llvm::GIM_CheckMemoryAddressSpace
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:168
llvm::GIM_CheckIsImm
@ GIM_CheckIsImm
Check the specified operand is an Imm.
Definition: InstructionSelector.h:253
InstructionSelector.h
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:238
llvm::GIM_CheckImmOperandPredicate
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:148
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:442
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
TypeID
Type::TypeID TypeID
Definition: Mips16HardFloat.cpp:102
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:29
llvm::APFloat
Definition: APFloat.h:701
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:511
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GIM_CheckNumOperands
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:131
llvm::GIR_MergeMemOperands
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:395
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:19
llvm::GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckIsBuildVectorAllZeros
Definition: InstructionSelector.h:192
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::GIM_CheckCmpPredicate
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
Definition: InstructionSelector.h:243
llvm::GIR_EraseFromParent
@ GIR_EraseFromParent
Erase from parent.
Definition: InstructionSelector.h:399
llvm::GIM_CheckAtomicOrdering
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:152
I
#define I(x, y, z)
Definition: MD5.cpp:58
CodeGenCoverage.h
llvm::GIR_ComplexSubOperandRenderer
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:352
llvm::InstructionSelector::ISelInfoTy::TypeObjects
const LLT * TypeObjects
Definition: InstructionSelector.h:506
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::Optional::getValue
constexpr const T & getValue() const &
Definition: Optional.h:306
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::GIR_CustomRenderer
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:357
llvm::GIR_ConstrainOperandRC
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:383
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:542
llvm::GIM_CheckIsSameOperand
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:265
llvm::GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckAtomicOrderingWeakerThan
Definition: InstructionSelector.h:154
DataLayout.h
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:351
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::GIR_CopySubReg
@ GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:311
llvm::GIM_RecordInsn
@ GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:110
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:811
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:508
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::GIM_SwitchOpcode
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:95
llvm::InstructionSelector::ISelInfoTy::FeatureBitsets
const PredicateBitset * FeatureBitsets
Definition: InstructionSelector.h:507
llvm::RegisterBankInfo::getRegBankFromRegClass
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
Definition: RegisterBankInfo.h:603
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1119
llvm::GIR_ConstrainSelectedInstOperands
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:388
uint16_t
llvm::GIR_AddImplicitDef
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:316
llvm::GIR_BuildMI
@ GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:291
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::GIR_AddTempRegister
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:330
llvm::GIPFP_MI_Invalid
@ GIPFP_MI_Invalid
Definition: InstructionSelectorImpl.h:45
Success
#define Success
Definition: AArch64Disassembler.cpp:280
llvm::GIR_AddRegister
@ GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:324
llvm::GIPFP_I64_Invalid
@ GIPFP_I64_Invalid
Definition: InstructionSelectorImpl.h:42
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::GIR_AddImplicitUse
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:320
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:55
llvm::isStrongerThan
bool isStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Returns true if ao is stronger than other as defined by the AtomicOrdering lattice,...
Definition: AtomicOrdering.h:90
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::GIM_CheckOpcode
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:119
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:352
SmallVector.h
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:538
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:51
llvm::GIM_CheckRegBankForClass
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:213
llvm::InstructionSelector::ISelInfoTy
Definition: InstructionSelector.h:493
llvm::GIR_Done
@ GIR_Done
A successful emission.
Definition: InstructionSelector.h:407
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::GIM_CheckIsBuildVectorAllOnes
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Definition: InstructionSelector.h:191
MachineOperand.h
llvm::GIR_MutateOpcode
@ GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:286
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
llvm::GIM_CheckAPIntImmPredicate
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:139
llvm::GIM_CheckI64ImmPredicate
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:135
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
Definition: InstructionSelectorImpl.h:50
llvm::GIPFP_APInt_Invalid
@ GIPFP_APInt_Invalid
Definition: InstructionSelectorImpl.h:43
raw_ostream.h
llvm::GIM_Try
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:87
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
Debug.h
llvm::GIR_Coverage
@ GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:411
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1113
llvm::GIR_CopyConstantAsSImm
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:371
llvm::GIM_CheckMemorySizeEqualTo
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:159
llvm::LLT
Definition: LowLevelTypeImpl.h:39