LLVM  14.0.0git
InstructionSelectorImpl.h
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API for the instruction selector.
10 /// This class is responsible for selecting machine instructions.
11 /// It's implemented by the target. It's used by the InstructionSelect pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
16 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
17 
18 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/Support/Debug.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 
37 namespace llvm {
38 
39 /// GlobalISel PatFrag Predicates
40 enum {
45 };
46 
47 template <class TgtInstructionSelector, class PredicateBitset,
48  class ComplexMatcherMemFn, class CustomRendererFn>
50  TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
52  &ISelInfo,
53  const int64_t *MatchTable, const TargetInstrInfo &TII,
55  const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
56  CodeGenCoverage &CoverageInfo) const {
57 
58  uint64_t CurrentIdx = 0;
59  SmallVector<uint64_t, 4> OnFailResumeAt;
60 
61  // Bypass the flag check on the instruction, and only look at the MCInstrDesc.
62  bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
63 
64  const uint16_t Flags = State.MIs[0]->getFlags();
65 
66  enum RejectAction { RejectAndGiveUp, RejectAndResume };
67  auto handleReject = [&]() -> RejectAction {
69  dbgs() << CurrentIdx << ": Rejected\n");
70  if (OnFailResumeAt.empty())
71  return RejectAndGiveUp;
72  CurrentIdx = OnFailResumeAt.pop_back_val();
74  dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " ("
75  << OnFailResumeAt.size() << " try-blocks remain)\n");
76  return RejectAndResume;
77  };
78 
79  auto propagateFlags = [=](NewMIVector &OutMIs) {
80  for (auto MIB : OutMIs) {
81  // Set the NoFPExcept flag when no original matched instruction could
82  // raise an FP exception, but the new instruction potentially might.
83  uint16_t MIBFlags = Flags;
84  if (NoFPException && MIB->mayRaiseFPException())
85  MIBFlags |= MachineInstr::NoFPExcept;
86  MIB.setMIFlags(MIBFlags);
87  }
88 
89  return true;
90  };
91 
92  while (true) {
93  assert(CurrentIdx != ~0u && "Invalid MatchTable index");
94  int64_t MatcherOpcode = MatchTable[CurrentIdx++];
95  switch (MatcherOpcode) {
96  case GIM_Try: {
98  dbgs() << CurrentIdx << ": Begin try-block\n");
99  OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
100  break;
101  }
102 
103  case GIM_RecordInsn: {
104  int64_t NewInsnID = MatchTable[CurrentIdx++];
105  int64_t InsnID = MatchTable[CurrentIdx++];
106  int64_t OpIdx = MatchTable[CurrentIdx++];
107 
108  // As an optimisation we require that MIs[0] is always the root. Refuse
109  // any attempt to modify it.
110  assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
111 
112  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
113  if (!MO.isReg()) {
115  dbgs() << CurrentIdx << ": Not a register\n");
116  if (handleReject() == RejectAndGiveUp)
117  return false;
118  break;
119  }
122  dbgs() << CurrentIdx << ": Is a physical register\n");
123  if (handleReject() == RejectAndGiveUp)
124  return false;
125  break;
126  }
127 
128  MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());
129  if ((size_t)NewInsnID < State.MIs.size())
130  State.MIs[NewInsnID] = NewMI;
131  else {
132  assert((size_t)NewInsnID == State.MIs.size() &&
133  "Expected to store MIs in order");
134  State.MIs.push_back(NewMI);
135  }
137  dbgs() << CurrentIdx << ": MIs[" << NewInsnID
138  << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
139  << ")\n");
140  break;
141  }
142 
143  case GIM_CheckFeatures: {
144  int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
146  dbgs() << CurrentIdx
147  << ": GIM_CheckFeatures(ExpectedBitsetID="
148  << ExpectedBitsetID << ")\n");
149  if ((AvailableFeatures & ISelInfo.FeatureBitsets[ExpectedBitsetID]) !=
150  ISelInfo.FeatureBitsets[ExpectedBitsetID]) {
151  if (handleReject() == RejectAndGiveUp)
152  return false;
153  }
154  break;
155  }
156 
157  case GIM_CheckOpcode:
159  int64_t InsnID = MatchTable[CurrentIdx++];
160  int64_t Expected0 = MatchTable[CurrentIdx++];
161  int64_t Expected1 = -1;
162  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
163  Expected1 = MatchTable[CurrentIdx++];
164 
165  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
166  unsigned Opcode = State.MIs[InsnID]->getOpcode();
167 
169  dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
170  << "], ExpectedOpcode=" << Expected0;
171  if (MatcherOpcode == GIM_CheckOpcodeIsEither)
172  dbgs() << " || " << Expected1;
173  dbgs() << ") // Got=" << Opcode << "\n";
174  );
175 
176  if (Opcode != Expected0 && Opcode != Expected1) {
177  if (handleReject() == RejectAndGiveUp)
178  return false;
179  }
180  break;
181  }
182  case GIM_SwitchOpcode: {
183  int64_t InsnID = MatchTable[CurrentIdx++];
184  int64_t LowerBound = MatchTable[CurrentIdx++];
185  int64_t UpperBound = MatchTable[CurrentIdx++];
186  int64_t Default = MatchTable[CurrentIdx++];
187 
188  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
189  const int64_t Opcode = State.MIs[InsnID]->getOpcode();
190 
192  dbgs() << CurrentIdx << ": GIM_SwitchOpcode(MIs[" << InsnID << "], ["
193  << LowerBound << ", " << UpperBound << "), Default=" << Default
194  << ", JumpTable...) // Got=" << Opcode << "\n";
195  });
196  if (Opcode < LowerBound || UpperBound <= Opcode) {
197  CurrentIdx = Default;
198  break;
199  }
200  CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)];
201  if (!CurrentIdx) {
202  CurrentIdx = Default;
203  break;
204  }
205  OnFailResumeAt.push_back(Default);
206  break;
207  }
208 
209  case GIM_SwitchType: {
210  int64_t InsnID = MatchTable[CurrentIdx++];
211  int64_t OpIdx = MatchTable[CurrentIdx++];
212  int64_t LowerBound = MatchTable[CurrentIdx++];
213  int64_t UpperBound = MatchTable[CurrentIdx++];
214  int64_t Default = MatchTable[CurrentIdx++];
215 
216  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
217  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
218 
220  dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
221  << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
222  << UpperBound << "), Default=" << Default
223  << ", JumpTable...) // Got=";
224  if (!MO.isReg())
225  dbgs() << "Not a VReg\n";
226  else
227  dbgs() << MRI.getType(MO.getReg()) << "\n";
228  });
229  if (!MO.isReg()) {
230  CurrentIdx = Default;
231  break;
232  }
233  const LLT Ty = MRI.getType(MO.getReg());
234  const auto TyI = ISelInfo.TypeIDMap.find(Ty);
235  if (TyI == ISelInfo.TypeIDMap.end()) {
236  CurrentIdx = Default;
237  break;
238  }
239  const int64_t TypeID = TyI->second;
240  if (TypeID < LowerBound || UpperBound <= TypeID) {
241  CurrentIdx = Default;
242  break;
243  }
244  CurrentIdx = MatchTable[CurrentIdx + (TypeID - LowerBound)];
245  if (!CurrentIdx) {
246  CurrentIdx = Default;
247  break;
248  }
249  OnFailResumeAt.push_back(Default);
250  break;
251  }
252 
253  case GIM_CheckNumOperands: {
254  int64_t InsnID = MatchTable[CurrentIdx++];
255  int64_t Expected = MatchTable[CurrentIdx++];
257  dbgs() << CurrentIdx << ": GIM_CheckNumOperands(MIs["
258  << InsnID << "], Expected=" << Expected << ")\n");
259  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
260  if (State.MIs[InsnID]->getNumOperands() != Expected) {
261  if (handleReject() == RejectAndGiveUp)
262  return false;
263  }
264  break;
265  }
268  int64_t InsnID = MatchTable[CurrentIdx++];
269  int64_t OpIdx = MatcherOpcode == GIM_CheckImmOperandPredicate
270  ? MatchTable[CurrentIdx++]
271  : 1;
272  int64_t Predicate = MatchTable[CurrentIdx++];
274  dbgs() << CurrentIdx << ": GIM_CheckImmPredicate(MIs["
275  << InsnID << "]->getOperand(" << OpIdx
276  << "), Predicate=" << Predicate << ")\n");
277  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
278  assert((State.MIs[InsnID]->getOperand(OpIdx).isImm() ||
279  State.MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
280  "Expected immediate operand");
281  assert(Predicate > GIPFP_I64_Invalid && "Expected a valid predicate");
282  int64_t Value = 0;
283  if (State.MIs[InsnID]->getOperand(OpIdx).isCImm())
284  Value = State.MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
285  else if (State.MIs[InsnID]->getOperand(OpIdx).isImm())
286  Value = State.MIs[InsnID]->getOperand(OpIdx).getImm();
287  else
288  llvm_unreachable("Expected Imm or CImm operand");
289 
291  if (handleReject() == RejectAndGiveUp)
292  return false;
293  break;
294  }
296  int64_t InsnID = MatchTable[CurrentIdx++];
297  int64_t Predicate = MatchTable[CurrentIdx++];
299  dbgs()
300  << CurrentIdx << ": GIM_CheckAPIntImmPredicate(MIs["
301  << InsnID << "], Predicate=" << Predicate << ")\n");
302  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
303  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
304  "Expected G_CONSTANT");
305  assert(Predicate > GIPFP_APInt_Invalid && "Expected a valid predicate");
306  APInt Value;
307  if (State.MIs[InsnID]->getOperand(1).isCImm())
308  Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
309  else
310  llvm_unreachable("Expected Imm or CImm operand");
311 
313  if (handleReject() == RejectAndGiveUp)
314  return false;
315  break;
316  }
318  int64_t InsnID = MatchTable[CurrentIdx++];
319  int64_t Predicate = MatchTable[CurrentIdx++];
321  dbgs()
322  << CurrentIdx << ": GIM_CheckAPFloatImmPredicate(MIs["
323  << InsnID << "], Predicate=" << Predicate << ")\n");
324  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
325  assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
326  "Expected G_FCONSTANT");
327  assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand");
328  assert(Predicate > GIPFP_APFloat_Invalid && "Expected a valid predicate");
329  APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
330 
332  if (handleReject() == RejectAndGiveUp)
333  return false;
334  break;
335  }
338  int64_t InsnID = MatchTable[CurrentIdx++];
339 
341  dbgs() << CurrentIdx
342  << ": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
343  << InsnID << "])\n");
344  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
345 
346  const MachineInstr *MI = State.MIs[InsnID];
347  assert((MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
348  MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
349  "Expected G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC");
350 
351  if (MatcherOpcode == GIM_CheckIsBuildVectorAllOnes) {
352  if (!isBuildVectorAllOnes(*MI, MRI)) {
353  if (handleReject() == RejectAndGiveUp)
354  return false;
355  }
356  } else {
357  if (!isBuildVectorAllZeros(*MI, MRI)) {
358  if (handleReject() == RejectAndGiveUp)
359  return false;
360  }
361  }
362 
363  break;
364  }
366  int64_t InsnID = MatchTable[CurrentIdx++];
367  int64_t Predicate = MatchTable[CurrentIdx++];
369  dbgs()
370  << CurrentIdx << ": GIM_CheckCxxPredicate(MIs["
371  << InsnID << "], Predicate=" << Predicate << ")\n");
372  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
373  assert(Predicate > GIPFP_MI_Invalid && "Expected a valid predicate");
374 
375  if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID],
376  State.RecordedOperands))
377  if (handleReject() == RejectAndGiveUp)
378  return false;
379  break;
380  }
382  int64_t InsnID = MatchTable[CurrentIdx++];
383  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
385  dbgs() << CurrentIdx << ": GIM_CheckAtomicOrdering(MIs["
386  << InsnID << "], " << (uint64_t)Ordering << ")\n");
387  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
388  if (!State.MIs[InsnID]->hasOneMemOperand())
389  if (handleReject() == RejectAndGiveUp)
390  return false;
391 
392  for (const auto &MMO : State.MIs[InsnID]->memoperands())
393  if (MMO->getMergedOrdering() != Ordering)
394  if (handleReject() == RejectAndGiveUp)
395  return false;
396  break;
397  }
399  int64_t InsnID = MatchTable[CurrentIdx++];
400  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
402  dbgs() << CurrentIdx
403  << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
404  << InsnID << "], " << (uint64_t)Ordering << ")\n");
405  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
406  if (!State.MIs[InsnID]->hasOneMemOperand())
407  if (handleReject() == RejectAndGiveUp)
408  return false;
409 
410  for (const auto &MMO : State.MIs[InsnID]->memoperands())
411  if (!isAtLeastOrStrongerThan(MMO->getMergedOrdering(), Ordering))
412  if (handleReject() == RejectAndGiveUp)
413  return false;
414  break;
415  }
417  int64_t InsnID = MatchTable[CurrentIdx++];
418  AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
420  dbgs() << CurrentIdx
421  << ": GIM_CheckAtomicOrderingWeakerThan(MIs["
422  << InsnID << "], " << (uint64_t)Ordering << ")\n");
423  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
424  if (!State.MIs[InsnID]->hasOneMemOperand())
425  if (handleReject() == RejectAndGiveUp)
426  return false;
427 
428  for (const auto &MMO : State.MIs[InsnID]->memoperands())
429  if (!isStrongerThan(Ordering, MMO->getMergedOrdering()))
430  if (handleReject() == RejectAndGiveUp)
431  return false;
432  break;
433  }
435  int64_t InsnID = MatchTable[CurrentIdx++];
436  int64_t MMOIdx = MatchTable[CurrentIdx++];
437  // This accepts a list of possible address spaces.
438  const int NumAddrSpace = MatchTable[CurrentIdx++];
439 
440  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
441  if (handleReject() == RejectAndGiveUp)
442  return false;
443  break;
444  }
445 
446  // Need to still jump to the end of the list of address spaces if we find
447  // a match earlier.
448  const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
449 
450  const MachineMemOperand *MMO
451  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
452  const unsigned MMOAddrSpace = MMO->getAddrSpace();
453 
454  bool Success = false;
455  for (int I = 0; I != NumAddrSpace; ++I) {
456  unsigned AddrSpace = MatchTable[CurrentIdx++];
459  dbgs() << "addrspace(" << MMOAddrSpace << ") vs "
460  << AddrSpace << '\n');
461 
462  if (AddrSpace == MMOAddrSpace) {
463  Success = true;
464  break;
465  }
466  }
467 
468  CurrentIdx = LastIdx;
469  if (!Success && handleReject() == RejectAndGiveUp)
470  return false;
471  break;
472  }
474  int64_t InsnID = MatchTable[CurrentIdx++];
475  int64_t MMOIdx = MatchTable[CurrentIdx++];
476  unsigned MinAlign = MatchTable[CurrentIdx++];
477 
478  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
479 
480  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
481  if (handleReject() == RejectAndGiveUp)
482  return false;
483  break;
484  }
485 
486  MachineMemOperand *MMO
487  = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
489  dbgs() << CurrentIdx << ": GIM_CheckMemoryAlignment"
490  << "(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
491  << ")->getAlignment() >= " << MinAlign << ")\n");
492  if (MMO->getAlign() < MinAlign && handleReject() == RejectAndGiveUp)
493  return false;
494 
495  break;
496  }
498  int64_t InsnID = MatchTable[CurrentIdx++];
499  int64_t MMOIdx = MatchTable[CurrentIdx++];
500  uint64_t Size = MatchTable[CurrentIdx++];
501 
503  dbgs() << CurrentIdx
504  << ": GIM_CheckMemorySizeEqual(MIs[" << InsnID
505  << "]->memoperands() + " << MMOIdx
506  << ", Size=" << Size << ")\n");
507  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
508 
509  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
510  if (handleReject() == RejectAndGiveUp)
511  return false;
512  break;
513  }
514 
515  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
516 
518  dbgs() << MMO->getSize() << " bytes vs " << Size
519  << " bytes\n");
520  if (MMO->getSize() != Size)
521  if (handleReject() == RejectAndGiveUp)
522  return false;
523 
524  break;
525  }
529  int64_t InsnID = MatchTable[CurrentIdx++];
530  int64_t MMOIdx = MatchTable[CurrentIdx++];
531  int64_t OpIdx = MatchTable[CurrentIdx++];
532 
535  dbgs() << CurrentIdx << ": GIM_CheckMemorySize"
536  << (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT
537  ? "EqualTo"
538  : MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT
539  ? "GreaterThan"
540  : "LessThan")
541  << "LLT(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
542  << ", OpIdx=" << OpIdx << ")\n");
543  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
544 
545  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
546  if (!MO.isReg()) {
548  dbgs() << CurrentIdx << ": Not a register\n");
549  if (handleReject() == RejectAndGiveUp)
550  return false;
551  break;
552  }
553 
554  if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
555  if (handleReject() == RejectAndGiveUp)
556  return false;
557  break;
558  }
559 
560  MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
561 
562  unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
563  if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
564  MMO->getSizeInBits() != Size) {
565  if (handleReject() == RejectAndGiveUp)
566  return false;
567  } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
568  MMO->getSizeInBits() >= Size) {
569  if (handleReject() == RejectAndGiveUp)
570  return false;
571  } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
572  MMO->getSizeInBits() <= Size)
573  if (handleReject() == RejectAndGiveUp)
574  return false;
575 
576  break;
577  }
578  case GIM_CheckType: {
579  int64_t InsnID = MatchTable[CurrentIdx++];
580  int64_t OpIdx = MatchTable[CurrentIdx++];
581  int64_t TypeID = MatchTable[CurrentIdx++];
583  dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
584  << "]->getOperand(" << OpIdx
585  << "), TypeID=" << TypeID << ")\n");
586  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
587  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
588  if (!MO.isReg() ||
589  MRI.getType(MO.getReg()) != ISelInfo.TypeObjects[TypeID]) {
590  if (handleReject() == RejectAndGiveUp)
591  return false;
592  }
593  break;
594  }
595  case GIM_CheckPointerToAny: {
596  int64_t InsnID = MatchTable[CurrentIdx++];
597  int64_t OpIdx = MatchTable[CurrentIdx++];
598  uint64_t SizeInBits = MatchTable[CurrentIdx++];
599 
601  dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs["
602  << InsnID << "]->getOperand(" << OpIdx
603  << "), SizeInBits=" << SizeInBits << ")\n");
604  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
605  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
606  const LLT Ty = MRI.getType(MO.getReg());
607 
608  // iPTR must be looked up in the target.
609  if (SizeInBits == 0) {
610  MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
611  const unsigned AddrSpace = Ty.getAddressSpace();
612  SizeInBits = MF->getDataLayout().getPointerSizeInBits(AddrSpace);
613  }
614 
615  assert(SizeInBits != 0 && "Pointer size must be known");
616 
617  if (MO.isReg()) {
618  if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits)
619  if (handleReject() == RejectAndGiveUp)
620  return false;
621  } else if (handleReject() == RejectAndGiveUp)
622  return false;
623 
624  break;
625  }
626  case GIM_RecordNamedOperand: {
627  int64_t InsnID = MatchTable[CurrentIdx++];
628  int64_t OpIdx = MatchTable[CurrentIdx++];
629  uint64_t StoreIdx = MatchTable[CurrentIdx++];
630 
632  dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs["
633  << InsnID << "]->getOperand(" << OpIdx
634  << "), StoreIdx=" << StoreIdx << ")\n");
635  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
636  assert(StoreIdx < State.RecordedOperands.size() && "Index out of range");
637  State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx);
638  break;
639  }
641  int64_t InsnID = MatchTable[CurrentIdx++];
642  int64_t OpIdx = MatchTable[CurrentIdx++];
643  int64_t RCEnum = MatchTable[CurrentIdx++];
645  dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
646  << InsnID << "]->getOperand(" << OpIdx
647  << "), RCEnum=" << RCEnum << ")\n");
648  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
649  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
650  if (!MO.isReg() ||
651  &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum),
652  MRI.getType(MO.getReg())) !=
653  RBI.getRegBank(MO.getReg(), MRI, TRI)) {
654  if (handleReject() == RejectAndGiveUp)
655  return false;
656  }
657  break;
658  }
659 
661  int64_t InsnID = MatchTable[CurrentIdx++];
662  int64_t OpIdx = MatchTable[CurrentIdx++];
663  int64_t RendererID = MatchTable[CurrentIdx++];
664  int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
666  dbgs() << CurrentIdx << ": State.Renderers[" << RendererID
667  << "] = GIM_CheckComplexPattern(MIs[" << InsnID
668  << "]->getOperand(" << OpIdx
669  << "), ComplexPredicateID=" << ComplexPredicateID
670  << ")\n");
671  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
672  // FIXME: Use std::invoke() when it's available.
673  ComplexRendererFns Renderer =
674  (ISel.*ISelInfo.ComplexPredicates[ComplexPredicateID])(
675  State.MIs[InsnID]->getOperand(OpIdx));
676  if (Renderer.hasValue())
677  State.Renderers[RendererID] = Renderer.getValue();
678  else
679  if (handleReject() == RejectAndGiveUp)
680  return false;
681  break;
682  }
683 
684  case GIM_CheckConstantInt: {
685  int64_t InsnID = MatchTable[CurrentIdx++];
686  int64_t OpIdx = MatchTable[CurrentIdx++];
687  int64_t Value = MatchTable[CurrentIdx++];
689  dbgs() << CurrentIdx << ": GIM_CheckConstantInt(MIs["
690  << InsnID << "]->getOperand(" << OpIdx
691  << "), Value=" << Value << ")\n");
692  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
693  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
694  if (MO.isReg()) {
695  // isOperandImmEqual() will sign-extend to 64-bits, so should we.
696  LLT Ty = MRI.getType(MO.getReg());
698 
699  if (!isOperandImmEqual(MO, Value, MRI)) {
700  if (handleReject() == RejectAndGiveUp)
701  return false;
702  }
703  } else if (handleReject() == RejectAndGiveUp)
704  return false;
705 
706  break;
707  }
708 
709  case GIM_CheckLiteralInt: {
710  int64_t InsnID = MatchTable[CurrentIdx++];
711  int64_t OpIdx = MatchTable[CurrentIdx++];
712  int64_t Value = MatchTable[CurrentIdx++];
714  dbgs() << CurrentIdx << ": GIM_CheckLiteralInt(MIs["
715  << InsnID << "]->getOperand(" << OpIdx
716  << "), Value=" << Value << ")\n");
717  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
718  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
719  if (MO.isImm() && MO.getImm() == Value)
720  break;
721 
722  if (MO.isCImm() && MO.getCImm()->equalsInt(Value))
723  break;
724 
725  if (handleReject() == RejectAndGiveUp)
726  return false;
727 
728  break;
729  }
730 
731  case GIM_CheckIntrinsicID: {
732  int64_t InsnID = MatchTable[CurrentIdx++];
733  int64_t OpIdx = MatchTable[CurrentIdx++];
734  int64_t Value = MatchTable[CurrentIdx++];
736  dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs["
737  << InsnID << "]->getOperand(" << OpIdx
738  << "), Value=" << Value << ")\n");
739  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
740  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
741  if (!MO.isIntrinsicID() || MO.getIntrinsicID() != Value)
742  if (handleReject() == RejectAndGiveUp)
743  return false;
744  break;
745  }
746  case GIM_CheckCmpPredicate: {
747  int64_t InsnID = MatchTable[CurrentIdx++];
748  int64_t OpIdx = MatchTable[CurrentIdx++];
749  int64_t Value = MatchTable[CurrentIdx++];
751  dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs["
752  << InsnID << "]->getOperand(" << OpIdx
753  << "), Value=" << Value << ")\n");
754  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
755  MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
756  if (!MO.isPredicate() || MO.getPredicate() != Value)
757  if (handleReject() == RejectAndGiveUp)
758  return false;
759  break;
760  }
761  case GIM_CheckIsMBB: {
762  int64_t InsnID = MatchTable[CurrentIdx++];
763  int64_t OpIdx = MatchTable[CurrentIdx++];
765  dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID
766  << "]->getOperand(" << OpIdx << "))\n");
767  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
768  if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
769  if (handleReject() == RejectAndGiveUp)
770  return false;
771  }
772  break;
773  }
774  case GIM_CheckIsImm: {
775  int64_t InsnID = MatchTable[CurrentIdx++];
776  int64_t OpIdx = MatchTable[CurrentIdx++];
778  dbgs() << CurrentIdx << ": GIM_CheckIsImm(MIs[" << InsnID
779  << "]->getOperand(" << OpIdx << "))\n");
780  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
781  if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) {
782  if (handleReject() == RejectAndGiveUp)
783  return false;
784  }
785  break;
786  }
787  case GIM_CheckIsSafeToFold: {
788  int64_t InsnID = MatchTable[CurrentIdx++];
790  dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs["
791  << InsnID << "])\n");
792  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
793  if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) {
794  if (handleReject() == RejectAndGiveUp)
795  return false;
796  }
797  break;
798  }
799  case GIM_CheckIsSameOperand: {
800  int64_t InsnID = MatchTable[CurrentIdx++];
801  int64_t OpIdx = MatchTable[CurrentIdx++];
802  int64_t OtherInsnID = MatchTable[CurrentIdx++];
803  int64_t OtherOpIdx = MatchTable[CurrentIdx++];
805  dbgs() << CurrentIdx << ": GIM_CheckIsSameOperand(MIs["
806  << InsnID << "][" << OpIdx << "], MIs["
807  << OtherInsnID << "][" << OtherOpIdx << "])\n");
808  assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
809  assert(State.MIs[OtherInsnID] != nullptr && "Used insn before defined");
810  if (!State.MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
811  State.MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
812  if (handleReject() == RejectAndGiveUp)
813  return false;
814  }
815  break;
816  }
817  case GIM_Reject:
819  dbgs() << CurrentIdx << ": GIM_Reject\n");
820  if (handleReject() == RejectAndGiveUp)
821  return false;
822  break;
823 
824  case GIR_MutateOpcode: {
825  int64_t OldInsnID = MatchTable[CurrentIdx++];
826  uint64_t NewInsnID = MatchTable[CurrentIdx++];
827  int64_t NewOpcode = MatchTable[CurrentIdx++];
828  if (NewInsnID >= OutMIs.size())
829  OutMIs.resize(NewInsnID + 1);
830 
831  OutMIs[NewInsnID] = MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(),
832  State.MIs[OldInsnID]);
833  OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
835  dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs["
836  << NewInsnID << "], MIs[" << OldInsnID << "], "
837  << NewOpcode << ")\n");
838  break;
839  }
840 
841  case GIR_BuildMI: {
842  uint64_t NewInsnID = MatchTable[CurrentIdx++];
843  int64_t Opcode = MatchTable[CurrentIdx++];
844  if (NewInsnID >= OutMIs.size())
845  OutMIs.resize(NewInsnID + 1);
846 
847  OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
848  State.MIs[0]->getDebugLoc(), TII.get(Opcode));
850  dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
851  << NewInsnID << "], " << Opcode << ")\n");
852  break;
853  }
854 
855  case GIR_Copy: {
856  int64_t NewInsnID = MatchTable[CurrentIdx++];
857  int64_t OldInsnID = MatchTable[CurrentIdx++];
858  int64_t OpIdx = MatchTable[CurrentIdx++];
859  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
860  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
862  dbgs()
863  << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
864  << "], MIs[" << OldInsnID << "], " << OpIdx << ")\n");
865  break;
866  }
867 
868  case GIR_CopyOrAddZeroReg: {
869  int64_t NewInsnID = MatchTable[CurrentIdx++];
870  int64_t OldInsnID = MatchTable[CurrentIdx++];
871  int64_t OpIdx = MatchTable[CurrentIdx++];
872  int64_t ZeroReg = MatchTable[CurrentIdx++];
873  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
874  MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
875  if (isOperandImmEqual(MO, 0, MRI))
876  OutMIs[NewInsnID].addReg(ZeroReg);
877  else
878  OutMIs[NewInsnID].add(MO);
880  dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs["
881  << NewInsnID << "], MIs[" << OldInsnID << "], "
882  << OpIdx << ", " << ZeroReg << ")\n");
883  break;
884  }
885 
886  case GIR_CopySubReg: {
887  int64_t NewInsnID = MatchTable[CurrentIdx++];
888  int64_t OldInsnID = MatchTable[CurrentIdx++];
889  int64_t OpIdx = MatchTable[CurrentIdx++];
890  int64_t SubRegIdx = MatchTable[CurrentIdx++];
891  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
892  OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
893  0, SubRegIdx);
895  dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
896  << NewInsnID << "], MIs[" << OldInsnID << "], "
897  << OpIdx << ", " << SubRegIdx << ")\n");
898  break;
899  }
900 
901  case GIR_AddImplicitDef: {
902  int64_t InsnID = MatchTable[CurrentIdx++];
903  int64_t RegNum = MatchTable[CurrentIdx++];
904  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
905  OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
907  dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
908  << InsnID << "], " << RegNum << ")\n");
909  break;
910  }
911 
912  case GIR_AddImplicitUse: {
913  int64_t InsnID = MatchTable[CurrentIdx++];
914  int64_t RegNum = MatchTable[CurrentIdx++];
915  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
916  OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
918  dbgs() << CurrentIdx << ": GIR_AddImplicitUse(OutMIs["
919  << InsnID << "], " << RegNum << ")\n");
920  break;
921  }
922 
923  case GIR_AddRegister: {
924  int64_t InsnID = MatchTable[CurrentIdx++];
925  int64_t RegNum = MatchTable[CurrentIdx++];
926  uint64_t RegFlags = MatchTable[CurrentIdx++];
927  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
928  OutMIs[InsnID].addReg(RegNum, RegFlags);
931  dbgs() << CurrentIdx << ": GIR_AddRegister(OutMIs["
932  << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
933  break;
934  }
935 
936  case GIR_AddTempRegister:
937  case GIR_AddTempSubRegister: {
938  int64_t InsnID = MatchTable[CurrentIdx++];
939  int64_t TempRegID = MatchTable[CurrentIdx++];
940  uint64_t TempRegFlags = MatchTable[CurrentIdx++];
941  unsigned SubReg = 0;
942  if (MatcherOpcode == GIR_AddTempSubRegister)
943  SubReg = MatchTable[CurrentIdx++];
944 
945  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
946 
947  OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg);
949  dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs["
950  << InsnID << "], TempRegisters[" << TempRegID
951  << "]";
952  if (SubReg)
953  dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
954  dbgs() << ", " << TempRegFlags << ")\n");
955  break;
956  }
957 
958  case GIR_AddImm: {
959  int64_t InsnID = MatchTable[CurrentIdx++];
960  int64_t Imm = MatchTable[CurrentIdx++];
961  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
962  OutMIs[InsnID].addImm(Imm);
964  dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
965  << "], " << Imm << ")\n");
966  break;
967  }
968 
969  case GIR_ComplexRenderer: {
970  int64_t InsnID = MatchTable[CurrentIdx++];
971  int64_t RendererID = MatchTable[CurrentIdx++];
972  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
973  for (const auto &RenderOpFn : State.Renderers[RendererID])
974  RenderOpFn(OutMIs[InsnID]);
976  dbgs() << CurrentIdx << ": GIR_ComplexRenderer(OutMIs["
977  << InsnID << "], " << RendererID << ")\n");
978  break;
979  }
981  int64_t InsnID = MatchTable[CurrentIdx++];
982  int64_t RendererID = MatchTable[CurrentIdx++];
983  int64_t RenderOpID = MatchTable[CurrentIdx++];
984  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
985  State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
987  dbgs() << CurrentIdx
988  << ": GIR_ComplexSubOperandRenderer(OutMIs["
989  << InsnID << "], " << RendererID << ", "
990  << RenderOpID << ")\n");
991  break;
992  }
993 
994  case GIR_CopyConstantAsSImm: {
995  int64_t NewInsnID = MatchTable[CurrentIdx++];
996  int64_t OldInsnID = MatchTable[CurrentIdx++];
997  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
998  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
999  if (State.MIs[OldInsnID]->getOperand(1).isCImm()) {
1000  OutMIs[NewInsnID].addImm(
1001  State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
1002  } else if (State.MIs[OldInsnID]->getOperand(1).isImm())
1003  OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
1004  else
1005  llvm_unreachable("Expected Imm or CImm operand");
1007  dbgs() << CurrentIdx << ": GIR_CopyConstantAsSImm(OutMIs["
1008  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1009  break;
1010  }
1011 
1012  // TODO: Needs a test case once we have a pattern that uses this.
1013  case GIR_CopyFConstantAsFPImm: {
1014  int64_t NewInsnID = MatchTable[CurrentIdx++];
1015  int64_t OldInsnID = MatchTable[CurrentIdx++];
1016  assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1017  assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT");
1018  if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
1019  OutMIs[NewInsnID].addFPImm(
1020  State.MIs[OldInsnID]->getOperand(1).getFPImm());
1021  else
1022  llvm_unreachable("Expected FPImm operand");
1024  dbgs() << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
1025  << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1026  break;
1027  }
1028 
1029  case GIR_CustomRenderer: {
1030  int64_t InsnID = MatchTable[CurrentIdx++];
1031  int64_t OldInsnID = MatchTable[CurrentIdx++];
1032  int64_t RendererFnID = MatchTable[CurrentIdx++];
1033  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1035  dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs["
1036  << InsnID << "], MIs[" << OldInsnID << "], "
1037  << RendererFnID << ")\n");
1038  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(
1039  OutMIs[InsnID], *State.MIs[OldInsnID],
1040  -1); // Not a source operand of the old instruction.
1041  break;
1042  }
1044  int64_t InsnID = MatchTable[CurrentIdx++];
1045  int64_t OldInsnID = MatchTable[CurrentIdx++];
1046  int64_t OpIdx = MatchTable[CurrentIdx++];
1047  int64_t RendererFnID = MatchTable[CurrentIdx++];
1048  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1049 
1052  dbgs() << CurrentIdx << ": GIR_CustomOperandRenderer(OutMIs["
1053  << InsnID << "], MIs[" << OldInsnID << "]->getOperand("
1054  << OpIdx << "), "
1055  << RendererFnID << ")\n");
1056  (ISel.*ISelInfo.CustomRenderers[RendererFnID])(OutMIs[InsnID],
1057  *State.MIs[OldInsnID],
1058  OpIdx);
1059  break;
1060  }
1061  case GIR_ConstrainOperandRC: {
1062  int64_t InsnID = MatchTable[CurrentIdx++];
1063  int64_t OpIdx = MatchTable[CurrentIdx++];
1064  int64_t RCEnum = MatchTable[CurrentIdx++];
1065  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1066  MachineInstr &I = *OutMIs[InsnID].getInstr();
1067  MachineFunction &MF = *I.getParent()->getParent();
1069  const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum);
1070  MachineOperand &MO = I.getOperand(OpIdx);
1071  constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO);
1073  dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
1074  << InsnID << "], " << OpIdx << ", " << RCEnum
1075  << ")\n");
1076  break;
1077  }
1078 
1080  int64_t InsnID = MatchTable[CurrentIdx++];
1081  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1082  constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
1083  RBI);
1085  dbgs() << CurrentIdx
1086  << ": GIR_ConstrainSelectedInstOperands(OutMIs["
1087  << InsnID << "])\n");
1088  break;
1089  }
1090 
1091  case GIR_MergeMemOperands: {
1092  int64_t InsnID = MatchTable[CurrentIdx++];
1093  assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1094 
1096  dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs["
1097  << InsnID << "]");
1098  int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList;
1099  while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
1102  dbgs() << ", MIs[" << MergeInsnID << "]");
1103  for (const auto &MMO : State.MIs[MergeInsnID]->memoperands())
1104  OutMIs[InsnID].addMemOperand(MMO);
1105  }
1107  break;
1108  }
1109 
1110  case GIR_EraseFromParent: {
1111  int64_t InsnID = MatchTable[CurrentIdx++];
1112  assert(State.MIs[InsnID] &&
1113  "Attempted to erase an undefined instruction");
1114  State.MIs[InsnID]->eraseFromParent();
1116  dbgs() << CurrentIdx << ": GIR_EraseFromParent(MIs["
1117  << InsnID << "])\n");
1118  break;
1119  }
1120 
1121  case GIR_MakeTempReg: {
1122  int64_t TempRegID = MatchTable[CurrentIdx++];
1123  int64_t TypeID = MatchTable[CurrentIdx++];
1124 
1125  State.TempRegisters[TempRegID] =
1126  MRI.createGenericVirtualRegister(ISelInfo.TypeObjects[TypeID]);
1128  dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
1129  << "] = GIR_MakeTempReg(" << TypeID << ")\n");
1130  break;
1131  }
1132 
1133  case GIR_Coverage: {
1134  int64_t RuleID = MatchTable[CurrentIdx++];
1135  CoverageInfo.setCovered(RuleID);
1136 
1138  dbgs()
1139  << CurrentIdx << ": GIR_Coverage(" << RuleID << ")");
1140  break;
1141  }
1142 
1143  case GIR_Done:
1145  dbgs() << CurrentIdx << ": GIR_Done\n");
1146  propagateFlags(OutMIs);
1147  return true;
1148 
1149  default:
1150  llvm_unreachable("Unexpected command");
1151  }
1152  }
1153 }
1154 
1155 } // end namespace llvm
1156 
1157 #endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::GIR_MutateOpcode
@ GIR_MutateOpcode
Mutate an instruction.
Definition: InstructionSelector.h:285
llvm::GIPFP_I64_Invalid
@ GIPFP_I64_Invalid
Definition: InstructionSelectorImpl.h:41
llvm::InstructionSelector::MatcherState::Renderers
std::vector< ComplexRendererFns::value_type > Renderers
Definition: InstructionSelector.h:471
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::GIR_ComplexRenderer
@ GIR_ComplexRenderer
Render complex operands to the specified instruction.
Definition: InstructionSelector.h:345
llvm::GIR_AddRegister
@ GIR_AddRegister
Add an register to the specified instruction.
Definition: InstructionSelector.h:323
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1087
llvm::InstructionSelector::testMIPredicate_MI
virtual bool testMIPredicate_MI(unsigned, const MachineInstr &, const std::array< const MachineOperand *, 3 > &Operands) const
Definition: InstructionSelector.h:545
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::GIM_CheckOpcode
@ GIM_CheckOpcode
Check the opcode on the specified instruction.
Definition: InstructionSelector.h:118
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:583
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::GIR_EraseFromParent
@ GIR_EraseFromParent
Erase from parent.
Definition: InstructionSelector.h:398
llvm::GIR_ComplexSubOperandRenderer
@ GIR_ComplexSubOperandRenderer
Render sub-operands of complex operands to the specified instruction.
Definition: InstructionSelector.h:351
llvm::GIR_AddImplicitUse
@ GIR_AddImplicitUse
Add an implicit register use to the specified instruction.
Definition: InstructionSelector.h:319
llvm::GIM_CheckIsBuildVectorAllOnes
@ GIM_CheckIsBuildVectorAllOnes
Check if this is a vector that can be treated as a vector splat constant.
Definition: InstructionSelector.h:190
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:432
ErrorHandling.h
RegisterBankInfo.h
llvm::InstructionSelector::MatcherState
Definition: InstructionSelector.h:470
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:241
llvm::GIM_RecordNamedOperand
@ GIM_RecordNamedOperand
Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some named operands that will be ...
Definition: InstructionSelector.h:273
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::GIR_Coverage
@ GIR_Coverage
Increment the rule coverage counter.
Definition: InstructionSelector.h:410
llvm::GIM_CheckLiteralInt
@ GIM_CheckLiteralInt
Check the operand is a specific literal integer (i.e.
Definition: InstructionSelector.h:231
llvm::GIM_CheckType
@ GIM_CheckType
Check the type for the specified operand.
Definition: InstructionSelector.h:202
llvm::GIR_CustomOperandRenderer
@ GIR_CustomOperandRenderer
Render operands to the specified instruction using a custom function, reading from a specific operand...
Definition: InstructionSelector.h:364
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::GIM_CheckConstantInt
@ GIM_CheckConstantInt
Check the operand is a specific integer.
Definition: InstructionSelector.h:225
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:325
llvm::InstructionSelector::MatcherState::MIs
RecordedMIVector MIs
Definition: InstructionSelector.h:472
llvm::Optional
Definition: APInt.h:33
llvm::InstructionSelector::testImmPredicate_I64
virtual bool testImmPredicate_I64(unsigned, int64_t) const
Definition: InstructionSelector.h:533
llvm::GIM_CheckCxxInsnPredicate
@ GIM_CheckCxxInsnPredicate
Check a generic C++ instruction predicate.
Definition: InstructionSelector.h:196
llvm::Expected
Tagged union holding either a T or a Error.
Definition: APFloat.h:42
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:635
llvm::CodeGenCoverage::setCovered
void setCovered(uint64_t RuleID)
Definition: CodeGenCoverage.cpp:28
llvm::GIM_CheckIsBuildVectorAllZeros
@ GIM_CheckIsBuildVectorAllZeros
Definition: InstructionSelector.h:191
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::InstructionSelector::MatcherState::TempRegisters
DenseMap< unsigned, unsigned > TempRegisters
Definition: InstructionSelector.h:473
llvm::GIM_CheckIntrinsicID
@ GIM_CheckIntrinsicID
Check the operand is a specific intrinsic ID.
Definition: InstructionSelector.h:236
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:136
MachineRegisterInfo.h
llvm::GIR_AddImm
@ GIR_AddImm
Add an immediate to the specified instruction.
Definition: InstructionSelector.h:341
llvm::Optional::hasValue
constexpr bool hasValue() const
Definition: Optional.h:288
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::GIPFP_APInt_Invalid
@ GIPFP_APInt_Invalid
Definition: InstructionSelectorImpl.h:42
llvm::isAtLeastOrStrongerThan
bool isAtLeastOrStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Definition: AtomicOrdering.h:105
llvm::GIM_CheckMemorySizeGreaterThanLLT
@ GIM_CheckMemorySizeGreaterThanLLT
Definition: InstructionSelector.h:183
llvm::MinAlign
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:672
llvm::GIM_CheckRegBankForClass
@ GIM_CheckRegBankForClass
Check the register bank for the specified operand.
Definition: InstructionSelector.h:212
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
DEBUG_WITH_TYPE
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
llvm::InstructionSelector::ISelInfoTy::CustomRenderers
const CustomRendererFn * CustomRenderers
Definition: InstructionSelector.h:508
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
Constants.h
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:229
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::GIM_CheckImmOperandPredicate
@ GIM_CheckImmOperandPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:147
llvm::GIM_CheckAtomicOrderingOrStrongerThan
@ GIM_CheckAtomicOrderingOrStrongerThan
Definition: InstructionSelector.h:152
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:439
Utils.h
llvm::ConstantInt::equalsInt
bool equalsInt(uint64_t V) const
A helper method that can be used to determine if the constant contained within is equal to a constant...
Definition: Constants.h:168
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::GIM_Try
@ GIM_Try
Begin a try-block to attempt a match and jump to OnFail if it is unsuccessful.
Definition: InstructionSelector.h:86
llvm::GIM_SwitchType
@ GIM_SwitchType
Switch over the LLT on the specified instruction operand.
Definition: InstructionSelector.h:103
llvm::InstructionSelector::MatcherState::RecordedOperands
std::array< const MachineOperand *, 3 > RecordedOperands
Named operands that predicate with 'let PredicateCodeUsesOperands = 1' referenced in its argument lis...
Definition: InstructionSelector.h:478
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:606
llvm::GIM_CheckIsImm
@ GIM_CheckIsImm
Check the specified operand is an Imm.
Definition: InstructionSelector.h:252
llvm::GIR_Copy
@ GIR_Copy
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:296
llvm::GIR_CopySubReg
@ GIR_CopySubReg
Copy an operand to the specified instruction.
Definition: InstructionSelector.h:310
llvm::MachineInstr::NoFPExcept
@ NoFPExcept
Definition: MachineInstr.h:108
llvm::GIM_SwitchOpcode
@ GIM_SwitchOpcode
Switch over the opcode on the specified instruction.
Definition: InstructionSelector.h:94
llvm::GIM_CheckIsSafeToFold
@ GIM_CheckIsSafeToFold
Check if the specified operand is safe to fold into the current instruction.
Definition: InstructionSelector.h:257
InstructionSelector.h
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:227
llvm::GIM_Reject
@ GIM_Reject
Fail the current try-block, or completely fail to match if there is no current try-block.
Definition: InstructionSelector.h:277
llvm::GIR_CopyConstantAsSImm
@ GIR_CopyConstantAsSImm
Render a G_CONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:370
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:441
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
TypeID
Type::TypeID TypeID
Definition: Mips16HardFloat.cpp:102
llvm::InstructionSelector::isOperandImmEqual
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
Definition: InstructionSelector.cpp:36
llvm::APFloat
Definition: APFloat.h:701
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::InstructionSelector::ISelInfoTy::TypeIDMap
SmallDenseMap< LLT, unsigned, 64 > TypeIDMap
Definition: InstructionSelector.h:510
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:20
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:542
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::GIM_CheckCmpPredicate
@ GIM_CheckCmpPredicate
Check the operand is a specific predicate.
Definition: InstructionSelector.h:242
llvm::GIM_CheckMemoryAddressSpace
@ GIM_CheckMemoryAddressSpace
Check the address space of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:167
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::GIR_CopyOrAddZeroReg
@ GIR_CopyOrAddZeroReg
Copy an operand to the specified instruction or add a zero register if the operand is a zero immediat...
Definition: InstructionSelector.h:304
llvm::GIR_AddTempSubRegister
@ GIR_AddTempSubRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:336
llvm::InstructionSelector::ISelInfoTy::TypeObjects
const LLT * TypeObjects
Definition: InstructionSelector.h:505
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:588
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:121
llvm::GIM_CheckMemoryAlignment
@ GIM_CheckMemoryAlignment
Check the minimum alignment of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:174
llvm::GIR_MakeTempReg
@ GIR_MakeTempReg
Create a new temporary register that's not constrained.
Definition: InstructionSelector.h:403
llvm::GIR_CustomRenderer
@ GIR_CustomRenderer
Render operands to the specified instruction using a custom function.
Definition: InstructionSelector.h:356
llvm::GIR_CopyFConstantAsFPImm
@ GIR_CopyFConstantAsFPImm
Render a G_FCONSTANT operator as a sign-extended immediate.
Definition: InstructionSelector.h:376
llvm::GIM_CheckAtomicOrderingWeakerThan
@ GIM_CheckAtomicOrderingWeakerThan
Definition: InstructionSelector.h:153
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::GIM_CheckNumOperands
@ GIM_CheckNumOperands
Check the instruction has the right number of operands.
Definition: InstructionSelector.h:130
llvm::GIR_Done
@ GIR_Done
A successful emission.
Definition: InstructionSelector.h:406
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::InstructionSelector::testImmPredicate_APFloat
virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const
Definition: InstructionSelector.h:541
llvm::GIR_AddTempRegister
@ GIR_AddTempRegister
Add a temporary register to the specified instruction.
Definition: InstructionSelector.h:329
llvm::GIM_CheckComplexPattern
@ GIM_CheckComplexPattern
Check the operand matches a complex predicate.
Definition: InstructionSelector.h:219
DataLayout.h
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:352
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::GIM_CheckMemorySizeEqualTo
@ GIM_CheckMemorySizeEqualTo
Check the size of the memory access for the given machine memory operand.
Definition: InstructionSelector.h:158
llvm::GIM_CheckAPIntImmPredicate
@ GIM_CheckAPIntImmPredicate
Check an immediate predicate on the specified instruction via an APInt.
Definition: InstructionSelector.h:138
llvm::GIM_RecordInsn
@ GIM_RecordInsn
Record the specified instruction.
Definition: InstructionSelector.h:109
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:777
llvm::InstructionSelector::ISelInfoTy::ComplexPredicates
const ComplexMatcherMemFn * ComplexPredicates
Definition: InstructionSelector.h:507
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::InstructionSelector::ISelInfoTy::FeatureBitsets
const PredicateBitset * FeatureBitsets
Definition: InstructionSelector.h:506
llvm::RegisterBankInfo::getRegBankFromRegClass
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
Definition: RegisterBankInfo.h:604
llvm::GIM_CheckFeatures
@ GIM_CheckFeatures
Check the feature bits.
Definition: InstructionSelector.h:113
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1060
llvm::GIM_CheckMemorySizeLessThanLLT
@ GIM_CheckMemorySizeLessThanLLT
Definition: InstructionSelector.h:182
uint16_t
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
Success
#define Success
Definition: AArch64Disassembler.cpp:260
llvm::GIR_MergeMemOperands
@ GIR_MergeMemOperands
Merge all memory operands into instruction.
Definition: InstructionSelector.h:394
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::GIR_AddImplicitDef
@ GIR_AddImplicitDef
Add an implicit register def to the specified instruction.
Definition: InstructionSelector.h:315
llvm::GIM_CheckOpcodeIsEither
@ GIM_CheckOpcodeIsEither
Check the opcode on the specified instruction, checking 2 acceptable alternatives.
Definition: InstructionSelector.h:125
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::GIM_CheckMemorySizeEqualToLLT
@ GIM_CheckMemorySizeEqualToLLT
Check the size of the memory access for the given machine memory operand against the size of an opera...
Definition: InstructionSelector.h:181
llvm::InstructionSelector::isObviouslySafeToFold
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Definition: InstructionSelector.cpp:62
llvm::isStrongerThan
bool isStrongerThan(AtomicOrdering AO, AtomicOrdering Other)
Returns true if ao is stronger than other as defined by the AtomicOrdering lattice,...
Definition: AtomicOrdering.h:90
llvm::GIM_CheckAtomicOrdering
@ GIM_CheckAtomicOrdering
Check a memory operation has the specified atomic ordering.
Definition: InstructionSelector.h:151
llvm::GIM_CheckIsSameOperand
@ GIM_CheckIsSameOperand
Check the specified operands are identical.
Definition: InstructionSelector.h:264
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:353
SmallVector.h
MachineInstrBuilder.h
llvm::GIR_ConstrainOperandRC
@ GIR_ConstrainOperandRC
Constrain an instruction operand to a register class.
Definition: InstructionSelector.h:382
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::InstructionSelector::testImmPredicate_APInt
virtual bool testImmPredicate_APInt(unsigned, const APInt &) const
Definition: InstructionSelector.h:537
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:50
llvm::InstructionSelector::ISelInfoTy
Definition: InstructionSelector.h:492
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
MachineOperand.h
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:409
llvm::GIPFP_MI_Invalid
@ GIPFP_MI_Invalid
Definition: InstructionSelectorImpl.h:44
llvm::GIR_ConstrainSelectedInstOperands
@ GIR_ConstrainSelectedInstOperands
Constrain an instructions operands according to the instruction description.
Definition: InstructionSelector.h:387
llvm::InstructionSelector::executeMatchTable
bool executeMatchTable(TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
Execute a given matcher table and return true if the match was successful and false otherwise.
Definition: InstructionSelectorImpl.h:49
llvm::GIM_CheckIsMBB
@ GIM_CheckIsMBB
Check the specified operand is an MBB.
Definition: InstructionSelector.h:247
llvm::GIM_CheckI64ImmPredicate
@ GIM_CheckI64ImmPredicate
Check an immediate predicate on the specified instruction.
Definition: InstructionSelector.h:134
llvm::GIR_BuildMI
@ GIR_BuildMI
Build a new instruction.
Definition: InstructionSelector.h:290
raw_ostream.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::GIM_CheckPointerToAny
@ GIM_CheckPointerToAny
Check the type of a pointer to any address space.
Definition: InstructionSelector.h:207
TargetRegisterInfo.h
llvm::GIU_MergeMemOperands_EndOfList
@ GIU_MergeMemOperands_EndOfList
Indicates the end of the variable-length MergeInsnID list in a GIR_MergeMemOperands opcode.
Definition: InstructionSelector.h:419
llvm::GIPFP_APFloat_Invalid
@ GIPFP_APFloat_Invalid
Definition: InstructionSelectorImpl.h:43
Debug.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1054
llvm::GIM_CheckAPFloatImmPredicate
@ GIM_CheckAPFloatImmPredicate
Check a floating point immediate predicate on the specified instruction.
Definition: InstructionSelector.h:142
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:282
llvm::LLT
Definition: LowLevelTypeImpl.h:40