LLVM 17.0.0git
RISCVMCInstLower.cpp
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1//===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains code to lower RISCV MachineInstrs to their corresponding
10// MCInst records.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCV.h"
15#include "RISCVSubtarget.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCInst.h"
26
27using namespace llvm;
28
30 const AsmPrinter &AP) {
31 MCContext &Ctx = AP.OutContext;
33
34 switch (MO.getTargetFlags()) {
35 default:
36 llvm_unreachable("Unknown target flag on GV operand");
39 break;
42 break;
43 case RISCVII::MO_PLT:
45 break;
46 case RISCVII::MO_LO:
48 break;
49 case RISCVII::MO_HI:
51 break;
54 break;
57 break;
60 break;
63 break;
66 break;
69 break;
72 break;
75 break;
76 }
77
78 const MCExpr *ME =
80
81 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
83 ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
84
86 ME = RISCVMCExpr::create(ME, Kind, Ctx);
87 return MCOperand::createExpr(ME);
88}
89
91 MCOperand &MCOp,
92 const AsmPrinter &AP) {
93 switch (MO.getType()) {
94 default:
95 report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type");
97 // Ignore all implicit register operands.
98 if (MO.isImplicit())
99 return false;
100 MCOp = MCOperand::createReg(MO.getReg());
101 break;
103 // Regmasks are like implicit defs.
104 return false;
106 MCOp = MCOperand::createImm(MO.getImm());
107 break;
109 MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
110 break;
112 MCOp = lowerSymbolOperand(MO, AP.getSymbolPreferLocal(*MO.getGlobal()), AP);
113 break;
115 MCOp = lowerSymbolOperand(
116 MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
117 break;
119 MCOp = lowerSymbolOperand(
120 MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
121 break;
123 MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
124 break;
126 MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
127 break;
129 MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), AP);
130 break;
131 }
132 return true;
133}
134
136 MCInst &OutMI) {
138 RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
139 if (!RVV)
140 return false;
141
142 OutMI.setOpcode(RVV->BaseInstr);
143
144 const MachineBasicBlock *MBB = MI->getParent();
145 assert(MBB && "MI expected to be in a basic block");
146 const MachineFunction *MF = MBB->getParent();
147 assert(MF && "MBB expected to be in a machine function");
148
149 const TargetRegisterInfo *TRI =
150 MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
151
152 assert(TRI && "TargetRegisterInfo expected");
153
154 uint64_t TSFlags = MI->getDesc().TSFlags;
155 unsigned NumOps = MI->getNumExplicitOperands();
156
157 // Skip policy, VL and SEW operands which are the last operands if present.
159 --NumOps;
161 --NumOps;
163 --NumOps;
164
165 bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
166 for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
167 const MachineOperand &MO = MI->getOperand(OpNo);
168 // Skip vl ouput. It should be the second output.
169 if (hasVLOutput && OpNo == 1)
170 continue;
171
172 // Skip merge op. It should be the first operand after the result.
173 if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
174 assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
175 continue;
176 }
177
178 MCOperand MCOp;
179 switch (MO.getType()) {
180 default:
181 llvm_unreachable("Unknown operand type");
183 Register Reg = MO.getReg();
184
185 if (RISCV::VRM2RegClass.contains(Reg) ||
186 RISCV::VRM4RegClass.contains(Reg) ||
187 RISCV::VRM8RegClass.contains(Reg)) {
188 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
189 assert(Reg && "Subregister does not exist");
190 } else if (RISCV::FPR16RegClass.contains(Reg)) {
191 Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
192 assert(Reg && "Subregister does not exist");
193 } else if (RISCV::FPR64RegClass.contains(Reg)) {
194 Reg = TRI->getSubReg(Reg, RISCV::sub_32);
195 assert(Reg && "Superregister does not exist");
196 }
197
198 MCOp = MCOperand::createReg(Reg);
199 break;
200 }
202 MCOp = MCOperand::createImm(MO.getImm());
203 break;
204 }
205 OutMI.addOperand(MCOp);
206 }
207
208 // Unmasked pseudo instructions need to append dummy mask operand to
209 // V instructions. All V instructions are modeled as the masked version.
211 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
212
213 return true;
214}
215
217 AsmPrinter &AP) {
219 return false;
220
221 OutMI.setOpcode(MI->getOpcode());
222
223 for (const MachineOperand &MO : MI->operands()) {
224 MCOperand MCOp;
225 if (lowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
226 OutMI.addOperand(MCOp);
227 }
228
229 switch (OutMI.getOpcode()) {
230 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
231 const Function &F = MI->getParent()->getParent()->getFunction();
232 if (F.hasFnAttribute("patchable-function-entry")) {
233 unsigned Num;
234 if (F.getFnAttribute("patchable-function-entry")
235 .getValueAsString()
236 .getAsInteger(10, Num))
237 return false;
238 AP.emitNops(Num);
239 return true;
240 }
241 break;
242 }
243 case RISCV::PseudoReadVLENB:
244 OutMI.setOpcode(RISCV::CSRRS);
246 RISCVSysReg::lookupSysRegByName("VLENB")->Encoding));
247 OutMI.addOperand(MCOperand::createReg(RISCV::X0));
248 break;
249 case RISCV::PseudoReadVL:
250 OutMI.setOpcode(RISCV::CSRRS);
251 OutMI.addOperand(
252 MCOperand::createImm(RISCVSysReg::lookupSysRegByName("VL")->Encoding));
253 OutMI.addOperand(MCOperand::createReg(RISCV::X0));
254 break;
255 }
256 return false;
257}
MachineBasicBlock & MBB
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
uint64_t TSFlags
static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP)
static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:467
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:84
void emitNops(unsigned N)
Emit N NOP instructions.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
Definition: AsmPrinter.cpp:666
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:94
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:525
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
int64_t getImm() const
bool isImplicit() const
MachineBasicBlock * getMBB() const
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
static const RISCVMCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
Definition: RISCVMCExpr.cpp:31
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool hasDummyMaskOp(uint64_t TSFlags)
static bool hasMergeOp(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool hasSEWOp(uint64_t TSFlags)
bool isFaultFirstLoad(const MachineInstr &MI)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP)
bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)