LLVM  15.0.0git
RISCVMCInstLower.cpp
Go to the documentation of this file.
1 //===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains code to lower RISCV MachineInstrs to their corresponding
10 // MCInst records.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
26 
27 using namespace llvm;
28 
30  const AsmPrinter &AP) {
31  MCContext &Ctx = AP.OutContext;
33 
34  switch (MO.getTargetFlags()) {
35  default:
36  llvm_unreachable("Unknown target flag on GV operand");
37  case RISCVII::MO_None:
39  break;
40  case RISCVII::MO_CALL:
42  break;
43  case RISCVII::MO_PLT:
45  break;
46  case RISCVII::MO_LO:
48  break;
49  case RISCVII::MO_HI:
51  break;
54  break;
57  break;
58  case RISCVII::MO_GOT_HI:
60  break;
63  break;
66  break;
69  break;
72  break;
75  break;
76  }
77 
78  const MCExpr *ME =
80 
81  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
83  ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
84 
86  ME = RISCVMCExpr::create(ME, Kind, Ctx);
87  return MCOperand::createExpr(ME);
88 }
89 
91  MCOperand &MCOp,
92  const AsmPrinter &AP) {
93  switch (MO.getType()) {
94  default:
95  report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type");
97  // Ignore all implicit register operands.
98  if (MO.isImplicit())
99  return false;
100  MCOp = MCOperand::createReg(MO.getReg());
101  break;
103  // Regmasks are like implicit defs.
104  return false;
106  MCOp = MCOperand::createImm(MO.getImm());
107  break;
109  MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
110  break;
112  MCOp = lowerSymbolOperand(MO, AP.getSymbolPreferLocal(*MO.getGlobal()), AP);
113  break;
115  MCOp = lowerSymbolOperand(
116  MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
117  break;
119  MCOp = lowerSymbolOperand(
120  MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
121  break;
123  MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
124  break;
126  MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
127  break;
128  }
129  return true;
130 }
131 
133  MCInst &OutMI) {
134  const RISCVVPseudosTable::PseudoInfo *RVV =
135  RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
136  if (!RVV)
137  return false;
138 
139  OutMI.setOpcode(RVV->BaseInstr);
140 
141  const MachineBasicBlock *MBB = MI->getParent();
142  assert(MBB && "MI expected to be in a basic block");
143  const MachineFunction *MF = MBB->getParent();
144  assert(MF && "MBB expected to be in a machine function");
145 
146  const TargetRegisterInfo *TRI =
147  MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
148 
149  assert(TRI && "TargetRegisterInfo expected");
150 
151  uint64_t TSFlags = MI->getDesc().TSFlags;
152  unsigned NumOps = MI->getNumExplicitOperands();
153 
154  // Skip policy, VL and SEW operands which are the last operands if present.
155  if (RISCVII::hasVecPolicyOp(TSFlags))
156  --NumOps;
157  if (RISCVII::hasVLOp(TSFlags))
158  --NumOps;
159  if (RISCVII::hasSEWOp(TSFlags))
160  --NumOps;
161 
162  bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
163  for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
164  const MachineOperand &MO = MI->getOperand(OpNo);
165  // Skip vl ouput. It should be the second output.
166  if (hasVLOutput && OpNo == 1)
167  continue;
168 
169  // Skip merge op. It should be the first operand after the result.
170  if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
171  assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
172  continue;
173  }
174 
175  MCOperand MCOp;
176  switch (MO.getType()) {
177  default:
178  llvm_unreachable("Unknown operand type");
180  Register Reg = MO.getReg();
181 
182  if (RISCV::VRM2RegClass.contains(Reg) ||
183  RISCV::VRM4RegClass.contains(Reg) ||
184  RISCV::VRM8RegClass.contains(Reg)) {
185  Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
186  assert(Reg && "Subregister does not exist");
187  } else if (RISCV::FPR16RegClass.contains(Reg)) {
188  Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
189  assert(Reg && "Subregister does not exist");
190  } else if (RISCV::FPR64RegClass.contains(Reg)) {
191  Reg = TRI->getSubReg(Reg, RISCV::sub_32);
192  assert(Reg && "Superregister does not exist");
193  }
194 
195  MCOp = MCOperand::createReg(Reg);
196  break;
197  }
199  MCOp = MCOperand::createImm(MO.getImm());
200  break;
201  }
202  OutMI.addOperand(MCOp);
203  }
204 
205  // Unmasked pseudo instructions need to append dummy mask operand to
206  // V instructions. All V instructions are modeled as the masked version.
207  if (RISCVII::hasDummyMaskOp(TSFlags))
208  OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
209 
210  return true;
211 }
212 
214  AsmPrinter &AP) {
216  return false;
217 
218  OutMI.setOpcode(MI->getOpcode());
219 
220  for (const MachineOperand &MO : MI->operands()) {
221  MCOperand MCOp;
222  if (lowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
223  OutMI.addOperand(MCOp);
224  }
225 
226  switch (OutMI.getOpcode()) {
227  case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
228  const Function &F = MI->getParent()->getParent()->getFunction();
229  if (F.hasFnAttribute("patchable-function-entry")) {
230  unsigned Num;
231  if (F.getFnAttribute("patchable-function-entry")
232  .getValueAsString()
233  .getAsInteger(10, Num))
234  return false;
235  AP.emitNops(Num);
236  return true;
237  }
238  break;
239  }
240  case RISCV::PseudoReadVLENB:
241  OutMI.setOpcode(RISCV::CSRRS);
243  RISCVSysReg::lookupSysRegByName("VLENB")->Encoding));
244  OutMI.addOperand(MCOperand::createReg(RISCV::X0));
245  break;
246  case RISCV::PseudoReadVL:
247  OutMI.setOpcode(RISCV::CSRRS);
248  OutMI.addOperand(
250  OutMI.addOperand(MCOperand::createReg(RISCV::X0));
251  break;
252  }
253  return false;
254 }
AsmPrinter.h
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::RISCVII::MO_PLT
@ MO_PLT
Definition: RISCVBaseInfo.h:195
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::RISCVMCExpr::VK_RISCV_TLS_GD_HI
@ VK_RISCV_TLS_GD_HI
Definition: RISCVMCExpr.h:36
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::Function
Definition: Function.h:60
llvm::RISCVMCExpr::VK_RISCV_TPREL_ADD
@ VK_RISCV_TPREL_ADD
Definition: RISCVMCExpr.h:34
llvm::AArch64SysReg::lookupSysRegByName
const SysReg * lookupSysRegByName(StringRef)
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::RISCVII::MO_TLS_GD_HI
@ MO_TLS_GD_HI
Definition: RISCVBaseInfo.h:205
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:577
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::RISCVII::hasSEWOp
static bool hasSEWOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:151
llvm::MachineOperand::isJTI
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:336
RISCVMCExpr.h
llvm::RISCVMCExpr::VK_RISCV_TPREL_LO
@ VK_RISCV_TPREL_LO
Definition: RISCVMCExpr.h:32
llvm::RISCVVPseudosTable::PseudoInfo
Definition: RISCVInstrInfo.h:204
llvm::RISCVMCExpr::VK_RISCV_HI
@ VK_RISCV_HI
Definition: RISCVMCExpr.h:28
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::RISCVMCExpr::VK_RISCV_TPREL_HI
@ VK_RISCV_TPREL_HI
Definition: RISCVMCExpr.h:33
llvm::RISCVII::hasVecPolicyOp
static bool hasVecPolicyOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:159
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:609
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCV::isFaultFirstLoad
bool isFaultFirstLoad(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:1936
llvm::RISCVMCExpr::VK_RISCV_TLS_GOT_HI
@ VK_RISCV_TLS_GOT_HI
Definition: RISCVMCExpr.h:35
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::RISCVMCExpr::VariantKind
VariantKind
Definition: RISCVMCExpr.h:25
llvm::RISCVVPseudosTable::PseudoInfo::BaseInstr
uint16_t BaseInstr
Definition: RISCVInstrInfo.h:206
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:57
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::RISCVMCExpr::VK_RISCV_LO
@ VK_RISCV_LO
Definition: RISCVMCExpr.h:27
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
MCContext.h
llvm::lowerRISCVMachineInstrToMCInst
bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
Definition: RISCVMCInstLower.cpp:213
MCInst.h
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:328
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::RISCVII::hasVLOp
static bool hasVLOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:155
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::RISCVII::MO_GOT_HI
@ MO_GOT_HI
Definition: RISCVBaseInfo.h:200
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::RISCVMCExpr::VK_RISCV_None
@ VK_RISCV_None
Definition: RISCVMCExpr.h:26
llvm::RISCVII::MO_PCREL_HI
@ MO_PCREL_HI
Definition: RISCVBaseInfo.h:199
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::RISCVMCExpr::create
static const RISCVMCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
Definition: RISCVMCExpr.cpp:31
llvm::RISCVII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: RISCVBaseInfo.h:201
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::AsmPrinter::GetCPISymbol
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
Definition: AsmPrinter.cpp:3342
llvm::RISCVMCExpr::VK_RISCV_PCREL_HI
@ VK_RISCV_PCREL_HI
Definition: RISCVMCExpr.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::RISCVII::MO_None
@ MO_None
Definition: RISCVBaseInfo.h:193
llvm::AsmPrinter::GetBlockAddressSymbol
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
Definition: AsmPrinter.cpp:3332
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:588
llvm::AsmPrinter::getSymbolPreferLocal
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
Definition: AsmPrinter.cpp:658
llvm::lowerRISCVMachineOperandToMCOperand
bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP)
Definition: RISCVMCInstLower.cpp:90
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
llvm::RISCVMCExpr::VK_RISCV_PCREL_LO
@ VK_RISCV_PCREL_LO
Definition: RISCVMCExpr.h:29
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCVII::MO_PCREL_LO
@ MO_PCREL_LO
Definition: RISCVBaseInfo.h:198
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::RISCVMCExpr::VK_RISCV_GOT_HI
@ VK_RISCV_GOT_HI
Definition: RISCVMCExpr.h:31
llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:91
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
RISCV.h
llvm::RISCVII::hasMergeOp
static bool hasMergeOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:147
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:59
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:525
llvm::RISCVII::MO_TPREL_HI
@ MO_TPREL_HI
Definition: RISCVBaseInfo.h:202
llvm::AsmPrinter::GetExternalSymbolSymbol
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
Definition: AsmPrinter.cpp:3389
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
MCAsmInfo.h
llvm::AsmPrinter::GetJTISymbol
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
Definition: AsmPrinter.cpp:3370
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
lowerSymbolOperand
static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP)
Definition: RISCVMCInstLower.cpp:29
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:194
llvm::RISCVII::MO_LO
@ MO_LO
Definition: RISCVBaseInfo.h:196
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVII::MO_HI
@ MO_HI
Definition: RISCVBaseInfo.h:197
llvm::AsmPrinter::emitNops
void emitNops(unsigned N)
Emit N NOP instructions.
Definition: AsmPrinter.cpp:3318
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:81
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
lowerRISCVVMachineInstrToMCInst
static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI)
Definition: RISCVMCInstLower.cpp:132
RISCVSubtarget.h
llvm::RISCVMCExpr::VK_RISCV_CALL
@ VK_RISCV_CALL
Definition: RISCVMCExpr.h:37
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:617
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::RISCVII::hasDummyMaskOp
static bool hasDummyMaskOp(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:139
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:63
llvm::RISCVMCExpr::VK_RISCV_CALL_PLT
@ VK_RISCV_CALL_PLT
Definition: RISCVMCExpr.h:38
raw_ostream.h
llvm::RISCVII::MO_TPREL_ADD
@ MO_TPREL_ADD
Definition: RISCVBaseInfo.h:203
MCExpr.h
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::RISCVII::MO_TLS_GOT_HI
@ MO_TLS_GOT_HI
Definition: RISCVBaseInfo.h:204
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:57