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135 RISCVVPseudosTable::getPseudoInfo(
MI->getOpcode());
142 assert(
MBB &&
"MI expected to be in a basic block");
144 assert(MF &&
"MBB expected to be in a machine function");
149 assert(
TRI &&
"TargetRegisterInfo expected");
152 unsigned NumOps =
MI->getNumExplicitOperands();
163 for (
unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
166 if (hasVLOutput && OpNo == 1)
171 assert(
MI->getNumExplicitDefs() == 1U + hasVLOutput);
186 assert(
Reg &&
"Subregister does not exist");
189 assert(
Reg &&
"Subregister does not exist");
192 assert(
Reg &&
"Superregister does not exist");
227 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
228 const Function &
F =
MI->getParent()->getParent()->getFunction();
229 if (
F.hasFnAttribute(
"patchable-function-entry")) {
231 if (
F.getFnAttribute(
"patchable-function-entry")
233 .getAsInteger(10, Num))
240 case RISCV::PseudoReadVLENB:
246 case RISCV::PseudoReadVL:
@ MO_BlockAddress
Address of a basic block.
@ MO_Immediate
Immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MCOperand createExpr(const MCExpr *Val)
const GlobalValue * getGlobal() const
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
const SysReg * lookupSysRegByName(StringRef)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
return AArch64::GPR64RegClass contains(Reg)
const BlockAddress * getBlockAddress() const
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool hasSEWOp(uint64_t TSFlags)
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Instances of this class represent a single low-level machine instruction.
static bool hasVecPolicyOp(uint64_t TSFlags)
int64_t getOffset() const
Return the offset from the symbol in this operand.
unsigned const TargetRegisterInfo * TRI
@ MO_Register
Register operand.
bool isFaultFirstLoad(const MachineInstr &MI)
void setOpcode(unsigned Op)
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
@ MO_GlobalAddress
Address of a global value.
bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineOperand class - Representation of each machine instruction operand.
static bool hasVLOp(uint64_t TSFlags)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void addOperand(const MCOperand Op)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static const RISCVMCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
unsigned getTargetFlags() const
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
Representation of each machine instruction.
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP)
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MCContext & OutContext
This is the context for the output file that we are streaming.
Register getReg() const
getReg - Returns the register number.
static bool hasMergeOp(uint64_t TSFlags)
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
MachineBasicBlock * getMBB() const
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCOperand createReg(unsigned Reg)
@ MO_MachineBasicBlock
MachineBasicBlock reference.
static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP)
Wrapper class representing virtual and physical registers.
void emitNops(unsigned N)
Emit N NOP instructions.
@ MO_ExternalSymbol
Name of external global symbol.
unsigned getOpcode() const
This class is intended to be used as a driving class for all asm writers.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI)
const char * getSymbolName() const
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Instances of this class represent operands of the MCInst class.
static bool hasDummyMaskOp(uint64_t TSFlags)
@ MO_RegisterMask
Mask of preserved registers.
Base class for the full range of assembler expressions which are needed for parsing.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.