LLVM  15.0.0git
RISCVMacroFusion.cpp
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1 //===- RISCVMacroFusion.cpp - RISCV Macro Fusion --------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file contains the RISCV implementation of the DAG scheduling
10 /// mutation to pair instructions back to back.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 #include "RISCVMacroFusion.h"
15 #include "RISCVSubtarget.h"
18 
19 using namespace llvm;
20 
21 // Fuse LUI followed by ADDI or ADDIW.
22 // rd = imm[31:0] which decomposes to
23 // lui rd, imm[31:12]
24 // addi(w) rd, rd, imm[11:0]
25 static bool isLUIADDI(const MachineInstr *FirstMI,
26  const MachineInstr &SecondMI) {
27  if (SecondMI.getOpcode() != RISCV::ADDI &&
28  SecondMI.getOpcode() != RISCV::ADDIW)
29  return false;
30 
31  // Assume the 1st instr to be a wildcard if it is unspecified.
32  if (!FirstMI)
33  return true;
34 
35  if (FirstMI->getOpcode() != RISCV::LUI)
36  return false;
37 
38  // The first operand of ADDI might be a frame index.
39  if (!SecondMI.getOperand(1).isReg())
40  return false;
41 
42  Register FirstDest = FirstMI->getOperand(0).getReg();
43 
44  // Destination of LUI should be the ADDI(W) source register.
45  if (SecondMI.getOperand(1).getReg() != FirstDest)
46  return false;
47 
48  // If the FirstMI destination is non-virtual, it should match the SecondMI
49  // destination.
50  return FirstDest.isVirtual() || SecondMI.getOperand(0).getReg() == FirstDest;
51 }
52 
54  const TargetSubtargetInfo &TSI,
55  const MachineInstr *FirstMI,
56  const MachineInstr &SecondMI) {
57  const RISCVSubtarget &ST = static_cast<const RISCVSubtarget &>(TSI);
58 
59  if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI))
60  return true;
61 
62  return false;
63 }
64 
65 std::unique_ptr<ScheduleDAGMutation> llvm::createRISCVMacroFusionDAGMutation() {
67 }
RISCVMacroFusion.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
TargetInstrInfo.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::createMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent)
Create a DAG scheduling mutation to pair instructions back to back for instructions that benefit acco...
Definition: MacroFusion.cpp:200
llvm::shouldScheduleAdjacent
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.
Definition: ARMMacroFusion.cpp:51
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
MacroFusion.h
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::createRISCVMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
Definition: RISCVMacroFusion.cpp:65
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
isLUIADDI
static bool isLUIADDI(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Definition: RISCVMacroFusion.cpp:25
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
RISCVSubtarget.h