LLVM 18.0.0git
RISCVMacroFusion.cpp
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1//===- RISCVMacroFusion.cpp - RISC-V Macro Fusion -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file contains the RISC-V implementation of the DAG scheduling
10/// mutation to pair instructions back to back.
11//
12//===----------------------------------------------------------------------===//
13//
14#include "RISCVMacroFusion.h"
15#include "RISCVSubtarget.h"
18
19using namespace llvm;
20
21// Fuse LUI followed by ADDI or ADDIW.
22// rd = imm[31:0] which decomposes to
23// lui rd, imm[31:12]
24// addi(w) rd, rd, imm[11:0]
25static bool isLUIADDI(const MachineInstr *FirstMI,
26 const MachineInstr &SecondMI) {
27 if (SecondMI.getOpcode() != RISCV::ADDI &&
28 SecondMI.getOpcode() != RISCV::ADDIW)
29 return false;
30
31 // Assume the 1st instr to be a wildcard if it is unspecified.
32 if (!FirstMI)
33 return true;
34
35 if (FirstMI->getOpcode() != RISCV::LUI)
36 return false;
37
38 // The first operand of ADDI might be a frame index.
39 if (!SecondMI.getOperand(1).isReg())
40 return false;
41
42 Register FirstDest = FirstMI->getOperand(0).getReg();
43
44 // Destination of LUI should be the ADDI(W) source register.
45 if (SecondMI.getOperand(1).getReg() != FirstDest)
46 return false;
47
48 // If the input is virtual make sure this is the only user.
49 if (FirstDest.isVirtual()) {
50 auto &MRI = SecondMI.getMF()->getRegInfo();
51 return MRI.hasOneNonDBGUse(FirstDest);
52 }
53
54 // If the FirstMI destination is non-virtual, it should match the SecondMI
55 // destination.
56 return SecondMI.getOperand(0).getReg() == FirstDest;
57}
58
60 const TargetSubtargetInfo &TSI,
61 const MachineInstr *FirstMI,
62 const MachineInstr &SecondMI) {
63 const RISCVSubtarget &ST = static_cast<const RISCVSubtarget &>(TSI);
64
65 if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI))
66 return true;
67
68 return false;
69}
70
71std::unique_ptr<ScheduleDAGMutation> llvm::createRISCVMacroFusionDAGMutation() {
73}
unsigned const MachineRegisterInfo * MRI
const HexagonInstrInfo * TII
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
static bool isLUIADDI(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
TargetInstrInfo - Interface to description of machine instruction set.
TargetSubtargetInfo - Generic base class for all target subtargets.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent)
Create a DAG scheduling mutation to pair instructions back to back for instructions that benefit acco...