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27 if (SecondMI.
getOpcode() != RISCV::ADDI &&
59 if (
ST.hasLUIADDIFusion() &&
isLUIADDI(FirstMI, SecondMI))
This is an optimization pass for GlobalISel generic memory operations.
TargetInstrInfo - Interface to description of machine instruction set.
const MachineOperand & getOperand(unsigned i) const
const HexagonInstrInfo * TII
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent)
Create a DAG scheduling mutation to pair instructions back to back for instructions that benefit acco...
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const TargetSubtargetInfo &TSI, const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Check if the instr pair, FirstMI and SecondMI, should be fused together.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
Register getReg() const
getReg - Returns the register number.
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
TargetSubtargetInfo - Generic base class for all target subtargets.
static bool isLUIADDI(const MachineInstr *FirstMI, const MachineInstr &SecondMI)
Wrapper class representing virtual and physical registers.