LLVM  15.0.0git
SIMCCodeEmitter.cpp
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1 //===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The SI code emitter produces machine code that can be executed
11 /// directly on the GPU device.
12 //
13 //===----------------------------------------------------------------------===//
14 
18 #include "SIDefines.h"
19 #include "Utils/AMDGPUBaseInfo.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/Support/Casting.h"
27 
28 using namespace llvm;
29 
30 namespace {
31 
32 class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
33  const MCRegisterInfo &MRI;
34 
35  /// Encode an fp or int literal
36  uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
37  const MCSubtargetInfo &STI) const;
38 
39 public:
40  SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
41  : AMDGPUMCCodeEmitter(mcii), MRI(*ctx.getRegisterInfo()) {}
42  SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
43  SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
44 
45  /// Encode the instruction and write it to the OS.
46  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
48  const MCSubtargetInfo &STI) const override;
49 
50  /// \returns the encoding for an MCOperand.
51  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
53  const MCSubtargetInfo &STI) const override;
54 
55  /// Use a fixup to encode the simm16 field for SOPP branch
56  /// instructions.
57  unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
59  const MCSubtargetInfo &STI) const override;
60 
61  unsigned getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
63  const MCSubtargetInfo &STI) const override;
64 
65  unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
67  const MCSubtargetInfo &STI) const override;
68 
69  unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
71  const MCSubtargetInfo &STI) const override;
72 
73  unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
75  const MCSubtargetInfo &STI) const override;
76 
77 private:
78  uint64_t getImplicitOpSelHiEncoding(int Opcode) const;
79 };
80 
81 } // end anonymous namespace
82 
84  MCContext &Ctx) {
85  return new SIMCCodeEmitter(MCII, Ctx);
86 }
87 
88 // Returns the encoding value to use if the given integer is an integer inline
89 // immediate value, or 0 if it is not.
90 template <typename IntTy>
91 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
92  if (Imm >= 0 && Imm <= 64)
93  return 128 + Imm;
94 
95  if (Imm >= -16 && Imm <= -1)
96  return 192 + std::abs(Imm);
97 
98  return 0;
99 }
100 
102  uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
103  return IntImm == 0 ? 255 : IntImm;
104 }
105 
107  uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
108  if (IntImm != 0)
109  return IntImm;
110 
111  if (Val == 0x3800) // 0.5
112  return 240;
113 
114  if (Val == 0xB800) // -0.5
115  return 241;
116 
117  if (Val == 0x3C00) // 1.0
118  return 242;
119 
120  if (Val == 0xBC00) // -1.0
121  return 243;
122 
123  if (Val == 0x4000) // 2.0
124  return 244;
125 
126  if (Val == 0xC000) // -2.0
127  return 245;
128 
129  if (Val == 0x4400) // 4.0
130  return 246;
131 
132  if (Val == 0xC400) // -4.0
133  return 247;
134 
135  if (Val == 0x3118 && // 1.0 / (2.0 * pi)
136  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
137  return 248;
138 
139  return 255;
140 }
141 
143  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
144  if (IntImm != 0)
145  return IntImm;
146 
147  if (Val == FloatToBits(0.5f))
148  return 240;
149 
150  if (Val == FloatToBits(-0.5f))
151  return 241;
152 
153  if (Val == FloatToBits(1.0f))
154  return 242;
155 
156  if (Val == FloatToBits(-1.0f))
157  return 243;
158 
159  if (Val == FloatToBits(2.0f))
160  return 244;
161 
162  if (Val == FloatToBits(-2.0f))
163  return 245;
164 
165  if (Val == FloatToBits(4.0f))
166  return 246;
167 
168  if (Val == FloatToBits(-4.0f))
169  return 247;
170 
171  if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
172  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
173  return 248;
174 
175  return 255;
176 }
177 
179  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
180  if (IntImm != 0)
181  return IntImm;
182 
183  if (Val == DoubleToBits(0.5))
184  return 240;
185 
186  if (Val == DoubleToBits(-0.5))
187  return 241;
188 
189  if (Val == DoubleToBits(1.0))
190  return 242;
191 
192  if (Val == DoubleToBits(-1.0))
193  return 243;
194 
195  if (Val == DoubleToBits(2.0))
196  return 244;
197 
198  if (Val == DoubleToBits(-2.0))
199  return 245;
200 
201  if (Val == DoubleToBits(4.0))
202  return 246;
203 
204  if (Val == DoubleToBits(-4.0))
205  return 247;
206 
207  if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
208  STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
209  return 248;
210 
211  return 255;
212 }
213 
214 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
215  const MCOperandInfo &OpInfo,
216  const MCSubtargetInfo &STI) const {
217  int64_t Imm;
218  if (MO.isExpr()) {
219  const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
220  if (!C)
221  return 255;
222 
223  Imm = C->getValue();
224  } else {
225 
226  assert(!MO.isDFPImm());
227 
228  if (!MO.isImm())
229  return ~0;
230 
231  Imm = MO.getImm();
232  }
233 
234  switch (OpInfo.OperandType) {
246  return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
247 
253  return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
254 
258  return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
263  // FIXME Is this correct? What do inline immediates do on SI for f16 src
264  // which does not have f16 support?
265  return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
268  if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])
269  return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
271  return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
273  }
276  return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
279  uint16_t Lo16 = static_cast<uint16_t>(Imm);
280  uint32_t Encoding = getLit16Encoding(Lo16, STI);
281  return Encoding;
282  }
285  return MO.getImm();
286  default:
287  llvm_unreachable("invalid operand size");
288  }
289 }
290 
291 uint64_t SIMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
292  using namespace AMDGPU::VOP3PEncoding;
293  using namespace AMDGPU::OpName;
294 
295  if (AMDGPU::getNamedOperandIdx(Opcode, op_sel_hi) != -1) {
296  if (AMDGPU::getNamedOperandIdx(Opcode, src2) != -1)
297  return 0;
298  if (AMDGPU::getNamedOperandIdx(Opcode, src1) != -1)
299  return OP_SEL_HI_2;
300  if (AMDGPU::getNamedOperandIdx(Opcode, src0) != -1)
301  return OP_SEL_HI_1 | OP_SEL_HI_2;
302  }
304 }
305 
306 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
308  const MCSubtargetInfo &STI) const {
309  verifyInstructionPredicates(MI,
310  computeAvailableFeatures(STI.getFeatureBits()));
311 
312  int Opcode = MI.getOpcode();
313  uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
314  const MCInstrDesc &Desc = MCII.get(Opcode);
315  unsigned bytes = Desc.getSize();
316 
317  // Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions.
318  // Note that accvgpr_read/write are MAI, have src0, but do not use op_sel.
319  if ((Desc.TSFlags & SIInstrFlags::VOP3P) ||
320  Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
321  Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {
322  Encoding |= getImplicitOpSelHiEncoding(Opcode);
323  }
324 
325  for (unsigned i = 0; i < bytes; i++) {
326  OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
327  }
328 
329  // NSA encoding.
330  if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
331  int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
332  AMDGPU::OpName::vaddr0);
333  int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
334  AMDGPU::OpName::srsrc);
335  assert(vaddr0 >= 0 && srsrc > vaddr0);
336  unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
337  unsigned NumPadding = (-NumExtraAddrs) & 3;
338 
339  for (unsigned i = 0; i < NumExtraAddrs; ++i)
340  OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i),
341  Fixups, STI));
342  for (unsigned i = 0; i < NumPadding; ++i)
343  OS.write(0);
344  }
345 
346  if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) ||
347  (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]))
348  return;
349 
350  // Do not print literals from SISrc Operands for insts with mandatory literals
351  int ImmLitIdx =
352  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
353  if (ImmLitIdx != -1)
354  return;
355 
356  // Check for additional literals
357  for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
358 
359  // Check if this operand should be encoded as [SV]Src
360  if (!AMDGPU::isSISrcOperand(Desc, i))
361  continue;
362 
363  // Is this operand a literal immediate?
364  const MCOperand &Op = MI.getOperand(i);
365  if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
366  continue;
367 
368  // Yes! Encode it
369  int64_t Imm = 0;
370 
371  if (Op.isImm())
372  Imm = Op.getImm();
373  else if (Op.isExpr()) {
374  if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
375  Imm = C->getValue();
376 
377  } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
378  llvm_unreachable("Must be immediate or expr");
379 
380  for (unsigned j = 0; j < 4; j++) {
381  OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
382  }
383 
384  // Only one literal value allowed
385  break;
386  }
387 }
388 
389 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
391  const MCSubtargetInfo &STI) const {
392  const MCOperand &MO = MI.getOperand(OpNo);
393 
394  if (MO.isExpr()) {
395  const MCExpr *Expr = MO.getExpr();
397  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
398  return 0;
399  }
400 
401  return getMachineOpValue(MI, MO, Fixups, STI);
402 }
403 
404 unsigned SIMCCodeEmitter::getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
406  const MCSubtargetInfo &STI) const {
407  auto Offset = MI.getOperand(OpNo).getImm();
408  // VI only supports 20-bit unsigned offsets.
409  assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));
410  return Offset;
411 }
412 
413 unsigned
414 SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
416  const MCSubtargetInfo &STI) const {
417  using namespace AMDGPU::SDWA;
418 
419  uint64_t RegEnc = 0;
420 
421  const MCOperand &MO = MI.getOperand(OpNo);
422 
423  if (MO.isReg()) {
424  unsigned Reg = MO.getReg();
425  RegEnc |= MRI.getEncodingValue(Reg);
429  }
430  return RegEnc;
431  } else {
432  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
433  uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
434  if (Enc != ~0U && Enc != 255) {
435  return Enc | SDWA9EncValues::SRC_SGPR_MASK;
436  }
437  }
438 
439  llvm_unreachable("Unsupported operand kind");
440  return 0;
441 }
442 
443 unsigned
444 SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
446  const MCSubtargetInfo &STI) const {
447  using namespace AMDGPU::SDWA;
448 
449  uint64_t RegEnc = 0;
450 
451  const MCOperand &MO = MI.getOperand(OpNo);
452 
453  unsigned Reg = MO.getReg();
454  if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
455  RegEnc |= MRI.getEncodingValue(Reg);
458  }
459  return RegEnc;
460 }
461 
462 unsigned
463 SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
465  const MCSubtargetInfo &STI) const {
466  unsigned Reg = MI.getOperand(OpNo).getReg();
467  uint64_t Enc = MRI.getEncodingValue(Reg);
468 
469  // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
470  // instructions use acc[0:1] modifier bits to distinguish. These bits are
471  // encoded as a virtual 9th bit of the register for these operands.
472  if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
473  MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
474  MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
475  MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
476  MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
477  MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
478  MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||
479  MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
480  MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||
481  MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
482  Enc |= 512;
483 
484  return Enc;
485 }
486 
487 static bool needsPCRel(const MCExpr *Expr) {
488  switch (Expr->getKind()) {
489  case MCExpr::SymbolRef: {
490  auto *SE = cast<MCSymbolRefExpr>(Expr);
491  MCSymbolRefExpr::VariantKind Kind = SE->getKind();
494  }
495  case MCExpr::Binary: {
496  auto *BE = cast<MCBinaryExpr>(Expr);
497  if (BE->getOpcode() == MCBinaryExpr::Sub)
498  return false;
499  return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
500  }
501  case MCExpr::Unary:
502  return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
503  case MCExpr::Target:
504  case MCExpr::Constant:
505  return false;
506  }
507  llvm_unreachable("invalid kind");
508 }
509 
510 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
511  const MCOperand &MO,
513  const MCSubtargetInfo &STI) const {
514  if (MO.isReg())
515  return MRI.getEncodingValue(MO.getReg());
516 
517  if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
518  // FIXME: If this is expression is PCRel or not should not depend on what
519  // the expression looks like. Given that this is just a general expression,
520  // it should probably be FK_Data_4 and whatever is producing
521  //
522  // s_add_u32 s2, s2, (extern_const_addrspace+16
523  //
524  // And expecting a PCRel should instead produce
525  //
526  // .Ltmp1:
527  // s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
529  if (needsPCRel(MO.getExpr()))
530  Kind = FK_PCRel_4;
531  else
532  Kind = FK_Data_4;
533 
534  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
535  uint32_t Offset = Desc.getSize();
536  assert(Offset == 4 || Offset == 8);
537 
538  Fixups.push_back(
539  MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
540  }
541 
542  // Figure out the operand number, needed for isSrcOperand check
543  unsigned OpNo = 0;
544  for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
545  if (&MO == &MI.getOperand(OpNo))
546  break;
547  }
548 
549  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
550  if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
551  uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
552  if (Enc != ~0U)
553  return Enc;
554 
555  } else if (MO.isImm())
556  return MO.getImm();
557 
558  llvm_unreachable("Encoding of this operand type is not supported yet.");
559  return 0;
560 }
561 
562 #define ENABLE_INSTR_PREDICATE_VERIFIER
563 #include "AMDGPUGenMCCodeEmitter.inc"
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:164
i
i
Definition: README.txt:29
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1827
llvm::createSIMCCodeEmitter
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: SIMCCodeEmitter.cpp:83
needsPCRel
static bool needsPCRel(const MCExpr *Expr)
Definition: SIMCCodeEmitter.cpp:487
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
AMDGPUFixupKinds.h
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_0
@ OP_SEL_HI_0
Definition: SIDefines.h:876
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:159
getLit64Encoding
static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:178
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::AMDGPU::fixup_si_sopp_br
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
Definition: AMDGPUFixupKinds.h:18
llvm::AMDGPU::OPERAND_KIMM16
@ OPERAND_KIMM16
Definition: SIDefines.h:172
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:153
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPU::OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:155
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:690
getLit32Encoding
static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:142
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:775
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:148
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:622
SubtargetFeature.h
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:160
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition: MCExpr.h:42
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:177
MCContext.h
AMDGPUMCCodeEmitter.h
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1753
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:680
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:149
llvm::raw_ostream::write
raw_ostream & write(unsigned char C)
Definition: raw_ostream.cpp:219
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:156
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:167
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1690
llvm::MCExpr::Binary
@ Binary
Binary expressions.
Definition: MCExpr.h:38
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
getLit16IntEncoding
static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:101
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_2
@ OP_SEL_HI_2
Definition: SIDefines.h:878
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1662
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:151
llvm::AMDGPU::SDWA::SRC_VGPR_MASK
@ SRC_VGPR_MASK
Definition: SIDefines.h:773
llvm::MCSymbolRefExpr::VK_AMDGPU_ABS32_HI
@ VK_AMDGPU_ABS32_HI
Definition: MCExpr.h:340
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:57
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
AMDGPUMCTargetDesc.h
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:406
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:161
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
uint64_t
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:163
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
getIntInlineImmEncoding
static uint32_t getIntInlineImmEncoding(IntTy Imm)
Definition: SIMCCodeEmitter.cpp:91
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:175
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::AMDGPU::VOP3PEncoding::OP_SEL_HI_1
@ OP_SEL_HI_1
Definition: SIDefines.h:877
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:165
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:152
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:178
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:46
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:147
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:176
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1836
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::AMDGPUMCCodeEmitter
Definition: AMDGPUMCCodeEmitter.h:28
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:179
j
return j(j<< 16)
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::AMDGPU::SDWA::SRC_SGPR_MASK
@ SRC_SGPR_MASK
Definition: SIDefines.h:772
llvm::AMDGPU::OPERAND_KIMM32
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:171
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:154
uint16_t
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7835
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:338
SIDefines.h
llvm::MCBinaryExpr::Sub
@ Sub
Subtraction.
Definition: MCExpr.h:506
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:166
Casting.h
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:168
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:774
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::MCExpr::Unary
@ Unary
Unary expressions.
Definition: MCExpr.h:41
llvm::MCExpr::Constant
@ Constant
Constant expressions.
Definition: MCExpr.h:39
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:145
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:162
getLit16Encoding
static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI)
Definition: SIMCCodeEmitter.cpp:106
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:150
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:180
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1281
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition: MCInst.h:64
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:146
llvm::MCSymbolRefExpr::VK_AMDGPU_ABS32_LO
@ VK_AMDGPU_ABS32_LO
Definition: MCExpr.h:339
llvm::AMDGPU::Fixups
Fixups
Definition: AMDGPUFixupKinds.h:16
AMDGPUBaseInfo.h
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:181