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45 return EvexOpcode <
RHS.EvexOpcode;
50 return TE.EvexOpcode < Opc;
53 #include "X86GenEVEX2VEXTables.inc"
55 #define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible"
56 #define EVEX2VEX_NAME "x86-evex-to-vex-compress"
58 #define DEBUG_TYPE EVEX2VEX_NAME
100 if (!
ST->hasAVX512())
103 bool Changed =
false;
111 Changed |= CompressEvexToVexImpl(
MI);
118 auto isHiRegIdx = [](
unsigned Reg) {
120 if (
Reg >= X86::XMM16 &&
Reg <= X86::XMM31)
124 if (
Reg >= X86::YMM16 &&
Reg <= X86::YMM31)
139 "ZMM instructions should not be in the EVEX->VEX tables");
152 unsigned Opc =
MI.getOpcode();
154 case X86::VALIGNDZ128rri:
155 case X86::VALIGNDZ128rmi:
156 case X86::VALIGNQZ128rri:
157 case X86::VALIGNQZ128rmi: {
158 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
159 "Unexpected new opcode!");
160 unsigned Scale = (Opc == X86::VALIGNQZ128rri ||
161 Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
163 Imm.setImm(
Imm.getImm() * Scale);
166 case X86::VSHUFF32X4Z256rmi:
167 case X86::VSHUFF32X4Z256rri:
168 case X86::VSHUFF64X2Z256rmi:
169 case X86::VSHUFF64X2Z256rri:
170 case X86::VSHUFI32X4Z256rmi:
171 case X86::VSHUFI32X4Z256rri:
172 case X86::VSHUFI64X2Z256rmi:
173 case X86::VSHUFI64X2Z256rri: {
174 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
175 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
176 "Unexpected new opcode!");
178 int64_t ImmVal =
Imm.getImm();
180 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
183 case X86::VRNDSCALEPDZ128rri:
184 case X86::VRNDSCALEPDZ128rmi:
185 case X86::VRNDSCALEPSZ128rri:
186 case X86::VRNDSCALEPSZ128rmi:
187 case X86::VRNDSCALEPDZ256rri:
188 case X86::VRNDSCALEPDZ256rmi:
189 case X86::VRNDSCALEPSZ256rri:
190 case X86::VRNDSCALEPSZ256rmi:
191 case X86::VRNDSCALESDZr:
192 case X86::VRNDSCALESDZm:
193 case X86::VRNDSCALESSZr:
194 case X86::VRNDSCALESSZm:
195 case X86::VRNDSCALESDZr_Int:
196 case X86::VRNDSCALESDZm_Int:
197 case X86::VRNDSCALESSZr_Int:
198 case X86::VRNDSCALESSZm_Int:
200 int64_t ImmVal =
Imm.getImm();
202 if ((ImmVal & 0xf) != ImmVal)
213 bool EvexToVexInstPass::CompressEvexToVexImpl(
MachineInstr &
MI)
const {
241 static std::atomic<bool> TableChecked(
false);
242 if (!TableChecked.load(std::memory_order_relaxed)) {
244 "X86EvexToVex128CompressTable is not sorted!");
246 "X86EvexToVex256CompressTable is not sorted!");
247 TableChecked.store(
true, std::memory_order_relaxed);
257 if (
I == Table.
end() ||
I->EvexOpcode !=
MI.getOpcode())
260 unsigned NewOpc =
I->VexOpcode;
265 if (!CheckVEXInstPredicate(
MI,
ST))
271 MI.setDesc(
TII->get(NewOpc));
279 return new EvexToVexInstPass();
This is an optimization pass for GlobalISel generic memory operations.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
friend bool operator<(const X86EvexToVexCompressTableEntry &TE, unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Properties which a MachineFunction may have at a given point in time.
bool operator<(const X86EvexToVexCompressTableEntry &RHS) const
static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, const X86Subtarget *ST)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool usesExtendedRegister(const MachineInstr &MI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
Wrapper class representing virtual and physical registers.
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
FunctionPass class - This class is used to implement most global optimizations.