51 return TE.EvexOpcode < Opc;
54#include "X86GenEVEX2VEXTables.inc"
56#define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible"
57#define EVEX2VEX_NAME "x86-evex-to-vex-compress"
59#define DEBUG_TYPE EVEX2VEX_NAME
83 MachineFunctionProperties::Property::NoVRegs);
95char EvexToVexInstPass::ID = 0;
101 if (!
ST->hasAVX512())
104 bool Changed =
false;
112 Changed |= CompressEvexToVexImpl(
MI);
119 auto isHiRegIdx = [](
unsigned Reg) {
121 if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
125 if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
139 assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) &&
140 "ZMM instructions should not be in the EVEX->VEX tables");
153 unsigned Opc =
MI.getOpcode();
155 case X86::VALIGNDZ128rri:
156 case X86::VALIGNDZ128rmi:
157 case X86::VALIGNQZ128rri:
158 case X86::VALIGNQZ128rmi: {
159 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
160 "Unexpected new opcode!");
161 unsigned Scale = (Opc == X86::VALIGNQZ128rri ||
162 Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
164 Imm.setImm(Imm.getImm() * Scale);
167 case X86::VSHUFF32X4Z256rmi:
168 case X86::VSHUFF32X4Z256rri:
169 case X86::VSHUFF64X2Z256rmi:
170 case X86::VSHUFF64X2Z256rri:
171 case X86::VSHUFI32X4Z256rmi:
172 case X86::VSHUFI32X4Z256rri:
173 case X86::VSHUFI64X2Z256rmi:
174 case X86::VSHUFI64X2Z256rri: {
175 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
176 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
177 "Unexpected new opcode!");
179 int64_t ImmVal = Imm.getImm();
181 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
184 case X86::VRNDSCALEPDZ128rri:
185 case X86::VRNDSCALEPDZ128rmi:
186 case X86::VRNDSCALEPSZ128rri:
187 case X86::VRNDSCALEPSZ128rmi:
188 case X86::VRNDSCALEPDZ256rri:
189 case X86::VRNDSCALEPDZ256rmi:
190 case X86::VRNDSCALEPSZ256rri:
191 case X86::VRNDSCALEPSZ256rmi:
192 case X86::VRNDSCALESDZr:
193 case X86::VRNDSCALESDZm:
194 case X86::VRNDSCALESSZr:
195 case X86::VRNDSCALESSZm:
196 case X86::VRNDSCALESDZr_Int:
197 case X86::VRNDSCALESDZm_Int:
198 case X86::VRNDSCALESSZr_Int:
199 case X86::VRNDSCALESSZm_Int:
201 int64_t ImmVal = Imm.getImm();
203 if ((ImmVal & 0xf) != ImmVal)
214bool EvexToVexInstPass::CompressEvexToVexImpl(
MachineInstr &
MI)
const {
242 static std::atomic<bool> TableChecked(
false);
243 if (!TableChecked.load(std::memory_order_relaxed)) {
245 "X86EvexToVex128CompressTable is not sorted!");
247 "X86EvexToVex256CompressTable is not sorted!");
248 TableChecked.store(
true, std::memory_order_relaxed);
255 :
ArrayRef(X86EvexToVex128CompressTable);
258 if (
I == Table.
end() ||
I->EvexOpcode !=
MI.getOpcode())
261 unsigned NewOpc =
I->VexOpcode;
266 if (!CheckVEXInstPredicate(
MI, ST))
272 MI.setDesc(
TII->get(NewOpc));
280 return new EvexToVexInstPass();
const HexagonInstrInfo * TII
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, const X86Subtarget *ST)
static bool usesExtendedRegister(const MachineInstr &MI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
friend bool operator<(const X86EvexToVexCompressTableEntry &TE, unsigned Opc)
bool operator<(const X86EvexToVexCompressTableEntry &RHS) const
Description of the encoding of one expression Op.