LLVM  14.0.0git
X86EvexToVex.cpp
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1 //===- X86EvexToVex.cpp ---------------------------------------------------===//
2 // Compress EVEX instructions to VEX encoding when possible to reduce code size
3 //
4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // See https://llvm.org/LICENSE.txt for license information.
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file defines the pass that goes over all AVX-512 instructions which
12 /// are encoded using the EVEX prefix and if possible replaces them by their
13 /// corresponding VEX encoding which is usually shorter by 2 bytes.
14 /// EVEX instructions may be encoded via the VEX prefix when the AVX-512
15 /// instruction has a corresponding AVX/AVX2 opcode, when vector length
16 /// accessed by instruction is less than 512 bits and when it does not use
17 // the xmm or the mask registers or xmm/ymm registers with indexes higher than 15.
18 /// The pass applies code reduction on the generated code for AVX-512 instrs.
19 //
20 //===----------------------------------------------------------------------===//
21 
24 #include "X86.h"
25 #include "X86InstrInfo.h"
26 #include "X86Subtarget.h"
27 #include "llvm/ADT/StringRef.h"
32 #include "llvm/MC/MCInstrDesc.h"
33 #include "llvm/Pass.h"
34 #include <cassert>
35 #include <cstdint>
36 
37 using namespace llvm;
38 
39 // Including the generated EVEX2VEX tables.
43 
44  bool operator<(const X86EvexToVexCompressTableEntry &RHS) const {
45  return EvexOpcode < RHS.EvexOpcode;
46  }
47 
49  unsigned Opc) {
50  return TE.EvexOpcode < Opc;
51  }
52 };
53 #include "X86GenEVEX2VEXTables.inc"
54 
55 #define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible"
56 #define EVEX2VEX_NAME "x86-evex-to-vex-compress"
57 
58 #define DEBUG_TYPE EVEX2VEX_NAME
59 
60 namespace {
61 
62 class EvexToVexInstPass : public MachineFunctionPass {
63 
64  /// For EVEX instructions that can be encoded using VEX encoding, replace
65  /// them by the VEX encoding in order to reduce size.
66  bool CompressEvexToVexImpl(MachineInstr &MI) const;
67 
68 public:
69  static char ID;
70 
71  EvexToVexInstPass() : MachineFunctionPass(ID) { }
72 
73  StringRef getPassName() const override { return EVEX2VEX_DESC; }
74 
75  /// Loop over all of the basic blocks, replacing EVEX instructions
76  /// by equivalent VEX instructions when possible for reducing code size.
77  bool runOnMachineFunction(MachineFunction &MF) override;
78 
79  // This pass runs after regalloc and doesn't support VReg operands.
80  MachineFunctionProperties getRequiredProperties() const override {
83  }
84 
85 private:
86  /// Machine instruction info used throughout the class.
87  const X86InstrInfo *TII = nullptr;
88 
89  const X86Subtarget *ST = nullptr;
90 };
91 
92 } // end anonymous namespace
93 
94 char EvexToVexInstPass::ID = 0;
95 
96 bool EvexToVexInstPass::runOnMachineFunction(MachineFunction &MF) {
97  TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
98 
99  ST = &MF.getSubtarget<X86Subtarget>();
100  if (!ST->hasAVX512())
101  return false;
102 
103  bool Changed = false;
104 
105  /// Go over all basic blocks in function and replace
106  /// EVEX encoded instrs by VEX encoding when possible.
107  for (MachineBasicBlock &MBB : MF) {
108 
109  // Traverse the basic block.
110  for (MachineInstr &MI : MBB)
111  Changed |= CompressEvexToVexImpl(MI);
112  }
113 
114  return Changed;
115 }
116 
117 static bool usesExtendedRegister(const MachineInstr &MI) {
118  auto isHiRegIdx = [](unsigned Reg) {
119  // Check for XMM register with indexes between 16 - 31.
120  if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
121  return true;
122 
123  // Check for YMM register with indexes between 16 - 31.
124  if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
125  return true;
126 
127  return false;
128  };
129 
130  // Check that operands are not ZMM regs or
131  // XMM/YMM regs with hi indexes between 16 - 31.
132  for (const MachineOperand &MO : MI.explicit_operands()) {
133  if (!MO.isReg())
134  continue;
135 
136  Register Reg = MO.getReg();
137 
138  assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) &&
139  "ZMM instructions should not be in the EVEX->VEX tables");
140 
141  if (isHiRegIdx(Reg))
142  return true;
143  }
144 
145  return false;
146 }
147 
148 // Do any custom cleanup needed to finalize the conversion.
149 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc,
150  const X86Subtarget *ST) {
151  (void)NewOpc;
152  unsigned Opc = MI.getOpcode();
153  switch (Opc) {
154  case X86::VALIGNDZ128rri:
155  case X86::VALIGNDZ128rmi:
156  case X86::VALIGNQZ128rri:
157  case X86::VALIGNQZ128rmi: {
158  assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
159  "Unexpected new opcode!");
160  unsigned Scale = (Opc == X86::VALIGNQZ128rri ||
161  Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
162  MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
163  Imm.setImm(Imm.getImm() * Scale);
164  break;
165  }
166  case X86::VSHUFF32X4Z256rmi:
167  case X86::VSHUFF32X4Z256rri:
168  case X86::VSHUFF64X2Z256rmi:
169  case X86::VSHUFF64X2Z256rri:
170  case X86::VSHUFI32X4Z256rmi:
171  case X86::VSHUFI32X4Z256rri:
172  case X86::VSHUFI64X2Z256rmi:
173  case X86::VSHUFI64X2Z256rri: {
174  assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
175  NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
176  "Unexpected new opcode!");
177  MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
178  int64_t ImmVal = Imm.getImm();
179  // Set bit 5, move bit 1 to bit 4, copy bit 0.
180  Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
181  break;
182  }
183  case X86::VRNDSCALEPDZ128rri:
184  case X86::VRNDSCALEPDZ128rmi:
185  case X86::VRNDSCALEPSZ128rri:
186  case X86::VRNDSCALEPSZ128rmi:
187  case X86::VRNDSCALEPDZ256rri:
188  case X86::VRNDSCALEPDZ256rmi:
189  case X86::VRNDSCALEPSZ256rri:
190  case X86::VRNDSCALEPSZ256rmi:
191  case X86::VRNDSCALESDZr:
192  case X86::VRNDSCALESDZm:
193  case X86::VRNDSCALESSZr:
194  case X86::VRNDSCALESSZm:
195  case X86::VRNDSCALESDZr_Int:
196  case X86::VRNDSCALESDZm_Int:
197  case X86::VRNDSCALESSZr_Int:
198  case X86::VRNDSCALESSZm_Int:
199  const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
200  int64_t ImmVal = Imm.getImm();
201  // Ensure that only bits 3:0 of the immediate are used.
202  if ((ImmVal & 0xf) != ImmVal)
203  return false;
204  break;
205  }
206 
207  return true;
208 }
209 
210 
211 // For EVEX instructions that can be encoded using VEX encoding
212 // replace them by the VEX encoding in order to reduce size.
213 bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
214  // VEX format.
215  // # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1
216  // [Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]
217  //
218  // EVEX format.
219  // # of bytes: 4 1 1 1 4 / 1 1
220  // [Prefixes] EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]
221 
222  const MCInstrDesc &Desc = MI.getDesc();
223 
224  // Check for EVEX instructions only.
225  if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX)
226  return false;
227 
228  // Check for EVEX instructions with mask or broadcast as in these cases
229  // the EVEX prefix is needed in order to carry this information
230  // thus preventing the transformation to VEX encoding.
231  if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B))
232  return false;
233 
234  // Check for EVEX instructions with L2 set. These instructions are 512-bits
235  // and can't be converted to VEX.
236  if (Desc.TSFlags & X86II::EVEX_L2)
237  return false;
238 
239 #ifndef NDEBUG
240  // Make sure the tables are sorted.
241  static std::atomic<bool> TableChecked(false);
242  if (!TableChecked.load(std::memory_order_relaxed)) {
243  assert(llvm::is_sorted(X86EvexToVex128CompressTable) &&
244  "X86EvexToVex128CompressTable is not sorted!");
245  assert(llvm::is_sorted(X86EvexToVex256CompressTable) &&
246  "X86EvexToVex256CompressTable is not sorted!");
247  TableChecked.store(true, std::memory_order_relaxed);
248  }
249 #endif
250 
251  // Use the VEX.L bit to select the 128 or 256-bit table.
253  (Desc.TSFlags & X86II::VEX_L) ? makeArrayRef(X86EvexToVex256CompressTable)
254  : makeArrayRef(X86EvexToVex128CompressTable);
255 
256  const auto *I = llvm::lower_bound(Table, MI.getOpcode());
257  if (I == Table.end() || I->EvexOpcode != MI.getOpcode())
258  return false;
259 
260  unsigned NewOpc = I->VexOpcode;
261 
263  return false;
264 
265  if (!CheckVEXInstPredicate(MI, ST))
266  return false;
267 
268  if (!performCustomAdjustments(MI, NewOpc, ST))
269  return false;
270 
271  MI.setDesc(TII->get(NewOpc));
272  MI.setAsmPrinterFlag(X86::AC_EVEX_2_VEX);
273  return true;
274 }
275 
276 INITIALIZE_PASS(EvexToVexInstPass, EVEX2VEX_NAME, EVEX2VEX_DESC, false, false)
277 
279  return new EvexToVexInstPass();
280 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
X86Subtarget.h
MCInstrDesc.h
X86EvexToVexCompressTableEntry::EvexOpcode
uint16_t EvexOpcode
Definition: X86EvexToVex.cpp:41
llvm::lower_bound
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1661
StringRef.h
Pass.h
llvm::X86II::EVEX_K
@ EVEX_K
Definition: X86BaseInfo.h:937
llvm::X86Subtarget
Definition: X86Subtarget.h:52
X86EvexToVexCompressTableEntry::operator<
friend bool operator<(const X86EvexToVexCompressTableEntry &TE, unsigned Opc)
Definition: X86EvexToVex.cpp:48
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
llvm::X86II::VEX_L
@ VEX_L
Definition: X86BaseInfo.h:933
EVEX2VEX_NAME
#define EVEX2VEX_NAME
Definition: X86EvexToVex.cpp:56
X86EvexToVexCompressTableEntry::operator<
bool operator<(const X86EvexToVexCompressTableEntry &RHS) const
Definition: X86EvexToVex.cpp:44
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
X86.h
llvm::X86::AC_EVEX_2_VEX
@ AC_EVEX_2_VEX
Definition: X86InstrInfo.h:33
performCustomAdjustments
static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc, const X86Subtarget *ST)
Definition: X86EvexToVex.cpp:149
llvm::X86II::EncodingMask
@ EncodingMask
Definition: X86BaseInfo.h:900
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int64_t getImm() const
Definition: MachineOperand.h:537
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:173
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
I
#define I(x, y, z)
Definition: MD5.cpp:59
MachineFunctionPass.h
X86EvexToVexCompressTableEntry::VexOpcode
uint16_t VexOpcode
Definition: X86EvexToVex.cpp:42
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86II::EVEX
@ EVEX
Definition: X86BaseInfo.h:912
usesExtendedRegister
static bool usesExtendedRegister(const MachineInstr &MI)
Definition: X86EvexToVex.cpp:117
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::X86II::EVEX_L2
@ EVEX_L2
Definition: X86BaseInfo.h:945
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::createX86EvexToVexInsts
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
Definition: X86EvexToVex.cpp:278
uint16_t
X86EvexToVexCompressTableEntry
Definition: X86EvexToVex.cpp:40
llvm::is_sorted
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
Definition: STLExtras.h:1622
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#define EVEX2VEX_DESC
Definition: X86EvexToVex.cpp:55
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:476
X86BaseInfo.h
MachineOperand.h
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
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iterator end() const
Definition: ArrayRef.h:154
X86InstComments.h
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unsigned ID
Definition: TargetTransformInfo.h:37
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@ EVEX_B
Definition: X86BaseInfo.h:949