LLVM  10.0.0svn
X86WinAllocaExpander.cpp
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1 //===----- X86WinAllocaExpander.cpp - Expand WinAlloca pseudo instruction -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a pass that expands WinAlloca pseudo-instructions.
10 //
11 // It performs a conservative analysis to determine whether each allocation
12 // falls within a region of the stack that is safe to use, or whether stack
13 // probes must be emitted.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "X86.h"
18 #include "X86InstrBuilder.h"
19 #include "X86InstrInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86Subtarget.h"
26 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Function.h"
30 
31 using namespace llvm;
32 
33 namespace {
34 
35 class X86WinAllocaExpander : public MachineFunctionPass {
36 public:
37  X86WinAllocaExpander() : MachineFunctionPass(ID) {}
38 
39  bool runOnMachineFunction(MachineFunction &MF) override;
40 
41 private:
42  /// Strategies for lowering a WinAlloca.
43  enum Lowering { TouchAndSub, Sub, Probe };
44 
45  /// Deterministic-order map from WinAlloca instruction to desired lowering.
46  typedef MapVector<MachineInstr*, Lowering> LoweringMap;
47 
48  /// Compute which lowering to use for each WinAlloca instruction.
49  void computeLowerings(MachineFunction &MF, LoweringMap& Lowerings);
50 
51  /// Get the appropriate lowering based on current offset and amount.
52  Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
53 
54  /// Lower a WinAlloca instruction.
55  void lower(MachineInstr* MI, Lowering L);
56 
58  const X86Subtarget *STI;
59  const TargetInstrInfo *TII;
60  const X86RegisterInfo *TRI;
61  unsigned StackPtr;
62  unsigned SlotSize;
63  int64_t StackProbeSize;
64  bool NoStackArgProbe;
65 
66  StringRef getPassName() const override { return "X86 WinAlloca Expander"; }
67  static char ID;
68 };
69 
71 
72 } // end anonymous namespace
73 
75  return new X86WinAllocaExpander();
76 }
77 
78 /// Return the allocation amount for a WinAlloca instruction, or -1 if unknown.
80  assert(MI->getOpcode() == X86::WIN_ALLOCA_32 ||
81  MI->getOpcode() == X86::WIN_ALLOCA_64);
82  assert(MI->getOperand(0).isReg());
83 
84  Register AmountReg = MI->getOperand(0).getReg();
85  MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg);
86 
87  if (!Def ||
88  (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) ||
89  !Def->getOperand(1).isImm())
90  return -1;
91 
92  return Def->getOperand(1).getImm();
93 }
94 
95 X86WinAllocaExpander::Lowering
96 X86WinAllocaExpander::getLowering(int64_t CurrentOffset,
97  int64_t AllocaAmount) {
98  // For a non-constant amount or a large amount, we have to probe.
99  if (AllocaAmount < 0 || AllocaAmount > StackProbeSize)
100  return Probe;
101 
102  // If it fits within the safe region of the stack, just subtract.
103  if (CurrentOffset + AllocaAmount <= StackProbeSize)
104  return Sub;
105 
106  // Otherwise, touch the current tip of the stack, then subtract.
107  return TouchAndSub;
108 }
109 
110 static bool isPushPop(const MachineInstr &MI) {
111  switch (MI.getOpcode()) {
112  case X86::PUSH32i8:
113  case X86::PUSH32r:
114  case X86::PUSH32rmm:
115  case X86::PUSH32rmr:
116  case X86::PUSHi32:
117  case X86::PUSH64i8:
118  case X86::PUSH64r:
119  case X86::PUSH64rmm:
120  case X86::PUSH64rmr:
121  case X86::PUSH64i32:
122  case X86::POP32r:
123  case X86::POP64r:
124  return true;
125  default:
126  return false;
127  }
128 }
129 
130 void X86WinAllocaExpander::computeLowerings(MachineFunction &MF,
131  LoweringMap &Lowerings) {
132  // Do a one-pass reverse post-order walk of the CFG to conservatively estimate
133  // the offset between the stack pointer and the lowest touched part of the
134  // stack, and use that to decide how to lower each WinAlloca instruction.
135 
136  // Initialize OutOffset[B], the stack offset at exit from B, to something big.
138  for (MachineBasicBlock &MBB : MF)
139  OutOffset[&MBB] = INT32_MAX;
140 
141  // Note: we don't know the offset at the start of the entry block since the
142  // prologue hasn't been inserted yet, and how much that will adjust the stack
143  // pointer depends on register spills, which have not been computed yet.
144 
145  // Compute the reverse post-order.
147 
148  for (MachineBasicBlock *MBB : RPO) {
149  int64_t Offset = -1;
150  for (MachineBasicBlock *Pred : MBB->predecessors())
151  Offset = std::max(Offset, OutOffset[Pred]);
152  if (Offset == -1) Offset = INT32_MAX;
153 
154  for (MachineInstr &MI : *MBB) {
155  if (MI.getOpcode() == X86::WIN_ALLOCA_32 ||
156  MI.getOpcode() == X86::WIN_ALLOCA_64) {
157  // A WinAlloca moves StackPtr, and potentially touches it.
158  int64_t Amount = getWinAllocaAmount(&MI, MRI);
159  Lowering L = getLowering(Offset, Amount);
160  Lowerings[&MI] = L;
161  switch (L) {
162  case Sub:
163  Offset += Amount;
164  break;
165  case TouchAndSub:
166  Offset = Amount;
167  break;
168  case Probe:
169  Offset = 0;
170  break;
171  }
172  } else if (MI.isCall() || isPushPop(MI)) {
173  // Calls, pushes and pops touch the tip of the stack.
174  Offset = 0;
175  } else if (MI.getOpcode() == X86::ADJCALLSTACKUP32 ||
176  MI.getOpcode() == X86::ADJCALLSTACKUP64) {
177  Offset -= MI.getOperand(0).getImm();
178  } else if (MI.getOpcode() == X86::ADJCALLSTACKDOWN32 ||
179  MI.getOpcode() == X86::ADJCALLSTACKDOWN64) {
180  Offset += MI.getOperand(0).getImm();
181  } else if (MI.modifiesRegister(StackPtr, TRI)) {
182  // Any other modification of SP means we've lost track of it.
183  Offset = INT32_MAX;
184  }
185  }
186 
187  OutOffset[MBB] = Offset;
188  }
189 }
190 
191 static unsigned getSubOpcode(bool Is64Bit, int64_t Amount) {
192  if (Is64Bit)
193  return isInt<8>(Amount) ? X86::SUB64ri8 : X86::SUB64ri32;
194  return isInt<8>(Amount) ? X86::SUB32ri8 : X86::SUB32ri;
195 }
196 
197 void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) {
198  DebugLoc DL = MI->getDebugLoc();
199  MachineBasicBlock *MBB = MI->getParent();
201 
202  int64_t Amount = getWinAllocaAmount(MI, MRI);
203  if (Amount == 0) {
204  MI->eraseFromParent();
205  return;
206  }
207 
208  // These two variables differ on x32, which is a 64-bit target with a
209  // 32-bit alloca.
210  bool Is64Bit = STI->is64Bit();
211  bool Is64BitAlloca = MI->getOpcode() == X86::WIN_ALLOCA_64;
212  assert(SlotSize == 4 || SlotSize == 8);
213 
214  switch (L) {
215  case TouchAndSub: {
216  assert(Amount >= SlotSize);
217 
218  // Use a push to touch the top of the stack.
219  unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
220  BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
221  .addReg(RegA, RegState::Undef);
222  Amount -= SlotSize;
223  if (!Amount)
224  break;
225 
226  // Fall through to make any remaining adjustment.
228  }
229  case Sub:
230  assert(Amount > 0);
231  if (Amount == SlotSize) {
232  // Use push to save size.
233  unsigned RegA = Is64Bit ? X86::RAX : X86::EAX;
234  BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
235  .addReg(RegA, RegState::Undef);
236  } else {
237  // Sub.
238  BuildMI(*MBB, I, DL,
239  TII->get(getSubOpcode(Is64BitAlloca, Amount)), StackPtr)
240  .addReg(StackPtr)
241  .addImm(Amount);
242  }
243  break;
244  case Probe:
245  if (!NoStackArgProbe) {
246  // The probe lowering expects the amount in RAX/EAX.
247  unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX;
248  BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)
249  .addReg(MI->getOperand(0).getReg());
250 
251  // Do the probe.
252  STI->getFrameLowering()->emitStackProbe(*MBB->getParent(), *MBB, MI, DL,
253  /*InProlog=*/false);
254  } else {
255  // Sub
256  BuildMI(*MBB, I, DL,
257  TII->get(Is64BitAlloca ? X86::SUB64rr : X86::SUB32rr), StackPtr)
258  .addReg(StackPtr)
259  .addReg(MI->getOperand(0).getReg());
260  }
261  break;
262  }
263 
264  Register AmountReg = MI->getOperand(0).getReg();
265  MI->eraseFromParent();
266 
267  // Delete the definition of AmountReg.
268  if (MRI->use_empty(AmountReg))
269  if (MachineInstr *AmountDef = MRI->getUniqueVRegDef(AmountReg))
270  AmountDef->eraseFromParent();
271 }
272 
273 bool X86WinAllocaExpander::runOnMachineFunction(MachineFunction &MF) {
275  return false;
276 
277  MRI = &MF.getRegInfo();
278  STI = &MF.getSubtarget<X86Subtarget>();
279  TII = STI->getInstrInfo();
280  TRI = STI->getRegisterInfo();
281  StackPtr = TRI->getStackRegister();
282  SlotSize = TRI->getSlotSize();
283 
284  StackProbeSize = 4096;
285  if (MF.getFunction().hasFnAttribute("stack-probe-size")) {
286  MF.getFunction()
287  .getFnAttribute("stack-probe-size")
289  .getAsInteger(0, StackProbeSize);
290  }
291  NoStackArgProbe = MF.getFunction().hasFnAttribute("no-stack-arg-probe");
292  if (NoStackArgProbe)
293  StackProbeSize = INT64_MAX;
294 
295  LoweringMap Lowerings;
296  computeLowerings(MF, Lowerings);
297  for (auto &P : Lowerings)
298  lower(P.first, P.second);
299 
300  return true;
301 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Shadow Stack GC Lowering
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:339
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
This class implements a map that also provides access to all stored values in a deterministic order...
Definition: MapVector.h:37
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
#define INT64_MAX
Definition: DataTypes.h:77
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
static int64_t getWinAllocaAmount(MachineInstr *MI, MachineRegisterInfo *MRI)
Return the allocation amount for a WinAlloca instruction, or -1 if unknown.
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
iterator_range< pred_iterator > predecessors()
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:492
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:390
int64_t getImm() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:220
#define I(x, y, z)
Definition: MD5.cpp:58
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
rpo Deduce function attributes in RPO
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
static unsigned getSubOpcode(bool Is64Bit, int64_t Amount)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static bool isPushPop(const MachineInstr &MI)
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19