| AClass enum value | llvm::ARMSubtarget | protected |
| allowPositionIndependentMovt() const | llvm::ARMSubtarget | inline |
| allowsUnalignedMem() const | llvm::ARMSubtarget | inline |
| ARMArch | llvm::ARMSubtarget | protected |
| ARMArchEnum enum name | llvm::ARMSubtarget | protected |
| ARMLdStMultipleTiming enum name | llvm::ARMSubtarget | |
| ARMProcClass | llvm::ARMSubtarget | protected |
| ARMProcClassEnum enum name | llvm::ARMSubtarget | protected |
| ARMProcFamily | llvm::ARMSubtarget | protected |
| ARMProcFamilyEnum enum name | llvm::ARMSubtarget | protected |
| ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false) | llvm::ARMSubtarget | |
| CPUString | llvm::ARMSubtarget | protected |
| DoubleIssue enum value | llvm::ARMSubtarget | |
| DoubleIssueCheckUnalignedAccess enum value | llvm::ARMSubtarget | |
| enableMachinePipeliner() const override | llvm::ARMSubtarget | |
| enableMachineScheduler() const override | llvm::ARMSubtarget | |
| enablePostRAMachineScheduler() const override | llvm::ARMSubtarget | |
| enablePostRAScheduler() const override | llvm::ARMSubtarget | |
| enableSubRegLiveness() const override | llvm::ARMSubtarget | |
| getCallLowering() const override | llvm::ARMSubtarget | |
| getCPUString() const | llvm::ARMSubtarget | inline |
| getDualLoadStoreAlignment() const | llvm::ARMSubtarget | inline |
| getFrameLowering() const override | llvm::ARMSubtarget | inline |
| getFramePointerReg() const | llvm::ARMSubtarget | inline |
| getGPRAllocationOrder(const MachineFunction &MF) const | llvm::ARMSubtarget | |
| getInstrInfo() const override | llvm::ARMSubtarget | inline |
| getInstrItineraryData() const override | llvm::ARMSubtarget | inline |
| getInstructionSelector() const override | llvm::ARMSubtarget | |
| getLdStMultipleTiming() const | llvm::ARMSubtarget | inline |
| getLegalizerInfo() const override | llvm::ARMSubtarget | |
| getMaxInlineSizeThreshold() const | llvm::ARMSubtarget | inline |
| getMaxInterleaveFactor() const | llvm::ARMSubtarget | inline |
| getMaxMemcpyTPInlineSizeThreshold() const | llvm::ARMSubtarget | inline |
| getMispredictionPenalty() const | llvm::ARMSubtarget | |
| getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const | llvm::ARMSubtarget | inline |
| getPartialUpdateClearance() const | llvm::ARMSubtarget | inline |
| getPreferBranchLogAlignment() const | llvm::ARMSubtarget | inline |
| getPreISelOperandLatencyAdjustment() const | llvm::ARMSubtarget | inline |
| getPushPopSplitVariation(const MachineFunction &MF) const | llvm::ARMSubtarget | |
| getRegBankInfo() const override | llvm::ARMSubtarget | |
| getRegisterInfo() const override | llvm::ARMSubtarget | inline |
| getReturnOpcode() const | llvm::ARMSubtarget | inline |
| getSelectionDAGInfo() const override | llvm::ARMSubtarget | inline |
| getStackAlignment() const | llvm::ARMSubtarget | inline |
| getTargetLowering() const override | llvm::ARMSubtarget | inline |
| getTargetTriple() const | llvm::ARMSubtarget | inline |
| hasAnyDataBarrier() const | llvm::ARMSubtarget | inline |
| hasARMOps() const | llvm::ARMSubtarget | inline |
| hasBaseDSP() const | llvm::ARMSubtarget | inline |
| hasFPARMv8Base() const | llvm::ARMSubtarget | inline |
| hasFusion() const | llvm::ARMSubtarget | inline |
| hasMinSize() const | llvm::ARMSubtarget | inline |
| hasVFP2Base() const | llvm::ARMSubtarget | inline |
| hasVFP3Base() const | llvm::ARMSubtarget | inline |
| hasVFP4Base() const | llvm::ARMSubtarget | inline |
| ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override | llvm::ARMSubtarget | |
| initializeSubtargetDependencies(StringRef CPU, StringRef FS) | llvm::ARMSubtarget | |
| InstrItins | llvm::ARMSubtarget | protected |
| isAAPCS16_ABI() const | llvm::ARMSubtarget | |
| isAAPCS_ABI() const | llvm::ARMSubtarget | |
| isAClass() const | llvm::ARMSubtarget | inline |
| isAPCS_ABI() const | llvm::ARMSubtarget | |
| isCortexA15() const | llvm::ARMSubtarget | inline |
| isCortexA5() const | llvm::ARMSubtarget | inline |
| isCortexA7() const | llvm::ARMSubtarget | inline |
| isCortexA8() const | llvm::ARMSubtarget | inline |
| isCortexA9() const | llvm::ARMSubtarget | inline |
| isCortexM3() const | llvm::ARMSubtarget | inline |
| isCortexM55() const | llvm::ARMSubtarget | inline |
| isCortexM7() const | llvm::ARMSubtarget | inline |
| isCortexM85() const | llvm::ARMSubtarget | inline |
| isCortexR5() const | llvm::ARMSubtarget | inline |
| isGVIndirectSymbol(const GlobalValue *GV) const | llvm::ARMSubtarget | |
| isGVInGOT(const GlobalValue *GV) const | llvm::ARMSubtarget | |
| isKrait() const | llvm::ARMSubtarget | inline |
| isLikeA9() const | llvm::ARMSubtarget | inline |
| isLittle() const | llvm::ARMSubtarget | inline |
| IsLittle | llvm::ARMSubtarget | protected |
| isMClass() const | llvm::ARMSubtarget | inline |
| isR9Reserved() const | llvm::ARMSubtarget | inline |
| isRClass() const | llvm::ARMSubtarget | inline |
| isReadTPSoft() const | llvm::ARMSubtarget | inline |
| isROPI() const | llvm::ARMSubtarget | |
| isRWPI() const | llvm::ARMSubtarget | |
| isSwift() const | llvm::ARMSubtarget | inline |
| isTargetAEABI() const | llvm::ARMSubtarget | inline |
| isTargetAndroid() const | llvm::ARMSubtarget | inline |
| isTargetCOFF() const | llvm::ARMSubtarget | inline |
| isTargetDarwin() const | llvm::ARMSubtarget | inline |
| isTargetDriverKit() const | llvm::ARMSubtarget | inline |
| isTargetEHABICompatible() const | llvm::ARMSubtarget | inline |
| isTargetELF() const | llvm::ARMSubtarget | inline |
| isTargetGNUAEABI() const | llvm::ARMSubtarget | inline |
| isTargetHardFloat() const | llvm::ARMSubtarget | |
| isTargetIOS() const | llvm::ARMSubtarget | inline |
| isTargetLinux() const | llvm::ARMSubtarget | inline |
| isTargetMachO() const | llvm::ARMSubtarget | inline |
| isTargetMuslAEABI() const | llvm::ARMSubtarget | inline |
| isTargetNaCl() const | llvm::ARMSubtarget | inline |
| isTargetNetBSD() const | llvm::ARMSubtarget | inline |
| isTargetWatchABI() const | llvm::ARMSubtarget | inline |
| isTargetWatchOS() const | llvm::ARMSubtarget | inline |
| isTargetWindows() const | llvm::ARMSubtarget | inline |
| isThumb1Only() const | llvm::ARMSubtarget | inline |
| isThumb2() const | llvm::ARMSubtarget | inline |
| isXRaySupported() const override | llvm::ARMSubtarget | |
| LdStMultipleTiming | llvm::ARMSubtarget | protected |
| MaxInterleaveFactor | llvm::ARMSubtarget | protected |
| MClass enum value | llvm::ARMSubtarget | protected |
| MVEVectorCostFactor | llvm::ARMSubtarget | protected |
| None enum value | llvm::ARMSubtarget | protected |
| NoSplit enum value | llvm::ARMSubtarget | |
| Options | llvm::ARMSubtarget | protected |
| OptMinSize | llvm::ARMSubtarget | protected |
| Others enum value | llvm::ARMSubtarget | protected |
| ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) | llvm::ARMSubtarget | |
| PartialUpdateClearance | llvm::ARMSubtarget | protected |
| PreferBranchLogAlignment | llvm::ARMSubtarget | protected |
| PreISelOperandLatencyAdjustment | llvm::ARMSubtarget | protected |
| PushPopSplitVariation enum name | llvm::ARMSubtarget | |
| RClass enum value | llvm::ARMSubtarget | protected |
| RestrictIT | llvm::ARMSubtarget | protected |
| restrictIT() const | llvm::ARMSubtarget | inline |
| SchedModel | llvm::ARMSubtarget | protected |
| SingleIssue enum value | llvm::ARMSubtarget | |
| SingleIssuePlusExtras enum value | llvm::ARMSubtarget | |
| SplitR11AAPCSSignRA enum value | llvm::ARMSubtarget | |
| SplitR11WindowsSEH enum value | llvm::ARMSubtarget | |
| SplitR7 enum value | llvm::ARMSubtarget | |
| stackAlignment | llvm::ARMSubtarget | protected |
| SupportsTailCall | llvm::ARMSubtarget | protected |
| supportsTailCall() const | llvm::ARMSubtarget | inline |
| TargetTriple | llvm::ARMSubtarget | protected |
| TM | llvm::ARMSubtarget | protected |
| useAA() const override | llvm::ARMSubtarget | inline |
| useDFAforSMS() const override | llvm::ARMSubtarget | |
| useFastISel() const | llvm::ARMSubtarget | |
| useFPVFMx() const | llvm::ARMSubtarget | inline |
| useFPVFMx16() const | llvm::ARMSubtarget | inline |
| useFPVFMx64() const | llvm::ARMSubtarget | inline |
| useFPVMLx() const | llvm::ARMSubtarget | inline |
| useMachinePipeliner() const | llvm::ARMSubtarget | inline |
| useMachineScheduler() const | llvm::ARMSubtarget | inline |
| useMovt() const | llvm::ARMSubtarget | |
| UseMulOps | llvm::ARMSubtarget | protected |
| useMulOps() const | llvm::ARMSubtarget | inline |
| useNEONForSinglePrecisionFP() const | llvm::ARMSubtarget | inline |
| UseSjLjEH | llvm::ARMSubtarget | protected |
| useSjLjEH() const | llvm::ARMSubtarget | inline |
| useStride4VFPs() const | llvm::ARMSubtarget | |
