| allowMixed16_32() const | llvm::MipsSubtarget | inline |
| CallLoweringInfo | llvm::MipsSubtarget | protected |
| disableMadd4() const | llvm::MipsSubtarget | inline |
| enableLongBranchPass() const | llvm::MipsSubtarget | inline |
| enablePostRAScheduler() const override | llvm::MipsSubtarget | |
| getABI() const | llvm::MipsSubtarget | |
| getCallLowering() const override | llvm::MipsSubtarget | |
| getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override | llvm::MipsSubtarget | |
| getFrameLowering() const override | llvm::MipsSubtarget | inline |
| getGPRSizeInBytes() const | llvm::MipsSubtarget | inline |
| getInstrInfo() const override | llvm::MipsSubtarget | inline |
| getInstrItineraryData() const override | llvm::MipsSubtarget | inline |
| getInstructionSelector() const override | llvm::MipsSubtarget | |
| getLegalizerInfo() const override | llvm::MipsSubtarget | |
| getOptLevelToEnablePostRAScheduler() const override | llvm::MipsSubtarget | |
| getRegBankInfo() const override | llvm::MipsSubtarget | |
| getRegisterInfo() const override | llvm::MipsSubtarget | inline |
| getRelocationModel() const | llvm::MipsSubtarget | |
| getSelectionDAGInfo() const override | llvm::MipsSubtarget | |
| getStackAlignment() const | llvm::MipsSubtarget | inline |
| getTargetLowering() const override | llvm::MipsSubtarget | inline |
| has3D() const | llvm::MipsSubtarget | inline |
| hasCnMips() const | llvm::MipsSubtarget | inline |
| hasCnMipsP() const | llvm::MipsSubtarget | inline |
| hasCRC() const | llvm::MipsSubtarget | inline |
| hasDSP() const | llvm::MipsSubtarget | inline |
| hasDSPR2() const | llvm::MipsSubtarget | inline |
| hasDSPR3() const | llvm::MipsSubtarget | inline |
| hasEVA() const | llvm::MipsSubtarget | inline |
| hasExtractInsert() const | llvm::MipsSubtarget | inline |
| hasGINV() const | llvm::MipsSubtarget | inline |
| hasMips1() const | llvm::MipsSubtarget | inline |
| hasMips2() const | llvm::MipsSubtarget | inline |
| hasMips3() const | llvm::MipsSubtarget | inline |
| hasMips32() const | llvm::MipsSubtarget | inline |
| hasMips32r2() const | llvm::MipsSubtarget | inline |
| hasMips32r3() const | llvm::MipsSubtarget | inline |
| hasMips32r5() const | llvm::MipsSubtarget | inline |
| hasMips32r6() const | llvm::MipsSubtarget | inline |
| hasMips4() const | llvm::MipsSubtarget | inline |
| hasMips4_32() const | llvm::MipsSubtarget | inline |
| hasMips4_32r2() const | llvm::MipsSubtarget | inline |
| hasMips5() const | llvm::MipsSubtarget | inline |
| hasMips64() const | llvm::MipsSubtarget | inline |
| hasMips64r2() const | llvm::MipsSubtarget | inline |
| hasMips64r3() const | llvm::MipsSubtarget | inline |
| hasMips64r5() const | llvm::MipsSubtarget | inline |
| hasMips64r6() const | llvm::MipsSubtarget | inline |
| hasMSA() const | llvm::MipsSubtarget | inline |
| hasMT() const | llvm::MipsSubtarget | inline |
| hasMTHC1() const | llvm::MipsSubtarget | inline |
| hasStandardEncoding() const | llvm::MipsSubtarget | inline |
| hasSym32() const | llvm::MipsSubtarget | inline |
| hasVFPU() const | llvm::MipsSubtarget | inline |
| hasVirt() const | llvm::MipsSubtarget | inline |
| inAbs2008Mode() const | llvm::MipsSubtarget | inline |
| initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) | llvm::MipsSubtarget | |
| inMicroMips32r6Mode() const | llvm::MipsSubtarget | inline |
| inMicroMipsMode() const | llvm::MipsSubtarget | inline |
| inMips16HardFloat() const | llvm::MipsSubtarget | inline |
| inMips16Mode() const | llvm::MipsSubtarget | inline |
| inMips16ModeDefault() const | llvm::MipsSubtarget | inline |
| InstSelector | llvm::MipsSubtarget | protected |
| isABI_FPXX() const | llvm::MipsSubtarget | inline |
| isABI_N32() const | llvm::MipsSubtarget | |
| isABI_N64() const | llvm::MipsSubtarget | |
| isABI_O32() const | llvm::MipsSubtarget | |
| isABICalls() const | llvm::MipsSubtarget | inline |
| isFP64bit() const | llvm::MipsSubtarget | inline |
| isFPXX() const | llvm::MipsSubtarget | inline |
| isGP32bit() const | llvm::MipsSubtarget | inline |
| isGP64bit() const | llvm::MipsSubtarget | inline |
| isLittle() const | llvm::MipsSubtarget | inline |
| isNaN2008() const | llvm::MipsSubtarget | inline |
| isPositionIndependent() const | llvm::MipsSubtarget | |
| isPTR32bit() const | llvm::MipsSubtarget | inline |
| isPTR64bit() const | llvm::MipsSubtarget | inline |
| isSingleFloat() const | llvm::MipsSubtarget | inline |
| isTargetELF() const | llvm::MipsSubtarget | inline |
| isTargetNaCl() const | llvm::MipsSubtarget | inline |
| isXRaySupported() const override | llvm::MipsSubtarget | inline |
| Legalizer | llvm::MipsSubtarget | protected |
| MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride) | llvm::MipsSubtarget | |
| noOddSPReg() const | llvm::MipsSubtarget | inline |
| os16() const | llvm::MipsSubtarget | inline |
| ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) | llvm::MipsSubtarget | |
| RegBankInfo | llvm::MipsSubtarget | protected |
| setHelperClassesMips16() | llvm::MipsSubtarget | |
| setHelperClassesMipsSE() | llvm::MipsSubtarget | |
| systemSupportsUnalignedAccess() const | llvm::MipsSubtarget | inline |
| useConstantIslands() | llvm::MipsSubtarget | static |
| useIndirectJumpsHazard() const | llvm::MipsSubtarget | inline |
| useLongCalls() const | llvm::MipsSubtarget | inline |
| useOddSPReg() const | llvm::MipsSubtarget | inline |
| useSmallSection() const | llvm::MipsSubtarget | inline |
| useSoftFloat() const | llvm::MipsSubtarget | inline |
| useXGOT() const | llvm::MipsSubtarget | inline |
| ~MipsSubtarget() override | llvm::MipsSubtarget | |
