LLVM  16.0.0git
llvm::PPCPostRASchedStrategy Member List

This is the complete list of members for llvm::PPCPostRASchedStrategy, including all inherited members.

biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) constllvm::PPCPostRASchedStrategyprotected
BotHeightReduce enum valuellvm::GenericSchedulerBase
BotPathReduce enum valuellvm::GenericSchedulerBase
BotRootsllvm::PostGenericSchedulerprotected
CandReason enum namellvm::GenericSchedulerBase
Cluster enum valuellvm::GenericSchedulerBase
Contextllvm::GenericSchedulerBaseprotected
DAGllvm::PostGenericSchedulerprotected
doMBBSchedRegionsTopDown() constllvm::MachineSchedStrategyinlinevirtual
dumpPolicy() constllvm::MachineSchedStrategyinlinevirtual
enterMBB(MachineBasicBlock *MBB) overridellvm::PPCPostRASchedStrategyprotectedvirtual
GenericSchedulerBase(const MachineSchedContext *C)llvm::GenericSchedulerBaseinlineprotected
getReasonStr(GenericSchedulerBase::CandReason Reason)llvm::GenericSchedulerBasestatic
initialize(ScheduleDAGMI *Dag) overridellvm::PPCPostRASchedStrategyprotectedvirtual
initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) overridellvm::PostGenericSchedulerinlinevirtual
leaveMBB() overridellvm::PPCPostRASchedStrategyprotectedvirtual
NextDefUse enum valuellvm::GenericSchedulerBase
NoCand enum valuellvm::GenericSchedulerBase
NodeOrder enum valuellvm::GenericSchedulerBase
Only1 enum valuellvm::GenericSchedulerBase
PhysReg enum valuellvm::GenericSchedulerBase
pickNode(bool &IsTopNode) overridellvm::PPCPostRASchedStrategyprotectedvirtual
pickNodeFromQueue(SchedCandidate &Cand)llvm::PostGenericSchedulerprotected
PostGenericScheduler(const MachineSchedContext *C)llvm::PostGenericSchedulerinline
PPCPostRASchedStrategy(const MachineSchedContext *C)llvm::PPCPostRASchedStrategyinline
RegCritical enum valuellvm::GenericSchedulerBase
RegExcess enum valuellvm::GenericSchedulerBase
registerRoots() overridellvm::PostGenericSchedulervirtual
RegMax enum valuellvm::GenericSchedulerBase
releaseBottomNode(SUnit *SU) overridellvm::PostGenericSchedulerinlinevirtual
releaseTopNode(SUnit *SU) overridellvm::PostGenericSchedulerinlinevirtual
Remllvm::GenericSchedulerBaseprotected
ResourceDemand enum valuellvm::GenericSchedulerBase
ResourceReduce enum valuellvm::GenericSchedulerBase
SchedModelllvm::GenericSchedulerBaseprotected
schedNode(SUnit *SU, bool IsTopNode) overridellvm::PostGenericSchedulervirtual
scheduleTree(unsigned SubtreeID) overridellvm::PostGenericSchedulerinlinevirtual
setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone, SchedBoundary *OtherZone)llvm::GenericSchedulerBaseprotected
shouldTrackLaneMasks() constllvm::MachineSchedStrategyinlinevirtual
shouldTrackPressure() const overridellvm::PostGenericSchedulerinlinevirtual
Stall enum valuellvm::GenericSchedulerBase
Topllvm::PostGenericSchedulerprotected
TopDepthReduce enum valuellvm::GenericSchedulerBase
TopPathReduce enum valuellvm::GenericSchedulerBase
traceCandidate(const SchedCandidate &Cand)llvm::GenericSchedulerBaseprotected
TRIllvm::GenericSchedulerBaseprotected
tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) overridellvm::PPCPostRASchedStrategyprotectedvirtual
Weak enum valuellvm::GenericSchedulerBase
~MachineSchedStrategy()=defaultllvm::MachineSchedStrategyvirtual
~PostGenericScheduler() override=defaultllvm::PostGenericScheduler