LLVM  14.0.0git
llvm::TargetInstrInfo Member List

This is the complete list of members for llvm::TargetInstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) constllvm::TargetInstrInfoinlinevirtual
analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) constllvm::TargetInstrInfoinlinevirtual
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) constllvm::TargetInstrInfoinlinevirtual
analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) constllvm::TargetInstrInfoinlinevirtual
analyzeLoopForPipelining(MachineBasicBlock *LoopBB) constllvm::TargetInstrInfoinlinevirtual
analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) constllvm::TargetInstrInfoinlinevirtual
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) constllvm::TargetInstrInfoinlinevirtual
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) constllvm::TargetInstrInfoinlinevirtual
breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) constllvm::TargetInstrInfoinlinevirtual
canCopyGluedNodeDuringSchedule(SDNode *N) constllvm::TargetInstrInfoinlinevirtual
canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) constllvm::TargetInstrInfoinlinevirtual
canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) constllvm::TargetInstrInfoinlinevirtual
ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) constllvm::TargetInstrInfoinlinevirtual
CommuteAnyOperandIndexllvm::TargetInstrInfostatic
commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) constllvm::TargetInstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) constllvm::TargetInstrInfoprotectedvirtual
ComplexDeprecationPredicate typedefllvm::MCInstrInfo
convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) constllvm::TargetInstrInfoinlinevirtual
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) constllvm::TargetInstrInfoinlinevirtual
createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfovirtual
createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) constllvm::TargetInstrInfoinlinevirtual
createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) constllvm::TargetInstrInfoinlinevirtual
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) constllvm::TargetInstrInfovirtual
CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) constllvm::TargetInstrInfovirtual
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) constllvm::TargetInstrInfovirtual
CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) constllvm::TargetInstrInfoinlinevirtual
CreateTargetScheduleState(const TargetSubtargetInfo &) constllvm::TargetInstrInfoinlinevirtual
decomposeMachineOperandsTargetFlags(unsigned) constllvm::TargetInstrInfoinlinevirtual
defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) constllvm::TargetInstrInfo
describeLoadedValue(const MachineInstr &MI, Register Reg) constllvm::TargetInstrInfovirtual
duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) constllvm::TargetInstrInfovirtual
expandPostRAPseudo(MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) constllvm::TargetInstrInfoinlinevirtual
finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) constllvm::TargetInstrInfoinlinevirtual
findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) constllvm::TargetInstrInfovirtual
fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)llvm::TargetInstrInfoprotectedstatic
FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) constllvm::TargetInstrInfoinlinevirtual
foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) constllvm::TargetInstrInfo
foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) constllvm::TargetInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) constllvm::TargetInstrInfoinlineprotectedvirtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) constllvm::TargetInstrInfoinlineprotectedvirtual
genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) constllvm::TargetInstrInfovirtual
get(unsigned Opcode) constllvm::MCInstrInfoinline
getAddressSpaceForPseudoSourceKind(unsigned Kind) constllvm::TargetInstrInfoinlinevirtual
getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) constllvm::TargetInstrInfoinlinevirtual
getBranchDestBlock(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
getCalleeOperand(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
getCallFrameDestroyOpcode() constllvm::TargetInstrInfoinline
getCallFrameSetupOpcode() constllvm::TargetInstrInfoinline
getCatchReturnOpcode() constllvm::TargetInstrInfoinline
getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) constllvm::TargetInstrInfoinlinevirtual
getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) constllvm::MCInstrInfo
getExecutionDomain(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
getExtendResourceLenLimit() constllvm::TargetInstrInfoinlinevirtual
getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) constllvm::TargetInstrInfo
getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) constllvm::TargetInstrInfoinlineprotectedvirtual
getFrameSize(const MachineInstr &I) constllvm::TargetInstrInfoinline
getFrameTotalSize(const MachineInstr &I) constllvm::TargetInstrInfoinline
getIncrementValue(const MachineInstr &MI, int &Value) constllvm::TargetInstrInfoinlinevirtual
getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) constllvm::TargetInstrInfovirtual
getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) constllvm::TargetInstrInfo
getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) constllvm::TargetInstrInfoinlineprotectedvirtual
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) constllvm::TargetInstrInfovirtual
getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) constllvm::TargetInstrInfovirtual
getInstSizeInBytes(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) constllvm::TargetInstrInfovirtual
getMachineCSELookAheadLimit() constllvm::TargetInstrInfoinlinevirtual
getMemOperandAACheckLimit() constllvm::TargetInstrInfoinlinevirtual
getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfo
getMIRFormatter() constllvm::TargetInstrInfoinlinevirtual
getName(unsigned Opcode) constllvm::MCInstrInfoinline
getNop() constllvm::TargetInstrInfovirtual
getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) constllvm::TargetInstrInfovirtual
getNumOpcodes() constllvm::MCInstrInfoinline
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) constllvm::TargetInstrInfoinlinevirtual
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) constllvm::TargetInstrInfovirtual
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) constllvm::TargetInstrInfovirtual
getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) constllvm::TargetInstrInfoinlinevirtual
getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) constllvm::TargetInstrInfoinlinevirtual
getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
getPatchpointUnfoldableRange(const MachineInstr &MI) constllvm::TargetInstrInfovirtual
getPredicationCost(const MachineInstr &MI) constllvm::TargetInstrInfovirtual
getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) constllvm::TargetInstrInfovirtual
getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) constllvm::TargetInstrInfo
getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) constllvm::TargetInstrInfoinlineprotectedvirtual
getReturnOpcode() constllvm::TargetInstrInfoinline
getSerializableBitmaskMachineOperandTargetFlags() constllvm::TargetInstrInfoinlinevirtual
getSerializableDirectMachineOperandTargetFlags() constllvm::TargetInstrInfoinlinevirtual
getSerializableMachineMemOperandTargetFlags() constllvm::TargetInstrInfoinlinevirtual
getSerializableTargetIndices() constllvm::TargetInstrInfoinlinevirtual
getSPAdjust(const MachineInstr &MI) constllvm::TargetInstrInfovirtual
getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) constllvm::TargetInstrInfovirtual
getTailDuplicateSize(CodeGenOpt::Level OptLevel) constllvm::TargetInstrInfoinlinevirtual
getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
hasCommutePreference(MachineInstr &MI, bool &Commute) constllvm::TargetInstrInfoinlinevirtual
hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) constllvm::TargetInstrInfoinlinevirtual
hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) constllvm::TargetInstrInfovirtual
hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) constllvm::TargetInstrInfovirtual
hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) constllvm::TargetInstrInfovirtual
hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) constllvm::TargetInstrInfo
hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) constllvm::TargetInstrInfovirtual
InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, const uint8_t *DF, const ComplexDeprecationPredicate *CDI, unsigned NO)llvm::MCInstrInfoinline
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) constllvm::TargetInstrInfoinlinevirtual
insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) constllvm::TargetInstrInfoinlinevirtual
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) constllvm::TargetInstrInfovirtual
insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) constllvm::TargetInstrInfovirtual
insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) constllvm::TargetInstrInfoinlinevirtual
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) constllvm::TargetInstrInfoinlinevirtual
insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) constllvm::TargetInstrInfoinline
isAddImmediate(const MachineInstr &MI, Register Reg) constllvm::TargetInstrInfoinlinevirtual
isAsCheapAsAMove(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
isAssociativeAndCommutative(const MachineInstr &Inst) constllvm::TargetInstrInfoinlinevirtual
isBasicBlockPrologue(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) constllvm::TargetInstrInfoinlinevirtual
isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) constllvm::TargetInstrInfoinlinevirtual
isCopyInstr(const MachineInstr &MI) constllvm::TargetInstrInfoinline
isCopyInstrImpl(const MachineInstr &MI) constllvm::TargetInstrInfoinlineprotectedvirtual
isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) constllvm::TargetInstrInfoinlinevirtual
isFrameInstr(const MachineInstr &I) constllvm::TargetInstrInfoinline
isFrameSetup(const MachineInstr &I) constllvm::TargetInstrInfoinline
isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) constllvm::TargetInstrInfoinlinevirtual
isGenericOpcode(unsigned Opc)llvm::TargetInstrInfoinlinestatic
isHighLatencyDef(int opc) constllvm::TargetInstrInfoinlinevirtual
isIgnorableUse(const MachineOperand &MO) constllvm::TargetInstrInfoinlinevirtual
isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) constllvm::TargetInstrInfoinlinevirtual
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) constllvm::TargetInstrInfoinlinevirtual
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) constllvm::TargetInstrInfoinlinevirtual
isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) constllvm::TargetInstrInfoinlinevirtual
isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) constllvm::TargetInstrInfovirtual
isPCRelRegisterOperandLegal(const MachineOperand &MO) constllvm::TargetInstrInfoinlinevirtual
isPostIncrement(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
isPredicable(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
isPredicated(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) constllvm::TargetInstrInfoinlinevirtual
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) constllvm::TargetInstrInfoinlinevirtual
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) constllvm::TargetInstrInfoinlinevirtual
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) constllvm::TargetInstrInfoinlinevirtual
isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) constllvm::TargetInstrInfoinlineprotectedvirtual
isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) constllvm::TargetInstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) constllvm::TargetInstrInfoinlinevirtual
isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) constllvm::TargetInstrInfovirtual
isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) constllvm::TargetInstrInfoinlinevirtual
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) constllvm::TargetInstrInfoinlinevirtual
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) constllvm::TargetInstrInfoinlinevirtual
isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) constllvm::TargetInstrInfoinlinevirtual
isSubregFoldable() constllvm::TargetInstrInfoinlinevirtual
isTailCall(const MachineInstr &Inst) constllvm::TargetInstrInfoinlinevirtual
isThroughputPattern(MachineCombinerPattern Pattern) constllvm::TargetInstrInfovirtual
isTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA=nullptr) constllvm::TargetInstrInfoinline
isUnconditionalTailCall(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
isUnpredicatedTerminator(const MachineInstr &MI) constllvm::TargetInstrInfo
isUnspillableTerminator(const MachineInstr *MI) constllvm::TargetInstrInfoinline
isUnspillableTerminatorImpl(const MachineInstr *MI) constllvm::TargetInstrInfoinlineprotectedvirtual
isZeroCost(unsigned Opcode) constllvm::TargetInstrInfoinline
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) constllvm::TargetInstrInfovirtual
operator=(const TargetInstrInfo &)=deletellvm::TargetInstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) constllvm::TargetInstrInfoinlinevirtual
optimizeCondBranch(MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) constllvm::TargetInstrInfoinlinevirtual
optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) constllvm::TargetInstrInfoinlinevirtual
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) constllvm::TargetInstrInfovirtual
predictBranchSizeForIfCvt(MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) constllvm::TargetInstrInfovirtual
reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) constllvm::TargetInstrInfo
reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) constllvm::TargetInstrInfoinlinevirtual
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) constllvm::TargetInstrInfovirtual
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) constllvm::TargetInstrInfoinlinevirtual
replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) constllvm::TargetInstrInfoinlinevirtual
ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) constllvm::TargetInstrInfovirtual
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) constllvm::TargetInstrInfoinlinevirtual
setExecutionDomain(MachineInstr &MI, unsigned Domain) constllvm::TargetInstrInfoinlinevirtual
setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) constllvm::TargetInstrInfoinlinevirtual
shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) constllvm::TargetInstrInfoinlinevirtual
shouldOutlineFromFunctionByDefault(MachineFunction &MF) constllvm::TargetInstrInfoinlinevirtual
shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) constllvm::TargetInstrInfoinlinevirtual
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) constllvm::TargetInstrInfoinlinevirtual
shouldSink(const MachineInstr &MI) constllvm::TargetInstrInfoinlinevirtual
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) constllvm::TargetInstrInfoinlinevirtual
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) constllvm::TargetInstrInfoinlinevirtual
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)llvm::TargetInstrInfoinline
TargetInstrInfo(const TargetInstrInfo &)=deletellvm::TargetInstrInfo
unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) constllvm::TargetInstrInfoinlinevirtual
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) constllvm::TargetInstrInfoinlinevirtual
useMachineCombiner() constllvm::TargetInstrInfoinlinevirtual
usePreRAHazardRecognizer() constllvm::TargetInstrInfo
verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) constllvm::TargetInstrInfoinlinevirtual
~TargetInstrInfo()llvm::TargetInstrInfovirtual