#include <assert.h>
#include <stdio.h>
#include <cstdio>

Include dependency graph for README.txt:

Macros
#define	PMD_MASK (~((1UL << 23) - 1))

Functions
The legalization code for mul with overflow needs to be made more robust before this can be implemented though Get the C front end to expand	hypot (x, y) -> llvm.sqrt(x x+y y) when errno and precision don 't matter(ffastmath). Misc/mandel will like this. :) This isn 't safe in general, even on darwin. See the libm implementation of hypot for examples(which special case when x/y are exactly zero to get signed zeros etc right). On targets with expensive 64-bit multiply, we could LSR this:for(i=...

	for (i=...;++i, tmp+=tmp) x

This would be a win on but not x86 or ppc64	setlt (loadi8 Phi)

int	foo (int z, int n)

This is blocked on not handling X X X	powi (X, 3)(see note above). The issue is that we end up getting t

void	f ()

int	h (int j, int l)

float	sincosf (float x, float sin, float cos)

long double	sincosl (long double x, long double sin, long double cos)

	if (target< 32)

but this requires TBAA This isn t recognized as bswap by	instcombine (yes, it really is bswap)

We don t delete this output free because trip count analysis doesn t realize that it is	finite (if it were infinite, it would be undefined). Not having this blocks Loop Idiom from matching strlen and friends. void foo(char *C)

These idioms should be recognized as	popcount (see PR1488)

unsigned int	popcount (unsigned int input)

	for (i=0;i< 32;i++) if(a &(1<<(31-i))) return i

This sort of thing should be added to the loop idiom pass These should turn into single	bit (unaligned?) loads on little/big endian processors. unsigned short read_16_le(const unsigned char *adr)

unsigned short	read_16_be (const unsigned char *adr)

int	test (U32 inst, U64 regs)

return *	pow2m1 (n - 1)+1

< i32 > ret i32 tmp foo define i32	bar (i32 *%x)

THotKey	GetHotKey ()

	into (-m64 -O3 -fno-exceptions -static -fomit-frame-pointer)

	if (x==3) y=0

The loop unroller should partially unroll	loops (instead of peeling them) when code growth isn 't too bad and when an unroll count allows simplification of some code within the loop. One trivial example is

unsigned long long	f6 (unsigned long long x, unsigned long long y, int z)

	This (and similar related idioms)

return	j (j<< 16)

aka conv or ret i32 or6 or even i depending on the speed of the multiplier The best way to handle this is to canonicalize it to a multiply in IR and have codegen handle lowering multiplies to shifts on cpus where shifts are faster We do a number of simplifications in simplify libcalls to strength reduce standard library but we don t currently merge them together For it is useful to merge	memcpy (a, b, strlen(b)) -> strcpy. This can only be done safely if "b" isn 't modified between the strlen and memcpy of course. We compile this program:(from GCC PR11680) http:Into code that runs the same speed in fast/slow modes, but both modes run 2x slower than when compile with GCC(either 4.0 or 4.2):$ llvm-g++perf.cpp -O3 -fno-exceptions $ time ./a.out fast 1.821u 0.003s 0:01.82 100.0% 0+0k 0+0io 0pf+0w $ g++perf.cpp -O3 -fno-exceptions $ time ./a.out fast 0.821u 0.001s 0:00.82 100.0% 0+0k 0+0io 0pf+0w It looks like we are making the same inlining decisions, so this may be raw codegen badness or something else(haven 't investigated). Divisibility by constant can be simplified(according to GCC PR12849) from being a mulhi to being a mul lo(cheaper). Testcase:void bar(unsigned n)

This is equivalent to the where is the multiplicative inverse and	is ((2^32) -1)/3+1

This should optimize to or at least something sane Currently not optimized with clang emit llvm bc opt O3 int	a (int a, int b, int c)

Should fold to a &&b c Currently not optimized with clang emit llvm bc opt O3 int	a (int x)

Should combine to x &Currently not optimized with clang emit llvm bc opt O3 unsigned	a (unsigned a)

Should combine to a *Currently not optimized with clang emit llvm bc opt O3 unsigned	a (char *x)

There s an unnecessary zext in the generated code with clang emit llvm bc opt O3 unsigned	a (unsigned long long x)

Should combine to *unsigned x &Currently not optimized with clang emit llvm bc opt O3 int	g (int x)

Should combine to x<=9" (the sub has nsw). Currently notoptimized with "clang -emit-llvm-bc\|opt -O3".int g(int x) { return (x + 10) < 0; }Should combine to "x< -10" (the add has nsw). Currently notoptimized with "clang -emit-llvm-bc\|opt -O3".int f(int i, int j) { return i < j + 1; }int g(int i, int j) { return j > i - 1; }Should combine to "i<=j" (the add/sub has nsw). Currently notoptimized with "clang -emit-llvm-bc\|opt -O3".unsigned f(unsigned x) { return ((x & 7) + 1) & 15; }The & 15 part should be optimized away, it doesn't change the result. Currentlynot optimized with "clang -emit-llvm-bc\|opt -O3".This was noticed in the entryblock for grokdeclarator in 403.gcc: %tmp = icmp eq i32 %decl_context, 4 %decl_context_addr.0 = select i1 %tmp, i32 3, i32 %decl_context %tmp1 = icmp eq i32 %decl_context_addr.0, 1 %decl_context_addr.1 = select i1 %tmp1, i32 0, i32 %decl_context_addr.0tmp1 should be simplified to something like: (!tmp \|\| decl_context == 1)This allows recursive simplifications, tmp1 is used all over the place inthe function, e.g. by: %tmp23 = icmp eq i32 %decl_context_addr.1, 0 ; <i1> [#uses=1] %tmp24 = xor i1 %tmp1, true ; <i1> [#uses=1] %or.cond8 = and i1 %tmp23, %tmp24 ; <i1> [#uses=1]later.[STORE SINKING]Store sinking: This code:void f (int n, int cond, int res) { int i; res = 0; for (i = 0; i < n; i++) if (cond) res ^= 234; }On this function GVN hoists the fully redundant value of res, but nothingmoves the store out. This gives us this code:bb: ; preds = %bb2, %entry %.rle = phi i32 [ 0, %entry ], [ %.rle6, %bb2 ] %i.05 = phi i32 [ 0, %entry ], [ %indvar.next, %bb2 ] %1 = load i32* %cond, align 4 %2 = icmp eq i32 %1, 0 br i1 %2, label %bb2, label %bb1bb1: ; preds = %bb %3 = xor i32 %.rle, 234 store i32 %3, i32* %res, align 4 br label %bb2bb2: ; preds = %bb, %bb1 %.rle6 = phi i32 [ %3, %bb1 ], [ %.rle, %bb ] %indvar.next = add i32 %i.05, 1 %exitcond = icmp eq i32 %indvar.next, %n br i1 %exitcond, label %return, label %bbDSE should sink partially dead stores to get the store out of the loop.Here's another partial dead case:http:Scalar PRE hoists the mul in the common block up to the else:int test (int a, int b, int c, int g) { int d, e; if (a) d = b * c; else d = b - c; e = b * c + g; return d + e;}It would be better to do the mul once to reduce codesize above the if.This is GCC PR38204.This simple function from 179.art:int winner, numf2s;struct { double y; int reset; } Y;void find_match() { int i; winner = 0; for (i=0;i<numf2s;i++) if (Y[i].y > Y[winner].y) winner =i;}Compiles into (with clang TBAA):for.body: ; preds = %for.inc, %bb.nph %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.inc ] %i.01718 = phi i32 [ 0, %bb.nph ], [ %i.01719, %for.inc ] %tmp4 = getelementptr inbounds %struct.anon %tmp3, i64 %indvar, i32 0 %tmp5 = load double* %tmp4, align 8, !tbaa !4 %idxprom7 = sext i32 %i.01718 to i64 %tmp10 = getelementptr inbounds %struct.anon* %tmp3, i64 %idxprom7, i32 0 %tmp11 = load double* %tmp10, align 8, !tbaa !4 %cmp12 = fcmp ogt double %tmp5, %tmp11 br i1 %cmp12, label %if.then, label %for.incif.then: ; preds = %for.body %i.017 = trunc i64 %indvar to i32 br label %for.incfor.inc: ; preds = %for.body, %if.then %i.01719 = phi i32 [ %i.01718, %for.body ], [ %i.017, %if.then ] %indvar.next = add i64 %indvar, 1 %exitcond = icmp eq i64 %indvar.next, %tmp22 br i1 %exitcond, label %for.cond.for.end_crit_edge, label %for.bodyIt is good that we hoisted the reloads of numf2's, and Y out of the loop andsunk the store to winner out.However, this is awful on several levels: the conditional truncate in the loop(-indvars at fault? why can't we completely promote the IV to i64?).Beyond that, we have a partially redundant load in the loop: if "winner" (aka %i.01718) isn't updated, we reload Y[winner].y the next time through the loop.Similarly, the addressing that feeds it (including the sext) is redundant. Inthe end we get this generated assembly:LBB0_2: ## %for.body ## =>This Inner Loop Header: Depth=1 movsd (%rdi), %xmm0 movslq %edx, %r8 shlq $4, %r8 ucomisd (%rcx,%r8), %xmm0 jbe LBB0_4 movl %esi, %edxLBB0_4: ## %for.inc addq $16, %rdi incq %rsi cmpq %rsi, %rax jne LBB0_2All things considered this isn't too bad, but we shouldn't need the movslq orthe shlq instruction, or the load folded into ucomisd every time through theloop.On an x86-specific topic, if the loop can't be restructure, the movl should be acmov.[STORE SINKING]GCC PR37810 is an interesting case where we should sink load/store reloadinto the if block and outside the loop, so we don't reload/store it on thenon-call path.for () { P += 1; if () call(); else ...->tmp = Pfor () { tmp += 1; if () { P = tmp; call(); tmp = P; } else ...}P = tmp;We now hoist the reload after the call (Transforms/GVN/lpre-call-wrap.ll), butwe don't sink the store. We need partially dead store sinking.[LOAD PRE CRIT EDGE SPLITTING]GCC PR37166: Sinking of loads prevents SROA'ing the "g" struct on the stackleading to excess stack traffic. This could be handled by GVN with some crazysymbolic phi translation. The code we get looks like (g is on the stack):bb2: ; preds = %bb1.. %9 = getelementptr %struct.f %g, i32 0, i32 0 store i32 %8, i32* %9, align bel %bb3bb3: ; preds = %bb1, %bb2, %bb %c_addr.0 = phi %struct.f* [ %g, %bb2 ], [ %c, %bb ], [ %c, %bb1 ] %b_addr.0 = phi %struct.f* [ %b, %bb2 ], [ %g, %bb ], [ %b, %bb1 ] %10 = getelementptr %struct.f* %c_addr.0, i32 0, i32 0 %11 = load i32* %10, align 4%11 is partially redundant, an in BB2 it should have the value %8.GCC PR33344 and PR35287 are similar cases.[LOAD PRE]There are many load PRE testcases in testsuite/gcc.dg/tree-ssa/loadpre* in theGCC testsuite, ones we don't get yet are (checked through loadpre25):[CRIT EDGE BREAKING]predcom-4.c[PRE OF READONLY CALL]loadpre5.c[TURN SELECT INTO BRANCH]loadpre14.c loadpre15.c actually a conditional increment: loadpre18.c loadpre19.c[LOAD PRE / STORE SINKING / SPEC HACK]This is a chunk of code from 456.hmmer:int f(int M, int mc, int mpp, int tpmm, int ip, int tpim, int dpp, int tpdm, int xmb, int bp, int ms) { int k, sc; for (k = 1; k <= M; k++) { mc[k] = mpp[k-1] + tpmm[k-1]; if ((sc = ip[k-1] + tpim[k-1]) > mc[k]) mc[k] = sc; if ((sc = dpp[k-1] + tpdm[k-1]) > mc[k]) mc[k] = sc; if ((sc = xmb + bp[k]) > mc[k]) mc[k] = sc; mc[k] += ms[k]; }}It is very profitable for this benchmark to turn the conditional stores to mc[k]into a conditional move (select instr in IR) and allow the final store to do thestore. See GCC PR27313 for more details. Note that this is valid to xform evenwith the new C++ memory model, since mc[k] is previously loaded and laterstored.[SCALAR PRE]There are many PRE testcases in testsuite/gcc.dg/tree-ssa/ssa-pre-.c in theGCC testsuite.There are some interesting cases in testsuite/gcc.dg/tree-ssa/pred-comm* in theGCC testsuite. For example, we get the first example in predcom-1.c, but miss the second one:unsigned fib[1000];unsigned avg[1000];__attribute__ ((noinline))void count_averages(int n) { int i; for (i = 1; i < n; i++) avg[i] = (((unsigned long) fib[i - 1] + fib[i] + fib[i + 1]) / 3) & 0xffff;}which compiles into two loads instead of one in the loop.predcom-2.c is the same as predcom-1.cpredcom-3.c is very similar but needs loads feeding each other instead ofstore->load.[ALIAS ANALYSIS]Type based alias analysis:http:We should do better analysis of posix_memalign. At the least it shouldno-capture its pointer argument, at best, we should know that the out-valueresult doesn't point to anything (like malloc). One example of this is inSingleSource/Benchmarks/Misc/dt.cInteresting missed case because of control flow flattening (should be 2 loads):http:With: llvm-gcc t2.c -S -o - -O0 -emit-llvm \| llvm-as \| opt -mem2reg -gvn -instcombine \| llvm-diswe miss it because we need 1) CRIT EDGE 2) MULTIPLE DIFFERENTVALS PRODUCED BY ONE BLOCK OVER DIFFERENT PATHShttp:We could eliminate the branch condition here, loading from null is undefined:struct S { int w, x, y, z; };struct T { int r; struct S s; };void bar (struct S, int);void foo (int a, struct T b){ struct S c = 0; if (a) c = &b.s; bar (c, a);}simplifylibcalls should do several optimizations for strspn/strcspn:strcspn(x, "a") -> inlined loop for up to	letters (similarly for strspn)

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into	memcpy (GCC PR47917) char buf1[6]

Variables
instcombine should handle this C2 when and C2 are unsigned Similarly for udiv and signed operands Currently InstCombine avoids this transform but will do it when the signs of the operands and the sign of the divide match See the FIXME in InstructionCombining cpp in the visitSetCondInst method after the switch case for Instruction::UDiv(around line 4447) for more details. The SingleSource/Benchmarks/Shootout-C++/hash and hash2 tests have examples of this const ruct.[LOOP OPTIMIZATION] SingleSource/Benchmarks/Misc/dt.c shows several interesting optimization opportunities in its double_array_divs_variable function typedef unsigned long long	U64

Target Independent	Opportunities

Target Independent unsigned int	b

	i

into	__pad0__

This would be a win on	ppc32

This would be a win on but not x86 or ppc64	Shrink

This would be a win on but not x86 or ppc64 Reassociate should turn things	like

into llvm powi	calls

into llvm powi allowing the code generator to produce balanced multiplication trees	First

into llvm powi allowing the code generator to produce balanced multiplication trees the intrinsic needs to be extended to support	integers

into llvm powi allowing the code generator to produce balanced multiplication trees the intrinsic needs to be extended to support and second the code generator needs to be enhanced to lower these to multiplication trees Interesting testcase for add shift mul	reassoc

into llvm powi allowing the code generator to produce balanced multiplication trees the intrinsic needs to be extended to support and second the code generator needs to be enhanced to lower these to multiplication trees Interesting testcase for add shift mul int	y

This is blocked on not handling X X X which is the same number of multiplies and is	canonical

This is blocked on not handling X X X which is the same number of multiplies and is because the *X has multiple uses Here s a simple	example

This is blocked on not handling X X X which is the same number of multiplies and is because the X has multiple uses Here s a simple X1	C = mul i32 %B

This is blocked on not handling X X X which is the same number of multiplies and is because the *X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC	PR16157

This is blocked on not handling X X X which is the same number of multiplies and is because the *X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC	a1

This is blocked on not handling X X X which is the same number of multiplies and is because the *X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC	a2

This is blocked on not handling X X X which is the same number of multiplies and is because the *X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC	a3

This is blocked on not handling X X X which is the same number of multiplies and is because the *X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC	a4

int	b0

int	b1

int	b2

int	b3

int	b4

This requires reassociating to forms of expressions that are already	available

This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian	systems

This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian int *	l { return memcmp(j,l,4)

this could be done in SelectionDAGISel	cpp

this could be done in SelectionDAGISel along with other special	cases

this could be done in SelectionDAGISel along with other special	for

this could be done in SelectionDAGISel along with other special bytes It would be nice to revert this	patch

Add support for conditional	increments

Add support for conditional and other related patterns Instead	of

Add support for conditional and other related patterns Instead eax	cmpl

Add support for conditional and other related patterns Instead eax eax je LBB16_2	LBB16_1

Add support for conditional and other related patterns Instead eax eax je LBB16_2 eax edi	sbbl

Add support for conditional and other related patterns Instead eax eax je LBB16_2 eax edi eax movl	eax

Add support for conditional and other related patterns Instead eax eax je LBB16_2 eax edi eax movl _foo	Combine

Doing so could allow SROA of the destination pointers See	also

i< reg->	size

	else

We don t delete this output free	loop

This should be recognized as	CLZ

	return

instcombine should handle this	transform

instcombine should handle this C2 when	X

instcombine should handle this C2 when	C1

Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On	x86

Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On this means we use one extra register for the function when effective_addr2 is declared as U64 than when it is declared U32 PHI Slicing could be extended to do this Tail call elim should be more	aggressive

Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On this means we use one extra register for the function when effective_addr2 is declared as U64 than when it is declared U32 PHI Slicing could be extended to do this Tail call elim should be more checking to see if the call is followed by an uncond branch to an exit	block

instruction into the terminating blocks because there was other	code

optimized out of the function after the taildup	happened

RUN	__pad1__

RUN< i32 >	tmp = icmp ne i32 %tmp.1

RUN< i32 >< i1 > br i1 label	then

	preds

then	result = phi i32 [ 0, %else.0 ]

then ret i32 result Tail recursion elimination should	handle

	Also

multiplies can be turned into SHL	s

multiplies can be turned into SHL so they should be handled as if they were associative return like	this

RUN	__pad2__

< i32 > tmp	foo = call i32 @foo( i32* %x )

We should investigate an instruction sinking pass Consider this silly example in pic	mode

we compile this	to

we compile this esp call L1 $pb L1	$pb

we compile this esp call L1 $pb L1 esp je LBB1_2	LBB1_1

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret	LBB1_2

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the	assertion

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of	arguments

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a	function

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this	case

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this whole function isel would also handle this Investigate lowering of sparse switch statements into perfect hash	tables

bool	Control

bool	Shift

bool	Alt

THotKey	m_HotKey

Clang compiles this	into

Clang compiles this	i8

Clang compiles this	i64

Clang compiles this	i32

Clang compiles this i1	false = getelementptr [8 x i64]* %input

Clang compiles this i1 i64 store i64	align = getelementptr [8 x i64]* %input

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps	xmm0

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp	movq

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s	http

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret	int

Unrolling by would eliminate the &in both	copies

Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various	targets

Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including	ppc

Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On	X86

Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On we miss a bunch of rotate by variable cases because the rotate matching code in dag combine doesn t look through truncates aggressively enough Here are some testcases reduces from GCC	PR17886

compiles	shl5 = shl i32 %conv

compiles	shl9 = shl i32 %conv

compiles	or = or i32 %shl9

compiles conv	or6 = or i32 %or

compiles conv shl5	or10 = or i32 %or6

compiles conv shl5 shl ret i32 or10 it would be better	as

aka	__pad3__

aka conv or ret i32 or6 or even i depending on the speed of the multiplier The best way to handle this is to canonicalize it to a multiply in IR and have codegen handle lowering multiplies to shifts on cpus where shifts are faster We do a number of simplifications in simplify libcalls to strength reduce standard library	functions

This is equivalent to the	following

The same transformation can work with an even modulo with the addition of a	rotate

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports	rotates

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports	though

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality	comparisons

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for	n

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for the first function produces better code on X86 From GCC	Bug

This should optimize to	x

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into	buf2 [6]

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into	buf3 [4]

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into	buf4 [4]

Macro Definition Documentation

◆ PMD_MASK

#define PMD_MASK (~((1UL << 23) - 1))

Function Documentation

◆ a() [1/5]

Should combine to a* Currently not optimized with clang emit llvm bc opt O3 unsigned a ( char * x )

Definition at line 883 of file README.txt.

◆ a() [2/5]

This should optimize to or at least something sane Currently not optimized with clang emit llvm bc opt O3 int a	(	int	a,
		int	b,
		int	c
	)

Definition at line 853 of file README.txt.

◆ a() [3/5]

Should fold to a&& b c Currently not optimized with clang emit llvm bc opt O3 int a ( int x )

Definition at line 859 of file README.txt.

◆ a() [4/5]

Should combine to x& Currently not optimized with clang emit llvm bc opt O3 unsigned a ( unsigned a )

Definition at line 877 of file README.txt.

◆ a() [5/5]

There s an unnecessary zext in the generated code with clang emit llvm bc opt O3 unsigned a ( unsigned long long x )

Definition at line 889 of file README.txt.

References x.

◆ bar()

<i32> ret i32 tmp foo define i32 bar ( i32 *% x )

Definition at line 387 of file README.txt.

References call(), entry, foo, i32, ret(), uses, and x.

◆ bit()

This sort of thing should be added to the loop idiom pass These should turn into single bit ( unaligned? ) const

Definition at line 249 of file README.txt.

◆ f()

void f ( )

Definition at line 85 of file README.txt.

References a1, a2, a3, a4, b1, b2, b3, and b4.

◆ f6()

unsigned long long f6	(	unsigned long long	x,
		unsigned long long	y,
		int	z
	)

Definition at line 575 of file README.txt.

◆ finite()

We don t delete this output free because trip count analysis doesn t realize that it is finite	(	if it were	infinite,
		it would be	undefined
	)

Definition at line 206 of file README.txt.

◆ foo()

int foo	(	int	z,
		int	n
	)

Definition at line 64 of file README.txt.

References bar, n, and z.

◆ for() [1/2]

for	(	i	= `...;++i`,
		tmp+	= `tmp`
	)

◆ for() [2/2]

for ( )

◆ g()

Should combine to* unsigned x& Currently not optimized with clang emit llvm bc opt O3 int g ( int x )

Definition at line 895 of file README.txt.

References x.

◆ GetHotKey()

THotKey GetHotKey ( )

Definition at line 470 of file README.txt.

References m_HotKey.

◆ h()

int h	(	int *	j,
		int *	l
	)

Definition at line 101 of file README.txt.

◆ hypot()

The legalization code for mul with overflow needs to be made more robust before this can be implemented though Get the C front end to expand hypot	(	x	,
		y
	)		-> llvm.sqrt(x x+y y) when errno and precision don 't matter(ffastmath). Misc/mandel will like this. :) This isn 't safe in general, even on darwin. See the libm implementation of hypot for examples(which special case when x/y are exactly zero to get signed zeros etc right). On targets with expensive 64-bit multiply, we could LSR this:for(i=...

◆ if() [1/2]

if ( )

Definition at line 176 of file README.txt.

◆ if() [2/2]

if ( x = =3 )

pure virtual

◆ instcombine()

but this requires TBAA This isn t recognized as bswap by instcombine	(	yes	,
		it really is	bswap
	)

Definition at line 191 of file README.txt.

◆ into()

into ( -m64 -O3 -fno-exceptions -static -fomit-frame- pointer )

Definition at line 472 of file README.txt.

References foo, and input.

◆ is()

This is equivalent to the where is the multiplicative inverse and is ( (2^32) - 1 )

Definition at line 672 of file README.txt.

References n.

◆ j()

return j ( j<< 16 )

Referenced by AnalyzeArguments(), llvm::analyzeArguments(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::PBQP::applyR1(), llvm::PBQP::applyR2(), llvm::SwitchCG::SwitchLowering::buildBitTests(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::LoopVectorizationCostModel::calculateRegisterUsage(), canLowerByDroppingElements(), CanMergeParamLoadStoresStartingAt(), CollectOpsToWiden(), combineBasicSADPattern(), combineVPDPBUSDPattern(), CompactSwizzlableVector(), llvm::EHStreamer::computeActionsTable(), llvm::EHStreamer::computePadMap(), ComputePTXValueVTs(), computeZeroableShuffleElements(), concatSubVector(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::IntervalMapImpl::NodeBase< std::pair< IndexT, IndexT >, char, N >::copy(), llvm::createBitMaskForGaps(), llvm::createInterleaveMask(), llvm::createReplicatedMask(), llvm::DecodeSubVectorBroadcast(), detectAVGPattern(), llvm::DistributeRange(), EltsFromConsecutiveLoads(), llvm::AsmPrinter::emitConstantPool(), llvm::encodeBase64(), llvm::IntervalMapImpl::NodeBase< std::pair< IndexT, IndexT >, char, N >::erase(), llvm::LegalizerHelper::fewerElementsVectorMerge(), llvm::LegalizerHelper::fewerElementsVectorPhi(), llvm::UnwindOpcodeAssembler::Finalize(), llvm::SwitchCG::SwitchLowering::findBitTestClusters(), FindInOperandList(), llvm::SwitchCG::SwitchLowering::findJumpTables(), llvm::RecordRecTy::get(), llvm::ScalarEvolution::getAddExpr(), llvm::HexagonMCInstrInfo::getDuplexPossibilties(), getFauxShuffleMask(), llvm::MachineFunction::getFilterIDFor(), getPSHUFShuffleMask(), llvm::GetReturnInfo(), llvm::getShuffleReduction(), getTargetConstantBitsFromNode(), GroupByComplexity(), llvm::CallLowering::handleAssignments(), llvm::BuildVectorSDNode::isConstantSplat(), isHopBuildVector(), isHorizontalBinOp(), llvm::R600InstrInfo::isLegalUpTo(), isMultiLaneShuffleMask(), isNByteElemShuffleMask(), IsSafeAndProfitableToMove(), llvm::PPC::isSplatShuffleMask(), isUZP_v_undef_Mask(), isVMerge(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), KnuthDiv(), LowerBITREVERSE_XOP(), llvm::LoongArchTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::AArch64TargetLowering::lowerInterleavedStore(), llvm::ARMTargetLowering::lowerInterleavedStore(), LowerMUL(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerV16I8Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_SHF(), LowervXi8MulWithUNPCK(), match1BitShuffleAsKSHIFT(), matchShuffleAsBitRotate(), matchShuffleAsShift(), llvm::CombinerHelper::matchTruncStoreMerge(), llvm::PBQP::RegAlloc::MatrixMetadata::MatrixMetadata(), llvm::IntervalMapImpl::NodeBase< std::pair< IndexT, IndexT >, char, N >::moveLeft(), llvm::IntervalMapImpl::NodeBase< std::pair< IndexT, IndexT >, char, N >::moveRight(), llvm::LegalizerHelper::narrowScalar(), llvm::LiveRange::overlapsFrom(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::cl::generic_parser_base::printGenericOptionDiff(), resolveTargetShuffleInputsAndMask(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::MachineFunction::tidyLandingPads(), tryCombineToBSL(), llvm::LegalizationArtifactCombiner::tryCombineUnmergeValues(), umul_ov(), llvm::UnrollLoop(), llvm::SelectionDAG::UnrollVectorOp(), llvm::InstCombinerImpl::visitLandingPadInst(), and llvm::Interpreter::visitShuffleVectorInst().

◆ letters()

Should combine to x<= 9" (the sub has nsw). Currently notoptimized with "clang -emit-llvm-bc | opt -O3".int g(int x) { return (x + 10) < 0; }Should combine to "x < -10" (the add has nsw). Currently notoptimized with "clang -emit-llvm-bc | opt -O3".int f(int i, int j) { return i < j + 1; }int g(int i, int j) { return j > i - 1; }Should combine to "i <= j" (the add/sub has nsw). Currently notoptimized with "clang -emit-llvm-bc | opt -O3".unsigned f(unsigned x) { return ((x & 7) + 1) & 15; }The & 15 part should be optimized away, it doesn't change the result. Currentlynot optimized with "clang -emit-llvm-bc | opt -O3".This was noticed in the entryblock for grokdeclarator in 403.gcc: %tmp = icmp eq i32 %decl_context, 4 %decl_context_addr.0 = select i1 %tmp, i32 3, i32 %decl_context %tmp1 = icmp eq i32 %decl_context_addr.0, 1 %decl_context_addr.1 = select i1 %tmp1, i32 0, i32 %decl_context_addr.0tmp1 should be simplified to something like: (!tmp || decl_context == 1)This allows recursive simplifications, tmp1 is used all over the place inthe function, e.g. by: %tmp23 = icmp eq i32 %decl_context_addr.1, 0 ; <i1> [#uses=1] %tmp24 = xor i1 %tmp1, true ; <i1> [#uses=1] %or.cond8 = and i1 %tmp23, %tmp24 ; <i1> [#uses=1]later.[STORE SINKING]Store sinking: This code:void f (int n, int *cond, int *res) { int i; *res = 0; for (i = 0; i < n; i++) if (*cond) *res ^= 234; }On this function GVN hoists the fully redundant value of *res, but nothingmoves the store out. This gives us this code:bb: ; preds = %bb2, %entry %.rle = phi i32 [ 0, %entry ], [ %.rle6, %bb2 ] %i.05 = phi i32 [ 0, %entry ], [ %indvar.next, %bb2 ] %1 = load i32* %cond, align 4 %2 = icmp eq i32 %1, 0 br i1 %2, label %bb2, label %bb1bb1: ; preds = %bb %3 = xor i32 %.rle, 234 store i32 %3, i32* %res, align 4 br label %bb2bb2: ; preds = %bb, %bb1 %.rle6 = phi i32 [ %3, %bb1 ], [ %.rle, %bb ] %indvar.next = add i32 %i.05, 1 %exitcond = icmp eq i32 %indvar.next, %n br i1 %exitcond, label %return, label %bbDSE should sink partially dead stores to get the store out of the loop.Here's another partial dead case:http:Scalar PRE hoists the mul in the common block up to the else:int test (int a, int b, int c, int g) { int d, e; if (a) d = b * c; else d = b - c; e = b * c + g; return d + e;}It would be better to do the mul once to reduce codesize above the if.This is GCC PR38204.This simple function from 179.art:int winner, numf2s;struct { double y; int reset; } *Y;void find_match() { int i; winner = 0; for (i=0;i<numf2s;i++) if (Y[i].y > Y[winner].y) winner =i;}Compiles into (with clang TBAA):for.body: ; preds = %for.inc, %bb.nph %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %for.inc ] %i.01718 = phi i32 [ 0, %bb.nph ], [ %i.01719, %for.inc ] %tmp4 = getelementptr inbounds %struct.anon* %tmp3, i64 %indvar, i32 0 %tmp5 = load double* %tmp4, align 8, !tbaa !4 %idxprom7 = sext i32 %i.01718 to i64 %tmp10 = getelementptr inbounds %struct.anon* %tmp3, i64 %idxprom7, i32 0 %tmp11 = load double* %tmp10, align 8, !tbaa !4 %cmp12 = fcmp ogt double %tmp5, %tmp11 br i1 %cmp12, label %if.then, label %for.incif.then: ; preds = %for.body %i.017 = trunc i64 %indvar to i32 br label %for.incfor.inc: ; preds = %for.body, %if.then %i.01719 = phi i32 [ %i.01718, %for.body ], [ %i.017, %if.then ] %indvar.next = add i64 %indvar, 1 %exitcond = icmp eq i64 %indvar.next, %tmp22 br i1 %exitcond, label %for.cond.for.end_crit_edge, label %for.bodyIt is good that we hoisted the reloads of numf2's, and Y out of the loop andsunk the store to winner out.However, this is awful on several levels: the conditional truncate in the loop(-indvars at fault? why can't we completely promote the IV to i64?).Beyond that, we have a partially redundant load in the loop: if "winner" (aka %i.01718) isn't updated, we reload Y[winner].y the next time through the loop.Similarly, the addressing that feeds it (including the sext) is redundant. Inthe end we get this generated assembly:LBB0_2: ## %for.body ## =>This Inner Loop Header: Depth=1 movsd (%rdi), %xmm0 movslq %edx, %r8 shlq $4, %r8 ucomisd (%rcx,%r8), %xmm0 jbe LBB0_4 movl %esi, %edxLBB0_4: ## %for.inc addq $16, %rdi incq %rsi cmpq %rsi, %rax jne LBB0_2All things considered this isn't too bad, but we shouldn't need the movslq orthe shlq instruction, or the load folded into ucomisd every time through theloop.On an x86-specific topic, if the loop can't be restructure, the movl should be acmov.[STORE SINKING]GCC PR37810 is an interesting case where we should sink load/store reloadinto the if block and outside the loop, so we don't reload/store it on thenon-call path.for () { *P += 1; if () call(); else ...->tmp = *Pfor () { tmp += 1; if () { *P = tmp; call(); tmp = *P; } else ...}*P = tmp;We now hoist the reload after the call (Transforms/GVN/lpre-call-wrap.ll), butwe don't sink the store. We need partially dead store sinking.[LOAD PRE CRIT EDGE SPLITTING]GCC PR37166: Sinking of loads prevents SROA'ing the "g" struct on the stackleading to excess stack traffic. This could be handled by GVN with some crazysymbolic phi translation. The code we get looks like (g is on the stack):bb2: ; preds = %bb1.. %9 = getelementptr %struct.f* %g, i32 0, i32 0 store i32 %8, i32* %9, align bel %bb3bb3: ; preds = %bb1, %bb2, %bb %c_addr.0 = phi %struct.f* [ %g, %bb2 ], [ %c, %bb ], [ %c, %bb1 ] %b_addr.0 = phi %struct.f* [ %b, %bb2 ], [ %g, %bb ], [ %b, %bb1 ] %10 = getelementptr %struct.f* %c_addr.0, i32 0, i32 0 %11 = load i32* %10, align 4%11 is partially redundant, an in BB2 it should have the value %8.GCC PR33344 and PR35287 are similar cases.[LOAD PRE]There are many load PRE testcases in testsuite/gcc.dg/tree-ssa/loadpre* in theGCC testsuite, ones we don't get yet are (checked through loadpre25):[CRIT EDGE BREAKING]predcom-4.c[PRE OF READONLY CALL]loadpre5.c[TURN SELECT INTO BRANCH]loadpre14.c loadpre15.c actually a conditional increment: loadpre18.c loadpre19.c[LOAD PRE / STORE SINKING / SPEC HACK]This is a chunk of code from 456.hmmer:int f(int M, int *mc, int *mpp, int *tpmm, int *ip, int *tpim, int *dpp, int *tpdm, int xmb, int *bp, int *ms) { int k, sc; for (k = 1; k <= M; k++) { mc[k] = mpp[k-1] + tpmm[k-1]; if ((sc = ip[k-1] + tpim[k-1]) > mc[k]) mc[k] = sc; if ((sc = dpp[k-1] + tpdm[k-1]) > mc[k]) mc[k] = sc; if ((sc = xmb + bp[k]) > mc[k]) mc[k] = sc; mc[k] += ms[k]; }}It is very profitable for this benchmark to turn the conditional stores to mc[k]into a conditional move (select instr in IR) and allow the final store to do thestore. See GCC PR27313 for more details. Note that this is valid to xform evenwith the new C++ memory model, since mc[k] is previously loaded and laterstored.[SCALAR PRE]There are many PRE testcases in testsuite/gcc.dg/tree-ssa/ssa-pre-*.c in theGCC testsuite.There are some interesting cases in testsuite/gcc.dg/tree-ssa/pred-comm* in theGCC testsuite. For example, we get the first example in predcom-1.c, but miss the second one:unsigned fib[1000];unsigned avg[1000];__attribute__ ((noinline))void count_averages(int n) { int i; for (i = 1; i < n; i++) avg[i] = (((unsigned long) fib[i - 1] + fib[i] + fib[i + 1]) / 3) & 0xffff;}which compiles into two loads instead of one in the loop.predcom-2.c is the same as predcom-1.cpredcom-3.c is very similar but needs loads feeding each other instead ofstore->load.[ALIAS ANALYSIS]Type based alias analysis:http:We should do better analysis of posix_memalign. At the least it shouldno-capture its pointer argument, at best, we should know that the out-valueresult doesn't point to anything (like malloc). One example of this is inSingleSource/Benchmarks/Misc/dt.cInteresting missed case because of control flow flattening (should be 2 loads):http:With: llvm-gcc t2.c -S -o - -O0 -emit-llvm | llvm-as | opt -mem2reg -gvn -instcombine | llvm-diswe miss it because we need 1) CRIT EDGE 2) MULTIPLE DIFFERENTVALS PRODUCED BY ONE BLOCK OVER DIFFERENT PATHShttp:We could eliminate the branch condition here, loading from null is undefined:struct S { int w, x, y, z; };struct T { int r; struct S s; };void bar (struct S, int);void foo (int a, struct T b){ struct S *c = 0; if (a) c = &b.s; bar (*c, a);}simplifylibcalls should do several optimizations for strspn/strcspn:strcspn(x, "a") -> inlined loop for up to letters ( similarly for strspn )

Definition at line 1233 of file README.txt.

◆ loops()

The loop unroller should partially unroll loops ( instead of peeling them )

Definition at line 544 of file README.txt.

◆ memcpy() [1/2]

aka conv or ret i32 or6 or even i depending on the speed of the multiplier The best way to handle this is to canonicalize it to a multiply in IR and have codegen handle lowering multiplies to shifts on cpus where shifts are faster We do a number of simplifications in simplify libcalls to strength reduce standard library but we don t currently merge them together For it is useful to merge memcpy	(	a	,
		b	,
		strlen(b)
	)		-> strcpy. This can only be done safely if "b" isn't modified between the strlen and memcpy of course. We compile this program: (from GCC PR11680) http: Into code that runs the same speed in fast/slow modes, but both modes run 2x slower than when compile with GCC (either 4.0 or 4.2): $ llvm-g++ perf.cpp -O3 -fno-exceptions $ time ./a.out fast 1.821u 0.003s 0:01.82 100.0% 0+0k 0+0io 0pf+0w $ g++ perf.cpp -O3 -fno-exceptions $ time ./a.out fast 0.821u 0.001s 0:00.82 100.0% 0+0k 0+0io 0pf+0w It looks like we are making the same inlining decisions, so this may be raw codegen badness or something else (haven't investigated). Divisibility by constant can be simplified (according to GCC PR12849) from being a mulhi to being a mul lo (cheaper). Testcase: void bar(unsigned n)

Definition at line 639 of file README.txt.

References n.

◆ memcpy() [2/2]

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into memcpy ( GCC PR47917 )

◆ popcount() [1/2]

These idioms should be recognized as popcount ( see PR1488 )

Definition at line 219 of file README.txt.

◆ popcount() [2/2]

unsigned int popcount ( unsigned int input )

Definition at line 228 of file README.txt.

◆ pow2m1()

return* pow2m1 ( n - 1 )

◆ powi()

This is blocked on not handling X* X* X powi	(	X	,
		3
	)

Referenced by llvm::canConstantFoldCallTo(), cannotBeOrderedLessThanZeroImpl(), createPowWithIntegerExponent(), foldFDivPowDivisor(), llvm::BasicTTIImplBase< AMDGPUTTIImpl >::getIntrinsicInstrCost(), llvm::ARMTTIImpl::isLoweredToCall(), llvm::isTriviallyVectorizable(), llvm::isVectorIntrinsicWithOverloadTypeAtArg(), llvm::isVectorIntrinsicWithScalarOpAtArg(), simplifyBinaryIntrinsic(), llvm::InstCombinerImpl::visitCallInst(), and llvm::InstCombinerImpl::visitFMul().

◆ read_16_be()

unsigned short read_16_be ( const unsigned char * adr )

Definition at line 255 of file README.txt.

◆ setlt()

This would be a win on but not x86 or ppc64 setlt ( loadi8 Phi )

◆ sincosf()

float sincosf	(	float	x,
		float *	sin,
		float *	cos
	)

◆ sincosl()

long double sincosl	(	long double	x,
		long double *	sin,
		long double *	cos
	)

◆ test()

int test	(	U32 *	inst,
		U64 *	regs
	)

Definition at line 301 of file README.txt.

◆ This()

This ( and similar related idioms )

Definition at line 592 of file README.txt.

Variable Documentation

◆ $pb

we compile this esp call L1 $pb L1 $pb

Definition at line 410 of file README.txt.

◆ pad0

into __pad0__

Definition at line 33 of file README.txt.

◆ pad1

RUN __pad1__

Definition at line 336 of file README.txt.

◆ pad2

RUN __pad2__

Definition at line 382 of file README.txt.

◆ pad3

aka __pad3__

Definition at line 624 of file README.txt.

◆ a1

This is blocked on not handling X* X* X which is the same number of multiplies and is because the* X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC a1

Definition at line 84 of file README.txt.

Referenced by f().

◆ a2

This is blocked on not handling X* X* X which is the same number of multiplies and is because the* X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC a2

Definition at line 84 of file README.txt.

Referenced by f().

◆ a3

This is blocked on not handling X* X* X which is the same number of multiplies and is because the* X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC a3

Definition at line 84 of file README.txt.

Referenced by f().

◆ a4

This is blocked on not handling X* X* X which is the same number of multiplies and is because the* X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC a4

Definition at line 84 of file README.txt.

Referenced by f().

◆ aggressive

Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On this means we use one extra register for the function when effective_addr2 is declared as U64 than when it is declared U32 PHI Slicing could be extended to do this Tail call elim should be more aggressive

Definition at line 326 of file README.txt.

◆ align

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 align = getelementptr [8 x i64]* %input

Definition at line 507 of file README.txt.

◆ also

Doing so could allow SROA of the destination pointers See also

Definition at line 166 of file README.txt.

◆ Also

Also

Definition at line 370 of file README.txt.

◆ Alt

bool Alt

Definition at line 468 of file README.txt.

Referenced by llvm::TargetLowering::SimplifyDemandedBits().

◆ arguments

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of arguments

Definition at line 425 of file README.txt.

◆ as

therefore end up llgh r3 lr r0 br r14 but truncating the load would lh r3 br r14 Functions ret i64 and ought to be implemented as

Definition at line 615 of file README.txt.

Referenced by llvm::ELFAttributeParser::printAttribute().

◆ assertion

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the assertion

Definition at line 422 of file README.txt.

◆ available

This requires reassociating to forms of expressions that are already available

Definition at line 92 of file README.txt.

◆ b

Add support for conditional and other related patterns Instead eax eax je LBB16_2 eax edi eax movl _foo b

Initial value:

{
 if ((unsigned long long)a*b>0xffffffff)
   exit(0)

Definition at line 8 of file README.txt.

◆ b0

int b0

◆ b1

int b1

Definition at line 84 of file README.txt.

Referenced by f(), and llvm::findMaximalSubpartOfIllFormedUTF8Sequence().

◆ b2

int b2

Definition at line 84 of file README.txt.

Referenced by EmitUnwindCode(), f(), and llvm::findMaximalSubpartOfIllFormedUTF8Sequence().

◆ b3

int b3

Definition at line 84 of file README.txt.

Referenced by f(), and llvm::findMaximalSubpartOfIllFormedUTF8Sequence().

◆ b4

int b4

Definition at line 84 of file README.txt.

Referenced by f().

◆ block

Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On this means we use one extra register for the function when effective_addr2 is declared as U64 than when it is declared U32 PHI Slicing could be extended to do this Tail call elim should be more checking to see if the call is followed by an uncond branch to an exit block

Definition at line 329 of file README.txt.

◆ buf2

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into buf2[6]

Definition at line 1253 of file README.txt.

◆ buf3

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into buf3[4]

Definition at line 1253 of file README.txt.

◆ buf4

This should turn into a switch on the character See PR3253 for some notes on codegen hmmer apparently uses strcspn and strspn a lot omnetpp uses strspn simplifylibcalls should turn these snprintf idioms into buf4[4]

Definition at line 1253 of file README.txt.

◆ Bug

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for the first function produces better code on X86 From GCC Bug

Definition at line 763 of file README.txt.

◆ C

This is blocked on not handling X* X* X which is the same number of multiplies and is because the* X has multiple uses Here s a simple X1* C = mul i32 %B

Definition at line 75 of file README.txt.

Referenced by zero().

◆ C1

instcombine should handle this C2 when C1

Definition at line 263 of file README.txt.

◆ calls

into llvm powi calls

Definition at line 51 of file README.txt.

◆ canonical

This is blocked on not handling X* X* X which is the same number of multiplies and is canonical

Definition at line 70 of file README.txt.

◆ case

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this case

Definition at line 429 of file README.txt.

◆ cases

this could be done in SelectionDAGISel along with other special cases

Definition at line 103 of file README.txt.

◆ CLZ

This should be recognized as CLZ

Definition at line 238 of file README.txt.

Referenced by isSignExtendingOpW().

◆ cmpl

currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be eax cmpl

Definition at line 135 of file README.txt.

◆ code

instruction into the terminating blocks because there was other code

Definition at line 331 of file README.txt.

◆ Combine

Add support for conditional and other related patterns Instead eax eax je LBB16_2 eax edi eax movl _foo Combine

Definition at line 149 of file README.txt.

◆ comparisons

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality comparisons

Definition at line 685 of file README.txt.

◆ Control

bool Control

Definition at line 468 of file README.txt.

◆ copies

Unrolling by would eliminate the& in both copies

Definition at line 561 of file README.txt.

◆ cpp

this could be done in SelectionDAGISel cpp

Definition at line 103 of file README.txt.

◆ eax

currently compiles eax eax je LBB0_3 testl eax

Definition at line 145 of file README.txt.

Referenced by get_cpu_features().

◆ else

< i32 > br label return else

Initial value:

{
     for(i=0; i<reg->size; i++)
       reg->node[i].state ^= Res & 0xFFFFFFFF00000000ULL
   }
   
... which would only do one 32-bit XOR per loop iteration instead of two.
 
It would also be nice to recognize the reg->size doesn't alias reg->node[i]

Definition at line 179 of file README.txt.

◆ example

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for example

Definition at line 74 of file README.txt.

◆ false

Clang compiles this i1 false = getelementptr [8 x i64]* %input

Definition at line 505 of file README.txt.

◆ First

into llvm powi allowing the code generator to produce balanced multiplication trees First

Definition at line 54 of file README.txt.

◆ following

This is equivalent to the following

Definition at line 671 of file README.txt.

◆ foo

int foo = call i32 @foo( i32* %x )

Definition at line 383 of file README.txt.

Referenced by bar(), LiveDebugValues::MLocTracker::dump_mloc_map(), LiveDebugValues::InstrRefBasedLDV::dump_mloc_transfer(), and into().

◆ for

this could be done in SelectionDAGISel along with other special for

◆ function

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a function

Definition at line 427 of file README.txt.

◆ functions

aka conv or ret i32 or6 or even i depending on the speed of the multiplier The best way to handle this is to canonicalize it to a multiply in IR and have codegen handle lowering multiplies to shifts on cpus where shifts are faster We do a number of simplifications in simplify libcalls to strength reduce standard library functions

Definition at line 631 of file README.txt.

◆ handle

then ret i32 result Tail recursion elimination should handle

Definition at line 355 of file README.txt.

Referenced by llvm_orc_deregisterEHFrameSectionWrapper(), llvm_orc_registerEHFrameSectionWrapper(), llvm_orc_registerJITLoaderGDBAllocAction(), llvm_orc_registerJITLoaderGDBWrapper(), llvm::orc::rt_bootstrap::runAsIntFunctionWrapper(), llvm::orc::rt_bootstrap::runAsMainWrapper(), llvm::orc::rt_bootstrap::runAsVoidFunctionWrapper(), llvm::orc::rt_bootstrap::writeBuffersWrapper(), and llvm::orc::rt_bootstrap::writeUIntsWrapper().

◆ happened

optimized out of the function after the taildup happened

Definition at line 332 of file README.txt.

◆ http

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s http

Definition at line 532 of file README.txt.

◆ i

int i

Initial value:

{

x = 1ULL << i

Definition at line 29 of file README.txt.

◆ i32

Clang compiles this i32

Definition at line 504 of file README.txt.

◆ i64

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64

Definition at line 504 of file README.txt.

Referenced by getBaseWithOffsetUsingSplitOR(), and AMDGPUDAGToDAGISel::Select().

◆ i8

Clang compiles this i8

Definition at line 504 of file README.txt.

Referenced by AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), and to().

◆ increments

Add support for conditional increments

Definition at line 131 of file README.txt.

◆ int

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int

Definition at line 536 of file README.txt.

Referenced by llvm::pdb::DbiStreamBuilder::addDbgStream(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), analyzeLoopUnrollCost(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), BUCompareLatency(), CalculateTailCallSPDiff(), checkResourceLimit(), clusterSortPtrAccesses(), combineAddOfPMADDWD(), combineExtractWithShuffle(), combineShuffleOfScalars(), combineShuffleToVectorExtend(), combineTargetShuffle(), combineTruncationShuffle(), combineX86ShufflesRecursively(), llvm::ShuffleVectorInst::commuteShuffleMask(), CompareSCEVComplexity(), CompareValueComplexity(), completeEphemeralValues(), computeExcessPressureDelta(), computeFreeStackSlots(), ComputeImportForModule(), computeMaxPressureDelta(), constructDup(), llvm::detail::PopulationCounter< T, SizeOfT >::count(), llvm::detail::PopulationCounter< T, 8 >::count(), createShuffleMaskFromVSELECT(), llvm::MachineFrameInfo::CreateSpillStackObject(), llvm::MachineFrameInfo::CreateStackObject(), llvm::DecodeEXTRQIMask(), llvm::DecodeINSERTQIMask(), DecodeInsSize(), llvm::DecodeVPERM2X128Mask(), llvm::M68kRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::EmitAnyX86InstComments(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::SparcFrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), emitFrameOffsetAdj(), llvm::WebAssemblyAsmPrinter::EmitProducerInfo(), llvm::SparcFrameLowering::emitPrologue(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), llvm::pdb::DbiStreamBuilder::finalizeMsfLayout(), FoldIntToFPToInt(), llvm::InstCombinerImpl::foldItoFPtoI(), foldShuffleOfConcatUndefs(), foldTruncInsElt(), llvm::ARM_AM::getAM2Opc(), getARMIndexedAddressParts(), llvm::SlotTracker::getAttributeGroupSlot(), llvm::RISCVTTIImpl::getCastInstrCost(), getFauxShuffleMask(), llvm::SlotTracker::getGlobalSlot(), llvm::SlotTracker::getGUIDSlot(), llvm::ScoreboardHazardRecognizer::getHazardType(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::SlotTracker::getLocalSlot(), llvm::SlotTracker::getMetadataSlot(), llvm::SlotTracker::getModulePathSlot(), getMVEIndexedAddressParts(), llvm::logicalview::LVOperation::getOperandsCodeViewInfo(), llvm::logicalview::LVOperation::getOperandsDWARFInfo(), getOrCreateFrameHelper(), getShuffleComment(), getShuffleScalarElt(), getT2IndexedAddressParts(), getTargetConstantBitsFromNode(), llvm::SlotTracker::getTypeIdSlot(), llvm::RegPressureTracker::getUpwardPressureDelta(), handleIndirectSymViaGOTPCRel(), llvm::MachineInstr::hasComplexRegisterTies(), iJIT_NotifyEvent(), llvm::MachineFrameInfo::isFixedObjectIndex(), isKnownExactCastIntToFP(), llvm::SelectionDAG::isSplatValue(), IsValueFullyAvailableInBlock(), llvm::cfg::LegalizeUpdates(), lle_X_memset(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::MipsCallLowering::lowerFormalArguments(), LowerMULH(), lowerShuffleAsBroadcast(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), llvm::SelectionDAG::matchBinOpReduction(), llvm::operator<<(), AbstractManglingParser< ManglingParser< Alloc >, Alloc >::parseTemplateParamDecl(), partitionShuffleOfConcats(), llvm::SystemZConstantPoolValue::print(), llvm::MachineFrameInfo::print(), printBitField(), llvm::SparcInstPrinter::printCCOperand(), llvm::VEInstPrinter::printCCOperand(), llvm::printCompactDWARFExpr(), printField(), PrintHelpOptionList(), llvm::PPCInstPrinter::printImmZeroOperand(), llvm::PPCInstPrinter::printInst(), llvm::NVPTXInstPrinter::printLdStCode(), llvm::VEInstPrinter::printMImmOperand(), llvm::NVPTXInstPrinter::printMmaCode(), llvm::ScopedPrinter::printNumber(), llvm::SparcInstPrinter::printOperand(), llvm::VEInstPrinter::printRDOperand(), llvm::PPCInstPrinter::printS5ImmOperand(), llvm::PPCInstPrinter::printU1ImmOperand(), llvm::PPCInstPrinter::printU2ImmOperand(), llvm::PPCInstPrinter::printU3ImmOperand(), llvm::PPCInstPrinter::printU4ImmOperand(), llvm::PPCInstPrinter::printU5ImmOperand(), llvm::PPCInstPrinter::printU6ImmOperand(), llvm::PPCInstPrinter::printU7ImmOperand(), llvm::PPCInstPrinter::printU8ImmOperand(), llvm::readExponent(), llvm::AArch64FrameLowering::resolveFrameOffsetReference(), llvm::orc::SelfExecutorProcessControl::runAsIntFunction(), llvm::orc::SelfExecutorProcessControl::runAsMain(), llvm::orc::rt_bootstrap::runAsMainWrapper(), llvm::orc::SelfExecutorProcessControl::runAsVoidFunction(), llvm::MCJIT::runFunction(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::ImportedFunctionsInliningStatistics::setModuleInfo(), llvm::MachineOperand::setOffset(), llvm::GCNHazardRecognizer::ShouldPreferAnother(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::VETargetLowering::splitPackedLoadStore(), llvm::VETargetLowering::splitVectorOp(), llvm::Register::stackSlot2Index(), this(), and llvm::detail::IEEEFloat::toString().

◆ integers

into llvm powi allowing the code generator to produce balanced multiplication trees the intrinsic needs to be extended to support integers

Definition at line 54 of file README.txt.

◆ into

In fpstack this compiles into

Definition at line 504 of file README.txt.

◆ l

This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian int* l { return memcmp(j,l,4)

Definition at line 100 of file README.txt.

◆ LBB16_1

Add support for conditional and other related patterns Instead eax eax je LBB16_2 LBB16_1

Definition at line 142 of file README.txt.

◆ LBB1_1

we compile this esp call L1 $pb L1 esp je LBB1_2 LBB1_1

Definition at line 414 of file README.txt.

◆ LBB1_2

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret LBB1_2

Definition at line 420 of file README.txt.

◆ like

Where MAX_UNSIGNED state is a bit int On a bit platform it would be just so cool to turn it into something like

Definition at line 48 of file README.txt.

◆ loop

is twice as slow as this loop

Definition at line 205 of file README.txt.

◆ m_HotKey

THotKey m_HotKey

Referenced by GetHotKey().

◆ mode

We should investigate an instruction sinking pass Consider this silly example in pic mode

Definition at line 400 of file README.txt.

◆ movq

Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp movq

Definition at line 521 of file README.txt.

◆ n

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n

Definition at line 685 of file README.txt.

Referenced by llvm::IntervalMapImpl::adjustSiblingSizes(), appendToGlobalArray(), llvm::pointer_union_detail::bitsRequired(), llvm::ScheduleDAGInstrs::buildSchedGraph(), Choose(), CombineVLDDUP(), llvm::ComputeMappedEditDistance(), llvm::decodeSLEB128(), llvm::decodeULEB128(), llvm::IntervalMapImpl::distribute(), llvm::detail::indexed_accessor_range_base< DerivedT, std::pair< BaseT, ptrdiff_t >, T, T *, T & >::drop_back(), llvm::detail::indexed_accessor_range_base< DerivedT, std::pair< BaseT, ptrdiff_t >, T, T *, T & >::drop_front(), llvm::encodeBase64(), llvm::SpillPlacement::finish(), foo(), llvm::getAlign(), llvm::SpillPlacement::Node::getDissentingNeighbors(), llvm::DWARFContext::getInliningInfoForAddress(), llvm::HexagonMCCodeEmitter::getMachineOpValue(), llvm::getOclOrSpirvBuiltinDemangledName(), llvm::df_iterator< Inverse< T >, df_iterator_default_set< typename GraphTraits< T >::NodeRef >, External >::getPath(), llvm::SparcRegisterInfo::getReservedRegs(), llvm::X86RegisterInfo::getReservedRegs(), llvm::IndexedMap< unsigned, llvm::VirtReg2IndexFunctor >::grow(), handleSwitchExpect(), llvm::rdf::NodeAllocator::id(), llvm::IndexedMap< unsigned, llvm::VirtReg2IndexFunctor >::inBounds(), INITIALIZE_PASS(), llvm::yaml::ScalarTraits< MaybeAlign >::input(), is(), llvm::SpillPlacement::iterate(), KnuthDiv(), llvm_strlcpy(), LowerCTPOP(), llvm::BitTracker::RegisterCell::meet(), memcpy(), nch(), llvm::IntervalMapImpl::NodeRef::NodeRef(), llvm::iterator_facade_base< iterator, std::forward_iterator_tag, const entry >::operator+(), llvm::iterator_adaptor_base< const_succ_op_iterator, const_value_op_iterator, std::random_access_iterator_tag, const BasicBlock *, ptrdiff_t, const BasicBlock *, const BasicBlock * >::operator+=(), llvm::iterator_facade_base< iterator, std::forward_iterator_tag, const entry >::operator-(), llvm::iterator_adaptor_base< const_succ_op_iterator, const_value_op_iterator, std::random_access_iterator_tag, const BasicBlock *, ptrdiff_t, const BasicBlock *, const BasicBlock * >::operator-=(), llvm::operator<<(), llvm::IndexedMap< unsigned, llvm::VirtReg2IndexFunctor >::operator[](), llvm::SetVector< llvm::MCSection *, SmallVector< llvm::MCSection *, N >, SmallDenseSet< llvm::MCSection *, N > >::operator[](), llvm::iterator_facade_base< iterator, std::forward_iterator_tag, const entry >::operator[](), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), PerformVECTOR_SHUFFLECombine(), llvm::powerOf5(), llvm::HexagonInstrInfo::PredicateInstruction(), FloatLiteralImpl< Float >::printLeft(), llvm::ImutAVLFactory< ImutInfo >::recoverNodes(), llvm::BitTracker::RegisterCell::regify(), llvm::APInt::roundToDouble(), ScaleVectorOffset(), llvm::SpillPlacement::scanActiveBundles(), llvm::cl::Option::setNumAdditionalVals(), llvm::cl::list< DataType, StorageClass, ParserClass >::setNumAdditionalVals(), llvm::ARMFunctionInfo::setNumAlignedDPRCS2Regs(), llvm::IntervalMapImpl::NodeRef::setSize(), llvm::ImutAVLTree< ImutInfo >::size(), llvm::detail::indexed_accessor_range_base< DerivedT, std::pair< BaseT, ptrdiff_t >, T, T *, T & >::slice(), llvm::detail::indexed_accessor_range_base< DerivedT, std::pair< BaseT, ptrdiff_t >, T, T *, T & >::take_back(), llvm::detail::indexed_accessor_range_base< DerivedT, std::pair< BaseT, ptrdiff_t >, T, T *, T & >::take_front(), llvm::APInt::tcDivide(), llvm::APInt::tcExtract(), llvm::APInt::tcLSB(), llvm::APInt::tcMSB(), llvm::APInt::tcMultiplyPart(), TryCombineBaseUpdate(), llvm::writeUnsignedDecimal(), x(), and y().

◆ of

This is equivalent to the where is the multiplicative inverse of

Definition at line 134 of file README.txt.

◆ Opportunities

Target Independent Opportunities

Definition at line 8 of file README.txt.

◆ or

aka or = or i32 %shl9

Definition at line 606 of file README.txt.

◆ or10

compiles conv shl5 or10 = or i32 %or6

Definition at line 608 of file README.txt.

◆ or6

aka conv or6 = or i32 %or

Definition at line 607 of file README.txt.

◆ patch

this could be done in SelectionDAGISel along with other special bytes It would be nice to revert this patch

Definition at line 104 of file README.txt.

◆ ppc

Unrolling by would eliminate the& in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including ppc

Definition at line 567 of file README.txt.

◆ ppc32

This would be a win on ppc32

Definition at line 37 of file README.txt.

◆ PR16157

This is blocked on not handling X* X* X which is the same number of multiplies and is because the* X has multiple uses Here s a simple X1 B ret i32 C Reassociate should handle the example in GCC PR16157

Definition at line 84 of file README.txt.

◆ PR17886

Unrolling by would eliminate the& in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On we miss a bunch of rotate by variable cases because the rotate matching code in dag combine doesn t look through truncates aggressively enough Here are some testcases reduces from GCC PR17886

Definition at line 572 of file README.txt.

◆ preds

preds

Initial value:

= %entry

%tmp.5 = add i32 %a

Definition at line 340 of file README.txt.

Referenced by abort_gzip(), foo(), llvm::MIPatternMatch::m_all_of(), and llvm::MIPatternMatch::m_any_of().

◆ reassoc

into llvm powi allowing the code generator to produce balanced multiplication trees the intrinsic needs to be extended to support and second the code generator needs to be enhanced to lower these to multiplication trees Interesting testcase for add shift mul reassoc

Definition at line 61 of file README.txt.

◆ result

then result = phi i32 [ 0, %else.0 ]

Definition at line 355 of file README.txt.

◆ return

< i32 > br label return return

Definition at line 242 of file README.txt.

Referenced by llvm::object::MachOObjectFile::getVersionMinMajor(), llvm::object::MachOObjectFile::getVersionMinMinor(), llvm::performOptimizedStructLayout(), llvm::SparcInstPrinter::printOperand(), and llvm::SplitModule().

◆ rotate

The same transformation can work with an even modulo with the addition of a rotate

Definition at line 680 of file README.txt.

Referenced by DecodeNEONComplexLane64Instruction().

◆ rotates

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports rotates

Definition at line 681 of file README.txt.

◆ s

multiplies can be turned into SHL s

Definition at line 370 of file README.txt.

◆ sbbl

Add support for conditional and other related patterns Instead eax eax je LBB16_2 eax edi sbbl

Definition at line 144 of file README.txt.

◆ Shift

bool Shift

Definition at line 468 of file README.txt.

◆ shl5

aka conv shl5 = shl i32 %conv

Definition at line 604 of file README.txt.

◆ shl9

compiles shl9 = shl i32 %conv

Definition at line 605 of file README.txt.

◆ Shrink

This would be a win on but not x86 or ppc64 Shrink

Definition at line 41 of file README.txt.

◆ size

i<reg-> size

Definition at line 166 of file README.txt.

◆ systems

Note that only the low bits of effective_addr2 are used On bit systems

Definition at line 100 of file README.txt.

◆ tables

we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this whole function isel would also handle this Investigate lowering of sparse switch statements into perfect hash tables

Definition at line 439 of file README.txt.

◆ targets

Unrolling by would eliminate the& in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various targets

Definition at line 567 of file README.txt.

◆ then

< i1 > br i1 label label return then

Definition at line 338 of file README.txt.

◆ this

multiplies can be turned into SHL so they should be handled as if they were associative return like this

Definition at line 378 of file README.txt.

◆ though

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports though

Definition at line 681 of file README.txt.

◆ tmp

<i32> tmp = icmp ne i32 %tmp.1

Definition at line 337 of file README.txt.

◆ to

we compile this to

Definition at line 406 of file README.txt.

◆ transform

instcombine should handle this transform

Definition at line 262 of file README.txt.

Referenced by llvm::InterleaveGroup< InstTy >::addMetadata(), llvm::logicalview::flattenedFilePath(), llvm::Clause::getFormattedParserClassName(), llvm::LoopVectorizationCostModel::getVectorIntrinsicCost(), INITIALIZE_PASS(), llvm::PBQP::Vector::operator+=(), llvm::PBQP::Matrix::operator+=(), llvm::AArch64InstPrinter::printSysAlias(), llvm::AArch64InstPrinter::printSyspAlias(), llvm::xray::profileFromTrace(), llvm::readWideAPInt(), llvm::transform(), and llvm::logicalview::transformPath().

◆ U64

instcombine should handle this C2 when and C2 are unsigned Similarly for udiv and signed operands Currently InstCombine avoids this transform but will do it when the signs of the operands and the sign of the divide match See the FIXME in InstructionCombining cpp in the visitSetCondInst method after the switch case for Instruction::UDiv (around line 4447) for more details. The SingleSource/Benchmarks/Shootout-C++/hash and hash2 tests have examples of this const ruct. [LOOP OPTIMIZATION] SingleSource/Benchmarks/Misc/dt.c shows several interesting optimization opportunities in its double_array_divs_variable function typedef unsigned long long U64

Definition at line 268 of file README.txt.

Referenced by parseBasicType().

◆ X

instcombine should handle this C2 when X

Definition at line 263 of file README.txt.

Referenced by test().

◆ x

This should optimize to x

Definition at line 767 of file README.txt.

◆ x86

There are other cases in various td files Take something like the following on x86

Definition at line 318 of file README.txt.

Referenced by llvm::archToDevDivInternalArch(), llvm::archToLegacyVCArch(), llvm::archToWindowsSDKArch(), llvm::identify_magic(), mapArchToCVCPUType(), llvm::pdb::operator<<(), and readPrefixes().

◆ X86

Unrolling by would eliminate the& in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86

Definition at line 568 of file README.txt.

Referenced by llvm::X86InstrInfo::isDataInvariant(), streamMapping(), llvm::X86InstrInfo::X86InstrInfo(), and llvm::X86RegisterInfo::X86RegisterInfo().

◆ xmm0

gets compiled into this on rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps rsp movaps xmm0

Definition at line 517 of file README.txt.

◆ y

The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for the first function produces better code on X86 From GCC int y

Initial value:

{

return x*x*x+y+x*x*x*x*x*y*y*y*y

Definition at line 61 of file README.txt.

Referenced by llvm::ComputeMappedEditDistance(), llvm::Optional< uint64_t >::create(), exit(), g(), llvm::getMaxNTIDy(), llvm::ScalarEvolution::getMulExpr(), llvm::getReqNTIDy(), llvm::hashing::detail::hash_1to3_bytes(), llvm::IntervalMap< uint64_t, uint16_t, 8, IntervalMapHalfOpenInfo< uint64_t > >::insert(), llvm::IntervalMap< KeyT, ValT, N, Traits >::iterator::insert(), llvm::IntervalMapImpl::LeafNode< uint64_t, uint16_t, N, IntervalMapHalfOpenInfo< uint64_t > >::insertFrom(), llvm::ExecutionEngine::LoadValueFromMemory(), llvm::make_range(), llvm::InstIterator< BB_t, BB_i_t, BI_t, II_t >::operator!=(), llvm::optional_detail::OptionalStorage< uint64_t >::operator=(), llvm::optional_detail::OptionalStorage< T, true >::operator=(), llvm::Optional< uint64_t >::operator=(), llvm::InstIterator< BB_t, BB_i_t, BI_t, II_t >::operator==(), and runNVVMIntrRange().

Macros

Functions

Variables

Macro Definition Documentation

◆ PMD_MASK

Function Documentation

◆ a() [1/5]

◆ a() [2/5]

◆ a() [3/5]

◆ a() [4/5]

◆ a() [5/5]

◆ bar()

◆ bit()

◆ f()

◆ f6()

◆ finite()

◆ foo()

◆ for() [1/2]

◆ for() [2/2]

◆ g()

◆ GetHotKey()

◆ h()

◆ hypot()

◆ if() [1/2]

◆ if() [2/2]

◆ instcombine()

◆ into()

◆ is()

◆ j()

◆ letters()

◆ loops()

◆ memcpy() [1/2]

◆ memcpy() [2/2]

◆ popcount() [1/2]

◆ popcount() [2/2]

◆ pow2m1()

◆ powi()

◆ read_16_be()

◆ setlt()

◆ sincosf()

◆ sincosl()

◆ test()

◆ This()

Variable Documentation

◆ $pb

◆ __pad0__

◆ __pad1__

◆ __pad2__

◆ __pad3__

◆ a1

◆ a2

◆ a3

◆ a4

◆ aggressive

◆ align

◆ also

◆ Also

◆ Alt

◆ arguments

◆ as

◆ assertion

◆ available

◆ b

◆ b0

◆ b1

◆ b2

◆ b3

◆ b4

◆ block

◆ buf2

◆ buf3

◆ buf4

◆ Bug

◆ C

◆ C1

◆ calls

◆ canonical

◆ case

◆ cases

◆ CLZ

◆ pad0

◆ pad1

◆ pad2

◆ pad3