LLVM  13.0.0git
Functions | Variables
lib/Target/Sparc/README.txt File Reference

Functions

To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st g0 retl nop should be replaced with a brz in V9 mode *Same as but emit conditional move on register zero (p192) in V9 mode. Testcase
 

Variables

To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 mode
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this though
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this intp
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc i0
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop LBBt1_1
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st l0
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st LBBt1_2
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st g0
 
To do *Keep the address of the constant pool in a register instead of forming its address all of the time *We can fold small constant offsets into the hi lo references to constant pool addresses as well *When in V9 register allocate icc *[0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand *Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st g0 retl nop should be replaced with a brz in V9 mode *Same as above
 
*Emit MULX[SU] DIVX instructions in V9 mode instead of fiddling with the Y register
 

Function Documentation

◆ zero()

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st g0 retl nop should be replaced with a brz in V9 mode* Same as but emit conditional move on register zero ( p192  )

Definition at line 40 of file README.txt.

References b, C, D, ret(), and select().

Variable Documentation

◆ above

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st g0 retl nop should be replaced with a brz in V9 mode* Same as above

Definition at line 40 of file README.txt.

◆ g0

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st g0

Definition at line 34 of file README.txt.

◆ i0

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc i0

Definition at line 27 of file README.txt.

◆ l0

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st l0

Definition at line 31 of file README.txt.

◆ LBBt1_1

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop LBBt1_1

Definition at line 27 of file README.txt.

◆ LBBt1_2

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6 subcc l0 bne LBBt1_2 ! F nop l0 st LBBt1_2

Definition at line 34 of file README.txt.

◆ mode

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 mode

Definition at line 8 of file README.txt.

◆ o6

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int o6

Definition at line 26 of file README.txt.

◆ p

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this int* p
Initial value:
{
%C = seteq int %a, 0
br bool %C, label %T, label %F
T:
store int 123, int* %p
br label %F
F:
ret float undef
}
codegens to this:
save -96

Definition at line 13 of file README.txt.

◆ register

* Emit MULX [SU] DIVX instructions in V9 mode instead of fiddling with the Y register

Definition at line 50 of file README.txt.

◆ though

To do* Keep the address of the constant pool in a register instead of forming its address all of the time* We can fold small constant offsets into the hi lo references to constant pool addresses as well* When in V9 register allocate icc* [0-3] Add support for isel ing UMUL_LOHI instead of marking it as Expand* Emit the Branch on Integer Register with Prediction instructions It s not clear how to write a pattern for this though

Definition at line 13 of file README.txt.

store
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj obj **nth_el If the i64 division is lowered to a then a safe point array and nth_el no longer point into the correct object The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries But the loads cannot be copied like this if there was an intervening store
Definition: README.txt:133
to
Should compile to
Definition: README.txt:449
T
#define T
Definition: Mips16ISelLowering.cpp:341
ret
to esp esp setne al movzbw ax esp setg cl movzbw cx cmove cx cl jne LBB1_2 esp ret(also really horrible code on ppc). This is due to the expand code for 64-bit compares. GCC produces multiple branches
p
the resulting code requires compare and branches when and if * p
Definition: README.txt:396
F
#define F(x, y, z)
Definition: MD5.cpp:56
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
C
This is blocked on not handling X *X *X which is the same number of multiplies and is because the *X has multiple uses Here s a simple X1 * C
Definition: README.txt:75
t1
<%struct.bf ** > define void t1() nounwind ssp
Definition: README.txt:1497