llvm::AMDGPU::SIModeRegisterDefaults Struct Reference

#include "Target/AMDGPU/Utils/AMDGPUBaseInfo.h"

Collaboration diagram for llvm::AMDGPU::SIModeRegisterDefaults:

Public Member Functions
	SIModeRegisterDefaults ()
	SIModeRegisterDefaults (const Function &F)
bool	operator== (const SIModeRegisterDefaults Other) const
bool	isInlineCompatible (SIModeRegisterDefaults CalleeMode) const

Static Public Member Functions
static SIModeRegisterDefaults	getDefaultForCallingConv (CallingConv::ID CC)

Public Attributes
bool	IEEE: 1
	Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008. More...
bool	DX10Clamp: 1
	Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through. More...

Detailed Description

Definition at line 651 of file AMDGPUBaseInfo.h.

Constructor & Destructor Documentation

SIModeRegisterDefaults() [1/2]

llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults ( )

inline

Definition at line 664 of file AMDGPUBaseInfo.h.

SIModeRegisterDefaults() [2/2]

llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults

(

const Function &

F

)

Definition at line 1304 of file AMDGPUBaseInfo.cpp.

References llvm::StringRef::empty(), llvm::Function::getCallingConv(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), and llvm::FPDenormal::IEEE.

Member Function Documentation

getDefaultForCallingConv()

static SIModeRegisterDefaults llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv ( CallingConv::ID  CC )

inlinestatic

Definition at line 670 of file AMDGPUBaseInfo.h.

References DX10Clamp, IEEE, llvm::AMDGPU::isCompute(), and Mode.

isInlineCompatible()

bool llvm::AMDGPU::SIModeRegisterDefaults::isInlineCompatible ( SIModeRegisterDefaults  CalleeMode ) const

inline

Definition at line 683 of file AMDGPUBaseInfo.h.

Referenced by llvm::GCNTTIImpl::areInlineCompatible().

operator==()

bool llvm::AMDGPU::SIModeRegisterDefaults::operator== ( const SIModeRegisterDefaults  Other ) const

inline

Definition at line 677 of file AMDGPUBaseInfo.h.

References DX10Clamp, llvm::FPDenormal::IEEE, and IEEE.

Member Data Documentation

DX10Clamp

bool llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp

Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through.

Definition at line 660 of file AMDGPUBaseInfo.h.

Referenced by getDefaultForCallingConv(), getSplatConstantFP(), hasAnyNonFlatUseOfReg(), isClampZeroToOne(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and llvm::yaml::SIMode::SIMode().

IEEE

bool llvm::AMDGPU::SIModeRegisterDefaults::IEEE

Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008.

Min_dx10 and max_dx10 become IEEE 754- 2008 compliant due to signaling NaN propagation and quieting.

Definition at line 656 of file AMDGPUBaseInfo.h.

Referenced by getDefaultForCallingConv(), getOModValue(), hasAnyNonFlatUseOfReg(), llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), llvm::SITargetLowering::shouldEmitPCReloc(), and llvm::yaml::SIMode::SIMode().

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The documentation for this struct was generated from the following files:

• lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
• lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp