llvm::AMDGPU::SIModeRegisterDefaults Struct Reference

#include "Target/AMDGPU/Utils/AMDGPUBaseInfo.h"

Collaboration diagram for llvm::AMDGPU::SIModeRegisterDefaults:

Public Member Functions
	SIModeRegisterDefaults ()
	SIModeRegisterDefaults (const Function &F)
bool	operator== (const SIModeRegisterDefaults Other) const
bool	allFP32Denormals () const
bool	allFP64FP16Denormals () const
uint32_t	fpDenormModeSPValue () const
	Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode. More...
uint32_t	fpDenormModeDPValue () const
	Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode. More...
bool	isInlineCompatible (SIModeRegisterDefaults CalleeMode) const

Static Public Member Functions
static SIModeRegisterDefaults	getDefaultForCallingConv (CallingConv::ID CC)
static bool	oneWayCompatible (bool CallerMode, bool CalleeMode)
	Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller. More...

Public Attributes
bool	IEEE: 1
	Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008. More...
bool	DX10Clamp: 1
	Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through. More...
bool	FP32InputDenormals: 1
	If this is set, neither input or output denormals are flushed for most f32 instructions. More...
bool	FP32OutputDenormals: 1
bool	FP64FP16InputDenormals: 1
	If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions. More...
bool	FP64FP16OutputDenormals: 1

Detailed Description

Definition at line 764 of file AMDGPUBaseInfo.h.

Constructor & Destructor Documentation

SIModeRegisterDefaults() [1/2]

llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults ( )

inline

Definition at line 785 of file AMDGPUBaseInfo.h.

SIModeRegisterDefaults() [2/2]

llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults

(

const Function &

F

)

Definition at line 1561 of file AMDGPUBaseInfo.cpp.

References DX10Clamp, llvm::StringRef::empty(), F(), FP32InputDenormals, FP32OutputDenormals, FP64FP16InputDenormals, FP64FP16OutputDenormals, getDefaultForCallingConv(), llvm::DenormalMode::IEEE, IEEE, llvm::DenormalMode::Input, llvm::DenormalMode::Output, and llvm::parseDenormalFPAttribute().

Member Function Documentation

allFP32Denormals()

bool llvm::AMDGPU::SIModeRegisterDefaults::allFP32Denormals ( ) const

inline

Definition at line 809 of file AMDGPUBaseInfo.h.

References FP32InputDenormals, and FP32OutputDenormals.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), and llvm::AMDGPUTargetLowering::LowerUDIVREM64().

allFP64FP16Denormals()

bool llvm::AMDGPU::SIModeRegisterDefaults::allFP64FP16Denormals ( ) const

inline

Definition at line 813 of file AMDGPUBaseInfo.h.

References FP64FP16InputDenormals, and FP64FP16OutputDenormals.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFMad().

fpDenormModeDPValue()

uint32_t llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeDPValue ( ) const

inline

Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.

Definition at line 831 of file AMDGPUBaseInfo.h.

References FP64FP16InputDenormals, FP64FP16OutputDenormals, FP_DENORM_FLUSH_IN, FP_DENORM_FLUSH_IN_FLUSH_OUT, FP_DENORM_FLUSH_NONE, and FP_DENORM_FLUSH_OUT.

fpDenormModeSPValue()

uint32_t llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeSPValue ( ) const

inline

Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.

Definition at line 819 of file AMDGPUBaseInfo.h.

References FP32InputDenormals, FP32OutputDenormals, FP_DENORM_FLUSH_IN, FP_DENORM_FLUSH_IN_FLUSH_OUT, FP_DENORM_FLUSH_NONE, and FP_DENORM_FLUSH_OUT.

getDefaultForCallingConv()

static SIModeRegisterDefaults llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv ( CallingConv::ID  CC )

inlinestatic

Definition at line 795 of file AMDGPUBaseInfo.h.

References llvm::AMDGPU::isShader(), and Mode.

Referenced by SIModeRegisterDefaults().

isInlineCompatible()

bool llvm::AMDGPU::SIModeRegisterDefaults::isInlineCompatible ( SIModeRegisterDefaults  CalleeMode ) const

inline

Definition at line 849 of file AMDGPUBaseInfo.h.

References DX10Clamp, FP32InputDenormals, FP32OutputDenormals, FP64FP16InputDenormals, FP64FP16OutputDenormals, IEEE, and oneWayCompatible().

Referenced by llvm::GCNTTIImpl::areInlineCompatible().

oneWayCompatible()

static bool llvm::AMDGPU::SIModeRegisterDefaults::oneWayCompatible ( bool  CallerMode, bool  CalleeMode  )

inlinestatic

Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller.

Definition at line 843 of file AMDGPUBaseInfo.h.

Referenced by isInlineCompatible().

operator==()

bool llvm::AMDGPU::SIModeRegisterDefaults::operator== ( const SIModeRegisterDefaults  Other ) const

inline

Definition at line 801 of file AMDGPUBaseInfo.h.

References DX10Clamp, FP32InputDenormals, FP32OutputDenormals, FP64FP16InputDenormals, FP64FP16OutputDenormals, IEEE, and Other.

Member Data Documentation

DX10Clamp

bool llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp

Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through.

Definition at line 773 of file AMDGPUBaseInfo.h.

Referenced by isInlineCompatible(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

FP32InputDenormals

bool llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals

If this is set, neither input or output denormals are flushed for most f32 instructions.

Definition at line 777 of file AMDGPUBaseInfo.h.

Referenced by allFP32Denormals(), fpDenormModeSPValue(), isInlineCompatible(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

FP32OutputDenormals

bool llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals

Definition at line 778 of file AMDGPUBaseInfo.h.

Referenced by allFP32Denormals(), fpDenormModeSPValue(), isInlineCompatible(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

FP64FP16InputDenormals

bool llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals

If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions.

Definition at line 782 of file AMDGPUBaseInfo.h.

Referenced by allFP64FP16Denormals(), fpDenormModeDPValue(), isInlineCompatible(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

FP64FP16OutputDenormals

bool llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals

Definition at line 783 of file AMDGPUBaseInfo.h.

Referenced by allFP64FP16Denormals(), fpDenormModeDPValue(), isInlineCompatible(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

IEEE

bool llvm::AMDGPU::SIModeRegisterDefaults::IEEE

Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008.

Min_dx10 and max_dx10 become IEEE 754- 2008 compliant due to signaling NaN propagation and quieting.

Definition at line 769 of file AMDGPUBaseInfo.h.

Referenced by isInlineCompatible(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum(), llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

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The documentation for this struct was generated from the following files:

• lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
• lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp