Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Assembly Matcher Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_ASSEMBLER_HEADER
11 : #undef GET_ASSEMBLER_HEADER
12 : // This should be included into the middle of the declaration of
13 : // your subclasses implementation of MCTargetAsmParser.
14 : uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15 : void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16 : const OperandVector &Operands);
17 : void convertToMapAndConstraints(unsigned Kind,
18 : const OperandVector &Operands) override;
19 : unsigned MatchInstructionImpl(const OperandVector &Operands,
20 : MCInst &Inst,
21 : uint64_t &ErrorInfo,
22 : bool matchingInlineAsm,
23 : unsigned VariantID = 0);
24 : OperandMatchResultTy MatchOperandParserImpl(
25 : OperandVector &Operands,
26 : StringRef Mnemonic,
27 : bool ParseForAllFeatures = false);
28 : OperandMatchResultTy tryCustomParseOperand(
29 : OperandVector &Operands,
30 : unsigned MCK);
31 :
32 : #endif // GET_ASSEMBLER_HEADER_INFO
33 :
34 :
35 : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
36 : #undef GET_OPERAND_DIAGNOSTIC_TYPES
37 :
38 : Match_AddSubRegExtendLarge,
39 : Match_AddSubRegExtendSmall,
40 : Match_AddSubRegShift32,
41 : Match_AddSubRegShift64,
42 : Match_AddSubSecondSource,
43 : Match_InvalidComplexRotationEven,
44 : Match_InvalidComplexRotationOdd,
45 : Match_InvalidCondCode,
46 : Match_InvalidFPImm,
47 : Match_InvalidGPR64NoXZRshifted16,
48 : Match_InvalidGPR64NoXZRshifted32,
49 : Match_InvalidGPR64NoXZRshifted64,
50 : Match_InvalidGPR64NoXZRshifted8,
51 : Match_InvalidGPR64shifted16,
52 : Match_InvalidGPR64shifted32,
53 : Match_InvalidGPR64shifted64,
54 : Match_InvalidGPR64shifted8,
55 : Match_InvalidImm0_1,
56 : Match_InvalidImm0_127,
57 : Match_InvalidImm0_15,
58 : Match_InvalidImm0_255,
59 : Match_InvalidImm0_31,
60 : Match_InvalidImm0_63,
61 : Match_InvalidImm0_65535,
62 : Match_InvalidImm0_7,
63 : Match_InvalidImm1_16,
64 : Match_InvalidImm1_32,
65 : Match_InvalidImm1_64,
66 : Match_InvalidImm1_8,
67 : Match_InvalidIndexRange0_1,
68 : Match_InvalidIndexRange0_15,
69 : Match_InvalidIndexRange0_3,
70 : Match_InvalidIndexRange0_7,
71 : Match_InvalidIndexRange1_1,
72 : Match_InvalidLabel,
73 : Match_InvalidMemoryIndexed1,
74 : Match_InvalidMemoryIndexed16,
75 : Match_InvalidMemoryIndexed16SImm4,
76 : Match_InvalidMemoryIndexed16SImm7,
77 : Match_InvalidMemoryIndexed16SImm9,
78 : Match_InvalidMemoryIndexed16UImm6,
79 : Match_InvalidMemoryIndexed1SImm4,
80 : Match_InvalidMemoryIndexed1SImm6,
81 : Match_InvalidMemoryIndexed1UImm6,
82 : Match_InvalidMemoryIndexed2,
83 : Match_InvalidMemoryIndexed2SImm4,
84 : Match_InvalidMemoryIndexed2UImm5,
85 : Match_InvalidMemoryIndexed2UImm6,
86 : Match_InvalidMemoryIndexed3SImm4,
87 : Match_InvalidMemoryIndexed4,
88 : Match_InvalidMemoryIndexed4SImm4,
89 : Match_InvalidMemoryIndexed4SImm7,
90 : Match_InvalidMemoryIndexed4UImm5,
91 : Match_InvalidMemoryIndexed4UImm6,
92 : Match_InvalidMemoryIndexed8,
93 : Match_InvalidMemoryIndexed8SImm10,
94 : Match_InvalidMemoryIndexed8SImm7,
95 : Match_InvalidMemoryIndexed8UImm5,
96 : Match_InvalidMemoryIndexed8UImm6,
97 : Match_InvalidMemoryIndexedSImm5,
98 : Match_InvalidMemoryIndexedSImm6,
99 : Match_InvalidMemoryIndexedSImm8,
100 : Match_InvalidMemoryIndexedSImm9,
101 : Match_InvalidMemoryWExtend128,
102 : Match_InvalidMemoryWExtend16,
103 : Match_InvalidMemoryWExtend32,
104 : Match_InvalidMemoryWExtend64,
105 : Match_InvalidMemoryWExtend8,
106 : Match_InvalidMemoryXExtend128,
107 : Match_InvalidMemoryXExtend16,
108 : Match_InvalidMemoryXExtend32,
109 : Match_InvalidMemoryXExtend64,
110 : Match_InvalidMemoryXExtend8,
111 : Match_InvalidMovImm32Shift,
112 : Match_InvalidMovImm64Shift,
113 : Match_InvalidSVEAddSubImm16,
114 : Match_InvalidSVEAddSubImm32,
115 : Match_InvalidSVEAddSubImm64,
116 : Match_InvalidSVEAddSubImm8,
117 : Match_InvalidSVECpyImm16,
118 : Match_InvalidSVECpyImm32,
119 : Match_InvalidSVECpyImm64,
120 : Match_InvalidSVECpyImm8,
121 : Match_InvalidSVEExactFPImmOperandHalfOne,
122 : Match_InvalidSVEExactFPImmOperandHalfTwo,
123 : Match_InvalidSVEExactFPImmOperandZeroOne,
124 : Match_InvalidSVEIndexRange0_15,
125 : Match_InvalidSVEIndexRange0_3,
126 : Match_InvalidSVEIndexRange0_31,
127 : Match_InvalidSVEIndexRange0_63,
128 : Match_InvalidSVEIndexRange0_7,
129 : Match_InvalidSVEPattern,
130 : Match_InvalidSVEPredicate3bAnyReg,
131 : Match_InvalidSVEPredicate3bBReg,
132 : Match_InvalidSVEPredicate3bDReg,
133 : Match_InvalidSVEPredicate3bHReg,
134 : Match_InvalidSVEPredicate3bSReg,
135 : Match_InvalidSVEPredicateAnyReg,
136 : Match_InvalidSVEPredicateBReg,
137 : Match_InvalidSVEPredicateDReg,
138 : Match_InvalidSVEPredicateHReg,
139 : Match_InvalidSVEPredicateSReg,
140 : Match_InvalidZPR0,
141 : Match_InvalidZPR128,
142 : Match_InvalidZPR16,
143 : Match_InvalidZPR32,
144 : Match_InvalidZPR32LSL16,
145 : Match_InvalidZPR32LSL32,
146 : Match_InvalidZPR32LSL64,
147 : Match_InvalidZPR32LSL8,
148 : Match_InvalidZPR32SXTW16,
149 : Match_InvalidZPR32SXTW32,
150 : Match_InvalidZPR32SXTW64,
151 : Match_InvalidZPR32SXTW8,
152 : Match_InvalidZPR32UXTW16,
153 : Match_InvalidZPR32UXTW32,
154 : Match_InvalidZPR32UXTW64,
155 : Match_InvalidZPR32UXTW8,
156 : Match_InvalidZPR64,
157 : Match_InvalidZPR64LSL16,
158 : Match_InvalidZPR64LSL32,
159 : Match_InvalidZPR64LSL64,
160 : Match_InvalidZPR64LSL8,
161 : Match_InvalidZPR64SXTW16,
162 : Match_InvalidZPR64SXTW32,
163 : Match_InvalidZPR64SXTW64,
164 : Match_InvalidZPR64SXTW8,
165 : Match_InvalidZPR64UXTW16,
166 : Match_InvalidZPR64UXTW32,
167 : Match_InvalidZPR64UXTW64,
168 : Match_InvalidZPR64UXTW8,
169 : Match_InvalidZPR8,
170 : Match_InvalidZPR_3b16,
171 : Match_InvalidZPR_3b32,
172 : Match_InvalidZPR_3b8,
173 : Match_InvalidZPR_4b16,
174 : Match_InvalidZPR_4b32,
175 : Match_InvalidZPR_4b64,
176 : Match_LogicalSecondSource,
177 : Match_MRS,
178 : Match_MSR,
179 : END_OPERAND_DIAGNOSTIC_TYPES
180 : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
181 :
182 :
183 : #ifdef GET_REGISTER_MATCHER
184 : #undef GET_REGISTER_MATCHER
185 :
186 : // Flags for subtarget features that participate in instruction matching.
187 : enum SubtargetFeatureFlag : uint32_t {
188 : Feature_HasV8_1a = (1ULL << 25),
189 : Feature_HasV8_2a = (1ULL << 26),
190 : Feature_HasV8_3a = (1ULL << 27),
191 : Feature_HasV8_4a = (1ULL << 28),
192 : Feature_HasV8_5a = (1ULL << 29),
193 : Feature_HasFPARMv8 = (1ULL << 8),
194 : Feature_HasNEON = (1ULL << 14),
195 : Feature_HasCrypto = (1ULL << 5),
196 : Feature_HasSM4 = (1ULL << 21),
197 : Feature_HasSHA3 = (1ULL << 20),
198 : Feature_HasSHA2 = (1ULL << 19),
199 : Feature_HasAES = (1ULL << 0),
200 : Feature_HasDotProd = (1ULL << 6),
201 : Feature_HasCRC = (1ULL << 4),
202 : Feature_HasLSE = (1ULL << 12),
203 : Feature_HasRAS = (1ULL << 16),
204 : Feature_HasRDM = (1ULL << 18),
205 : Feature_HasFullFP16 = (1ULL << 10),
206 : Feature_HasFP16FML = (1ULL << 7),
207 : Feature_HasSPE = (1ULL << 22),
208 : Feature_HasFuseAES = (1ULL << 11),
209 : Feature_HasSVE = (1ULL << 23),
210 : Feature_HasRCPC = (1ULL << 17),
211 : Feature_HasAltNZCV = (1ULL << 1),
212 : Feature_HasFRInt3264 = (1ULL << 9),
213 : Feature_HasSpecCtrl = (1ULL << 24),
214 : Feature_HasPredCtrl = (1ULL << 15),
215 : Feature_HasCCDP = (1ULL << 3),
216 : Feature_HasBTI = (1ULL << 2),
217 : Feature_HasMTE = (1ULL << 13),
218 : Feature_UseNegativeImmediates = (1ULL << 30),
219 : Feature_None = 0
220 : };
221 :
222 220518 : static unsigned MatchRegisterName(StringRef Name) {
223 220518 : switch (Name.size()) {
224 : default: break;
225 160096 : case 2: // 91 strings to match.
226 : switch (Name[0]) {
227 : default: break;
228 5551 : case 'b': // 10 strings to match.
229 : switch (Name[1]) {
230 : default: break;
231 : case '0': // 1 string to match.
232 : return 9; // "b0"
233 : case '1': // 1 string to match.
234 : return 10; // "b1"
235 : case '2': // 1 string to match.
236 : return 11; // "b2"
237 : case '3': // 1 string to match.
238 : return 12; // "b3"
239 : case '4': // 1 string to match.
240 : return 13; // "b4"
241 : case '5': // 1 string to match.
242 : return 14; // "b5"
243 : case '6': // 1 string to match.
244 : return 15; // "b6"
245 : case '7': // 1 string to match.
246 : return 16; // "b7"
247 : case '8': // 1 string to match.
248 : return 17; // "b8"
249 : case '9': // 1 string to match.
250 : return 18; // "b9"
251 : }
252 : break;
253 6323 : case 'd': // 10 strings to match.
254 : switch (Name[1]) {
255 : default: break;
256 : case '0': // 1 string to match.
257 : return 41; // "d0"
258 : case '1': // 1 string to match.
259 : return 42; // "d1"
260 : case '2': // 1 string to match.
261 : return 43; // "d2"
262 : case '3': // 1 string to match.
263 : return 44; // "d3"
264 : case '4': // 1 string to match.
265 : return 45; // "d4"
266 : case '5': // 1 string to match.
267 : return 46; // "d5"
268 : case '6': // 1 string to match.
269 : return 47; // "d6"
270 : case '7': // 1 string to match.
271 : return 48; // "d7"
272 : case '8': // 1 string to match.
273 : return 49; // "d8"
274 : case '9': // 1 string to match.
275 : return 50; // "d9"
276 : }
277 : break;
278 7921 : case 'h': // 10 strings to match.
279 : switch (Name[1]) {
280 : default: break;
281 : case '0': // 1 string to match.
282 : return 73; // "h0"
283 : case '1': // 1 string to match.
284 : return 74; // "h1"
285 : case '2': // 1 string to match.
286 : return 75; // "h2"
287 : case '3': // 1 string to match.
288 : return 76; // "h3"
289 : case '4': // 1 string to match.
290 : return 77; // "h4"
291 : case '5': // 1 string to match.
292 : return 78; // "h5"
293 : case '6': // 1 string to match.
294 : return 79; // "h6"
295 : case '7': // 1 string to match.
296 : return 80; // "h7"
297 : case '8': // 1 string to match.
298 : return 81; // "h8"
299 : case '9': // 1 string to match.
300 : return 82; // "h9"
301 : }
302 : break;
303 0 : case 'p': // 10 strings to match.
304 : switch (Name[1]) {
305 : default: break;
306 : case '0': // 1 string to match.
307 : return 105; // "p0"
308 : case '1': // 1 string to match.
309 : return 106; // "p1"
310 : case '2': // 1 string to match.
311 : return 107; // "p2"
312 : case '3': // 1 string to match.
313 : return 108; // "p3"
314 : case '4': // 1 string to match.
315 : return 109; // "p4"
316 : case '5': // 1 string to match.
317 : return 110; // "p5"
318 : case '6': // 1 string to match.
319 : return 111; // "p6"
320 : case '7': // 1 string to match.
321 : return 112; // "p7"
322 : case '8': // 1 string to match.
323 : return 113; // "p8"
324 : case '9': // 1 string to match.
325 : return 114; // "p9"
326 : }
327 : break;
328 859 : case 'q': // 10 strings to match.
329 : switch (Name[1]) {
330 : default: break;
331 : case '0': // 1 string to match.
332 : return 121; // "q0"
333 : case '1': // 1 string to match.
334 : return 122; // "q1"
335 : case '2': // 1 string to match.
336 : return 123; // "q2"
337 : case '3': // 1 string to match.
338 : return 124; // "q3"
339 : case '4': // 1 string to match.
340 : return 125; // "q4"
341 : case '5': // 1 string to match.
342 : return 126; // "q5"
343 : case '6': // 1 string to match.
344 : return 127; // "q6"
345 : case '7': // 1 string to match.
346 : return 128; // "q7"
347 : case '8': // 1 string to match.
348 : return 129; // "q8"
349 : case '9': // 1 string to match.
350 : return 130; // "q9"
351 : }
352 : break;
353 20143 : case 's': // 11 strings to match.
354 : switch (Name[1]) {
355 : default: break;
356 : case '0': // 1 string to match.
357 : return 153; // "s0"
358 : case '1': // 1 string to match.
359 : return 154; // "s1"
360 : case '2': // 1 string to match.
361 : return 155; // "s2"
362 : case '3': // 1 string to match.
363 : return 156; // "s3"
364 : case '4': // 1 string to match.
365 : return 157; // "s4"
366 : case '5': // 1 string to match.
367 : return 158; // "s5"
368 : case '6': // 1 string to match.
369 : return 159; // "s6"
370 : case '7': // 1 string to match.
371 : return 160; // "s7"
372 : case '8': // 1 string to match.
373 : return 161; // "s8"
374 : case '9': // 1 string to match.
375 : return 162; // "s9"
376 : case 'p': // 1 string to match.
377 : return 5; // "sp"
378 : }
379 : break;
380 30386 : case 'w': // 10 strings to match.
381 : switch (Name[1]) {
382 : default: break;
383 : case '0': // 1 string to match.
384 : return 185; // "w0"
385 : case '1': // 1 string to match.
386 : return 186; // "w1"
387 : case '2': // 1 string to match.
388 : return 187; // "w2"
389 : case '3': // 1 string to match.
390 : return 188; // "w3"
391 : case '4': // 1 string to match.
392 : return 189; // "w4"
393 : case '5': // 1 string to match.
394 : return 190; // "w5"
395 : case '6': // 1 string to match.
396 : return 191; // "w6"
397 : case '7': // 1 string to match.
398 : return 192; // "w7"
399 : case '8': // 1 string to match.
400 : return 193; // "w8"
401 : case '9': // 1 string to match.
402 : return 194; // "w9"
403 : }
404 : break;
405 88453 : case 'x': // 10 strings to match.
406 : switch (Name[1]) {
407 : default: break;
408 : case '0': // 1 string to match.
409 : return 216; // "x0"
410 : case '1': // 1 string to match.
411 : return 217; // "x1"
412 : case '2': // 1 string to match.
413 : return 218; // "x2"
414 : case '3': // 1 string to match.
415 : return 219; // "x3"
416 : case '4': // 1 string to match.
417 : return 220; // "x4"
418 : case '5': // 1 string to match.
419 : return 221; // "x5"
420 : case '6': // 1 string to match.
421 : return 222; // "x6"
422 : case '7': // 1 string to match.
423 : return 223; // "x7"
424 : case '8': // 1 string to match.
425 : return 224; // "x8"
426 : case '9': // 1 string to match.
427 : return 225; // "x9"
428 : }
429 : break;
430 0 : case 'z': // 10 strings to match.
431 : switch (Name[1]) {
432 : default: break;
433 : case '0': // 1 string to match.
434 : return 245; // "z0"
435 : case '1': // 1 string to match.
436 : return 246; // "z1"
437 : case '2': // 1 string to match.
438 : return 247; // "z2"
439 : case '3': // 1 string to match.
440 : return 248; // "z3"
441 : case '4': // 1 string to match.
442 : return 249; // "z4"
443 : case '5': // 1 string to match.
444 : return 250; // "z5"
445 : case '6': // 1 string to match.
446 : return 251; // "z6"
447 : case '7': // 1 string to match.
448 : return 252; // "z7"
449 : case '8': // 1 string to match.
450 : return 253; // "z8"
451 : case '9': // 1 string to match.
452 : return 254; // "z9"
453 : }
454 : break;
455 : }
456 : break;
457 55784 : case 3: // 184 strings to match.
458 : switch (Name[0]) {
459 : default: break;
460 628 : case 'b': // 22 strings to match.
461 : switch (Name[1]) {
462 : default: break;
463 356 : case '1': // 10 strings to match.
464 : switch (Name[2]) {
465 : default: break;
466 : case '0': // 1 string to match.
467 : return 19; // "b10"
468 : case '1': // 1 string to match.
469 : return 20; // "b11"
470 : case '2': // 1 string to match.
471 : return 21; // "b12"
472 : case '3': // 1 string to match.
473 : return 22; // "b13"
474 : case '4': // 1 string to match.
475 : return 23; // "b14"
476 : case '5': // 1 string to match.
477 : return 24; // "b15"
478 : case '6': // 1 string to match.
479 : return 25; // "b16"
480 : case '7': // 1 string to match.
481 : return 26; // "b17"
482 : case '8': // 1 string to match.
483 : return 27; // "b18"
484 : case '9': // 1 string to match.
485 : return 28; // "b19"
486 : }
487 : break;
488 22 : case '2': // 10 strings to match.
489 : switch (Name[2]) {
490 : default: break;
491 : case '0': // 1 string to match.
492 : return 29; // "b20"
493 : case '1': // 1 string to match.
494 : return 30; // "b21"
495 : case '2': // 1 string to match.
496 : return 31; // "b22"
497 : case '3': // 1 string to match.
498 : return 32; // "b23"
499 : case '4': // 1 string to match.
500 : return 33; // "b24"
501 : case '5': // 1 string to match.
502 : return 34; // "b25"
503 : case '6': // 1 string to match.
504 : return 35; // "b26"
505 : case '7': // 1 string to match.
506 : return 36; // "b27"
507 : case '8': // 1 string to match.
508 : return 37; // "b28"
509 : case '9': // 1 string to match.
510 : return 38; // "b29"
511 : }
512 : break;
513 82 : case '3': // 2 strings to match.
514 : switch (Name[2]) {
515 : default: break;
516 : case '0': // 1 string to match.
517 : return 39; // "b30"
518 82 : case '1': // 1 string to match.
519 82 : return 40; // "b31"
520 : }
521 : break;
522 : }
523 : break;
524 3528 : case 'd': // 22 strings to match.
525 : switch (Name[1]) {
526 : default: break;
527 1184 : case '1': // 10 strings to match.
528 : switch (Name[2]) {
529 : default: break;
530 : case '0': // 1 string to match.
531 : return 51; // "d10"
532 : case '1': // 1 string to match.
533 : return 52; // "d11"
534 : case '2': // 1 string to match.
535 : return 53; // "d12"
536 : case '3': // 1 string to match.
537 : return 54; // "d13"
538 : case '4': // 1 string to match.
539 : return 55; // "d14"
540 : case '5': // 1 string to match.
541 : return 56; // "d15"
542 : case '6': // 1 string to match.
543 : return 57; // "d16"
544 : case '7': // 1 string to match.
545 : return 58; // "d17"
546 : case '8': // 1 string to match.
547 : return 59; // "d18"
548 : case '9': // 1 string to match.
549 : return 60; // "d19"
550 : }
551 : break;
552 1776 : case '2': // 10 strings to match.
553 : switch (Name[2]) {
554 : default: break;
555 : case '0': // 1 string to match.
556 : return 61; // "d20"
557 : case '1': // 1 string to match.
558 : return 62; // "d21"
559 : case '2': // 1 string to match.
560 : return 63; // "d22"
561 : case '3': // 1 string to match.
562 : return 64; // "d23"
563 : case '4': // 1 string to match.
564 : return 65; // "d24"
565 : case '5': // 1 string to match.
566 : return 66; // "d25"
567 : case '6': // 1 string to match.
568 : return 67; // "d26"
569 : case '7': // 1 string to match.
570 : return 68; // "d27"
571 : case '8': // 1 string to match.
572 : return 69; // "d28"
573 : case '9': // 1 string to match.
574 : return 70; // "d29"
575 : }
576 : break;
577 568 : case '3': // 2 strings to match.
578 : switch (Name[2]) {
579 : default: break;
580 : case '0': // 1 string to match.
581 : return 71; // "d30"
582 430 : case '1': // 1 string to match.
583 430 : return 72; // "d31"
584 : }
585 : break;
586 : }
587 : break;
588 : case 'f': // 1 string to match.
589 46 : if (memcmp(Name.data()+1, "fr", 2) != 0)
590 : break;
591 : return 1; // "ffr"
592 3344 : case 'h': // 22 strings to match.
593 : switch (Name[1]) {
594 : default: break;
595 2806 : case '1': // 10 strings to match.
596 : switch (Name[2]) {
597 : default: break;
598 : case '0': // 1 string to match.
599 : return 83; // "h10"
600 : case '1': // 1 string to match.
601 : return 84; // "h11"
602 : case '2': // 1 string to match.
603 : return 85; // "h12"
604 : case '3': // 1 string to match.
605 : return 86; // "h13"
606 : case '4': // 1 string to match.
607 : return 87; // "h14"
608 : case '5': // 1 string to match.
609 : return 88; // "h15"
610 : case '6': // 1 string to match.
611 : return 89; // "h16"
612 : case '7': // 1 string to match.
613 : return 90; // "h17"
614 : case '8': // 1 string to match.
615 : return 91; // "h18"
616 : case '9': // 1 string to match.
617 : return 92; // "h19"
618 : }
619 : break;
620 446 : case '2': // 10 strings to match.
621 : switch (Name[2]) {
622 : default: break;
623 : case '0': // 1 string to match.
624 : return 93; // "h20"
625 : case '1': // 1 string to match.
626 : return 94; // "h21"
627 : case '2': // 1 string to match.
628 : return 95; // "h22"
629 : case '3': // 1 string to match.
630 : return 96; // "h23"
631 : case '4': // 1 string to match.
632 : return 97; // "h24"
633 : case '5': // 1 string to match.
634 : return 98; // "h25"
635 : case '6': // 1 string to match.
636 : return 99; // "h26"
637 : case '7': // 1 string to match.
638 : return 100; // "h27"
639 : case '8': // 1 string to match.
640 : return 101; // "h28"
641 : case '9': // 1 string to match.
642 : return 102; // "h29"
643 : }
644 : break;
645 92 : case '3': // 2 strings to match.
646 : switch (Name[2]) {
647 : default: break;
648 : case '0': // 1 string to match.
649 : return 103; // "h30"
650 82 : case '1': // 1 string to match.
651 82 : return 104; // "h31"
652 : }
653 : break;
654 : }
655 : break;
656 102 : case 'p': // 6 strings to match.
657 102 : if (Name[1] != '1')
658 : break;
659 : switch (Name[2]) {
660 : default: break;
661 : case '0': // 1 string to match.
662 : return 115; // "p10"
663 : case '1': // 1 string to match.
664 : return 116; // "p11"
665 : case '2': // 1 string to match.
666 : return 117; // "p12"
667 : case '3': // 1 string to match.
668 : return 118; // "p13"
669 : case '4': // 1 string to match.
670 : return 119; // "p14"
671 : case '5': // 1 string to match.
672 : return 120; // "p15"
673 : }
674 : break;
675 754 : case 'q': // 22 strings to match.
676 : switch (Name[1]) {
677 : default: break;
678 174 : case '1': // 10 strings to match.
679 : switch (Name[2]) {
680 : default: break;
681 : case '0': // 1 string to match.
682 : return 131; // "q10"
683 : case '1': // 1 string to match.
684 : return 132; // "q11"
685 : case '2': // 1 string to match.
686 : return 133; // "q12"
687 : case '3': // 1 string to match.
688 : return 134; // "q13"
689 : case '4': // 1 string to match.
690 : return 135; // "q14"
691 : case '5': // 1 string to match.
692 : return 136; // "q15"
693 : case '6': // 1 string to match.
694 : return 137; // "q16"
695 : case '7': // 1 string to match.
696 : return 138; // "q17"
697 : case '8': // 1 string to match.
698 : return 139; // "q18"
699 : case '9': // 1 string to match.
700 : return 140; // "q19"
701 : }
702 : break;
703 572 : case '2': // 10 strings to match.
704 : switch (Name[2]) {
705 : default: break;
706 : case '0': // 1 string to match.
707 : return 141; // "q20"
708 : case '1': // 1 string to match.
709 : return 142; // "q21"
710 : case '2': // 1 string to match.
711 : return 143; // "q22"
712 : case '3': // 1 string to match.
713 : return 144; // "q23"
714 : case '4': // 1 string to match.
715 : return 145; // "q24"
716 : case '5': // 1 string to match.
717 : return 146; // "q25"
718 : case '6': // 1 string to match.
719 : return 147; // "q26"
720 : case '7': // 1 string to match.
721 : return 148; // "q27"
722 : case '8': // 1 string to match.
723 : return 149; // "q28"
724 : case '9': // 1 string to match.
725 : return 150; // "q29"
726 : }
727 : break;
728 8 : case '3': // 2 strings to match.
729 : switch (Name[2]) {
730 : default: break;
731 : case '0': // 1 string to match.
732 : return 151; // "q30"
733 0 : case '1': // 1 string to match.
734 0 : return 152; // "q31"
735 : }
736 : break;
737 : }
738 : break;
739 3956 : case 's': // 22 strings to match.
740 : switch (Name[1]) {
741 : default: break;
742 1924 : case '1': // 10 strings to match.
743 : switch (Name[2]) {
744 : default: break;
745 : case '0': // 1 string to match.
746 : return 163; // "s10"
747 : case '1': // 1 string to match.
748 : return 164; // "s11"
749 : case '2': // 1 string to match.
750 : return 165; // "s12"
751 : case '3': // 1 string to match.
752 : return 166; // "s13"
753 : case '4': // 1 string to match.
754 : return 167; // "s14"
755 : case '5': // 1 string to match.
756 : return 168; // "s15"
757 : case '6': // 1 string to match.
758 : return 169; // "s16"
759 : case '7': // 1 string to match.
760 : return 170; // "s17"
761 : case '8': // 1 string to match.
762 : return 171; // "s18"
763 : case '9': // 1 string to match.
764 : return 172; // "s19"
765 : }
766 : break;
767 1474 : case '2': // 10 strings to match.
768 : switch (Name[2]) {
769 : default: break;
770 : case '0': // 1 string to match.
771 : return 173; // "s20"
772 : case '1': // 1 string to match.
773 : return 174; // "s21"
774 : case '2': // 1 string to match.
775 : return 175; // "s22"
776 : case '3': // 1 string to match.
777 : return 176; // "s23"
778 : case '4': // 1 string to match.
779 : return 177; // "s24"
780 : case '5': // 1 string to match.
781 : return 178; // "s25"
782 : case '6': // 1 string to match.
783 : return 179; // "s26"
784 : case '7': // 1 string to match.
785 : return 180; // "s27"
786 : case '8': // 1 string to match.
787 : return 181; // "s28"
788 : case '9': // 1 string to match.
789 : return 182; // "s29"
790 : }
791 : break;
792 526 : case '3': // 2 strings to match.
793 : switch (Name[2]) {
794 : default: break;
795 : case '0': // 1 string to match.
796 : return 183; // "s30"
797 428 : case '1': // 1 string to match.
798 428 : return 184; // "s31"
799 : }
800 : break;
801 : }
802 : break;
803 12088 : case 'w': // 23 strings to match.
804 : switch (Name[1]) {
805 : default: break;
806 3680 : case '1': // 10 strings to match.
807 : switch (Name[2]) {
808 : default: break;
809 : case '0': // 1 string to match.
810 : return 195; // "w10"
811 : case '1': // 1 string to match.
812 : return 196; // "w11"
813 : case '2': // 1 string to match.
814 : return 197; // "w12"
815 : case '3': // 1 string to match.
816 : return 198; // "w13"
817 : case '4': // 1 string to match.
818 : return 199; // "w14"
819 : case '5': // 1 string to match.
820 : return 200; // "w15"
821 : case '6': // 1 string to match.
822 : return 201; // "w16"
823 : case '7': // 1 string to match.
824 : return 202; // "w17"
825 : case '8': // 1 string to match.
826 : return 203; // "w18"
827 : case '9': // 1 string to match.
828 : return 204; // "w19"
829 : }
830 : break;
831 3027 : case '2': // 10 strings to match.
832 : switch (Name[2]) {
833 : default: break;
834 : case '0': // 1 string to match.
835 : return 205; // "w20"
836 : case '1': // 1 string to match.
837 : return 206; // "w21"
838 : case '2': // 1 string to match.
839 : return 207; // "w22"
840 : case '3': // 1 string to match.
841 : return 208; // "w23"
842 : case '4': // 1 string to match.
843 : return 209; // "w24"
844 : case '5': // 1 string to match.
845 : return 210; // "w25"
846 : case '6': // 1 string to match.
847 : return 211; // "w26"
848 : case '7': // 1 string to match.
849 : return 212; // "w27"
850 : case '8': // 1 string to match.
851 : return 213; // "w28"
852 : case '9': // 1 string to match.
853 : return 214; // "w29"
854 : }
855 : break;
856 316 : case '3': // 1 string to match.
857 316 : if (Name[2] != '0')
858 : break;
859 : return 215; // "w30"
860 2616 : case 's': // 1 string to match.
861 2616 : if (Name[2] != 'p')
862 : break;
863 : return 6; // "wsp"
864 2449 : case 'z': // 1 string to match.
865 2449 : if (Name[2] != 'r')
866 : break;
867 : return 7; // "wzr"
868 : }
869 : break;
870 25064 : case 'x': // 22 strings to match.
871 : switch (Name[1]) {
872 : default: break;
873 15244 : case '1': // 10 strings to match.
874 : switch (Name[2]) {
875 : default: break;
876 : case '0': // 1 string to match.
877 : return 226; // "x10"
878 : case '1': // 1 string to match.
879 : return 227; // "x11"
880 : case '2': // 1 string to match.
881 : return 228; // "x12"
882 : case '3': // 1 string to match.
883 : return 229; // "x13"
884 : case '4': // 1 string to match.
885 : return 230; // "x14"
886 : case '5': // 1 string to match.
887 : return 231; // "x15"
888 : case '6': // 1 string to match.
889 : return 232; // "x16"
890 : case '7': // 1 string to match.
891 : return 233; // "x17"
892 : case '8': // 1 string to match.
893 : return 234; // "x18"
894 : case '9': // 1 string to match.
895 : return 235; // "x19"
896 : }
897 : break;
898 5986 : case '2': // 10 strings to match.
899 : switch (Name[2]) {
900 : default: break;
901 : case '0': // 1 string to match.
902 : return 236; // "x20"
903 : case '1': // 1 string to match.
904 : return 237; // "x21"
905 : case '2': // 1 string to match.
906 : return 238; // "x22"
907 : case '3': // 1 string to match.
908 : return 239; // "x23"
909 : case '4': // 1 string to match.
910 : return 240; // "x24"
911 : case '5': // 1 string to match.
912 : return 241; // "x25"
913 : case '6': // 1 string to match.
914 : return 242; // "x26"
915 : case '7': // 1 string to match.
916 : return 243; // "x27"
917 : case '8': // 1 string to match.
918 : return 244; // "x28"
919 : case '9': // 1 string to match.
920 : return 2; // "x29"
921 : }
922 : break;
923 956 : case '3': // 1 string to match.
924 956 : if (Name[2] != '0')
925 : break;
926 : return 3; // "x30"
927 2766 : case 'z': // 1 string to match.
928 2766 : if (Name[2] != 'r')
929 : break;
930 : return 8; // "xzr"
931 : }
932 : break;
933 182 : case 'z': // 22 strings to match.
934 : switch (Name[1]) {
935 : default: break;
936 0 : case '1': // 10 strings to match.
937 : switch (Name[2]) {
938 : default: break;
939 : case '0': // 1 string to match.
940 : return 255; // "z10"
941 : case '1': // 1 string to match.
942 : return 256; // "z11"
943 : case '2': // 1 string to match.
944 : return 257; // "z12"
945 : case '3': // 1 string to match.
946 : return 258; // "z13"
947 : case '4': // 1 string to match.
948 : return 259; // "z14"
949 : case '5': // 1 string to match.
950 : return 260; // "z15"
951 : case '6': // 1 string to match.
952 : return 261; // "z16"
953 : case '7': // 1 string to match.
954 : return 262; // "z17"
955 : case '8': // 1 string to match.
956 : return 263; // "z18"
957 : case '9': // 1 string to match.
958 : return 264; // "z19"
959 : }
960 : break;
961 0 : case '2': // 10 strings to match.
962 : switch (Name[2]) {
963 : default: break;
964 : case '0': // 1 string to match.
965 : return 265; // "z20"
966 : case '1': // 1 string to match.
967 : return 266; // "z21"
968 : case '2': // 1 string to match.
969 : return 267; // "z22"
970 : case '3': // 1 string to match.
971 : return 268; // "z23"
972 : case '4': // 1 string to match.
973 : return 269; // "z24"
974 : case '5': // 1 string to match.
975 : return 270; // "z25"
976 : case '6': // 1 string to match.
977 : return 271; // "z26"
978 : case '7': // 1 string to match.
979 : return 272; // "z27"
980 : case '8': // 1 string to match.
981 : return 273; // "z28"
982 : case '9': // 1 string to match.
983 : return 274; // "z29"
984 : }
985 : break;
986 156 : case '3': // 2 strings to match.
987 : switch (Name[2]) {
988 : default: break;
989 : case '0': // 1 string to match.
990 : return 275; // "z30"
991 0 : case '1': // 1 string to match.
992 0 : return 276; // "z31"
993 : }
994 : break;
995 : }
996 : break;
997 : }
998 : break;
999 : case 4: // 1 string to match.
1000 2822 : if (memcmp(Name.data()+0, "nzcv", 4) != 0)
1001 : break;
1002 : return 4; // "nzcv"
1003 1175 : case 5: // 10 strings to match.
1004 1175 : if (Name[0] != 'z')
1005 : break;
1006 : switch (Name[1]) {
1007 : default: break;
1008 : case '0': // 1 string to match.
1009 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1010 : break;
1011 : return 277; // "z0_hi"
1012 : case '1': // 1 string to match.
1013 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1014 : break;
1015 : return 278; // "z1_hi"
1016 : case '2': // 1 string to match.
1017 393 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1018 : break;
1019 : return 279; // "z2_hi"
1020 : case '3': // 1 string to match.
1021 308 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1022 : break;
1023 : return 280; // "z3_hi"
1024 : case '4': // 1 string to match.
1025 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1026 : break;
1027 : return 281; // "z4_hi"
1028 : case '5': // 1 string to match.
1029 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1030 : break;
1031 : return 282; // "z5_hi"
1032 : case '6': // 1 string to match.
1033 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1034 : break;
1035 : return 283; // "z6_hi"
1036 : case '7': // 1 string to match.
1037 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1038 : break;
1039 : return 284; // "z7_hi"
1040 : case '8': // 1 string to match.
1041 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1042 : break;
1043 : return 285; // "z8_hi"
1044 : case '9': // 1 string to match.
1045 0 : if (memcmp(Name.data()+2, "_hi", 3) != 0)
1046 : break;
1047 : return 286; // "z9_hi"
1048 : }
1049 : break;
1050 238 : case 6: // 22 strings to match.
1051 238 : if (Name[0] != 'z')
1052 : break;
1053 : switch (Name[1]) {
1054 : default: break;
1055 0 : case '1': // 10 strings to match.
1056 : switch (Name[2]) {
1057 : default: break;
1058 : case '0': // 1 string to match.
1059 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1060 : break;
1061 : return 287; // "z10_hi"
1062 : case '1': // 1 string to match.
1063 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1064 : break;
1065 : return 288; // "z11_hi"
1066 : case '2': // 1 string to match.
1067 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1068 : break;
1069 : return 289; // "z12_hi"
1070 : case '3': // 1 string to match.
1071 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1072 : break;
1073 : return 290; // "z13_hi"
1074 : case '4': // 1 string to match.
1075 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1076 : break;
1077 : return 291; // "z14_hi"
1078 : case '5': // 1 string to match.
1079 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1080 : break;
1081 : return 292; // "z15_hi"
1082 : case '6': // 1 string to match.
1083 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1084 : break;
1085 : return 293; // "z16_hi"
1086 : case '7': // 1 string to match.
1087 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1088 : break;
1089 : return 294; // "z17_hi"
1090 : case '8': // 1 string to match.
1091 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1092 : break;
1093 : return 295; // "z18_hi"
1094 : case '9': // 1 string to match.
1095 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1096 : break;
1097 : return 296; // "z19_hi"
1098 : }
1099 : break;
1100 0 : case '2': // 10 strings to match.
1101 : switch (Name[2]) {
1102 : default: break;
1103 : case '0': // 1 string to match.
1104 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1105 : break;
1106 : return 297; // "z20_hi"
1107 : case '1': // 1 string to match.
1108 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1109 : break;
1110 : return 298; // "z21_hi"
1111 : case '2': // 1 string to match.
1112 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1113 : break;
1114 : return 299; // "z22_hi"
1115 : case '3': // 1 string to match.
1116 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1117 : break;
1118 : return 300; // "z23_hi"
1119 : case '4': // 1 string to match.
1120 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1121 : break;
1122 : return 301; // "z24_hi"
1123 : case '5': // 1 string to match.
1124 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1125 : break;
1126 : return 302; // "z25_hi"
1127 : case '6': // 1 string to match.
1128 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1129 : break;
1130 : return 303; // "z26_hi"
1131 : case '7': // 1 string to match.
1132 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1133 : break;
1134 : return 304; // "z27_hi"
1135 : case '8': // 1 string to match.
1136 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1137 : break;
1138 : return 305; // "z28_hi"
1139 : case '9': // 1 string to match.
1140 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1141 : break;
1142 : return 306; // "z29_hi"
1143 : }
1144 : break;
1145 0 : case '3': // 2 strings to match.
1146 : switch (Name[2]) {
1147 : default: break;
1148 : case '0': // 1 string to match.
1149 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1150 : break;
1151 : return 307; // "z30_hi"
1152 : case '1': // 1 string to match.
1153 0 : if (memcmp(Name.data()+3, "_hi", 3) != 0)
1154 : break;
1155 : return 308; // "z31_hi"
1156 : }
1157 : break;
1158 : }
1159 : break;
1160 : }
1161 : return 0;
1162 : }
1163 :
1164 : #endif // GET_REGISTER_MATCHER
1165 :
1166 :
1167 : #ifdef GET_SUBTARGET_FEATURE_NAME
1168 : #undef GET_SUBTARGET_FEATURE_NAME
1169 :
1170 : // User-level names for subtarget features that participate in
1171 : // instruction matching.
1172 6019 : static const char *getSubtargetFeatureName(uint64_t Val) {
1173 6019 : switch(Val) {
1174 : case Feature_HasV8_1a: return "armv8.1a";
1175 0 : case Feature_HasV8_2a: return "armv8.2a";
1176 67 : case Feature_HasV8_3a: return "armv8.3a";
1177 63 : case Feature_HasV8_4a: return "armv8.4a";
1178 0 : case Feature_HasV8_5a: return "armv8.5a";
1179 3 : case Feature_HasFPARMv8: return "fp-armv8";
1180 247 : case Feature_HasNEON: return "neon";
1181 0 : case Feature_HasCrypto: return "crypto";
1182 19 : case Feature_HasSM4: return "sm4";
1183 17 : case Feature_HasSHA3: return "sha3";
1184 12 : case Feature_HasSHA2: return "sha2";
1185 7 : case Feature_HasAES: return "aes";
1186 10 : case Feature_HasDotProd: return "dotprod";
1187 19 : case Feature_HasCRC: return "crc";
1188 4 : case Feature_HasLSE: return "lse";
1189 1 : case Feature_HasRAS: return "ras";
1190 0 : case Feature_HasRDM: return "rdm";
1191 335 : case Feature_HasFullFP16: return "fullfp16";
1192 96 : case Feature_HasFP16FML: return "fp16fml";
1193 1 : case Feature_HasSPE: return "spe";
1194 0 : case Feature_HasFuseAES: return "fuse-aes";
1195 4849 : case Feature_HasSVE: return "sve";
1196 6 : case Feature_HasRCPC: return "rcpc";
1197 4 : case Feature_HasAltNZCV: return "altnzcv";
1198 40 : case Feature_HasFRInt3264: return "frint3264";
1199 1 : case Feature_HasSpecCtrl: return "specctrl";
1200 0 : case Feature_HasPredCtrl: return "predctrl";
1201 0 : case Feature_HasCCDP: return "ccdp";
1202 4 : case Feature_HasBTI: return "bti";
1203 184 : case Feature_HasMTE: return "mte";
1204 30 : case Feature_UseNegativeImmediates: return "NegativeImmediates";
1205 0 : default: return "(unknown)";
1206 : }
1207 : }
1208 :
1209 : #endif // GET_SUBTARGET_FEATURE_NAME
1210 :
1211 :
1212 : #ifdef GET_MATCHER_IMPLEMENTATION
1213 : #undef GET_MATCHER_IMPLEMENTATION
1214 :
1215 : enum {
1216 : Tie0_1_1,
1217 : Tie0_1_2,
1218 : Tie0_1_3,
1219 : Tie0_1_5,
1220 : Tie0_1_6,
1221 : Tie0_2_2,
1222 : Tie0_3_3,
1223 : Tie0_4_4,
1224 : Tie0_5_5,
1225 : Tie1_1_1,
1226 : Tie1_2_2,
1227 : Tie255_1_2,
1228 : };
1229 :
1230 : static const uint8_t TiedAsmOperandTable[][3] = {
1231 : /* Tie0_1_1 */ { 0, 1, 1 },
1232 : /* Tie0_1_2 */ { 0, 1, 2 },
1233 : /* Tie0_1_3 */ { 0, 1, 3 },
1234 : /* Tie0_1_5 */ { 0, 1, 5 },
1235 : /* Tie0_1_6 */ { 0, 1, 6 },
1236 : /* Tie0_2_2 */ { 0, 2, 2 },
1237 : /* Tie0_3_3 */ { 0, 3, 3 },
1238 : /* Tie0_4_4 */ { 0, 4, 4 },
1239 : /* Tie0_5_5 */ { 0, 5, 5 },
1240 : /* Tie1_1_1 */ { 1, 1, 1 },
1241 : /* Tie1_2_2 */ { 1, 2, 2 },
1242 : /* Tie255_1_2 */ { 255, 1, 2 },
1243 : };
1244 :
1245 : namespace {
1246 : enum OperatorConversionKind {
1247 : CVT_Done,
1248 : CVT_Reg,
1249 : CVT_Tied,
1250 : CVT_95_Reg,
1251 : CVT_95_addVectorReg128Operands,
1252 : CVT_95_addVectorReg64Operands,
1253 : CVT_95_addRegOperands,
1254 : CVT_imm_95_16,
1255 : CVT_imm_95_24,
1256 : CVT_imm_95_0,
1257 : CVT_95_addImmNegWithOptionalShiftOperands_LT_12_GT_,
1258 : CVT_95_addImmWithOptionalShiftOperands_LT_12_GT_,
1259 : CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_,
1260 : CVT_95_addShifterOperands,
1261 : CVT_95_addExtendOperands,
1262 : CVT_95_addExtend64Operands,
1263 : CVT_95_addImmScaledOperands_LT_16_GT_,
1264 : CVT_95_addImmOperands,
1265 : CVT_95_addAdrLabelOperands,
1266 : CVT_95_addAdrpLabelOperands,
1267 : CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_,
1268 : CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_,
1269 : CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_,
1270 : CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_,
1271 : CVT_imm_95_31,
1272 : CVT_imm_95_63,
1273 : CVT_95_addBranchTarget26Operands,
1274 : CVT_95_addCondCodeOperands,
1275 : CVT_95_addPCRelLabel19Operands,
1276 : CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_,
1277 : CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_,
1278 : CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_,
1279 : CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_,
1280 : CVT_imm_95_32,
1281 : CVT_95_addBTIHintOperands,
1282 : CVT_imm_95_15,
1283 : CVT_regWZR,
1284 : CVT_regXZR,
1285 : CVT_imm_95_1,
1286 : CVT_imm_95_20,
1287 : CVT_95_addBarrierOperands,
1288 : CVT_95_addVectorIndexOperands,
1289 : CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_,
1290 : CVT_95_addComplexRotationOddOperands,
1291 : CVT_95_addComplexRotationEvenOperands,
1292 : CVT_95_addFPImmOperands,
1293 : CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_zero_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_,
1294 : CVT_95_addVectorRegLoOperands,
1295 : CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_two_GT_,
1296 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_,
1297 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_,
1298 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_,
1299 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_,
1300 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_,
1301 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_,
1302 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_,
1303 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_,
1304 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_,
1305 : CVT_95_addImmScaledOperands_LT_1_GT_,
1306 : CVT_95_addImmScaledOperands_LT_8_GT_,
1307 : CVT_95_addImmScaledOperands_LT_2_GT_,
1308 : CVT_95_addImmScaledOperands_LT_4_GT_,
1309 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_,
1310 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_,
1311 : CVT_95_addImmScaledOperands_LT_3_GT_,
1312 : CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_,
1313 : CVT_95_addUImm12OffsetOperands_LT_4_GT_,
1314 : CVT_95_addUImm12OffsetOperands_LT_8_GT_,
1315 : CVT_95_addUImm12OffsetOperands_LT_1_GT_,
1316 : CVT_95_addUImm12OffsetOperands_LT_2_GT_,
1317 : CVT_95_addUImm12OffsetOperands_LT_16_GT_,
1318 : CVT_95_addMemExtendOperands,
1319 : CVT_95_addMemExtend8Operands,
1320 : CVT_95_addMOVZMovAliasOperands_LT_0_GT_,
1321 : CVT_95_addMOVZMovAliasOperands_LT_16_GT_,
1322 : CVT_95_addMOVNMovAliasOperands_LT_0_GT_,
1323 : CVT_95_addMOVNMovAliasOperands_LT_16_GT_,
1324 : CVT_95_addMOVZMovAliasOperands_LT_32_GT_,
1325 : CVT_95_addMOVZMovAliasOperands_LT_48_GT_,
1326 : CVT_imm_95_48,
1327 : CVT_95_addMOVNMovAliasOperands_LT_32_GT_,
1328 : CVT_95_addMOVNMovAliasOperands_LT_48_GT_,
1329 : CVT_95_addFPRasZPRRegOperands_LT_128_GT_,
1330 : CVT_95_addFPRasZPRRegOperands_LT_16_GT_,
1331 : CVT_95_addFPRasZPRRegOperands_LT_32_GT_,
1332 : CVT_95_addFPRasZPRRegOperands_LT_64_GT_,
1333 : CVT_95_addFPRasZPRRegOperands_LT_8_GT_,
1334 : CVT_95_addSIMDImmType10Operands,
1335 : CVT_95_addMRSSystemRegisterOperands,
1336 : CVT_95_addMSRSystemRegisterOperands,
1337 : CVT_95_addSystemPStateFieldWithImm0_95_15Operands,
1338 : CVT_95_addSystemPStateFieldWithImm0_95_1Operands,
1339 : CVT_95_addPrefetchOperands,
1340 : CVT_95_addPSBHintOperands,
1341 : CVT_imm_95_4,
1342 : CVT_regLR,
1343 : CVT_95_addUImm6Operands,
1344 : CVT_imm_95_5,
1345 : CVT_95_addGPR64as32Operands,
1346 : CVT_imm_95_7,
1347 : CVT_95_addSysCROperands,
1348 : CVT_95_addBranchTarget14Operands,
1349 : CVT_95_addGPR32as64Operands,
1350 : CVT_imm_95_2,
1351 : CVT_imm_95_3,
1352 : CVT_NUM_CONVERTERS
1353 : };
1354 :
1355 : enum InstructionConversionKind {
1356 : Convert__Reg1_0__Reg1_1,
1357 : Convert__VectorReg1281_1__VectorReg1281_2,
1358 : Convert__VectorReg641_1__VectorReg641_2,
1359 : Convert__VectorReg1281_0__VectorReg1281_2,
1360 : Convert__VectorReg641_0__VectorReg641_2,
1361 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4,
1362 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4,
1363 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4,
1364 : Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4,
1365 : Convert__Reg1_0__Reg1_1__Reg1_2,
1366 : Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16,
1367 : Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24,
1368 : Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
1369 : Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2,
1370 : Convert__Reg1_0__Reg1_1__AddSubImm2_2,
1371 : Convert__SVEVectorHReg1_0__Tie0_1_2__SVEAddSubImm162_2,
1372 : Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2,
1373 : Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2,
1374 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2,
1375 : Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2,
1376 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2,
1377 : Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2,
1378 : Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2,
1379 : Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3,
1380 : Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3,
1381 : Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3,
1382 : Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3,
1383 : Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3,
1384 : Convert__Reg1_0__Reg1_1__Reg1_2__Extend641_3,
1385 : Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3,
1386 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4,
1387 : Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4,
1388 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5,
1389 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5,
1390 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5,
1391 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorBReg1_5,
1392 : Convert__Reg1_0__Reg1_1__UImm6s161_2__Imm0_151_3,
1393 : Convert__VectorReg641_1__VectorReg1281_2__VectorReg1281_3,
1394 : Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4,
1395 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3,
1396 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4,
1397 : Convert__FPRAsmOperandFPR641_1__VectorReg1281_2,
1398 : Convert__FPRAsmOperandFPR641_0__VectorReg1281_1,
1399 : Convert__Reg1_0__Reg1_1__SImm61_2,
1400 : Convert__Reg1_1__VectorReg1281_2,
1401 : Convert__Reg1_1__VectorReg641_2,
1402 : Convert__Reg1_0__VectorReg1281_1,
1403 : Convert__Reg1_0__VectorReg641_1,
1404 : Convert__Reg1_0__AdrLabel1_1,
1405 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL32161_3,
1406 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL32321_3,
1407 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL32641_3,
1408 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL3281_3,
1409 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL64161_3,
1410 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL64321_3,
1411 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL64641_3,
1412 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL6481_3,
1413 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64161_3,
1414 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64321_3,
1415 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64641_3,
1416 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW6481_3,
1417 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64161_3,
1418 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64321_3,
1419 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64641_3,
1420 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW6481_3,
1421 : Convert__Reg1_0__AdrpLabel1_1,
1422 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2,
1423 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2,
1424 : Convert__Reg1_0__Reg1_1__LogicalImm321_2,
1425 : Convert__Reg1_0__Reg1_1__LogicalImm641_2,
1426 : Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2,
1427 : Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2,
1428 : Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2,
1429 : Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2,
1430 : Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3,
1431 : Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3,
1432 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateBReg1_5,
1433 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_2,
1434 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_2,
1435 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2,
1436 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_2,
1437 : Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31,
1438 : Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63,
1439 : Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm1_161_2,
1440 : Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorDReg1_2,
1441 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm1_321_2,
1442 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorDReg1_2,
1443 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm1_641_2,
1444 : Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm1_81_2,
1445 : Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorDReg1_2,
1446 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_161_5,
1447 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5,
1448 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_321_5,
1449 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5,
1450 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_641_5,
1451 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_81_5,
1452 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5,
1453 : Convert__Reg1_0,
1454 : Convert_NoOperands,
1455 : Convert__BranchTarget261_0,
1456 : Convert__CondCode1_1__PCRelLabel191_2,
1457 : Convert__imm_95_0__imm_95_0__imm_95_0__imm_95_0,
1458 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorReg1281_6,
1459 : Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_311_2__Imm0_311_3,
1460 : Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2__Imm0_631_3,
1461 : Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0,
1462 : Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0,
1463 : Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2,
1464 : Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2,
1465 : Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0,
1466 : Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0,
1467 : Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2,
1468 : Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2,
1469 : Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2,
1470 : Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2,
1471 : Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3,
1472 : Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
1473 : Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3,
1474 : Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
1475 : Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3,
1476 : Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
1477 : Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3,
1478 : Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
1479 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3,
1480 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4,
1481 : Convert__Imm0_655351_0,
1482 : Convert__SVEPredicateBReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4,
1483 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4,
1484 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__Tie0_1_6,
1485 : Convert__imm_95_32,
1486 : Convert__BTIHint1_0,
1487 : Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3,
1488 : Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3,
1489 : Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3,
1490 : Convert__Reg1_0__PCRelLabel191_1,
1491 : Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3,
1492 : Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3,
1493 : Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2,
1494 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorHReg1_3,
1495 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorSReg1_3,
1496 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorDReg1_3,
1497 : Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorBReg1_3,
1498 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorHReg1_3,
1499 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorSReg1_3,
1500 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorDReg1_3,
1501 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorBReg1_3,
1502 : Convert__imm_95_15,
1503 : Convert__Imm0_151_0,
1504 : Convert__Reg1_0__Reg1_2__Reg1_1,
1505 : Convert__VectorReg1281_1__VectorReg1281_3__VectorReg1281_2,
1506 : Convert__VectorReg641_1__VectorReg641_3__VectorReg641_2,
1507 : Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2,
1508 : Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2,
1509 : Convert__regWZR__Reg1_0__Reg1_1__imm_95_16,
1510 : Convert__regXZR__Reg1_0__Reg1_1__imm_95_24,
1511 : Convert__regWZR__Reg1_0__Reg1_1__imm_95_0,
1512 : Convert__regWZR__Reg1_0__AddSubImmNeg2_1,
1513 : Convert__regWZR__Reg1_0__AddSubImm2_1,
1514 : Convert__regXZR__Reg1_0__Reg1_1__imm_95_0,
1515 : Convert__regXZR__Reg1_0__AddSubImmNeg2_1,
1516 : Convert__regXZR__Reg1_0__AddSubImm2_1,
1517 : Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2,
1518 : Convert__regWZR__Reg1_0__Reg1_1__Extend1_2,
1519 : Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2,
1520 : Convert__regXZR__Reg1_0__Reg1_1__Extend1_2,
1521 : Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2,
1522 : Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__SImm51_5,
1523 : Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__SVEVectorHReg1_5,
1524 : Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__SVEVectorDReg1_5,
1525 : Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SImm51_5,
1526 : Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5,
1527 : Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorDReg1_5,
1528 : Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SImm51_5,
1529 : Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5,
1530 : Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__SImm51_5,
1531 : Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__SVEVectorDReg1_5,
1532 : Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__SVEVectorBReg1_5,
1533 : Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__Imm0_1271_5,
1534 : Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__Imm0_1271_5,
1535 : Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__Imm0_1271_5,
1536 : Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__Imm0_1271_5,
1537 : Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_5__SVEVectorHReg1_4,
1538 : Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__SVEVectorSReg1_4,
1539 : Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__SVEVectorDReg1_4,
1540 : Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_5__SVEVectorBReg1_4,
1541 : Convert__regXZR__Reg1_0__Reg1_1,
1542 : Convert__Reg1_0__imm_95_31__imm_95_1,
1543 : Convert__Reg1_0__SVEPattern1_1__imm_95_1,
1544 : Convert__Reg1_0__SVEPattern1_1__Imm1_161_3,
1545 : Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateHReg1_2,
1546 : Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateSReg1_2,
1547 : Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateDReg1_2,
1548 : Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_2,
1549 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_2,
1550 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2,
1551 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4,
1552 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm162_4,
1553 : Convert__SVEVectorHReg1_0__SVEPredicateAnyReg1_1__SVECpyImm162_4,
1554 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4,
1555 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm322_4,
1556 : Convert__SVEVectorSReg1_0__SVEPredicateAnyReg1_1__SVECpyImm322_4,
1557 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4,
1558 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm642_4,
1559 : Convert__SVEVectorDReg1_0__SVEPredicateAnyReg1_1__SVECpyImm642_4,
1560 : Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4,
1561 : Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm82_4,
1562 : Convert__SVEVectorBReg1_0__SVEPredicateAnyReg1_1__SVECpyImm82_4,
1563 : Convert__imm_95_20,
1564 : Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3,
1565 : Convert__Reg1_0__regWZR__regWZR__CondCode1_1,
1566 : Convert__Reg1_0__regXZR__regXZR__CondCode1_1,
1567 : Convert__imm_95_0,
1568 : Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1,
1569 : Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1,
1570 : Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3,
1571 : Convert__SVEVectorDReg1_0__Tie0_1_1__imm_95_31__imm_95_1,
1572 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1,
1573 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3,
1574 : Convert__SVEVectorHReg1_0__Tie0_1_1__imm_95_31__imm_95_1,
1575 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1,
1576 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3,
1577 : Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_1,
1578 : Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_1,
1579 : Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_1,
1580 : Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_1,
1581 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1,
1582 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1,
1583 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1,
1584 : Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_1,
1585 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1,
1586 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3,
1587 : Convert__Barrier1_0,
1588 : Convert__SVEVectorHReg1_0__Reg1_1,
1589 : Convert__SVEVectorHReg1_0__SVECpyImm162_1,
1590 : Convert__SVEVectorSReg1_0__Reg1_1,
1591 : Convert__SVEVectorSReg1_0__SVECpyImm322_1,
1592 : Convert__SVEVectorDReg1_0__Reg1_1,
1593 : Convert__SVEVectorDReg1_0__SVECpyImm642_1,
1594 : Convert__SVEVectorBReg1_0__Reg1_1,
1595 : Convert__SVEVectorBReg1_0__SVECpyImm82_1,
1596 : Convert__VectorReg1281_1__Reg1_2,
1597 : Convert__VectorReg641_1__Reg1_2,
1598 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_71_2,
1599 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_31_2,
1600 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_11_2,
1601 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_151_2,
1602 : Convert__VectorReg1281_0__Reg1_2,
1603 : Convert__VectorReg641_0__Reg1_2,
1604 : Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2,
1605 : Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEIndexRange0_311_2,
1606 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEIndexRange0_151_2,
1607 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEIndexRange0_71_2,
1608 : Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEIndexRange0_631_2,
1609 : Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_151_3,
1610 : Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_11_3,
1611 : Convert__VectorReg641_1__VectorReg1281_2__IndexRange0_31_3,
1612 : Convert__VectorReg641_1__VectorReg1281_2__IndexRange0_71_3,
1613 : Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_31_3,
1614 : Convert__VectorReg641_1__VectorReg1281_2__IndexRange0_151_3,
1615 : Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_71_3,
1616 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_71_3,
1617 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_31_3,
1618 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_11_3,
1619 : Convert__Reg1_0__VectorReg1281_1__IndexRange0_151_3,
1620 : Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_151_4,
1621 : Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_11_4,
1622 : Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_31_4,
1623 : Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_71_4,
1624 : Convert__VectorReg641_0__VectorReg1281_2__IndexRange0_31_4,
1625 : Convert__VectorReg641_0__VectorReg1281_2__IndexRange0_71_4,
1626 : Convert__VectorReg641_0__VectorReg1281_2__IndexRange0_151_4,
1627 : Convert__SVEVectorHReg1_0__SVELogicalImm161_1,
1628 : Convert__SVEVectorSReg1_0__SVELogicalImm321_1,
1629 : Convert__SVEVectorDReg1_0__LogicalImm641_1,
1630 : Convert__SVEVectorBReg1_0__SVELogicalImm81_1,
1631 : Convert__imm_95_16,
1632 : Convert__SVEVectorBReg1_0__Tie0_1_2__SVEVectorBReg1_2__Imm0_2551_3,
1633 : Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__Imm1_4,
1634 : Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__Imm1_4,
1635 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__Imm1_6,
1636 : Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__Imm1_6,
1637 : Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_311_3,
1638 : Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_631_3,
1639 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5,
1640 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5,
1641 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5,
1642 : Convert__FPRAsmOperandFPR161_1__VectorReg641_2,
1643 : Convert__FPRAsmOperandFPR321_1__VectorReg641_2,
1644 : Convert__FPRAsmOperandFPR161_0__VectorReg641_1,
1645 : Convert__FPRAsmOperandFPR321_0__VectorReg641_1,
1646 : Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__ComplexRotationOdd1_4,
1647 : Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__ComplexRotationOdd1_4,
1648 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6,
1649 : Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6,
1650 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5__ComplexRotationOdd1_6,
1651 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5__ComplexRotationOdd1_6,
1652 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5__ComplexRotationOdd1_6,
1653 : Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4,
1654 : Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4,
1655 : Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4,
1656 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__ComplexRotationEven1_4,
1657 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3__ComplexRotationEven1_4,
1658 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_31_3__ComplexRotationEven1_4,
1659 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_11_3__ComplexRotationEven1_4,
1660 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__IndexRange0_11_4__ComplexRotationEven1_5,
1661 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_11_4__ComplexRotationEven1_5,
1662 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_31_4__ComplexRotationEven1_5,
1663 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6,
1664 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6,
1665 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorHReg1_4__SVEVectorHReg1_5__ComplexRotationEven1_6,
1666 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5__ComplexRotationEven1_6,
1667 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5__ComplexRotationEven1_6,
1668 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_11_6__ComplexRotationEven1_7,
1669 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_31_6__ComplexRotationEven1_7,
1670 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__IndexRange0_11_6__ComplexRotationEven1_7,
1671 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__FPImm1_4,
1672 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__FPImm1_4,
1673 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__FPImm1_4,
1674 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4,
1675 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4,
1676 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4,
1677 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4,
1678 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4,
1679 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4,
1680 : Convert__VectorReg1281_0__VectorReg641_2,
1681 : Convert__VectorReg641_0__VectorReg1281_2,
1682 : Convert__Reg1_0__Reg1_1__Imm1_161_2,
1683 : Convert__Reg1_0__Reg1_1__Imm1_321_2,
1684 : Convert__Reg1_0__Reg1_1__Imm1_641_2,
1685 : Convert__VectorReg1281_1__VectorReg1281_2__Imm1_641_3,
1686 : Convert__VectorReg641_1__VectorReg641_2__Imm1_321_3,
1687 : Convert__VectorReg641_1__VectorReg641_2__Imm1_161_3,
1688 : Convert__VectorReg1281_1__VectorReg1281_2__Imm1_321_3,
1689 : Convert__VectorReg1281_1__VectorReg1281_2__Imm1_161_3,
1690 : Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4,
1691 : Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4,
1692 : Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4,
1693 : Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4,
1694 : Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4,
1695 : Convert__SVEVectorHReg1_0__FPImm1_1,
1696 : Convert__SVEVectorSReg1_0__FPImm1_1,
1697 : Convert__SVEVectorDReg1_0__FPImm1_1,
1698 : Convert__SVEVectorHReg1_0__SVEVectorHReg1_1,
1699 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_1,
1700 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_1,
1701 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorHReg1_4__SVEVectorHReg1_5,
1702 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5,
1703 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5,
1704 : Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3,
1705 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5,
1706 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5,
1707 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5,
1708 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3,
1709 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector3bSReg1_2__IndexRange0_31_3,
1710 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3,
1711 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_11_4,
1712 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4,
1713 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4,
1714 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_31_4,
1715 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4,
1716 : Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR641_2__VectorReg1281_3__IndexRange0_11_4,
1717 : Convert__FPRAsmOperandFPR161_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4,
1718 : Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4,
1719 : Convert__FPRAsmOperandFPR161_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4,
1720 : Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4,
1721 : Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR641_1__VectorReg1281_2__IndexRange0_11_4,
1722 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_11_6,
1723 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_31_6,
1724 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorRegLo1_4__IndexRange0_71_6,
1725 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6,
1726 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6,
1727 : Convert__imm_95_0__imm_95_0__imm_95_0,
1728 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__IndexRange0_71_3,
1729 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_71_6,
1730 : Convert__Reg1_0__FPImm1_1,
1731 : Convert__VectorReg1281_1__FPImm1_2,
1732 : Convert__VectorReg641_1__FPImm1_2,
1733 : Convert__Reg1_0__regWZR,
1734 : Convert__Reg1_0__regXZR,
1735 : Convert__VectorReg1281_0__FPImm1_2,
1736 : Convert__VectorReg641_0__FPImm1_2,
1737 : Convert__SVEVectorHReg1_0__imm_95_0__imm_95_0,
1738 : Convert__SVEVectorSReg1_0__imm_95_0__imm_95_0,
1739 : Convert__SVEVectorDReg1_0__imm_95_0__imm_95_0,
1740 : Convert__Reg1_1__VectorReg1281_2__IndexRange1_11_3,
1741 : Convert__VectorReg1281_1__Reg1_3__IndexRange1_11_2,
1742 : Convert__Reg1_0__VectorReg1281_1__IndexRange1_11_3,
1743 : Convert__VectorReg1281_0__Reg1_3__IndexRange1_11_2,
1744 : Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__imm_95_0__imm_95_0,
1745 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__imm_95_0__imm_95_0,
1746 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__imm_95_0__imm_95_0,
1747 : Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3,
1748 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVector3bSReg1_2__IndexRange0_31_3,
1749 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3,
1750 : Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__IndexRange0_11_4,
1751 : Convert__VectorReg641_1__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4,
1752 : Convert__VectorReg641_1__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4,
1753 : Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__IndexRange0_31_4,
1754 : Convert__VectorReg1281_1__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4,
1755 : Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR641_2__VectorReg1281_3__IndexRange0_11_4,
1756 : Convert__FPRAsmOperandFPR161_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4,
1757 : Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4,
1758 : Convert__FPRAsmOperandFPR161_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4,
1759 : Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4,
1760 : Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__VectorReg1281_2__IndexRange0_11_4,
1761 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfTwo1_5,
1762 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfTwo1_5,
1763 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfTwo1_5,
1764 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__IndexRange0_11_6,
1765 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__IndexRange0_31_6,
1766 : Convert__VectorReg1281_0__VectorReg1281_2__VectorRegLo1_4__IndexRange0_71_6,
1767 : Convert__VectorReg641_0__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6,
1768 : Convert__VectorReg641_0__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6,
1769 : Convert__SVEVectorHReg1_0__Tie0_1_2__SVEVectorHReg1_2__Imm0_71_3,
1770 : Convert__SVEVectorSReg1_0__Tie0_1_2__SVEVectorSReg1_2__Imm0_71_3,
1771 : Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__Imm0_71_3,
1772 : Convert__Imm0_1271_0,
1773 : Convert__SVEVectorHReg1_0__Reg1_1__Reg1_2,
1774 : Convert__SVEVectorHReg1_0__Reg1_1__SImm51_2,
1775 : Convert__SVEVectorHReg1_0__SImm51_1__Reg1_2,
1776 : Convert__SVEVectorHReg1_0__SImm51_1__SImm51_2,
1777 : Convert__SVEVectorSReg1_0__Reg1_1__Reg1_2,
1778 : Convert__SVEVectorSReg1_0__Reg1_1__SImm51_2,
1779 : Convert__SVEVectorSReg1_0__SImm51_1__Reg1_2,
1780 : Convert__SVEVectorSReg1_0__SImm51_1__SImm51_2,
1781 : Convert__SVEVectorDReg1_0__Reg1_1__Reg1_2,
1782 : Convert__SVEVectorDReg1_0__Reg1_1__SImm51_2,
1783 : Convert__SVEVectorDReg1_0__SImm51_1__Reg1_2,
1784 : Convert__SVEVectorDReg1_0__SImm51_1__SImm51_2,
1785 : Convert__SVEVectorBReg1_0__Reg1_1__Reg1_2,
1786 : Convert__SVEVectorBReg1_0__Reg1_1__SImm51_2,
1787 : Convert__SVEVectorBReg1_0__SImm51_1__Reg1_2,
1788 : Convert__SVEVectorBReg1_0__SImm51_1__SImm51_2,
1789 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_3,
1790 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_3,
1791 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_3,
1792 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_3,
1793 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_151_2__Reg1_3,
1794 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_11_2__Reg1_3,
1795 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_71_2__Reg1_3,
1796 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_31_2__Reg1_3,
1797 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_151_2__VectorReg1281_3__IndexRange0_151_4,
1798 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_4,
1799 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_4,
1800 : Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_4,
1801 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_151_2__VectorReg1281_3__IndexRange0_151_5,
1802 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_5,
1803 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_5,
1804 : Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_5,
1805 : Convert__SVEVectorHReg1_0__Tie0_1_1__Reg1_1,
1806 : Convert__SVEVectorSReg1_0__Tie0_1_1__Reg1_1,
1807 : Convert__SVEVectorDReg1_0__Tie0_1_1__Reg1_1,
1808 : Convert__SVEVectorBReg1_0__Tie0_1_1__Reg1_1,
1809 : Convert__Reg1_0__Reg1_1__regXZR,
1810 : Convert__TypedVectorList4_1681_0__Reg1_2,
1811 : Convert__TypedVectorList4_1641_0__Reg1_2,
1812 : Convert__TypedVectorList4_2641_0__Reg1_2,
1813 : Convert__TypedVectorList4_2321_0__Reg1_2,
1814 : Convert__TypedVectorList4_4161_0__Reg1_2,
1815 : Convert__TypedVectorList4_4321_0__Reg1_2,
1816 : Convert__TypedVectorList4_881_0__Reg1_2,
1817 : Convert__TypedVectorList4_8161_0__Reg1_2,
1818 : Convert__TypedVectorList1_1681_0__Reg1_2,
1819 : Convert__TypedVectorList1_1641_0__Reg1_2,
1820 : Convert__TypedVectorList1_2641_0__Reg1_2,
1821 : Convert__TypedVectorList1_2321_0__Reg1_2,
1822 : Convert__TypedVectorList1_4161_0__Reg1_2,
1823 : Convert__TypedVectorList1_4321_0__Reg1_2,
1824 : Convert__TypedVectorList1_881_0__Reg1_2,
1825 : Convert__TypedVectorList1_8161_0__Reg1_2,
1826 : Convert__TypedVectorList3_1681_0__Reg1_2,
1827 : Convert__TypedVectorList3_1641_0__Reg1_2,
1828 : Convert__TypedVectorList3_2641_0__Reg1_2,
1829 : Convert__TypedVectorList3_2321_0__Reg1_2,
1830 : Convert__TypedVectorList3_4161_0__Reg1_2,
1831 : Convert__TypedVectorList3_4321_0__Reg1_2,
1832 : Convert__TypedVectorList3_881_0__Reg1_2,
1833 : Convert__TypedVectorList3_8161_0__Reg1_2,
1834 : Convert__TypedVectorList2_1681_0__Reg1_2,
1835 : Convert__TypedVectorList2_1641_0__Reg1_2,
1836 : Convert__TypedVectorList2_2641_0__Reg1_2,
1837 : Convert__TypedVectorList2_2321_0__Reg1_2,
1838 : Convert__TypedVectorList2_4161_0__Reg1_2,
1839 : Convert__TypedVectorList2_4321_0__Reg1_2,
1840 : Convert__TypedVectorList2_881_0__Reg1_2,
1841 : Convert__TypedVectorList2_8161_0__Reg1_2,
1842 : Convert__VecListFour1281_1__Reg1_3,
1843 : Convert__VecListOne1281_1__Reg1_3,
1844 : Convert__VecListThree1281_1__Reg1_3,
1845 : Convert__VecListTwo1281_1__Reg1_3,
1846 : Convert__VecListFour641_1__Reg1_3,
1847 : Convert__VecListOne641_1__Reg1_3,
1848 : Convert__VecListThree641_1__Reg1_3,
1849 : Convert__VecListTwo641_1__Reg1_3,
1850 : Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR,
1851 : Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4,
1852 : Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR,
1853 : Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4,
1854 : Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR,
1855 : Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4,
1856 : Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR,
1857 : Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4,
1858 : Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR,
1859 : Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4,
1860 : Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR,
1861 : Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4,
1862 : Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR,
1863 : Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4,
1864 : Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR,
1865 : Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4,
1866 : Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR,
1867 : Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4,
1868 : Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR,
1869 : Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4,
1870 : Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR,
1871 : Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4,
1872 : Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR,
1873 : Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4,
1874 : Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR,
1875 : Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4,
1876 : Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR,
1877 : Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4,
1878 : Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR,
1879 : Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4,
1880 : Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR,
1881 : Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4,
1882 : Convert__TypedVectorList1_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3,
1883 : Convert__TypedVectorList1_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3,
1884 : Convert__TypedVectorList1_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3,
1885 : Convert__TypedVectorList1_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3,
1886 : Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__regXZR,
1887 : Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__Reg1_4,
1888 : Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR,
1889 : Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4,
1890 : Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__regXZR,
1891 : Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__Reg1_4,
1892 : Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__regXZR,
1893 : Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__Reg1_4,
1894 : Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__regXZR,
1895 : Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__Reg1_4,
1896 : Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__regXZR,
1897 : Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__Reg1_4,
1898 : Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__regXZR,
1899 : Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__Reg1_4,
1900 : Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__regXZR,
1901 : Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__Reg1_4,
1902 : Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__regXZR,
1903 : Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__Reg1_4,
1904 : Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR,
1905 : Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4,
1906 : Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__regXZR,
1907 : Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__Reg1_4,
1908 : Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__regXZR,
1909 : Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__Reg1_4,
1910 : Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__regXZR,
1911 : Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__Reg1_4,
1912 : Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__regXZR,
1913 : Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__Reg1_4,
1914 : Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__regXZR,
1915 : Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__Reg1_4,
1916 : Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__regXZR,
1917 : Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__Reg1_4,
1918 : Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR,
1919 : Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5,
1920 : Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__regXZR,
1921 : Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__Reg1_5,
1922 : Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR,
1923 : Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5,
1924 : Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR,
1925 : Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5,
1926 : Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR,
1927 : Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5,
1928 : Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR,
1929 : Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5,
1930 : Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR,
1931 : Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5,
1932 : Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__regXZR,
1933 : Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__Reg1_5,
1934 : Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4,
1935 : Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4,
1936 : Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4,
1937 : Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4,
1938 : Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR,
1939 : Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5,
1940 : Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR,
1941 : Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5,
1942 : Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR,
1943 : Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5,
1944 : Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR,
1945 : Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5,
1946 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR,
1947 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6,
1948 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR,
1949 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6,
1950 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR,
1951 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6,
1952 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR,
1953 : Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6,
1954 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1955 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1956 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0,
1957 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1958 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0,
1959 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1960 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1961 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1962 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1963 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0,
1964 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
1965 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0,
1966 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1967 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1968 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6,
1969 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6,
1970 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6,
1971 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1972 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6,
1973 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6,
1974 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6,
1975 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6,
1976 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1977 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1978 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1979 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1980 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6,
1981 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6,
1982 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6,
1983 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
1984 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6,
1985 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6,
1986 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6,
1987 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6,
1988 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1989 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1990 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1991 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1992 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1993 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1994 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1995 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6,
1996 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
1997 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6,
1998 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6,
1999 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6,
2000 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6,
2001 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6,
2002 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6,
2003 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
2004 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6,
2005 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6,
2006 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6,
2007 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6,
2008 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6,
2009 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6,
2010 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2011 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2012 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6,
2013 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6,
2014 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6,
2015 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6,
2016 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6,
2017 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2018 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6,
2019 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6,
2020 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6,
2021 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6,
2022 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2023 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2024 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6,
2025 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6,
2026 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6,
2027 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6,
2028 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6,
2029 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2030 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6,
2031 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6,
2032 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6,
2033 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6,
2034 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2035 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2036 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2037 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2038 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2039 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2040 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2041 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6,
2042 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6,
2043 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6,
2044 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
2045 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
2046 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
2047 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
2048 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
2049 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6,
2050 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2051 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2052 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2053 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2054 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2055 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2056 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
2057 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2058 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
2059 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6,
2060 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
2061 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
2062 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
2063 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6,
2064 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
2065 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6,
2066 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6,
2067 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6,
2068 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6,
2069 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
2070 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6,
2071 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6,
2072 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6,
2073 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6,
2074 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6,
2075 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6,
2076 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6,
2077 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6,
2078 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6,
2079 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6,
2080 : Convert__TypedVectorList2_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3,
2081 : Convert__TypedVectorList2_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3,
2082 : Convert__TypedVectorList2_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3,
2083 : Convert__TypedVectorList2_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3,
2084 : Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4,
2085 : Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4,
2086 : Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4,
2087 : Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4,
2088 : Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR,
2089 : Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5,
2090 : Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR,
2091 : Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5,
2092 : Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR,
2093 : Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5,
2094 : Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR,
2095 : Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5,
2096 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR,
2097 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6,
2098 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR,
2099 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6,
2100 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR,
2101 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6,
2102 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR,
2103 : Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6,
2104 : Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2105 : Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
2106 : Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
2107 : Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2108 : Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
2109 : Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
2110 : Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2111 : Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2112 : Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
2113 : Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2114 : Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
2115 : Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6,
2116 : Convert__TypedVectorList3_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3,
2117 : Convert__TypedVectorList3_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3,
2118 : Convert__TypedVectorList3_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3,
2119 : Convert__TypedVectorList3_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3,
2120 : Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4,
2121 : Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4,
2122 : Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4,
2123 : Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4,
2124 : Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR,
2125 : Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5,
2126 : Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR,
2127 : Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5,
2128 : Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR,
2129 : Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5,
2130 : Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR,
2131 : Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5,
2132 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR,
2133 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6,
2134 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR,
2135 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6,
2136 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR,
2137 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6,
2138 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR,
2139 : Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6,
2140 : Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2141 : Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
2142 : Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
2143 : Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2144 : Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
2145 : Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
2146 : Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2147 : Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2148 : Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
2149 : Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2150 : Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
2151 : Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6,
2152 : Convert__TypedVectorList4_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3,
2153 : Convert__TypedVectorList4_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3,
2154 : Convert__TypedVectorList4_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3,
2155 : Convert__TypedVectorList4_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3,
2156 : Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4,
2157 : Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4,
2158 : Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4,
2159 : Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4,
2160 : Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR,
2161 : Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5,
2162 : Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR,
2163 : Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5,
2164 : Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR,
2165 : Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5,
2166 : Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR,
2167 : Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5,
2168 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR,
2169 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6,
2170 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR,
2171 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6,
2172 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR,
2173 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6,
2174 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR,
2175 : Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6,
2176 : Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2177 : Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6,
2178 : Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
2179 : Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2180 : Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6,
2181 : Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
2182 : Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2183 : Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6,
2184 : Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
2185 : Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0,
2186 : Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6,
2187 : Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6,
2188 : Convert__Reg1_1__Reg1_0__Reg1_3,
2189 : Convert__Reg1_0__GPR64sp01_2,
2190 : Convert__Reg1_0__Reg1_2__imm_95_0,
2191 : Convert__Reg1_0__Reg1_2__SImm91_3,
2192 : Convert__Reg1_0__Reg1_1__GPR64sp01_3,
2193 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2194 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2195 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2196 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2197 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2198 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2199 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2200 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR,
2201 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2202 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2203 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2204 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2205 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2206 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2207 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2208 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6,
2209 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6,
2210 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6,
2211 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
2212 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
2213 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
2214 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
2215 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
2216 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6,
2217 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
2218 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
2219 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
2220 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6,
2221 : Convert__Reg1_0__Reg1_2__SImm9s161_3,
2222 : Convert__Reg1_2__Reg1_0__Tie0_3_3,
2223 : Convert__Reg1_0__Reg1_1__Reg1_3__imm_95_0,
2224 : Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__imm_95_0,
2225 : Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__imm_95_0,
2226 : Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__imm_95_0,
2227 : Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4,
2228 : Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s81_4,
2229 : Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4,
2230 : Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__SImm7s81_4,
2231 : Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__SImm7s161_4,
2232 : Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5,
2233 : Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_5,
2234 : Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5,
2235 : Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_5,
2236 : Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_5,
2237 : Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4,
2238 : Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_4,
2239 : Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4,
2240 : Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_4,
2241 : Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_4,
2242 : Convert__FPRAsmOperandFPR321_0__PCRelLabel191_1,
2243 : Convert__FPRAsmOperandFPR641_0__PCRelLabel191_1,
2244 : Convert__FPRAsmOperandFPR1281_0__PCRelLabel191_1,
2245 : Convert__SVEPredicateAnyReg1_0__Reg1_2__imm_95_0,
2246 : Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0,
2247 : Convert__FPRAsmOperandFPR81_0__Reg1_2__imm_95_0,
2248 : Convert__FPRAsmOperandFPR161_0__Reg1_2__imm_95_0,
2249 : Convert__FPRAsmOperandFPR321_0__Reg1_2__imm_95_0,
2250 : Convert__FPRAsmOperandFPR641_0__Reg1_2__imm_95_0,
2251 : Convert__FPRAsmOperandFPR1281_0__Reg1_2__imm_95_0,
2252 : Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_4,
2253 : Convert__Reg1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
2254 : Convert__Reg1_0__Reg1_2__SImm9OffsetFB321_3,
2255 : Convert__Reg1_0__Reg1_2__UImm12Offset41_3,
2256 : Convert__Reg1_0__Reg1_2__SImm9OffsetFB641_3,
2257 : Convert__Reg1_0__Reg1_2__UImm12Offset81_3,
2258 : Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_4,
2259 : Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
2260 : Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm9OffsetFB81_3,
2261 : Convert__FPRAsmOperandFPR81_0__Reg1_2__UImm12Offset11_3,
2262 : Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_4,
2263 : Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
2264 : Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm9OffsetFB161_3,
2265 : Convert__FPRAsmOperandFPR161_0__Reg1_2__UImm12Offset21_3,
2266 : Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_4,
2267 : Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
2268 : Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm9OffsetFB321_3,
2269 : Convert__FPRAsmOperandFPR321_0__Reg1_2__UImm12Offset41_3,
2270 : Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_4,
2271 : Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
2272 : Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm9OffsetFB641_3,
2273 : Convert__FPRAsmOperandFPR641_0__Reg1_2__UImm12Offset81_3,
2274 : Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_4,
2275 : Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
2276 : Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm9OffsetFB1281_3,
2277 : Convert__FPRAsmOperandFPR1281_0__Reg1_2__UImm12Offset161_3,
2278 : Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend322_4,
2279 : Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend322_4,
2280 : Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_3,
2281 : Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend642_4,
2282 : Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend642_4,
2283 : Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemWExtend82_4,
2284 : Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemXExtend82_4,
2285 : Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_3,
2286 : Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemWExtend162_4,
2287 : Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemXExtend162_4,
2288 : Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_3,
2289 : Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemWExtend322_4,
2290 : Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemXExtend322_4,
2291 : Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_3,
2292 : Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemWExtend642_4,
2293 : Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemXExtend642_4,
2294 : Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_3,
2295 : Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemWExtend1282_4,
2296 : Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemXExtend1282_4,
2297 : Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_3,
2298 : Convert__SVEPredicateAnyReg1_0__Reg1_2__SImm91_3,
2299 : Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3,
2300 : Convert__Reg1_0__Reg1_2__SImm10s81_3,
2301 : Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm10s81_3,
2302 : Convert__Reg1_0__Reg1_2__SImm9OffsetFB81_3,
2303 : Convert__Reg1_0__Reg1_2__UImm12Offset11_3,
2304 : Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend82_4,
2305 : Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend82_4,
2306 : Convert__Reg1_0__Reg1_2__SImm9OffsetFB161_3,
2307 : Convert__Reg1_0__Reg1_2__UImm12Offset21_3,
2308 : Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend162_4,
2309 : Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend162_4,
2310 : Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm91_3,
2311 : Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm91_3,
2312 : Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm91_3,
2313 : Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm91_3,
2314 : Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm91_3,
2315 : Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm0_151_2,
2316 : Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm0_311_2,
2317 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm0_631_2,
2318 : Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm0_71_2,
2319 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_151_5,
2320 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5,
2321 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_631_5,
2322 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_71_5,
2323 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorBReg1_4__SVEVectorBReg1_5,
2324 : Convert__Reg1_0__Reg1_1__Reg1_2__regWZR,
2325 : Convert__Reg1_0__Reg1_1__Reg1_2__regXZR,
2326 : Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0,
2327 : Convert__Reg1_0__regWZR__Reg1_1__imm_95_0,
2328 : Convert__Reg1_0__MOVZ32_lsl0MovAlias1_1__imm_95_0,
2329 : Convert__Reg1_0__MOVZ32_lsl16MovAlias1_1__imm_95_16,
2330 : Convert__Reg1_0__MOVN32_lsl0MovAlias1_1__imm_95_0,
2331 : Convert__Reg1_0__MOVN32_lsl16MovAlias1_1__imm_95_16,
2332 : Convert__Reg1_0__regWZR__LogicalImm321_1,
2333 : Convert__Reg1_0__regXZR__Reg1_1__imm_95_0,
2334 : Convert__Reg1_0__MOVZ64_lsl0MovAlias1_1__imm_95_0,
2335 : Convert__Reg1_0__MOVZ64_lsl16MovAlias1_1__imm_95_16,
2336 : Convert__Reg1_0__MOVZ64_lsl32MovAlias1_1__imm_95_32,
2337 : Convert__Reg1_0__MOVZ64_lsl48MovAlias1_1__imm_95_48,
2338 : Convert__Reg1_0__MOVN64_lsl0MovAlias1_1__imm_95_0,
2339 : Convert__Reg1_0__MOVN64_lsl16MovAlias1_1__imm_95_16,
2340 : Convert__Reg1_0__MOVN64_lsl32MovAlias1_1__imm_95_32,
2341 : Convert__Reg1_0__MOVN64_lsl48MovAlias1_1__imm_95_48,
2342 : Convert__Reg1_0__regXZR__LogicalImm641_1,
2343 : Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_1__SVEPredicateBReg1_1,
2344 : Convert__SVEVectorQReg1_0__FPR128asZPR1_1__imm_95_0,
2345 : Convert__SVEVectorHReg1_0__SVEPreferredLogicalImm161_1,
2346 : Convert__SVEVectorHReg1_0__FPR16asZPR1_1__imm_95_0,
2347 : Convert__SVEVectorSReg1_0__SVEPreferredLogicalImm321_1,
2348 : Convert__SVEVectorSReg1_0__FPR32asZPR1_1__imm_95_0,
2349 : Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_1,
2350 : Convert__SVEVectorDReg1_0__SVEPreferredLogicalImm641_1,
2351 : Convert__SVEVectorDReg1_0__FPR64asZPR1_1__imm_95_0,
2352 : Convert__SVEVectorBReg1_0__FPR8asZPR1_1__imm_95_0,
2353 : Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_2,
2354 : Convert__VectorReg641_1__VectorReg641_2__VectorReg641_2,
2355 : Convert__Reg1_1__VectorReg1281_2__IndexRange0_11_3,
2356 : Convert__Reg1_1__VectorReg1281_2__IndexRange0_31_3,
2357 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_2,
2358 : Convert__VectorReg641_0__VectorReg641_2__VectorReg641_2,
2359 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateBReg1_0,
2360 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateBReg1_4,
2361 : Convert__SVEVectorHReg1_0__SVEPredicateAnyReg1_1__SVEVectorHReg1_4__SVEVectorHReg1_0,
2362 : Convert__SVEVectorSReg1_0__SVEPredicateAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_0,
2363 : Convert__SVEVectorDReg1_0__SVEPredicateAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_0,
2364 : Convert__SVEVectorBReg1_0__SVEPredicateAnyReg1_1__SVEVectorBReg1_4__SVEVectorBReg1_0,
2365 : Convert__Reg1_0__SIMDImmType101_1,
2366 : Convert__VectorReg1281_1__Imm0_2551_2,
2367 : Convert__VectorReg1281_1__SIMDImmType101_2,
2368 : Convert__VectorReg641_1__Imm0_2551_2__imm_95_0,
2369 : Convert__VectorReg1281_1__Imm0_2551_2__imm_95_0,
2370 : Convert__VectorReg641_1__Imm0_2551_2,
2371 : Convert__VectorReg1281_0__Imm0_2551_2,
2372 : Convert__VectorReg1281_0__SIMDImmType101_2,
2373 : Convert__VectorReg1281_0__Imm0_2551_2__imm_95_0,
2374 : Convert__VectorReg641_0__Imm0_2551_2__imm_95_0,
2375 : Convert__VectorReg641_0__Imm0_2551_2,
2376 : Convert__VectorReg641_1__Imm0_2551_2__LogicalVecShifter1_3,
2377 : Convert__VectorReg641_1__Imm0_2551_2__MoveVecShifter1_3,
2378 : Convert__VectorReg641_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
2379 : Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecShifter1_3,
2380 : Convert__VectorReg1281_1__Imm0_2551_2__MoveVecShifter1_3,
2381 : Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
2382 : Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecShifter1_3,
2383 : Convert__VectorReg1281_0__Imm0_2551_2__MoveVecShifter1_3,
2384 : Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
2385 : Convert__VectorReg641_0__Imm0_2551_2__LogicalVecShifter1_3,
2386 : Convert__VectorReg641_0__Imm0_2551_2__MoveVecShifter1_3,
2387 : Convert__VectorReg641_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3,
2388 : Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0,
2389 : Convert__Reg1_0__Tie0_1_1__MovKSymbolG01_1__imm_95_0,
2390 : Convert__Reg1_0__Tie0_1_1__MovKSymbolG11_1__imm_95_16,
2391 : Convert__Reg1_0__Tie0_1_1__MovKSymbolG21_1__imm_95_32,
2392 : Convert__Reg1_0__Tie0_1_1__MovKSymbolG31_1__imm_95_48,
2393 : Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2,
2394 : Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2,
2395 : Convert__Reg1_0__Imm0_655351_1__imm_95_0,
2396 : Convert__Reg1_0__MovZSymbolG01_1__imm_95_0,
2397 : Convert__Reg1_0__MovZSymbolG11_1__imm_95_16,
2398 : Convert__Reg1_0__MovZSymbolG21_1__imm_95_32,
2399 : Convert__Reg1_0__MovZSymbolG31_1__imm_95_48,
2400 : Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2,
2401 : Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2,
2402 : Convert__SVEVectorAnyReg1_0__SVEVectorAnyReg1_1,
2403 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4,
2404 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4,
2405 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4,
2406 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4,
2407 : Convert__Reg1_0__MRSSystemRegister1_1,
2408 : Convert__MSRSystemRegister1_0__Reg1_1,
2409 : Convert__SystemPStateFieldWithImm0_151_0__Imm0_151_1,
2410 : Convert__SystemPStateFieldWithImm0_11_0__Imm0_11_1,
2411 : Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2,
2412 : Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2,
2413 : Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2,
2414 : Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2,
2415 : Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2,
2416 : Convert__Reg1_0__regXZR__Reg1_1__LogicalShifter641_2,
2417 : Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2,
2418 : Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2,
2419 : Convert__Reg1_0__regWZR__Reg1_1,
2420 : Convert__Reg1_0__regXZR__Reg1_1,
2421 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateAnyReg1_1,
2422 : Convert__SVEPredicateBReg1_0,
2423 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3,
2424 : Convert__VectorReg1281_1__VectorReg641_2__VectorReg641_3,
2425 : Convert__VectorReg1281_0__VectorReg641_2__VectorReg641_4,
2426 : Convert__SVEPredicateHReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3,
2427 : Convert__SVEPredicateSReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3,
2428 : Convert__SVEPredicateDReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3,
2429 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2430 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0,
2431 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0,
2432 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2433 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4,
2434 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4,
2435 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4,
2436 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4,
2437 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4,
2438 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4,
2439 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4,
2440 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm6s11_4,
2441 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
2442 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32641_4,
2443 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32641_4,
2444 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4,
2445 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4,
2446 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4,
2447 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s81_4,
2448 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4,
2449 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2450 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4,
2451 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4,
2452 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4,
2453 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4,
2454 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4,
2455 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4,
2456 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4,
2457 : Convert__Prefetch1_0__PCRelLabel191_1,
2458 : Convert__Prefetch1_0__Reg1_2__imm_95_0,
2459 : Convert__Prefetch1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0,
2460 : Convert__Prefetch1_0__Reg1_2__UImm12Offset81_3,
2461 : Convert__Prefetch1_0__Reg1_2__Reg1_3__MemWExtend642_4,
2462 : Convert__Prefetch1_0__Reg1_2__Reg1_3__MemXExtend642_4,
2463 : Convert__Prefetch1_0__Reg1_2__SImm91_3,
2464 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2465 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4,
2466 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4,
2467 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4,
2468 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4,
2469 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4,
2470 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4,
2471 : Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4,
2472 : Convert__PSBHint1_0,
2473 : Convert__imm_95_4,
2474 : Convert__SVEPredicateAnyReg1_0__SVEPredicateBReg1_1,
2475 : Convert__SVEPredicateHReg1_0__imm_95_31,
2476 : Convert__SVEPredicateSReg1_0__imm_95_31,
2477 : Convert__SVEPredicateDReg1_0__imm_95_31,
2478 : Convert__SVEPredicateBReg1_0__imm_95_31,
2479 : Convert__SVEPredicateHReg1_0__SVEPattern1_1,
2480 : Convert__SVEPredicateSReg1_0__SVEPattern1_1,
2481 : Convert__SVEPredicateDReg1_0__SVEPattern1_1,
2482 : Convert__SVEPredicateBReg1_0__SVEPattern1_1,
2483 : Convert__SVEPredicateHReg1_0__SVEPredicateBReg1_1,
2484 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1,
2485 : Convert__Reg1_0__SImm61_1,
2486 : Convert__regLR,
2487 : Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1,
2488 : Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1,
2489 : Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1,
2490 : Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1,
2491 : Convert__SVEVectorBReg1_0__SVEVectorBReg1_1,
2492 : Convert__Reg1_0__UImm61_1__Imm0_151_2,
2493 : Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_311_2,
2494 : Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_631_2,
2495 : Convert__VectorReg641_1__VectorReg1281_2__Imm1_321_3,
2496 : Convert__VectorReg641_1__VectorReg1281_2__Imm1_161_3,
2497 : Convert__VectorReg641_1__VectorReg1281_2__Imm1_81_3,
2498 : Convert__VectorReg641_0__VectorReg1281_2__Imm1_321_4,
2499 : Convert__VectorReg641_0__VectorReg1281_2__Imm1_161_4,
2500 : Convert__VectorReg641_0__VectorReg1281_2__Imm1_81_4,
2501 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_81_3,
2502 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3,
2503 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_161_3,
2504 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4,
2505 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4,
2506 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4,
2507 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg641_3,
2508 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg641_4,
2509 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2,
2510 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2,
2511 : Convert__VectorReg1281_1__VectorReg1281_2__VectorReg641_3,
2512 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg641_4,
2513 : Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3,
2514 : Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3,
2515 : Convert__imm_95_0__Tie0_1_1__imm_95_0__imm_95_0,
2516 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorBReg1_1__SVEVectorBReg1_2,
2517 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVectorHReg1_2,
2518 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__IndexRange0_31_3,
2519 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_1__VectorReg1281_2__IndexRange0_31_3,
2520 : Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorBReg1_1__SVEVector3bBReg1_2__IndexRange0_31_3,
2521 : Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector4bHReg1_2__IndexRange0_11_3,
2522 : Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_2__SVEPredicateBReg1_3,
2523 : Convert__SVEVectorHReg1_0__SVEPredicateAnyReg1_1__SVEVectorHReg1_2__SVEVectorHReg1_3,
2524 : Convert__SVEVectorSReg1_0__SVEPredicateAnyReg1_1__SVEVectorSReg1_2__SVEVectorSReg1_3,
2525 : Convert__SVEVectorDReg1_0__SVEPredicateAnyReg1_1__SVEVectorDReg1_2__SVEVectorDReg1_3,
2526 : Convert__SVEVectorBReg1_0__SVEPredicateAnyReg1_1__SVEVectorBReg1_2__SVEVectorBReg1_3,
2527 : Convert__imm_95_5,
2528 : Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3,
2529 : Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2,
2530 : Convert__imm_95_0__imm_95_0__Tie0_1_1,
2531 : Convert__VectorReg1281_0__VectorReg1281_2__Tie0_1_1,
2532 : Convert__Reg1_0__Reg1_1__Imm0_631_2,
2533 : Convert__VectorReg1281_1__VectorReg1281_2__Imm0_71_3,
2534 : Convert__VectorReg1281_1__VectorReg1281_2__Imm0_631_3,
2535 : Convert__VectorReg641_1__VectorReg641_2__Imm0_311_3,
2536 : Convert__VectorReg641_1__VectorReg641_2__Imm0_151_3,
2537 : Convert__VectorReg1281_1__VectorReg1281_2__Imm0_311_3,
2538 : Convert__VectorReg641_1__VectorReg641_2__Imm0_71_3,
2539 : Convert__VectorReg1281_1__VectorReg1281_2__Imm0_151_3,
2540 : Convert__VectorReg1281_0__VectorReg1281_2__Imm0_71_4,
2541 : Convert__VectorReg1281_0__VectorReg1281_2__Imm0_631_4,
2542 : Convert__VectorReg1281_0__VectorReg1281_2__Imm0_311_4,
2543 : Convert__VectorReg1281_0__VectorReg1281_2__Imm0_151_4,
2544 : Convert__VectorReg641_0__VectorReg641_2__Imm0_311_4,
2545 : Convert__VectorReg641_0__VectorReg641_2__Imm0_151_4,
2546 : Convert__VectorReg641_0__VectorReg641_2__Imm0_71_4,
2547 : Convert__VectorReg1281_1__VectorReg641_2,
2548 : Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2,
2549 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_71_3,
2550 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_631_3,
2551 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_311_3,
2552 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_151_3,
2553 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_311_3,
2554 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_71_3,
2555 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_151_3,
2556 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_71_4,
2557 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_631_4,
2558 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_311_4,
2559 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_151_4,
2560 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_311_4,
2561 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_151_4,
2562 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_71_4,
2563 : Convert__imm_95_0__Tie0_1_1__imm_95_0__imm_95_0__imm_95_0,
2564 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4,
2565 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4,
2566 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6,
2567 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6,
2568 : Convert__Reg1_1__VectorReg1281_2__IndexRange0_151_3,
2569 : Convert__Reg1_1__VectorReg1281_2__IndexRange0_71_3,
2570 : Convert__VectorReg1281_1__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4,
2571 : Convert__VectorReg1281_1__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4,
2572 : Convert__VectorReg1281_0__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6,
2573 : Convert__VectorReg1281_0__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6,
2574 : Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1,
2575 : Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1,
2576 : Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4,
2577 : Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_3,
2578 : Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_3,
2579 : Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_3,
2580 : Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_3,
2581 : Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
2582 : Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4,
2583 : Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4,
2584 : Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4,
2585 : Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4,
2586 : Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4,
2587 : Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4,
2588 : Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4,
2589 : Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4,
2590 : Convert__Reg1_0__Reg1_1__Imm1_81_2,
2591 : Convert__Reg1_0__Reg1_1__Imm0_151_2,
2592 : Convert__Reg1_0__Reg1_1__Imm0_311_2,
2593 : Convert__Reg1_0__Reg1_1__Imm0_71_2,
2594 : Convert__VectorReg641_1__VectorReg1281_2,
2595 : Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm1_641_2,
2596 : Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_641_3,
2597 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_321_3,
2598 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_161_3,
2599 : Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_81_3,
2600 : Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_641_4,
2601 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_321_4,
2602 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_161_4,
2603 : Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_81_4,
2604 : Convert__VectorReg1281_1__VectorReg1281_2__Imm1_81_3,
2605 : Convert__VectorReg641_1__VectorReg641_2__Imm1_81_3,
2606 : Convert__VectorReg1281_0__VectorReg1281_2__Imm1_81_4,
2607 : Convert__VectorReg641_0__VectorReg641_2__Imm1_81_4,
2608 : Convert__VectorReg1281_1__VectorReg641_2__Imm0_311_3,
2609 : Convert__VectorReg1281_1__VectorReg641_2__Imm0_151_3,
2610 : Convert__VectorReg1281_1__VectorReg641_2__Imm0_71_3,
2611 : Convert__VectorReg1281_0__VectorReg641_2__Imm0_311_4,
2612 : Convert__VectorReg1281_0__VectorReg641_2__Imm0_151_4,
2613 : Convert__VectorReg1281_0__VectorReg641_2__Imm0_71_4,
2614 : Convert__TypedVectorList1_081_0__IndexRange0_151_1__Reg1_3,
2615 : Convert__TypedVectorList1_0641_0__IndexRange0_11_1__Reg1_3,
2616 : Convert__TypedVectorList1_0161_0__IndexRange0_71_1__Reg1_3,
2617 : Convert__TypedVectorList1_0321_0__IndexRange0_31_1__Reg1_3,
2618 : Convert__VecListOne1281_1__IndexRange0_151_2__Reg1_4,
2619 : Convert__VecListOne1281_1__IndexRange0_11_2__Reg1_4,
2620 : Convert__VecListOne1281_1__IndexRange0_71_2__Reg1_4,
2621 : Convert__VecListOne1281_1__IndexRange0_31_2__Reg1_4,
2622 : Convert__Reg1_3__TypedVectorList1_081_0__IndexRange0_151_1__Tie0_4_4__regXZR,
2623 : Convert__Reg1_3__TypedVectorList1_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5,
2624 : Convert__Reg1_3__TypedVectorList1_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR,
2625 : Convert__Reg1_3__TypedVectorList1_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5,
2626 : Convert__Reg1_3__TypedVectorList1_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR,
2627 : Convert__Reg1_3__TypedVectorList1_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5,
2628 : Convert__Reg1_3__TypedVectorList1_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR,
2629 : Convert__Reg1_3__TypedVectorList1_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5,
2630 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_151_2__Tie0_5_5__regXZR,
2631 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6,
2632 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_11_2__Tie0_5_5__regXZR,
2633 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6,
2634 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_71_2__Tie0_5_5__regXZR,
2635 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6,
2636 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_31_2__Tie0_5_5__regXZR,
2637 : Convert__Reg1_4__VecListOne1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6,
2638 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2639 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2640 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0,
2641 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2642 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0,
2643 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2644 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2645 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2646 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2647 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0,
2648 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2649 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0,
2650 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2651 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2652 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4,
2653 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4,
2654 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4,
2655 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2656 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4,
2657 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4,
2658 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4,
2659 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4,
2660 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2661 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2662 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2663 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2664 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4,
2665 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4,
2666 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4,
2667 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2668 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4,
2669 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4,
2670 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4,
2671 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4,
2672 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2673 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2674 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2675 : Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2676 : Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2677 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2678 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2679 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4,
2680 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
2681 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4,
2682 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4,
2683 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4,
2684 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4,
2685 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4,
2686 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4,
2687 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
2688 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4,
2689 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4,
2690 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4,
2691 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4,
2692 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4,
2693 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4,
2694 : Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2695 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2696 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4,
2697 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4,
2698 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4,
2699 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4,
2700 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4,
2701 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2702 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4,
2703 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4,
2704 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4,
2705 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4,
2706 : Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2707 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2708 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4,
2709 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4,
2710 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4,
2711 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4,
2712 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4,
2713 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2714 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4,
2715 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4,
2716 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4,
2717 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4,
2718 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2719 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4,
2720 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4,
2721 : Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4,
2722 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2723 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4,
2724 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4,
2725 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4,
2726 : Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4,
2727 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2728 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4,
2729 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4,
2730 : Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4,
2731 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2732 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4,
2733 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4,
2734 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4,
2735 : Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4,
2736 : Convert__TypedVectorList2_081_0__IndexRange0_151_1__Reg1_3,
2737 : Convert__TypedVectorList2_0641_0__IndexRange0_11_1__Reg1_3,
2738 : Convert__TypedVectorList2_0161_0__IndexRange0_71_1__Reg1_3,
2739 : Convert__TypedVectorList2_0321_0__IndexRange0_31_1__Reg1_3,
2740 : Convert__VecListTwo1281_1__IndexRange0_151_2__Reg1_4,
2741 : Convert__VecListTwo1281_1__IndexRange0_11_2__Reg1_4,
2742 : Convert__VecListTwo1281_1__IndexRange0_71_2__Reg1_4,
2743 : Convert__VecListTwo1281_1__IndexRange0_31_2__Reg1_4,
2744 : Convert__Reg1_3__TypedVectorList2_081_0__IndexRange0_151_1__Tie0_4_4__regXZR,
2745 : Convert__Reg1_3__TypedVectorList2_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5,
2746 : Convert__Reg1_3__TypedVectorList2_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR,
2747 : Convert__Reg1_3__TypedVectorList2_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5,
2748 : Convert__Reg1_3__TypedVectorList2_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR,
2749 : Convert__Reg1_3__TypedVectorList2_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5,
2750 : Convert__Reg1_3__TypedVectorList2_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR,
2751 : Convert__Reg1_3__TypedVectorList2_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5,
2752 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_151_2__Tie0_5_5__regXZR,
2753 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6,
2754 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_11_2__Tie0_5_5__regXZR,
2755 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6,
2756 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_71_2__Tie0_5_5__regXZR,
2757 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6,
2758 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_31_2__Tie0_5_5__regXZR,
2759 : Convert__Reg1_4__VecListTwo1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6,
2760 : Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2761 : Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2762 : Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
2763 : Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2764 : Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
2765 : Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
2766 : Convert__Reg1_1__imm_95_0,
2767 : Convert__Reg1_1__Tie0_2_2__SImm9s161_3,
2768 : Convert__Reg1_1__SImm9s161_2,
2769 : Convert__Reg1_1__Tie0_2_2__SImm9s161_2,
2770 : Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2771 : Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2772 : Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
2773 : Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2774 : Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2775 : Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4,
2776 : Convert__TypedVectorList3_081_0__IndexRange0_151_1__Reg1_3,
2777 : Convert__TypedVectorList3_0641_0__IndexRange0_11_1__Reg1_3,
2778 : Convert__TypedVectorList3_0161_0__IndexRange0_71_1__Reg1_3,
2779 : Convert__TypedVectorList3_0321_0__IndexRange0_31_1__Reg1_3,
2780 : Convert__VecListThree1281_1__IndexRange0_151_2__Reg1_4,
2781 : Convert__VecListThree1281_1__IndexRange0_11_2__Reg1_4,
2782 : Convert__VecListThree1281_1__IndexRange0_71_2__Reg1_4,
2783 : Convert__VecListThree1281_1__IndexRange0_31_2__Reg1_4,
2784 : Convert__Reg1_3__TypedVectorList3_081_0__IndexRange0_151_1__Tie0_4_4__regXZR,
2785 : Convert__Reg1_3__TypedVectorList3_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5,
2786 : Convert__Reg1_3__TypedVectorList3_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR,
2787 : Convert__Reg1_3__TypedVectorList3_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5,
2788 : Convert__Reg1_3__TypedVectorList3_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR,
2789 : Convert__Reg1_3__TypedVectorList3_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5,
2790 : Convert__Reg1_3__TypedVectorList3_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR,
2791 : Convert__Reg1_3__TypedVectorList3_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5,
2792 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_151_2__Tie0_5_5__regXZR,
2793 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6,
2794 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_11_2__Tie0_5_5__regXZR,
2795 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6,
2796 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_71_2__Tie0_5_5__regXZR,
2797 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6,
2798 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_31_2__Tie0_5_5__regXZR,
2799 : Convert__Reg1_4__VecListThree1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6,
2800 : Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2801 : Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2802 : Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
2803 : Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2804 : Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
2805 : Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
2806 : Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2807 : Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2808 : Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
2809 : Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2810 : Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2811 : Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4,
2812 : Convert__TypedVectorList4_081_0__IndexRange0_151_1__Reg1_3,
2813 : Convert__TypedVectorList4_0641_0__IndexRange0_11_1__Reg1_3,
2814 : Convert__TypedVectorList4_0161_0__IndexRange0_71_1__Reg1_3,
2815 : Convert__TypedVectorList4_0321_0__IndexRange0_31_1__Reg1_3,
2816 : Convert__VecListFour1281_1__IndexRange0_151_2__Reg1_4,
2817 : Convert__VecListFour1281_1__IndexRange0_11_2__Reg1_4,
2818 : Convert__VecListFour1281_1__IndexRange0_71_2__Reg1_4,
2819 : Convert__VecListFour1281_1__IndexRange0_31_2__Reg1_4,
2820 : Convert__Reg1_3__TypedVectorList4_081_0__IndexRange0_151_1__Tie0_4_4__regXZR,
2821 : Convert__Reg1_3__TypedVectorList4_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5,
2822 : Convert__Reg1_3__TypedVectorList4_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR,
2823 : Convert__Reg1_3__TypedVectorList4_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5,
2824 : Convert__Reg1_3__TypedVectorList4_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR,
2825 : Convert__Reg1_3__TypedVectorList4_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5,
2826 : Convert__Reg1_3__TypedVectorList4_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR,
2827 : Convert__Reg1_3__TypedVectorList4_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5,
2828 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_151_2__Tie0_5_5__regXZR,
2829 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6,
2830 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_11_2__Tie0_5_5__regXZR,
2831 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6,
2832 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_71_2__Tie0_5_5__regXZR,
2833 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6,
2834 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_31_2__Tie0_5_5__regXZR,
2835 : Convert__Reg1_4__VecListFour1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6,
2836 : Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2837 : Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4,
2838 : Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
2839 : Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2840 : Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4,
2841 : Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
2842 : Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2843 : Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4,
2844 : Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
2845 : Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0,
2846 : Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4,
2847 : Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4,
2848 : Convert__regWZR__Reg1_0__Reg1_2,
2849 : Convert__regXZR__Reg1_0__Reg1_2,
2850 : Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_5,
2851 : Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s161_4,
2852 : Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_4,
2853 : Convert__Reg1_0__Reg1_1__Reg1_2__GPR64sp01_4,
2854 : Convert__SVEVectorHReg1_0__SVEVectorBReg1_1,
2855 : Convert__SVEVectorSReg1_0__SVEVectorHReg1_1,
2856 : Convert__SVEVectorDReg1_0__SVEVectorSReg1_1,
2857 : Convert__Reg1_0__Tie0_1_1__Reg1_1,
2858 : Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7,
2859 : Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15,
2860 : Convert__VectorReg1281_1__VectorReg641_2__imm_95_0,
2861 : Convert__VectorReg1281_0__VectorReg641_2__imm_95_0,
2862 : Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0,
2863 : Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0,
2864 : Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31,
2865 : Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__regXZR,
2866 : Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__Reg1_4,
2867 : Convert__Reg1_0__Imm0_71_1__SysCR1_2__SysCR1_3__Imm0_71_4,
2868 : Convert__SVEVectorHReg1_0__SVEVectorList1161_1__SVEVectorHReg1_2,
2869 : Convert__SVEVectorSReg1_0__SVEVectorList1321_1__SVEVectorSReg1_2,
2870 : Convert__SVEVectorDReg1_0__SVEVectorList1641_1__SVEVectorDReg1_2,
2871 : Convert__SVEVectorBReg1_0__SVEVectorList181_1__SVEVectorBReg1_2,
2872 : Convert__VectorReg1281_1__VecListFour1281_2__VectorReg1281_3,
2873 : Convert__VectorReg1281_1__VecListOne1281_2__VectorReg1281_3,
2874 : Convert__VectorReg1281_1__VecListThree1281_2__VectorReg1281_3,
2875 : Convert__VectorReg1281_1__VecListTwo1281_2__VectorReg1281_3,
2876 : Convert__VectorReg641_1__VecListFour1281_2__VectorReg641_3,
2877 : Convert__VectorReg641_1__VecListOne1281_2__VectorReg641_3,
2878 : Convert__VectorReg641_1__VecListThree1281_2__VectorReg641_3,
2879 : Convert__VectorReg641_1__VecListTwo1281_2__VectorReg641_3,
2880 : Convert__VectorReg1281_0__TypedVectorList4_1681_2__VectorReg1281_3,
2881 : Convert__VectorReg1281_0__TypedVectorList1_1681_2__VectorReg1281_3,
2882 : Convert__VectorReg1281_0__TypedVectorList3_1681_2__VectorReg1281_3,
2883 : Convert__VectorReg1281_0__TypedVectorList2_1681_2__VectorReg1281_3,
2884 : Convert__VectorReg641_0__TypedVectorList4_1681_2__VectorReg641_3,
2885 : Convert__VectorReg641_0__TypedVectorList1_1681_2__VectorReg641_3,
2886 : Convert__VectorReg641_0__TypedVectorList3_1681_2__VectorReg641_3,
2887 : Convert__VectorReg641_0__TypedVectorList2_1681_2__VectorReg641_3,
2888 : Convert__Reg1_0__Imm0_311_1__BranchTarget141_2,
2889 : Convert__Reg1_0__Imm32_631_1__BranchTarget141_2,
2890 : Convert__GPR32as641_0__TBZImm0_311_1__BranchTarget141_2,
2891 : Convert__VectorReg1281_1__Tie0_2_2__VecListFour1281_2__VectorReg1281_3,
2892 : Convert__VectorReg1281_1__Tie0_2_2__VecListOne1281_2__VectorReg1281_3,
2893 : Convert__VectorReg1281_1__Tie0_2_2__VecListThree1281_2__VectorReg1281_3,
2894 : Convert__VectorReg1281_1__Tie0_2_2__VecListTwo1281_2__VectorReg1281_3,
2895 : Convert__VectorReg641_1__Tie0_2_2__VecListFour1281_2__VectorReg641_3,
2896 : Convert__VectorReg641_1__Tie0_2_2__VecListOne1281_2__VectorReg641_3,
2897 : Convert__VectorReg641_1__Tie0_2_2__VecListThree1281_2__VectorReg641_3,
2898 : Convert__VectorReg641_1__Tie0_2_2__VecListTwo1281_2__VectorReg641_3,
2899 : Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg1281_3,
2900 : Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg1281_3,
2901 : Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg1281_3,
2902 : Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg1281_3,
2903 : Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg641_3,
2904 : Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg641_3,
2905 : Convert__VectorReg641_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg641_3,
2906 : Convert__VectorReg641_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg641_3,
2907 : Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1__SVEPredicateHReg1_2,
2908 : Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1__SVEPredicateSReg1_2,
2909 : Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1__SVEPredicateDReg1_2,
2910 : Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_2,
2911 : Convert__regWZR__Reg1_0__LogicalImm321_1,
2912 : Convert__regXZR__Reg1_0__LogicalImm641_1,
2913 : Convert__regWZR__Reg1_0__Reg1_1__LogicalShifter321_2,
2914 : Convert__regXZR__Reg1_0__Reg1_1__LogicalShifter641_2,
2915 : Convert__SVEVectorHReg1_0__Tie0_1_2__Imm0_2551_2,
2916 : Convert__SVEVectorSReg1_0__Tie0_1_2__Imm0_2551_2,
2917 : Convert__SVEVectorDReg1_0__Tie0_1_2__Imm0_2551_2,
2918 : Convert__SVEVectorBReg1_0__Tie0_1_2__Imm0_2551_2,
2919 : Convert__imm_95_2,
2920 : Convert__imm_95_3,
2921 : Convert__SVEPredicateHReg1_0__Reg1_1__Reg1_2,
2922 : Convert__SVEPredicateSReg1_0__Reg1_1__Reg1_2,
2923 : Convert__SVEPredicateDReg1_0__Reg1_1__Reg1_2,
2924 : Convert__SVEPredicateBReg1_0__Reg1_1__Reg1_2,
2925 : Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__UImm61_6,
2926 : Convert__imm_95_1,
2927 : CVT_NUM_SIGNATURES
2928 : };
2929 :
2930 : } // end anonymous namespace
2931 :
2932 : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][13] = {
2933 : // Convert__Reg1_0__Reg1_1
2934 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
2935 : // Convert__VectorReg1281_1__VectorReg1281_2
2936 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
2937 : // Convert__VectorReg641_1__VectorReg641_2
2938 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
2939 : // Convert__VectorReg1281_0__VectorReg1281_2
2940 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
2941 : // Convert__VectorReg641_0__VectorReg641_2
2942 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
2943 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4
2944 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
2945 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4
2946 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
2947 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4
2948 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
2949 : // Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4
2950 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
2951 : // Convert__Reg1_0__Reg1_1__Reg1_2
2952 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2953 : // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16
2954 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_16, 0, CVT_Done },
2955 : // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_24
2956 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_24, 0, CVT_Done },
2957 : // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
2958 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
2959 : // Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2
2960 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmNegWithOptionalShiftOperands_LT_12_GT_, 3, CVT_Done },
2961 : // Convert__Reg1_0__Reg1_1__AddSubImm2_2
2962 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmWithOptionalShiftOperands_LT_12_GT_, 3, CVT_Done },
2963 : // Convert__SVEVectorHReg1_0__Tie0_1_2__SVEAddSubImm162_2
2964 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 3, CVT_Done },
2965 : // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorHReg1_2
2966 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2967 : // Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2
2968 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 3, CVT_Done },
2969 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorSReg1_2
2970 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2971 : // Convert__SVEVectorDReg1_0__Tie0_1_2__SVEAddSubImm642_2
2972 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 3, CVT_Done },
2973 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2
2974 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2975 : // Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2
2976 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 3, CVT_Done },
2977 : // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorBReg1_2
2978 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
2979 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3
2980 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
2981 : // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3
2982 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
2983 : // Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter321_3
2984 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
2985 : // Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3
2986 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtendOperands, 4, CVT_Done },
2987 : // Convert__Reg1_0__Reg1_1__Reg1_2__ArithmeticShifter641_3
2988 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
2989 : // Convert__Reg1_0__Reg1_1__Reg1_2__Extend641_3
2990 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtend64Operands, 4, CVT_Done },
2991 : // Convert__Reg1_0__Reg1_1__Reg1_2__ExtendLSL641_3
2992 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addExtend64Operands, 4, CVT_Done },
2993 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4
2994 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
2995 : // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4
2996 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
2997 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5
2998 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
2999 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5
3000 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
3001 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5
3002 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
3003 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorBReg1_5
3004 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
3005 : // Convert__Reg1_0__Reg1_1__UImm6s161_2__Imm0_151_3
3006 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmScaledOperands_LT_16_GT_, 3, CVT_95_addImmOperands, 4, CVT_Done },
3007 : // Convert__VectorReg641_1__VectorReg1281_2__VectorReg1281_3
3008 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
3009 : // Convert__VectorReg641_0__VectorReg1281_2__VectorReg1281_4
3010 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
3011 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3
3012 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
3013 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4
3014 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_Done },
3015 : // Convert__FPRAsmOperandFPR641_1__VectorReg1281_2
3016 : { CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
3017 : // Convert__FPRAsmOperandFPR641_0__VectorReg1281_1
3018 : { CVT_95_addRegOperands, 1, CVT_95_addVectorReg128Operands, 2, CVT_Done },
3019 : // Convert__Reg1_0__Reg1_1__SImm61_2
3020 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3021 : // Convert__Reg1_1__VectorReg1281_2
3022 : { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
3023 : // Convert__Reg1_1__VectorReg641_2
3024 : { CVT_95_Reg, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
3025 : // Convert__Reg1_0__VectorReg1281_1
3026 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_Done },
3027 : // Convert__Reg1_0__VectorReg641_1
3028 : { CVT_95_Reg, 1, CVT_95_addVectorReg64Operands, 2, CVT_Done },
3029 : // Convert__Reg1_0__AdrLabel1_1
3030 : { CVT_95_Reg, 1, CVT_95_addAdrLabelOperands, 2, CVT_Done },
3031 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL32161_3
3032 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3033 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL32321_3
3034 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3035 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL32641_3
3036 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3037 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_2__ZPRExtendLSL3281_3
3038 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3039 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL64161_3
3040 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3041 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL64321_3
3042 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3043 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL64641_3
3044 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3045 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendLSL6481_3
3046 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3047 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64161_3
3048 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3049 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64321_3
3050 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3051 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64641_3
3052 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3053 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW6481_3
3054 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3055 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64161_3
3056 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3057 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64321_3
3058 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3059 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64641_3
3060 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3061 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW6481_3
3062 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
3063 : // Convert__Reg1_0__AdrpLabel1_1
3064 : { CVT_95_Reg, 1, CVT_95_addAdrpLabelOperands, 2, CVT_Done },
3065 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2
3066 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
3067 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2
3068 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
3069 : // Convert__Reg1_0__Reg1_1__LogicalImm321_2
3070 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 3, CVT_Done },
3071 : // Convert__Reg1_0__Reg1_1__LogicalImm641_2
3072 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 3, CVT_Done },
3073 : // Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2
3074 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_, 3, CVT_Done },
3075 : // Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2
3076 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 3, CVT_Done },
3077 : // Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2
3078 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 3, CVT_Done },
3079 : // Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2
3080 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_, 3, CVT_Done },
3081 : // Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3
3082 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3083 : // Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3
3084 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3085 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateBReg1_5
3086 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3087 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_2
3088 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3089 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_2
3090 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3091 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2
3092 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3093 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_2
3094 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3095 : // Convert__Reg1_0__Reg1_1__Imm0_311_2__imm_95_31
3096 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_imm_95_31, 0, CVT_Done },
3097 : // Convert__Reg1_0__Reg1_1__Imm0_631_2__imm_95_63
3098 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_imm_95_63, 0, CVT_Done },
3099 : // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm1_161_2
3100 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3101 : // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVectorDReg1_2
3102 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3103 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm1_321_2
3104 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3105 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVectorDReg1_2
3106 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3107 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm1_641_2
3108 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3109 : // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm1_81_2
3110 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3111 : // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEVectorDReg1_2
3112 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3113 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_161_5
3114 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
3115 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5
3116 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
3117 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_321_5
3118 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
3119 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5
3120 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
3121 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_641_5
3122 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
3123 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm1_81_5
3124 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
3125 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5
3126 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_Done },
3127 : // Convert__Reg1_0
3128 : { CVT_95_Reg, 1, CVT_Done },
3129 : // Convert_NoOperands
3130 : { CVT_Done },
3131 : // Convert__BranchTarget261_0
3132 : { CVT_95_addBranchTarget26Operands, 1, CVT_Done },
3133 : // Convert__CondCode1_1__PCRelLabel191_2
3134 : { CVT_95_addCondCodeOperands, 2, CVT_95_addPCRelLabel19Operands, 3, CVT_Done },
3135 : // Convert__imm_95_0__imm_95_0__imm_95_0__imm_95_0
3136 : { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3137 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__VectorReg1281_6
3138 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorReg128Operands, 7, CVT_Done },
3139 : // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_311_2__Imm0_311_3
3140 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3141 : // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2__Imm0_631_3
3142 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3143 : // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__imm_95_0
3144 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
3145 : // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__imm_95_0
3146 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
3147 : // Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2
3148 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_, 3, CVT_Done },
3149 : // Convert__Reg1_0__Reg1_1__LogicalImm64Not1_2
3150 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_, 3, CVT_Done },
3151 : // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__imm_95_0
3152 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
3153 : // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__imm_95_0
3154 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
3155 : // Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2
3156 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_, 3, CVT_Done },
3157 : // Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2
3158 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_, 3, CVT_Done },
3159 : // Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2
3160 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_, 3, CVT_Done },
3161 : // Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2
3162 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_, 3, CVT_Done },
3163 : // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3
3164 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3165 : // Convert__VectorReg641_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3
3166 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3167 : // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecShifter1_3
3168 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3169 : // Convert__VectorReg1281_1__Tie0_2_2__Imm0_2551_2__LogicalVecHalfWordShifter1_3
3170 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3171 : // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3
3172 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3173 : // Convert__VectorReg1281_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
3174 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3175 : // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecShifter1_3
3176 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3177 : // Convert__VectorReg641_0__Tie0_1_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
3178 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
3179 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3
3180 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
3181 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4
3182 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
3183 : // Convert__Imm0_655351_0
3184 : { CVT_95_addImmOperands, 1, CVT_Done },
3185 : // Convert__SVEPredicateBReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4
3186 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3187 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4
3188 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3189 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__Tie0_1_6
3190 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Tied, Tie0_1_6, CVT_Done },
3191 : // Convert__imm_95_32
3192 : { CVT_imm_95_32, 0, CVT_Done },
3193 : // Convert__BTIHint1_0
3194 : { CVT_95_addBTIHintOperands, 1, CVT_Done },
3195 : // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_3
3196 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done },
3197 : // Convert__WSeqPair1_0__Tie0_1_1__WSeqPair1_1__Reg1_3
3198 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_Done },
3199 : // Convert__XSeqPair1_0__Tie0_1_1__XSeqPair1_1__Reg1_3
3200 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_Done },
3201 : // Convert__Reg1_0__PCRelLabel191_1
3202 : { CVT_95_Reg, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
3203 : // Convert__Reg1_0__Reg1_1__Imm0_151_2__CondCode1_3
3204 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
3205 : // Convert__Reg1_0__Imm0_311_1__Imm0_151_2__CondCode1_3
3206 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
3207 : // Convert__Reg1_0__Reg1_1__Reg1_1__CondCode1_2
3208 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 3, CVT_Done },
3209 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorHReg1_3
3210 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3211 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorSReg1_3
3212 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3213 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorDReg1_3
3214 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3215 : // Convert__Reg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorBReg1_3
3216 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3217 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorHReg1_3
3218 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3219 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorSReg1_3
3220 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3221 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorDReg1_3
3222 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3223 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_3__SVEVectorBReg1_3
3224 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_95_addRegOperands, 4, CVT_Done },
3225 : // Convert__imm_95_15
3226 : { CVT_imm_95_15, 0, CVT_Done },
3227 : // Convert__Imm0_151_0
3228 : { CVT_95_addImmOperands, 1, CVT_Done },
3229 : // Convert__Reg1_0__Reg1_2__Reg1_1
3230 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
3231 : // Convert__VectorReg1281_1__VectorReg1281_3__VectorReg1281_2
3232 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorReg128Operands, 3, CVT_Done },
3233 : // Convert__VectorReg641_1__VectorReg641_3__VectorReg641_2
3234 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 4, CVT_95_addVectorReg64Operands, 3, CVT_Done },
3235 : // Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2
3236 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorReg128Operands, 3, CVT_Done },
3237 : // Convert__VectorReg641_0__VectorReg641_4__VectorReg641_2
3238 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 5, CVT_95_addVectorReg64Operands, 3, CVT_Done },
3239 : // Convert__regWZR__Reg1_0__Reg1_1__imm_95_16
3240 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_16, 0, CVT_Done },
3241 : // Convert__regXZR__Reg1_0__Reg1_1__imm_95_24
3242 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_24, 0, CVT_Done },
3243 : // Convert__regWZR__Reg1_0__Reg1_1__imm_95_0
3244 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
3245 : // Convert__regWZR__Reg1_0__AddSubImmNeg2_1
3246 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addImmNegWithOptionalShiftOperands_LT_12_GT_, 2, CVT_Done },
3247 : // Convert__regWZR__Reg1_0__AddSubImm2_1
3248 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addImmWithOptionalShiftOperands_LT_12_GT_, 2, CVT_Done },
3249 : // Convert__regXZR__Reg1_0__Reg1_1__imm_95_0
3250 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
3251 : // Convert__regXZR__Reg1_0__AddSubImmNeg2_1
3252 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addImmNegWithOptionalShiftOperands_LT_12_GT_, 2, CVT_Done },
3253 : // Convert__regXZR__Reg1_0__AddSubImm2_1
3254 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addImmWithOptionalShiftOperands_LT_12_GT_, 2, CVT_Done },
3255 : // Convert__regWZR__Reg1_0__Reg1_1__ArithmeticShifter321_2
3256 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
3257 : // Convert__regWZR__Reg1_0__Reg1_1__Extend1_2
3258 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtendOperands, 3, CVT_Done },
3259 : // Convert__regXZR__Reg1_0__Reg1_1__ArithmeticShifter641_2
3260 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
3261 : // Convert__regXZR__Reg1_0__Reg1_1__Extend1_2
3262 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtendOperands, 3, CVT_Done },
3263 : // Convert__regXZR__Reg1_0__Reg1_1__ExtendLSL641_2
3264 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addExtend64Operands, 3, CVT_Done },
3265 : // Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__SImm51_5
3266 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3267 : // Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__SVEVectorHReg1_5
3268 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3269 : // Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__SVEVectorDReg1_5
3270 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3271 : // Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SImm51_5
3272 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3273 : // Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_5
3274 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3275 : // Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__SVEVectorDReg1_5
3276 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3277 : // Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SImm51_5
3278 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3279 : // Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_5
3280 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3281 : // Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__SImm51_5
3282 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3283 : // Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__SVEVectorDReg1_5
3284 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3285 : // Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__SVEVectorBReg1_5
3286 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3287 : // Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4__Imm0_1271_5
3288 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3289 : // Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4__Imm0_1271_5
3290 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3291 : // Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4__Imm0_1271_5
3292 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3293 : // Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4__Imm0_1271_5
3294 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3295 : // Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_5__SVEVectorHReg1_4
3296 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 5, CVT_Done },
3297 : // Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__SVEVectorSReg1_4
3298 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 5, CVT_Done },
3299 : // Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__SVEVectorDReg1_4
3300 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 5, CVT_Done },
3301 : // Convert__SVEPredicateBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_5__SVEVectorBReg1_4
3302 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addRegOperands, 5, CVT_Done },
3303 : // Convert__regXZR__Reg1_0__Reg1_1
3304 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
3305 : // Convert__Reg1_0__imm_95_31__imm_95_1
3306 : { CVT_95_Reg, 1, CVT_imm_95_31, 0, CVT_imm_95_1, 0, CVT_Done },
3307 : // Convert__Reg1_0__SVEPattern1_1__imm_95_1
3308 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3309 : // Convert__Reg1_0__SVEPattern1_1__Imm1_161_3
3310 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3311 : // Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateHReg1_2
3312 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3313 : // Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateSReg1_2
3314 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3315 : // Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateDReg1_2
3316 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3317 : // Convert__Reg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_2
3318 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3319 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_2
3320 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3321 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_2
3322 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
3323 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4
3324 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 5, CVT_Done },
3325 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm162_4
3326 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3327 : // Convert__SVEVectorHReg1_0__SVEPredicateAnyReg1_1__SVECpyImm162_4
3328 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3329 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4
3330 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 5, CVT_Done },
3331 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm322_4
3332 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3333 : // Convert__SVEVectorSReg1_0__SVEPredicateAnyReg1_1__SVECpyImm322_4
3334 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3335 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4
3336 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 5, CVT_Done },
3337 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm642_4
3338 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3339 : // Convert__SVEVectorDReg1_0__SVEPredicateAnyReg1_1__SVECpyImm642_4
3340 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3341 : // Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4
3342 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_Reg, 5, CVT_Done },
3343 : // Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__SVECpyImm82_4
3344 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3345 : // Convert__SVEVectorBReg1_0__SVEPredicateAnyReg1_1__SVECpyImm82_4
3346 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 5, CVT_Done },
3347 : // Convert__imm_95_20
3348 : { CVT_imm_95_20, 0, CVT_Done },
3349 : // Convert__Reg1_0__Reg1_1__Reg1_2__CondCode1_3
3350 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 4, CVT_Done },
3351 : // Convert__Reg1_0__regWZR__regWZR__CondCode1_1
3352 : { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_regWZR, 0, CVT_95_addCondCodeOperands, 2, CVT_Done },
3353 : // Convert__Reg1_0__regXZR__regXZR__CondCode1_1
3354 : { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_regXZR, 0, CVT_95_addCondCodeOperands, 2, CVT_Done },
3355 : // Convert__imm_95_0
3356 : { CVT_imm_95_0, 0, CVT_Done },
3357 : // Convert__Reg1_0__Tie0_1_1__imm_95_31__imm_95_1
3358 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_31, 0, CVT_imm_95_1, 0, CVT_Done },
3359 : // Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1
3360 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3361 : // Convert__Reg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3
3362 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3363 : // Convert__SVEVectorDReg1_0__Tie0_1_1__imm_95_31__imm_95_1
3364 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_31, 0, CVT_imm_95_1, 0, CVT_Done },
3365 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1
3366 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3367 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3
3368 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3369 : // Convert__SVEVectorHReg1_0__Tie0_1_1__imm_95_31__imm_95_1
3370 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_31, 0, CVT_imm_95_1, 0, CVT_Done },
3371 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1
3372 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3373 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3
3374 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3375 : // Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_1
3376 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
3377 : // Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_1
3378 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
3379 : // Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_1
3380 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
3381 : // Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_1
3382 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
3383 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1
3384 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_Done },
3385 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1
3386 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_Done },
3387 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1
3388 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_Done },
3389 : // Convert__SVEVectorSReg1_0__Tie0_1_1__imm_95_31__imm_95_1
3390 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_31, 0, CVT_imm_95_1, 0, CVT_Done },
3391 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__imm_95_1
3392 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
3393 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPattern1_1__Imm1_161_3
3394 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
3395 : // Convert__Barrier1_0
3396 : { CVT_95_addBarrierOperands, 1, CVT_Done },
3397 : // Convert__SVEVectorHReg1_0__Reg1_1
3398 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
3399 : // Convert__SVEVectorHReg1_0__SVECpyImm162_1
3400 : { CVT_95_addRegOperands, 1, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 2, CVT_Done },
3401 : // Convert__SVEVectorSReg1_0__Reg1_1
3402 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
3403 : // Convert__SVEVectorSReg1_0__SVECpyImm322_1
3404 : { CVT_95_addRegOperands, 1, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 2, CVT_Done },
3405 : // Convert__SVEVectorDReg1_0__Reg1_1
3406 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
3407 : // Convert__SVEVectorDReg1_0__SVECpyImm642_1
3408 : { CVT_95_addRegOperands, 1, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 2, CVT_Done },
3409 : // Convert__SVEVectorBReg1_0__Reg1_1
3410 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
3411 : // Convert__SVEVectorBReg1_0__SVECpyImm82_1
3412 : { CVT_95_addRegOperands, 1, CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_, 2, CVT_Done },
3413 : // Convert__VectorReg1281_1__Reg1_2
3414 : { CVT_95_addVectorReg128Operands, 2, CVT_95_Reg, 3, CVT_Done },
3415 : // Convert__VectorReg641_1__Reg1_2
3416 : { CVT_95_addVectorReg64Operands, 2, CVT_95_Reg, 3, CVT_Done },
3417 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_71_2
3418 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3419 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_31_2
3420 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3421 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_11_2
3422 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3423 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_151_2
3424 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3425 : // Convert__VectorReg1281_0__Reg1_2
3426 : { CVT_95_addVectorReg128Operands, 1, CVT_95_Reg, 3, CVT_Done },
3427 : // Convert__VectorReg641_0__Reg1_2
3428 : { CVT_95_addVectorReg64Operands, 1, CVT_95_Reg, 3, CVT_Done },
3429 : // Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2
3430 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3431 : // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEIndexRange0_311_2
3432 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3433 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEIndexRange0_151_2
3434 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3435 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEIndexRange0_71_2
3436 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3437 : // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__SVEIndexRange0_631_2
3438 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3439 : // Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_151_3
3440 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3441 : // Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_11_3
3442 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3443 : // Convert__VectorReg641_1__VectorReg1281_2__IndexRange0_31_3
3444 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3445 : // Convert__VectorReg641_1__VectorReg1281_2__IndexRange0_71_3
3446 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3447 : // Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_31_3
3448 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3449 : // Convert__VectorReg641_1__VectorReg1281_2__IndexRange0_151_3
3450 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3451 : // Convert__VectorReg1281_1__VectorReg1281_2__IndexRange0_71_3
3452 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3453 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_71_3
3454 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3455 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_31_3
3456 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3457 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_11_3
3458 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3459 : // Convert__Reg1_0__VectorReg1281_1__IndexRange0_151_3
3460 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3461 : // Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_151_4
3462 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3463 : // Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_11_4
3464 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3465 : // Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_31_4
3466 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3467 : // Convert__VectorReg1281_0__VectorReg1281_2__IndexRange0_71_4
3468 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3469 : // Convert__VectorReg641_0__VectorReg1281_2__IndexRange0_31_4
3470 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3471 : // Convert__VectorReg641_0__VectorReg1281_2__IndexRange0_71_4
3472 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3473 : // Convert__VectorReg641_0__VectorReg1281_2__IndexRange0_151_4
3474 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3475 : // Convert__SVEVectorHReg1_0__SVELogicalImm161_1
3476 : { CVT_95_addRegOperands, 1, CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_, 2, CVT_Done },
3477 : // Convert__SVEVectorSReg1_0__SVELogicalImm321_1
3478 : { CVT_95_addRegOperands, 1, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
3479 : // Convert__SVEVectorDReg1_0__LogicalImm641_1
3480 : { CVT_95_addRegOperands, 1, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
3481 : // Convert__SVEVectorBReg1_0__SVELogicalImm81_1
3482 : { CVT_95_addRegOperands, 1, CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_, 2, CVT_Done },
3483 : // Convert__imm_95_16
3484 : { CVT_imm_95_16, 0, CVT_Done },
3485 : // Convert__SVEVectorBReg1_0__Tie0_1_2__SVEVectorBReg1_2__Imm0_2551_3
3486 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3487 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__Imm1_4
3488 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addImmOperands, 5, CVT_Done },
3489 : // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__Imm1_4
3490 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addImmOperands, 5, CVT_Done },
3491 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__Imm1_6
3492 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addImmOperands, 7, CVT_Done },
3493 : // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__Imm1_6
3494 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addImmOperands, 7, CVT_Done },
3495 : // Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_311_3
3496 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3497 : // Convert__Reg1_0__Reg1_1__Reg1_2__Imm0_631_3
3498 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3499 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5
3500 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_, 6, CVT_Done },
3501 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5
3502 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_, 6, CVT_Done },
3503 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5
3504 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_, 6, CVT_Done },
3505 : // Convert__FPRAsmOperandFPR161_1__VectorReg641_2
3506 : { CVT_95_addRegOperands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
3507 : // Convert__FPRAsmOperandFPR321_1__VectorReg641_2
3508 : { CVT_95_addRegOperands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
3509 : // Convert__FPRAsmOperandFPR161_0__VectorReg641_1
3510 : { CVT_95_addRegOperands, 1, CVT_95_addVectorReg64Operands, 2, CVT_Done },
3511 : // Convert__FPRAsmOperandFPR321_0__VectorReg641_1
3512 : { CVT_95_addRegOperands, 1, CVT_95_addVectorReg64Operands, 2, CVT_Done },
3513 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__ComplexRotationOdd1_4
3514 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
3515 : // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_3__ComplexRotationOdd1_4
3516 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
3517 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__ComplexRotationOdd1_6
3518 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
3519 : // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__ComplexRotationOdd1_6
3520 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
3521 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorHReg1_5__ComplexRotationOdd1_6
3522 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
3523 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorSReg1_5__ComplexRotationOdd1_6
3524 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
3525 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEVectorDReg1_5__ComplexRotationOdd1_6
3526 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addRegOperands, 6, CVT_95_addComplexRotationOddOperands, 7, CVT_Done },
3527 : // Convert__SVEPredicateHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4
3528 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3529 : // Convert__SVEPredicateSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4
3530 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3531 : // Convert__SVEPredicateDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4
3532 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3533 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__ComplexRotationEven1_4
3534 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
3535 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg641_3__ComplexRotationEven1_4
3536 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
3537 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_31_3__ComplexRotationEven1_4
3538 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
3539 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector4bSReg1_2__IndexRange0_11_3__ComplexRotationEven1_4
3540 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
3541 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__IndexRange0_11_4__ComplexRotationEven1_5
3542 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3543 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_11_4__ComplexRotationEven1_5
3544 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3545 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_31_4__ComplexRotationEven1_5
3546 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3547 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__ComplexRotationEven1_6
3548 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
3549 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg641_4__ComplexRotationEven1_6
3550 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
3551 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorHReg1_4__SVEVectorHReg1_5__ComplexRotationEven1_6
3552 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
3553 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5__ComplexRotationEven1_6
3554 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
3555 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5__ComplexRotationEven1_6
3556 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_95_addComplexRotationEvenOperands, 7, CVT_Done },
3557 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_11_6__ComplexRotationEven1_7
3558 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
3559 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_31_6__ComplexRotationEven1_7
3560 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
3561 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__IndexRange0_11_6__ComplexRotationEven1_7
3562 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_95_addComplexRotationEvenOperands, 8, CVT_Done },
3563 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__FPImm1_4
3564 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addFPImmOperands, 5, CVT_Done },
3565 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__FPImm1_4
3566 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addFPImmOperands, 5, CVT_Done },
3567 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__FPImm1_4
3568 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addFPImmOperands, 5, CVT_Done },
3569 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4
3570 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3571 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4
3572 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3573 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4
3574 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3575 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4
3576 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3577 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4
3578 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3579 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4
3580 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
3581 : // Convert__VectorReg1281_0__VectorReg641_2
3582 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
3583 : // Convert__VectorReg641_0__VectorReg1281_2
3584 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_Done },
3585 : // Convert__Reg1_0__Reg1_1__Imm1_161_2
3586 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3587 : // Convert__Reg1_0__Reg1_1__Imm1_321_2
3588 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3589 : // Convert__Reg1_0__Reg1_1__Imm1_641_2
3590 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3591 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_641_3
3592 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3593 : // Convert__VectorReg641_1__VectorReg641_2__Imm1_321_3
3594 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3595 : // Convert__VectorReg641_1__VectorReg641_2__Imm1_161_3
3596 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3597 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_321_3
3598 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3599 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_161_3
3600 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3601 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_641_4
3602 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3603 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_321_4
3604 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3605 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_161_4
3606 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3607 : // Convert__VectorReg641_0__VectorReg641_2__Imm1_321_4
3608 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3609 : // Convert__VectorReg641_0__VectorReg641_2__Imm1_161_4
3610 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
3611 : // Convert__SVEVectorHReg1_0__FPImm1_1
3612 : { CVT_95_addRegOperands, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
3613 : // Convert__SVEVectorSReg1_0__FPImm1_1
3614 : { CVT_95_addRegOperands, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
3615 : // Convert__SVEVectorDReg1_0__FPImm1_1
3616 : { CVT_95_addRegOperands, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
3617 : // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1
3618 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
3619 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1
3620 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
3621 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1
3622 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
3623 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorHReg1_4__SVEVectorHReg1_5
3624 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3625 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorSReg1_4__SVEVectorSReg1_5
3626 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3627 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorDReg1_4__SVEVectorDReg1_5
3628 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
3629 : // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3
3630 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3631 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5
3632 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_zero_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_, 6, CVT_Done },
3633 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5
3634 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_zero_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_, 6, CVT_Done },
3635 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5
3636 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_zero_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_, 6, CVT_Done },
3637 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3
3638 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3639 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorSReg1_1__SVEVector3bSReg1_2__IndexRange0_31_3
3640 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3641 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3
3642 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3643 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_11_4
3644 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3645 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4
3646 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3647 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4
3648 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3649 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorReg1281_3__IndexRange0_31_4
3650 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3651 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4
3652 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3653 : // Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR641_2__VectorReg1281_3__IndexRange0_11_4
3654 : { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3655 : // Convert__FPRAsmOperandFPR161_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4
3656 : { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3657 : // Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4
3658 : { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3659 : // Convert__FPRAsmOperandFPR161_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4
3660 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3661 : // Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4
3662 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3663 : // Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR641_1__VectorReg1281_2__IndexRange0_11_4
3664 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3665 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_11_6
3666 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3667 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_31_6
3668 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3669 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorRegLo1_4__IndexRange0_71_6
3670 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3671 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6
3672 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3673 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6
3674 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3675 : // Convert__imm_95_0__imm_95_0__imm_95_0
3676 : { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3677 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__IndexRange0_71_3
3678 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3679 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__VectorReg1281_4__IndexRange0_71_6
3680 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3681 : // Convert__Reg1_0__FPImm1_1
3682 : { CVT_95_Reg, 1, CVT_95_addFPImmOperands, 2, CVT_Done },
3683 : // Convert__VectorReg1281_1__FPImm1_2
3684 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addFPImmOperands, 3, CVT_Done },
3685 : // Convert__VectorReg641_1__FPImm1_2
3686 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addFPImmOperands, 3, CVT_Done },
3687 : // Convert__Reg1_0__regWZR
3688 : { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_Done },
3689 : // Convert__Reg1_0__regXZR
3690 : { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_Done },
3691 : // Convert__VectorReg1281_0__FPImm1_2
3692 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addFPImmOperands, 3, CVT_Done },
3693 : // Convert__VectorReg641_0__FPImm1_2
3694 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addFPImmOperands, 3, CVT_Done },
3695 : // Convert__SVEVectorHReg1_0__imm_95_0__imm_95_0
3696 : { CVT_95_addRegOperands, 1, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3697 : // Convert__SVEVectorSReg1_0__imm_95_0__imm_95_0
3698 : { CVT_95_addRegOperands, 1, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3699 : // Convert__SVEVectorDReg1_0__imm_95_0__imm_95_0
3700 : { CVT_95_addRegOperands, 1, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3701 : // Convert__Reg1_1__VectorReg1281_2__IndexRange1_11_3
3702 : { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3703 : // Convert__VectorReg1281_1__Reg1_3__IndexRange1_11_2
3704 : { CVT_95_addVectorReg128Operands, 2, CVT_95_Reg, 4, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3705 : // Convert__Reg1_0__VectorReg1281_1__IndexRange1_11_3
3706 : { CVT_95_Reg, 1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3707 : // Convert__VectorReg1281_0__Reg1_3__IndexRange1_11_2
3708 : { CVT_95_addVectorReg128Operands, 1, CVT_95_Reg, 4, CVT_95_addVectorIndexOperands, 3, CVT_Done },
3709 : // Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__imm_95_0__imm_95_0
3710 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3711 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__imm_95_0__imm_95_0
3712 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3713 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEPredicateAnyReg1_1__imm_95_0__imm_95_0
3714 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
3715 : // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__SVEVector3bHReg1_2__IndexRange0_71_3
3716 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3717 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__SVEVector3bSReg1_2__IndexRange0_31_3
3718 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3719 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3
3720 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
3721 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__IndexRange0_11_4
3722 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3723 : // Convert__VectorReg641_1__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4
3724 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3725 : // Convert__VectorReg641_1__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4
3726 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3727 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3__IndexRange0_31_4
3728 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3729 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4
3730 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3731 : // Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR641_2__VectorReg1281_3__IndexRange0_11_4
3732 : { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3733 : // Convert__FPRAsmOperandFPR161_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4
3734 : { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3735 : // Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4
3736 : { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3737 : // Convert__FPRAsmOperandFPR161_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4
3738 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3739 : // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4
3740 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3741 : // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__VectorReg1281_2__IndexRange0_11_4
3742 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3743 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfTwo1_5
3744 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_two_GT_, 6, CVT_Done },
3745 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfTwo1_5
3746 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_two_GT_, 6, CVT_Done },
3747 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfTwo1_5
3748 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_two_GT_, 6, CVT_Done },
3749 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__IndexRange0_11_6
3750 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3751 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__IndexRange0_31_6
3752 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3753 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorRegLo1_4__IndexRange0_71_6
3754 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3755 : // Convert__VectorReg641_0__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6
3756 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3757 : // Convert__VectorReg641_0__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6
3758 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
3759 : // Convert__SVEVectorHReg1_0__Tie0_1_2__SVEVectorHReg1_2__Imm0_71_3
3760 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3761 : // Convert__SVEVectorSReg1_0__Tie0_1_2__SVEVectorSReg1_2__Imm0_71_3
3762 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3763 : // Convert__SVEVectorDReg1_0__Tie0_1_2__SVEVectorDReg1_2__Imm0_71_3
3764 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addRegOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3765 : // Convert__Imm0_1271_0
3766 : { CVT_95_addImmOperands, 1, CVT_Done },
3767 : // Convert__SVEVectorHReg1_0__Reg1_1__Reg1_2
3768 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3769 : // Convert__SVEVectorHReg1_0__Reg1_1__SImm51_2
3770 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3771 : // Convert__SVEVectorHReg1_0__SImm51_1__Reg1_2
3772 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
3773 : // Convert__SVEVectorHReg1_0__SImm51_1__SImm51_2
3774 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3775 : // Convert__SVEVectorSReg1_0__Reg1_1__Reg1_2
3776 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3777 : // Convert__SVEVectorSReg1_0__Reg1_1__SImm51_2
3778 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3779 : // Convert__SVEVectorSReg1_0__SImm51_1__Reg1_2
3780 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
3781 : // Convert__SVEVectorSReg1_0__SImm51_1__SImm51_2
3782 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3783 : // Convert__SVEVectorDReg1_0__Reg1_1__Reg1_2
3784 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3785 : // Convert__SVEVectorDReg1_0__Reg1_1__SImm51_2
3786 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3787 : // Convert__SVEVectorDReg1_0__SImm51_1__Reg1_2
3788 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
3789 : // Convert__SVEVectorDReg1_0__SImm51_1__SImm51_2
3790 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3791 : // Convert__SVEVectorBReg1_0__Reg1_1__Reg1_2
3792 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3793 : // Convert__SVEVectorBReg1_0__Reg1_1__SImm51_2
3794 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
3795 : // Convert__SVEVectorBReg1_0__SImm51_1__Reg1_2
3796 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
3797 : // Convert__SVEVectorBReg1_0__SImm51_1__SImm51_2
3798 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3799 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_3
3800 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3801 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_3
3802 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3803 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_3
3804 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3805 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_3
3806 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3807 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_151_2__Reg1_3
3808 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3809 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_11_2__Reg1_3
3810 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3811 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_71_2__Reg1_3
3812 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3813 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_31_2__Reg1_3
3814 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 4, CVT_Done },
3815 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_151_2__VectorReg1281_3__IndexRange0_151_4
3816 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3817 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_4
3818 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3819 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_4
3820 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3821 : // Convert__VectorReg1281_1__Tie0_2_2__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_4
3822 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
3823 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_151_2__VectorReg1281_3__IndexRange0_151_5
3824 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
3825 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_11_2__VectorReg1281_3__IndexRange0_11_5
3826 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
3827 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_71_2__VectorReg1281_3__IndexRange0_71_5
3828 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
3829 : // Convert__VectorReg1281_0__Tie0_1_1__IndexRange0_31_2__VectorReg1281_3__IndexRange0_31_5
3830 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 6, CVT_Done },
3831 : // Convert__SVEVectorHReg1_0__Tie0_1_1__Reg1_1
3832 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
3833 : // Convert__SVEVectorSReg1_0__Tie0_1_1__Reg1_1
3834 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
3835 : // Convert__SVEVectorDReg1_0__Tie0_1_1__Reg1_1
3836 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
3837 : // Convert__SVEVectorBReg1_0__Tie0_1_1__Reg1_1
3838 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
3839 : // Convert__Reg1_0__Reg1_1__regXZR
3840 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regXZR, 0, CVT_Done },
3841 : // Convert__TypedVectorList4_1681_0__Reg1_2
3842 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3843 : // Convert__TypedVectorList4_1641_0__Reg1_2
3844 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3845 : // Convert__TypedVectorList4_2641_0__Reg1_2
3846 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3847 : // Convert__TypedVectorList4_2321_0__Reg1_2
3848 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3849 : // Convert__TypedVectorList4_4161_0__Reg1_2
3850 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3851 : // Convert__TypedVectorList4_4321_0__Reg1_2
3852 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3853 : // Convert__TypedVectorList4_881_0__Reg1_2
3854 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3855 : // Convert__TypedVectorList4_8161_0__Reg1_2
3856 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3857 : // Convert__TypedVectorList1_1681_0__Reg1_2
3858 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3859 : // Convert__TypedVectorList1_1641_0__Reg1_2
3860 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3861 : // Convert__TypedVectorList1_2641_0__Reg1_2
3862 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3863 : // Convert__TypedVectorList1_2321_0__Reg1_2
3864 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3865 : // Convert__TypedVectorList1_4161_0__Reg1_2
3866 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3867 : // Convert__TypedVectorList1_4321_0__Reg1_2
3868 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3869 : // Convert__TypedVectorList1_881_0__Reg1_2
3870 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3871 : // Convert__TypedVectorList1_8161_0__Reg1_2
3872 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3873 : // Convert__TypedVectorList3_1681_0__Reg1_2
3874 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3875 : // Convert__TypedVectorList3_1641_0__Reg1_2
3876 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3877 : // Convert__TypedVectorList3_2641_0__Reg1_2
3878 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3879 : // Convert__TypedVectorList3_2321_0__Reg1_2
3880 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3881 : // Convert__TypedVectorList3_4161_0__Reg1_2
3882 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3883 : // Convert__TypedVectorList3_4321_0__Reg1_2
3884 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3885 : // Convert__TypedVectorList3_881_0__Reg1_2
3886 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3887 : // Convert__TypedVectorList3_8161_0__Reg1_2
3888 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3889 : // Convert__TypedVectorList2_1681_0__Reg1_2
3890 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3891 : // Convert__TypedVectorList2_1641_0__Reg1_2
3892 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3893 : // Convert__TypedVectorList2_2641_0__Reg1_2
3894 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3895 : // Convert__TypedVectorList2_2321_0__Reg1_2
3896 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3897 : // Convert__TypedVectorList2_4161_0__Reg1_2
3898 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3899 : // Convert__TypedVectorList2_4321_0__Reg1_2
3900 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3901 : // Convert__TypedVectorList2_881_0__Reg1_2
3902 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3903 : // Convert__TypedVectorList2_8161_0__Reg1_2
3904 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_Reg, 3, CVT_Done },
3905 : // Convert__VecListFour1281_1__Reg1_3
3906 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3907 : // Convert__VecListOne1281_1__Reg1_3
3908 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3909 : // Convert__VecListThree1281_1__Reg1_3
3910 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3911 : // Convert__VecListTwo1281_1__Reg1_3
3912 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3913 : // Convert__VecListFour641_1__Reg1_3
3914 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3915 : // Convert__VecListOne641_1__Reg1_3
3916 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3917 : // Convert__VecListThree641_1__Reg1_3
3918 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3919 : // Convert__VecListTwo641_1__Reg1_3
3920 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 2, CVT_95_Reg, 4, CVT_Done },
3921 : // Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR
3922 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3923 : // Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4
3924 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3925 : // Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR
3926 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3927 : // Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4
3928 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3929 : // Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR
3930 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3931 : // Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4
3932 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3933 : // Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR
3934 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3935 : // Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4
3936 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3937 : // Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR
3938 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3939 : // Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4
3940 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3941 : // Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR
3942 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3943 : // Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4
3944 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3945 : // Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR
3946 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3947 : // Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4
3948 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3949 : // Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR
3950 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3951 : // Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4
3952 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3953 : // Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR
3954 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3955 : // Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4
3956 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3957 : // Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR
3958 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3959 : // Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4
3960 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3961 : // Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR
3962 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3963 : // Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4
3964 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3965 : // Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR
3966 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3967 : // Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4
3968 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3969 : // Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR
3970 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3971 : // Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4
3972 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3973 : // Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR
3974 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3975 : // Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4
3976 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3977 : // Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR
3978 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3979 : // Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4
3980 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3981 : // Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR
3982 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3983 : // Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4
3984 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3985 : // Convert__TypedVectorList1_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3
3986 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
3987 : // Convert__TypedVectorList1_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3
3988 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
3989 : // Convert__TypedVectorList1_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3
3990 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
3991 : // Convert__TypedVectorList1_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3
3992 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
3993 : // Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__regXZR
3994 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3995 : // Convert__Reg1_2__TypedVectorList3_1681_0__Tie0_3_3__Reg1_4
3996 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
3997 : // Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR
3998 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
3999 : // Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4
4000 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4001 : // Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__regXZR
4002 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4003 : // Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__Reg1_4
4004 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4005 : // Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__regXZR
4006 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4007 : // Convert__Reg1_2__TypedVectorList3_2321_0__Tie0_3_3__Reg1_4
4008 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4009 : // Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__regXZR
4010 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4011 : // Convert__Reg1_2__TypedVectorList3_4161_0__Tie0_3_3__Reg1_4
4012 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4013 : // Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__regXZR
4014 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4015 : // Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__Reg1_4
4016 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4017 : // Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__regXZR
4018 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4019 : // Convert__Reg1_2__TypedVectorList3_881_0__Tie0_3_3__Reg1_4
4020 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4021 : // Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__regXZR
4022 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4023 : // Convert__Reg1_2__TypedVectorList3_8161_0__Tie0_3_3__Reg1_4
4024 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4025 : // Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__regXZR
4026 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4027 : // Convert__Reg1_2__TypedVectorList2_1681_0__Tie0_3_3__Reg1_4
4028 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4029 : // Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR
4030 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4031 : // Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4
4032 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4033 : // Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__regXZR
4034 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4035 : // Convert__Reg1_2__TypedVectorList2_2641_0__Tie0_3_3__Reg1_4
4036 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4037 : // Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__regXZR
4038 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4039 : // Convert__Reg1_2__TypedVectorList2_2321_0__Tie0_3_3__Reg1_4
4040 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4041 : // Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__regXZR
4042 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4043 : // Convert__Reg1_2__TypedVectorList2_4161_0__Tie0_3_3__Reg1_4
4044 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4045 : // Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__regXZR
4046 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4047 : // Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__Reg1_4
4048 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4049 : // Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__regXZR
4050 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4051 : // Convert__Reg1_2__TypedVectorList2_881_0__Tie0_3_3__Reg1_4
4052 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4053 : // Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__regXZR
4054 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_regXZR, 0, CVT_Done },
4055 : // Convert__Reg1_2__TypedVectorList2_8161_0__Tie0_3_3__Reg1_4
4056 : { CVT_95_Reg, 3, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_3_3, CVT_95_Reg, 5, CVT_Done },
4057 : // Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR
4058 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4059 : // Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5
4060 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4061 : // Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__regXZR
4062 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4063 : // Convert__Reg1_3__VecListOne1281_1__Tie0_4_4__Reg1_5
4064 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4065 : // Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR
4066 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4067 : // Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5
4068 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4069 : // Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR
4070 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4071 : // Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5
4072 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4073 : // Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR
4074 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4075 : // Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5
4076 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4077 : // Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR
4078 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4079 : // Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5
4080 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4081 : // Convert__Reg1_3__VecListThree641_1__Tie0_4_4__regXZR
4082 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4083 : // Convert__Reg1_3__VecListThree641_1__Tie0_4_4__Reg1_5
4084 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4085 : // Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__regXZR
4086 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4087 : // Convert__Reg1_3__VecListTwo641_1__Tie0_4_4__Reg1_5
4088 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4089 : // Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4
4090 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4091 : // Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4
4092 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4093 : // Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4
4094 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4095 : // Convert__VecListOne1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4
4096 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4097 : // Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR
4098 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4099 : // Convert__Reg1_3__TypedVectorList1_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5
4100 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4101 : // Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR
4102 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4103 : // Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5
4104 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4105 : // Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR
4106 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4107 : // Convert__Reg1_3__TypedVectorList1_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5
4108 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4109 : // Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR
4110 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4111 : // Convert__Reg1_3__TypedVectorList1_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5
4112 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4113 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR
4114 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4115 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6
4116 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4117 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR
4118 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4119 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6
4120 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4121 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR
4122 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4123 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6
4124 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4125 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR
4126 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4127 : // Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6
4128 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4129 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4130 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4131 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4132 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4133 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0
4134 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
4135 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4136 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4137 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0
4138 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
4139 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4140 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4141 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4142 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4143 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4144 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4145 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4146 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4147 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0
4148 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
4149 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4150 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4151 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0
4152 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_imm_95_0, 0, CVT_Done },
4153 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4154 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4155 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4156 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4157 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6
4158 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4159 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6
4160 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4161 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6
4162 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4163 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4164 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4165 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6
4166 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4167 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6
4168 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4169 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6
4170 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4171 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6
4172 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4173 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4174 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4175 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4176 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4177 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4178 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4179 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4180 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4181 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW328Only1_6
4182 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4183 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW328Only1_6
4184 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4185 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__Imm0_311_6
4186 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4187 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4188 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4189 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL6481_6
4190 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4191 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW648Only1_6
4192 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4193 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW648Only1_6
4194 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4195 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Imm0_311_6
4196 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmOperands, 7, CVT_Done },
4197 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4198 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4199 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4200 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4201 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4202 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4203 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4204 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4205 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4206 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4207 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4208 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4209 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4210 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4211 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6
4212 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4213 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
4214 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4215 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6
4216 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4217 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6
4218 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4219 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6
4220 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4221 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6
4222 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4223 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6
4224 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4225 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6
4226 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
4227 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
4228 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4229 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64641_6
4230 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4231 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6
4232 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4233 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW6481_6
4234 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4235 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6
4236 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4237 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW6481_6
4238 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4239 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6
4240 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
4241 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4242 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4243 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4244 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4245 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6
4246 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4247 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6
4248 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4249 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6
4250 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4251 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6
4252 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4253 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6
4254 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4255 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4256 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4257 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6
4258 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4259 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6
4260 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4261 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6
4262 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4263 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6
4264 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4265 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4266 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4267 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4268 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4269 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6
4270 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4271 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW3281_6
4272 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4273 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6
4274 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4275 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW3281_6
4276 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4277 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s21_6
4278 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4279 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4280 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4281 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64161_6
4282 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4283 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64161_6
4284 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4285 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64161_6
4286 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4287 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s21_6
4288 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4289 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4290 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4291 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4292 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4293 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4294 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4295 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4296 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4297 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4298 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4299 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4300 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4301 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4302 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4303 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s11_6
4304 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_1_GT_, 7, CVT_Done },
4305 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6
4306 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
4307 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s81_6
4308 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_8_GT_, 7, CVT_Done },
4309 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
4310 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4311 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
4312 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4313 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
4314 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4315 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
4316 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4317 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
4318 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4319 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s21_6
4320 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4321 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4322 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4323 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4324 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4325 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4326 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4327 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4328 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4329 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4330 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4331 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4332 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4333 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
4334 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4335 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4336 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4337 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
4338 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4339 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6
4340 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_16_GT_, 7, CVT_Done },
4341 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
4342 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4343 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
4344 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4345 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
4346 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4347 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6
4348 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4349 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
4350 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4351 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6
4352 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4353 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6
4354 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4355 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6
4356 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4357 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6
4358 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4359 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
4360 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4361 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendLSL64321_6
4362 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4363 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64321_6
4364 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4365 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64321_6
4366 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4367 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6
4368 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4369 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6
4370 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4371 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6
4372 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4373 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6
4374 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4375 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32321_6
4376 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4377 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32321_6
4378 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4379 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6
4380 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4381 : // Convert__TypedVectorList2_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3
4382 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4383 : // Convert__TypedVectorList2_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3
4384 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4385 : // Convert__TypedVectorList2_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3
4386 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4387 : // Convert__TypedVectorList2_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3
4388 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4389 : // Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4
4390 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4391 : // Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4
4392 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4393 : // Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4
4394 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4395 : // Convert__VecListTwo1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4
4396 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4397 : // Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR
4398 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4399 : // Convert__Reg1_3__TypedVectorList2_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5
4400 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4401 : // Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR
4402 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4403 : // Convert__Reg1_3__TypedVectorList2_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5
4404 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4405 : // Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR
4406 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4407 : // Convert__Reg1_3__TypedVectorList2_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5
4408 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4409 : // Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR
4410 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4411 : // Convert__Reg1_3__TypedVectorList2_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5
4412 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4413 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR
4414 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4415 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6
4416 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4417 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR
4418 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4419 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6
4420 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4421 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR
4422 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4423 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6
4424 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4425 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR
4426 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4427 : // Convert__Reg1_4__VecListTwo1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6
4428 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4429 : // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4430 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4431 : // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4432 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4433 : // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
4434 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4435 : // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4436 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4437 : // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
4438 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4439 : // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
4440 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4441 : // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4442 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4443 : // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4444 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4445 : // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
4446 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4447 : // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4448 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4449 : // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
4450 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4451 : // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6
4452 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_2_GT_, 7, CVT_Done },
4453 : // Convert__TypedVectorList3_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3
4454 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4455 : // Convert__TypedVectorList3_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3
4456 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4457 : // Convert__TypedVectorList3_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3
4458 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4459 : // Convert__TypedVectorList3_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3
4460 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4461 : // Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4
4462 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4463 : // Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4
4464 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4465 : // Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4
4466 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4467 : // Convert__VecListThree1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4
4468 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4469 : // Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR
4470 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4471 : // Convert__Reg1_3__TypedVectorList3_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5
4472 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4473 : // Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR
4474 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4475 : // Convert__Reg1_3__TypedVectorList3_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5
4476 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4477 : // Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR
4478 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4479 : // Convert__Reg1_3__TypedVectorList3_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5
4480 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4481 : // Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR
4482 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4483 : // Convert__Reg1_3__TypedVectorList3_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5
4484 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4485 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR
4486 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4487 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6
4488 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4489 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR
4490 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4491 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6
4492 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4493 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR
4494 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4495 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6
4496 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4497 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR
4498 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4499 : // Convert__Reg1_4__VecListThree1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6
4500 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4501 : // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4502 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4503 : // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4504 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4505 : // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
4506 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
4507 : // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4508 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4509 : // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
4510 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4511 : // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
4512 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
4513 : // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4514 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4515 : // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4516 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4517 : // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
4518 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
4519 : // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4520 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4521 : // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
4522 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4523 : // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6
4524 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_3_GT_, 7, CVT_Done },
4525 : // Convert__TypedVectorList4_081_0__Tie0_1_1__IndexRange0_151_1__Reg1_3
4526 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4527 : // Convert__TypedVectorList4_0641_0__Tie0_1_1__IndexRange0_11_1__Reg1_3
4528 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4529 : // Convert__TypedVectorList4_0161_0__Tie0_1_1__IndexRange0_71_1__Reg1_3
4530 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4531 : // Convert__TypedVectorList4_0321_0__Tie0_1_1__IndexRange0_31_1__Reg1_3
4532 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
4533 : // Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_151_2__Reg1_4
4534 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4535 : // Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_11_2__Reg1_4
4536 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4537 : // Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_71_2__Reg1_4
4538 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4539 : // Convert__VecListFour1281_1__Tie0_2_2__IndexRange0_31_2__Reg1_4
4540 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
4541 : // Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__regXZR
4542 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4543 : // Convert__Reg1_3__TypedVectorList4_081_0__Tie1_1_1__IndexRange0_151_1__Tie0_4_4__Reg1_5
4544 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4545 : // Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR
4546 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4547 : // Convert__Reg1_3__TypedVectorList4_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5
4548 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4549 : // Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__regXZR
4550 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4551 : // Convert__Reg1_3__TypedVectorList4_0161_0__Tie1_1_1__IndexRange0_71_1__Tie0_4_4__Reg1_5
4552 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4553 : // Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__regXZR
4554 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4555 : // Convert__Reg1_3__TypedVectorList4_0321_0__Tie1_1_1__IndexRange0_31_1__Tie0_4_4__Reg1_5
4556 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4557 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__regXZR
4558 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4559 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_151_2__Tie0_5_5__Reg1_6
4560 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4561 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR
4562 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4563 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6
4564 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4565 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__regXZR
4566 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4567 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_71_2__Tie0_5_5__Reg1_6
4568 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4569 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__regXZR
4570 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
4571 : // Convert__Reg1_4__VecListFour1281_1__Tie1_2_2__IndexRange0_31_2__Tie0_5_5__Reg1_6
4572 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_Tied, Tie1_2_2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
4573 : // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4574 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4575 : // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6
4576 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4577 : // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
4578 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4579 : // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4580 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4581 : // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted641_6
4582 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4583 : // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
4584 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4585 : // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4586 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4587 : // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted161_6
4588 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4589 : // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
4590 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4591 : // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0
4592 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_Done },
4593 : // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6
4594 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4595 : // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6
4596 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addImmScaledOperands_LT_4_GT_, 7, CVT_Done },
4597 : // Convert__Reg1_1__Reg1_0__Reg1_3
4598 : { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_Done },
4599 : // Convert__Reg1_0__GPR64sp01_2
4600 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_Done },
4601 : // Convert__Reg1_0__Reg1_2__imm_95_0
4602 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4603 : // Convert__Reg1_0__Reg1_2__SImm91_3
4604 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4605 : // Convert__Reg1_0__Reg1_1__GPR64sp01_3
4606 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands, 4, CVT_Done },
4607 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4608 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4609 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4610 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4611 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4612 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4613 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4614 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4615 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4616 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4617 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4618 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4619 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4620 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4621 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR
4622 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_regXZR, 0, CVT_Done },
4623 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4624 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4625 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4626 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4627 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4628 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4629 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4630 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4631 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4632 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4633 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4634 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4635 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4636 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4637 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6
4638 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4639 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6
4640 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4641 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted641_6
4642 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4643 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
4644 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4645 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
4646 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4647 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
4648 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4649 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
4650 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4651 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
4652 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4653 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6
4654 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4655 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
4656 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4657 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
4658 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4659 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
4660 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4661 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6
4662 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 6, CVT_95_addRegOperands, 7, CVT_Done },
4663 : // Convert__Reg1_0__Reg1_2__SImm9s161_3
4664 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmScaledOperands_LT_16_GT_, 4, CVT_Done },
4665 : // Convert__Reg1_2__Reg1_0__Tie0_3_3
4666 : { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_Done },
4667 : // Convert__Reg1_0__Reg1_1__Reg1_3__imm_95_0
4668 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
4669 : // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__imm_95_0
4670 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
4671 : // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__imm_95_0
4672 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
4673 : // Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__imm_95_0
4674 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
4675 : // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s41_4
4676 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
4677 : // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s81_4
4678 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
4679 : // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Reg1_3__SImm7s41_4
4680 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
4681 : // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Reg1_3__SImm7s81_4
4682 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
4683 : // Convert__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Reg1_3__SImm7s161_4
4684 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_16_GT_, 5, CVT_Done },
4685 : // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_5
4686 : { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 6, CVT_Done },
4687 : // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_5
4688 : { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 6, CVT_Done },
4689 : // Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_5
4690 : { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 6, CVT_Done },
4691 : // Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_5
4692 : { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 6, CVT_Done },
4693 : // Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_5
4694 : { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_16_GT_, 6, CVT_Done },
4695 : // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s41_4
4696 : { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
4697 : // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s81_4
4698 : { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
4699 : // Convert__Reg1_3__FPRAsmOperandFPR321_0__FPRAsmOperandFPR321_1__Tie0_4_4__SImm7s41_4
4700 : { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
4701 : // Convert__Reg1_3__FPRAsmOperandFPR641_0__FPRAsmOperandFPR641_1__Tie0_4_4__SImm7s81_4
4702 : { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
4703 : // Convert__Reg1_3__FPRAsmOperandFPR1281_0__FPRAsmOperandFPR1281_1__Tie0_4_4__SImm7s161_4
4704 : { CVT_95_Reg, 4, CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_16_GT_, 5, CVT_Done },
4705 : // Convert__FPRAsmOperandFPR321_0__PCRelLabel191_1
4706 : { CVT_95_addRegOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
4707 : // Convert__FPRAsmOperandFPR641_0__PCRelLabel191_1
4708 : { CVT_95_addRegOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
4709 : // Convert__FPRAsmOperandFPR1281_0__PCRelLabel191_1
4710 : { CVT_95_addRegOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
4711 : // Convert__SVEPredicateAnyReg1_0__Reg1_2__imm_95_0
4712 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4713 : // Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0
4714 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4715 : // Convert__FPRAsmOperandFPR81_0__Reg1_2__imm_95_0
4716 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4717 : // Convert__FPRAsmOperandFPR161_0__Reg1_2__imm_95_0
4718 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4719 : // Convert__FPRAsmOperandFPR321_0__Reg1_2__imm_95_0
4720 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4721 : // Convert__FPRAsmOperandFPR641_0__Reg1_2__imm_95_0
4722 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4723 : // Convert__FPRAsmOperandFPR1281_0__Reg1_2__imm_95_0
4724 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
4725 : // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_4
4726 : { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
4727 : // Convert__Reg1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
4728 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
4729 : // Convert__Reg1_0__Reg1_2__SImm9OffsetFB321_3
4730 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4731 : // Convert__Reg1_0__Reg1_2__UImm12Offset41_3
4732 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_4_GT_, 4, CVT_Done },
4733 : // Convert__Reg1_0__Reg1_2__SImm9OffsetFB641_3
4734 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4735 : // Convert__Reg1_0__Reg1_2__UImm12Offset81_3
4736 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
4737 : // Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_4
4738 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
4739 : // Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
4740 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
4741 : // Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm9OffsetFB81_3
4742 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4743 : // Convert__FPRAsmOperandFPR81_0__Reg1_2__UImm12Offset11_3
4744 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_1_GT_, 4, CVT_Done },
4745 : // Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_4
4746 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
4747 : // Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
4748 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
4749 : // Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm9OffsetFB161_3
4750 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4751 : // Convert__FPRAsmOperandFPR161_0__Reg1_2__UImm12Offset21_3
4752 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_2_GT_, 4, CVT_Done },
4753 : // Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_4
4754 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
4755 : // Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
4756 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
4757 : // Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm9OffsetFB321_3
4758 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4759 : // Convert__FPRAsmOperandFPR321_0__Reg1_2__UImm12Offset41_3
4760 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_4_GT_, 4, CVT_Done },
4761 : // Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_4
4762 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
4763 : // Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
4764 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
4765 : // Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm9OffsetFB641_3
4766 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4767 : // Convert__FPRAsmOperandFPR641_0__Reg1_2__UImm12Offset81_3
4768 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
4769 : // Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_4
4770 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 5, CVT_Done },
4771 : // Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
4772 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
4773 : // Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm9OffsetFB1281_3
4774 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4775 : // Convert__FPRAsmOperandFPR1281_0__Reg1_2__UImm12Offset161_3
4776 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_16_GT_, 4, CVT_Done },
4777 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend322_4
4778 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4779 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend322_4
4780 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4781 : // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm91_3
4782 : { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
4783 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend642_4
4784 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4785 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend642_4
4786 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4787 : // Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemWExtend82_4
4788 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
4789 : // Convert__FPRAsmOperandFPR81_0__Reg1_2__Reg1_3__MemXExtend82_4
4790 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
4791 : // Convert__Reg1_2__FPRAsmOperandFPR81_0__Tie0_3_3__SImm91_3
4792 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
4793 : // Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemWExtend162_4
4794 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4795 : // Convert__FPRAsmOperandFPR161_0__Reg1_2__Reg1_3__MemXExtend162_4
4796 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4797 : // Convert__Reg1_2__FPRAsmOperandFPR161_0__Tie0_3_3__SImm91_3
4798 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
4799 : // Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemWExtend322_4
4800 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4801 : // Convert__FPRAsmOperandFPR321_0__Reg1_2__Reg1_3__MemXExtend322_4
4802 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4803 : // Convert__Reg1_2__FPRAsmOperandFPR321_0__Tie0_3_3__SImm91_3
4804 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
4805 : // Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemWExtend642_4
4806 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4807 : // Convert__FPRAsmOperandFPR641_0__Reg1_2__Reg1_3__MemXExtend642_4
4808 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4809 : // Convert__Reg1_2__FPRAsmOperandFPR641_0__Tie0_3_3__SImm91_3
4810 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
4811 : // Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemWExtend1282_4
4812 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4813 : // Convert__FPRAsmOperandFPR1281_0__Reg1_2__Reg1_3__MemXExtend1282_4
4814 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4815 : // Convert__Reg1_2__FPRAsmOperandFPR1281_0__Tie0_3_3__SImm91_3
4816 : { CVT_95_Reg, 3, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_Done },
4817 : // Convert__SVEPredicateAnyReg1_0__Reg1_2__SImm91_3
4818 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4819 : // Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3
4820 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4821 : // Convert__Reg1_0__Reg1_2__SImm10s81_3
4822 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmScaledOperands_LT_8_GT_, 4, CVT_Done },
4823 : // Convert__Reg1_2__Reg1_0__Tie0_3_3__SImm10s81_3
4824 : { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Tied, Tie0_3_3, CVT_95_addImmScaledOperands_LT_8_GT_, 4, CVT_Done },
4825 : // Convert__Reg1_0__Reg1_2__SImm9OffsetFB81_3
4826 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4827 : // Convert__Reg1_0__Reg1_2__UImm12Offset11_3
4828 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_1_GT_, 4, CVT_Done },
4829 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend82_4
4830 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
4831 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend82_4
4832 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtend8Operands, 5, CVT_Done },
4833 : // Convert__Reg1_0__Reg1_2__SImm9OffsetFB161_3
4834 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4835 : // Convert__Reg1_0__Reg1_2__UImm12Offset21_3
4836 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_2_GT_, 4, CVT_Done },
4837 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemWExtend162_4
4838 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4839 : // Convert__Reg1_0__Reg1_2__Reg1_3__MemXExtend162_4
4840 : { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
4841 : // Convert__FPRAsmOperandFPR81_0__Reg1_2__SImm91_3
4842 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4843 : // Convert__FPRAsmOperandFPR161_0__Reg1_2__SImm91_3
4844 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4845 : // Convert__FPRAsmOperandFPR321_0__Reg1_2__SImm91_3
4846 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4847 : // Convert__FPRAsmOperandFPR641_0__Reg1_2__SImm91_3
4848 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4849 : // Convert__FPRAsmOperandFPR1281_0__Reg1_2__SImm91_3
4850 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4851 : // Convert__SVEVectorHReg1_0__SVEVectorHReg1_1__Imm0_151_2
4852 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4853 : // Convert__SVEVectorSReg1_0__SVEVectorSReg1_1__Imm0_311_2
4854 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4855 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__Imm0_631_2
4856 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4857 : // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1__Imm0_71_2
4858 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4859 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_151_5
4860 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
4861 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_311_5
4862 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
4863 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_631_5
4864 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
4865 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__Imm0_71_5
4866 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_5, CVT_95_addImmOperands, 6, CVT_Done },
4867 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_1__SVEVectorBReg1_4__SVEVectorBReg1_5
4868 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 6, CVT_Done },
4869 : // Convert__Reg1_0__Reg1_1__Reg1_2__regWZR
4870 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_regWZR, 0, CVT_Done },
4871 : // Convert__Reg1_0__Reg1_1__Reg1_2__regXZR
4872 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_regXZR, 0, CVT_Done },
4873 : // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0
4874 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
4875 : // Convert__Reg1_0__regWZR__Reg1_1__imm_95_0
4876 : { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
4877 : // Convert__Reg1_0__MOVZ32_lsl0MovAlias1_1__imm_95_0
4878 : { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4879 : // Convert__Reg1_0__MOVZ32_lsl16MovAlias1_1__imm_95_16
4880 : { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
4881 : // Convert__Reg1_0__MOVN32_lsl0MovAlias1_1__imm_95_0
4882 : { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4883 : // Convert__Reg1_0__MOVN32_lsl16MovAlias1_1__imm_95_16
4884 : { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
4885 : // Convert__Reg1_0__regWZR__LogicalImm321_1
4886 : { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
4887 : // Convert__Reg1_0__regXZR__Reg1_1__imm_95_0
4888 : { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
4889 : // Convert__Reg1_0__MOVZ64_lsl0MovAlias1_1__imm_95_0
4890 : { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4891 : // Convert__Reg1_0__MOVZ64_lsl16MovAlias1_1__imm_95_16
4892 : { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
4893 : // Convert__Reg1_0__MOVZ64_lsl32MovAlias1_1__imm_95_32
4894 : { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_32_GT_, 2, CVT_imm_95_32, 0, CVT_Done },
4895 : // Convert__Reg1_0__MOVZ64_lsl48MovAlias1_1__imm_95_48
4896 : { CVT_95_Reg, 1, CVT_95_addMOVZMovAliasOperands_LT_48_GT_, 2, CVT_imm_95_48, 0, CVT_Done },
4897 : // Convert__Reg1_0__MOVN64_lsl0MovAlias1_1__imm_95_0
4898 : { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_0_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4899 : // Convert__Reg1_0__MOVN64_lsl16MovAlias1_1__imm_95_16
4900 : { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_16_GT_, 2, CVT_imm_95_16, 0, CVT_Done },
4901 : // Convert__Reg1_0__MOVN64_lsl32MovAlias1_1__imm_95_32
4902 : { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_32_GT_, 2, CVT_imm_95_32, 0, CVT_Done },
4903 : // Convert__Reg1_0__MOVN64_lsl48MovAlias1_1__imm_95_48
4904 : { CVT_95_Reg, 1, CVT_95_addMOVNMovAliasOperands_LT_48_GT_, 2, CVT_imm_95_48, 0, CVT_Done },
4905 : // Convert__Reg1_0__regXZR__LogicalImm641_1
4906 : { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
4907 : // Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_1__SVEPredicateBReg1_1
4908 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
4909 : // Convert__SVEVectorQReg1_0__FPR128asZPR1_1__imm_95_0
4910 : { CVT_95_addRegOperands, 1, CVT_95_addFPRasZPRRegOperands_LT_128_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4911 : // Convert__SVEVectorHReg1_0__SVEPreferredLogicalImm161_1
4912 : { CVT_95_addRegOperands, 1, CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_, 2, CVT_Done },
4913 : // Convert__SVEVectorHReg1_0__FPR16asZPR1_1__imm_95_0
4914 : { CVT_95_addRegOperands, 1, CVT_95_addFPRasZPRRegOperands_LT_16_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4915 : // Convert__SVEVectorSReg1_0__SVEPreferredLogicalImm321_1
4916 : { CVT_95_addRegOperands, 1, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
4917 : // Convert__SVEVectorSReg1_0__FPR32asZPR1_1__imm_95_0
4918 : { CVT_95_addRegOperands, 1, CVT_95_addFPRasZPRRegOperands_LT_32_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4919 : // Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_1
4920 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
4921 : // Convert__SVEVectorDReg1_0__SVEPreferredLogicalImm641_1
4922 : { CVT_95_addRegOperands, 1, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
4923 : // Convert__SVEVectorDReg1_0__FPR64asZPR1_1__imm_95_0
4924 : { CVT_95_addRegOperands, 1, CVT_95_addFPRasZPRRegOperands_LT_64_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4925 : // Convert__SVEVectorBReg1_0__FPR8asZPR1_1__imm_95_0
4926 : { CVT_95_addRegOperands, 1, CVT_95_addFPRasZPRRegOperands_LT_8_GT_, 2, CVT_imm_95_0, 0, CVT_Done },
4927 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_2
4928 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 3, CVT_Done },
4929 : // Convert__VectorReg641_1__VectorReg641_2__VectorReg641_2
4930 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 3, CVT_Done },
4931 : // Convert__Reg1_1__VectorReg1281_2__IndexRange0_11_3
4932 : { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
4933 : // Convert__Reg1_1__VectorReg1281_2__IndexRange0_31_3
4934 : { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
4935 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_2
4936 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 3, CVT_Done },
4937 : // Convert__VectorReg641_0__VectorReg641_2__VectorReg641_2
4938 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 3, CVT_Done },
4939 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateBReg1_0
4940 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 1, CVT_Done },
4941 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateBReg1_4
4942 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 5, CVT_Done },
4943 : // Convert__SVEVectorHReg1_0__SVEPredicateAnyReg1_1__SVEVectorHReg1_4__SVEVectorHReg1_0
4944 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 1, CVT_Done },
4945 : // Convert__SVEVectorSReg1_0__SVEPredicateAnyReg1_1__SVEVectorSReg1_4__SVEVectorSReg1_0
4946 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 1, CVT_Done },
4947 : // Convert__SVEVectorDReg1_0__SVEPredicateAnyReg1_1__SVEVectorDReg1_4__SVEVectorDReg1_0
4948 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 1, CVT_Done },
4949 : // Convert__SVEVectorBReg1_0__SVEPredicateAnyReg1_1__SVEVectorBReg1_4__SVEVectorBReg1_0
4950 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 1, CVT_Done },
4951 : // Convert__Reg1_0__SIMDImmType101_1
4952 : { CVT_95_Reg, 1, CVT_95_addSIMDImmType10Operands, 2, CVT_Done },
4953 : // Convert__VectorReg1281_1__Imm0_2551_2
4954 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4955 : // Convert__VectorReg1281_1__SIMDImmType101_2
4956 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addSIMDImmType10Operands, 3, CVT_Done },
4957 : // Convert__VectorReg641_1__Imm0_2551_2__imm_95_0
4958 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4959 : // Convert__VectorReg1281_1__Imm0_2551_2__imm_95_0
4960 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4961 : // Convert__VectorReg641_1__Imm0_2551_2
4962 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
4963 : // Convert__VectorReg1281_0__Imm0_2551_2
4964 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_Done },
4965 : // Convert__VectorReg1281_0__SIMDImmType101_2
4966 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addSIMDImmType10Operands, 3, CVT_Done },
4967 : // Convert__VectorReg1281_0__Imm0_2551_2__imm_95_0
4968 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4969 : // Convert__VectorReg641_0__Imm0_2551_2__imm_95_0
4970 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
4971 : // Convert__VectorReg641_0__Imm0_2551_2
4972 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_Done },
4973 : // Convert__VectorReg641_1__Imm0_2551_2__LogicalVecShifter1_3
4974 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4975 : // Convert__VectorReg641_1__Imm0_2551_2__MoveVecShifter1_3
4976 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4977 : // Convert__VectorReg641_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
4978 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4979 : // Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecShifter1_3
4980 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4981 : // Convert__VectorReg1281_1__Imm0_2551_2__MoveVecShifter1_3
4982 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4983 : // Convert__VectorReg1281_1__Imm0_2551_2__LogicalVecHalfWordShifter1_3
4984 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4985 : // Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecShifter1_3
4986 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4987 : // Convert__VectorReg1281_0__Imm0_2551_2__MoveVecShifter1_3
4988 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4989 : // Convert__VectorReg1281_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3
4990 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4991 : // Convert__VectorReg641_0__Imm0_2551_2__LogicalVecShifter1_3
4992 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4993 : // Convert__VectorReg641_0__Imm0_2551_2__MoveVecShifter1_3
4994 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4995 : // Convert__VectorReg641_0__Imm0_2551_2__LogicalVecHalfWordShifter1_3
4996 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addImmOperands, 3, CVT_95_addShifterOperands, 4, CVT_Done },
4997 : // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0
4998 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
4999 : // Convert__Reg1_0__Tie0_1_1__MovKSymbolG01_1__imm_95_0
5000 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
5001 : // Convert__Reg1_0__Tie0_1_1__MovKSymbolG11_1__imm_95_16
5002 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_16, 0, CVT_Done },
5003 : // Convert__Reg1_0__Tie0_1_1__MovKSymbolG21_1__imm_95_32
5004 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_32, 0, CVT_Done },
5005 : // Convert__Reg1_0__Tie0_1_1__MovKSymbolG31_1__imm_95_48
5006 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_imm_95_48, 0, CVT_Done },
5007 : // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2
5008 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5009 : // Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2
5010 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5011 : // Convert__Reg1_0__Imm0_655351_1__imm_95_0
5012 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
5013 : // Convert__Reg1_0__MovZSymbolG01_1__imm_95_0
5014 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
5015 : // Convert__Reg1_0__MovZSymbolG11_1__imm_95_16
5016 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_16, 0, CVT_Done },
5017 : // Convert__Reg1_0__MovZSymbolG21_1__imm_95_32
5018 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_32, 0, CVT_Done },
5019 : // Convert__Reg1_0__MovZSymbolG31_1__imm_95_48
5020 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_48, 0, CVT_Done },
5021 : // Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2
5022 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5023 : // Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2
5024 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5025 : // Convert__SVEVectorAnyReg1_0__SVEVectorAnyReg1_1
5026 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5027 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1_4
5028 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
5029 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_4
5030 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
5031 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_4
5032 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
5033 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorBReg1_4
5034 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_Done },
5035 : // Convert__Reg1_0__MRSSystemRegister1_1
5036 : { CVT_95_Reg, 1, CVT_95_addMRSSystemRegisterOperands, 2, CVT_Done },
5037 : // Convert__MSRSystemRegister1_0__Reg1_1
5038 : { CVT_95_addMSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
5039 : // Convert__SystemPStateFieldWithImm0_151_0__Imm0_151_1
5040 : { CVT_95_addSystemPStateFieldWithImm0_95_15Operands, 1, CVT_95_addImmOperands, 2, CVT_Done },
5041 : // Convert__SystemPStateFieldWithImm0_11_0__Imm0_11_1
5042 : { CVT_95_addSystemPStateFieldWithImm0_95_1Operands, 1, CVT_95_addImmOperands, 2, CVT_Done },
5043 : // Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2
5044 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
5045 : // Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2
5046 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
5047 : // Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2
5048 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
5049 : // Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2
5050 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
5051 : // Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2
5052 : { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5053 : // Convert__Reg1_0__regXZR__Reg1_1__LogicalShifter641_2
5054 : { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5055 : // Convert__Reg1_0__regWZR__Reg1_1__ArithmeticShifter321_2
5056 : { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5057 : // Convert__Reg1_0__regXZR__Reg1_1__ArithmeticShifter641_2
5058 : { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
5059 : // Convert__Reg1_0__regWZR__Reg1_1
5060 : { CVT_95_Reg, 1, CVT_regWZR, 0, CVT_95_Reg, 2, CVT_Done },
5061 : // Convert__Reg1_0__regXZR__Reg1_1
5062 : { CVT_95_Reg, 1, CVT_regXZR, 0, CVT_95_Reg, 2, CVT_Done },
5063 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_4__SVEPredicateAnyReg1_1
5064 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 5, CVT_95_addRegOperands, 2, CVT_Done },
5065 : // Convert__SVEPredicateBReg1_0
5066 : { CVT_95_addRegOperands, 1, CVT_Done },
5067 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3
5068 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5069 : // Convert__VectorReg1281_1__VectorReg641_2__VectorReg641_3
5070 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5071 : // Convert__VectorReg1281_0__VectorReg641_2__VectorReg641_4
5072 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
5073 : // Convert__SVEPredicateHReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3
5074 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5075 : // Convert__SVEPredicateSReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3
5076 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5077 : // Convert__SVEPredicateDReg1_0__SVEPredicateAnyReg1_1__Tie0_1_3
5078 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5079 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5080 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5081 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0
5082 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
5083 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0
5084 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
5085 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5086 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5087 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4
5088 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5089 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4
5090 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5091 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4
5092 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5093 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4
5094 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5095 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4
5096 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5097 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4
5098 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
5099 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4
5100 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
5101 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm6s11_4
5102 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5103 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
5104 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5105 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32641_4
5106 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5107 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32641_4
5108 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5109 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4
5110 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5111 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4
5112 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5113 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4
5114 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5115 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s81_4
5116 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
5117 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4
5118 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
5119 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5120 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5121 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4
5122 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5123 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4
5124 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5125 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4
5126 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5127 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4
5128 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5129 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4
5130 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5131 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4
5132 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5133 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4
5134 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5135 : // Convert__Prefetch1_0__PCRelLabel191_1
5136 : { CVT_95_addPrefetchOperands, 1, CVT_95_addPCRelLabel19Operands, 2, CVT_Done },
5137 : // Convert__Prefetch1_0__Reg1_2__imm_95_0
5138 : { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
5139 : // Convert__Prefetch1_0__Reg1_2__Reg1_3__imm_95_0__imm_95_0
5140 : { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
5141 : // Convert__Prefetch1_0__Reg1_2__UImm12Offset81_3
5142 : { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_addUImm12OffsetOperands_LT_8_GT_, 4, CVT_Done },
5143 : // Convert__Prefetch1_0__Reg1_2__Reg1_3__MemWExtend642_4
5144 : { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
5145 : // Convert__Prefetch1_0__Reg1_2__Reg1_3__MemXExtend642_4
5146 : { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemExtendOperands, 5, CVT_Done },
5147 : // Convert__Prefetch1_0__Reg1_2__SImm91_3
5148 : { CVT_95_addPrefetchOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
5149 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5150 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5151 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4
5152 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5153 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4
5154 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5155 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4
5156 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5157 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4
5158 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5159 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4
5160 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5161 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4
5162 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5163 : // Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4
5164 : { CVT_95_addPrefetchOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5165 : // Convert__PSBHint1_0
5166 : { CVT_95_addPSBHintOperands, 1, CVT_Done },
5167 : // Convert__imm_95_4
5168 : { CVT_imm_95_4, 0, CVT_Done },
5169 : // Convert__SVEPredicateAnyReg1_0__SVEPredicateBReg1_1
5170 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5171 : // Convert__SVEPredicateHReg1_0__imm_95_31
5172 : { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
5173 : // Convert__SVEPredicateSReg1_0__imm_95_31
5174 : { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
5175 : // Convert__SVEPredicateDReg1_0__imm_95_31
5176 : { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
5177 : // Convert__SVEPredicateBReg1_0__imm_95_31
5178 : { CVT_95_addRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
5179 : // Convert__SVEPredicateHReg1_0__SVEPattern1_1
5180 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
5181 : // Convert__SVEPredicateSReg1_0__SVEPattern1_1
5182 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
5183 : // Convert__SVEPredicateDReg1_0__SVEPattern1_1
5184 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
5185 : // Convert__SVEPredicateBReg1_0__SVEPattern1_1
5186 : { CVT_95_addRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
5187 : // Convert__SVEPredicateHReg1_0__SVEPredicateBReg1_1
5188 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5189 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1
5190 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5191 : // Convert__Reg1_0__SImm61_1
5192 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
5193 : // Convert__regLR
5194 : { CVT_regLR, 0, CVT_Done },
5195 : // Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1
5196 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5197 : // Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1
5198 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5199 : // Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1
5200 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5201 : // Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1
5202 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5203 : // Convert__SVEVectorBReg1_0__SVEVectorBReg1_1
5204 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5205 : // Convert__Reg1_0__UImm61_1__Imm0_151_2
5206 : { CVT_95_Reg, 1, CVT_95_addUImm6Operands, 2, CVT_95_addImmOperands, 3, CVT_Done },
5207 : // Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_311_2
5208 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5209 : // Convert__Reg1_0__Reg1_1__Reg1_1__Imm0_631_2
5210 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5211 : // Convert__VectorReg641_1__VectorReg1281_2__Imm1_321_3
5212 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5213 : // Convert__VectorReg641_1__VectorReg1281_2__Imm1_161_3
5214 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5215 : // Convert__VectorReg641_1__VectorReg1281_2__Imm1_81_3
5216 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5217 : // Convert__VectorReg641_0__VectorReg1281_2__Imm1_321_4
5218 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5219 : // Convert__VectorReg641_0__VectorReg1281_2__Imm1_161_4
5220 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5221 : // Convert__VectorReg641_0__VectorReg1281_2__Imm1_81_4
5222 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5223 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_81_3
5224 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5225 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3
5226 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5227 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_161_3
5228 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5229 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4
5230 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5231 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4
5232 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5233 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4
5234 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5235 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg641_3
5236 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5237 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg641_4
5238 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
5239 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2
5240 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
5241 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2
5242 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_Done },
5243 : // Convert__VectorReg1281_1__VectorReg1281_2__VectorReg641_3
5244 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5245 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg641_4
5246 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg64Operands, 5, CVT_Done },
5247 : // Convert__Reg1_0__Reg1_1__Imm0_311_2__Imm0_311_3
5248 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5249 : // Convert__Reg1_0__Reg1_1__Imm0_631_2__Imm0_631_3
5250 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5251 : // Convert__imm_95_0__Tie0_1_1__imm_95_0__imm_95_0
5252 : { CVT_imm_95_0, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
5253 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorBReg1_1__SVEVectorBReg1_2
5254 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
5255 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVectorHReg1_2
5256 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
5257 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_1__VectorReg1281_2__IndexRange0_31_3
5258 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
5259 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_1__VectorReg1281_2__IndexRange0_31_3
5260 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
5261 : // Convert__SVEVectorSReg1_0__Tie0_1_1__SVEVectorBReg1_1__SVEVector3bBReg1_2__IndexRange0_31_3
5262 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
5263 : // Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorHReg1_1__SVEVector4bHReg1_2__IndexRange0_11_3
5264 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
5265 : // Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPredicateBReg1_2__SVEPredicateBReg1_3
5266 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
5267 : // Convert__SVEVectorHReg1_0__SVEPredicateAnyReg1_1__SVEVectorHReg1_2__SVEVectorHReg1_3
5268 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
5269 : // Convert__SVEVectorSReg1_0__SVEPredicateAnyReg1_1__SVEVectorSReg1_2__SVEVectorSReg1_3
5270 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
5271 : // Convert__SVEVectorDReg1_0__SVEPredicateAnyReg1_1__SVEVectorDReg1_2__SVEVectorDReg1_3
5272 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
5273 : // Convert__SVEVectorBReg1_0__SVEPredicateAnyReg1_1__SVEVectorBReg1_2__SVEVectorBReg1_3
5274 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_Done },
5275 : // Convert__imm_95_5
5276 : { CVT_imm_95_5, 0, CVT_Done },
5277 : // Convert__Reg1_1__Tie0_2_2__Reg1_2__VectorReg1281_3
5278 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5279 : // Convert__Reg1_0__Tie0_1_1__Reg1_1__VectorReg1281_2
5280 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
5281 : // Convert__imm_95_0__imm_95_0__Tie0_1_1
5282 : { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Tied, Tie0_1_1, CVT_Done },
5283 : // Convert__VectorReg1281_0__VectorReg1281_2__Tie0_1_1
5284 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
5285 : // Convert__Reg1_0__Reg1_1__Imm0_631_2
5286 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5287 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_71_3
5288 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5289 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_631_3
5290 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5291 : // Convert__VectorReg641_1__VectorReg641_2__Imm0_311_3
5292 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5293 : // Convert__VectorReg641_1__VectorReg641_2__Imm0_151_3
5294 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5295 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_311_3
5296 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5297 : // Convert__VectorReg641_1__VectorReg641_2__Imm0_71_3
5298 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5299 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm0_151_3
5300 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5301 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_71_4
5302 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5303 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_631_4
5304 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5305 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_311_4
5306 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5307 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm0_151_4
5308 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5309 : // Convert__VectorReg641_0__VectorReg641_2__Imm0_311_4
5310 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5311 : // Convert__VectorReg641_0__VectorReg641_2__Imm0_151_4
5312 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5313 : // Convert__VectorReg641_0__VectorReg641_2__Imm0_71_4
5314 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5315 : // Convert__VectorReg1281_1__VectorReg641_2
5316 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_Done },
5317 : // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm0_631_2
5318 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5319 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_71_3
5320 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5321 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_631_3
5322 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5323 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_311_3
5324 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5325 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_151_3
5326 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5327 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_311_3
5328 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5329 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm0_71_3
5330 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5331 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm0_151_3
5332 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5333 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_71_4
5334 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5335 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_631_4
5336 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5337 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_311_4
5338 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5339 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm0_151_4
5340 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5341 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_311_4
5342 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5343 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_151_4
5344 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5345 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm0_71_4
5346 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5347 : // Convert__imm_95_0__Tie0_1_1__imm_95_0__imm_95_0__imm_95_0
5348 : { CVT_imm_95_0, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
5349 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4
5350 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5351 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4
5352 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5353 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6
5354 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
5355 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6
5356 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
5357 : // Convert__Reg1_1__VectorReg1281_2__IndexRange0_151_3
5358 : { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
5359 : // Convert__Reg1_1__VectorReg1281_2__IndexRange0_71_3
5360 : { CVT_95_Reg, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 4, CVT_Done },
5361 : // Convert__VectorReg1281_1__VectorReg641_2__VectorReg1281_3__IndexRange0_31_4
5362 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5363 : // Convert__VectorReg1281_1__VectorReg641_2__VectorRegLo1_3__IndexRange0_71_4
5364 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5365 : // Convert__VectorReg1281_0__VectorReg641_2__VectorReg1281_4__IndexRange0_31_6
5366 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
5367 : // Convert__VectorReg1281_0__VectorReg641_2__VectorRegLo1_4__IndexRange0_71_6
5368 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addVectorRegLoOperands, 5, CVT_95_addVectorIndexOperands, 7, CVT_Done },
5369 : // Convert__Reg1_0__Tie255_1_2__GPR64as321_1__imm_95_31__imm_95_1
5370 : { CVT_95_Reg, 1, CVT_Tied, Tie255_1_2, CVT_95_addGPR64as32Operands, 2, CVT_imm_95_31, 0, CVT_imm_95_1, 0, CVT_Done },
5371 : // Convert__Reg1_0__Tie255_1_2__GPR64as321_1__SVEPattern1_2__imm_95_1
5372 : { CVT_95_Reg, 1, CVT_Tied, Tie255_1_2, CVT_95_addGPR64as32Operands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_Done },
5373 : // Convert__Reg1_0__Tie0_1_2__SVEPattern1_2__Imm1_161_4
5374 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5375 : // Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_3
5376 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5377 : // Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_3
5378 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5379 : // Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_3
5380 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5381 : // Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_3
5382 : { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Tied, Tie0_1_3, CVT_Done },
5383 : // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
5384 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
5385 : // Convert__FPRAsmOperandFPR321_1__Tie0_2_2__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4
5386 : { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5387 : // Convert__FPRAsmOperandFPR641_1__Tie0_2_2__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4
5388 : { CVT_95_addRegOperands, 2, CVT_Tied, Tie0_2_2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5389 : // Convert__FPRAsmOperandFPR321_0__Tie0_1_1__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4
5390 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5391 : // Convert__FPRAsmOperandFPR641_0__Tie0_1_1__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4
5392 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5393 : // Convert__FPRAsmOperandFPR321_1__FPRAsmOperandFPR161_2__VectorRegLo1_3__IndexRange0_71_4
5394 : { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorRegLoOperands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5395 : // Convert__FPRAsmOperandFPR641_1__FPRAsmOperandFPR321_2__VectorReg1281_3__IndexRange0_31_4
5396 : { CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addVectorReg128Operands, 4, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5397 : // Convert__FPRAsmOperandFPR321_0__FPRAsmOperandFPR161_1__VectorRegLo1_2__IndexRange0_71_4
5398 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorRegLoOperands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5399 : // Convert__FPRAsmOperandFPR641_0__FPRAsmOperandFPR321_1__VectorReg1281_2__IndexRange0_31_4
5400 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorIndexOperands, 5, CVT_Done },
5401 : // Convert__Reg1_0__Reg1_1__Imm1_81_2
5402 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5403 : // Convert__Reg1_0__Reg1_1__Imm0_151_2
5404 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5405 : // Convert__Reg1_0__Reg1_1__Imm0_311_2
5406 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5407 : // Convert__Reg1_0__Reg1_1__Imm0_71_2
5408 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5409 : // Convert__VectorReg641_1__VectorReg1281_2
5410 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_Done },
5411 : // Convert__Reg1_0__Tie0_1_1__Reg1_1__Imm1_641_2
5412 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
5413 : // Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_641_3
5414 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5415 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_321_3
5416 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5417 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_161_3
5418 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5419 : // Convert__VectorReg641_1__Tie0_2_2__VectorReg641_2__Imm1_81_3
5420 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5421 : // Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_641_4
5422 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5423 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_321_4
5424 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5425 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_161_4
5426 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5427 : // Convert__VectorReg641_0__Tie0_1_1__VectorReg641_2__Imm1_81_4
5428 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5429 : // Convert__VectorReg1281_1__VectorReg1281_2__Imm1_81_3
5430 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5431 : // Convert__VectorReg641_1__VectorReg641_2__Imm1_81_3
5432 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5433 : // Convert__VectorReg1281_0__VectorReg1281_2__Imm1_81_4
5434 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5435 : // Convert__VectorReg641_0__VectorReg641_2__Imm1_81_4
5436 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5437 : // Convert__VectorReg1281_1__VectorReg641_2__Imm0_311_3
5438 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5439 : // Convert__VectorReg1281_1__VectorReg641_2__Imm0_151_3
5440 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5441 : // Convert__VectorReg1281_1__VectorReg641_2__Imm0_71_3
5442 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 4, CVT_Done },
5443 : // Convert__VectorReg1281_0__VectorReg641_2__Imm0_311_4
5444 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5445 : // Convert__VectorReg1281_0__VectorReg641_2__Imm0_151_4
5446 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5447 : // Convert__VectorReg1281_0__VectorReg641_2__Imm0_71_4
5448 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_95_addImmOperands, 5, CVT_Done },
5449 : // Convert__TypedVectorList1_081_0__IndexRange0_151_1__Reg1_3
5450 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5451 : // Convert__TypedVectorList1_0641_0__IndexRange0_11_1__Reg1_3
5452 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5453 : // Convert__TypedVectorList1_0161_0__IndexRange0_71_1__Reg1_3
5454 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5455 : // Convert__TypedVectorList1_0321_0__IndexRange0_31_1__Reg1_3
5456 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5457 : // Convert__VecListOne1281_1__IndexRange0_151_2__Reg1_4
5458 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5459 : // Convert__VecListOne1281_1__IndexRange0_11_2__Reg1_4
5460 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5461 : // Convert__VecListOne1281_1__IndexRange0_71_2__Reg1_4
5462 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5463 : // Convert__VecListOne1281_1__IndexRange0_31_2__Reg1_4
5464 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5465 : // Convert__Reg1_3__TypedVectorList1_081_0__IndexRange0_151_1__Tie0_4_4__regXZR
5466 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5467 : // Convert__Reg1_3__TypedVectorList1_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5
5468 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5469 : // Convert__Reg1_3__TypedVectorList1_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR
5470 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5471 : // Convert__Reg1_3__TypedVectorList1_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5
5472 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5473 : // Convert__Reg1_3__TypedVectorList1_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR
5474 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5475 : // Convert__Reg1_3__TypedVectorList1_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5
5476 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5477 : // Convert__Reg1_3__TypedVectorList1_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR
5478 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5479 : // Convert__Reg1_3__TypedVectorList1_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5
5480 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5481 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_151_2__Tie0_5_5__regXZR
5482 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5483 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6
5484 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5485 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_11_2__Tie0_5_5__regXZR
5486 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5487 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6
5488 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5489 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_71_2__Tie0_5_5__regXZR
5490 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5491 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6
5492 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5493 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_31_2__Tie0_5_5__regXZR
5494 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5495 : // Convert__Reg1_4__VecListOne1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6
5496 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5497 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5498 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5499 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5500 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5501 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0
5502 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
5503 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5504 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5505 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0
5506 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
5507 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5508 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5509 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5510 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5511 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5512 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5513 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5514 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5515 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__imm_95_0
5516 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
5517 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5518 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5519 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__imm_95_0
5520 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_imm_95_0, 0, CVT_Done },
5521 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5522 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5523 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5524 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5525 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4
5526 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5527 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4
5528 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5529 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4
5530 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
5531 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5532 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5533 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4
5534 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5535 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4
5536 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5537 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4
5538 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5539 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4
5540 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
5541 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5542 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5543 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5544 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5545 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5546 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5547 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5548 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5549 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW328Only1_4
5550 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5551 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW328Only1_4
5552 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5553 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Imm0_311_4
5554 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
5555 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5556 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5557 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL6481_4
5558 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5559 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW648Only1_4
5560 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5561 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW648Only1_4
5562 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5563 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Imm0_311_4
5564 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
5565 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5566 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5567 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5568 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5569 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5570 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5571 : // Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5572 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5573 : // Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5574 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5575 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5576 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5577 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5578 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5579 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s11_4
5580 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_1_GT_, 5, CVT_Done },
5581 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
5582 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5583 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4
5584 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5585 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4
5586 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5587 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4
5588 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5589 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4
5590 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5591 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4
5592 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5593 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4
5594 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
5595 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
5596 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5597 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64641_4
5598 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5599 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4
5600 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5601 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW6481_4
5602 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5603 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4
5604 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5605 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW6481_4
5606 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5607 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4
5608 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_8_GT_, 5, CVT_Done },
5609 : // Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5610 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5611 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5612 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5613 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4
5614 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5615 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4
5616 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5617 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4
5618 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5619 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4
5620 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5621 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4
5622 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5623 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5624 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5625 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4
5626 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5627 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4
5628 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5629 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4
5630 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5631 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4
5632 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5633 : // Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5634 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5635 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5636 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5637 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4
5638 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5639 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW3281_4
5640 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5641 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4
5642 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5643 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW3281_4
5644 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5645 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s21_4
5646 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5647 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5648 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5649 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64161_4
5650 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5651 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64161_4
5652 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5653 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64161_4
5654 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5655 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s21_4
5656 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5657 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5658 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5659 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4
5660 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5661 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4
5662 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5663 : // Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4
5664 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5665 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5666 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5667 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4
5668 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5669 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4
5670 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5671 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4
5672 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5673 : // Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4
5674 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5675 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5676 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5677 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32321_4
5678 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5679 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32321_4
5680 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5681 : // Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4
5682 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5683 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5684 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5685 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendLSL64321_4
5686 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5687 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64321_4
5688 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5689 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64321_4
5690 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5691 : // Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4
5692 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5693 : // Convert__TypedVectorList2_081_0__IndexRange0_151_1__Reg1_3
5694 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5695 : // Convert__TypedVectorList2_0641_0__IndexRange0_11_1__Reg1_3
5696 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5697 : // Convert__TypedVectorList2_0161_0__IndexRange0_71_1__Reg1_3
5698 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5699 : // Convert__TypedVectorList2_0321_0__IndexRange0_31_1__Reg1_3
5700 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5701 : // Convert__VecListTwo1281_1__IndexRange0_151_2__Reg1_4
5702 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5703 : // Convert__VecListTwo1281_1__IndexRange0_11_2__Reg1_4
5704 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5705 : // Convert__VecListTwo1281_1__IndexRange0_71_2__Reg1_4
5706 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5707 : // Convert__VecListTwo1281_1__IndexRange0_31_2__Reg1_4
5708 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5709 : // Convert__Reg1_3__TypedVectorList2_081_0__IndexRange0_151_1__Tie0_4_4__regXZR
5710 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5711 : // Convert__Reg1_3__TypedVectorList2_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5
5712 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5713 : // Convert__Reg1_3__TypedVectorList2_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR
5714 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5715 : // Convert__Reg1_3__TypedVectorList2_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5
5716 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5717 : // Convert__Reg1_3__TypedVectorList2_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR
5718 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5719 : // Convert__Reg1_3__TypedVectorList2_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5
5720 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5721 : // Convert__Reg1_3__TypedVectorList2_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR
5722 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5723 : // Convert__Reg1_3__TypedVectorList2_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5
5724 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5725 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_151_2__Tie0_5_5__regXZR
5726 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5727 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6
5728 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5729 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_11_2__Tie0_5_5__regXZR
5730 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5731 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6
5732 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5733 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_71_2__Tie0_5_5__regXZR
5734 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5735 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6
5736 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5737 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_31_2__Tie0_5_5__regXZR
5738 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5739 : // Convert__Reg1_4__VecListTwo1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6
5740 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5741 : // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5742 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5743 : // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5744 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5745 : // Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
5746 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5747 : // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5748 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5749 : // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
5750 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5751 : // Convert__SVEVectorList2641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
5752 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5753 : // Convert__Reg1_1__imm_95_0
5754 : { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
5755 : // Convert__Reg1_1__Tie0_2_2__SImm9s161_3
5756 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmScaledOperands_LT_16_GT_, 4, CVT_Done },
5757 : // Convert__Reg1_1__SImm9s161_2
5758 : { CVT_95_Reg, 2, CVT_95_addImmScaledOperands_LT_16_GT_, 3, CVT_Done },
5759 : // Convert__Reg1_1__Tie0_2_2__SImm9s161_2
5760 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmScaledOperands_LT_16_GT_, 3, CVT_Done },
5761 : // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5762 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5763 : // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5764 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5765 : // Convert__SVEVectorList2161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
5766 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5767 : // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5768 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5769 : // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5770 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5771 : // Convert__SVEVectorList2321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4
5772 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_2_GT_, 5, CVT_Done },
5773 : // Convert__TypedVectorList3_081_0__IndexRange0_151_1__Reg1_3
5774 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5775 : // Convert__TypedVectorList3_0641_0__IndexRange0_11_1__Reg1_3
5776 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5777 : // Convert__TypedVectorList3_0161_0__IndexRange0_71_1__Reg1_3
5778 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5779 : // Convert__TypedVectorList3_0321_0__IndexRange0_31_1__Reg1_3
5780 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5781 : // Convert__VecListThree1281_1__IndexRange0_151_2__Reg1_4
5782 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5783 : // Convert__VecListThree1281_1__IndexRange0_11_2__Reg1_4
5784 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5785 : // Convert__VecListThree1281_1__IndexRange0_71_2__Reg1_4
5786 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5787 : // Convert__VecListThree1281_1__IndexRange0_31_2__Reg1_4
5788 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5789 : // Convert__Reg1_3__TypedVectorList3_081_0__IndexRange0_151_1__Tie0_4_4__regXZR
5790 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5791 : // Convert__Reg1_3__TypedVectorList3_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5
5792 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5793 : // Convert__Reg1_3__TypedVectorList3_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR
5794 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5795 : // Convert__Reg1_3__TypedVectorList3_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5
5796 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5797 : // Convert__Reg1_3__TypedVectorList3_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR
5798 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5799 : // Convert__Reg1_3__TypedVectorList3_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5
5800 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5801 : // Convert__Reg1_3__TypedVectorList3_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR
5802 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5803 : // Convert__Reg1_3__TypedVectorList3_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5
5804 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5805 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_151_2__Tie0_5_5__regXZR
5806 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5807 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6
5808 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5809 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_11_2__Tie0_5_5__regXZR
5810 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5811 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6
5812 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5813 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_71_2__Tie0_5_5__regXZR
5814 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5815 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6
5816 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5817 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_31_2__Tie0_5_5__regXZR
5818 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5819 : // Convert__Reg1_4__VecListThree1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6
5820 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5821 : // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5822 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5823 : // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5824 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5825 : // Convert__SVEVectorList381_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
5826 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
5827 : // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5828 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5829 : // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
5830 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5831 : // Convert__SVEVectorList3641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
5832 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
5833 : // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5834 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5835 : // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5836 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5837 : // Convert__SVEVectorList3161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
5838 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
5839 : // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5840 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5841 : // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5842 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5843 : // Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4
5844 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_3_GT_, 5, CVT_Done },
5845 : // Convert__TypedVectorList4_081_0__IndexRange0_151_1__Reg1_3
5846 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5847 : // Convert__TypedVectorList4_0641_0__IndexRange0_11_1__Reg1_3
5848 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5849 : // Convert__TypedVectorList4_0161_0__IndexRange0_71_1__Reg1_3
5850 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5851 : // Convert__TypedVectorList4_0321_0__IndexRange0_31_1__Reg1_3
5852 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_95_Reg, 4, CVT_Done },
5853 : // Convert__VecListFour1281_1__IndexRange0_151_2__Reg1_4
5854 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5855 : // Convert__VecListFour1281_1__IndexRange0_11_2__Reg1_4
5856 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5857 : // Convert__VecListFour1281_1__IndexRange0_71_2__Reg1_4
5858 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5859 : // Convert__VecListFour1281_1__IndexRange0_31_2__Reg1_4
5860 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_95_Reg, 5, CVT_Done },
5861 : // Convert__Reg1_3__TypedVectorList4_081_0__IndexRange0_151_1__Tie0_4_4__regXZR
5862 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5863 : // Convert__Reg1_3__TypedVectorList4_081_0__IndexRange0_151_1__Tie0_4_4__Reg1_5
5864 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5865 : // Convert__Reg1_3__TypedVectorList4_0641_0__IndexRange0_11_1__Tie0_4_4__regXZR
5866 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5867 : // Convert__Reg1_3__TypedVectorList4_0641_0__IndexRange0_11_1__Tie0_4_4__Reg1_5
5868 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5869 : // Convert__Reg1_3__TypedVectorList4_0161_0__IndexRange0_71_1__Tie0_4_4__regXZR
5870 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5871 : // Convert__Reg1_3__TypedVectorList4_0161_0__IndexRange0_71_1__Tie0_4_4__Reg1_5
5872 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5873 : // Convert__Reg1_3__TypedVectorList4_0321_0__IndexRange0_31_1__Tie0_4_4__regXZR
5874 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
5875 : // Convert__Reg1_3__TypedVectorList4_0321_0__IndexRange0_31_1__Tie0_4_4__Reg1_5
5876 : { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
5877 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_151_2__Tie0_5_5__regXZR
5878 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5879 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_151_2__Tie0_5_5__Reg1_6
5880 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5881 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_11_2__Tie0_5_5__regXZR
5882 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5883 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_11_2__Tie0_5_5__Reg1_6
5884 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5885 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_71_2__Tie0_5_5__regXZR
5886 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5887 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_71_2__Tie0_5_5__Reg1_6
5888 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5889 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_31_2__Tie0_5_5__regXZR
5890 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_regXZR, 0, CVT_Done },
5891 : // Convert__Reg1_4__VecListFour1281_1__IndexRange0_31_2__Tie0_5_5__Reg1_6
5892 : { CVT_95_Reg, 5, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 2, CVT_95_addVectorIndexOperands, 3, CVT_Tied, Tie0_5_5, CVT_95_Reg, 7, CVT_Done },
5893 : // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5894 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5895 : // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4
5896 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5897 : // Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
5898 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5899 : // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5900 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5901 : // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted641_4
5902 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5903 : // Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
5904 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5905 : // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5906 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5907 : // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted161_4
5908 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5909 : // Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
5910 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5911 : // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0
5912 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
5913 : // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4
5914 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addRegOperands, 5, CVT_Done },
5915 : // Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4
5916 : { CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_, 1, CVT_95_addRegOperands, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_4_GT_, 5, CVT_Done },
5917 : // Convert__regWZR__Reg1_0__Reg1_2
5918 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
5919 : // Convert__regXZR__Reg1_0__Reg1_2
5920 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
5921 : // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_5
5922 : { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_16_GT_, 6, CVT_Done },
5923 : // Convert__Reg1_0__Reg1_1__Reg1_3__SImm7s161_4
5924 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmScaledOperands_LT_16_GT_, 5, CVT_Done },
5925 : // Convert__Reg1_3__Reg1_0__Reg1_1__Tie0_4_4__SImm7s161_4
5926 : { CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_4_4, CVT_95_addImmScaledOperands_LT_16_GT_, 5, CVT_Done },
5927 : // Convert__Reg1_0__Reg1_1__Reg1_2__GPR64sp01_4
5928 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands, 5, CVT_Done },
5929 : // Convert__SVEVectorHReg1_0__SVEVectorBReg1_1
5930 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5931 : // Convert__SVEVectorSReg1_0__SVEVectorHReg1_1
5932 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5933 : // Convert__SVEVectorDReg1_0__SVEVectorSReg1_1
5934 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
5935 : // Convert__Reg1_0__Tie0_1_1__Reg1_1
5936 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
5937 : // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_7
5938 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_7, 0, CVT_Done },
5939 : // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_15
5940 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_15, 0, CVT_Done },
5941 : // Convert__VectorReg1281_1__VectorReg641_2__imm_95_0
5942 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg64Operands, 3, CVT_imm_95_0, 0, CVT_Done },
5943 : // Convert__VectorReg1281_0__VectorReg641_2__imm_95_0
5944 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg64Operands, 3, CVT_imm_95_0, 0, CVT_Done },
5945 : // Convert__VectorReg1281_1__VectorReg1281_2__imm_95_0
5946 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorReg128Operands, 3, CVT_imm_95_0, 0, CVT_Done },
5947 : // Convert__VectorReg1281_0__VectorReg1281_2__imm_95_0
5948 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_imm_95_0, 0, CVT_Done },
5949 : // Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_31
5950 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done },
5951 : // Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__regXZR
5952 : { CVT_95_addImmOperands, 1, CVT_95_addSysCROperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addImmOperands, 4, CVT_regXZR, 0, CVT_Done },
5953 : // Convert__Imm0_71_0__SysCR1_1__SysCR1_2__Imm0_71_3__Reg1_4
5954 : { CVT_95_addImmOperands, 1, CVT_95_addSysCROperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addImmOperands, 4, CVT_95_Reg, 5, CVT_Done },
5955 : // Convert__Reg1_0__Imm0_71_1__SysCR1_2__SysCR1_3__Imm0_71_4
5956 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addSysCROperands, 3, CVT_95_addSysCROperands, 4, CVT_95_addImmOperands, 5, CVT_Done },
5957 : // Convert__SVEVectorHReg1_0__SVEVectorList1161_1__SVEVectorHReg1_2
5958 : { CVT_95_addRegOperands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 2, CVT_95_addRegOperands, 3, CVT_Done },
5959 : // Convert__SVEVectorSReg1_0__SVEVectorList1321_1__SVEVectorSReg1_2
5960 : { CVT_95_addRegOperands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 2, CVT_95_addRegOperands, 3, CVT_Done },
5961 : // Convert__SVEVectorDReg1_0__SVEVectorList1641_1__SVEVectorDReg1_2
5962 : { CVT_95_addRegOperands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 2, CVT_95_addRegOperands, 3, CVT_Done },
5963 : // Convert__SVEVectorBReg1_0__SVEVectorList181_1__SVEVectorBReg1_2
5964 : { CVT_95_addRegOperands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_, 2, CVT_95_addRegOperands, 3, CVT_Done },
5965 : // Convert__VectorReg1281_1__VecListFour1281_2__VectorReg1281_3
5966 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5967 : // Convert__VectorReg1281_1__VecListOne1281_2__VectorReg1281_3
5968 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5969 : // Convert__VectorReg1281_1__VecListThree1281_2__VectorReg1281_3
5970 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5971 : // Convert__VectorReg1281_1__VecListTwo1281_2__VectorReg1281_3
5972 : { CVT_95_addVectorReg128Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5973 : // Convert__VectorReg641_1__VecListFour1281_2__VectorReg641_3
5974 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5975 : // Convert__VectorReg641_1__VecListOne1281_2__VectorReg641_3
5976 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5977 : // Convert__VectorReg641_1__VecListThree1281_2__VectorReg641_3
5978 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5979 : // Convert__VectorReg641_1__VecListTwo1281_2__VectorReg641_3
5980 : { CVT_95_addVectorReg64Operands, 2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5981 : // Convert__VectorReg1281_0__TypedVectorList4_1681_2__VectorReg1281_3
5982 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5983 : // Convert__VectorReg1281_0__TypedVectorList1_1681_2__VectorReg1281_3
5984 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5985 : // Convert__VectorReg1281_0__TypedVectorList3_1681_2__VectorReg1281_3
5986 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5987 : // Convert__VectorReg1281_0__TypedVectorList2_1681_2__VectorReg1281_3
5988 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
5989 : // Convert__VectorReg641_0__TypedVectorList4_1681_2__VectorReg641_3
5990 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5991 : // Convert__VectorReg641_0__TypedVectorList1_1681_2__VectorReg641_3
5992 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5993 : // Convert__VectorReg641_0__TypedVectorList3_1681_2__VectorReg641_3
5994 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5995 : // Convert__VectorReg641_0__TypedVectorList2_1681_2__VectorReg641_3
5996 : { CVT_95_addVectorReg64Operands, 1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
5997 : // Convert__Reg1_0__Imm0_311_1__BranchTarget141_2
5998 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
5999 : // Convert__Reg1_0__Imm32_631_1__BranchTarget141_2
6000 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
6001 : // Convert__GPR32as641_0__TBZImm0_311_1__BranchTarget141_2
6002 : { CVT_95_addGPR32as64Operands, 1, CVT_95_addImmOperands, 2, CVT_95_addBranchTarget14Operands, 3, CVT_Done },
6003 : // Convert__VectorReg1281_1__Tie0_2_2__VecListFour1281_2__VectorReg1281_3
6004 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6005 : // Convert__VectorReg1281_1__Tie0_2_2__VecListOne1281_2__VectorReg1281_3
6006 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6007 : // Convert__VectorReg1281_1__Tie0_2_2__VecListThree1281_2__VectorReg1281_3
6008 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6009 : // Convert__VectorReg1281_1__Tie0_2_2__VecListTwo1281_2__VectorReg1281_3
6010 : { CVT_95_addVectorReg128Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6011 : // Convert__VectorReg641_1__Tie0_2_2__VecListFour1281_2__VectorReg641_3
6012 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6013 : // Convert__VectorReg641_1__Tie0_2_2__VecListOne1281_2__VectorReg641_3
6014 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6015 : // Convert__VectorReg641_1__Tie0_2_2__VecListThree1281_2__VectorReg641_3
6016 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6017 : // Convert__VectorReg641_1__Tie0_2_2__VecListTwo1281_2__VectorReg641_3
6018 : { CVT_95_addVectorReg64Operands, 2, CVT_Tied, Tie0_2_2, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6019 : // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg1281_3
6020 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6021 : // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg1281_3
6022 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6023 : // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg1281_3
6024 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6025 : // Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg1281_3
6026 : { CVT_95_addVectorReg128Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg128Operands, 4, CVT_Done },
6027 : // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg641_3
6028 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6029 : // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg641_3
6030 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6031 : // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList3_1681_2__VectorReg641_3
6032 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6033 : // Convert__VectorReg641_0__Tie0_1_1__TypedVectorList2_1681_2__VectorReg641_3
6034 : { CVT_95_addVectorReg64Operands, 1, CVT_Tied, Tie0_1_1, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 3, CVT_95_addVectorReg64Operands, 4, CVT_Done },
6035 : // Convert__SVEPredicateHReg1_0__SVEPredicateHReg1_1__SVEPredicateHReg1_2
6036 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
6037 : // Convert__SVEPredicateSReg1_0__SVEPredicateSReg1_1__SVEPredicateSReg1_2
6038 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
6039 : // Convert__SVEPredicateDReg1_0__SVEPredicateDReg1_1__SVEPredicateDReg1_2
6040 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
6041 : // Convert__SVEPredicateBReg1_0__SVEPredicateBReg1_1__SVEPredicateBReg1_2
6042 : { CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
6043 : // Convert__regWZR__Reg1_0__LogicalImm321_1
6044 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_, 2, CVT_Done },
6045 : // Convert__regXZR__Reg1_0__LogicalImm641_1
6046 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_, 2, CVT_Done },
6047 : // Convert__regWZR__Reg1_0__Reg1_1__LogicalShifter321_2
6048 : { CVT_regWZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
6049 : // Convert__regXZR__Reg1_0__Reg1_1__LogicalShifter641_2
6050 : { CVT_regXZR, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addShifterOperands, 3, CVT_Done },
6051 : // Convert__SVEVectorHReg1_0__Tie0_1_2__Imm0_2551_2
6052 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
6053 : // Convert__SVEVectorSReg1_0__Tie0_1_2__Imm0_2551_2
6054 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
6055 : // Convert__SVEVectorDReg1_0__Tie0_1_2__Imm0_2551_2
6056 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
6057 : // Convert__SVEVectorBReg1_0__Tie0_1_2__Imm0_2551_2
6058 : { CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addImmOperands, 3, CVT_Done },
6059 : // Convert__imm_95_2
6060 : { CVT_imm_95_2, 0, CVT_Done },
6061 : // Convert__imm_95_3
6062 : { CVT_imm_95_3, 0, CVT_Done },
6063 : // Convert__SVEPredicateHReg1_0__Reg1_1__Reg1_2
6064 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
6065 : // Convert__SVEPredicateSReg1_0__Reg1_1__Reg1_2
6066 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
6067 : // Convert__SVEPredicateDReg1_0__Reg1_1__Reg1_2
6068 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
6069 : // Convert__SVEPredicateBReg1_0__Reg1_1__Reg1_2
6070 : { CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
6071 : // Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4__UImm61_6
6072 : { CVT_95_addVectorReg128Operands, 1, CVT_95_addVectorReg128Operands, 3, CVT_95_addVectorReg128Operands, 5, CVT_95_addUImm6Operands, 7, CVT_Done },
6073 : // Convert__imm_95_1
6074 : { CVT_imm_95_1, 0, CVT_Done },
6075 : };
6076 :
6077 0 : void AArch64AsmParser::
6078 : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
6079 : const OperandVector &Operands) {
6080 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
6081 0 : const uint8_t *Converter = ConversionTable[Kind];
6082 : unsigned OpIdx;
6083 : Inst.setOpcode(Opcode);
6084 0 : for (const uint8_t *p = Converter; *p; p+= 2) {
6085 0 : OpIdx = *(p + 1);
6086 0 : switch (*p) {
6087 0 : default: llvm_unreachable("invalid conversion entry!");
6088 0 : case CVT_Reg:
6089 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
6090 : break;
6091 0 : case CVT_Tied: {
6092 : assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
6093 : std::begin(TiedAsmOperandTable)) &&
6094 : "Tied operand not found");
6095 0 : unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
6096 0 : if (TiedResOpnd != (uint8_t) -1)
6097 : Inst.addOperand(Inst.getOperand(TiedResOpnd));
6098 : break;
6099 : }
6100 0 : case CVT_95_Reg:
6101 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
6102 : break;
6103 0 : case CVT_95_addVectorReg128Operands:
6104 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorReg128Operands(Inst, 1);
6105 : break;
6106 0 : case CVT_95_addVectorReg64Operands:
6107 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorReg64Operands(Inst, 1);
6108 : break;
6109 0 : case CVT_95_addRegOperands:
6110 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
6111 : break;
6112 : case CVT_imm_95_16:
6113 0 : Inst.addOperand(MCOperand::createImm(16));
6114 0 : break;
6115 : case CVT_imm_95_24:
6116 0 : Inst.addOperand(MCOperand::createImm(24));
6117 0 : break;
6118 : case CVT_imm_95_0:
6119 0 : Inst.addOperand(MCOperand::createImm(0));
6120 0 : break;
6121 0 : case CVT_95_addImmNegWithOptionalShiftOperands_LT_12_GT_:
6122 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmNegWithOptionalShiftOperands<12>(Inst, 2);
6123 0 : break;
6124 0 : case CVT_95_addImmWithOptionalShiftOperands_LT_12_GT_:
6125 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmWithOptionalShiftOperands<12>(Inst, 2);
6126 0 : break;
6127 0 : case CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_:
6128 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmWithOptionalShiftOperands<8>(Inst, 2);
6129 0 : break;
6130 0 : case CVT_95_addShifterOperands:
6131 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addShifterOperands(Inst, 1);
6132 0 : break;
6133 0 : case CVT_95_addExtendOperands:
6134 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addExtendOperands(Inst, 1);
6135 0 : break;
6136 0 : case CVT_95_addExtend64Operands:
6137 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addExtend64Operands(Inst, 1);
6138 0 : break;
6139 0 : case CVT_95_addImmScaledOperands_LT_16_GT_:
6140 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<16>(Inst, 1);
6141 : break;
6142 0 : case CVT_95_addImmOperands:
6143 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
6144 : break;
6145 0 : case CVT_95_addAdrLabelOperands:
6146 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
6147 : break;
6148 0 : case CVT_95_addAdrpLabelOperands:
6149 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addAdrpLabelOperands(Inst, 1);
6150 0 : break;
6151 0 : case CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_:
6152 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int32_t>(Inst, 1);
6153 0 : break;
6154 0 : case CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_:
6155 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int64_t>(Inst, 1);
6156 0 : break;
6157 0 : case CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_:
6158 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int16_t>(Inst, 1);
6159 0 : break;
6160 0 : case CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_:
6161 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int8_t>(Inst, 1);
6162 0 : break;
6163 : case CVT_imm_95_31:
6164 0 : Inst.addOperand(MCOperand::createImm(31));
6165 0 : break;
6166 : case CVT_imm_95_63:
6167 0 : Inst.addOperand(MCOperand::createImm(63));
6168 0 : break;
6169 0 : case CVT_95_addBranchTarget26Operands:
6170 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addBranchTarget26Operands(Inst, 1);
6171 0 : break;
6172 0 : case CVT_95_addCondCodeOperands:
6173 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 1);
6174 : break;
6175 0 : case CVT_95_addPCRelLabel19Operands:
6176 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addPCRelLabel19Operands(Inst, 1);
6177 0 : break;
6178 0 : case CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_:
6179 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int32_t>(Inst, 1);
6180 0 : break;
6181 0 : case CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_:
6182 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int64_t>(Inst, 1);
6183 0 : break;
6184 0 : case CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_:
6185 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int16_t>(Inst, 1);
6186 0 : break;
6187 0 : case CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_:
6188 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int8_t>(Inst, 1);
6189 0 : break;
6190 : case CVT_imm_95_32:
6191 0 : Inst.addOperand(MCOperand::createImm(32));
6192 0 : break;
6193 0 : case CVT_95_addBTIHintOperands:
6194 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addBTIHintOperands(Inst, 1);
6195 : break;
6196 : case CVT_imm_95_15:
6197 0 : Inst.addOperand(MCOperand::createImm(15));
6198 0 : break;
6199 : case CVT_regWZR:
6200 0 : Inst.addOperand(MCOperand::createReg(AArch64::WZR));
6201 0 : break;
6202 : case CVT_regXZR:
6203 0 : Inst.addOperand(MCOperand::createReg(AArch64::XZR));
6204 0 : break;
6205 : case CVT_imm_95_1:
6206 0 : Inst.addOperand(MCOperand::createImm(1));
6207 0 : break;
6208 : case CVT_imm_95_20:
6209 0 : Inst.addOperand(MCOperand::createImm(20));
6210 0 : break;
6211 0 : case CVT_95_addBarrierOperands:
6212 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addBarrierOperands(Inst, 1);
6213 : break;
6214 0 : case CVT_95_addVectorIndexOperands:
6215 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorIndexOperands(Inst, 1);
6216 : break;
6217 0 : case CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_:
6218 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addExactFPImmOperands<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(Inst, 1);
6219 0 : break;
6220 0 : case CVT_95_addComplexRotationOddOperands:
6221 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
6222 : break;
6223 0 : case CVT_95_addComplexRotationEvenOperands:
6224 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
6225 : break;
6226 0 : case CVT_95_addFPImmOperands:
6227 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
6228 0 : break;
6229 0 : case CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_zero_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_:
6230 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addExactFPImmOperands<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(Inst, 1);
6231 0 : break;
6232 0 : case CVT_95_addVectorRegLoOperands:
6233 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorRegLoOperands(Inst, 1);
6234 : break;
6235 0 : case CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_two_GT_:
6236 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addExactFPImmOperands<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(Inst, 1);
6237 0 : break;
6238 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_:
6239 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 4>(Inst, 1);
6240 : break;
6241 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_:
6242 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 4>(Inst, 1);
6243 : break;
6244 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_:
6245 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 1>(Inst, 1);
6246 : break;
6247 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_:
6248 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 1>(Inst, 1);
6249 : break;
6250 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_:
6251 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 3>(Inst, 1);
6252 : break;
6253 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_:
6254 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 3>(Inst, 1);
6255 : break;
6256 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_:
6257 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_QReg, 2>(Inst, 1);
6258 : break;
6259 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_:
6260 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_DReg, 2>(Inst, 1);
6261 : break;
6262 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_:
6263 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 1>(Inst, 1);
6264 : break;
6265 0 : case CVT_95_addImmScaledOperands_LT_1_GT_:
6266 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<1>(Inst, 1);
6267 : break;
6268 0 : case CVT_95_addImmScaledOperands_LT_8_GT_:
6269 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<8>(Inst, 1);
6270 : break;
6271 0 : case CVT_95_addImmScaledOperands_LT_2_GT_:
6272 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<2>(Inst, 1);
6273 : break;
6274 0 : case CVT_95_addImmScaledOperands_LT_4_GT_:
6275 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<4>(Inst, 1);
6276 : break;
6277 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_:
6278 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 2>(Inst, 1);
6279 : break;
6280 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_:
6281 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 3>(Inst, 1);
6282 : break;
6283 0 : case CVT_95_addImmScaledOperands_LT_3_GT_:
6284 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addImmScaledOperands<3>(Inst, 1);
6285 : break;
6286 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_:
6287 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addVectorListOperands<AArch64Operand::VecListIdx_ZReg, 4>(Inst, 1);
6288 : break;
6289 0 : case CVT_95_addUImm12OffsetOperands_LT_4_GT_:
6290 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<4>(Inst, 1);
6291 0 : break;
6292 0 : case CVT_95_addUImm12OffsetOperands_LT_8_GT_:
6293 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<8>(Inst, 1);
6294 0 : break;
6295 0 : case CVT_95_addUImm12OffsetOperands_LT_1_GT_:
6296 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<1>(Inst, 1);
6297 0 : break;
6298 0 : case CVT_95_addUImm12OffsetOperands_LT_2_GT_:
6299 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<2>(Inst, 1);
6300 0 : break;
6301 0 : case CVT_95_addUImm12OffsetOperands_LT_16_GT_:
6302 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm12OffsetOperands<16>(Inst, 1);
6303 0 : break;
6304 0 : case CVT_95_addMemExtendOperands:
6305 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMemExtendOperands(Inst, 2);
6306 0 : break;
6307 0 : case CVT_95_addMemExtend8Operands:
6308 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMemExtend8Operands(Inst, 2);
6309 0 : break;
6310 0 : case CVT_95_addMOVZMovAliasOperands_LT_0_GT_:
6311 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<0>(Inst, 1);
6312 : break;
6313 0 : case CVT_95_addMOVZMovAliasOperands_LT_16_GT_:
6314 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<16>(Inst, 1);
6315 : break;
6316 0 : case CVT_95_addMOVNMovAliasOperands_LT_0_GT_:
6317 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<0>(Inst, 1);
6318 : break;
6319 0 : case CVT_95_addMOVNMovAliasOperands_LT_16_GT_:
6320 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<16>(Inst, 1);
6321 : break;
6322 0 : case CVT_95_addMOVZMovAliasOperands_LT_32_GT_:
6323 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<32>(Inst, 1);
6324 : break;
6325 0 : case CVT_95_addMOVZMovAliasOperands_LT_48_GT_:
6326 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVZMovAliasOperands<48>(Inst, 1);
6327 : break;
6328 : case CVT_imm_95_48:
6329 0 : Inst.addOperand(MCOperand::createImm(48));
6330 0 : break;
6331 0 : case CVT_95_addMOVNMovAliasOperands_LT_32_GT_:
6332 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<32>(Inst, 1);
6333 : break;
6334 0 : case CVT_95_addMOVNMovAliasOperands_LT_48_GT_:
6335 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMOVNMovAliasOperands<48>(Inst, 1);
6336 : break;
6337 0 : case CVT_95_addFPRasZPRRegOperands_LT_128_GT_:
6338 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPRasZPRRegOperands<128>(Inst, 1);
6339 : break;
6340 0 : case CVT_95_addFPRasZPRRegOperands_LT_16_GT_:
6341 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPRasZPRRegOperands<16>(Inst, 1);
6342 : break;
6343 0 : case CVT_95_addFPRasZPRRegOperands_LT_32_GT_:
6344 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPRasZPRRegOperands<32>(Inst, 1);
6345 : break;
6346 0 : case CVT_95_addFPRasZPRRegOperands_LT_64_GT_:
6347 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPRasZPRRegOperands<64>(Inst, 1);
6348 : break;
6349 0 : case CVT_95_addFPRasZPRRegOperands_LT_8_GT_:
6350 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addFPRasZPRRegOperands<8>(Inst, 1);
6351 : break;
6352 0 : case CVT_95_addSIMDImmType10Operands:
6353 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addSIMDImmType10Operands(Inst, 1);
6354 0 : break;
6355 0 : case CVT_95_addMRSSystemRegisterOperands:
6356 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMRSSystemRegisterOperands(Inst, 1);
6357 : break;
6358 0 : case CVT_95_addMSRSystemRegisterOperands:
6359 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addMSRSystemRegisterOperands(Inst, 1);
6360 : break;
6361 0 : case CVT_95_addSystemPStateFieldWithImm0_95_15Operands:
6362 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addSystemPStateFieldWithImm0_15Operands(Inst, 1);
6363 : break;
6364 0 : case CVT_95_addSystemPStateFieldWithImm0_95_1Operands:
6365 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addSystemPStateFieldWithImm0_1Operands(Inst, 1);
6366 : break;
6367 0 : case CVT_95_addPrefetchOperands:
6368 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addPrefetchOperands(Inst, 1);
6369 : break;
6370 0 : case CVT_95_addPSBHintOperands:
6371 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addPSBHintOperands(Inst, 1);
6372 : break;
6373 : case CVT_imm_95_4:
6374 0 : Inst.addOperand(MCOperand::createImm(4));
6375 0 : break;
6376 : case CVT_regLR:
6377 0 : Inst.addOperand(MCOperand::createReg(AArch64::LR));
6378 0 : break;
6379 0 : case CVT_95_addUImm6Operands:
6380 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addUImm6Operands(Inst, 1);
6381 : break;
6382 : case CVT_imm_95_5:
6383 0 : Inst.addOperand(MCOperand::createImm(5));
6384 0 : break;
6385 0 : case CVT_95_addGPR64as32Operands:
6386 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addGPR64as32Operands(Inst, 1);
6387 0 : break;
6388 : case CVT_imm_95_7:
6389 0 : Inst.addOperand(MCOperand::createImm(7));
6390 0 : break;
6391 0 : case CVT_95_addSysCROperands:
6392 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addSysCROperands(Inst, 1);
6393 : break;
6394 0 : case CVT_95_addBranchTarget14Operands:
6395 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addBranchTarget14Operands(Inst, 1);
6396 0 : break;
6397 0 : case CVT_95_addGPR32as64Operands:
6398 0 : static_cast<AArch64Operand&>(*Operands[OpIdx]).addGPR32as64Operands(Inst, 1);
6399 0 : break;
6400 : case CVT_imm_95_2:
6401 0 : Inst.addOperand(MCOperand::createImm(2));
6402 0 : break;
6403 : case CVT_imm_95_3:
6404 0 : Inst.addOperand(MCOperand::createImm(3));
6405 0 : break;
6406 : }
6407 : }
6408 0 : }
6409 :
6410 0 : void AArch64AsmParser::
6411 : convertToMapAndConstraints(unsigned Kind,
6412 : const OperandVector &Operands) {
6413 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
6414 : unsigned NumMCOperands = 0;
6415 0 : const uint8_t *Converter = ConversionTable[Kind];
6416 0 : for (const uint8_t *p = Converter; *p; p+= 2) {
6417 0 : switch (*p) {
6418 0 : default: llvm_unreachable("invalid conversion entry!");
6419 0 : case CVT_Reg:
6420 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6421 0 : Operands[*(p + 1)]->setConstraint("r");
6422 0 : ++NumMCOperands;
6423 0 : break;
6424 0 : case CVT_Tied:
6425 0 : ++NumMCOperands;
6426 0 : break;
6427 0 : case CVT_95_Reg:
6428 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6429 0 : Operands[*(p + 1)]->setConstraint("r");
6430 0 : NumMCOperands += 1;
6431 0 : break;
6432 0 : case CVT_95_addVectorReg128Operands:
6433 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6434 0 : Operands[*(p + 1)]->setConstraint("m");
6435 0 : NumMCOperands += 1;
6436 0 : break;
6437 0 : case CVT_95_addVectorReg64Operands:
6438 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6439 0 : Operands[*(p + 1)]->setConstraint("m");
6440 0 : NumMCOperands += 1;
6441 0 : break;
6442 0 : case CVT_95_addRegOperands:
6443 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6444 0 : Operands[*(p + 1)]->setConstraint("m");
6445 0 : NumMCOperands += 1;
6446 0 : break;
6447 0 : case CVT_imm_95_16:
6448 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6449 0 : Operands[*(p + 1)]->setConstraint("");
6450 0 : ++NumMCOperands;
6451 0 : break;
6452 0 : case CVT_imm_95_24:
6453 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6454 0 : Operands[*(p + 1)]->setConstraint("");
6455 0 : ++NumMCOperands;
6456 0 : break;
6457 0 : case CVT_imm_95_0:
6458 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6459 0 : Operands[*(p + 1)]->setConstraint("");
6460 0 : ++NumMCOperands;
6461 0 : break;
6462 0 : case CVT_95_addImmNegWithOptionalShiftOperands_LT_12_GT_:
6463 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6464 0 : Operands[*(p + 1)]->setConstraint("m");
6465 0 : NumMCOperands += 2;
6466 0 : break;
6467 0 : case CVT_95_addImmWithOptionalShiftOperands_LT_12_GT_:
6468 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6469 0 : Operands[*(p + 1)]->setConstraint("m");
6470 0 : NumMCOperands += 2;
6471 0 : break;
6472 0 : case CVT_95_addImmWithOptionalShiftOperands_LT_8_GT_:
6473 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6474 0 : Operands[*(p + 1)]->setConstraint("m");
6475 0 : NumMCOperands += 2;
6476 0 : break;
6477 0 : case CVT_95_addShifterOperands:
6478 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6479 0 : Operands[*(p + 1)]->setConstraint("m");
6480 0 : NumMCOperands += 1;
6481 0 : break;
6482 0 : case CVT_95_addExtendOperands:
6483 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6484 0 : Operands[*(p + 1)]->setConstraint("m");
6485 0 : NumMCOperands += 1;
6486 0 : break;
6487 0 : case CVT_95_addExtend64Operands:
6488 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6489 0 : Operands[*(p + 1)]->setConstraint("m");
6490 0 : NumMCOperands += 1;
6491 0 : break;
6492 0 : case CVT_95_addImmScaledOperands_LT_16_GT_:
6493 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6494 0 : Operands[*(p + 1)]->setConstraint("m");
6495 0 : NumMCOperands += 1;
6496 0 : break;
6497 0 : case CVT_95_addImmOperands:
6498 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6499 0 : Operands[*(p + 1)]->setConstraint("m");
6500 0 : NumMCOperands += 1;
6501 0 : break;
6502 0 : case CVT_95_addAdrLabelOperands:
6503 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6504 0 : Operands[*(p + 1)]->setConstraint("m");
6505 0 : NumMCOperands += 1;
6506 0 : break;
6507 0 : case CVT_95_addAdrpLabelOperands:
6508 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6509 0 : Operands[*(p + 1)]->setConstraint("m");
6510 0 : NumMCOperands += 1;
6511 0 : break;
6512 0 : case CVT_95_addLogicalImmOperands_LT_int32_95_t_GT_:
6513 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6514 0 : Operands[*(p + 1)]->setConstraint("m");
6515 0 : NumMCOperands += 1;
6516 0 : break;
6517 0 : case CVT_95_addLogicalImmOperands_LT_int64_95_t_GT_:
6518 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6519 0 : Operands[*(p + 1)]->setConstraint("m");
6520 0 : NumMCOperands += 1;
6521 0 : break;
6522 0 : case CVT_95_addLogicalImmOperands_LT_int16_95_t_GT_:
6523 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6524 0 : Operands[*(p + 1)]->setConstraint("m");
6525 0 : NumMCOperands += 1;
6526 0 : break;
6527 0 : case CVT_95_addLogicalImmOperands_LT_int8_95_t_GT_:
6528 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6529 0 : Operands[*(p + 1)]->setConstraint("m");
6530 0 : NumMCOperands += 1;
6531 0 : break;
6532 0 : case CVT_imm_95_31:
6533 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6534 0 : Operands[*(p + 1)]->setConstraint("");
6535 0 : ++NumMCOperands;
6536 0 : break;
6537 0 : case CVT_imm_95_63:
6538 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6539 0 : Operands[*(p + 1)]->setConstraint("");
6540 0 : ++NumMCOperands;
6541 0 : break;
6542 0 : case CVT_95_addBranchTarget26Operands:
6543 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6544 0 : Operands[*(p + 1)]->setConstraint("m");
6545 0 : NumMCOperands += 1;
6546 0 : break;
6547 0 : case CVT_95_addCondCodeOperands:
6548 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6549 0 : Operands[*(p + 1)]->setConstraint("m");
6550 0 : NumMCOperands += 1;
6551 0 : break;
6552 0 : case CVT_95_addPCRelLabel19Operands:
6553 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6554 0 : Operands[*(p + 1)]->setConstraint("m");
6555 0 : NumMCOperands += 1;
6556 0 : break;
6557 0 : case CVT_95_addLogicalImmNotOperands_LT_int32_95_t_GT_:
6558 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6559 0 : Operands[*(p + 1)]->setConstraint("m");
6560 0 : NumMCOperands += 1;
6561 0 : break;
6562 0 : case CVT_95_addLogicalImmNotOperands_LT_int64_95_t_GT_:
6563 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6564 0 : Operands[*(p + 1)]->setConstraint("m");
6565 0 : NumMCOperands += 1;
6566 0 : break;
6567 0 : case CVT_95_addLogicalImmNotOperands_LT_int16_95_t_GT_:
6568 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6569 0 : Operands[*(p + 1)]->setConstraint("m");
6570 0 : NumMCOperands += 1;
6571 0 : break;
6572 0 : case CVT_95_addLogicalImmNotOperands_LT_int8_95_t_GT_:
6573 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6574 0 : Operands[*(p + 1)]->setConstraint("m");
6575 0 : NumMCOperands += 1;
6576 0 : break;
6577 0 : case CVT_imm_95_32:
6578 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6579 0 : Operands[*(p + 1)]->setConstraint("");
6580 0 : ++NumMCOperands;
6581 0 : break;
6582 0 : case CVT_95_addBTIHintOperands:
6583 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6584 0 : Operands[*(p + 1)]->setConstraint("m");
6585 0 : NumMCOperands += 1;
6586 0 : break;
6587 0 : case CVT_imm_95_15:
6588 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6589 0 : Operands[*(p + 1)]->setConstraint("");
6590 0 : ++NumMCOperands;
6591 0 : break;
6592 0 : case CVT_regWZR:
6593 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6594 0 : Operands[*(p + 1)]->setConstraint("m");
6595 0 : ++NumMCOperands;
6596 0 : break;
6597 0 : case CVT_regXZR:
6598 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6599 0 : Operands[*(p + 1)]->setConstraint("m");
6600 0 : ++NumMCOperands;
6601 0 : break;
6602 0 : case CVT_imm_95_1:
6603 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6604 0 : Operands[*(p + 1)]->setConstraint("");
6605 0 : ++NumMCOperands;
6606 0 : break;
6607 0 : case CVT_imm_95_20:
6608 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6609 0 : Operands[*(p + 1)]->setConstraint("");
6610 0 : ++NumMCOperands;
6611 0 : break;
6612 0 : case CVT_95_addBarrierOperands:
6613 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6614 0 : Operands[*(p + 1)]->setConstraint("m");
6615 0 : NumMCOperands += 1;
6616 0 : break;
6617 0 : case CVT_95_addVectorIndexOperands:
6618 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6619 0 : Operands[*(p + 1)]->setConstraint("m");
6620 0 : NumMCOperands += 1;
6621 0 : break;
6622 0 : case CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_:
6623 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6624 0 : Operands[*(p + 1)]->setConstraint("m");
6625 0 : NumMCOperands += 1;
6626 0 : break;
6627 0 : case CVT_95_addComplexRotationOddOperands:
6628 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6629 0 : Operands[*(p + 1)]->setConstraint("m");
6630 0 : NumMCOperands += 1;
6631 0 : break;
6632 0 : case CVT_95_addComplexRotationEvenOperands:
6633 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6634 0 : Operands[*(p + 1)]->setConstraint("m");
6635 0 : NumMCOperands += 1;
6636 0 : break;
6637 0 : case CVT_95_addFPImmOperands:
6638 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6639 0 : Operands[*(p + 1)]->setConstraint("m");
6640 0 : NumMCOperands += 1;
6641 0 : break;
6642 0 : case CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_zero_44__32_AArch64ExactFPImm_COLON__COLON_one_GT_:
6643 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6644 0 : Operands[*(p + 1)]->setConstraint("m");
6645 0 : NumMCOperands += 1;
6646 0 : break;
6647 0 : case CVT_95_addVectorRegLoOperands:
6648 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6649 0 : Operands[*(p + 1)]->setConstraint("m");
6650 0 : NumMCOperands += 1;
6651 0 : break;
6652 0 : case CVT_95_addExactFPImmOperands_LT_AArch64ExactFPImm_COLON__COLON_half_44__32_AArch64ExactFPImm_COLON__COLON_two_GT_:
6653 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6654 0 : Operands[*(p + 1)]->setConstraint("m");
6655 0 : NumMCOperands += 1;
6656 0 : break;
6657 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_:
6658 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6659 0 : Operands[*(p + 1)]->setConstraint("m");
6660 0 : NumMCOperands += 1;
6661 0 : break;
6662 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_4_GT_:
6663 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6664 0 : Operands[*(p + 1)]->setConstraint("m");
6665 0 : NumMCOperands += 1;
6666 0 : break;
6667 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_:
6668 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6669 0 : Operands[*(p + 1)]->setConstraint("m");
6670 0 : NumMCOperands += 1;
6671 0 : break;
6672 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_1_GT_:
6673 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6674 0 : Operands[*(p + 1)]->setConstraint("m");
6675 0 : NumMCOperands += 1;
6676 0 : break;
6677 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_:
6678 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6679 0 : Operands[*(p + 1)]->setConstraint("m");
6680 0 : NumMCOperands += 1;
6681 0 : break;
6682 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_3_GT_:
6683 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6684 0 : Operands[*(p + 1)]->setConstraint("m");
6685 0 : NumMCOperands += 1;
6686 0 : break;
6687 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_:
6688 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6689 0 : Operands[*(p + 1)]->setConstraint("m");
6690 0 : NumMCOperands += 1;
6691 0 : break;
6692 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_DReg_44__32_2_GT_:
6693 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6694 0 : Operands[*(p + 1)]->setConstraint("m");
6695 0 : NumMCOperands += 1;
6696 0 : break;
6697 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_1_GT_:
6698 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6699 0 : Operands[*(p + 1)]->setConstraint("m");
6700 0 : NumMCOperands += 1;
6701 0 : break;
6702 0 : case CVT_95_addImmScaledOperands_LT_1_GT_:
6703 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6704 0 : Operands[*(p + 1)]->setConstraint("m");
6705 0 : NumMCOperands += 1;
6706 0 : break;
6707 0 : case CVT_95_addImmScaledOperands_LT_8_GT_:
6708 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6709 0 : Operands[*(p + 1)]->setConstraint("m");
6710 0 : NumMCOperands += 1;
6711 0 : break;
6712 0 : case CVT_95_addImmScaledOperands_LT_2_GT_:
6713 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6714 0 : Operands[*(p + 1)]->setConstraint("m");
6715 0 : NumMCOperands += 1;
6716 0 : break;
6717 0 : case CVT_95_addImmScaledOperands_LT_4_GT_:
6718 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6719 0 : Operands[*(p + 1)]->setConstraint("m");
6720 0 : NumMCOperands += 1;
6721 0 : break;
6722 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_2_GT_:
6723 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6724 0 : Operands[*(p + 1)]->setConstraint("m");
6725 0 : NumMCOperands += 1;
6726 0 : break;
6727 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_3_GT_:
6728 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6729 0 : Operands[*(p + 1)]->setConstraint("m");
6730 0 : NumMCOperands += 1;
6731 0 : break;
6732 0 : case CVT_95_addImmScaledOperands_LT_3_GT_:
6733 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6734 0 : Operands[*(p + 1)]->setConstraint("m");
6735 0 : NumMCOperands += 1;
6736 0 : break;
6737 0 : case CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_ZReg_44__32_4_GT_:
6738 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6739 0 : Operands[*(p + 1)]->setConstraint("m");
6740 0 : NumMCOperands += 1;
6741 0 : break;
6742 0 : case CVT_95_addUImm12OffsetOperands_LT_4_GT_:
6743 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6744 0 : Operands[*(p + 1)]->setConstraint("m");
6745 0 : NumMCOperands += 1;
6746 0 : break;
6747 0 : case CVT_95_addUImm12OffsetOperands_LT_8_GT_:
6748 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6749 0 : Operands[*(p + 1)]->setConstraint("m");
6750 0 : NumMCOperands += 1;
6751 0 : break;
6752 0 : case CVT_95_addUImm12OffsetOperands_LT_1_GT_:
6753 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6754 0 : Operands[*(p + 1)]->setConstraint("m");
6755 0 : NumMCOperands += 1;
6756 0 : break;
6757 0 : case CVT_95_addUImm12OffsetOperands_LT_2_GT_:
6758 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6759 0 : Operands[*(p + 1)]->setConstraint("m");
6760 0 : NumMCOperands += 1;
6761 0 : break;
6762 0 : case CVT_95_addUImm12OffsetOperands_LT_16_GT_:
6763 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6764 0 : Operands[*(p + 1)]->setConstraint("m");
6765 0 : NumMCOperands += 1;
6766 0 : break;
6767 0 : case CVT_95_addMemExtendOperands:
6768 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6769 0 : Operands[*(p + 1)]->setConstraint("m");
6770 0 : NumMCOperands += 2;
6771 0 : break;
6772 0 : case CVT_95_addMemExtend8Operands:
6773 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6774 0 : Operands[*(p + 1)]->setConstraint("m");
6775 0 : NumMCOperands += 2;
6776 0 : break;
6777 0 : case CVT_95_addMOVZMovAliasOperands_LT_0_GT_:
6778 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6779 0 : Operands[*(p + 1)]->setConstraint("m");
6780 0 : NumMCOperands += 1;
6781 0 : break;
6782 0 : case CVT_95_addMOVZMovAliasOperands_LT_16_GT_:
6783 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6784 0 : Operands[*(p + 1)]->setConstraint("m");
6785 0 : NumMCOperands += 1;
6786 0 : break;
6787 0 : case CVT_95_addMOVNMovAliasOperands_LT_0_GT_:
6788 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6789 0 : Operands[*(p + 1)]->setConstraint("m");
6790 0 : NumMCOperands += 1;
6791 0 : break;
6792 0 : case CVT_95_addMOVNMovAliasOperands_LT_16_GT_:
6793 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6794 0 : Operands[*(p + 1)]->setConstraint("m");
6795 0 : NumMCOperands += 1;
6796 0 : break;
6797 0 : case CVT_95_addMOVZMovAliasOperands_LT_32_GT_:
6798 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6799 0 : Operands[*(p + 1)]->setConstraint("m");
6800 0 : NumMCOperands += 1;
6801 0 : break;
6802 0 : case CVT_95_addMOVZMovAliasOperands_LT_48_GT_:
6803 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6804 0 : Operands[*(p + 1)]->setConstraint("m");
6805 0 : NumMCOperands += 1;
6806 0 : break;
6807 0 : case CVT_imm_95_48:
6808 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6809 0 : Operands[*(p + 1)]->setConstraint("");
6810 0 : ++NumMCOperands;
6811 0 : break;
6812 0 : case CVT_95_addMOVNMovAliasOperands_LT_32_GT_:
6813 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6814 0 : Operands[*(p + 1)]->setConstraint("m");
6815 0 : NumMCOperands += 1;
6816 0 : break;
6817 0 : case CVT_95_addMOVNMovAliasOperands_LT_48_GT_:
6818 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6819 0 : Operands[*(p + 1)]->setConstraint("m");
6820 0 : NumMCOperands += 1;
6821 0 : break;
6822 0 : case CVT_95_addFPRasZPRRegOperands_LT_128_GT_:
6823 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6824 0 : Operands[*(p + 1)]->setConstraint("m");
6825 0 : NumMCOperands += 1;
6826 0 : break;
6827 0 : case CVT_95_addFPRasZPRRegOperands_LT_16_GT_:
6828 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6829 0 : Operands[*(p + 1)]->setConstraint("m");
6830 0 : NumMCOperands += 1;
6831 0 : break;
6832 0 : case CVT_95_addFPRasZPRRegOperands_LT_32_GT_:
6833 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6834 0 : Operands[*(p + 1)]->setConstraint("m");
6835 0 : NumMCOperands += 1;
6836 0 : break;
6837 0 : case CVT_95_addFPRasZPRRegOperands_LT_64_GT_:
6838 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6839 0 : Operands[*(p + 1)]->setConstraint("m");
6840 0 : NumMCOperands += 1;
6841 0 : break;
6842 0 : case CVT_95_addFPRasZPRRegOperands_LT_8_GT_:
6843 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6844 0 : Operands[*(p + 1)]->setConstraint("m");
6845 0 : NumMCOperands += 1;
6846 0 : break;
6847 0 : case CVT_95_addSIMDImmType10Operands:
6848 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6849 0 : Operands[*(p + 1)]->setConstraint("m");
6850 0 : NumMCOperands += 1;
6851 0 : break;
6852 0 : case CVT_95_addMRSSystemRegisterOperands:
6853 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6854 0 : Operands[*(p + 1)]->setConstraint("m");
6855 0 : NumMCOperands += 1;
6856 0 : break;
6857 0 : case CVT_95_addMSRSystemRegisterOperands:
6858 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6859 0 : Operands[*(p + 1)]->setConstraint("m");
6860 0 : NumMCOperands += 1;
6861 0 : break;
6862 0 : case CVT_95_addSystemPStateFieldWithImm0_95_15Operands:
6863 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6864 0 : Operands[*(p + 1)]->setConstraint("m");
6865 0 : NumMCOperands += 1;
6866 0 : break;
6867 0 : case CVT_95_addSystemPStateFieldWithImm0_95_1Operands:
6868 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6869 0 : Operands[*(p + 1)]->setConstraint("m");
6870 0 : NumMCOperands += 1;
6871 0 : break;
6872 0 : case CVT_95_addPrefetchOperands:
6873 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6874 0 : Operands[*(p + 1)]->setConstraint("m");
6875 0 : NumMCOperands += 1;
6876 0 : break;
6877 0 : case CVT_95_addPSBHintOperands:
6878 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6879 0 : Operands[*(p + 1)]->setConstraint("m");
6880 0 : NumMCOperands += 1;
6881 0 : break;
6882 0 : case CVT_imm_95_4:
6883 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6884 0 : Operands[*(p + 1)]->setConstraint("");
6885 0 : ++NumMCOperands;
6886 0 : break;
6887 0 : case CVT_regLR:
6888 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6889 0 : Operands[*(p + 1)]->setConstraint("m");
6890 0 : ++NumMCOperands;
6891 0 : break;
6892 0 : case CVT_95_addUImm6Operands:
6893 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6894 0 : Operands[*(p + 1)]->setConstraint("m");
6895 0 : NumMCOperands += 1;
6896 0 : break;
6897 0 : case CVT_imm_95_5:
6898 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6899 0 : Operands[*(p + 1)]->setConstraint("");
6900 0 : ++NumMCOperands;
6901 0 : break;
6902 0 : case CVT_95_addGPR64as32Operands:
6903 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6904 0 : Operands[*(p + 1)]->setConstraint("m");
6905 0 : NumMCOperands += 1;
6906 0 : break;
6907 0 : case CVT_imm_95_7:
6908 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6909 0 : Operands[*(p + 1)]->setConstraint("");
6910 0 : ++NumMCOperands;
6911 0 : break;
6912 0 : case CVT_95_addSysCROperands:
6913 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6914 0 : Operands[*(p + 1)]->setConstraint("m");
6915 0 : NumMCOperands += 1;
6916 0 : break;
6917 0 : case CVT_95_addBranchTarget14Operands:
6918 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6919 0 : Operands[*(p + 1)]->setConstraint("m");
6920 0 : NumMCOperands += 1;
6921 0 : break;
6922 0 : case CVT_95_addGPR32as64Operands:
6923 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6924 0 : Operands[*(p + 1)]->setConstraint("m");
6925 0 : NumMCOperands += 1;
6926 0 : break;
6927 0 : case CVT_imm_95_2:
6928 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6929 0 : Operands[*(p + 1)]->setConstraint("");
6930 0 : ++NumMCOperands;
6931 0 : break;
6932 0 : case CVT_imm_95_3:
6933 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
6934 0 : Operands[*(p + 1)]->setConstraint("");
6935 0 : ++NumMCOperands;
6936 0 : break;
6937 : }
6938 : }
6939 0 : }
6940 :
6941 : namespace {
6942 :
6943 : /// MatchClassKind - The kinds of classes which participate in
6944 : /// instruction matching.
6945 : enum MatchClassKind {
6946 : InvalidMatchClass = 0,
6947 : OptionalMatchClass = 1,
6948 : MCK__DOT_16B, // '.16B'
6949 : MCK__DOT_1D, // '.1D'
6950 : MCK__DOT_1Q, // '.1Q'
6951 : MCK__DOT_2D, // '.2D'
6952 : MCK__DOT_2H, // '.2H'
6953 : MCK__DOT_2S, // '.2S'
6954 : MCK__DOT_4B, // '.4B'
6955 : MCK__DOT_4H, // '.4H'
6956 : MCK__DOT_4S, // '.4S'
6957 : MCK__DOT_8B, // '.8B'
6958 : MCK__DOT_8H, // '.8H'
6959 : MCK__DOT_B, // '.B'
6960 : MCK__DOT_D, // '.D'
6961 : MCK__DOT_H, // '.H'
6962 : MCK__DOT_Q, // '.Q'
6963 : MCK__DOT_S, // '.S'
6964 : MCK__EXCLAIM_, // '!'
6965 : MCK__35_0, // '#0'
6966 : MCK__35_1, // '#1'
6967 : MCK__35_12, // '#12'
6968 : MCK__35_16, // '#16'
6969 : MCK__35_2, // '#2'
6970 : MCK__35_24, // '#24'
6971 : MCK__35_3, // '#3'
6972 : MCK__35_32, // '#32'
6973 : MCK__35_4, // '#4'
6974 : MCK__35_48, // '#48'
6975 : MCK__35_6, // '#6'
6976 : MCK__35_64, // '#64'
6977 : MCK__35_8, // '#8'
6978 : MCK__DOT_, // '.'
6979 : MCK__DOT_0, // '.0'
6980 : MCK__DOT_16b, // '.16b'
6981 : MCK__DOT_1d, // '.1d'
6982 : MCK__DOT_1q, // '.1q'
6983 : MCK__DOT_2d, // '.2d'
6984 : MCK__DOT_2h, // '.2h'
6985 : MCK__DOT_2s, // '.2s'
6986 : MCK__DOT_4b, // '.4b'
6987 : MCK__DOT_4h, // '.4h'
6988 : MCK__DOT_4s, // '.4s'
6989 : MCK__DOT_8b, // '.8b'
6990 : MCK__DOT_8h, // '.8h'
6991 : MCK__DOT_b, // '.b'
6992 : MCK__DOT_d, // '.d'
6993 : MCK__DOT_h, // '.h'
6994 : MCK__DOT_q, // '.q'
6995 : MCK__DOT_s, // '.s'
6996 : MCK__47_, // '/'
6997 : MCK__91_, // '['
6998 : MCK__93_, // ']'
6999 : MCK_m, // 'm'
7000 : MCK_mul, // 'mul'
7001 : MCK_vl, // 'vl'
7002 : MCK_z, // 'z'
7003 : MCK_LAST_TOKEN = MCK_z,
7004 : MCK_Reg61, // derived register class
7005 : MCK_CCR, // register class 'CCR'
7006 : MCK_GPR32sponly, // register class 'GPR32sponly'
7007 : MCK_GPR64sponly, // register class 'GPR64sponly'
7008 : MCK_Reg60, // derived register class
7009 : MCK_Reg62, // derived register class
7010 : MCK_rtcGPR64, // register class 'rtcGPR64'
7011 : MCK_Reg70, // derived register class
7012 : MCK_Reg71, // derived register class
7013 : MCK_Reg90, // derived register class
7014 : MCK_Reg91, // derived register class
7015 : MCK_Reg63, // derived register class
7016 : MCK_Reg72, // derived register class
7017 : MCK_Reg87, // derived register class
7018 : MCK_Reg89, // derived register class
7019 : MCK_Reg92, // derived register class
7020 : MCK_Reg103, // derived register class
7021 : MCK_Reg64, // derived register class
7022 : MCK_Reg69, // derived register class
7023 : MCK_Reg73, // derived register class
7024 : MCK_Reg85, // derived register class
7025 : MCK_Reg86, // derived register class
7026 : MCK_Reg88, // derived register class
7027 : MCK_Reg93, // derived register class
7028 : MCK_Reg101, // derived register class
7029 : MCK_Reg102, // derived register class
7030 : MCK_PPR_3b, // register class 'PPR_3b'
7031 : MCK_ZPR_3b, // register class 'ZPR_3b'
7032 : MCK_Reg31, // derived register class
7033 : MCK_Reg74, // derived register class
7034 : MCK_Reg32, // derived register class
7035 : MCK_Reg41, // derived register class
7036 : MCK_Reg42, // derived register class
7037 : MCK_Reg75, // derived register class
7038 : MCK_Reg84, // derived register class
7039 : MCK_Reg94, // derived register class
7040 : MCK_Reg27, // derived register class
7041 : MCK_Reg33, // derived register class
7042 : MCK_Reg38, // derived register class
7043 : MCK_Reg40, // derived register class
7044 : MCK_Reg43, // derived register class
7045 : MCK_Reg48, // derived register class
7046 : MCK_Reg65, // derived register class
7047 : MCK_Reg76, // derived register class
7048 : MCK_Reg81, // derived register class
7049 : MCK_Reg83, // derived register class
7050 : MCK_Reg95, // derived register class
7051 : MCK_Reg100, // derived register class
7052 : MCK_Reg28, // derived register class
7053 : MCK_Reg30, // derived register class
7054 : MCK_Reg34, // derived register class
7055 : MCK_Reg36, // derived register class
7056 : MCK_Reg37, // derived register class
7057 : MCK_Reg39, // derived register class
7058 : MCK_Reg44, // derived register class
7059 : MCK_Reg46, // derived register class
7060 : MCK_Reg47, // derived register class
7061 : MCK_Reg66, // derived register class
7062 : MCK_Reg68, // derived register class
7063 : MCK_Reg77, // derived register class
7064 : MCK_Reg79, // derived register class
7065 : MCK_Reg80, // derived register class
7066 : MCK_Reg82, // derived register class
7067 : MCK_Reg96, // derived register class
7068 : MCK_Reg98, // derived register class
7069 : MCK_Reg99, // derived register class
7070 : MCK_FPR128_lo, // register class 'FPR128_lo'
7071 : MCK_PPR, // register class 'PPR'
7072 : MCK_ZPR_4b, // register class 'ZPR_4b'
7073 : MCK_Reg53, // derived register class
7074 : MCK_Reg54, // derived register class
7075 : MCK_Reg59, // derived register class
7076 : MCK_tcGPR64, // register class 'tcGPR64'
7077 : MCK_Reg49, // derived register class
7078 : MCK_Reg55, // derived register class
7079 : MCK_Reg50, // derived register class
7080 : MCK_Reg52, // derived register class
7081 : MCK_Reg56, // derived register class
7082 : MCK_Reg58, // derived register class
7083 : MCK_GPR32common, // register class 'GPR32common'
7084 : MCK_GPR64common, // register class 'GPR64common'
7085 : MCK_DD, // register class 'DD'
7086 : MCK_DDD, // register class 'DDD'
7087 : MCK_DDDD, // register class 'DDDD'
7088 : MCK_FPR128, // register class 'FPR128'
7089 : MCK_FPR16, // register class 'FPR16'
7090 : MCK_FPR32, // register class 'FPR32'
7091 : MCK_FPR64, // register class 'FPR64'
7092 : MCK_FPR8, // register class 'FPR8'
7093 : MCK_GPR32, // register class 'GPR32'
7094 : MCK_GPR32sp, // register class 'GPR32sp'
7095 : MCK_GPR64, // register class 'GPR64'
7096 : MCK_GPR64sp, // register class 'GPR64sp'
7097 : MCK_QQ, // register class 'QQ'
7098 : MCK_QQQ, // register class 'QQQ'
7099 : MCK_QQQQ, // register class 'QQQQ'
7100 : MCK_WSeqPairsClass, // register class 'WSeqPairsClass'
7101 : MCK_XSeqPairsClass, // register class 'XSeqPairsClass'
7102 : MCK_ZPR, // register class 'ZPR'
7103 : MCK_ZPR2, // register class 'ZPR2'
7104 : MCK_ZPR3, // register class 'ZPR3'
7105 : MCK_ZPR4, // register class 'ZPR4'
7106 : MCK_GPR32all, // register class 'GPR32all'
7107 : MCK_GPR64all, // register class 'GPR64all'
7108 : MCK_LAST_REGISTER = MCK_GPR64all,
7109 : MCK_AddSubImmNeg, // user defined class 'AddSubImmNegOperand'
7110 : MCK_AddSubImm, // user defined class 'AddSubImmOperand'
7111 : MCK_AdrLabel, // user defined class 'AdrOperand'
7112 : MCK_AdrpLabel, // user defined class 'AdrpOperand'
7113 : MCK_BTIHint, // user defined class 'BTIHintOperand'
7114 : MCK_Barrier, // user defined class 'BarrierAsmOperand'
7115 : MCK_BranchTarget14, // user defined class 'BranchTarget14Operand'
7116 : MCK_BranchTarget26, // user defined class 'BranchTarget26Operand'
7117 : MCK_CondCode, // user defined class 'CondCode'
7118 : MCK_Extend64, // user defined class 'ExtendOperand64'
7119 : MCK_ExtendLSL64, // user defined class 'ExtendOperandLSL64'
7120 : MCK_Extend, // user defined class 'ExtendOperand'
7121 : MCK_FPImm, // user defined class 'FPImmOperand'
7122 : MCK_GPR32as64, // user defined class 'GPR32as64Operand'
7123 : MCK_GPR64NoXZRshifted16, // user defined class 'GPR64NoXZRshiftedAsmOpnd16'
7124 : MCK_GPR64NoXZRshifted32, // user defined class 'GPR64NoXZRshiftedAsmOpnd32'
7125 : MCK_GPR64NoXZRshifted64, // user defined class 'GPR64NoXZRshiftedAsmOpnd64'
7126 : MCK_GPR64NoXZRshifted8, // user defined class 'GPR64NoXZRshiftedAsmOpnd8'
7127 : MCK_GPR64as32, // user defined class 'GPR64as32Operand'
7128 : MCK_GPR64shifted16, // user defined class 'GPR64shiftedAsmOpnd16'
7129 : MCK_GPR64shifted32, // user defined class 'GPR64shiftedAsmOpnd32'
7130 : MCK_GPR64shifted64, // user defined class 'GPR64shiftedAsmOpnd64'
7131 : MCK_GPR64shifted8, // user defined class 'GPR64shiftedAsmOpnd8'
7132 : MCK_GPR64sp0, // user defined class 'GPR64spPlus0Operand'
7133 : MCK_Imm0_127, // user defined class 'Imm0_127Operand'
7134 : MCK_Imm0_15, // user defined class 'Imm0_15Operand'
7135 : MCK_Imm0_1, // user defined class 'Imm0_1Operand'
7136 : MCK_Imm0_255, // user defined class 'Imm0_255Operand'
7137 : MCK_Imm0_31, // user defined class 'Imm0_31Operand'
7138 : MCK_Imm0_63, // user defined class 'Imm0_63Operand'
7139 : MCK_Imm0_65535, // user defined class 'Imm0_65535Operand'
7140 : MCK_Imm0_7, // user defined class 'Imm0_7Operand'
7141 : MCK_Imm1_16, // user defined class 'Imm1_16Operand'
7142 : MCK_Imm1_32, // user defined class 'Imm1_32Operand'
7143 : MCK_Imm1_64, // user defined class 'Imm1_64Operand'
7144 : MCK_Imm1_8, // user defined class 'Imm1_8Operand'
7145 : MCK_Imm, // user defined class 'ImmAsmOperand'
7146 : MCK_LogicalImm32Not, // user defined class 'LogicalImm32NotOperand'
7147 : MCK_LogicalImm32, // user defined class 'LogicalImm32Operand'
7148 : MCK_LogicalImm64Not, // user defined class 'LogicalImm64NotOperand'
7149 : MCK_LogicalImm64, // user defined class 'LogicalImm64Operand'
7150 : MCK_MRSSystemRegister, // user defined class 'MRSSystemRegisterOperand'
7151 : MCK_MSRSystemRegister, // user defined class 'MSRSystemRegisterOperand'
7152 : MCK_MemWExtend128, // user defined class 'MemWExtend128Operand'
7153 : MCK_MemWExtend16, // user defined class 'MemWExtend16Operand'
7154 : MCK_MemWExtend32, // user defined class 'MemWExtend32Operand'
7155 : MCK_MemWExtend64, // user defined class 'MemWExtend64Operand'
7156 : MCK_MemWExtend8, // user defined class 'MemWExtend8Operand'
7157 : MCK_MemXExtend128, // user defined class 'MemXExtend128Operand'
7158 : MCK_MemXExtend16, // user defined class 'MemXExtend16Operand'
7159 : MCK_MemXExtend32, // user defined class 'MemXExtend32Operand'
7160 : MCK_MemXExtend64, // user defined class 'MemXExtend64Operand'
7161 : MCK_MemXExtend8, // user defined class 'MemXExtend8Operand'
7162 : MCK_MovKSymbolG0, // user defined class 'MovKSymbolG0AsmOperand'
7163 : MCK_MovKSymbolG1, // user defined class 'MovKSymbolG1AsmOperand'
7164 : MCK_MovKSymbolG2, // user defined class 'MovKSymbolG2AsmOperand'
7165 : MCK_MovKSymbolG3, // user defined class 'MovKSymbolG3AsmOperand'
7166 : MCK_MovZSymbolG0, // user defined class 'MovZSymbolG0AsmOperand'
7167 : MCK_MovZSymbolG1, // user defined class 'MovZSymbolG1AsmOperand'
7168 : MCK_MovZSymbolG2, // user defined class 'MovZSymbolG2AsmOperand'
7169 : MCK_MovZSymbolG3, // user defined class 'MovZSymbolG3AsmOperand'
7170 : MCK_PCRelLabel19, // user defined class 'PCRelLabel19Operand'
7171 : MCK_SVEPredicateHReg, // user defined class 'PPRAsmOp16'
7172 : MCK_SVEPredicateSReg, // user defined class 'PPRAsmOp32'
7173 : MCK_SVEPredicate3bHReg, // user defined class 'PPRAsmOp3b16'
7174 : MCK_SVEPredicate3bSReg, // user defined class 'PPRAsmOp3b32'
7175 : MCK_SVEPredicate3bDReg, // user defined class 'PPRAsmOp3b64'
7176 : MCK_SVEPredicate3bBReg, // user defined class 'PPRAsmOp3b8'
7177 : MCK_SVEPredicate3bAnyReg, // user defined class 'PPRAsmOp3bAny'
7178 : MCK_SVEPredicateDReg, // user defined class 'PPRAsmOp64'
7179 : MCK_SVEPredicateBReg, // user defined class 'PPRAsmOp8'
7180 : MCK_SVEPredicateAnyReg, // user defined class 'PPRAsmOpAny'
7181 : MCK_PSBHint, // user defined class 'PSBHintOperand'
7182 : MCK_Prefetch, // user defined class 'PrefetchOperand'
7183 : MCK_SIMDImmType10, // user defined class 'SIMDImmType10Operand'
7184 : MCK_SImm10s8, // user defined class 'SImm10s8Operand'
7185 : MCK_SImm4s16, // user defined class 'SImm4s16Operand'
7186 : MCK_SImm4s1, // user defined class 'SImm4s1Operand'
7187 : MCK_SImm4s2, // user defined class 'SImm4s2Operand'
7188 : MCK_SImm4s3, // user defined class 'SImm4s3Operand'
7189 : MCK_SImm4s4, // user defined class 'SImm4s4Operand'
7190 : MCK_SImm5, // user defined class 'SImm5Operand'
7191 : MCK_SImm6, // user defined class 'SImm6Operand'
7192 : MCK_SImm6s1, // user defined class 'SImm6s1Operand'
7193 : MCK_SImm7s16, // user defined class 'SImm7s16Operand'
7194 : MCK_SImm7s4, // user defined class 'SImm7s4Operand'
7195 : MCK_SImm7s8, // user defined class 'SImm7s8Operand'
7196 : MCK_SImm8, // user defined class 'SImm8Operand'
7197 : MCK_SImm9OffsetFB128, // user defined class 'SImm9OffsetFB128Operand'
7198 : MCK_SImm9OffsetFB16, // user defined class 'SImm9OffsetFB16Operand'
7199 : MCK_SImm9OffsetFB32, // user defined class 'SImm9OffsetFB32Operand'
7200 : MCK_SImm9OffsetFB64, // user defined class 'SImm9OffsetFB64Operand'
7201 : MCK_SImm9OffsetFB8, // user defined class 'SImm9OffsetFB8Operand'
7202 : MCK_SImm9, // user defined class 'SImm9Operand'
7203 : MCK_SVEAddSubImm16, // user defined class 'SVEAddSubImmOperand16'
7204 : MCK_SVEAddSubImm32, // user defined class 'SVEAddSubImmOperand32'
7205 : MCK_SVEAddSubImm64, // user defined class 'SVEAddSubImmOperand64'
7206 : MCK_SVEAddSubImm8, // user defined class 'SVEAddSubImmOperand8'
7207 : MCK_SVECpyImm16, // user defined class 'SVECpyImmOperand16'
7208 : MCK_SVECpyImm32, // user defined class 'SVECpyImmOperand32'
7209 : MCK_SVECpyImm64, // user defined class 'SVECpyImmOperand64'
7210 : MCK_SVECpyImm8, // user defined class 'SVECpyImmOperand8'
7211 : MCK_SVEPattern, // user defined class 'SVEPatternOperand'
7212 : MCK_SVEPrefetch, // user defined class 'SVEPrefetchOperand'
7213 : MCK_SVEIndexRange0_63, // user defined class 'SVEVectorIndexExtDupBOperand'
7214 : MCK_SVEIndexRange0_7, // user defined class 'SVEVectorIndexExtDupDOperand'
7215 : MCK_SVEIndexRange0_31, // user defined class 'SVEVectorIndexExtDupHOperand'
7216 : MCK_SVEIndexRange0_3, // user defined class 'SVEVectorIndexExtDupQOperand'
7217 : MCK_SVEIndexRange0_15, // user defined class 'SVEVectorIndexExtDupSOperand'
7218 : MCK_LogicalVecHalfWordShifter, // user defined class 'LogicalVecHalfWordShifterOperand'
7219 : MCK_ArithmeticShifter32, // user defined class 'ArithmeticShifterOperand32'
7220 : MCK_ArithmeticShifter64, // user defined class 'ArithmeticShifterOperand64'
7221 : MCK_LogicalShifter32, // user defined class 'LogicalShifterOperand32'
7222 : MCK_LogicalShifter64, // user defined class 'LogicalShifterOperand64'
7223 : MCK_LogicalVecShifter, // user defined class 'LogicalVecShifterOperand'
7224 : MCK_MovImm32Shifter, // user defined class 'MovImm32ShifterOperand'
7225 : MCK_MovImm64Shifter, // user defined class 'MovImm64ShifterOperand'
7226 : MCK_MoveVecShifter, // user defined class 'MoveVecShifterOperand'
7227 : MCK_Shifter, // user defined class 'ShifterOperand'
7228 : MCK_SysCR, // user defined class 'SysCRAsmOperand'
7229 : MCK_SystemPStateFieldWithImm0_15, // user defined class 'SystemPStateFieldWithImm0_15Operand'
7230 : MCK_SystemPStateFieldWithImm0_1, // user defined class 'SystemPStateFieldWithImm0_1Operand'
7231 : MCK_TBZImm0_31, // user defined class 'TBZImm0_31Operand'
7232 : MCK_Imm32_63, // user defined class 'TBZImm32_63Operand'
7233 : MCK_UImm12Offset16, // user defined class 'UImm12OffsetScale16Operand'
7234 : MCK_UImm12Offset1, // user defined class 'UImm12OffsetScale1Operand'
7235 : MCK_UImm12Offset2, // user defined class 'UImm12OffsetScale2Operand'
7236 : MCK_UImm12Offset4, // user defined class 'UImm12OffsetScale4Operand'
7237 : MCK_UImm12Offset8, // user defined class 'UImm12OffsetScale8Operand'
7238 : MCK_UImm5s2, // user defined class 'UImm5s2Operand'
7239 : MCK_UImm5s4, // user defined class 'UImm5s4Operand'
7240 : MCK_UImm5s8, // user defined class 'UImm5s8Operand'
7241 : MCK_UImm6, // user defined class 'UImm6Operand'
7242 : MCK_UImm6s16, // user defined class 'UImm6s16Operand'
7243 : MCK_UImm6s1, // user defined class 'UImm6s1Operand'
7244 : MCK_UImm6s2, // user defined class 'UImm6s2Operand'
7245 : MCK_UImm6s4, // user defined class 'UImm6s4Operand'
7246 : MCK_UImm6s8, // user defined class 'UImm6s8Operand'
7247 : MCK_VecListFour128, // user defined class 'VecListFour_128AsmOperand'
7248 : MCK_TypedVectorList4_168, // user defined class 'VecListFour_16bAsmOperand'
7249 : MCK_TypedVectorList4_164, // user defined class 'VecListFour_1dAsmOperand'
7250 : MCK_TypedVectorList4_264, // user defined class 'VecListFour_2dAsmOperand'
7251 : MCK_TypedVectorList4_232, // user defined class 'VecListFour_2sAsmOperand'
7252 : MCK_TypedVectorList4_416, // user defined class 'VecListFour_4hAsmOperand'
7253 : MCK_TypedVectorList4_432, // user defined class 'VecListFour_4sAsmOperand'
7254 : MCK_VecListFour64, // user defined class 'VecListFour_64AsmOperand'
7255 : MCK_TypedVectorList4_88, // user defined class 'VecListFour_8bAsmOperand'
7256 : MCK_TypedVectorList4_816, // user defined class 'VecListFour_8hAsmOperand'
7257 : MCK_TypedVectorList4_08, // user defined class 'VecListFour_bAsmOperand'
7258 : MCK_TypedVectorList4_064, // user defined class 'VecListFour_dAsmOperand'
7259 : MCK_TypedVectorList4_016, // user defined class 'VecListFour_hAsmOperand'
7260 : MCK_TypedVectorList4_032, // user defined class 'VecListFour_sAsmOperand'
7261 : MCK_VecListOne128, // user defined class 'VecListOne_128AsmOperand'
7262 : MCK_TypedVectorList1_168, // user defined class 'VecListOne_16bAsmOperand'
7263 : MCK_TypedVectorList1_164, // user defined class 'VecListOne_1dAsmOperand'
7264 : MCK_TypedVectorList1_264, // user defined class 'VecListOne_2dAsmOperand'
7265 : MCK_TypedVectorList1_232, // user defined class 'VecListOne_2sAsmOperand'
7266 : MCK_TypedVectorList1_416, // user defined class 'VecListOne_4hAsmOperand'
7267 : MCK_TypedVectorList1_432, // user defined class 'VecListOne_4sAsmOperand'
7268 : MCK_VecListOne64, // user defined class 'VecListOne_64AsmOperand'
7269 : MCK_TypedVectorList1_88, // user defined class 'VecListOne_8bAsmOperand'
7270 : MCK_TypedVectorList1_816, // user defined class 'VecListOne_8hAsmOperand'
7271 : MCK_TypedVectorList1_08, // user defined class 'VecListOne_bAsmOperand'
7272 : MCK_TypedVectorList1_064, // user defined class 'VecListOne_dAsmOperand'
7273 : MCK_TypedVectorList1_016, // user defined class 'VecListOne_hAsmOperand'
7274 : MCK_TypedVectorList1_032, // user defined class 'VecListOne_sAsmOperand'
7275 : MCK_VecListThree128, // user defined class 'VecListThree_128AsmOperand'
7276 : MCK_TypedVectorList3_168, // user defined class 'VecListThree_16bAsmOperand'
7277 : MCK_TypedVectorList3_164, // user defined class 'VecListThree_1dAsmOperand'
7278 : MCK_TypedVectorList3_264, // user defined class 'VecListThree_2dAsmOperand'
7279 : MCK_TypedVectorList3_232, // user defined class 'VecListThree_2sAsmOperand'
7280 : MCK_TypedVectorList3_416, // user defined class 'VecListThree_4hAsmOperand'
7281 : MCK_TypedVectorList3_432, // user defined class 'VecListThree_4sAsmOperand'
7282 : MCK_VecListThree64, // user defined class 'VecListThree_64AsmOperand'
7283 : MCK_TypedVectorList3_88, // user defined class 'VecListThree_8bAsmOperand'
7284 : MCK_TypedVectorList3_816, // user defined class 'VecListThree_8hAsmOperand'
7285 : MCK_TypedVectorList3_08, // user defined class 'VecListThree_bAsmOperand'
7286 : MCK_TypedVectorList3_064, // user defined class 'VecListThree_dAsmOperand'
7287 : MCK_TypedVectorList3_016, // user defined class 'VecListThree_hAsmOperand'
7288 : MCK_TypedVectorList3_032, // user defined class 'VecListThree_sAsmOperand'
7289 : MCK_VecListTwo128, // user defined class 'VecListTwo_128AsmOperand'
7290 : MCK_TypedVectorList2_168, // user defined class 'VecListTwo_16bAsmOperand'
7291 : MCK_TypedVectorList2_164, // user defined class 'VecListTwo_1dAsmOperand'
7292 : MCK_TypedVectorList2_264, // user defined class 'VecListTwo_2dAsmOperand'
7293 : MCK_TypedVectorList2_232, // user defined class 'VecListTwo_2sAsmOperand'
7294 : MCK_TypedVectorList2_416, // user defined class 'VecListTwo_4hAsmOperand'
7295 : MCK_TypedVectorList2_432, // user defined class 'VecListTwo_4sAsmOperand'
7296 : MCK_VecListTwo64, // user defined class 'VecListTwo_64AsmOperand'
7297 : MCK_TypedVectorList2_88, // user defined class 'VecListTwo_8bAsmOperand'
7298 : MCK_TypedVectorList2_816, // user defined class 'VecListTwo_8hAsmOperand'
7299 : MCK_TypedVectorList2_08, // user defined class 'VecListTwo_bAsmOperand'
7300 : MCK_TypedVectorList2_064, // user defined class 'VecListTwo_dAsmOperand'
7301 : MCK_TypedVectorList2_016, // user defined class 'VecListTwo_hAsmOperand'
7302 : MCK_TypedVectorList2_032, // user defined class 'VecListTwo_sAsmOperand'
7303 : MCK_IndexRange1_1, // user defined class 'VectorIndex1Operand'
7304 : MCK_IndexRange0_15, // user defined class 'VectorIndexBOperand'
7305 : MCK_IndexRange0_1, // user defined class 'VectorIndexDOperand'
7306 : MCK_IndexRange0_7, // user defined class 'VectorIndexHOperand'
7307 : MCK_IndexRange0_3, // user defined class 'VectorIndexSOperand'
7308 : MCK_VectorReg128, // user defined class 'VectorReg128AsmOperand'
7309 : MCK_VectorReg64, // user defined class 'VectorReg64AsmOperand'
7310 : MCK_VectorRegLo, // user defined class 'VectorRegLoAsmOperand'
7311 : MCK_WSeqPair, // user defined class 'WSeqPairsAsmOperandClass'
7312 : MCK_XSeqPair, // user defined class 'XSeqPairsAsmOperandClass'
7313 : MCK_ZPRExtendLSL3216, // user defined class 'ZPR32AsmOpndExtLSL16'
7314 : MCK_ZPRExtendLSL3232, // user defined class 'ZPR32AsmOpndExtLSL32'
7315 : MCK_ZPRExtendLSL3264, // user defined class 'ZPR32AsmOpndExtLSL64'
7316 : MCK_ZPRExtendLSL328, // user defined class 'ZPR32AsmOpndExtLSL8'
7317 : MCK_ZPRExtendSXTW3216, // user defined class 'ZPR32AsmOpndExtSXTW16'
7318 : MCK_ZPRExtendSXTW3232, // user defined class 'ZPR32AsmOpndExtSXTW32'
7319 : MCK_ZPRExtendSXTW3264, // user defined class 'ZPR32AsmOpndExtSXTW64'
7320 : MCK_ZPRExtendSXTW328, // user defined class 'ZPR32AsmOpndExtSXTW8'
7321 : MCK_ZPRExtendSXTW328Only, // user defined class 'ZPR32AsmOpndExtSXTW8Only'
7322 : MCK_ZPRExtendUXTW3216, // user defined class 'ZPR32AsmOpndExtUXTW16'
7323 : MCK_ZPRExtendUXTW3232, // user defined class 'ZPR32AsmOpndExtUXTW32'
7324 : MCK_ZPRExtendUXTW3264, // user defined class 'ZPR32AsmOpndExtUXTW64'
7325 : MCK_ZPRExtendUXTW328, // user defined class 'ZPR32AsmOpndExtUXTW8'
7326 : MCK_ZPRExtendUXTW328Only, // user defined class 'ZPR32AsmOpndExtUXTW8Only'
7327 : MCK_ZPRExtendLSL6416, // user defined class 'ZPR64AsmOpndExtLSL16'
7328 : MCK_ZPRExtendLSL6432, // user defined class 'ZPR64AsmOpndExtLSL32'
7329 : MCK_ZPRExtendLSL6464, // user defined class 'ZPR64AsmOpndExtLSL64'
7330 : MCK_ZPRExtendLSL648, // user defined class 'ZPR64AsmOpndExtLSL8'
7331 : MCK_ZPRExtendSXTW6416, // user defined class 'ZPR64AsmOpndExtSXTW16'
7332 : MCK_ZPRExtendSXTW6432, // user defined class 'ZPR64AsmOpndExtSXTW32'
7333 : MCK_ZPRExtendSXTW6464, // user defined class 'ZPR64AsmOpndExtSXTW64'
7334 : MCK_ZPRExtendSXTW648, // user defined class 'ZPR64AsmOpndExtSXTW8'
7335 : MCK_ZPRExtendSXTW648Only, // user defined class 'ZPR64AsmOpndExtSXTW8Only'
7336 : MCK_ZPRExtendUXTW6416, // user defined class 'ZPR64AsmOpndExtUXTW16'
7337 : MCK_ZPRExtendUXTW6432, // user defined class 'ZPR64AsmOpndExtUXTW32'
7338 : MCK_ZPRExtendUXTW6464, // user defined class 'ZPR64AsmOpndExtUXTW64'
7339 : MCK_ZPRExtendUXTW648, // user defined class 'ZPR64AsmOpndExtUXTW8'
7340 : MCK_ZPRExtendUXTW648Only, // user defined class 'ZPR64AsmOpndExtUXTW8Only'
7341 : MCK_SVEVectorQReg, // user defined class 'ZPRAsmOp128'
7342 : MCK_SVEVectorHReg, // user defined class 'ZPRAsmOp16'
7343 : MCK_SVEVectorSReg, // user defined class 'ZPRAsmOp32'
7344 : MCK_SVEVector3bHReg, // user defined class 'ZPRAsmOp3b16'
7345 : MCK_SVEVector3bSReg, // user defined class 'ZPRAsmOp3b32'
7346 : MCK_SVEVector3bBReg, // user defined class 'ZPRAsmOp3b8'
7347 : MCK_SVEVector4bHReg, // user defined class 'ZPRAsmOp4b16'
7348 : MCK_SVEVector4bSReg, // user defined class 'ZPRAsmOp4b32'
7349 : MCK_SVEVector4bDReg, // user defined class 'ZPRAsmOp4b64'
7350 : MCK_SVEVectorDReg, // user defined class 'ZPRAsmOp64'
7351 : MCK_SVEVectorBReg, // user defined class 'ZPRAsmOp8'
7352 : MCK_SVEVectorAnyReg, // user defined class 'ZPRAsmOpAny'
7353 : MCK_SImm9s16, // user defined class 'anonymous_1074'
7354 : MCK_ComplexRotationEven, // user defined class 'anonymous_1284'
7355 : MCK_ComplexRotationOdd, // user defined class 'anonymous_1285'
7356 : MCK_SVELogicalImm8, // user defined class 'anonymous_1335'
7357 : MCK_SVELogicalImm16, // user defined class 'anonymous_1336'
7358 : MCK_SVELogicalImm32, // user defined class 'anonymous_1337'
7359 : MCK_SVEPreferredLogicalImm16, // user defined class 'anonymous_1338'
7360 : MCK_SVEPreferredLogicalImm32, // user defined class 'anonymous_1339'
7361 : MCK_SVEPreferredLogicalImm64, // user defined class 'anonymous_1340'
7362 : MCK_SVELogicalImm8Not, // user defined class 'anonymous_1341'
7363 : MCK_SVELogicalImm16Not, // user defined class 'anonymous_1342'
7364 : MCK_SVELogicalImm32Not, // user defined class 'anonymous_1343'
7365 : MCK_SVEExactFPImmOperandHalfOne, // user defined class 'anonymous_1344'
7366 : MCK_SVEExactFPImmOperandHalfTwo, // user defined class 'anonymous_1345'
7367 : MCK_SVEExactFPImmOperandZeroOne, // user defined class 'anonymous_1346'
7368 : MCK_MOVZ32_lsl0MovAlias, // user defined class 'anonymous_1542_asmoperand'
7369 : MCK_MOVZ32_lsl16MovAlias, // user defined class 'anonymous_1543_asmoperand'
7370 : MCK_MOVZ64_lsl0MovAlias, // user defined class 'anonymous_1545_asmoperand'
7371 : MCK_MOVZ64_lsl16MovAlias, // user defined class 'anonymous_1547_asmoperand'
7372 : MCK_MOVZ64_lsl32MovAlias, // user defined class 'anonymous_1549_asmoperand'
7373 : MCK_MOVZ64_lsl48MovAlias, // user defined class 'anonymous_1551_asmoperand'
7374 : MCK_MOVN32_lsl0MovAlias, // user defined class 'anonymous_1553_asmoperand'
7375 : MCK_MOVN32_lsl16MovAlias, // user defined class 'anonymous_1555_asmoperand'
7376 : MCK_MOVN64_lsl0MovAlias, // user defined class 'anonymous_1557_asmoperand'
7377 : MCK_MOVN64_lsl16MovAlias, // user defined class 'anonymous_1559_asmoperand'
7378 : MCK_MOVN64_lsl32MovAlias, // user defined class 'anonymous_1561_asmoperand'
7379 : MCK_MOVN64_lsl48MovAlias, // user defined class 'anonymous_1563_asmoperand'
7380 : MCK_FPRAsmOperandFPR8, // user defined class 'anonymous_942'
7381 : MCK_FPRAsmOperandFPR16, // user defined class 'anonymous_943'
7382 : MCK_FPRAsmOperandFPR32, // user defined class 'anonymous_944'
7383 : MCK_FPRAsmOperandFPR64, // user defined class 'anonymous_945'
7384 : MCK_FPRAsmOperandFPR128, // user defined class 'anonymous_946'
7385 : MCK_FPR8asZPR, // user defined class 'anonymous_947'
7386 : MCK_FPR16asZPR, // user defined class 'anonymous_948'
7387 : MCK_FPR32asZPR, // user defined class 'anonymous_949'
7388 : MCK_FPR64asZPR, // user defined class 'anonymous_950'
7389 : MCK_FPR128asZPR, // user defined class 'anonymous_951'
7390 : MCK_SVEVectorList18, // user defined class 'anonymous_952'
7391 : MCK_SVEVectorList116, // user defined class 'anonymous_953'
7392 : MCK_SVEVectorList132, // user defined class 'anonymous_954'
7393 : MCK_SVEVectorList164, // user defined class 'anonymous_955'
7394 : MCK_SVEVectorList28, // user defined class 'anonymous_956'
7395 : MCK_SVEVectorList216, // user defined class 'anonymous_957'
7396 : MCK_SVEVectorList232, // user defined class 'anonymous_958'
7397 : MCK_SVEVectorList264, // user defined class 'anonymous_959'
7398 : MCK_SVEVectorList38, // user defined class 'anonymous_960'
7399 : MCK_SVEVectorList316, // user defined class 'anonymous_961'
7400 : MCK_SVEVectorList332, // user defined class 'anonymous_962'
7401 : MCK_SVEVectorList364, // user defined class 'anonymous_963'
7402 : MCK_SVEVectorList48, // user defined class 'anonymous_964'
7403 : MCK_SVEVectorList416, // user defined class 'anonymous_965'
7404 : MCK_SVEVectorList432, // user defined class 'anonymous_966'
7405 : MCK_SVEVectorList464, // user defined class 'anonymous_967'
7406 : NumMatchClassKinds
7407 : };
7408 :
7409 : }
7410 :
7411 0 : static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
7412 0 : return MCTargetAsmParser::Match_InvalidOperand;
7413 : }
7414 :
7415 171074 : static MatchClassKind matchTokenString(StringRef Name) {
7416 171074 : switch (Name.size()) {
7417 : default: break;
7418 122979 : case 1: // 7 strings to match.
7419 : switch (Name[0]) {
7420 : default: break;
7421 : case '!': // 1 string to match.
7422 : return MCK__EXCLAIM_; // "!"
7423 115 : case '.': // 1 string to match.
7424 115 : return MCK__DOT_; // "."
7425 32289 : case '/': // 1 string to match.
7426 32289 : return MCK__47_; // "/"
7427 46509 : case '[': // 1 string to match.
7428 46509 : return MCK__91_; // "["
7429 11539 : case ']': // 1 string to match.
7430 11539 : return MCK__93_; // "]"
7431 9333 : case 'm': // 1 string to match.
7432 9333 : return MCK_m; // "m"
7433 22938 : case 'z': // 1 string to match.
7434 22938 : return MCK_z; // "z"
7435 : }
7436 : break;
7437 7774 : case 2: // 19 strings to match.
7438 : switch (Name[0]) {
7439 : default: break;
7440 351 : case '#': // 7 strings to match.
7441 : switch (Name[1]) {
7442 : default: break;
7443 : case '0': // 1 string to match.
7444 : return MCK__35_0; // "#0"
7445 : case '1': // 1 string to match.
7446 : return MCK__35_1; // "#1"
7447 : case '2': // 1 string to match.
7448 : return MCK__35_2; // "#2"
7449 : case '3': // 1 string to match.
7450 : return MCK__35_3; // "#3"
7451 : case '4': // 1 string to match.
7452 : return MCK__35_4; // "#4"
7453 : case '6': // 1 string to match.
7454 : return MCK__35_6; // "#6"
7455 : case '8': // 1 string to match.
7456 : return MCK__35_8; // "#8"
7457 : }
7458 : break;
7459 6541 : case '.': // 11 strings to match.
7460 : switch (Name[1]) {
7461 : default: break;
7462 : case '0': // 1 string to match.
7463 : return MCK__DOT_0; // ".0"
7464 : case 'B': // 1 string to match.
7465 : return MCK__DOT_B; // ".B"
7466 : case 'D': // 1 string to match.
7467 : return MCK__DOT_D; // ".D"
7468 : case 'H': // 1 string to match.
7469 : return MCK__DOT_H; // ".H"
7470 : case 'Q': // 1 string to match.
7471 : return MCK__DOT_Q; // ".Q"
7472 : case 'S': // 1 string to match.
7473 : return MCK__DOT_S; // ".S"
7474 : case 'b': // 1 string to match.
7475 : return MCK__DOT_b; // ".b"
7476 : case 'd': // 1 string to match.
7477 : return MCK__DOT_d; // ".d"
7478 : case 'h': // 1 string to match.
7479 : return MCK__DOT_h; // ".h"
7480 : case 'q': // 1 string to match.
7481 : return MCK__DOT_q; // ".q"
7482 : case 's': // 1 string to match.
7483 : return MCK__DOT_s; // ".s"
7484 : }
7485 : break;
7486 882 : case 'v': // 1 string to match.
7487 882 : if (Name[1] != 'l')
7488 : break;
7489 : return MCK_vl; // "vl"
7490 : }
7491 : break;
7492 38092 : case 3: // 27 strings to match.
7493 : switch (Name[0]) {
7494 : default: break;
7495 0 : case '#': // 6 strings to match.
7496 : switch (Name[1]) {
7497 : default: break;
7498 0 : case '1': // 2 strings to match.
7499 : switch (Name[2]) {
7500 : default: break;
7501 : case '2': // 1 string to match.
7502 : return MCK__35_12; // "#12"
7503 0 : case '6': // 1 string to match.
7504 0 : return MCK__35_16; // "#16"
7505 : }
7506 : break;
7507 0 : case '2': // 1 string to match.
7508 0 : if (Name[2] != '4')
7509 : break;
7510 : return MCK__35_24; // "#24"
7511 0 : case '3': // 1 string to match.
7512 0 : if (Name[2] != '2')
7513 : break;
7514 : return MCK__35_32; // "#32"
7515 0 : case '4': // 1 string to match.
7516 0 : if (Name[2] != '8')
7517 : break;
7518 : return MCK__35_48; // "#48"
7519 0 : case '6': // 1 string to match.
7520 0 : if (Name[2] != '4')
7521 : break;
7522 : return MCK__35_64; // "#64"
7523 : }
7524 : break;
7525 36214 : case '.': // 20 strings to match.
7526 : switch (Name[1]) {
7527 : default: break;
7528 1021 : case '1': // 4 strings to match.
7529 : switch (Name[2]) {
7530 : default: break;
7531 : case 'D': // 1 string to match.
7532 : return MCK__DOT_1D; // ".1D"
7533 2 : case 'Q': // 1 string to match.
7534 2 : return MCK__DOT_1Q; // ".1Q"
7535 1003 : case 'd': // 1 string to match.
7536 1003 : return MCK__DOT_1d; // ".1d"
7537 14 : case 'q': // 1 string to match.
7538 14 : return MCK__DOT_1q; // ".1q"
7539 : }
7540 : break;
7541 9624 : case '2': // 6 strings to match.
7542 : switch (Name[2]) {
7543 : default: break;
7544 : case 'D': // 1 string to match.
7545 : return MCK__DOT_2D; // ".2D"
7546 : case 'H': // 1 string to match.
7547 : return MCK__DOT_2H; // ".2H"
7548 : case 'S': // 1 string to match.
7549 : return MCK__DOT_2S; // ".2S"
7550 : case 'd': // 1 string to match.
7551 : return MCK__DOT_2d; // ".2d"
7552 : case 'h': // 1 string to match.
7553 : return MCK__DOT_2h; // ".2h"
7554 : case 's': // 1 string to match.
7555 : return MCK__DOT_2s; // ".2s"
7556 : }
7557 : break;
7558 13105 : case '4': // 6 strings to match.
7559 : switch (Name[2]) {
7560 : default: break;
7561 : case 'B': // 1 string to match.
7562 : return MCK__DOT_4B; // ".4B"
7563 96 : case 'H': // 1 string to match.
7564 96 : return MCK__DOT_4H; // ".4H"
7565 109 : case 'S': // 1 string to match.
7566 109 : return MCK__DOT_4S; // ".4S"
7567 52 : case 'b': // 1 string to match.
7568 52 : return MCK__DOT_4b; // ".4b"
7569 6599 : case 'h': // 1 string to match.
7570 6599 : return MCK__DOT_4h; // ".4h"
7571 6233 : case 's': // 1 string to match.
7572 6233 : return MCK__DOT_4s; // ".4s"
7573 : }
7574 : break;
7575 12248 : case '8': // 4 strings to match.
7576 : switch (Name[2]) {
7577 : default: break;
7578 : case 'B': // 1 string to match.
7579 : return MCK__DOT_8B; // ".8B"
7580 4 : case 'H': // 1 string to match.
7581 4 : return MCK__DOT_8H; // ".8H"
7582 4931 : case 'b': // 1 string to match.
7583 4931 : return MCK__DOT_8b; // ".8b"
7584 7292 : case 'h': // 1 string to match.
7585 7292 : return MCK__DOT_8h; // ".8h"
7586 : }
7587 : break;
7588 : }
7589 : break;
7590 : case 'm': // 1 string to match.
7591 1878 : if (memcmp(Name.data()+1, "ul", 2) != 0)
7592 : break;
7593 : return MCK_mul; // "mul"
7594 : }
7595 : break;
7596 : case 4: // 2 strings to match.
7597 2229 : if (memcmp(Name.data()+0, ".16", 3) != 0)
7598 : break;
7599 : switch (Name[3]) {
7600 : default: break;
7601 : case 'B': // 1 string to match.
7602 : return MCK__DOT_16B; // ".16B"
7603 2214 : case 'b': // 1 string to match.
7604 2214 : return MCK__DOT_16b; // ".16b"
7605 : }
7606 : break;
7607 : }
7608 : return InvalidMatchClass;
7609 : }
7610 :
7611 : /// isSubclass - Compute whether \p A is a subclass of \p B.
7612 1124977 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
7613 1124977 : if (A == B)
7614 : return true;
7615 :
7616 980716 : switch (A) {
7617 : default:
7618 : return false;
7619 :
7620 15 : case MCK__DOT_16B:
7621 15 : return B == MCK__DOT_16b;
7622 :
7623 2 : case MCK__DOT_1D:
7624 2 : return B == MCK__DOT_1d;
7625 :
7626 2 : case MCK__DOT_1Q:
7627 2 : return B == MCK__DOT_1q;
7628 :
7629 8 : case MCK__DOT_2D:
7630 8 : return B == MCK__DOT_2d;
7631 :
7632 97 : case MCK__DOT_2H:
7633 97 : return B == MCK__DOT_2h;
7634 :
7635 104 : case MCK__DOT_2S:
7636 104 : return B == MCK__DOT_2s;
7637 :
7638 16 : case MCK__DOT_4B:
7639 16 : return B == MCK__DOT_4b;
7640 :
7641 96 : case MCK__DOT_4H:
7642 96 : return B == MCK__DOT_4h;
7643 :
7644 109 : case MCK__DOT_4S:
7645 109 : return B == MCK__DOT_4s;
7646 :
7647 21 : case MCK__DOT_8B:
7648 21 : return B == MCK__DOT_8b;
7649 :
7650 4 : case MCK__DOT_8H:
7651 4 : return B == MCK__DOT_8h;
7652 :
7653 0 : case MCK__DOT_B:
7654 0 : return B == MCK__DOT_b;
7655 :
7656 0 : case MCK__DOT_D:
7657 0 : return B == MCK__DOT_d;
7658 :
7659 0 : case MCK__DOT_H:
7660 0 : return B == MCK__DOT_h;
7661 :
7662 0 : case MCK__DOT_Q:
7663 0 : return B == MCK__DOT_q;
7664 :
7665 0 : case MCK__DOT_S:
7666 0 : return B == MCK__DOT_s;
7667 :
7668 0 : case MCK_Reg61:
7669 0 : switch (B) {
7670 : default: return false;
7671 0 : case MCK_Reg60: return true;
7672 0 : case MCK_Reg62: return true;
7673 0 : case MCK_Reg53: return true;
7674 0 : case MCK_Reg54: return true;
7675 0 : case MCK_Reg59: return true;
7676 0 : case MCK_Reg55: return true;
7677 0 : case MCK_Reg56: return true;
7678 0 : case MCK_Reg58: return true;
7679 0 : case MCK_XSeqPairsClass: return true;
7680 : }
7681 :
7682 4457 : case MCK_GPR32sponly:
7683 4457 : switch (B) {
7684 : default: return false;
7685 189 : case MCK_GPR32sp: return true;
7686 0 : case MCK_GPR32all: return true;
7687 : }
7688 :
7689 10794 : case MCK_GPR64sponly:
7690 10794 : switch (B) {
7691 : default: return false;
7692 5184 : case MCK_GPR64sp: return true;
7693 0 : case MCK_GPR64all: return true;
7694 : }
7695 :
7696 0 : case MCK_Reg60:
7697 : switch (B) {
7698 : default: return false;
7699 : case MCK_Reg53: return true;
7700 : case MCK_Reg54: return true;
7701 : case MCK_Reg59: return true;
7702 : case MCK_Reg55: return true;
7703 : case MCK_Reg56: return true;
7704 : case MCK_Reg58: return true;
7705 : case MCK_XSeqPairsClass: return true;
7706 : }
7707 :
7708 0 : case MCK_Reg62:
7709 : switch (B) {
7710 : default: return false;
7711 : case MCK_Reg53: return true;
7712 : case MCK_Reg54: return true;
7713 : case MCK_Reg59: return true;
7714 : case MCK_Reg55: return true;
7715 : case MCK_Reg56: return true;
7716 : case MCK_Reg58: return true;
7717 : case MCK_XSeqPairsClass: return true;
7718 : }
7719 :
7720 1636 : case MCK_rtcGPR64:
7721 : switch (B) {
7722 : default: return false;
7723 : case MCK_tcGPR64: return true;
7724 : case MCK_GPR64common: return true;
7725 : case MCK_GPR64: return true;
7726 : case MCK_GPR64sp: return true;
7727 : case MCK_GPR64all: return true;
7728 : }
7729 :
7730 0 : case MCK_Reg70:
7731 : switch (B) {
7732 : default: return false;
7733 : case MCK_Reg71: return true;
7734 : case MCK_Reg90: return true;
7735 : case MCK_Reg72: return true;
7736 : case MCK_Reg87: return true;
7737 : case MCK_Reg89: return true;
7738 : case MCK_Reg73: return true;
7739 : case MCK_Reg85: return true;
7740 : case MCK_Reg86: return true;
7741 : case MCK_Reg88: return true;
7742 : case MCK_Reg74: return true;
7743 : case MCK_Reg75: return true;
7744 : case MCK_Reg84: return true;
7745 : case MCK_Reg76: return true;
7746 : case MCK_Reg81: return true;
7747 : case MCK_Reg83: return true;
7748 : case MCK_Reg77: return true;
7749 : case MCK_Reg79: return true;
7750 : case MCK_Reg80: return true;
7751 : case MCK_Reg82: return true;
7752 : case MCK_ZPR4: return true;
7753 : }
7754 :
7755 0 : case MCK_Reg71:
7756 : switch (B) {
7757 : default: return false;
7758 : case MCK_Reg72: return true;
7759 : case MCK_Reg87: return true;
7760 : case MCK_Reg73: return true;
7761 : case MCK_Reg85: return true;
7762 : case MCK_Reg86: return true;
7763 : case MCK_Reg74: return true;
7764 : case MCK_Reg75: return true;
7765 : case MCK_Reg84: return true;
7766 : case MCK_Reg76: return true;
7767 : case MCK_Reg81: return true;
7768 : case MCK_Reg83: return true;
7769 : case MCK_Reg77: return true;
7770 : case MCK_Reg79: return true;
7771 : case MCK_Reg80: return true;
7772 : case MCK_Reg82: return true;
7773 : case MCK_ZPR4: return true;
7774 : }
7775 :
7776 0 : case MCK_Reg90:
7777 : switch (B) {
7778 : default: return false;
7779 : case MCK_Reg87: return true;
7780 : case MCK_Reg89: return true;
7781 : case MCK_Reg85: return true;
7782 : case MCK_Reg86: return true;
7783 : case MCK_Reg88: return true;
7784 : case MCK_Reg84: return true;
7785 : case MCK_Reg81: return true;
7786 : case MCK_Reg83: return true;
7787 : case MCK_Reg79: return true;
7788 : case MCK_Reg80: return true;
7789 : case MCK_Reg82: return true;
7790 : case MCK_ZPR4: return true;
7791 : }
7792 :
7793 0 : case MCK_Reg91:
7794 : switch (B) {
7795 : default: return false;
7796 : case MCK_Reg92: return true;
7797 : case MCK_Reg103: return true;
7798 : case MCK_Reg93: return true;
7799 : case MCK_Reg101: return true;
7800 : case MCK_Reg102: return true;
7801 : case MCK_Reg94: return true;
7802 : case MCK_Reg95: return true;
7803 : case MCK_Reg100: return true;
7804 : case MCK_Reg96: return true;
7805 : case MCK_Reg98: return true;
7806 : case MCK_Reg99: return true;
7807 : case MCK_ZPR3: return true;
7808 : }
7809 :
7810 0 : case MCK_Reg63:
7811 0 : switch (B) {
7812 : default: return false;
7813 0 : case MCK_Reg64: return true;
7814 0 : case MCK_Reg69: return true;
7815 0 : case MCK_Reg65: return true;
7816 0 : case MCK_Reg66: return true;
7817 0 : case MCK_Reg68: return true;
7818 0 : case MCK_ZPR2: return true;
7819 : }
7820 :
7821 0 : case MCK_Reg72:
7822 : switch (B) {
7823 : default: return false;
7824 : case MCK_Reg73: return true;
7825 : case MCK_Reg85: return true;
7826 : case MCK_Reg74: return true;
7827 : case MCK_Reg75: return true;
7828 : case MCK_Reg84: return true;
7829 : case MCK_Reg76: return true;
7830 : case MCK_Reg81: return true;
7831 : case MCK_Reg83: return true;
7832 : case MCK_Reg77: return true;
7833 : case MCK_Reg79: return true;
7834 : case MCK_Reg80: return true;
7835 : case MCK_Reg82: return true;
7836 : case MCK_ZPR4: return true;
7837 : }
7838 :
7839 0 : case MCK_Reg87:
7840 0 : switch (B) {
7841 : default: return false;
7842 0 : case MCK_Reg85: return true;
7843 0 : case MCK_Reg86: return true;
7844 0 : case MCK_Reg84: return true;
7845 0 : case MCK_Reg81: return true;
7846 0 : case MCK_Reg83: return true;
7847 0 : case MCK_Reg79: return true;
7848 0 : case MCK_Reg80: return true;
7849 0 : case MCK_Reg82: return true;
7850 0 : case MCK_ZPR4: return true;
7851 : }
7852 :
7853 0 : case MCK_Reg89:
7854 0 : switch (B) {
7855 : default: return false;
7856 0 : case MCK_Reg86: return true;
7857 0 : case MCK_Reg88: return true;
7858 0 : case MCK_Reg83: return true;
7859 0 : case MCK_Reg80: return true;
7860 0 : case MCK_Reg82: return true;
7861 0 : case MCK_ZPR4: return true;
7862 : }
7863 :
7864 0 : case MCK_Reg92:
7865 0 : switch (B) {
7866 : default: return false;
7867 0 : case MCK_Reg93: return true;
7868 0 : case MCK_Reg101: return true;
7869 0 : case MCK_Reg94: return true;
7870 0 : case MCK_Reg95: return true;
7871 0 : case MCK_Reg100: return true;
7872 0 : case MCK_Reg96: return true;
7873 0 : case MCK_Reg98: return true;
7874 0 : case MCK_Reg99: return true;
7875 0 : case MCK_ZPR3: return true;
7876 : }
7877 :
7878 0 : case MCK_Reg103:
7879 0 : switch (B) {
7880 : default: return false;
7881 0 : case MCK_Reg101: return true;
7882 0 : case MCK_Reg102: return true;
7883 0 : case MCK_Reg100: return true;
7884 0 : case MCK_Reg98: return true;
7885 0 : case MCK_Reg99: return true;
7886 0 : case MCK_ZPR3: return true;
7887 : }
7888 :
7889 0 : case MCK_Reg64:
7890 0 : switch (B) {
7891 : default: return false;
7892 0 : case MCK_Reg65: return true;
7893 0 : case MCK_Reg66: return true;
7894 0 : case MCK_Reg68: return true;
7895 0 : case MCK_ZPR2: return true;
7896 : }
7897 :
7898 0 : case MCK_Reg69:
7899 0 : switch (B) {
7900 : default: return false;
7901 0 : case MCK_Reg68: return true;
7902 0 : case MCK_ZPR2: return true;
7903 : }
7904 :
7905 0 : case MCK_Reg73:
7906 : switch (B) {
7907 : default: return false;
7908 : case MCK_Reg74: return true;
7909 : case MCK_Reg75: return true;
7910 : case MCK_Reg84: return true;
7911 : case MCK_Reg76: return true;
7912 : case MCK_Reg81: return true;
7913 : case MCK_Reg83: return true;
7914 : case MCK_Reg77: return true;
7915 : case MCK_Reg79: return true;
7916 : case MCK_Reg80: return true;
7917 : case MCK_Reg82: return true;
7918 : case MCK_ZPR4: return true;
7919 : }
7920 :
7921 0 : case MCK_Reg85:
7922 0 : switch (B) {
7923 : default: return false;
7924 0 : case MCK_Reg84: return true;
7925 0 : case MCK_Reg81: return true;
7926 0 : case MCK_Reg83: return true;
7927 0 : case MCK_Reg79: return true;
7928 0 : case MCK_Reg80: return true;
7929 0 : case MCK_Reg82: return true;
7930 0 : case MCK_ZPR4: return true;
7931 : }
7932 :
7933 0 : case MCK_Reg86:
7934 0 : switch (B) {
7935 : default: return false;
7936 0 : case MCK_Reg83: return true;
7937 0 : case MCK_Reg80: return true;
7938 0 : case MCK_Reg82: return true;
7939 0 : case MCK_ZPR4: return true;
7940 : }
7941 :
7942 0 : case MCK_Reg88:
7943 0 : switch (B) {
7944 : default: return false;
7945 0 : case MCK_Reg82: return true;
7946 0 : case MCK_ZPR4: return true;
7947 : }
7948 :
7949 0 : case MCK_Reg93:
7950 0 : switch (B) {
7951 : default: return false;
7952 0 : case MCK_Reg94: return true;
7953 0 : case MCK_Reg95: return true;
7954 0 : case MCK_Reg100: return true;
7955 0 : case MCK_Reg96: return true;
7956 0 : case MCK_Reg98: return true;
7957 0 : case MCK_Reg99: return true;
7958 0 : case MCK_ZPR3: return true;
7959 : }
7960 :
7961 0 : case MCK_Reg101:
7962 0 : switch (B) {
7963 : default: return false;
7964 0 : case MCK_Reg100: return true;
7965 0 : case MCK_Reg98: return true;
7966 0 : case MCK_Reg99: return true;
7967 0 : case MCK_ZPR3: return true;
7968 : }
7969 :
7970 0 : case MCK_Reg102:
7971 0 : switch (B) {
7972 : default: return false;
7973 0 : case MCK_Reg99: return true;
7974 0 : case MCK_ZPR3: return true;
7975 : }
7976 :
7977 16145 : case MCK_PPR_3b:
7978 16145 : return B == MCK_PPR;
7979 :
7980 108598 : case MCK_ZPR_3b:
7981 108598 : switch (B) {
7982 : default: return false;
7983 0 : case MCK_ZPR_4b: return true;
7984 0 : case MCK_ZPR: return true;
7985 : }
7986 :
7987 0 : case MCK_Reg31:
7988 : switch (B) {
7989 : default: return false;
7990 : case MCK_Reg32: return true;
7991 : case MCK_Reg41: return true;
7992 : case MCK_Reg33: return true;
7993 : case MCK_Reg38: return true;
7994 : case MCK_Reg40: return true;
7995 : case MCK_Reg34: return true;
7996 : case MCK_Reg36: return true;
7997 : case MCK_Reg37: return true;
7998 : case MCK_Reg39: return true;
7999 : case MCK_QQQQ: return true;
8000 : }
8001 :
8002 0 : case MCK_Reg74:
8003 : switch (B) {
8004 : default: return false;
8005 : case MCK_Reg75: return true;
8006 : case MCK_Reg84: return true;
8007 : case MCK_Reg76: return true;
8008 : case MCK_Reg81: return true;
8009 : case MCK_Reg83: return true;
8010 : case MCK_Reg77: return true;
8011 : case MCK_Reg79: return true;
8012 : case MCK_Reg80: return true;
8013 : case MCK_Reg82: return true;
8014 : case MCK_ZPR4: return true;
8015 : }
8016 :
8017 0 : case MCK_Reg32:
8018 0 : switch (B) {
8019 : default: return false;
8020 0 : case MCK_Reg33: return true;
8021 0 : case MCK_Reg38: return true;
8022 0 : case MCK_Reg34: return true;
8023 0 : case MCK_Reg36: return true;
8024 0 : case MCK_Reg37: return true;
8025 0 : case MCK_QQQQ: return true;
8026 : }
8027 :
8028 0 : case MCK_Reg41:
8029 0 : switch (B) {
8030 : default: return false;
8031 0 : case MCK_Reg38: return true;
8032 0 : case MCK_Reg40: return true;
8033 0 : case MCK_Reg36: return true;
8034 0 : case MCK_Reg37: return true;
8035 0 : case MCK_Reg39: return true;
8036 0 : case MCK_QQQQ: return true;
8037 : }
8038 :
8039 0 : case MCK_Reg42:
8040 0 : switch (B) {
8041 : default: return false;
8042 0 : case MCK_Reg43: return true;
8043 0 : case MCK_Reg48: return true;
8044 0 : case MCK_Reg44: return true;
8045 0 : case MCK_Reg46: return true;
8046 0 : case MCK_Reg47: return true;
8047 0 : case MCK_QQQ: return true;
8048 : }
8049 :
8050 0 : case MCK_Reg75:
8051 0 : switch (B) {
8052 : default: return false;
8053 0 : case MCK_Reg76: return true;
8054 0 : case MCK_Reg81: return true;
8055 0 : case MCK_Reg77: return true;
8056 0 : case MCK_Reg79: return true;
8057 0 : case MCK_Reg80: return true;
8058 0 : case MCK_ZPR4: return true;
8059 : }
8060 :
8061 0 : case MCK_Reg84:
8062 0 : switch (B) {
8063 : default: return false;
8064 0 : case MCK_Reg81: return true;
8065 0 : case MCK_Reg83: return true;
8066 0 : case MCK_Reg79: return true;
8067 0 : case MCK_Reg80: return true;
8068 0 : case MCK_Reg82: return true;
8069 0 : case MCK_ZPR4: return true;
8070 : }
8071 :
8072 0 : case MCK_Reg94:
8073 0 : switch (B) {
8074 : default: return false;
8075 0 : case MCK_Reg95: return true;
8076 0 : case MCK_Reg100: return true;
8077 0 : case MCK_Reg96: return true;
8078 0 : case MCK_Reg98: return true;
8079 0 : case MCK_Reg99: return true;
8080 0 : case MCK_ZPR3: return true;
8081 : }
8082 :
8083 0 : case MCK_Reg27:
8084 0 : switch (B) {
8085 : default: return false;
8086 0 : case MCK_Reg28: return true;
8087 0 : case MCK_Reg30: return true;
8088 0 : case MCK_QQ: return true;
8089 : }
8090 :
8091 0 : case MCK_Reg33:
8092 0 : switch (B) {
8093 : default: return false;
8094 0 : case MCK_Reg34: return true;
8095 0 : case MCK_Reg36: return true;
8096 0 : case MCK_QQQQ: return true;
8097 : }
8098 :
8099 0 : case MCK_Reg38:
8100 0 : switch (B) {
8101 : default: return false;
8102 0 : case MCK_Reg36: return true;
8103 0 : case MCK_Reg37: return true;
8104 0 : case MCK_QQQQ: return true;
8105 : }
8106 :
8107 0 : case MCK_Reg40:
8108 0 : switch (B) {
8109 : default: return false;
8110 0 : case MCK_Reg37: return true;
8111 0 : case MCK_Reg39: return true;
8112 0 : case MCK_QQQQ: return true;
8113 : }
8114 :
8115 0 : case MCK_Reg43:
8116 0 : switch (B) {
8117 : default: return false;
8118 0 : case MCK_Reg44: return true;
8119 0 : case MCK_Reg46: return true;
8120 0 : case MCK_QQQ: return true;
8121 : }
8122 :
8123 0 : case MCK_Reg48:
8124 0 : switch (B) {
8125 : default: return false;
8126 0 : case MCK_Reg46: return true;
8127 0 : case MCK_Reg47: return true;
8128 0 : case MCK_QQQ: return true;
8129 : }
8130 :
8131 0 : case MCK_Reg65:
8132 0 : switch (B) {
8133 : default: return false;
8134 0 : case MCK_Reg66: return true;
8135 0 : case MCK_Reg68: return true;
8136 0 : case MCK_ZPR2: return true;
8137 : }
8138 :
8139 0 : case MCK_Reg76:
8140 0 : switch (B) {
8141 : default: return false;
8142 0 : case MCK_Reg77: return true;
8143 0 : case MCK_Reg79: return true;
8144 0 : case MCK_ZPR4: return true;
8145 : }
8146 :
8147 0 : case MCK_Reg81:
8148 0 : switch (B) {
8149 : default: return false;
8150 0 : case MCK_Reg79: return true;
8151 0 : case MCK_Reg80: return true;
8152 0 : case MCK_ZPR4: return true;
8153 : }
8154 :
8155 0 : case MCK_Reg83:
8156 0 : switch (B) {
8157 : default: return false;
8158 0 : case MCK_Reg80: return true;
8159 0 : case MCK_Reg82: return true;
8160 0 : case MCK_ZPR4: return true;
8161 : }
8162 :
8163 0 : case MCK_Reg95:
8164 0 : switch (B) {
8165 : default: return false;
8166 0 : case MCK_Reg96: return true;
8167 0 : case MCK_Reg98: return true;
8168 0 : case MCK_ZPR3: return true;
8169 : }
8170 :
8171 0 : case MCK_Reg100:
8172 0 : switch (B) {
8173 : default: return false;
8174 0 : case MCK_Reg98: return true;
8175 0 : case MCK_Reg99: return true;
8176 0 : case MCK_ZPR3: return true;
8177 : }
8178 :
8179 0 : case MCK_Reg28:
8180 0 : return B == MCK_QQ;
8181 :
8182 0 : case MCK_Reg30:
8183 0 : return B == MCK_QQ;
8184 :
8185 0 : case MCK_Reg34:
8186 0 : return B == MCK_QQQQ;
8187 :
8188 0 : case MCK_Reg36:
8189 0 : return B == MCK_QQQQ;
8190 :
8191 0 : case MCK_Reg37:
8192 0 : return B == MCK_QQQQ;
8193 :
8194 0 : case MCK_Reg39:
8195 0 : return B == MCK_QQQQ;
8196 :
8197 0 : case MCK_Reg44:
8198 0 : return B == MCK_QQQ;
8199 :
8200 0 : case MCK_Reg46:
8201 0 : return B == MCK_QQQ;
8202 :
8203 0 : case MCK_Reg47:
8204 0 : return B == MCK_QQQ;
8205 :
8206 0 : case MCK_Reg66:
8207 0 : return B == MCK_ZPR2;
8208 :
8209 0 : case MCK_Reg68:
8210 0 : return B == MCK_ZPR2;
8211 :
8212 0 : case MCK_Reg77:
8213 0 : return B == MCK_ZPR4;
8214 :
8215 0 : case MCK_Reg79:
8216 0 : return B == MCK_ZPR4;
8217 :
8218 0 : case MCK_Reg80:
8219 0 : return B == MCK_ZPR4;
8220 :
8221 0 : case MCK_Reg82:
8222 0 : return B == MCK_ZPR4;
8223 :
8224 0 : case MCK_Reg96:
8225 0 : return B == MCK_ZPR3;
8226 :
8227 0 : case MCK_Reg98:
8228 0 : return B == MCK_ZPR3;
8229 :
8230 0 : case MCK_Reg99:
8231 0 : return B == MCK_ZPR3;
8232 :
8233 57015 : case MCK_FPR128_lo:
8234 57015 : return B == MCK_FPR128;
8235 :
8236 2400 : case MCK_ZPR_4b:
8237 2400 : return B == MCK_ZPR;
8238 :
8239 27 : case MCK_Reg53:
8240 : switch (B) {
8241 : default: return false;
8242 : case MCK_Reg54: return true;
8243 : case MCK_Reg59: return true;
8244 : case MCK_Reg55: return true;
8245 : case MCK_Reg56: return true;
8246 : case MCK_Reg58: return true;
8247 : case MCK_XSeqPairsClass: return true;
8248 : }
8249 :
8250 0 : case MCK_Reg54:
8251 : switch (B) {
8252 : default: return false;
8253 : case MCK_Reg55: return true;
8254 : case MCK_Reg56: return true;
8255 : case MCK_Reg58: return true;
8256 : case MCK_XSeqPairsClass: return true;
8257 : }
8258 :
8259 0 : case MCK_Reg59:
8260 0 : switch (B) {
8261 : default: return false;
8262 0 : case MCK_Reg58: return true;
8263 0 : case MCK_XSeqPairsClass: return true;
8264 : }
8265 :
8266 89053 : case MCK_tcGPR64:
8267 : switch (B) {
8268 : default: return false;
8269 : case MCK_GPR64common: return true;
8270 : case MCK_GPR64: return true;
8271 : case MCK_GPR64sp: return true;
8272 : case MCK_GPR64all: return true;
8273 : }
8274 :
8275 2 : case MCK_Reg49:
8276 : switch (B) {
8277 : default: return false;
8278 : case MCK_Reg50: return true;
8279 : case MCK_Reg52: return true;
8280 : case MCK_WSeqPairsClass: return true;
8281 : }
8282 :
8283 0 : case MCK_Reg55:
8284 : switch (B) {
8285 : default: return false;
8286 : case MCK_Reg56: return true;
8287 : case MCK_Reg58: return true;
8288 : case MCK_XSeqPairsClass: return true;
8289 : }
8290 :
8291 0 : case MCK_Reg50:
8292 0 : return B == MCK_WSeqPairsClass;
8293 :
8294 0 : case MCK_Reg52:
8295 0 : return B == MCK_WSeqPairsClass;
8296 :
8297 0 : case MCK_Reg56:
8298 0 : return B == MCK_XSeqPairsClass;
8299 :
8300 0 : case MCK_Reg58:
8301 0 : return B == MCK_XSeqPairsClass;
8302 :
8303 29811 : case MCK_GPR32common:
8304 : switch (B) {
8305 : default: return false;
8306 : case MCK_GPR32: return true;
8307 : case MCK_GPR32sp: return true;
8308 : case MCK_GPR32all: return true;
8309 : }
8310 :
8311 8338 : case MCK_GPR64common:
8312 : switch (B) {
8313 : default: return false;
8314 : case MCK_GPR64: return true;
8315 : case MCK_GPR64sp: return true;
8316 : case MCK_GPR64all: return true;
8317 : }
8318 :
8319 38033 : case MCK_GPR32:
8320 38033 : return B == MCK_GPR32all;
8321 :
8322 7267 : case MCK_GPR32sp:
8323 7267 : return B == MCK_GPR32all;
8324 :
8325 35512 : case MCK_GPR64:
8326 35512 : return B == MCK_GPR64all;
8327 :
8328 11346 : case MCK_GPR64sp:
8329 11346 : return B == MCK_GPR64all;
8330 :
8331 0 : case MCK_Extend64:
8332 0 : return B == MCK_Extend;
8333 :
8334 0 : case MCK_ExtendLSL64:
8335 0 : return B == MCK_Extend;
8336 :
8337 3 : case MCK_LogicalVecHalfWordShifter:
8338 3 : switch (B) {
8339 : default: return false;
8340 0 : case MCK_LogicalVecShifter: return true;
8341 0 : case MCK_Shifter: return true;
8342 : }
8343 :
8344 0 : case MCK_ArithmeticShifter32:
8345 0 : return B == MCK_Shifter;
8346 :
8347 0 : case MCK_ArithmeticShifter64:
8348 0 : return B == MCK_Shifter;
8349 :
8350 0 : case MCK_LogicalShifter32:
8351 0 : return B == MCK_Shifter;
8352 :
8353 0 : case MCK_LogicalShifter64:
8354 0 : return B == MCK_Shifter;
8355 :
8356 19 : case MCK_LogicalVecShifter:
8357 19 : return B == MCK_Shifter;
8358 :
8359 0 : case MCK_MovImm32Shifter:
8360 0 : return B == MCK_Shifter;
8361 :
8362 0 : case MCK_MovImm64Shifter:
8363 0 : return B == MCK_Shifter;
8364 :
8365 2 : case MCK_MoveVecShifter:
8366 2 : return B == MCK_Shifter;
8367 : }
8368 : }
8369 :
8370 1070263 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
8371 : AArch64Operand &Operand = (AArch64Operand&)GOp;
8372 1070263 : if (Kind == InvalidMatchClass)
8373 : return MCTargetAsmParser::Match_InvalidOperand;
8374 :
8375 1060011 : if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
8376 342148 : return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
8377 : MCTargetAsmParser::Match_Success :
8378 : MCTargetAsmParser::Match_InvalidOperand;
8379 :
8380 888937 : switch (Kind) {
8381 : default: break;
8382 : // 'AddSubImmNeg' class
8383 1012 : case MCK_AddSubImmNeg: {
8384 1012 : DiagnosticPredicate DP(Operand.isAddSubImmNeg());
8385 1012 : if (DP.isMatch())
8386 : return MCTargetAsmParser::Match_Success;
8387 : if (DP.isNearMatch())
8388 946 : return AArch64AsmParser::Match_AddSubSecondSource;
8389 : break;
8390 : }
8391 : // 'AddSubImm' class
8392 990 : case MCK_AddSubImm: {
8393 990 : DiagnosticPredicate DP(Operand.isAddSubImm());
8394 990 : if (DP.isMatch())
8395 : return MCTargetAsmParser::Match_Success;
8396 : if (DP.isNearMatch())
8397 500 : return AArch64AsmParser::Match_AddSubSecondSource;
8398 : break;
8399 : }
8400 : // 'AdrLabel' class
8401 44 : case MCK_AdrLabel: {
8402 : DiagnosticPredicate DP(Operand.isAdrLabel());
8403 44 : if (DP.isMatch())
8404 : return MCTargetAsmParser::Match_Success;
8405 : if (DP.isNearMatch())
8406 6 : return AArch64AsmParser::Match_InvalidLabel;
8407 : break;
8408 : }
8409 : // 'AdrpLabel' class
8410 204 : case MCK_AdrpLabel: {
8411 : DiagnosticPredicate DP(Operand.isAdrpLabel());
8412 204 : if (DP.isMatch())
8413 : return MCTargetAsmParser::Match_Success;
8414 : if (DP.isNearMatch())
8415 10 : return AArch64AsmParser::Match_InvalidLabel;
8416 : break;
8417 : }
8418 : // 'BTIHint' class
8419 12 : case MCK_BTIHint: {
8420 : DiagnosticPredicate DP(Operand.isBTIHint());
8421 12 : if (DP.isMatch())
8422 : return MCTargetAsmParser::Match_Success;
8423 : break;
8424 : }
8425 : // 'Barrier' class
8426 49 : case MCK_Barrier: {
8427 : DiagnosticPredicate DP(Operand.isBarrier());
8428 49 : if (DP.isMatch())
8429 : return MCTargetAsmParser::Match_Success;
8430 : break;
8431 : }
8432 : // 'BranchTarget14' class
8433 : case MCK_BranchTarget14: {
8434 : DiagnosticPredicate DP(Operand.isBranchTarget<14>());
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