Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Target Register Enum Values *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_REGINFO_ENUM
11 : #undef GET_REGINFO_ENUM
12 :
13 : namespace llvm {
14 :
15 : class MCRegisterClass;
16 : extern const MCRegisterClass AArch64MCRegisterClasses[];
17 :
18 : namespace AArch64 {
19 : enum {
20 : NoRegister,
21 : FFR = 1,
22 : FP = 2,
23 : LR = 3,
24 : NZCV = 4,
25 : SP = 5,
26 : WSP = 6,
27 : WZR = 7,
28 : XZR = 8,
29 : B0 = 9,
30 : B1 = 10,
31 : B2 = 11,
32 : B3 = 12,
33 : B4 = 13,
34 : B5 = 14,
35 : B6 = 15,
36 : B7 = 16,
37 : B8 = 17,
38 : B9 = 18,
39 : B10 = 19,
40 : B11 = 20,
41 : B12 = 21,
42 : B13 = 22,
43 : B14 = 23,
44 : B15 = 24,
45 : B16 = 25,
46 : B17 = 26,
47 : B18 = 27,
48 : B19 = 28,
49 : B20 = 29,
50 : B21 = 30,
51 : B22 = 31,
52 : B23 = 32,
53 : B24 = 33,
54 : B25 = 34,
55 : B26 = 35,
56 : B27 = 36,
57 : B28 = 37,
58 : B29 = 38,
59 : B30 = 39,
60 : B31 = 40,
61 : D0 = 41,
62 : D1 = 42,
63 : D2 = 43,
64 : D3 = 44,
65 : D4 = 45,
66 : D5 = 46,
67 : D6 = 47,
68 : D7 = 48,
69 : D8 = 49,
70 : D9 = 50,
71 : D10 = 51,
72 : D11 = 52,
73 : D12 = 53,
74 : D13 = 54,
75 : D14 = 55,
76 : D15 = 56,
77 : D16 = 57,
78 : D17 = 58,
79 : D18 = 59,
80 : D19 = 60,
81 : D20 = 61,
82 : D21 = 62,
83 : D22 = 63,
84 : D23 = 64,
85 : D24 = 65,
86 : D25 = 66,
87 : D26 = 67,
88 : D27 = 68,
89 : D28 = 69,
90 : D29 = 70,
91 : D30 = 71,
92 : D31 = 72,
93 : H0 = 73,
94 : H1 = 74,
95 : H2 = 75,
96 : H3 = 76,
97 : H4 = 77,
98 : H5 = 78,
99 : H6 = 79,
100 : H7 = 80,
101 : H8 = 81,
102 : H9 = 82,
103 : H10 = 83,
104 : H11 = 84,
105 : H12 = 85,
106 : H13 = 86,
107 : H14 = 87,
108 : H15 = 88,
109 : H16 = 89,
110 : H17 = 90,
111 : H18 = 91,
112 : H19 = 92,
113 : H20 = 93,
114 : H21 = 94,
115 : H22 = 95,
116 : H23 = 96,
117 : H24 = 97,
118 : H25 = 98,
119 : H26 = 99,
120 : H27 = 100,
121 : H28 = 101,
122 : H29 = 102,
123 : H30 = 103,
124 : H31 = 104,
125 : P0 = 105,
126 : P1 = 106,
127 : P2 = 107,
128 : P3 = 108,
129 : P4 = 109,
130 : P5 = 110,
131 : P6 = 111,
132 : P7 = 112,
133 : P8 = 113,
134 : P9 = 114,
135 : P10 = 115,
136 : P11 = 116,
137 : P12 = 117,
138 : P13 = 118,
139 : P14 = 119,
140 : P15 = 120,
141 : Q0 = 121,
142 : Q1 = 122,
143 : Q2 = 123,
144 : Q3 = 124,
145 : Q4 = 125,
146 : Q5 = 126,
147 : Q6 = 127,
148 : Q7 = 128,
149 : Q8 = 129,
150 : Q9 = 130,
151 : Q10 = 131,
152 : Q11 = 132,
153 : Q12 = 133,
154 : Q13 = 134,
155 : Q14 = 135,
156 : Q15 = 136,
157 : Q16 = 137,
158 : Q17 = 138,
159 : Q18 = 139,
160 : Q19 = 140,
161 : Q20 = 141,
162 : Q21 = 142,
163 : Q22 = 143,
164 : Q23 = 144,
165 : Q24 = 145,
166 : Q25 = 146,
167 : Q26 = 147,
168 : Q27 = 148,
169 : Q28 = 149,
170 : Q29 = 150,
171 : Q30 = 151,
172 : Q31 = 152,
173 : S0 = 153,
174 : S1 = 154,
175 : S2 = 155,
176 : S3 = 156,
177 : S4 = 157,
178 : S5 = 158,
179 : S6 = 159,
180 : S7 = 160,
181 : S8 = 161,
182 : S9 = 162,
183 : S10 = 163,
184 : S11 = 164,
185 : S12 = 165,
186 : S13 = 166,
187 : S14 = 167,
188 : S15 = 168,
189 : S16 = 169,
190 : S17 = 170,
191 : S18 = 171,
192 : S19 = 172,
193 : S20 = 173,
194 : S21 = 174,
195 : S22 = 175,
196 : S23 = 176,
197 : S24 = 177,
198 : S25 = 178,
199 : S26 = 179,
200 : S27 = 180,
201 : S28 = 181,
202 : S29 = 182,
203 : S30 = 183,
204 : S31 = 184,
205 : W0 = 185,
206 : W1 = 186,
207 : W2 = 187,
208 : W3 = 188,
209 : W4 = 189,
210 : W5 = 190,
211 : W6 = 191,
212 : W7 = 192,
213 : W8 = 193,
214 : W9 = 194,
215 : W10 = 195,
216 : W11 = 196,
217 : W12 = 197,
218 : W13 = 198,
219 : W14 = 199,
220 : W15 = 200,
221 : W16 = 201,
222 : W17 = 202,
223 : W18 = 203,
224 : W19 = 204,
225 : W20 = 205,
226 : W21 = 206,
227 : W22 = 207,
228 : W23 = 208,
229 : W24 = 209,
230 : W25 = 210,
231 : W26 = 211,
232 : W27 = 212,
233 : W28 = 213,
234 : W29 = 214,
235 : W30 = 215,
236 : X0 = 216,
237 : X1 = 217,
238 : X2 = 218,
239 : X3 = 219,
240 : X4 = 220,
241 : X5 = 221,
242 : X6 = 222,
243 : X7 = 223,
244 : X8 = 224,
245 : X9 = 225,
246 : X10 = 226,
247 : X11 = 227,
248 : X12 = 228,
249 : X13 = 229,
250 : X14 = 230,
251 : X15 = 231,
252 : X16 = 232,
253 : X17 = 233,
254 : X18 = 234,
255 : X19 = 235,
256 : X20 = 236,
257 : X21 = 237,
258 : X22 = 238,
259 : X23 = 239,
260 : X24 = 240,
261 : X25 = 241,
262 : X26 = 242,
263 : X27 = 243,
264 : X28 = 244,
265 : Z0 = 245,
266 : Z1 = 246,
267 : Z2 = 247,
268 : Z3 = 248,
269 : Z4 = 249,
270 : Z5 = 250,
271 : Z6 = 251,
272 : Z7 = 252,
273 : Z8 = 253,
274 : Z9 = 254,
275 : Z10 = 255,
276 : Z11 = 256,
277 : Z12 = 257,
278 : Z13 = 258,
279 : Z14 = 259,
280 : Z15 = 260,
281 : Z16 = 261,
282 : Z17 = 262,
283 : Z18 = 263,
284 : Z19 = 264,
285 : Z20 = 265,
286 : Z21 = 266,
287 : Z22 = 267,
288 : Z23 = 268,
289 : Z24 = 269,
290 : Z25 = 270,
291 : Z26 = 271,
292 : Z27 = 272,
293 : Z28 = 273,
294 : Z29 = 274,
295 : Z30 = 275,
296 : Z31 = 276,
297 : Z0_HI = 277,
298 : Z1_HI = 278,
299 : Z2_HI = 279,
300 : Z3_HI = 280,
301 : Z4_HI = 281,
302 : Z5_HI = 282,
303 : Z6_HI = 283,
304 : Z7_HI = 284,
305 : Z8_HI = 285,
306 : Z9_HI = 286,
307 : Z10_HI = 287,
308 : Z11_HI = 288,
309 : Z12_HI = 289,
310 : Z13_HI = 290,
311 : Z14_HI = 291,
312 : Z15_HI = 292,
313 : Z16_HI = 293,
314 : Z17_HI = 294,
315 : Z18_HI = 295,
316 : Z19_HI = 296,
317 : Z20_HI = 297,
318 : Z21_HI = 298,
319 : Z22_HI = 299,
320 : Z23_HI = 300,
321 : Z24_HI = 301,
322 : Z25_HI = 302,
323 : Z26_HI = 303,
324 : Z27_HI = 304,
325 : Z28_HI = 305,
326 : Z29_HI = 306,
327 : Z30_HI = 307,
328 : Z31_HI = 308,
329 : D0_D1 = 309,
330 : D1_D2 = 310,
331 : D2_D3 = 311,
332 : D3_D4 = 312,
333 : D4_D5 = 313,
334 : D5_D6 = 314,
335 : D6_D7 = 315,
336 : D7_D8 = 316,
337 : D8_D9 = 317,
338 : D9_D10 = 318,
339 : D10_D11 = 319,
340 : D11_D12 = 320,
341 : D12_D13 = 321,
342 : D13_D14 = 322,
343 : D14_D15 = 323,
344 : D15_D16 = 324,
345 : D16_D17 = 325,
346 : D17_D18 = 326,
347 : D18_D19 = 327,
348 : D19_D20 = 328,
349 : D20_D21 = 329,
350 : D21_D22 = 330,
351 : D22_D23 = 331,
352 : D23_D24 = 332,
353 : D24_D25 = 333,
354 : D25_D26 = 334,
355 : D26_D27 = 335,
356 : D27_D28 = 336,
357 : D28_D29 = 337,
358 : D29_D30 = 338,
359 : D30_D31 = 339,
360 : D31_D0 = 340,
361 : D0_D1_D2_D3 = 341,
362 : D1_D2_D3_D4 = 342,
363 : D2_D3_D4_D5 = 343,
364 : D3_D4_D5_D6 = 344,
365 : D4_D5_D6_D7 = 345,
366 : D5_D6_D7_D8 = 346,
367 : D6_D7_D8_D9 = 347,
368 : D7_D8_D9_D10 = 348,
369 : D8_D9_D10_D11 = 349,
370 : D9_D10_D11_D12 = 350,
371 : D10_D11_D12_D13 = 351,
372 : D11_D12_D13_D14 = 352,
373 : D12_D13_D14_D15 = 353,
374 : D13_D14_D15_D16 = 354,
375 : D14_D15_D16_D17 = 355,
376 : D15_D16_D17_D18 = 356,
377 : D16_D17_D18_D19 = 357,
378 : D17_D18_D19_D20 = 358,
379 : D18_D19_D20_D21 = 359,
380 : D19_D20_D21_D22 = 360,
381 : D20_D21_D22_D23 = 361,
382 : D21_D22_D23_D24 = 362,
383 : D22_D23_D24_D25 = 363,
384 : D23_D24_D25_D26 = 364,
385 : D24_D25_D26_D27 = 365,
386 : D25_D26_D27_D28 = 366,
387 : D26_D27_D28_D29 = 367,
388 : D27_D28_D29_D30 = 368,
389 : D28_D29_D30_D31 = 369,
390 : D29_D30_D31_D0 = 370,
391 : D30_D31_D0_D1 = 371,
392 : D31_D0_D1_D2 = 372,
393 : D0_D1_D2 = 373,
394 : D1_D2_D3 = 374,
395 : D2_D3_D4 = 375,
396 : D3_D4_D5 = 376,
397 : D4_D5_D6 = 377,
398 : D5_D6_D7 = 378,
399 : D6_D7_D8 = 379,
400 : D7_D8_D9 = 380,
401 : D8_D9_D10 = 381,
402 : D9_D10_D11 = 382,
403 : D10_D11_D12 = 383,
404 : D11_D12_D13 = 384,
405 : D12_D13_D14 = 385,
406 : D13_D14_D15 = 386,
407 : D14_D15_D16 = 387,
408 : D15_D16_D17 = 388,
409 : D16_D17_D18 = 389,
410 : D17_D18_D19 = 390,
411 : D18_D19_D20 = 391,
412 : D19_D20_D21 = 392,
413 : D20_D21_D22 = 393,
414 : D21_D22_D23 = 394,
415 : D22_D23_D24 = 395,
416 : D23_D24_D25 = 396,
417 : D24_D25_D26 = 397,
418 : D25_D26_D27 = 398,
419 : D26_D27_D28 = 399,
420 : D27_D28_D29 = 400,
421 : D28_D29_D30 = 401,
422 : D29_D30_D31 = 402,
423 : D30_D31_D0 = 403,
424 : D31_D0_D1 = 404,
425 : Q0_Q1 = 405,
426 : Q1_Q2 = 406,
427 : Q2_Q3 = 407,
428 : Q3_Q4 = 408,
429 : Q4_Q5 = 409,
430 : Q5_Q6 = 410,
431 : Q6_Q7 = 411,
432 : Q7_Q8 = 412,
433 : Q8_Q9 = 413,
434 : Q9_Q10 = 414,
435 : Q10_Q11 = 415,
436 : Q11_Q12 = 416,
437 : Q12_Q13 = 417,
438 : Q13_Q14 = 418,
439 : Q14_Q15 = 419,
440 : Q15_Q16 = 420,
441 : Q16_Q17 = 421,
442 : Q17_Q18 = 422,
443 : Q18_Q19 = 423,
444 : Q19_Q20 = 424,
445 : Q20_Q21 = 425,
446 : Q21_Q22 = 426,
447 : Q22_Q23 = 427,
448 : Q23_Q24 = 428,
449 : Q24_Q25 = 429,
450 : Q25_Q26 = 430,
451 : Q26_Q27 = 431,
452 : Q27_Q28 = 432,
453 : Q28_Q29 = 433,
454 : Q29_Q30 = 434,
455 : Q30_Q31 = 435,
456 : Q31_Q0 = 436,
457 : Q0_Q1_Q2_Q3 = 437,
458 : Q1_Q2_Q3_Q4 = 438,
459 : Q2_Q3_Q4_Q5 = 439,
460 : Q3_Q4_Q5_Q6 = 440,
461 : Q4_Q5_Q6_Q7 = 441,
462 : Q5_Q6_Q7_Q8 = 442,
463 : Q6_Q7_Q8_Q9 = 443,
464 : Q7_Q8_Q9_Q10 = 444,
465 : Q8_Q9_Q10_Q11 = 445,
466 : Q9_Q10_Q11_Q12 = 446,
467 : Q10_Q11_Q12_Q13 = 447,
468 : Q11_Q12_Q13_Q14 = 448,
469 : Q12_Q13_Q14_Q15 = 449,
470 : Q13_Q14_Q15_Q16 = 450,
471 : Q14_Q15_Q16_Q17 = 451,
472 : Q15_Q16_Q17_Q18 = 452,
473 : Q16_Q17_Q18_Q19 = 453,
474 : Q17_Q18_Q19_Q20 = 454,
475 : Q18_Q19_Q20_Q21 = 455,
476 : Q19_Q20_Q21_Q22 = 456,
477 : Q20_Q21_Q22_Q23 = 457,
478 : Q21_Q22_Q23_Q24 = 458,
479 : Q22_Q23_Q24_Q25 = 459,
480 : Q23_Q24_Q25_Q26 = 460,
481 : Q24_Q25_Q26_Q27 = 461,
482 : Q25_Q26_Q27_Q28 = 462,
483 : Q26_Q27_Q28_Q29 = 463,
484 : Q27_Q28_Q29_Q30 = 464,
485 : Q28_Q29_Q30_Q31 = 465,
486 : Q29_Q30_Q31_Q0 = 466,
487 : Q30_Q31_Q0_Q1 = 467,
488 : Q31_Q0_Q1_Q2 = 468,
489 : Q0_Q1_Q2 = 469,
490 : Q1_Q2_Q3 = 470,
491 : Q2_Q3_Q4 = 471,
492 : Q3_Q4_Q5 = 472,
493 : Q4_Q5_Q6 = 473,
494 : Q5_Q6_Q7 = 474,
495 : Q6_Q7_Q8 = 475,
496 : Q7_Q8_Q9 = 476,
497 : Q8_Q9_Q10 = 477,
498 : Q9_Q10_Q11 = 478,
499 : Q10_Q11_Q12 = 479,
500 : Q11_Q12_Q13 = 480,
501 : Q12_Q13_Q14 = 481,
502 : Q13_Q14_Q15 = 482,
503 : Q14_Q15_Q16 = 483,
504 : Q15_Q16_Q17 = 484,
505 : Q16_Q17_Q18 = 485,
506 : Q17_Q18_Q19 = 486,
507 : Q18_Q19_Q20 = 487,
508 : Q19_Q20_Q21 = 488,
509 : Q20_Q21_Q22 = 489,
510 : Q21_Q22_Q23 = 490,
511 : Q22_Q23_Q24 = 491,
512 : Q23_Q24_Q25 = 492,
513 : Q24_Q25_Q26 = 493,
514 : Q25_Q26_Q27 = 494,
515 : Q26_Q27_Q28 = 495,
516 : Q27_Q28_Q29 = 496,
517 : Q28_Q29_Q30 = 497,
518 : Q29_Q30_Q31 = 498,
519 : Q30_Q31_Q0 = 499,
520 : Q31_Q0_Q1 = 500,
521 : WZR_W0 = 501,
522 : W30_WZR = 502,
523 : W0_W1 = 503,
524 : W1_W2 = 504,
525 : W2_W3 = 505,
526 : W3_W4 = 506,
527 : W4_W5 = 507,
528 : W5_W6 = 508,
529 : W6_W7 = 509,
530 : W7_W8 = 510,
531 : W8_W9 = 511,
532 : W9_W10 = 512,
533 : W10_W11 = 513,
534 : W11_W12 = 514,
535 : W12_W13 = 515,
536 : W13_W14 = 516,
537 : W14_W15 = 517,
538 : W15_W16 = 518,
539 : W16_W17 = 519,
540 : W17_W18 = 520,
541 : W18_W19 = 521,
542 : W19_W20 = 522,
543 : W20_W21 = 523,
544 : W21_W22 = 524,
545 : W22_W23 = 525,
546 : W23_W24 = 526,
547 : W24_W25 = 527,
548 : W25_W26 = 528,
549 : W26_W27 = 529,
550 : W27_W28 = 530,
551 : W28_W29 = 531,
552 : W29_W30 = 532,
553 : FP_LR = 533,
554 : LR_XZR = 534,
555 : XZR_X0 = 535,
556 : X28_FP = 536,
557 : X0_X1 = 537,
558 : X1_X2 = 538,
559 : X2_X3 = 539,
560 : X3_X4 = 540,
561 : X4_X5 = 541,
562 : X5_X6 = 542,
563 : X6_X7 = 543,
564 : X7_X8 = 544,
565 : X8_X9 = 545,
566 : X9_X10 = 546,
567 : X10_X11 = 547,
568 : X11_X12 = 548,
569 : X12_X13 = 549,
570 : X13_X14 = 550,
571 : X14_X15 = 551,
572 : X15_X16 = 552,
573 : X16_X17 = 553,
574 : X17_X18 = 554,
575 : X18_X19 = 555,
576 : X19_X20 = 556,
577 : X20_X21 = 557,
578 : X21_X22 = 558,
579 : X22_X23 = 559,
580 : X23_X24 = 560,
581 : X24_X25 = 561,
582 : X25_X26 = 562,
583 : X26_X27 = 563,
584 : X27_X28 = 564,
585 : Z0_Z1 = 565,
586 : Z1_Z2 = 566,
587 : Z2_Z3 = 567,
588 : Z3_Z4 = 568,
589 : Z4_Z5 = 569,
590 : Z5_Z6 = 570,
591 : Z6_Z7 = 571,
592 : Z7_Z8 = 572,
593 : Z8_Z9 = 573,
594 : Z9_Z10 = 574,
595 : Z10_Z11 = 575,
596 : Z11_Z12 = 576,
597 : Z12_Z13 = 577,
598 : Z13_Z14 = 578,
599 : Z14_Z15 = 579,
600 : Z15_Z16 = 580,
601 : Z16_Z17 = 581,
602 : Z17_Z18 = 582,
603 : Z18_Z19 = 583,
604 : Z19_Z20 = 584,
605 : Z20_Z21 = 585,
606 : Z21_Z22 = 586,
607 : Z22_Z23 = 587,
608 : Z23_Z24 = 588,
609 : Z24_Z25 = 589,
610 : Z25_Z26 = 590,
611 : Z26_Z27 = 591,
612 : Z27_Z28 = 592,
613 : Z28_Z29 = 593,
614 : Z29_Z30 = 594,
615 : Z30_Z31 = 595,
616 : Z31_Z0 = 596,
617 : Z0_Z1_Z2_Z3 = 597,
618 : Z1_Z2_Z3_Z4 = 598,
619 : Z2_Z3_Z4_Z5 = 599,
620 : Z3_Z4_Z5_Z6 = 600,
621 : Z4_Z5_Z6_Z7 = 601,
622 : Z5_Z6_Z7_Z8 = 602,
623 : Z6_Z7_Z8_Z9 = 603,
624 : Z7_Z8_Z9_Z10 = 604,
625 : Z8_Z9_Z10_Z11 = 605,
626 : Z9_Z10_Z11_Z12 = 606,
627 : Z10_Z11_Z12_Z13 = 607,
628 : Z11_Z12_Z13_Z14 = 608,
629 : Z12_Z13_Z14_Z15 = 609,
630 : Z13_Z14_Z15_Z16 = 610,
631 : Z14_Z15_Z16_Z17 = 611,
632 : Z15_Z16_Z17_Z18 = 612,
633 : Z16_Z17_Z18_Z19 = 613,
634 : Z17_Z18_Z19_Z20 = 614,
635 : Z18_Z19_Z20_Z21 = 615,
636 : Z19_Z20_Z21_Z22 = 616,
637 : Z20_Z21_Z22_Z23 = 617,
638 : Z21_Z22_Z23_Z24 = 618,
639 : Z22_Z23_Z24_Z25 = 619,
640 : Z23_Z24_Z25_Z26 = 620,
641 : Z24_Z25_Z26_Z27 = 621,
642 : Z25_Z26_Z27_Z28 = 622,
643 : Z26_Z27_Z28_Z29 = 623,
644 : Z27_Z28_Z29_Z30 = 624,
645 : Z28_Z29_Z30_Z31 = 625,
646 : Z29_Z30_Z31_Z0 = 626,
647 : Z30_Z31_Z0_Z1 = 627,
648 : Z31_Z0_Z1_Z2 = 628,
649 : Z0_Z1_Z2 = 629,
650 : Z1_Z2_Z3 = 630,
651 : Z2_Z3_Z4 = 631,
652 : Z3_Z4_Z5 = 632,
653 : Z4_Z5_Z6 = 633,
654 : Z5_Z6_Z7 = 634,
655 : Z6_Z7_Z8 = 635,
656 : Z7_Z8_Z9 = 636,
657 : Z8_Z9_Z10 = 637,
658 : Z9_Z10_Z11 = 638,
659 : Z10_Z11_Z12 = 639,
660 : Z11_Z12_Z13 = 640,
661 : Z12_Z13_Z14 = 641,
662 : Z13_Z14_Z15 = 642,
663 : Z14_Z15_Z16 = 643,
664 : Z15_Z16_Z17 = 644,
665 : Z16_Z17_Z18 = 645,
666 : Z17_Z18_Z19 = 646,
667 : Z18_Z19_Z20 = 647,
668 : Z19_Z20_Z21 = 648,
669 : Z20_Z21_Z22 = 649,
670 : Z21_Z22_Z23 = 650,
671 : Z22_Z23_Z24 = 651,
672 : Z23_Z24_Z25 = 652,
673 : Z24_Z25_Z26 = 653,
674 : Z25_Z26_Z27 = 654,
675 : Z26_Z27_Z28 = 655,
676 : Z27_Z28_Z29 = 656,
677 : Z28_Z29_Z30 = 657,
678 : Z29_Z30_Z31 = 658,
679 : Z30_Z31_Z0 = 659,
680 : Z31_Z0_Z1 = 660,
681 : NUM_TARGET_REGS // 661
682 : };
683 : } // end namespace AArch64
684 :
685 : // Register classes
686 :
687 : namespace AArch64 {
688 : enum {
689 : FPR8RegClassID = 0,
690 : FPR16RegClassID = 1,
691 : PPRRegClassID = 2,
692 : PPR_3bRegClassID = 3,
693 : GPR32allRegClassID = 4,
694 : FPR32RegClassID = 5,
695 : GPR32RegClassID = 6,
696 : GPR32spRegClassID = 7,
697 : GPR32commonRegClassID = 8,
698 : CCRRegClassID = 9,
699 : GPR32sponlyRegClassID = 10,
700 : WSeqPairsClassRegClassID = 11,
701 : WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12,
702 : WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
703 : WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14,
704 : GPR64allRegClassID = 15,
705 : FPR64RegClassID = 16,
706 : GPR64RegClassID = 17,
707 : GPR64spRegClassID = 18,
708 : GPR64commonRegClassID = 19,
709 : tcGPR64RegClassID = 20,
710 : rtcGPR64RegClassID = 21,
711 : GPR64sponlyRegClassID = 22,
712 : DDRegClassID = 23,
713 : XSeqPairsClassRegClassID = 24,
714 : XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 25,
715 : XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26,
716 : XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 27,
717 : XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 28,
718 : XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29,
719 : XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 30,
720 : XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID = 31,
721 : XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID = 32,
722 : XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID = 33,
723 : FPR128RegClassID = 34,
724 : ZPRRegClassID = 35,
725 : FPR128_loRegClassID = 36,
726 : ZPR_4bRegClassID = 37,
727 : ZPR_3bRegClassID = 38,
728 : DDDRegClassID = 39,
729 : DDDDRegClassID = 40,
730 : QQRegClassID = 41,
731 : ZPR2RegClassID = 42,
732 : QQ_with_qsub0_in_FPR128_loRegClassID = 43,
733 : QQ_with_qsub1_in_FPR128_loRegClassID = 44,
734 : ZPR2_with_zsub1_in_ZPR_4bRegClassID = 45,
735 : ZPR2_with_zsub_in_FPR128_loRegClassID = 46,
736 : QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 47,
737 : ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 48,
738 : ZPR2_with_zsub0_in_ZPR_3bRegClassID = 49,
739 : ZPR2_with_zsub1_in_ZPR_3bRegClassID = 50,
740 : ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 51,
741 : QQQRegClassID = 52,
742 : ZPR3RegClassID = 53,
743 : QQQ_with_qsub0_in_FPR128_loRegClassID = 54,
744 : QQQ_with_qsub1_in_FPR128_loRegClassID = 55,
745 : QQQ_with_qsub2_in_FPR128_loRegClassID = 56,
746 : ZPR3_with_zsub1_in_ZPR_4bRegClassID = 57,
747 : ZPR3_with_zsub2_in_ZPR_4bRegClassID = 58,
748 : ZPR3_with_zsub_in_FPR128_loRegClassID = 59,
749 : QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 60,
750 : QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 61,
751 : ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 62,
752 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 63,
753 : QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 64,
754 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 65,
755 : ZPR3_with_zsub0_in_ZPR_3bRegClassID = 66,
756 : ZPR3_with_zsub1_in_ZPR_3bRegClassID = 67,
757 : ZPR3_with_zsub2_in_ZPR_3bRegClassID = 68,
758 : ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 69,
759 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 70,
760 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 71,
761 : QQQQRegClassID = 72,
762 : ZPR4RegClassID = 73,
763 : QQQQ_with_qsub0_in_FPR128_loRegClassID = 74,
764 : QQQQ_with_qsub1_in_FPR128_loRegClassID = 75,
765 : QQQQ_with_qsub2_in_FPR128_loRegClassID = 76,
766 : QQQQ_with_qsub3_in_FPR128_loRegClassID = 77,
767 : ZPR4_with_zsub1_in_ZPR_4bRegClassID = 78,
768 : ZPR4_with_zsub2_in_ZPR_4bRegClassID = 79,
769 : ZPR4_with_zsub3_in_ZPR_4bRegClassID = 80,
770 : ZPR4_with_zsub_in_FPR128_loRegClassID = 81,
771 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 82,
772 : QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 83,
773 : QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 84,
774 : ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 85,
775 : ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 86,
776 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 87,
777 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 88,
778 : QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 89,
779 : ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 90,
780 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 91,
781 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 92,
782 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 93,
783 : ZPR4_with_zsub0_in_ZPR_3bRegClassID = 94,
784 : ZPR4_with_zsub1_in_ZPR_3bRegClassID = 95,
785 : ZPR4_with_zsub2_in_ZPR_3bRegClassID = 96,
786 : ZPR4_with_zsub3_in_ZPR_3bRegClassID = 97,
787 : ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 98,
788 : ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 99,
789 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 100,
790 : ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 101,
791 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 102,
792 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 103,
793 :
794 : };
795 : } // end namespace AArch64
796 :
797 :
798 : // Register alternate name indices
799 :
800 : namespace AArch64 {
801 : enum {
802 : NoRegAltName, // 0
803 : vlist1, // 1
804 : vreg, // 2
805 : NUM_TARGET_REG_ALT_NAMES = 3
806 : };
807 : } // end namespace AArch64
808 :
809 :
810 : // Subregister indices
811 :
812 : namespace AArch64 {
813 : enum {
814 : NoSubRegister,
815 : bsub, // 1
816 : dsub, // 2
817 : dsub0, // 3
818 : dsub1, // 4
819 : dsub2, // 5
820 : dsub3, // 6
821 : hsub, // 7
822 : qhisub, // 8
823 : qsub, // 9
824 : qsub0, // 10
825 : qsub1, // 11
826 : qsub2, // 12
827 : qsub3, // 13
828 : ssub, // 14
829 : sub_32, // 15
830 : sube32, // 16
831 : sube64, // 17
832 : subo32, // 18
833 : subo64, // 19
834 : zsub, // 20
835 : zsub0, // 21
836 : zsub1, // 22
837 : zsub2, // 23
838 : zsub3, // 24
839 : zsub_hi, // 25
840 : dsub1_then_bsub, // 26
841 : dsub1_then_hsub, // 27
842 : dsub1_then_ssub, // 28
843 : dsub3_then_bsub, // 29
844 : dsub3_then_hsub, // 30
845 : dsub3_then_ssub, // 31
846 : dsub2_then_bsub, // 32
847 : dsub2_then_hsub, // 33
848 : dsub2_then_ssub, // 34
849 : qsub1_then_bsub, // 35
850 : qsub1_then_dsub, // 36
851 : qsub1_then_hsub, // 37
852 : qsub1_then_ssub, // 38
853 : qsub3_then_bsub, // 39
854 : qsub3_then_dsub, // 40
855 : qsub3_then_hsub, // 41
856 : qsub3_then_ssub, // 42
857 : qsub2_then_bsub, // 43
858 : qsub2_then_dsub, // 44
859 : qsub2_then_hsub, // 45
860 : qsub2_then_ssub, // 46
861 : subo64_then_sub_32, // 47
862 : zsub1_then_bsub, // 48
863 : zsub1_then_dsub, // 49
864 : zsub1_then_hsub, // 50
865 : zsub1_then_ssub, // 51
866 : zsub1_then_zsub, // 52
867 : zsub1_then_zsub_hi, // 53
868 : zsub3_then_bsub, // 54
869 : zsub3_then_dsub, // 55
870 : zsub3_then_hsub, // 56
871 : zsub3_then_ssub, // 57
872 : zsub3_then_zsub, // 58
873 : zsub3_then_zsub_hi, // 59
874 : zsub2_then_bsub, // 60
875 : zsub2_then_dsub, // 61
876 : zsub2_then_hsub, // 62
877 : zsub2_then_ssub, // 63
878 : zsub2_then_zsub, // 64
879 : zsub2_then_zsub_hi, // 65
880 : dsub0_dsub1, // 66
881 : dsub0_dsub1_dsub2, // 67
882 : dsub1_dsub2, // 68
883 : dsub1_dsub2_dsub3, // 69
884 : dsub2_dsub3, // 70
885 : dsub_qsub1_then_dsub, // 71
886 : dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72
887 : dsub_qsub1_then_dsub_qsub2_then_dsub, // 73
888 : qsub0_qsub1, // 74
889 : qsub0_qsub1_qsub2, // 75
890 : qsub1_qsub2, // 76
891 : qsub1_qsub2_qsub3, // 77
892 : qsub2_qsub3, // 78
893 : qsub1_then_dsub_qsub2_then_dsub, // 79
894 : qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 80
895 : qsub2_then_dsub_qsub3_then_dsub, // 81
896 : sub_32_subo64_then_sub_32, // 82
897 : dsub_zsub1_then_dsub, // 83
898 : zsub_zsub1_then_zsub, // 84
899 : dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85
900 : dsub_zsub1_then_dsub_zsub2_then_dsub, // 86
901 : zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87
902 : zsub_zsub1_then_zsub_zsub2_then_zsub, // 88
903 : zsub0_zsub1, // 89
904 : zsub0_zsub1_zsub2, // 90
905 : zsub1_zsub2, // 91
906 : zsub1_zsub2_zsub3, // 92
907 : zsub2_zsub3, // 93
908 : zsub1_then_dsub_zsub2_then_dsub, // 94
909 : zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 95
910 : zsub1_then_zsub_zsub2_then_zsub, // 96
911 : zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 97
912 : zsub2_then_dsub_zsub3_then_dsub, // 98
913 : zsub2_then_zsub_zsub3_then_zsub, // 99
914 : NUM_TARGET_SUBREGS
915 : };
916 : } // end namespace AArch64
917 :
918 : } // end namespace llvm
919 :
920 : #endif // GET_REGINFO_ENUM
921 :
922 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
923 : |* *|
924 : |* MC Register Information *|
925 : |* *|
926 : |* Automatically generated file, do not edit! *|
927 : |* *|
928 : \*===----------------------------------------------------------------------===*/
929 :
930 :
931 : #ifdef GET_REGINFO_MC_DESC
932 : #undef GET_REGINFO_MC_DESC
933 :
934 : namespace llvm {
935 :
936 : extern const MCPhysReg AArch64RegDiffLists[] = {
937 : /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0,
938 : /* 9 */ 65105, 1, 1, 1, 0,
939 : /* 14 */ 65201, 1, 1, 1, 0,
940 : /* 19 */ 6, 29, 1, 1, 0,
941 : /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
942 : /* 33 */ 65324, 499, 30, 1, 1, 0,
943 : /* 39 */ 64913, 1, 1, 75, 1, 1, 0,
944 : /* 46 */ 65073, 1, 1, 0,
945 : /* 50 */ 65169, 1, 1, 0,
946 : /* 54 */ 6, 1, 29, 1, 0,
947 : /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
948 : /* 68 */ 6, 30, 1, 0,
949 : /* 72 */ 6, 30, 1, 46, 30, 1, 0,
950 : /* 79 */ 1, 493, 1, 32, 1, 0,
951 : /* 85 */ 31, 286, 1, 33, 1, 0,
952 : /* 91 */ 64977, 1, 76, 1, 0,
953 : /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
954 : /* 111 */ 320, 1, 0,
955 : /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
956 : /* 129 */ 526, 1, 0,
957 : /* 132 */ 530, 1, 0,
958 : /* 135 */ 65053, 1, 0,
959 : /* 138 */ 65087, 1, 0,
960 : /* 141 */ 65137, 1, 0,
961 : /* 144 */ 65218, 1, 0,
962 : /* 147 */ 65233, 1, 0,
963 : /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
964 : /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
965 : /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
966 : /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
967 : /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
968 : /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
969 : /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0,
970 : /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
971 : /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
972 : /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
973 : /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0,
974 : /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0,
975 : /* 387 */ 31, 285, 2, 32, 2, 0,
976 : /* 393 */ 319, 2, 0,
977 : /* 396 */ 65324, 529, 1, 1, 3, 0,
978 : /* 402 */ 2, 3, 0,
979 : /* 405 */ 531, 3, 0,
980 : /* 408 */ 65004, 3, 0,
981 : /* 411 */ 4, 0,
982 : /* 413 */ 5, 0,
983 : /* 415 */ 31, 286, 1, 5, 28, 0,
984 : /* 421 */ 292, 28, 0,
985 : /* 424 */ 6, 1, 1, 29, 0,
986 : /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
987 : /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
988 : /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
989 : /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
990 : /* 502 */ 6, 1, 30, 0,
991 : /* 506 */ 6, 1, 30, 46, 1, 30, 0,
992 : /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0,
993 : /* 531 */ 6, 31, 0,
994 : /* 534 */ 6, 31, 46, 31, 0,
995 : /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0,
996 : /* 548 */ 32, 0,
997 : /* 550 */ 34, 0,
998 : /* 552 */ 5, 49, 0,
999 : /* 555 */ 63936, 49, 0,
1000 : /* 558 */ 65297, 77, 0,
1001 : /* 561 */ 1, 81, 0,
1002 : /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
1003 : /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
1004 : /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0,
1005 : /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0,
1006 : /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0,
1007 : /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0,
1008 : /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1009 : /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1010 : /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
1011 : /* 872 */ 96, 160, 0,
1012 : /* 875 */ 65042, 178, 0,
1013 : /* 878 */ 212, 0,
1014 : /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0,
1015 : /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
1016 : /* 899 */ 65009, 65535, 209, 65505, 316, 0,
1017 : /* 905 */ 65005, 212, 65325, 212, 317, 0,
1018 : /* 911 */ 65244, 65505, 65325, 212, 317, 0,
1019 : /* 917 */ 65215, 65505, 32, 65505, 317, 0,
1020 : /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
1021 : /* 935 */ 65005, 212, 65329, 65535, 495, 0,
1022 : /* 941 */ 65323, 0,
1023 : /* 943 */ 65249, 65328, 0,
1024 : /* 946 */ 65342, 0,
1025 : /* 948 */ 65374, 0,
1026 : /* 950 */ 65389, 0,
1027 : /* 952 */ 65405, 0,
1028 : /* 954 */ 65421, 0,
1029 : /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
1030 : /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
1031 : /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
1032 : /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
1033 : /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
1034 : /* 1073 */ 65469, 0,
1035 : /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
1036 : /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
1037 : /* 1093 */ 65456, 112, 65456, 65472, 0,
1038 : /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
1039 : /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1040 : /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1041 : /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
1042 : /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
1043 : /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
1044 : /* 1260 */ 65501, 0,
1045 : /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
1046 : /* 1277 */ 65533, 0,
1047 : /* 1279 */ 65535, 0,
1048 : };
1049 :
1050 : extern const LaneBitmask AArch64LaneMaskLists[] = {
1051 : /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
1052 : /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1053 : /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1054 : /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1055 : /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1056 : /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1057 : /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1058 : /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
1059 : /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
1060 : /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
1061 : /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1062 : /* 38 */ LaneBitmask(0x00004000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1063 : /* 43 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1064 : /* 52 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1065 : /* 59 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1066 : /* 64 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1067 : /* 68 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
1068 : /* 73 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
1069 : /* 78 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1070 : /* 83 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1071 : /* 87 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
1072 : /* 92 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
1073 : /* 97 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
1074 : /* 100 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1075 : /* 105 */ LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1076 : /* 114 */ LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1077 : /* 121 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
1078 : /* 130 */ LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1079 : /* 139 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1080 : };
1081 :
1082 : extern const uint16_t AArch64SubRegIdxLists[] = {
1083 : /* 0 */ 2, 14, 7, 1, 0,
1084 : /* 5 */ 15, 0,
1085 : /* 7 */ 16, 18, 0,
1086 : /* 10 */ 20, 2, 14, 7, 1, 25, 0,
1087 : /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
1088 : /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
1089 : /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
1090 : /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
1091 : /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
1092 : /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
1093 : /* 128 */ 17, 15, 19, 47, 82, 0,
1094 : /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
1095 : /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
1096 : /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
1097 : };
1098 :
1099 : extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
1100 : { 65535, 65535 },
1101 : { 0, 8 }, // bsub
1102 : { 0, 32 }, // dsub
1103 : { 0, 64 }, // dsub0
1104 : { 0, 64 }, // dsub1
1105 : { 0, 64 }, // dsub2
1106 : { 0, 64 }, // dsub3
1107 : { 0, 16 }, // hsub
1108 : { 0, 64 }, // qhisub
1109 : { 0, 64 }, // qsub
1110 : { 0, 128 }, // qsub0
1111 : { 0, 128 }, // qsub1
1112 : { 0, 128 }, // qsub2
1113 : { 0, 128 }, // qsub3
1114 : { 0, 32 }, // ssub
1115 : { 0, 32 }, // sub_32
1116 : { 0, 32 }, // sube32
1117 : { 0, 64 }, // sube64
1118 : { 0, 32 }, // subo32
1119 : { 0, 64 }, // subo64
1120 : { 0, 128 }, // zsub
1121 : { 65535, 128 }, // zsub0
1122 : { 65535, 128 }, // zsub1
1123 : { 65535, 128 }, // zsub2
1124 : { 65535, 128 }, // zsub3
1125 : { 0, 128 }, // zsub_hi
1126 : { 0, 8 }, // dsub1_then_bsub
1127 : { 0, 16 }, // dsub1_then_hsub
1128 : { 0, 32 }, // dsub1_then_ssub
1129 : { 0, 8 }, // dsub3_then_bsub
1130 : { 0, 16 }, // dsub3_then_hsub
1131 : { 0, 32 }, // dsub3_then_ssub
1132 : { 0, 8 }, // dsub2_then_bsub
1133 : { 0, 16 }, // dsub2_then_hsub
1134 : { 0, 32 }, // dsub2_then_ssub
1135 : { 0, 8 }, // qsub1_then_bsub
1136 : { 0, 32 }, // qsub1_then_dsub
1137 : { 0, 16 }, // qsub1_then_hsub
1138 : { 0, 32 }, // qsub1_then_ssub
1139 : { 0, 8 }, // qsub3_then_bsub
1140 : { 0, 32 }, // qsub3_then_dsub
1141 : { 0, 16 }, // qsub3_then_hsub
1142 : { 0, 32 }, // qsub3_then_ssub
1143 : { 0, 8 }, // qsub2_then_bsub
1144 : { 0, 32 }, // qsub2_then_dsub
1145 : { 0, 16 }, // qsub2_then_hsub
1146 : { 0, 32 }, // qsub2_then_ssub
1147 : { 0, 32 }, // subo64_then_sub_32
1148 : { 65535, 65535 }, // zsub1_then_bsub
1149 : { 65535, 65535 }, // zsub1_then_dsub
1150 : { 65535, 65535 }, // zsub1_then_hsub
1151 : { 65535, 65535 }, // zsub1_then_ssub
1152 : { 65535, 65535 }, // zsub1_then_zsub
1153 : { 65535, 65535 }, // zsub1_then_zsub_hi
1154 : { 65535, 65535 }, // zsub3_then_bsub
1155 : { 65535, 65535 }, // zsub3_then_dsub
1156 : { 65535, 65535 }, // zsub3_then_hsub
1157 : { 65535, 65535 }, // zsub3_then_ssub
1158 : { 65535, 65535 }, // zsub3_then_zsub
1159 : { 65535, 65535 }, // zsub3_then_zsub_hi
1160 : { 65535, 65535 }, // zsub2_then_bsub
1161 : { 65535, 65535 }, // zsub2_then_dsub
1162 : { 65535, 65535 }, // zsub2_then_hsub
1163 : { 65535, 65535 }, // zsub2_then_ssub
1164 : { 65535, 65535 }, // zsub2_then_zsub
1165 : { 65535, 65535 }, // zsub2_then_zsub_hi
1166 : { 65535, 128 }, // dsub0_dsub1
1167 : { 65535, 192 }, // dsub0_dsub1_dsub2
1168 : { 65535, 128 }, // dsub1_dsub2
1169 : { 65535, 192 }, // dsub1_dsub2_dsub3
1170 : { 65535, 128 }, // dsub2_dsub3
1171 : { 65535, 64 }, // dsub_qsub1_then_dsub
1172 : { 65535, 128 }, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1173 : { 65535, 96 }, // dsub_qsub1_then_dsub_qsub2_then_dsub
1174 : { 65535, 256 }, // qsub0_qsub1
1175 : { 65535, 384 }, // qsub0_qsub1_qsub2
1176 : { 65535, 256 }, // qsub1_qsub2
1177 : { 65535, 384 }, // qsub1_qsub2_qsub3
1178 : { 65535, 256 }, // qsub2_qsub3
1179 : { 65535, 64 }, // qsub1_then_dsub_qsub2_then_dsub
1180 : { 65535, 96 }, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1181 : { 65535, 64 }, // qsub2_then_dsub_qsub3_then_dsub
1182 : { 65535, 64 }, // sub_32_subo64_then_sub_32
1183 : { 65535, 31 }, // dsub_zsub1_then_dsub
1184 : { 65535, 127 }, // zsub_zsub1_then_zsub
1185 : { 65535, 29 }, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1186 : { 65535, 30 }, // dsub_zsub1_then_dsub_zsub2_then_dsub
1187 : { 65535, 125 }, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1188 : { 65535, 126 }, // zsub_zsub1_then_zsub_zsub2_then_zsub
1189 : { 65535, 256 }, // zsub0_zsub1
1190 : { 65535, 384 }, // zsub0_zsub1_zsub2
1191 : { 65535, 256 }, // zsub1_zsub2
1192 : { 65535, 384 }, // zsub1_zsub2_zsub3
1193 : { 65535, 256 }, // zsub2_zsub3
1194 : { 65535, 65534 }, // zsub1_then_dsub_zsub2_then_dsub
1195 : { 65535, 65533 }, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1196 : { 65535, 65534 }, // zsub1_then_zsub_zsub2_then_zsub
1197 : { 65535, 65533 }, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1198 : { 65535, 65534 }, // zsub2_then_dsub_zsub3_then_dsub
1199 : { 65535, 65534 }, // zsub2_then_zsub_zsub3_then_zsub
1200 : };
1201 :
1202 : extern const char AArch64RegStrings[] = {
1203 : /* 0 */ 'B', '1', '0', 0,
1204 : /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1205 : /* 17 */ 'H', '1', '0', 0,
1206 : /* 21 */ 'P', '1', '0', 0,
1207 : /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1208 : /* 38 */ 'S', '1', '0', 0,
1209 : /* 42 */ 'W', '9', '_', 'W', '1', '0', 0,
1210 : /* 49 */ 'X', '9', '_', 'X', '1', '0', 0,
1211 : /* 56 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
1212 : /* 69 */ 'B', '2', '0', 0,
1213 : /* 73 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1214 : /* 89 */ 'H', '2', '0', 0,
1215 : /* 93 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
1216 : /* 109 */ 'S', '2', '0', 0,
1217 : /* 113 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
1218 : /* 121 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
1219 : /* 129 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
1220 : /* 145 */ 'B', '3', '0', 0,
1221 : /* 149 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1222 : /* 165 */ 'H', '3', '0', 0,
1223 : /* 169 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
1224 : /* 185 */ 'S', '3', '0', 0,
1225 : /* 189 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
1226 : /* 197 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
1227 : /* 213 */ 'B', '0', 0,
1228 : /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
1229 : /* 231 */ 'H', '0', 0,
1230 : /* 234 */ 'P', '0', 0,
1231 : /* 237 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
1232 : /* 252 */ 'S', '0', 0,
1233 : /* 255 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
1234 : /* 262 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
1235 : /* 269 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
1236 : /* 284 */ 'B', '1', '1', 0,
1237 : /* 288 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1238 : /* 302 */ 'H', '1', '1', 0,
1239 : /* 306 */ 'P', '1', '1', 0,
1240 : /* 310 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1241 : /* 324 */ 'S', '1', '1', 0,
1242 : /* 328 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
1243 : /* 336 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
1244 : /* 344 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
1245 : /* 358 */ 'B', '2', '1', 0,
1246 : /* 362 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1247 : /* 378 */ 'H', '2', '1', 0,
1248 : /* 382 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
1249 : /* 398 */ 'S', '2', '1', 0,
1250 : /* 402 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
1251 : /* 410 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
1252 : /* 418 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
1253 : /* 434 */ 'B', '3', '1', 0,
1254 : /* 438 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1255 : /* 454 */ 'H', '3', '1', 0,
1256 : /* 458 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
1257 : /* 474 */ 'S', '3', '1', 0,
1258 : /* 478 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
1259 : /* 494 */ 'B', '1', 0,
1260 : /* 497 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
1261 : /* 511 */ 'H', '1', 0,
1262 : /* 514 */ 'P', '1', 0,
1263 : /* 517 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
1264 : /* 531 */ 'S', '1', 0,
1265 : /* 534 */ 'W', '0', '_', 'W', '1', 0,
1266 : /* 540 */ 'X', '0', '_', 'X', '1', 0,
1267 : /* 546 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
1268 : /* 560 */ 'B', '1', '2', 0,
1269 : /* 564 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1270 : /* 579 */ 'H', '1', '2', 0,
1271 : /* 583 */ 'P', '1', '2', 0,
1272 : /* 587 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1273 : /* 602 */ 'S', '1', '2', 0,
1274 : /* 606 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
1275 : /* 614 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
1276 : /* 622 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
1277 : /* 637 */ 'B', '2', '2', 0,
1278 : /* 641 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1279 : /* 657 */ 'H', '2', '2', 0,
1280 : /* 661 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
1281 : /* 677 */ 'S', '2', '2', 0,
1282 : /* 681 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
1283 : /* 689 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
1284 : /* 697 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
1285 : /* 713 */ 'B', '2', 0,
1286 : /* 716 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1287 : /* 729 */ 'H', '2', 0,
1288 : /* 732 */ 'P', '2', 0,
1289 : /* 735 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
1290 : /* 748 */ 'S', '2', 0,
1291 : /* 751 */ 'W', '1', '_', 'W', '2', 0,
1292 : /* 757 */ 'X', '1', '_', 'X', '2', 0,
1293 : /* 763 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
1294 : /* 776 */ 'B', '1', '3', 0,
1295 : /* 780 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1296 : /* 796 */ 'H', '1', '3', 0,
1297 : /* 800 */ 'P', '1', '3', 0,
1298 : /* 804 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1299 : /* 820 */ 'S', '1', '3', 0,
1300 : /* 824 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
1301 : /* 832 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
1302 : /* 840 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
1303 : /* 856 */ 'B', '2', '3', 0,
1304 : /* 860 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1305 : /* 876 */ 'H', '2', '3', 0,
1306 : /* 880 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
1307 : /* 896 */ 'S', '2', '3', 0,
1308 : /* 900 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
1309 : /* 908 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
1310 : /* 916 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
1311 : /* 932 */ 'B', '3', 0,
1312 : /* 935 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1313 : /* 947 */ 'H', '3', 0,
1314 : /* 950 */ 'P', '3', 0,
1315 : /* 953 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1316 : /* 965 */ 'S', '3', 0,
1317 : /* 968 */ 'W', '2', '_', 'W', '3', 0,
1318 : /* 974 */ 'X', '2', '_', 'X', '3', 0,
1319 : /* 980 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
1320 : /* 992 */ 'B', '1', '4', 0,
1321 : /* 996 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1322 : /* 1012 */ 'H', '1', '4', 0,
1323 : /* 1016 */ 'P', '1', '4', 0,
1324 : /* 1020 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1325 : /* 1036 */ 'S', '1', '4', 0,
1326 : /* 1040 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
1327 : /* 1048 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
1328 : /* 1056 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
1329 : /* 1072 */ 'B', '2', '4', 0,
1330 : /* 1076 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1331 : /* 1092 */ 'H', '2', '4', 0,
1332 : /* 1096 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
1333 : /* 1112 */ 'S', '2', '4', 0,
1334 : /* 1116 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
1335 : /* 1124 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
1336 : /* 1132 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
1337 : /* 1148 */ 'B', '4', 0,
1338 : /* 1151 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1339 : /* 1163 */ 'H', '4', 0,
1340 : /* 1166 */ 'P', '4', 0,
1341 : /* 1169 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1342 : /* 1181 */ 'S', '4', 0,
1343 : /* 1184 */ 'W', '3', '_', 'W', '4', 0,
1344 : /* 1190 */ 'X', '3', '_', 'X', '4', 0,
1345 : /* 1196 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
1346 : /* 1208 */ 'B', '1', '5', 0,
1347 : /* 1212 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1348 : /* 1228 */ 'H', '1', '5', 0,
1349 : /* 1232 */ 'P', '1', '5', 0,
1350 : /* 1236 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1351 : /* 1252 */ 'S', '1', '5', 0,
1352 : /* 1256 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
1353 : /* 1264 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
1354 : /* 1272 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
1355 : /* 1288 */ 'B', '2', '5', 0,
1356 : /* 1292 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1357 : /* 1308 */ 'H', '2', '5', 0,
1358 : /* 1312 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
1359 : /* 1328 */ 'S', '2', '5', 0,
1360 : /* 1332 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
1361 : /* 1340 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
1362 : /* 1348 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
1363 : /* 1364 */ 'B', '5', 0,
1364 : /* 1367 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1365 : /* 1379 */ 'H', '5', 0,
1366 : /* 1382 */ 'P', '5', 0,
1367 : /* 1385 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1368 : /* 1397 */ 'S', '5', 0,
1369 : /* 1400 */ 'W', '4', '_', 'W', '5', 0,
1370 : /* 1406 */ 'X', '4', '_', 'X', '5', 0,
1371 : /* 1412 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
1372 : /* 1424 */ 'B', '1', '6', 0,
1373 : /* 1428 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1374 : /* 1444 */ 'H', '1', '6', 0,
1375 : /* 1448 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
1376 : /* 1464 */ 'S', '1', '6', 0,
1377 : /* 1468 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
1378 : /* 1476 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
1379 : /* 1484 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
1380 : /* 1500 */ 'B', '2', '6', 0,
1381 : /* 1504 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1382 : /* 1520 */ 'H', '2', '6', 0,
1383 : /* 1524 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
1384 : /* 1540 */ 'S', '2', '6', 0,
1385 : /* 1544 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
1386 : /* 1552 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
1387 : /* 1560 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
1388 : /* 1576 */ 'B', '6', 0,
1389 : /* 1579 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1390 : /* 1591 */ 'H', '6', 0,
1391 : /* 1594 */ 'P', '6', 0,
1392 : /* 1597 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1393 : /* 1609 */ 'S', '6', 0,
1394 : /* 1612 */ 'W', '5', '_', 'W', '6', 0,
1395 : /* 1618 */ 'X', '5', '_', 'X', '6', 0,
1396 : /* 1624 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
1397 : /* 1636 */ 'B', '1', '7', 0,
1398 : /* 1640 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1399 : /* 1656 */ 'H', '1', '7', 0,
1400 : /* 1660 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
1401 : /* 1676 */ 'S', '1', '7', 0,
1402 : /* 1680 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
1403 : /* 1688 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
1404 : /* 1696 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
1405 : /* 1712 */ 'B', '2', '7', 0,
1406 : /* 1716 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1407 : /* 1732 */ 'H', '2', '7', 0,
1408 : /* 1736 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
1409 : /* 1752 */ 'S', '2', '7', 0,
1410 : /* 1756 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
1411 : /* 1764 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
1412 : /* 1772 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
1413 : /* 1788 */ 'B', '7', 0,
1414 : /* 1791 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1415 : /* 1803 */ 'H', '7', 0,
1416 : /* 1806 */ 'P', '7', 0,
1417 : /* 1809 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1418 : /* 1821 */ 'S', '7', 0,
1419 : /* 1824 */ 'W', '6', '_', 'W', '7', 0,
1420 : /* 1830 */ 'X', '6', '_', 'X', '7', 0,
1421 : /* 1836 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
1422 : /* 1848 */ 'B', '1', '8', 0,
1423 : /* 1852 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1424 : /* 1868 */ 'H', '1', '8', 0,
1425 : /* 1872 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
1426 : /* 1888 */ 'S', '1', '8', 0,
1427 : /* 1892 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
1428 : /* 1900 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
1429 : /* 1908 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
1430 : /* 1924 */ 'B', '2', '8', 0,
1431 : /* 1928 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1432 : /* 1944 */ 'H', '2', '8', 0,
1433 : /* 1948 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
1434 : /* 1964 */ 'S', '2', '8', 0,
1435 : /* 1968 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
1436 : /* 1976 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
1437 : /* 1984 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
1438 : /* 2000 */ 'B', '8', 0,
1439 : /* 2003 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1440 : /* 2015 */ 'H', '8', 0,
1441 : /* 2018 */ 'P', '8', 0,
1442 : /* 2021 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1443 : /* 2033 */ 'S', '8', 0,
1444 : /* 2036 */ 'W', '7', '_', 'W', '8', 0,
1445 : /* 2042 */ 'X', '7', '_', 'X', '8', 0,
1446 : /* 2048 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
1447 : /* 2060 */ 'B', '1', '9', 0,
1448 : /* 2064 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1449 : /* 2080 */ 'H', '1', '9', 0,
1450 : /* 2084 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
1451 : /* 2100 */ 'S', '1', '9', 0,
1452 : /* 2104 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
1453 : /* 2112 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
1454 : /* 2120 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
1455 : /* 2136 */ 'B', '2', '9', 0,
1456 : /* 2140 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1457 : /* 2156 */ 'H', '2', '9', 0,
1458 : /* 2160 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
1459 : /* 2176 */ 'S', '2', '9', 0,
1460 : /* 2180 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
1461 : /* 2188 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
1462 : /* 2204 */ 'B', '9', 0,
1463 : /* 2207 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1464 : /* 2219 */ 'H', '9', 0,
1465 : /* 2222 */ 'P', '9', 0,
1466 : /* 2225 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1467 : /* 2237 */ 'S', '9', 0,
1468 : /* 2240 */ 'W', '8', '_', 'W', '9', 0,
1469 : /* 2246 */ 'X', '8', '_', 'X', '9', 0,
1470 : /* 2252 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
1471 : /* 2264 */ 'Z', '1', '0', '_', 'H', 'I', 0,
1472 : /* 2271 */ 'Z', '2', '0', '_', 'H', 'I', 0,
1473 : /* 2278 */ 'Z', '3', '0', '_', 'H', 'I', 0,
1474 : /* 2285 */ 'Z', '0', '_', 'H', 'I', 0,
1475 : /* 2291 */ 'Z', '1', '1', '_', 'H', 'I', 0,
1476 : /* 2298 */ 'Z', '2', '1', '_', 'H', 'I', 0,
1477 : /* 2305 */ 'Z', '3', '1', '_', 'H', 'I', 0,
1478 : /* 2312 */ 'Z', '1', '_', 'H', 'I', 0,
1479 : /* 2318 */ 'Z', '1', '2', '_', 'H', 'I', 0,
1480 : /* 2325 */ 'Z', '2', '2', '_', 'H', 'I', 0,
1481 : /* 2332 */ 'Z', '2', '_', 'H', 'I', 0,
1482 : /* 2338 */ 'Z', '1', '3', '_', 'H', 'I', 0,
1483 : /* 2345 */ 'Z', '2', '3', '_', 'H', 'I', 0,
1484 : /* 2352 */ 'Z', '3', '_', 'H', 'I', 0,
1485 : /* 2358 */ 'Z', '1', '4', '_', 'H', 'I', 0,
1486 : /* 2365 */ 'Z', '2', '4', '_', 'H', 'I', 0,
1487 : /* 2372 */ 'Z', '4', '_', 'H', 'I', 0,
1488 : /* 2378 */ 'Z', '1', '5', '_', 'H', 'I', 0,
1489 : /* 2385 */ 'Z', '2', '5', '_', 'H', 'I', 0,
1490 : /* 2392 */ 'Z', '5', '_', 'H', 'I', 0,
1491 : /* 2398 */ 'Z', '1', '6', '_', 'H', 'I', 0,
1492 : /* 2405 */ 'Z', '2', '6', '_', 'H', 'I', 0,
1493 : /* 2412 */ 'Z', '6', '_', 'H', 'I', 0,
1494 : /* 2418 */ 'Z', '1', '7', '_', 'H', 'I', 0,
1495 : /* 2425 */ 'Z', '2', '7', '_', 'H', 'I', 0,
1496 : /* 2432 */ 'Z', '7', '_', 'H', 'I', 0,
1497 : /* 2438 */ 'Z', '1', '8', '_', 'H', 'I', 0,
1498 : /* 2445 */ 'Z', '2', '8', '_', 'H', 'I', 0,
1499 : /* 2452 */ 'Z', '8', '_', 'H', 'I', 0,
1500 : /* 2458 */ 'Z', '1', '9', '_', 'H', 'I', 0,
1501 : /* 2465 */ 'Z', '2', '9', '_', 'H', 'I', 0,
1502 : /* 2472 */ 'Z', '9', '_', 'H', 'I', 0,
1503 : /* 2478 */ 'X', '2', '8', '_', 'F', 'P', 0,
1504 : /* 2485 */ 'W', 'S', 'P', 0,
1505 : /* 2489 */ 'F', 'F', 'R', 0,
1506 : /* 2493 */ 'F', 'P', '_', 'L', 'R', 0,
1507 : /* 2499 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
1508 : /* 2507 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
1509 : /* 2514 */ 'N', 'Z', 'C', 'V', 0,
1510 : };
1511 :
1512 : extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
1513 : { 3, 0, 0, 0, 0, 0 },
1514 : { 2489, 8, 8, 4, 20465, 0 },
1515 : { 2482, 878, 405, 5, 20465, 27 },
1516 : { 2496, 878, 132, 5, 20465, 27 },
1517 : { 2514, 8, 8, 4, 20465, 0 },
1518 : { 2486, 7, 8, 5, 6576, 27 },
1519 : { 2485, 8, 1279, 4, 6576, 0 },
1520 : { 2503, 8, 79, 4, 6608, 0 },
1521 : { 2510, 1279, 129, 5, 6608, 27 },
1522 : { 213, 8, 214, 4, 20433, 0 },
1523 : { 494, 8, 296, 4, 20433, 0 },
1524 : { 713, 8, 438, 4, 20433, 0 },
1525 : { 932, 8, 150, 4, 20433, 0 },
1526 : { 1148, 8, 150, 4, 20433, 0 },
1527 : { 1364, 8, 150, 4, 20433, 0 },
1528 : { 1576, 8, 150, 4, 20433, 0 },
1529 : { 1788, 8, 150, 4, 20433, 0 },
1530 : { 2000, 8, 150, 4, 20433, 0 },
1531 : { 2204, 8, 150, 4, 20433, 0 },
1532 : { 0, 8, 150, 4, 20433, 0 },
1533 : { 284, 8, 150, 4, 20433, 0 },
1534 : { 560, 8, 150, 4, 20433, 0 },
1535 : { 776, 8, 150, 4, 20433, 0 },
1536 : { 992, 8, 150, 4, 20433, 0 },
1537 : { 1208, 8, 150, 4, 20433, 0 },
1538 : { 1424, 8, 150, 4, 20433, 0 },
1539 : { 1636, 8, 150, 4, 20433, 0 },
1540 : { 1848, 8, 150, 4, 20433, 0 },
1541 : { 2060, 8, 150, 4, 20433, 0 },
1542 : { 69, 8, 150, 4, 20433, 0 },
1543 : { 358, 8, 150, 4, 20433, 0 },
1544 : { 637, 8, 150, 4, 20433, 0 },
1545 : { 856, 8, 150, 4, 20433, 0 },
1546 : { 1072, 8, 150, 4, 20433, 0 },
1547 : { 1288, 8, 150, 4, 20433, 0 },
1548 : { 1500, 8, 150, 4, 20433, 0 },
1549 : { 1712, 8, 150, 4, 20433, 0 },
1550 : { 1924, 8, 150, 4, 20433, 0 },
1551 : { 2136, 8, 150, 4, 20433, 0 },
1552 : { 145, 8, 150, 4, 20433, 0 },
1553 : { 434, 8, 150, 4, 20433, 0 },
1554 : { 228, 1080, 217, 1, 20161, 3 },
1555 : { 508, 1080, 299, 1, 20161, 3 },
1556 : { 726, 1080, 441, 1, 20161, 3 },
1557 : { 944, 1080, 153, 1, 20161, 3 },
1558 : { 1160, 1080, 153, 1, 20161, 3 },
1559 : { 1376, 1080, 153, 1, 20161, 3 },
1560 : { 1588, 1080, 153, 1, 20161, 3 },
1561 : { 1800, 1080, 153, 1, 20161, 3 },
1562 : { 2012, 1080, 153, 1, 20161, 3 },
1563 : { 2216, 1080, 153, 1, 20161, 3 },
1564 : { 13, 1080, 153, 1, 20161, 3 },
1565 : { 298, 1080, 153, 1, 20161, 3 },
1566 : { 575, 1080, 153, 1, 20161, 3 },
1567 : { 792, 1080, 153, 1, 20161, 3 },
1568 : { 1008, 1080, 153, 1, 20161, 3 },
1569 : { 1224, 1080, 153, 1, 20161, 3 },
1570 : { 1440, 1080, 153, 1, 20161, 3 },
1571 : { 1652, 1080, 153, 1, 20161, 3 },
1572 : { 1864, 1080, 153, 1, 20161, 3 },
1573 : { 2076, 1080, 153, 1, 20161, 3 },
1574 : { 85, 1080, 153, 1, 20161, 3 },
1575 : { 374, 1080, 153, 1, 20161, 3 },
1576 : { 653, 1080, 153, 1, 20161, 3 },
1577 : { 872, 1080, 153, 1, 20161, 3 },
1578 : { 1088, 1080, 153, 1, 20161, 3 },
1579 : { 1304, 1080, 153, 1, 20161, 3 },
1580 : { 1516, 1080, 153, 1, 20161, 3 },
1581 : { 1728, 1080, 153, 1, 20161, 3 },
1582 : { 1940, 1080, 153, 1, 20161, 3 },
1583 : { 2152, 1080, 153, 1, 20161, 3 },
1584 : { 161, 1080, 153, 1, 20161, 3 },
1585 : { 450, 1080, 153, 1, 20161, 3 },
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1988 : { 2024, 956, 381, 75, 737, 93 },
1989 : { 2228, 956, 381, 75, 737, 93 },
1990 : { 28, 956, 381, 75, 737, 93 },
1991 : { 313, 956, 381, 75, 737, 93 },
1992 : { 590, 956, 381, 75, 737, 93 },
1993 : { 808, 956, 381, 75, 737, 93 },
1994 : { 1024, 956, 381, 75, 737, 93 },
1995 : { 1240, 956, 381, 75, 737, 93 },
1996 : { 1452, 956, 381, 75, 737, 93 },
1997 : { 1664, 956, 381, 75, 737, 93 },
1998 : { 1876, 956, 381, 75, 737, 93 },
1999 : { 2088, 956, 381, 75, 737, 93 },
2000 : { 97, 956, 381, 75, 737, 93 },
2001 : { 386, 956, 381, 75, 737, 93 },
2002 : { 665, 956, 381, 75, 737, 93 },
2003 : { 884, 956, 381, 75, 737, 93 },
2004 : { 1100, 956, 381, 75, 737, 93 },
2005 : { 1316, 956, 381, 75, 737, 93 },
2006 : { 1528, 956, 381, 75, 737, 93 },
2007 : { 1740, 956, 381, 75, 737, 93 },
2008 : { 1952, 956, 381, 75, 737, 93 },
2009 : { 2164, 956, 381, 75, 737, 93 },
2010 : { 173, 956, 381, 75, 737, 93 },
2011 : { 462, 956, 381, 75, 737, 93 },
2012 : { 241, 977, 381, 75, 1088, 83 },
2013 : { 521, 998, 381, 75, 8032, 22 },
2014 : { 255, 875, 550, 7, 8832, 32 },
2015 : { 2499, 943, 548, 7, 6432, 32 },
2016 : { 534, 144, 550, 7, 2209, 32 },
2017 : { 751, 144, 550, 7, 2209, 32 },
2018 : { 968, 144, 550, 7, 2209, 32 },
2019 : { 1184, 144, 550, 7, 2209, 32 },
2020 : { 1400, 144, 550, 7, 2209, 32 },
2021 : { 1612, 144, 550, 7, 2209, 32 },
2022 : { 1824, 144, 550, 7, 2209, 32 },
2023 : { 2036, 144, 550, 7, 2209, 32 },
2024 : { 2240, 144, 550, 7, 2209, 32 },
2025 : { 42, 144, 550, 7, 2209, 32 },
2026 : { 328, 144, 550, 7, 2209, 32 },
2027 : { 606, 144, 550, 7, 2209, 32 },
2028 : { 824, 144, 550, 7, 2209, 32 },
2029 : { 1040, 144, 550, 7, 2209, 32 },
2030 : { 1256, 144, 550, 7, 2209, 32 },
2031 : { 1468, 144, 550, 7, 2209, 32 },
2032 : { 1680, 144, 550, 7, 2209, 32 },
2033 : { 1892, 144, 550, 7, 2209, 32 },
2034 : { 2104, 144, 550, 7, 2209, 32 },
2035 : { 113, 144, 550, 7, 2209, 32 },
2036 : { 402, 144, 550, 7, 2209, 32 },
2037 : { 681, 144, 550, 7, 2209, 32 },
2038 : { 900, 144, 550, 7, 2209, 32 },
2039 : { 1116, 144, 550, 7, 2209, 32 },
2040 : { 1332, 144, 550, 7, 2209, 32 },
2041 : { 1544, 144, 550, 7, 2209, 32 },
2042 : { 1756, 144, 550, 7, 2209, 32 },
2043 : { 1968, 144, 550, 7, 2209, 32 },
2044 : { 2180, 144, 413, 7, 8976, 29 },
2045 : { 189, 144, 7, 7, 96, 32 },
2046 : { 2493, 905, 8, 128, 96, 97 },
2047 : { 2507, 935, 8, 128, 6529, 97 },
2048 : { 262, 899, 8, 128, 8883, 97 },
2049 : { 2478, 911, 8, 128, 8976, 26 },
2050 : { 540, 917, 8, 128, 2161, 97 },
2051 : { 757, 917, 8, 128, 2161, 97 },
2052 : { 974, 917, 8, 128, 2161, 97 },
2053 : { 1190, 917, 8, 128, 2161, 97 },
2054 : { 1406, 917, 8, 128, 2161, 97 },
2055 : { 1618, 917, 8, 128, 2161, 97 },
2056 : { 1830, 917, 8, 128, 2161, 97 },
2057 : { 2042, 917, 8, 128, 2161, 97 },
2058 : { 2246, 917, 8, 128, 2161, 97 },
2059 : { 49, 917, 8, 128, 2161, 97 },
2060 : { 336, 917, 8, 128, 2161, 97 },
2061 : { 614, 917, 8, 128, 2161, 97 },
2062 : { 832, 917, 8, 128, 2161, 97 },
2063 : { 1048, 917, 8, 128, 2161, 97 },
2064 : { 1264, 917, 8, 128, 2161, 97 },
2065 : { 1476, 917, 8, 128, 2161, 97 },
2066 : { 1688, 917, 8, 128, 2161, 97 },
2067 : { 1900, 917, 8, 128, 2161, 97 },
2068 : { 2112, 917, 8, 128, 2161, 97 },
2069 : { 121, 917, 8, 128, 2161, 97 },
2070 : { 410, 917, 8, 128, 2161, 97 },
2071 : { 689, 917, 8, 128, 2161, 97 },
2072 : { 908, 917, 8, 128, 2161, 97 },
2073 : { 1124, 917, 8, 128, 2161, 97 },
2074 : { 1340, 917, 8, 128, 2161, 97 },
2075 : { 1552, 917, 8, 128, 2161, 97 },
2076 : { 1764, 917, 8, 128, 2161, 97 },
2077 : { 1976, 917, 8, 128, 2161, 97 },
2078 : { 554, 564, 372, 134, 1457, 100 },
2079 : { 770, 564, 525, 134, 1457, 100 },
2080 : { 986, 564, 290, 134, 1457, 100 },
2081 : { 1202, 564, 290, 134, 1457, 100 },
2082 : { 1418, 564, 290, 134, 1457, 100 },
2083 : { 1630, 564, 290, 134, 1457, 100 },
2084 : { 1842, 564, 290, 134, 1457, 100 },
2085 : { 2054, 564, 290, 134, 1457, 100 },
2086 : { 2258, 564, 290, 134, 1457, 100 },
2087 : { 62, 564, 290, 134, 1457, 100 },
2088 : { 350, 564, 290, 134, 1457, 100 },
2089 : { 629, 564, 290, 134, 1457, 100 },
2090 : { 848, 564, 290, 134, 1457, 100 },
2091 : { 1064, 564, 290, 134, 1457, 100 },
2092 : { 1280, 564, 290, 134, 1457, 100 },
2093 : { 1492, 564, 290, 134, 1457, 100 },
2094 : { 1704, 564, 290, 134, 1457, 100 },
2095 : { 1916, 564, 290, 134, 1457, 100 },
2096 : { 2128, 564, 290, 134, 1457, 100 },
2097 : { 137, 564, 290, 134, 1457, 100 },
2098 : { 426, 564, 290, 134, 1457, 100 },
2099 : { 705, 564, 290, 134, 1457, 100 },
2100 : { 924, 564, 290, 134, 1457, 100 },
2101 : { 1140, 564, 290, 134, 1457, 100 },
2102 : { 1356, 564, 290, 134, 1457, 100 },
2103 : { 1568, 564, 290, 134, 1457, 100 },
2104 : { 1780, 564, 290, 134, 1457, 100 },
2105 : { 1992, 564, 290, 134, 1457, 100 },
2106 : { 2196, 564, 290, 134, 1457, 100 },
2107 : { 205, 564, 290, 134, 1457, 100 },
2108 : { 486, 564, 290, 134, 1457, 100 },
2109 : { 277, 581, 290, 134, 8544, 38 },
2110 : { 980, 780, 8, 181, 1, 121 },
2111 : { 1196, 780, 8, 181, 1, 121 },
2112 : { 1412, 780, 8, 181, 1, 121 },
2113 : { 1624, 780, 8, 181, 1, 121 },
2114 : { 1836, 780, 8, 181, 1, 121 },
2115 : { 2048, 780, 8, 181, 1, 121 },
2116 : { 2252, 780, 8, 181, 1, 121 },
2117 : { 56, 780, 8, 181, 1, 121 },
2118 : { 344, 780, 8, 181, 1, 121 },
2119 : { 622, 780, 8, 181, 1, 121 },
2120 : { 840, 780, 8, 181, 1, 121 },
2121 : { 1056, 780, 8, 181, 1, 121 },
2122 : { 1272, 780, 8, 181, 1, 121 },
2123 : { 1484, 780, 8, 181, 1, 121 },
2124 : { 1696, 780, 8, 181, 1, 121 },
2125 : { 1908, 780, 8, 181, 1, 121 },
2126 : { 2120, 780, 8, 181, 1, 121 },
2127 : { 129, 780, 8, 181, 1, 121 },
2128 : { 418, 780, 8, 181, 1, 121 },
2129 : { 697, 780, 8, 181, 1, 121 },
2130 : { 916, 780, 8, 181, 1, 121 },
2131 : { 1132, 780, 8, 181, 1, 121 },
2132 : { 1348, 780, 8, 181, 1, 121 },
2133 : { 1560, 780, 8, 181, 1, 121 },
2134 : { 1772, 780, 8, 181, 1, 121 },
2135 : { 1984, 780, 8, 181, 1, 121 },
2136 : { 2188, 780, 8, 181, 1, 121 },
2137 : { 197, 780, 8, 181, 1, 121 },
2138 : { 478, 780, 8, 181, 1, 121 },
2139 : { 269, 826, 8, 181, 384, 130 },
2140 : { 546, 688, 8, 181, 944, 105 },
2141 : { 763, 734, 8, 181, 6864, 43 },
2142 : { 767, 598, 545, 151, 625, 139 },
2143 : { 983, 598, 180, 151, 625, 139 },
2144 : { 1199, 598, 180, 151, 625, 139 },
2145 : { 1415, 598, 180, 151, 625, 139 },
2146 : { 1627, 598, 180, 151, 625, 139 },
2147 : { 1839, 598, 180, 151, 625, 139 },
2148 : { 2051, 598, 180, 151, 625, 139 },
2149 : { 2255, 598, 180, 151, 625, 139 },
2150 : { 59, 598, 180, 151, 625, 139 },
2151 : { 347, 598, 180, 151, 625, 139 },
2152 : { 625, 598, 180, 151, 625, 139 },
2153 : { 844, 598, 180, 151, 625, 139 },
2154 : { 1060, 598, 180, 151, 625, 139 },
2155 : { 1276, 598, 180, 151, 625, 139 },
2156 : { 1488, 598, 180, 151, 625, 139 },
2157 : { 1700, 598, 180, 151, 625, 139 },
2158 : { 1912, 598, 180, 151, 625, 139 },
2159 : { 2124, 598, 180, 151, 625, 139 },
2160 : { 133, 598, 180, 151, 625, 139 },
2161 : { 422, 598, 180, 151, 625, 139 },
2162 : { 701, 598, 180, 151, 625, 139 },
2163 : { 920, 598, 180, 151, 625, 139 },
2164 : { 1136, 598, 180, 151, 625, 139 },
2165 : { 1352, 598, 180, 151, 625, 139 },
2166 : { 1564, 598, 180, 151, 625, 139 },
2167 : { 1776, 598, 180, 151, 625, 139 },
2168 : { 1988, 598, 180, 151, 625, 139 },
2169 : { 2192, 598, 180, 151, 625, 139 },
2170 : { 201, 598, 180, 151, 625, 139 },
2171 : { 482, 598, 180, 151, 625, 139 },
2172 : { 273, 628, 180, 151, 1152, 114 },
2173 : { 550, 658, 180, 151, 8096, 52 },
2174 : };
2175 :
2176 : extern const MCPhysReg AArch64RegUnitRoots[][2] = {
2177 : { AArch64::FFR },
2178 : { AArch64::W29 },
2179 : { AArch64::W30 },
2180 : { AArch64::NZCV },
2181 : { AArch64::WSP },
2182 : { AArch64::WZR },
2183 : { AArch64::B0 },
2184 : { AArch64::B1 },
2185 : { AArch64::B2 },
2186 : { AArch64::B3 },
2187 : { AArch64::B4 },
2188 : { AArch64::B5 },
2189 : { AArch64::B6 },
2190 : { AArch64::B7 },
2191 : { AArch64::B8 },
2192 : { AArch64::B9 },
2193 : { AArch64::B10 },
2194 : { AArch64::B11 },
2195 : { AArch64::B12 },
2196 : { AArch64::B13 },
2197 : { AArch64::B14 },
2198 : { AArch64::B15 },
2199 : { AArch64::B16 },
2200 : { AArch64::B17 },
2201 : { AArch64::B18 },
2202 : { AArch64::B19 },
2203 : { AArch64::B20 },
2204 : { AArch64::B21 },
2205 : { AArch64::B22 },
2206 : { AArch64::B23 },
2207 : { AArch64::B24 },
2208 : { AArch64::B25 },
2209 : { AArch64::B26 },
2210 : { AArch64::B27 },
2211 : { AArch64::B28 },
2212 : { AArch64::B29 },
2213 : { AArch64::B30 },
2214 : { AArch64::B31 },
2215 : { AArch64::P0 },
2216 : { AArch64::P1 },
2217 : { AArch64::P2 },
2218 : { AArch64::P3 },
2219 : { AArch64::P4 },
2220 : { AArch64::P5 },
2221 : { AArch64::P6 },
2222 : { AArch64::P7 },
2223 : { AArch64::P8 },
2224 : { AArch64::P9 },
2225 : { AArch64::P10 },
2226 : { AArch64::P11 },
2227 : { AArch64::P12 },
2228 : { AArch64::P13 },
2229 : { AArch64::P14 },
2230 : { AArch64::P15 },
2231 : { AArch64::W0 },
2232 : { AArch64::W1 },
2233 : { AArch64::W2 },
2234 : { AArch64::W3 },
2235 : { AArch64::W4 },
2236 : { AArch64::W5 },
2237 : { AArch64::W6 },
2238 : { AArch64::W7 },
2239 : { AArch64::W8 },
2240 : { AArch64::W9 },
2241 : { AArch64::W10 },
2242 : { AArch64::W11 },
2243 : { AArch64::W12 },
2244 : { AArch64::W13 },
2245 : { AArch64::W14 },
2246 : { AArch64::W15 },
2247 : { AArch64::W16 },
2248 : { AArch64::W17 },
2249 : { AArch64::W18 },
2250 : { AArch64::W19 },
2251 : { AArch64::W20 },
2252 : { AArch64::W21 },
2253 : { AArch64::W22 },
2254 : { AArch64::W23 },
2255 : { AArch64::W24 },
2256 : { AArch64::W25 },
2257 : { AArch64::W26 },
2258 : { AArch64::W27 },
2259 : { AArch64::W28 },
2260 : { AArch64::Z0_HI },
2261 : { AArch64::Z1_HI },
2262 : { AArch64::Z2_HI },
2263 : { AArch64::Z3_HI },
2264 : { AArch64::Z4_HI },
2265 : { AArch64::Z5_HI },
2266 : { AArch64::Z6_HI },
2267 : { AArch64::Z7_HI },
2268 : { AArch64::Z8_HI },
2269 : { AArch64::Z9_HI },
2270 : { AArch64::Z10_HI },
2271 : { AArch64::Z11_HI },
2272 : { AArch64::Z12_HI },
2273 : { AArch64::Z13_HI },
2274 : { AArch64::Z14_HI },
2275 : { AArch64::Z15_HI },
2276 : { AArch64::Z16_HI },
2277 : { AArch64::Z17_HI },
2278 : { AArch64::Z18_HI },
2279 : { AArch64::Z19_HI },
2280 : { AArch64::Z20_HI },
2281 : { AArch64::Z21_HI },
2282 : { AArch64::Z22_HI },
2283 : { AArch64::Z23_HI },
2284 : { AArch64::Z24_HI },
2285 : { AArch64::Z25_HI },
2286 : { AArch64::Z26_HI },
2287 : { AArch64::Z27_HI },
2288 : { AArch64::Z28_HI },
2289 : { AArch64::Z29_HI },
2290 : { AArch64::Z30_HI },
2291 : { AArch64::Z31_HI },
2292 : };
2293 :
2294 : namespace { // Register classes...
2295 : // FPR8 Register Class...
2296 : const MCPhysReg FPR8[] = {
2297 : AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31,
2298 : };
2299 :
2300 : // FPR8 Bit set.
2301 : const uint8_t FPR8Bits[] = {
2302 : 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2303 : };
2304 :
2305 : // FPR16 Register Class...
2306 : const MCPhysReg FPR16[] = {
2307 : AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31,
2308 : };
2309 :
2310 : // FPR16 Bit set.
2311 : const uint8_t FPR16Bits[] = {
2312 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2313 : };
2314 :
2315 : // PPR Register Class...
2316 : const MCPhysReg PPR[] = {
2317 : AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15,
2318 : };
2319 :
2320 : // PPR Bit set.
2321 : const uint8_t PPRBits[] = {
2322 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
2323 : };
2324 :
2325 : // PPR_3b Register Class...
2326 : const MCPhysReg PPR_3b[] = {
2327 : AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
2328 : };
2329 :
2330 : // PPR_3b Bit set.
2331 : const uint8_t PPR_3bBits[] = {
2332 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
2333 : };
2334 :
2335 : // GPR32all Register Class...
2336 : const MCPhysReg GPR32all[] = {
2337 : AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP,
2338 : };
2339 :
2340 : // GPR32all Bit set.
2341 : const uint8_t GPR32allBits[] = {
2342 : 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2343 : };
2344 :
2345 : // FPR32 Register Class...
2346 : const MCPhysReg FPR32[] = {
2347 : AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31,
2348 : };
2349 :
2350 : // FPR32 Bit set.
2351 : const uint8_t FPR32Bits[] = {
2352 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2353 : };
2354 :
2355 : // GPR32 Register Class...
2356 : const MCPhysReg GPR32[] = {
2357 : AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR,
2358 : };
2359 :
2360 : // GPR32 Bit set.
2361 : const uint8_t GPR32Bits[] = {
2362 : 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2363 : };
2364 :
2365 : // GPR32sp Register Class...
2366 : const MCPhysReg GPR32sp[] = {
2367 : AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP,
2368 : };
2369 :
2370 : // GPR32sp Bit set.
2371 : const uint8_t GPR32spBits[] = {
2372 : 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2373 : };
2374 :
2375 : // GPR32common Register Class...
2376 : const MCPhysReg GPR32common[] = {
2377 : AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30,
2378 : };
2379 :
2380 : // GPR32common Bit set.
2381 : const uint8_t GPR32commonBits[] = {
2382 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2383 : };
2384 :
2385 : // CCR Register Class...
2386 : const MCPhysReg CCR[] = {
2387 : AArch64::NZCV,
2388 : };
2389 :
2390 : // CCR Bit set.
2391 : const uint8_t CCRBits[] = {
2392 : 0x10,
2393 : };
2394 :
2395 : // GPR32sponly Register Class...
2396 : const MCPhysReg GPR32sponly[] = {
2397 : AArch64::WSP,
2398 : };
2399 :
2400 : // GPR32sponly Bit set.
2401 : const uint8_t GPR32sponlyBits[] = {
2402 : 0x40,
2403 : };
2404 :
2405 : // WSeqPairsClass Register Class...
2406 : const MCPhysReg WSeqPairsClass[] = {
2407 : AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0,
2408 : };
2409 :
2410 : // WSeqPairsClass Bit set.
2411 : const uint8_t WSeqPairsClassBits[] = {
2412 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2413 : };
2414 :
2415 : // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
2416 : const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
2417 : AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR,
2418 : };
2419 :
2420 : // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
2421 : const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
2422 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f,
2423 : };
2424 :
2425 : // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2426 : const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
2427 : AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0,
2428 : };
2429 :
2430 : // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2431 : const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2432 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f,
2433 : };
2434 :
2435 : // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2436 : const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
2437 : AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30,
2438 : };
2439 :
2440 : // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2441 : const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2442 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
2443 : };
2444 :
2445 : // GPR64all Register Class...
2446 : const MCPhysReg GPR64all[] = {
2447 : AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP,
2448 : };
2449 :
2450 : // GPR64all Bit set.
2451 : const uint8_t GPR64allBits[] = {
2452 : 0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2453 : };
2454 :
2455 : // FPR64 Register Class...
2456 : const MCPhysReg FPR64[] = {
2457 : AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31,
2458 : };
2459 :
2460 : // FPR64 Bit set.
2461 : const uint8_t FPR64Bits[] = {
2462 : 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2463 : };
2464 :
2465 : // GPR64 Register Class...
2466 : const MCPhysReg GPR64[] = {
2467 : AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR,
2468 : };
2469 :
2470 : // GPR64 Bit set.
2471 : const uint8_t GPR64Bits[] = {
2472 : 0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2473 : };
2474 :
2475 : // GPR64sp Register Class...
2476 : const MCPhysReg GPR64sp[] = {
2477 : AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP,
2478 : };
2479 :
2480 : // GPR64sp Bit set.
2481 : const uint8_t GPR64spBits[] = {
2482 : 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2483 : };
2484 :
2485 : // GPR64common Register Class...
2486 : const MCPhysReg GPR64common[] = {
2487 : AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR,
2488 : };
2489 :
2490 : // GPR64common Bit set.
2491 : const uint8_t GPR64commonBits[] = {
2492 : 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2493 : };
2494 :
2495 : // tcGPR64 Register Class...
2496 : const MCPhysReg tcGPR64[] = {
2497 : AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18,
2498 : };
2499 :
2500 : // tcGPR64 Bit set.
2501 : const uint8_t tcGPR64Bits[] = {
2502 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07,
2503 : };
2504 :
2505 : // rtcGPR64 Register Class...
2506 : const MCPhysReg rtcGPR64[] = {
2507 : AArch64::X16, AArch64::X17,
2508 : };
2509 :
2510 : // rtcGPR64 Bit set.
2511 : const uint8_t rtcGPR64Bits[] = {
2512 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
2513 : };
2514 :
2515 : // GPR64sponly Register Class...
2516 : const MCPhysReg GPR64sponly[] = {
2517 : AArch64::SP,
2518 : };
2519 :
2520 : // GPR64sponly Bit set.
2521 : const uint8_t GPR64sponlyBits[] = {
2522 : 0x20,
2523 : };
2524 :
2525 : // DD Register Class...
2526 : const MCPhysReg DD[] = {
2527 : AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0,
2528 : };
2529 :
2530 : // DD Bit set.
2531 : const uint8_t DDBits[] = {
2532 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2533 : };
2534 :
2535 : // XSeqPairsClass Register Class...
2536 : const MCPhysReg XSeqPairsClass[] = {
2537 : AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0,
2538 : };
2539 :
2540 : // XSeqPairsClass Bit set.
2541 : const uint8_t XSeqPairsClassBits[] = {
2542 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2543 : };
2544 :
2545 : // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
2546 : const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
2547 : AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR,
2548 : };
2549 :
2550 : // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
2551 : const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
2552 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f,
2553 : };
2554 :
2555 : // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2556 : const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
2557 : AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0,
2558 : };
2559 :
2560 : // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2561 : const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2562 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f,
2563 : };
2564 :
2565 : // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2566 : const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
2567 : AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR,
2568 : };
2569 :
2570 : // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2571 : const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2572 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f,
2573 : };
2574 :
2575 : // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
2576 : const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
2577 : AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19,
2578 : };
2579 :
2580 : // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
2581 : const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
2582 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f,
2583 : };
2584 :
2585 : // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2586 : const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2587 : AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0,
2588 : };
2589 :
2590 : // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2591 : const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2592 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07,
2593 : };
2594 :
2595 : // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2596 : const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2597 : AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18,
2598 : };
2599 :
2600 : // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2601 : const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2602 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07,
2603 : };
2604 :
2605 : // XSeqPairsClass_with_sube64_in_rtcGPR64 Register Class...
2606 : const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64[] = {
2607 : AArch64::X16_X17, AArch64::X17_X18,
2608 : };
2609 :
2610 : // XSeqPairsClass_with_sube64_in_rtcGPR64 Bit set.
2611 : const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64Bits[] = {
2612 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
2613 : };
2614 :
2615 : // XSeqPairsClass_with_subo64_in_rtcGPR64 Register Class...
2616 : const MCPhysReg XSeqPairsClass_with_subo64_in_rtcGPR64[] = {
2617 : AArch64::X15_X16, AArch64::X16_X17,
2618 : };
2619 :
2620 : // XSeqPairsClass_with_subo64_in_rtcGPR64 Bit set.
2621 : const uint8_t XSeqPairsClass_with_subo64_in_rtcGPR64Bits[] = {
2622 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
2623 : };
2624 :
2625 : // XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64 Register Class...
2626 : const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64[] = {
2627 : AArch64::X16_X17,
2628 : };
2629 :
2630 : // XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64 Bit set.
2631 : const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Bits[] = {
2632 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
2633 : };
2634 :
2635 : // FPR128 Register Class...
2636 : const MCPhysReg FPR128[] = {
2637 : AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31,
2638 : };
2639 :
2640 : // FPR128 Bit set.
2641 : const uint8_t FPR128Bits[] = {
2642 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2643 : };
2644 :
2645 : // ZPR Register Class...
2646 : const MCPhysReg ZPR[] = {
2647 : AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31,
2648 : };
2649 :
2650 : // ZPR Bit set.
2651 : const uint8_t ZPRBits[] = {
2652 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2653 : };
2654 :
2655 : // FPR128_lo Register Class...
2656 : const MCPhysReg FPR128_lo[] = {
2657 : AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15,
2658 : };
2659 :
2660 : // FPR128_lo Bit set.
2661 : const uint8_t FPR128_loBits[] = {
2662 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
2663 : };
2664 :
2665 : // ZPR_4b Register Class...
2666 : const MCPhysReg ZPR_4b[] = {
2667 : AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
2668 : };
2669 :
2670 : // ZPR_4b Bit set.
2671 : const uint8_t ZPR_4bBits[] = {
2672 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2673 : };
2674 :
2675 : // ZPR_3b Register Class...
2676 : const MCPhysReg ZPR_3b[] = {
2677 : AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
2678 : };
2679 :
2680 : // ZPR_3b Bit set.
2681 : const uint8_t ZPR_3bBits[] = {
2682 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2683 : };
2684 :
2685 : // DDD Register Class...
2686 : const MCPhysReg DDD[] = {
2687 : AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1,
2688 : };
2689 :
2690 : // DDD Bit set.
2691 : const uint8_t DDDBits[] = {
2692 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2693 : };
2694 :
2695 : // DDDD Register Class...
2696 : const MCPhysReg DDDD[] = {
2697 : AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2,
2698 : };
2699 :
2700 : // DDDD Bit set.
2701 : const uint8_t DDDDBits[] = {
2702 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2703 : };
2704 :
2705 : // QQ Register Class...
2706 : const MCPhysReg QQ[] = {
2707 : AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0,
2708 : };
2709 :
2710 : // QQ Bit set.
2711 : const uint8_t QQBits[] = {
2712 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2713 : };
2714 :
2715 : // ZPR2 Register Class...
2716 : const MCPhysReg ZPR2[] = {
2717 : AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0,
2718 : };
2719 :
2720 : // ZPR2 Bit set.
2721 : const uint8_t ZPR2Bits[] = {
2722 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2723 : };
2724 :
2725 : // QQ_with_qsub0_in_FPR128_lo Register Class...
2726 : const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
2727 : AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
2728 : };
2729 :
2730 : // QQ_with_qsub0_in_FPR128_lo Bit set.
2731 : const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
2732 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2733 : };
2734 :
2735 : // QQ_with_qsub1_in_FPR128_lo Register Class...
2736 : const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
2737 : AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0,
2738 : };
2739 :
2740 : // QQ_with_qsub1_in_FPR128_lo Bit set.
2741 : const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
2742 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2743 : };
2744 :
2745 : // ZPR2_with_zsub1_in_ZPR_4b Register Class...
2746 : const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
2747 : AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0,
2748 : };
2749 :
2750 : // ZPR2_with_zsub1_in_ZPR_4b Bit set.
2751 : const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2752 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2753 : };
2754 :
2755 : // ZPR2_with_zsub_in_FPR128_lo Register Class...
2756 : const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
2757 : AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
2758 : };
2759 :
2760 : // ZPR2_with_zsub_in_FPR128_lo Bit set.
2761 : const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
2762 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2763 : };
2764 :
2765 : // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
2766 : const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
2767 : AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15,
2768 : };
2769 :
2770 : // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
2771 : const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
2772 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2773 : };
2774 :
2775 : // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class...
2776 : const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
2777 : AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15,
2778 : };
2779 :
2780 : // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set.
2781 : const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2782 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2783 : };
2784 :
2785 : // ZPR2_with_zsub0_in_ZPR_3b Register Class...
2786 : const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
2787 : AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
2788 : };
2789 :
2790 : // ZPR2_with_zsub0_in_ZPR_3b Bit set.
2791 : const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = {
2792 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2793 : };
2794 :
2795 : // ZPR2_with_zsub1_in_ZPR_3b Register Class...
2796 : const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
2797 : AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0,
2798 : };
2799 :
2800 : // ZPR2_with_zsub1_in_ZPR_3b Bit set.
2801 : const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2802 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
2803 : };
2804 :
2805 : // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class...
2806 : const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
2807 : AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7,
2808 : };
2809 :
2810 : // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set.
2811 : const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2812 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2813 : };
2814 :
2815 : // QQQ Register Class...
2816 : const MCPhysReg QQQ[] = {
2817 : AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1,
2818 : };
2819 :
2820 : // QQQ Bit set.
2821 : const uint8_t QQQBits[] = {
2822 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2823 : };
2824 :
2825 : // ZPR3 Register Class...
2826 : const MCPhysReg ZPR3[] = {
2827 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
2828 : };
2829 :
2830 : // ZPR3 Bit set.
2831 : const uint8_t ZPR3Bits[] = {
2832 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2833 : };
2834 :
2835 : // QQQ_with_qsub0_in_FPR128_lo Register Class...
2836 : const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
2837 : AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17,
2838 : };
2839 :
2840 : // QQQ_with_qsub0_in_FPR128_lo Bit set.
2841 : const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
2842 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2843 : };
2844 :
2845 : // QQQ_with_qsub1_in_FPR128_lo Register Class...
2846 : const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
2847 : AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1,
2848 : };
2849 :
2850 : // QQQ_with_qsub1_in_FPR128_lo Bit set.
2851 : const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
2852 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2853 : };
2854 :
2855 : // QQQ_with_qsub2_in_FPR128_lo Register Class...
2856 : const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
2857 : AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1,
2858 : };
2859 :
2860 : // QQQ_with_qsub2_in_FPR128_lo Bit set.
2861 : const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
2862 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2863 : };
2864 :
2865 : // ZPR3_with_zsub1_in_ZPR_4b Register Class...
2866 : const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
2867 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1,
2868 : };
2869 :
2870 : // ZPR3_with_zsub1_in_ZPR_4b Bit set.
2871 : const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2872 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2873 : };
2874 :
2875 : // ZPR3_with_zsub2_in_ZPR_4b Register Class...
2876 : const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
2877 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
2878 : };
2879 :
2880 : // ZPR3_with_zsub2_in_ZPR_4b Bit set.
2881 : const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2882 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2883 : };
2884 :
2885 : // ZPR3_with_zsub_in_FPR128_lo Register Class...
2886 : const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
2887 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17,
2888 : };
2889 :
2890 : // ZPR3_with_zsub_in_FPR128_lo Bit set.
2891 : const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
2892 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2893 : };
2894 :
2895 : // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
2896 : const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
2897 : AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
2898 : };
2899 :
2900 : // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
2901 : const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
2902 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2903 : };
2904 :
2905 : // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2906 : const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2907 : AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1,
2908 : };
2909 :
2910 : // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2911 : const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2912 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2913 : };
2914 :
2915 : // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2916 : const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2917 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1,
2918 : };
2919 :
2920 : // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2921 : const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2922 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2923 : };
2924 :
2925 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class...
2926 : const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
2927 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
2928 : };
2929 :
2930 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set.
2931 : const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2932 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2933 : };
2934 :
2935 : // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2936 : const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2937 : AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15,
2938 : };
2939 :
2940 : // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2941 : const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2942 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2943 : };
2944 :
2945 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2946 : const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2947 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15,
2948 : };
2949 :
2950 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2951 : const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2952 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2953 : };
2954 :
2955 : // ZPR3_with_zsub0_in_ZPR_3b Register Class...
2956 : const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
2957 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9,
2958 : };
2959 :
2960 : // ZPR3_with_zsub0_in_ZPR_3b Bit set.
2961 : const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = {
2962 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2963 : };
2964 :
2965 : // ZPR3_with_zsub1_in_ZPR_3b Register Class...
2966 : const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
2967 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1,
2968 : };
2969 :
2970 : // ZPR3_with_zsub1_in_ZPR_3b Bit set.
2971 : const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2972 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
2973 : };
2974 :
2975 : // ZPR3_with_zsub2_in_ZPR_3b Register Class...
2976 : const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
2977 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
2978 : };
2979 :
2980 : // ZPR3_with_zsub2_in_ZPR_3b Bit set.
2981 : const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2982 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18,
2983 : };
2984 :
2985 : // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
2986 : const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
2987 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1,
2988 : };
2989 :
2990 : // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
2991 : const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2992 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10,
2993 : };
2994 :
2995 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class...
2996 : const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
2997 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8,
2998 : };
2999 :
3000 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set.
3001 : const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = {
3002 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
3003 : };
3004 :
3005 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
3006 : const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3007 : AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
3008 : };
3009 :
3010 : // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
3011 : const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3012 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
3013 : };
3014 :
3015 : // QQQQ Register Class...
3016 : const MCPhysReg QQQQ[] = {
3017 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3018 : };
3019 :
3020 : // QQQQ Bit set.
3021 : const uint8_t QQQQBits[] = {
3022 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
3023 : };
3024 :
3025 : // ZPR4 Register Class...
3026 : const MCPhysReg ZPR4[] = {
3027 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3028 : };
3029 :
3030 : // ZPR4 Bit set.
3031 : const uint8_t ZPR4Bits[] = {
3032 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
3033 : };
3034 :
3035 : // QQQQ_with_qsub0_in_FPR128_lo Register Class...
3036 : const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
3037 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18,
3038 : };
3039 :
3040 : // QQQQ_with_qsub0_in_FPR128_lo Bit set.
3041 : const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
3042 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
3043 : };
3044 :
3045 : // QQQQ_with_qsub1_in_FPR128_lo Register Class...
3046 : const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
3047 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2,
3048 : };
3049 :
3050 : // QQQQ_with_qsub1_in_FPR128_lo Bit set.
3051 : const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
3052 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
3053 : };
3054 :
3055 : // QQQQ_with_qsub2_in_FPR128_lo Register Class...
3056 : const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
3057 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3058 : };
3059 :
3060 : // QQQQ_with_qsub2_in_FPR128_lo Bit set.
3061 : const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
3062 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
3063 : };
3064 :
3065 : // QQQQ_with_qsub3_in_FPR128_lo Register Class...
3066 : const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
3067 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3068 : };
3069 :
3070 : // QQQQ_with_qsub3_in_FPR128_lo Bit set.
3071 : const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
3072 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c,
3073 : };
3074 :
3075 : // ZPR4_with_zsub1_in_ZPR_4b Register Class...
3076 : const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
3077 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2,
3078 : };
3079 :
3080 : // ZPR4_with_zsub1_in_ZPR_4b Bit set.
3081 : const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3082 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
3083 : };
3084 :
3085 : // ZPR4_with_zsub2_in_ZPR_4b Register Class...
3086 : const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
3087 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3088 : };
3089 :
3090 : // ZPR4_with_zsub2_in_ZPR_4b Bit set.
3091 : const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3092 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
3093 : };
3094 :
3095 : // ZPR4_with_zsub3_in_ZPR_4b Register Class...
3096 : const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
3097 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3098 : };
3099 :
3100 : // ZPR4_with_zsub3_in_ZPR_4b Bit set.
3101 : const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3102 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c,
3103 : };
3104 :
3105 : // ZPR4_with_zsub_in_FPR128_lo Register Class...
3106 : const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
3107 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18,
3108 : };
3109 :
3110 : // ZPR4_with_zsub_in_FPR128_lo Bit set.
3111 : const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
3112 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
3113 : };
3114 :
3115 : // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
3116 : const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
3117 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
3118 : };
3119 :
3120 : // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
3121 : const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
3122 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
3123 : };
3124 :
3125 : // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3126 : const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3127 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2,
3128 : };
3129 :
3130 : // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3131 : const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3132 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
3133 : };
3134 :
3135 : // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3136 : const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3137 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3138 : };
3139 :
3140 : // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3141 : const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3142 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18,
3143 : };
3144 :
3145 : // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3146 : const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3147 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2,
3148 : };
3149 :
3150 : // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3151 : const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3152 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
3153 : };
3154 :
3155 : // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3156 : const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3157 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3158 : };
3159 :
3160 : // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3161 : const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3162 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18,
3163 : };
3164 :
3165 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class...
3166 : const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
3167 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
3168 : };
3169 :
3170 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set.
3171 : const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3172 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
3173 : };
3174 :
3175 : // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3176 : const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3177 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16,
3178 : };
3179 :
3180 : // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3181 : const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3182 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
3183 : };
3184 :
3185 : // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3186 : const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3187 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2,
3188 : };
3189 :
3190 : // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3191 : const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3192 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10,
3193 : };
3194 :
3195 : // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3196 : const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3197 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2,
3198 : };
3199 :
3200 : // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3201 : const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3202 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10,
3203 : };
3204 :
3205 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3206 : const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3207 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16,
3208 : };
3209 :
3210 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3211 : const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3212 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
3213 : };
3214 :
3215 : // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3216 : const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3217 : AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15,
3218 : };
3219 :
3220 : // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3221 : const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3222 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03,
3223 : };
3224 :
3225 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3226 : const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3227 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15,
3228 : };
3229 :
3230 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3231 : const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3232 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03,
3233 : };
3234 :
3235 : // ZPR4_with_zsub0_in_ZPR_3b Register Class...
3236 : const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
3237 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10,
3238 : };
3239 :
3240 : // ZPR4_with_zsub0_in_ZPR_3b Bit set.
3241 : const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = {
3242 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
3243 : };
3244 :
3245 : // ZPR4_with_zsub1_in_ZPR_3b Register Class...
3246 : const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
3247 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2,
3248 : };
3249 :
3250 : // ZPR4_with_zsub1_in_ZPR_3b Bit set.
3251 : const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3252 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
3253 : };
3254 :
3255 : // ZPR4_with_zsub2_in_ZPR_3b Register Class...
3256 : const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
3257 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3258 : };
3259 :
3260 : // ZPR4_with_zsub2_in_ZPR_3b Bit set.
3261 : const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3262 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18,
3263 : };
3264 :
3265 : // ZPR4_with_zsub3_in_ZPR_3b Register Class...
3266 : const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
3267 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3268 : };
3269 :
3270 : // ZPR4_with_zsub3_in_ZPR_3b Bit set.
3271 : const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3272 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c,
3273 : };
3274 :
3275 : // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3276 : const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3277 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2,
3278 : };
3279 :
3280 : // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3281 : const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3282 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10,
3283 : };
3284 :
3285 : // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3286 : const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3287 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3288 : };
3289 :
3290 : // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3291 : const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3292 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18,
3293 : };
3294 :
3295 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class...
3296 : const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
3297 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9,
3298 : };
3299 :
3300 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set.
3301 : const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3302 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
3303 : };
3304 :
3305 : // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3306 : const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3307 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2,
3308 : };
3309 :
3310 : // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3311 : const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3312 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10,
3313 : };
3314 :
3315 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3316 : const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3317 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
3318 : };
3319 :
3320 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3321 : const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3322 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
3323 : };
3324 :
3325 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3326 : const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3327 : AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7,
3328 : };
3329 :
3330 : // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3331 : const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3332 : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03,
3333 : };
3334 :
3335 : } // end anonymous namespace
3336 :
3337 : extern const char AArch64RegClassStrings[] = {
3338 : /* 0 */ 'F', 'P', 'R', '3', '2', 0,
3339 : /* 6 */ 'G', 'P', 'R', '3', '2', 0,
3340 : /* 12 */ 'Z', 'P', 'R', '2', 0,
3341 : /* 17 */ 'Z', 'P', 'R', '3', 0,
3342 : /* 22 */ 'F', 'P', 'R', '6', '4', 0,
3343 : /* 28 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3344 : /* 66 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3345 : /* 150 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3346 : /* 189 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3347 : /* 271 */ 'Z', 'P', 'R', '4', 0,
3348 : /* 276 */ 'F', 'P', 'R', '1', '6', 0,
3349 : /* 282 */ 'F', 'P', 'R', '1', '2', '8', 0,
3350 : /* 289 */ 'F', 'P', 'R', '8', 0,
3351 : /* 294 */ 'D', 'D', 'D', 'D', 0,
3352 : /* 299 */ 'Q', 'Q', 'Q', 'Q', 0,
3353 : /* 304 */ 'C', 'C', 'R', 0,
3354 : /* 308 */ 'P', 'P', 'R', 0,
3355 : /* 312 */ 'Z', 'P', 'R', 0,
3356 : /* 316 */ 'P', 'P', 'R', '_', '3', 'b', 0,
3357 : /* 323 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3358 : /* 349 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3359 : /* 375 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3360 : /* 401 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3361 : /* 459 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3362 : /* 517 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3363 : /* 575 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3364 : /* 631 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3365 : /* 689 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3366 : /* 745 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3367 : /* 803 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3368 : /* 859 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3369 : /* 915 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3370 : /* 973 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3371 : /* 1031 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3372 : /* 1089 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3373 : /* 1147 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3374 : /* 1203 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3375 : /* 1261 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3376 : /* 1317 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3377 : /* 1375 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3378 : /* 1431 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3379 : /* 1487 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3380 : /* 1545 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
3381 : /* 1554 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
3382 : /* 1563 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3383 : /* 1605 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3384 : /* 1647 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3385 : /* 1735 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3386 : /* 1823 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3387 : /* 1852 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3388 : /* 1914 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3389 : /* 1974 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3390 : /* 2032 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3391 : /* 2094 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3392 : /* 2156 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3393 : /* 2216 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3394 : /* 2276 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3395 : /* 2338 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3396 : /* 2400 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3397 : /* 2462 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3398 : /* 2490 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3399 : /* 2518 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3400 : /* 2546 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
3401 : /* 2554 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
3402 : /* 2562 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3403 : /* 2577 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3404 : /* 2592 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
3405 : /* 2604 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
3406 : };
3407 :
3408 : extern const MCRegisterClass AArch64MCRegisterClasses[] = {
3409 : { FPR8, FPR8Bits, 289, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, true },
3410 : { FPR16, FPR16Bits, 276, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 1, true },
3411 : { PPR, PPRBits, 308, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 1, true },
3412 : { PPR_3b, PPR_3bBits, 316, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 1, true },
3413 : { GPR32all, GPR32allBits, 1545, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 1, true },
3414 : { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 1, true },
3415 : { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 1, true },
3416 : { GPR32sp, GPR32spBits, 2546, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 1, true },
3417 : { GPR32common, GPR32commonBits, 1593, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 1, true },
3418 : { CCR, CCRBits, 304, 1, sizeof(CCRBits), AArch64::CCRRegClassID, -1, false },
3419 : { GPR32sponly, GPR32sponlyBits, 2592, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 1, true },
3420 : { WSeqPairsClass, WSeqPairsClassBits, 2562, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 1, true },
3421 : { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 1605, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 1, true },
3422 : { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 1693, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3423 : { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 1647, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3424 : { GPR64all, GPR64allBits, 1554, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 1, true },
3425 : { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 1, true },
3426 : { GPR64, GPR64Bits, 60, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 1, true },
3427 : { GPR64sp, GPR64spBits, 2554, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 1, true },
3428 : { GPR64common, GPR64commonBits, 1811, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 1, true },
3429 : { tcGPR64, tcGPR64Bits, 58, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 1, true },
3430 : { rtcGPR64, rtcGPR64Bits, 180, 2, sizeof(rtcGPR64Bits), AArch64::rtcGPR64RegClassID, 1, true },
3431 : { GPR64sponly, GPR64sponlyBits, 2604, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 1, true },
3432 : { DD, DDBits, 296, 32, sizeof(DDBits), AArch64::DDRegClassID, 1, true },
3433 : { XSeqPairsClass, XSeqPairsClassBits, 2577, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 1, true },
3434 : { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 1563, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 1, true },
3435 : { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 1781, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3436 : { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 1735, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3437 : { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 28, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 1, true },
3438 : { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 112, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3439 : { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 66, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3440 : { XSeqPairsClass_with_sube64_in_rtcGPR64, XSeqPairsClass_with_sube64_in_rtcGPR64Bits, 150, 2, sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID, 1, true },
3441 : { XSeqPairsClass_with_subo64_in_rtcGPR64, XSeqPairsClass_with_subo64_in_rtcGPR64Bits, 232, 2, sizeof(XSeqPairsClass_with_subo64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID, 1, true },
3442 : { XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64, XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Bits, 189, 1, sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID, 1, true },
3443 : { FPR128, FPR128Bits, 282, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 1, true },
3444 : { ZPR, ZPRBits, 312, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 1, true },
3445 : { FPR128_lo, FPR128_loBits, 1842, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 1, true },
3446 : { ZPR_4b, ZPR_4bBits, 1024, 16, sizeof(ZPR_4bBits), AArch64::ZPR_4bRegClassID, 1, true },
3447 : { ZPR_3b, ZPR_3bBits, 342, 8, sizeof(ZPR_3bBits), AArch64::ZPR_3bRegClassID, 1, true },
3448 : { DDD, DDDBits, 295, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 1, true },
3449 : { DDDD, DDDDBits, 294, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 1, true },
3450 : { QQ, QQBits, 301, 32, sizeof(QQBits), AArch64::QQRegClassID, 1, true },
3451 : { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 1, true },
3452 : { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 1825, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3453 : { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 1887, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3454 : { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, 1005, 16, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3455 : { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, 2462, 16, sizeof(ZPR2_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, 1, true },
3456 : { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 1974, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3457 : { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, 973, 15, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3458 : { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, 323, 8, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits), AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3459 : { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, 433, 8, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3460 : { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, 401, 7, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3461 : { QQQ, QQQBits, 300, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 1, true },
3462 : { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 1, true },
3463 : { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 1824, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3464 : { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 1886, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3465 : { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 2066, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3466 : { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, 1063, 16, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3467 : { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, 1177, 16, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3468 : { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, 2490, 16, sizeof(ZPR3_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, 1, true },
3469 : { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 1914, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3470 : { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2216, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3471 : { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1147, 15, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3472 : { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, 1031, 15, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3473 : { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2156, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3474 : { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1203, 14, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3475 : { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, 349, 8, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits), AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3476 : { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, 491, 8, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3477 : { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, 605, 8, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3478 : { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, 575, 7, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3479 : { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, 459, 7, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3480 : { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, 631, 6, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3481 : { QQQQ, QQQQBits, 299, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 1, true },
3482 : { ZPR4, ZPR4Bits, 271, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 1, true },
3483 : { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 1823, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3484 : { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 1885, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3485 : { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 2065, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3486 : { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 2309, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3487 : { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, 1121, 16, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3488 : { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, 1291, 16, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3489 : { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, 1405, 16, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3490 : { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, 2518, 16, sizeof(ZPR4_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, 1, true },
3491 : { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 1852, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3492 : { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 2094, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3493 : { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2400, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3494 : { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1261, 15, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3495 : { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1431, 15, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3496 : { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, 1089, 15, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3497 : { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 2032, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3498 : { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2338, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3499 : { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1375, 14, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3500 : { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1317, 14, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3501 : { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2276, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3502 : { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1487, 13, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3503 : { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, 375, 8, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits), AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3504 : { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, 549, 8, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3505 : { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, 719, 8, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3506 : { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, 833, 8, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3507 : { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, 689, 7, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3508 : { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 859, 7, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3509 : { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, 517, 7, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3510 : { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 803, 6, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3511 : { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, 745, 6, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3512 : { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, 915, 5, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3513 : };
3514 :
3515 : // AArch64 Dwarf<->LLVM register mappings.
3516 : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
3517 : { 0U, AArch64::W0 },
3518 : { 1U, AArch64::W1 },
3519 : { 2U, AArch64::W2 },
3520 : { 3U, AArch64::W3 },
3521 : { 4U, AArch64::W4 },
3522 : { 5U, AArch64::W5 },
3523 : { 6U, AArch64::W6 },
3524 : { 7U, AArch64::W7 },
3525 : { 8U, AArch64::W8 },
3526 : { 9U, AArch64::W9 },
3527 : { 10U, AArch64::W10 },
3528 : { 11U, AArch64::W11 },
3529 : { 12U, AArch64::W12 },
3530 : { 13U, AArch64::W13 },
3531 : { 14U, AArch64::W14 },
3532 : { 15U, AArch64::W15 },
3533 : { 16U, AArch64::W16 },
3534 : { 17U, AArch64::W17 },
3535 : { 18U, AArch64::W18 },
3536 : { 19U, AArch64::W19 },
3537 : { 20U, AArch64::W20 },
3538 : { 21U, AArch64::W21 },
3539 : { 22U, AArch64::W22 },
3540 : { 23U, AArch64::W23 },
3541 : { 24U, AArch64::W24 },
3542 : { 25U, AArch64::W25 },
3543 : { 26U, AArch64::W26 },
3544 : { 27U, AArch64::W27 },
3545 : { 28U, AArch64::W28 },
3546 : { 29U, AArch64::W29 },
3547 : { 30U, AArch64::W30 },
3548 : { 31U, AArch64::WSP },
3549 : { 47U, AArch64::FFR },
3550 : { 48U, AArch64::P0 },
3551 : { 49U, AArch64::P1 },
3552 : { 50U, AArch64::P2 },
3553 : { 51U, AArch64::P3 },
3554 : { 52U, AArch64::P4 },
3555 : { 53U, AArch64::P5 },
3556 : { 54U, AArch64::P6 },
3557 : { 55U, AArch64::P7 },
3558 : { 56U, AArch64::P8 },
3559 : { 57U, AArch64::P9 },
3560 : { 58U, AArch64::P10 },
3561 : { 59U, AArch64::P11 },
3562 : { 60U, AArch64::P12 },
3563 : { 61U, AArch64::P13 },
3564 : { 62U, AArch64::P14 },
3565 : { 63U, AArch64::P15 },
3566 : { 64U, AArch64::B0 },
3567 : { 65U, AArch64::B1 },
3568 : { 66U, AArch64::B2 },
3569 : { 67U, AArch64::B3 },
3570 : { 68U, AArch64::B4 },
3571 : { 69U, AArch64::B5 },
3572 : { 70U, AArch64::B6 },
3573 : { 71U, AArch64::B7 },
3574 : { 72U, AArch64::B8 },
3575 : { 73U, AArch64::B9 },
3576 : { 74U, AArch64::B10 },
3577 : { 75U, AArch64::B11 },
3578 : { 76U, AArch64::B12 },
3579 : { 77U, AArch64::B13 },
3580 : { 78U, AArch64::B14 },
3581 : { 79U, AArch64::B15 },
3582 : { 80U, AArch64::B16 },
3583 : { 81U, AArch64::B17 },
3584 : { 82U, AArch64::B18 },
3585 : { 83U, AArch64::B19 },
3586 : { 84U, AArch64::B20 },
3587 : { 85U, AArch64::B21 },
3588 : { 86U, AArch64::B22 },
3589 : { 87U, AArch64::B23 },
3590 : { 88U, AArch64::B24 },
3591 : { 89U, AArch64::B25 },
3592 : { 90U, AArch64::B26 },
3593 : { 91U, AArch64::B27 },
3594 : { 92U, AArch64::B28 },
3595 : { 93U, AArch64::B29 },
3596 : { 94U, AArch64::B30 },
3597 : { 95U, AArch64::B31 },
3598 : { 96U, AArch64::Z0 },
3599 : { 97U, AArch64::Z1 },
3600 : { 98U, AArch64::Z2 },
3601 : { 99U, AArch64::Z3 },
3602 : { 100U, AArch64::Z4 },
3603 : { 101U, AArch64::Z5 },
3604 : { 102U, AArch64::Z6 },
3605 : { 103U, AArch64::Z7 },
3606 : { 104U, AArch64::Z8 },
3607 : { 105U, AArch64::Z9 },
3608 : { 106U, AArch64::Z10 },
3609 : { 107U, AArch64::Z11 },
3610 : { 108U, AArch64::Z12 },
3611 : { 109U, AArch64::Z13 },
3612 : { 110U, AArch64::Z14 },
3613 : { 111U, AArch64::Z15 },
3614 : { 112U, AArch64::Z16 },
3615 : { 113U, AArch64::Z17 },
3616 : { 114U, AArch64::Z18 },
3617 : { 115U, AArch64::Z19 },
3618 : { 116U, AArch64::Z20 },
3619 : { 117U, AArch64::Z21 },
3620 : { 118U, AArch64::Z22 },
3621 : { 119U, AArch64::Z23 },
3622 : { 120U, AArch64::Z24 },
3623 : { 121U, AArch64::Z25 },
3624 : { 122U, AArch64::Z26 },
3625 : { 123U, AArch64::Z27 },
3626 : { 124U, AArch64::Z28 },
3627 : { 125U, AArch64::Z29 },
3628 : { 126U, AArch64::Z30 },
3629 : { 127U, AArch64::Z31 },
3630 : };
3631 : extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
3632 :
3633 : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
3634 : { 0U, AArch64::W0 },
3635 : { 1U, AArch64::W1 },
3636 : { 2U, AArch64::W2 },
3637 : { 3U, AArch64::W3 },
3638 : { 4U, AArch64::W4 },
3639 : { 5U, AArch64::W5 },
3640 : { 6U, AArch64::W6 },
3641 : { 7U, AArch64::W7 },
3642 : { 8U, AArch64::W8 },
3643 : { 9U, AArch64::W9 },
3644 : { 10U, AArch64::W10 },
3645 : { 11U, AArch64::W11 },
3646 : { 12U, AArch64::W12 },
3647 : { 13U, AArch64::W13 },
3648 : { 14U, AArch64::W14 },
3649 : { 15U, AArch64::W15 },
3650 : { 16U, AArch64::W16 },
3651 : { 17U, AArch64::W17 },
3652 : { 18U, AArch64::W18 },
3653 : { 19U, AArch64::W19 },
3654 : { 20U, AArch64::W20 },
3655 : { 21U, AArch64::W21 },
3656 : { 22U, AArch64::W22 },
3657 : { 23U, AArch64::W23 },
3658 : { 24U, AArch64::W24 },
3659 : { 25U, AArch64::W25 },
3660 : { 26U, AArch64::W26 },
3661 : { 27U, AArch64::W27 },
3662 : { 28U, AArch64::W28 },
3663 : { 29U, AArch64::W29 },
3664 : { 30U, AArch64::W30 },
3665 : { 31U, AArch64::WSP },
3666 : { 47U, AArch64::FFR },
3667 : { 48U, AArch64::P0 },
3668 : { 49U, AArch64::P1 },
3669 : { 50U, AArch64::P2 },
3670 : { 51U, AArch64::P3 },
3671 : { 52U, AArch64::P4 },
3672 : { 53U, AArch64::P5 },
3673 : { 54U, AArch64::P6 },
3674 : { 55U, AArch64::P7 },
3675 : { 56U, AArch64::P8 },
3676 : { 57U, AArch64::P9 },
3677 : { 58U, AArch64::P10 },
3678 : { 59U, AArch64::P11 },
3679 : { 60U, AArch64::P12 },
3680 : { 61U, AArch64::P13 },
3681 : { 62U, AArch64::P14 },
3682 : { 63U, AArch64::P15 },
3683 : { 64U, AArch64::B0 },
3684 : { 65U, AArch64::B1 },
3685 : { 66U, AArch64::B2 },
3686 : { 67U, AArch64::B3 },
3687 : { 68U, AArch64::B4 },
3688 : { 69U, AArch64::B5 },
3689 : { 70U, AArch64::B6 },
3690 : { 71U, AArch64::B7 },
3691 : { 72U, AArch64::B8 },
3692 : { 73U, AArch64::B9 },
3693 : { 74U, AArch64::B10 },
3694 : { 75U, AArch64::B11 },
3695 : { 76U, AArch64::B12 },
3696 : { 77U, AArch64::B13 },
3697 : { 78U, AArch64::B14 },
3698 : { 79U, AArch64::B15 },
3699 : { 80U, AArch64::B16 },
3700 : { 81U, AArch64::B17 },
3701 : { 82U, AArch64::B18 },
3702 : { 83U, AArch64::B19 },
3703 : { 84U, AArch64::B20 },
3704 : { 85U, AArch64::B21 },
3705 : { 86U, AArch64::B22 },
3706 : { 87U, AArch64::B23 },
3707 : { 88U, AArch64::B24 },
3708 : { 89U, AArch64::B25 },
3709 : { 90U, AArch64::B26 },
3710 : { 91U, AArch64::B27 },
3711 : { 92U, AArch64::B28 },
3712 : { 93U, AArch64::B29 },
3713 : { 94U, AArch64::B30 },
3714 : { 95U, AArch64::B31 },
3715 : { 96U, AArch64::Z0 },
3716 : { 97U, AArch64::Z1 },
3717 : { 98U, AArch64::Z2 },
3718 : { 99U, AArch64::Z3 },
3719 : { 100U, AArch64::Z4 },
3720 : { 101U, AArch64::Z5 },
3721 : { 102U, AArch64::Z6 },
3722 : { 103U, AArch64::Z7 },
3723 : { 104U, AArch64::Z8 },
3724 : { 105U, AArch64::Z9 },
3725 : { 106U, AArch64::Z10 },
3726 : { 107U, AArch64::Z11 },
3727 : { 108U, AArch64::Z12 },
3728 : { 109U, AArch64::Z13 },
3729 : { 110U, AArch64::Z14 },
3730 : { 111U, AArch64::Z15 },
3731 : { 112U, AArch64::Z16 },
3732 : { 113U, AArch64::Z17 },
3733 : { 114U, AArch64::Z18 },
3734 : { 115U, AArch64::Z19 },
3735 : { 116U, AArch64::Z20 },
3736 : { 117U, AArch64::Z21 },
3737 : { 118U, AArch64::Z22 },
3738 : { 119U, AArch64::Z23 },
3739 : { 120U, AArch64::Z24 },
3740 : { 121U, AArch64::Z25 },
3741 : { 122U, AArch64::Z26 },
3742 : { 123U, AArch64::Z27 },
3743 : { 124U, AArch64::Z28 },
3744 : { 125U, AArch64::Z29 },
3745 : { 126U, AArch64::Z30 },
3746 : { 127U, AArch64::Z31 },
3747 : };
3748 : extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
3749 :
3750 : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
3751 : { AArch64::FFR, 47U },
3752 : { AArch64::FP, 29U },
3753 : { AArch64::LR, 30U },
3754 : { AArch64::SP, 31U },
3755 : { AArch64::WSP, 31U },
3756 : { AArch64::WZR, 31U },
3757 : { AArch64::XZR, 31U },
3758 : { AArch64::B0, 64U },
3759 : { AArch64::B1, 65U },
3760 : { AArch64::B2, 66U },
3761 : { AArch64::B3, 67U },
3762 : { AArch64::B4, 68U },
3763 : { AArch64::B5, 69U },
3764 : { AArch64::B6, 70U },
3765 : { AArch64::B7, 71U },
3766 : { AArch64::B8, 72U },
3767 : { AArch64::B9, 73U },
3768 : { AArch64::B10, 74U },
3769 : { AArch64::B11, 75U },
3770 : { AArch64::B12, 76U },
3771 : { AArch64::B13, 77U },
3772 : { AArch64::B14, 78U },
3773 : { AArch64::B15, 79U },
3774 : { AArch64::B16, 80U },
3775 : { AArch64::B17, 81U },
3776 : { AArch64::B18, 82U },
3777 : { AArch64::B19, 83U },
3778 : { AArch64::B20, 84U },
3779 : { AArch64::B21, 85U },
3780 : { AArch64::B22, 86U },
3781 : { AArch64::B23, 87U },
3782 : { AArch64::B24, 88U },
3783 : { AArch64::B25, 89U },
3784 : { AArch64::B26, 90U },
3785 : { AArch64::B27, 91U },
3786 : { AArch64::B28, 92U },
3787 : { AArch64::B29, 93U },
3788 : { AArch64::B30, 94U },
3789 : { AArch64::B31, 95U },
3790 : { AArch64::D0, 64U },
3791 : { AArch64::D1, 65U },
3792 : { AArch64::D2, 66U },
3793 : { AArch64::D3, 67U },
3794 : { AArch64::D4, 68U },
3795 : { AArch64::D5, 69U },
3796 : { AArch64::D6, 70U },
3797 : { AArch64::D7, 71U },
3798 : { AArch64::D8, 72U },
3799 : { AArch64::D9, 73U },
3800 : { AArch64::D10, 74U },
3801 : { AArch64::D11, 75U },
3802 : { AArch64::D12, 76U },
3803 : { AArch64::D13, 77U },
3804 : { AArch64::D14, 78U },
3805 : { AArch64::D15, 79U },
3806 : { AArch64::D16, 80U },
3807 : { AArch64::D17, 81U },
3808 : { AArch64::D18, 82U },
3809 : { AArch64::D19, 83U },
3810 : { AArch64::D20, 84U },
3811 : { AArch64::D21, 85U },
3812 : { AArch64::D22, 86U },
3813 : { AArch64::D23, 87U },
3814 : { AArch64::D24, 88U },
3815 : { AArch64::D25, 89U },
3816 : { AArch64::D26, 90U },
3817 : { AArch64::D27, 91U },
3818 : { AArch64::D28, 92U },
3819 : { AArch64::D29, 93U },
3820 : { AArch64::D30, 94U },
3821 : { AArch64::D31, 95U },
3822 : { AArch64::H0, 64U },
3823 : { AArch64::H1, 65U },
3824 : { AArch64::H2, 66U },
3825 : { AArch64::H3, 67U },
3826 : { AArch64::H4, 68U },
3827 : { AArch64::H5, 69U },
3828 : { AArch64::H6, 70U },
3829 : { AArch64::H7, 71U },
3830 : { AArch64::H8, 72U },
3831 : { AArch64::H9, 73U },
3832 : { AArch64::H10, 74U },
3833 : { AArch64::H11, 75U },
3834 : { AArch64::H12, 76U },
3835 : { AArch64::H13, 77U },
3836 : { AArch64::H14, 78U },
3837 : { AArch64::H15, 79U },
3838 : { AArch64::H16, 80U },
3839 : { AArch64::H17, 81U },
3840 : { AArch64::H18, 82U },
3841 : { AArch64::H19, 83U },
3842 : { AArch64::H20, 84U },
3843 : { AArch64::H21, 85U },
3844 : { AArch64::H22, 86U },
3845 : { AArch64::H23, 87U },
3846 : { AArch64::H24, 88U },
3847 : { AArch64::H25, 89U },
3848 : { AArch64::H26, 90U },
3849 : { AArch64::H27, 91U },
3850 : { AArch64::H28, 92U },
3851 : { AArch64::H29, 93U },
3852 : { AArch64::H30, 94U },
3853 : { AArch64::H31, 95U },
3854 : { AArch64::P0, 48U },
3855 : { AArch64::P1, 49U },
3856 : { AArch64::P2, 50U },
3857 : { AArch64::P3, 51U },
3858 : { AArch64::P4, 52U },
3859 : { AArch64::P5, 53U },
3860 : { AArch64::P6, 54U },
3861 : { AArch64::P7, 55U },
3862 : { AArch64::P8, 56U },
3863 : { AArch64::P9, 57U },
3864 : { AArch64::P10, 58U },
3865 : { AArch64::P11, 59U },
3866 : { AArch64::P12, 60U },
3867 : { AArch64::P13, 61U },
3868 : { AArch64::P14, 62U },
3869 : { AArch64::P15, 63U },
3870 : { AArch64::Q0, 64U },
3871 : { AArch64::Q1, 65U },
3872 : { AArch64::Q2, 66U },
3873 : { AArch64::Q3, 67U },
3874 : { AArch64::Q4, 68U },
3875 : { AArch64::Q5, 69U },
3876 : { AArch64::Q6, 70U },
3877 : { AArch64::Q7, 71U },
3878 : { AArch64::Q8, 72U },
3879 : { AArch64::Q9, 73U },
3880 : { AArch64::Q10, 74U },
3881 : { AArch64::Q11, 75U },
3882 : { AArch64::Q12, 76U },
3883 : { AArch64::Q13, 77U },
3884 : { AArch64::Q14, 78U },
3885 : { AArch64::Q15, 79U },
3886 : { AArch64::Q16, 80U },
3887 : { AArch64::Q17, 81U },
3888 : { AArch64::Q18, 82U },
3889 : { AArch64::Q19, 83U },
3890 : { AArch64::Q20, 84U },
3891 : { AArch64::Q21, 85U },
3892 : { AArch64::Q22, 86U },
3893 : { AArch64::Q23, 87U },
3894 : { AArch64::Q24, 88U },
3895 : { AArch64::Q25, 89U },
3896 : { AArch64::Q26, 90U },
3897 : { AArch64::Q27, 91U },
3898 : { AArch64::Q28, 92U },
3899 : { AArch64::Q29, 93U },
3900 : { AArch64::Q30, 94U },
3901 : { AArch64::Q31, 95U },
3902 : { AArch64::S0, 64U },
3903 : { AArch64::S1, 65U },
3904 : { AArch64::S2, 66U },
3905 : { AArch64::S3, 67U },
3906 : { AArch64::S4, 68U },
3907 : { AArch64::S5, 69U },
3908 : { AArch64::S6, 70U },
3909 : { AArch64::S7, 71U },
3910 : { AArch64::S8, 72U },
3911 : { AArch64::S9, 73U },
3912 : { AArch64::S10, 74U },
3913 : { AArch64::S11, 75U },
3914 : { AArch64::S12, 76U },
3915 : { AArch64::S13, 77U },
3916 : { AArch64::S14, 78U },
3917 : { AArch64::S15, 79U },
3918 : { AArch64::S16, 80U },
3919 : { AArch64::S17, 81U },
3920 : { AArch64::S18, 82U },
3921 : { AArch64::S19, 83U },
3922 : { AArch64::S20, 84U },
3923 : { AArch64::S21, 85U },
3924 : { AArch64::S22, 86U },
3925 : { AArch64::S23, 87U },
3926 : { AArch64::S24, 88U },
3927 : { AArch64::S25, 89U },
3928 : { AArch64::S26, 90U },
3929 : { AArch64::S27, 91U },
3930 : { AArch64::S28, 92U },
3931 : { AArch64::S29, 93U },
3932 : { AArch64::S30, 94U },
3933 : { AArch64::S31, 95U },
3934 : { AArch64::W0, 0U },
3935 : { AArch64::W1, 1U },
3936 : { AArch64::W2, 2U },
3937 : { AArch64::W3, 3U },
3938 : { AArch64::W4, 4U },
3939 : { AArch64::W5, 5U },
3940 : { AArch64::W6, 6U },
3941 : { AArch64::W7, 7U },
3942 : { AArch64::W8, 8U },
3943 : { AArch64::W9, 9U },
3944 : { AArch64::W10, 10U },
3945 : { AArch64::W11, 11U },
3946 : { AArch64::W12, 12U },
3947 : { AArch64::W13, 13U },
3948 : { AArch64::W14, 14U },
3949 : { AArch64::W15, 15U },
3950 : { AArch64::W16, 16U },
3951 : { AArch64::W17, 17U },
3952 : { AArch64::W18, 18U },
3953 : { AArch64::W19, 19U },
3954 : { AArch64::W20, 20U },
3955 : { AArch64::W21, 21U },
3956 : { AArch64::W22, 22U },
3957 : { AArch64::W23, 23U },
3958 : { AArch64::W24, 24U },
3959 : { AArch64::W25, 25U },
3960 : { AArch64::W26, 26U },
3961 : { AArch64::W27, 27U },
3962 : { AArch64::W28, 28U },
3963 : { AArch64::W29, 29U },
3964 : { AArch64::W30, 30U },
3965 : { AArch64::X0, 0U },
3966 : { AArch64::X1, 1U },
3967 : { AArch64::X2, 2U },
3968 : { AArch64::X3, 3U },
3969 : { AArch64::X4, 4U },
3970 : { AArch64::X5, 5U },
3971 : { AArch64::X6, 6U },
3972 : { AArch64::X7, 7U },
3973 : { AArch64::X8, 8U },
3974 : { AArch64::X9, 9U },
3975 : { AArch64::X10, 10U },
3976 : { AArch64::X11, 11U },
3977 : { AArch64::X12, 12U },
3978 : { AArch64::X13, 13U },
3979 : { AArch64::X14, 14U },
3980 : { AArch64::X15, 15U },
3981 : { AArch64::X16, 16U },
3982 : { AArch64::X17, 17U },
3983 : { AArch64::X18, 18U },
3984 : { AArch64::X19, 19U },
3985 : { AArch64::X20, 20U },
3986 : { AArch64::X21, 21U },
3987 : { AArch64::X22, 22U },
3988 : { AArch64::X23, 23U },
3989 : { AArch64::X24, 24U },
3990 : { AArch64::X25, 25U },
3991 : { AArch64::X26, 26U },
3992 : { AArch64::X27, 27U },
3993 : { AArch64::X28, 28U },
3994 : { AArch64::Z0, 96U },
3995 : { AArch64::Z1, 97U },
3996 : { AArch64::Z2, 98U },
3997 : { AArch64::Z3, 99U },
3998 : { AArch64::Z4, 100U },
3999 : { AArch64::Z5, 101U },
4000 : { AArch64::Z6, 102U },
4001 : { AArch64::Z7, 103U },
4002 : { AArch64::Z8, 104U },
4003 : { AArch64::Z9, 105U },
4004 : { AArch64::Z10, 106U },
4005 : { AArch64::Z11, 107U },
4006 : { AArch64::Z12, 108U },
4007 : { AArch64::Z13, 109U },
4008 : { AArch64::Z14, 110U },
4009 : { AArch64::Z15, 111U },
4010 : { AArch64::Z16, 112U },
4011 : { AArch64::Z17, 113U },
4012 : { AArch64::Z18, 114U },
4013 : { AArch64::Z19, 115U },
4014 : { AArch64::Z20, 116U },
4015 : { AArch64::Z21, 117U },
4016 : { AArch64::Z22, 118U },
4017 : { AArch64::Z23, 119U },
4018 : { AArch64::Z24, 120U },
4019 : { AArch64::Z25, 121U },
4020 : { AArch64::Z26, 122U },
4021 : { AArch64::Z27, 123U },
4022 : { AArch64::Z28, 124U },
4023 : { AArch64::Z29, 125U },
4024 : { AArch64::Z30, 126U },
4025 : { AArch64::Z31, 127U },
4026 : };
4027 : extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
4028 :
4029 : extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
4030 : { AArch64::FFR, 47U },
4031 : { AArch64::FP, 29U },
4032 : { AArch64::LR, 30U },
4033 : { AArch64::SP, 31U },
4034 : { AArch64::WSP, 31U },
4035 : { AArch64::WZR, 31U },
4036 : { AArch64::XZR, 31U },
4037 : { AArch64::B0, 64U },
4038 : { AArch64::B1, 65U },
4039 : { AArch64::B2, 66U },
4040 : { AArch64::B3, 67U },
4041 : { AArch64::B4, 68U },
4042 : { AArch64::B5, 69U },
4043 : { AArch64::B6, 70U },
4044 : { AArch64::B7, 71U },
4045 : { AArch64::B8, 72U },
4046 : { AArch64::B9, 73U },
4047 : { AArch64::B10, 74U },
4048 : { AArch64::B11, 75U },
4049 : { AArch64::B12, 76U },
4050 : { AArch64::B13, 77U },
4051 : { AArch64::B14, 78U },
4052 : { AArch64::B15, 79U },
4053 : { AArch64::B16, 80U },
4054 : { AArch64::B17, 81U },
4055 : { AArch64::B18, 82U },
4056 : { AArch64::B19, 83U },
4057 : { AArch64::B20, 84U },
4058 : { AArch64::B21, 85U },
4059 : { AArch64::B22, 86U },
4060 : { AArch64::B23, 87U },
4061 : { AArch64::B24, 88U },
4062 : { AArch64::B25, 89U },
4063 : { AArch64::B26, 90U },
4064 : { AArch64::B27, 91U },
4065 : { AArch64::B28, 92U },
4066 : { AArch64::B29, 93U },
4067 : { AArch64::B30, 94U },
4068 : { AArch64::B31, 95U },
4069 : { AArch64::D0, 64U },
4070 : { AArch64::D1, 65U },
4071 : { AArch64::D2, 66U },
4072 : { AArch64::D3, 67U },
4073 : { AArch64::D4, 68U },
4074 : { AArch64::D5, 69U },
4075 : { AArch64::D6, 70U },
4076 : { AArch64::D7, 71U },
4077 : { AArch64::D8, 72U },
4078 : { AArch64::D9, 73U },
4079 : { AArch64::D10, 74U },
4080 : { AArch64::D11, 75U },
4081 : { AArch64::D12, 76U },
4082 : { AArch64::D13, 77U },
4083 : { AArch64::D14, 78U },
4084 : { AArch64::D15, 79U },
4085 : { AArch64::D16, 80U },
4086 : { AArch64::D17, 81U },
4087 : { AArch64::D18, 82U },
4088 : { AArch64::D19, 83U },
4089 : { AArch64::D20, 84U },
4090 : { AArch64::D21, 85U },
4091 : { AArch64::D22, 86U },
4092 : { AArch64::D23, 87U },
4093 : { AArch64::D24, 88U },
4094 : { AArch64::D25, 89U },
4095 : { AArch64::D26, 90U },
4096 : { AArch64::D27, 91U },
4097 : { AArch64::D28, 92U },
4098 : { AArch64::D29, 93U },
4099 : { AArch64::D30, 94U },
4100 : { AArch64::D31, 95U },
4101 : { AArch64::H0, 64U },
4102 : { AArch64::H1, 65U },
4103 : { AArch64::H2, 66U },
4104 : { AArch64::H3, 67U },
4105 : { AArch64::H4, 68U },
4106 : { AArch64::H5, 69U },
4107 : { AArch64::H6, 70U },
4108 : { AArch64::H7, 71U },
4109 : { AArch64::H8, 72U },
4110 : { AArch64::H9, 73U },
4111 : { AArch64::H10, 74U },
4112 : { AArch64::H11, 75U },
4113 : { AArch64::H12, 76U },
4114 : { AArch64::H13, 77U },
4115 : { AArch64::H14, 78U },
4116 : { AArch64::H15, 79U },
4117 : { AArch64::H16, 80U },
4118 : { AArch64::H17, 81U },
4119 : { AArch64::H18, 82U },
4120 : { AArch64::H19, 83U },
4121 : { AArch64::H20, 84U },
4122 : { AArch64::H21, 85U },
4123 : { AArch64::H22, 86U },
4124 : { AArch64::H23, 87U },
4125 : { AArch64::H24, 88U },
4126 : { AArch64::H25, 89U },
4127 : { AArch64::H26, 90U },
4128 : { AArch64::H27, 91U },
4129 : { AArch64::H28, 92U },
4130 : { AArch64::H29, 93U },
4131 : { AArch64::H30, 94U },
4132 : { AArch64::H31, 95U },
4133 : { AArch64::P0, 48U },
4134 : { AArch64::P1, 49U },
4135 : { AArch64::P2, 50U },
4136 : { AArch64::P3, 51U },
4137 : { AArch64::P4, 52U },
4138 : { AArch64::P5, 53U },
4139 : { AArch64::P6, 54U },
4140 : { AArch64::P7, 55U },
4141 : { AArch64::P8, 56U },
4142 : { AArch64::P9, 57U },
4143 : { AArch64::P10, 58U },
4144 : { AArch64::P11, 59U },
4145 : { AArch64::P12, 60U },
4146 : { AArch64::P13, 61U },
4147 : { AArch64::P14, 62U },
4148 : { AArch64::P15, 63U },
4149 : { AArch64::Q0, 64U },
4150 : { AArch64::Q1, 65U },
4151 : { AArch64::Q2, 66U },
4152 : { AArch64::Q3, 67U },
4153 : { AArch64::Q4, 68U },
4154 : { AArch64::Q5, 69U },
4155 : { AArch64::Q6, 70U },
4156 : { AArch64::Q7, 71U },
4157 : { AArch64::Q8, 72U },
4158 : { AArch64::Q9, 73U },
4159 : { AArch64::Q10, 74U },
4160 : { AArch64::Q11, 75U },
4161 : { AArch64::Q12, 76U },
4162 : { AArch64::Q13, 77U },
4163 : { AArch64::Q14, 78U },
4164 : { AArch64::Q15, 79U },
4165 : { AArch64::Q16, 80U },
4166 : { AArch64::Q17, 81U },
4167 : { AArch64::Q18, 82U },
4168 : { AArch64::Q19, 83U },
4169 : { AArch64::Q20, 84U },
4170 : { AArch64::Q21, 85U },
4171 : { AArch64::Q22, 86U },
4172 : { AArch64::Q23, 87U },
4173 : { AArch64::Q24, 88U },
4174 : { AArch64::Q25, 89U },
4175 : { AArch64::Q26, 90U },
4176 : { AArch64::Q27, 91U },
4177 : { AArch64::Q28, 92U },
4178 : { AArch64::Q29, 93U },
4179 : { AArch64::Q30, 94U },
4180 : { AArch64::Q31, 95U },
4181 : { AArch64::S0, 64U },
4182 : { AArch64::S1, 65U },
4183 : { AArch64::S2, 66U },
4184 : { AArch64::S3, 67U },
4185 : { AArch64::S4, 68U },
4186 : { AArch64::S5, 69U },
4187 : { AArch64::S6, 70U },
4188 : { AArch64::S7, 71U },
4189 : { AArch64::S8, 72U },
4190 : { AArch64::S9, 73U },
4191 : { AArch64::S10, 74U },
4192 : { AArch64::S11, 75U },
4193 : { AArch64::S12, 76U },
4194 : { AArch64::S13, 77U },
4195 : { AArch64::S14, 78U },
4196 : { AArch64::S15, 79U },
4197 : { AArch64::S16, 80U },
4198 : { AArch64::S17, 81U },
4199 : { AArch64::S18, 82U },
4200 : { AArch64::S19, 83U },
4201 : { AArch64::S20, 84U },
4202 : { AArch64::S21, 85U },
4203 : { AArch64::S22, 86U },
4204 : { AArch64::S23, 87U },
4205 : { AArch64::S24, 88U },
4206 : { AArch64::S25, 89U },
4207 : { AArch64::S26, 90U },
4208 : { AArch64::S27, 91U },
4209 : { AArch64::S28, 92U },
4210 : { AArch64::S29, 93U },
4211 : { AArch64::S30, 94U },
4212 : { AArch64::S31, 95U },
4213 : { AArch64::W0, 0U },
4214 : { AArch64::W1, 1U },
4215 : { AArch64::W2, 2U },
4216 : { AArch64::W3, 3U },
4217 : { AArch64::W4, 4U },
4218 : { AArch64::W5, 5U },
4219 : { AArch64::W6, 6U },
4220 : { AArch64::W7, 7U },
4221 : { AArch64::W8, 8U },
4222 : { AArch64::W9, 9U },
4223 : { AArch64::W10, 10U },
4224 : { AArch64::W11, 11U },
4225 : { AArch64::W12, 12U },
4226 : { AArch64::W13, 13U },
4227 : { AArch64::W14, 14U },
4228 : { AArch64::W15, 15U },
4229 : { AArch64::W16, 16U },
4230 : { AArch64::W17, 17U },
4231 : { AArch64::W18, 18U },
4232 : { AArch64::W19, 19U },
4233 : { AArch64::W20, 20U },
4234 : { AArch64::W21, 21U },
4235 : { AArch64::W22, 22U },
4236 : { AArch64::W23, 23U },
4237 : { AArch64::W24, 24U },
4238 : { AArch64::W25, 25U },
4239 : { AArch64::W26, 26U },
4240 : { AArch64::W27, 27U },
4241 : { AArch64::W28, 28U },
4242 : { AArch64::W29, 29U },
4243 : { AArch64::W30, 30U },
4244 : { AArch64::X0, 0U },
4245 : { AArch64::X1, 1U },
4246 : { AArch64::X2, 2U },
4247 : { AArch64::X3, 3U },
4248 : { AArch64::X4, 4U },
4249 : { AArch64::X5, 5U },
4250 : { AArch64::X6, 6U },
4251 : { AArch64::X7, 7U },
4252 : { AArch64::X8, 8U },
4253 : { AArch64::X9, 9U },
4254 : { AArch64::X10, 10U },
4255 : { AArch64::X11, 11U },
4256 : { AArch64::X12, 12U },
4257 : { AArch64::X13, 13U },
4258 : { AArch64::X14, 14U },
4259 : { AArch64::X15, 15U },
4260 : { AArch64::X16, 16U },
4261 : { AArch64::X17, 17U },
4262 : { AArch64::X18, 18U },
4263 : { AArch64::X19, 19U },
4264 : { AArch64::X20, 20U },
4265 : { AArch64::X21, 21U },
4266 : { AArch64::X22, 22U },
4267 : { AArch64::X23, 23U },
4268 : { AArch64::X24, 24U },
4269 : { AArch64::X25, 25U },
4270 : { AArch64::X26, 26U },
4271 : { AArch64::X27, 27U },
4272 : { AArch64::X28, 28U },
4273 : { AArch64::Z0, 96U },
4274 : { AArch64::Z1, 97U },
4275 : { AArch64::Z2, 98U },
4276 : { AArch64::Z3, 99U },
4277 : { AArch64::Z4, 100U },
4278 : { AArch64::Z5, 101U },
4279 : { AArch64::Z6, 102U },
4280 : { AArch64::Z7, 103U },
4281 : { AArch64::Z8, 104U },
4282 : { AArch64::Z9, 105U },
4283 : { AArch64::Z10, 106U },
4284 : { AArch64::Z11, 107U },
4285 : { AArch64::Z12, 108U },
4286 : { AArch64::Z13, 109U },
4287 : { AArch64::Z14, 110U },
4288 : { AArch64::Z15, 111U },
4289 : { AArch64::Z16, 112U },
4290 : { AArch64::Z17, 113U },
4291 : { AArch64::Z18, 114U },
4292 : { AArch64::Z19, 115U },
4293 : { AArch64::Z20, 116U },
4294 : { AArch64::Z21, 117U },
4295 : { AArch64::Z22, 118U },
4296 : { AArch64::Z23, 119U },
4297 : { AArch64::Z24, 120U },
4298 : { AArch64::Z25, 121U },
4299 : { AArch64::Z26, 122U },
4300 : { AArch64::Z27, 123U },
4301 : { AArch64::Z28, 124U },
4302 : { AArch64::Z29, 125U },
4303 : { AArch64::Z30, 126U },
4304 : { AArch64::Z31, 127U },
4305 : };
4306 : extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
4307 :
4308 : extern const uint16_t AArch64RegEncodingTable[] = {
4309 : 0,
4310 : 0,
4311 : 29,
4312 : 30,
4313 : 0,
4314 : 31,
4315 : 31,
4316 : 31,
4317 : 31,
4318 : 0,
4319 : 1,
4320 : 2,
4321 : 3,
4322 : 4,
4323 : 5,
4324 : 6,
4325 : 7,
4326 : 8,
4327 : 9,
4328 : 10,
4329 : 11,
4330 : 12,
4331 : 13,
4332 : 14,
4333 : 15,
4334 : 16,
4335 : 17,
4336 : 18,
4337 : 19,
4338 : 20,
4339 : 21,
4340 : 22,
4341 : 23,
4342 : 24,
4343 : 25,
4344 : 26,
4345 : 27,
4346 : 28,
4347 : 29,
4348 : 30,
4349 : 31,
4350 : 0,
4351 : 1,
4352 : 2,
4353 : 3,
4354 : 4,
4355 : 5,
4356 : 6,
4357 : 7,
4358 : 8,
4359 : 9,
4360 : 10,
4361 : 11,
4362 : 12,
4363 : 13,
4364 : 14,
4365 : 15,
4366 : 16,
4367 : 17,
4368 : 18,
4369 : 19,
4370 : 20,
4371 : 21,
4372 : 22,
4373 : 23,
4374 : 24,
4375 : 25,
4376 : 26,
4377 : 27,
4378 : 28,
4379 : 29,
4380 : 30,
4381 : 31,
4382 : 0,
4383 : 1,
4384 : 2,
4385 : 3,
4386 : 4,
4387 : 5,
4388 : 6,
4389 : 7,
4390 : 8,
4391 : 9,
4392 : 10,
4393 : 11,
4394 : 12,
4395 : 13,
4396 : 14,
4397 : 15,
4398 : 16,
4399 : 17,
4400 : 18,
4401 : 19,
4402 : 20,
4403 : 21,
4404 : 22,
4405 : 23,
4406 : 24,
4407 : 25,
4408 : 26,
4409 : 27,
4410 : 28,
4411 : 29,
4412 : 30,
4413 : 31,
4414 : 0,
4415 : 1,
4416 : 2,
4417 : 3,
4418 : 4,
4419 : 5,
4420 : 6,
4421 : 7,
4422 : 8,
4423 : 9,
4424 : 10,
4425 : 11,
4426 : 12,
4427 : 13,
4428 : 14,
4429 : 15,
4430 : 0,
4431 : 1,
4432 : 2,
4433 : 3,
4434 : 4,
4435 : 5,
4436 : 6,
4437 : 7,
4438 : 8,
4439 : 9,
4440 : 10,
4441 : 11,
4442 : 12,
4443 : 13,
4444 : 14,
4445 : 15,
4446 : 16,
4447 : 17,
4448 : 18,
4449 : 19,
4450 : 20,
4451 : 21,
4452 : 22,
4453 : 23,
4454 : 24,
4455 : 25,
4456 : 26,
4457 : 27,
4458 : 28,
4459 : 29,
4460 : 30,
4461 : 31,
4462 : 0,
4463 : 1,
4464 : 2,
4465 : 3,
4466 : 4,
4467 : 5,
4468 : 6,
4469 : 7,
4470 : 8,
4471 : 9,
4472 : 10,
4473 : 11,
4474 : 12,
4475 : 13,
4476 : 14,
4477 : 15,
4478 : 16,
4479 : 17,
4480 : 18,
4481 : 19,
4482 : 20,
4483 : 21,
4484 : 22,
4485 : 23,
4486 : 24,
4487 : 25,
4488 : 26,
4489 : 27,
4490 : 28,
4491 : 29,
4492 : 30,
4493 : 31,
4494 : 0,
4495 : 1,
4496 : 2,
4497 : 3,
4498 : 4,
4499 : 5,
4500 : 6,
4501 : 7,
4502 : 8,
4503 : 9,
4504 : 10,
4505 : 11,
4506 : 12,
4507 : 13,
4508 : 14,
4509 : 15,
4510 : 16,
4511 : 17,
4512 : 18,
4513 : 19,
4514 : 20,
4515 : 21,
4516 : 22,
4517 : 23,
4518 : 24,
4519 : 25,
4520 : 26,
4521 : 27,
4522 : 28,
4523 : 29,
4524 : 30,
4525 : 0,
4526 : 1,
4527 : 2,
4528 : 3,
4529 : 4,
4530 : 5,
4531 : 6,
4532 : 7,
4533 : 8,
4534 : 9,
4535 : 10,
4536 : 11,
4537 : 12,
4538 : 13,
4539 : 14,
4540 : 15,
4541 : 16,
4542 : 17,
4543 : 18,
4544 : 19,
4545 : 20,
4546 : 21,
4547 : 22,
4548 : 23,
4549 : 24,
4550 : 25,
4551 : 26,
4552 : 27,
4553 : 28,
4554 : 0,
4555 : 1,
4556 : 2,
4557 : 3,
4558 : 4,
4559 : 5,
4560 : 6,
4561 : 7,
4562 : 8,
4563 : 9,
4564 : 10,
4565 : 11,
4566 : 12,
4567 : 13,
4568 : 14,
4569 : 15,
4570 : 16,
4571 : 17,
4572 : 18,
4573 : 19,
4574 : 20,
4575 : 21,
4576 : 22,
4577 : 23,
4578 : 24,
4579 : 25,
4580 : 26,
4581 : 27,
4582 : 28,
4583 : 29,
4584 : 30,
4585 : 31,
4586 : 0,
4587 : 1,
4588 : 2,
4589 : 3,
4590 : 4,
4591 : 5,
4592 : 6,
4593 : 7,
4594 : 8,
4595 : 9,
4596 : 10,
4597 : 11,
4598 : 12,
4599 : 13,
4600 : 14,
4601 : 15,
4602 : 16,
4603 : 17,
4604 : 18,
4605 : 19,
4606 : 20,
4607 : 21,
4608 : 22,
4609 : 23,
4610 : 24,
4611 : 25,
4612 : 26,
4613 : 27,
4614 : 28,
4615 : 29,
4616 : 30,
4617 : 31,
4618 : 0,
4619 : 1,
4620 : 2,
4621 : 3,
4622 : 4,
4623 : 5,
4624 : 6,
4625 : 7,
4626 : 8,
4627 : 9,
4628 : 10,
4629 : 11,
4630 : 12,
4631 : 13,
4632 : 14,
4633 : 15,
4634 : 16,
4635 : 17,
4636 : 18,
4637 : 19,
4638 : 20,
4639 : 21,
4640 : 22,
4641 : 23,
4642 : 24,
4643 : 25,
4644 : 26,
4645 : 27,
4646 : 28,
4647 : 29,
4648 : 30,
4649 : 31,
4650 : 0,
4651 : 1,
4652 : 2,
4653 : 3,
4654 : 4,
4655 : 5,
4656 : 6,
4657 : 7,
4658 : 8,
4659 : 9,
4660 : 10,
4661 : 11,
4662 : 12,
4663 : 13,
4664 : 14,
4665 : 15,
4666 : 16,
4667 : 17,
4668 : 18,
4669 : 19,
4670 : 20,
4671 : 21,
4672 : 22,
4673 : 23,
4674 : 24,
4675 : 25,
4676 : 26,
4677 : 27,
4678 : 28,
4679 : 29,
4680 : 30,
4681 : 31,
4682 : 0,
4683 : 1,
4684 : 2,
4685 : 3,
4686 : 4,
4687 : 5,
4688 : 6,
4689 : 7,
4690 : 8,
4691 : 9,
4692 : 10,
4693 : 11,
4694 : 12,
4695 : 13,
4696 : 14,
4697 : 15,
4698 : 16,
4699 : 17,
4700 : 18,
4701 : 19,
4702 : 20,
4703 : 21,
4704 : 22,
4705 : 23,
4706 : 24,
4707 : 25,
4708 : 26,
4709 : 27,
4710 : 28,
4711 : 29,
4712 : 30,
4713 : 31,
4714 : 0,
4715 : 1,
4716 : 2,
4717 : 3,
4718 : 4,
4719 : 5,
4720 : 6,
4721 : 7,
4722 : 8,
4723 : 9,
4724 : 10,
4725 : 11,
4726 : 12,
4727 : 13,
4728 : 14,
4729 : 15,
4730 : 16,
4731 : 17,
4732 : 18,
4733 : 19,
4734 : 20,
4735 : 21,
4736 : 22,
4737 : 23,
4738 : 24,
4739 : 25,
4740 : 26,
4741 : 27,
4742 : 28,
4743 : 29,
4744 : 30,
4745 : 31,
4746 : 0,
4747 : 1,
4748 : 2,
4749 : 3,
4750 : 4,
4751 : 5,
4752 : 6,
4753 : 7,
4754 : 8,
4755 : 9,
4756 : 10,
4757 : 11,
4758 : 12,
4759 : 13,
4760 : 14,
4761 : 15,
4762 : 16,
4763 : 17,
4764 : 18,
4765 : 19,
4766 : 20,
4767 : 21,
4768 : 22,
4769 : 23,
4770 : 24,
4771 : 25,
4772 : 26,
4773 : 27,
4774 : 28,
4775 : 29,
4776 : 30,
4777 : 31,
4778 : 0,
4779 : 1,
4780 : 2,
4781 : 3,
4782 : 4,
4783 : 5,
4784 : 6,
4785 : 7,
4786 : 8,
4787 : 9,
4788 : 10,
4789 : 11,
4790 : 12,
4791 : 13,
4792 : 14,
4793 : 15,
4794 : 16,
4795 : 17,
4796 : 18,
4797 : 19,
4798 : 20,
4799 : 21,
4800 : 22,
4801 : 23,
4802 : 24,
4803 : 25,
4804 : 26,
4805 : 27,
4806 : 28,
4807 : 29,
4808 : 30,
4809 : 31,
4810 : 31,
4811 : 30,
4812 : 0,
4813 : 1,
4814 : 2,
4815 : 3,
4816 : 4,
4817 : 5,
4818 : 6,
4819 : 7,
4820 : 8,
4821 : 9,
4822 : 10,
4823 : 11,
4824 : 12,
4825 : 13,
4826 : 14,
4827 : 15,
4828 : 16,
4829 : 17,
4830 : 18,
4831 : 19,
4832 : 20,
4833 : 21,
4834 : 22,
4835 : 23,
4836 : 24,
4837 : 25,
4838 : 26,
4839 : 27,
4840 : 28,
4841 : 29,
4842 : 29,
4843 : 30,
4844 : 31,
4845 : 28,
4846 : 0,
4847 : 1,
4848 : 2,
4849 : 3,
4850 : 4,
4851 : 5,
4852 : 6,
4853 : 7,
4854 : 8,
4855 : 9,
4856 : 10,
4857 : 11,
4858 : 12,
4859 : 13,
4860 : 14,
4861 : 15,
4862 : 16,
4863 : 17,
4864 : 18,
4865 : 19,
4866 : 20,
4867 : 21,
4868 : 22,
4869 : 23,
4870 : 24,
4871 : 25,
4872 : 26,
4873 : 27,
4874 : 0,
4875 : 1,
4876 : 2,
4877 : 3,
4878 : 4,
4879 : 5,
4880 : 6,
4881 : 7,
4882 : 8,
4883 : 9,
4884 : 10,
4885 : 11,
4886 : 12,
4887 : 13,
4888 : 14,
4889 : 15,
4890 : 16,
4891 : 17,
4892 : 18,
4893 : 19,
4894 : 20,
4895 : 21,
4896 : 22,
4897 : 23,
4898 : 24,
4899 : 25,
4900 : 26,
4901 : 27,
4902 : 28,
4903 : 29,
4904 : 30,
4905 : 31,
4906 : 0,
4907 : 1,
4908 : 2,
4909 : 3,
4910 : 4,
4911 : 5,
4912 : 6,
4913 : 7,
4914 : 8,
4915 : 9,
4916 : 10,
4917 : 11,
4918 : 12,
4919 : 13,
4920 : 14,
4921 : 15,
4922 : 16,
4923 : 17,
4924 : 18,
4925 : 19,
4926 : 20,
4927 : 21,
4928 : 22,
4929 : 23,
4930 : 24,
4931 : 25,
4932 : 26,
4933 : 27,
4934 : 28,
4935 : 29,
4936 : 30,
4937 : 31,
4938 : 0,
4939 : 1,
4940 : 2,
4941 : 3,
4942 : 4,
4943 : 5,
4944 : 6,
4945 : 7,
4946 : 8,
4947 : 9,
4948 : 10,
4949 : 11,
4950 : 12,
4951 : 13,
4952 : 14,
4953 : 15,
4954 : 16,
4955 : 17,
4956 : 18,
4957 : 19,
4958 : 20,
4959 : 21,
4960 : 22,
4961 : 23,
4962 : 24,
4963 : 25,
4964 : 26,
4965 : 27,
4966 : 28,
4967 : 29,
4968 : 30,
4969 : 31,
4970 : };
4971 : static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4972 : RI->InitMCRegisterInfo(AArch64RegDesc, 661, RA, PC, AArch64MCRegisterClasses, 104, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100,
4973 : AArch64SubRegIdxRanges, AArch64RegEncodingTable);
4974 :
4975 : switch (DwarfFlavour) {
4976 : default:
4977 : llvm_unreachable("Unknown DWARF flavour");
4978 : case 0:
4979 : RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
4980 : break;
4981 : }
4982 : switch (EHFlavour) {
4983 : default:
4984 : llvm_unreachable("Unknown DWARF flavour");
4985 : case 0:
4986 : RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
4987 : break;
4988 : }
4989 : switch (DwarfFlavour) {
4990 : default:
4991 : llvm_unreachable("Unknown DWARF flavour");
4992 : case 0:
4993 : RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
4994 : break;
4995 : }
4996 : switch (EHFlavour) {
4997 : default:
4998 : llvm_unreachable("Unknown DWARF flavour");
4999 : case 0:
5000 : RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
5001 : break;
5002 : }
5003 : }
5004 :
5005 : } // end namespace llvm
5006 :
5007 : #endif // GET_REGINFO_MC_DESC
5008 :
5009 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5010 : |* *|
5011 : |* Register Information Header Fragment *|
5012 : |* *|
5013 : |* Automatically generated file, do not edit! *|
5014 : |* *|
5015 : \*===----------------------------------------------------------------------===*/
5016 :
5017 :
5018 : #ifdef GET_REGINFO_HEADER
5019 : #undef GET_REGINFO_HEADER
5020 :
5021 : #include "llvm/CodeGen/TargetRegisterInfo.h"
5022 :
5023 : namespace llvm {
5024 :
5025 : class AArch64FrameLowering;
5026 :
5027 : struct AArch64GenRegisterInfo : public TargetRegisterInfo {
5028 : explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5029 : unsigned PC = 0, unsigned HwMode = 0);
5030 : unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5031 : LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5032 : LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5033 : const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
5034 : const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5035 : unsigned getRegUnitWeight(unsigned RegUnit) const override;
5036 : unsigned getNumRegPressureSets() const override;
5037 : const char *getRegPressureSetName(unsigned Idx) const override;
5038 : unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5039 : const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5040 : const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5041 : ArrayRef<const char *> getRegMaskNames() const override;
5042 : ArrayRef<const uint32_t *> getRegMasks() const override;
5043 : /// Devirtualized TargetFrameLowering.
5044 : static const AArch64FrameLowering *getFrameLowering(
5045 : const MachineFunction &MF);
5046 : };
5047 :
5048 : namespace AArch64 { // Register classes
5049 : extern const TargetRegisterClass FPR8RegClass;
5050 : extern const TargetRegisterClass FPR16RegClass;
5051 : extern const TargetRegisterClass PPRRegClass;
5052 : extern const TargetRegisterClass PPR_3bRegClass;
5053 : extern const TargetRegisterClass GPR32allRegClass;
5054 : extern const TargetRegisterClass FPR32RegClass;
5055 : extern const TargetRegisterClass GPR32RegClass;
5056 : extern const TargetRegisterClass GPR32spRegClass;
5057 : extern const TargetRegisterClass GPR32commonRegClass;
5058 : extern const TargetRegisterClass CCRRegClass;
5059 : extern const TargetRegisterClass GPR32sponlyRegClass;
5060 : extern const TargetRegisterClass WSeqPairsClassRegClass;
5061 : extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass;
5062 : extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5063 : extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5064 : extern const TargetRegisterClass GPR64allRegClass;
5065 : extern const TargetRegisterClass FPR64RegClass;
5066 : extern const TargetRegisterClass GPR64RegClass;
5067 : extern const TargetRegisterClass GPR64spRegClass;
5068 : extern const TargetRegisterClass GPR64commonRegClass;
5069 : extern const TargetRegisterClass tcGPR64RegClass;
5070 : extern const TargetRegisterClass rtcGPR64RegClass;
5071 : extern const TargetRegisterClass GPR64sponlyRegClass;
5072 : extern const TargetRegisterClass DDRegClass;
5073 : extern const TargetRegisterClass XSeqPairsClassRegClass;
5074 : extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass;
5075 : extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
5076 : extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
5077 : extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
5078 : extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
5079 : extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
5080 : extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass;
5081 : extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_rtcGPR64RegClass;
5082 : extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClass;
5083 : extern const TargetRegisterClass FPR128RegClass;
5084 : extern const TargetRegisterClass ZPRRegClass;
5085 : extern const TargetRegisterClass FPR128_loRegClass;
5086 : extern const TargetRegisterClass ZPR_4bRegClass;
5087 : extern const TargetRegisterClass ZPR_3bRegClass;
5088 : extern const TargetRegisterClass DDDRegClass;
5089 : extern const TargetRegisterClass DDDDRegClass;
5090 : extern const TargetRegisterClass QQRegClass;
5091 : extern const TargetRegisterClass ZPR2RegClass;
5092 : extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
5093 : extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
5094 : extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass;
5095 : extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass;
5096 : extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
5097 : extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass;
5098 : extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass;
5099 : extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass;
5100 : extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass;
5101 : extern const TargetRegisterClass QQQRegClass;
5102 : extern const TargetRegisterClass ZPR3RegClass;
5103 : extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
5104 : extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
5105 : extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
5106 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass;
5107 : extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass;
5108 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass;
5109 : extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
5110 : extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5111 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5112 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass;
5113 : extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5114 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5115 : extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass;
5116 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass;
5117 : extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass;
5118 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5119 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass;
5120 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5121 : extern const TargetRegisterClass QQQQRegClass;
5122 : extern const TargetRegisterClass ZPR4RegClass;
5123 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
5124 : extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
5125 : extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
5126 : extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
5127 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass;
5128 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass;
5129 : extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass;
5130 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass;
5131 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
5132 : extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
5133 : extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5134 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
5135 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5136 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass;
5137 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
5138 : extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5139 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5140 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
5141 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5142 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5143 : extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass;
5144 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass;
5145 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass;
5146 : extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass;
5147 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
5148 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5149 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass;
5150 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5151 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
5152 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5153 : } // end namespace AArch64
5154 :
5155 : } // end namespace llvm
5156 :
5157 : #endif // GET_REGINFO_HEADER
5158 :
5159 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5160 : |* *|
5161 : |* Target Register and Register Classes Information *|
5162 : |* *|
5163 : |* Automatically generated file, do not edit! *|
5164 : |* *|
5165 : \*===----------------------------------------------------------------------===*/
5166 :
5167 :
5168 : #ifdef GET_REGINFO_TARGET_DESC
5169 : #undef GET_REGINFO_TARGET_DESC
5170 :
5171 : namespace llvm {
5172 :
5173 : extern const MCRegisterClass AArch64MCRegisterClasses[];
5174 :
5175 : static const MVT::SimpleValueType VTLists[] = {
5176 : /* 0 */ MVT::f32, MVT::i32, MVT::Other,
5177 : /* 3 */ MVT::i64, MVT::Other,
5178 : /* 5 */ MVT::f16, MVT::Other,
5179 : /* 7 */ MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::Other,
5180 : /* 12 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::Other,
5181 : /* 22 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::v8f16, MVT::Other,
5182 : /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
5183 : /* 39 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv1f32, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv1f64, MVT::nxv2f64, MVT::Other,
5184 : /* 52 */ MVT::Untyped, MVT::Other,
5185 : };
5186 :
5187 : static const char *const SubRegIndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1", "qsub2", "qsub3", "ssub", "sub_32", "sube32", "sube64", "subo32", "subo64", "zsub", "zsub0", "zsub1", "zsub2", "zsub3", "zsub_hi", "dsub1_then_bsub", "dsub1_then_hsub", "dsub1_then_ssub", "dsub3_then_bsub", "dsub3_then_hsub", "dsub3_then_ssub", "dsub2_then_bsub", "dsub2_then_hsub", "dsub2_then_ssub", "qsub1_then_bsub", "qsub1_then_dsub", "qsub1_then_hsub", "qsub1_then_ssub", "qsub3_then_bsub", "qsub3_then_dsub", "qsub3_then_hsub", "qsub3_then_ssub", "qsub2_then_bsub", "qsub2_then_dsub", "qsub2_then_hsub", "qsub2_then_ssub", "subo64_then_sub_32", "zsub1_then_bsub", "zsub1_then_dsub", "zsub1_then_hsub", "zsub1_then_ssub", "zsub1_then_zsub", "zsub1_then_zsub_hi", "zsub3_then_bsub", "zsub3_then_dsub", "zsub3_then_hsub", "zsub3_then_ssub", "zsub3_then_zsub", "zsub3_then_zsub_hi", "zsub2_then_bsub", "zsub2_then_dsub", "zsub2_then_hsub", "zsub2_then_ssub", "zsub2_then_zsub", "zsub2_then_zsub_hi", "dsub0_dsub1", "dsub0_dsub1_dsub2", "dsub1_dsub2", "dsub1_dsub2_dsub3", "dsub2_dsub3", "dsub_qsub1_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub", "qsub0_qsub1", "qsub0_qsub1_qsub2", "qsub1_qsub2", "qsub1_qsub2_qsub3", "qsub2_qsub3", "qsub1_then_dsub_qsub2_then_dsub", "qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "qsub2_then_dsub_qsub3_then_dsub", "sub_32_subo64_then_sub_32", "dsub_zsub1_then_dsub", "zsub_zsub1_then_zsub", "dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "dsub_zsub1_then_dsub_zsub2_then_dsub", "zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub_zsub1_then_zsub_zsub2_then_zsub", "zsub0_zsub1", "zsub0_zsub1_zsub2", "zsub1_zsub2", "zsub1_zsub2_zsub3", "zsub2_zsub3", "zsub1_then_dsub_zsub2_then_dsub", "zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "zsub1_then_zsub_zsub2_then_zsub", "zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub2_then_dsub_zsub3_then_dsub", "zsub2_then_zsub_zsub3_then_zsub", "" };
5188 :
5189 :
5190 : static const LaneBitmask SubRegIndexLaneMaskTable[] = {
5191 : LaneBitmask::getAll(),
5192 : LaneBitmask(0x00000001), // bsub
5193 : LaneBitmask(0x00000001), // dsub
5194 : LaneBitmask(0x00000001), // dsub0
5195 : LaneBitmask(0x00000080), // dsub1
5196 : LaneBitmask(0x00000200), // dsub2
5197 : LaneBitmask(0x00000100), // dsub3
5198 : LaneBitmask(0x00000001), // hsub
5199 : LaneBitmask(0x00000002), // qhisub
5200 : LaneBitmask(0x00000004), // qsub
5201 : LaneBitmask(0x00000001), // qsub0
5202 : LaneBitmask(0x00000400), // qsub1
5203 : LaneBitmask(0x00001000), // qsub2
5204 : LaneBitmask(0x00000800), // qsub3
5205 : LaneBitmask(0x00000001), // ssub
5206 : LaneBitmask(0x00000008), // sub_32
5207 : LaneBitmask(0x00000010), // sube32
5208 : LaneBitmask(0x00000008), // sube64
5209 : LaneBitmask(0x00000020), // subo32
5210 : LaneBitmask(0x00002000), // subo64
5211 : LaneBitmask(0x00000001), // zsub
5212 : LaneBitmask(0x00000041), // zsub0
5213 : LaneBitmask(0x0000C000), // zsub1
5214 : LaneBitmask(0x000C0000), // zsub2
5215 : LaneBitmask(0x00030000), // zsub3
5216 : LaneBitmask(0x00000040), // zsub_hi
5217 : LaneBitmask(0x00000080), // dsub1_then_bsub
5218 : LaneBitmask(0x00000080), // dsub1_then_hsub
5219 : LaneBitmask(0x00000080), // dsub1_then_ssub
5220 : LaneBitmask(0x00000100), // dsub3_then_bsub
5221 : LaneBitmask(0x00000100), // dsub3_then_hsub
5222 : LaneBitmask(0x00000100), // dsub3_then_ssub
5223 : LaneBitmask(0x00000200), // dsub2_then_bsub
5224 : LaneBitmask(0x00000200), // dsub2_then_hsub
5225 : LaneBitmask(0x00000200), // dsub2_then_ssub
5226 : LaneBitmask(0x00000400), // qsub1_then_bsub
5227 : LaneBitmask(0x00000400), // qsub1_then_dsub
5228 : LaneBitmask(0x00000400), // qsub1_then_hsub
5229 : LaneBitmask(0x00000400), // qsub1_then_ssub
5230 : LaneBitmask(0x00000800), // qsub3_then_bsub
5231 : LaneBitmask(0x00000800), // qsub3_then_dsub
5232 : LaneBitmask(0x00000800), // qsub3_then_hsub
5233 : LaneBitmask(0x00000800), // qsub3_then_ssub
5234 : LaneBitmask(0x00001000), // qsub2_then_bsub
5235 : LaneBitmask(0x00001000), // qsub2_then_dsub
5236 : LaneBitmask(0x00001000), // qsub2_then_hsub
5237 : LaneBitmask(0x00001000), // qsub2_then_ssub
5238 : LaneBitmask(0x00002000), // subo64_then_sub_32
5239 : LaneBitmask(0x00004000), // zsub1_then_bsub
5240 : LaneBitmask(0x00004000), // zsub1_then_dsub
5241 : LaneBitmask(0x00004000), // zsub1_then_hsub
5242 : LaneBitmask(0x00004000), // zsub1_then_ssub
5243 : LaneBitmask(0x00004000), // zsub1_then_zsub
5244 : LaneBitmask(0x00008000), // zsub1_then_zsub_hi
5245 : LaneBitmask(0x00010000), // zsub3_then_bsub
5246 : LaneBitmask(0x00010000), // zsub3_then_dsub
5247 : LaneBitmask(0x00010000), // zsub3_then_hsub
5248 : LaneBitmask(0x00010000), // zsub3_then_ssub
5249 : LaneBitmask(0x00010000), // zsub3_then_zsub
5250 : LaneBitmask(0x00020000), // zsub3_then_zsub_hi
5251 : LaneBitmask(0x00040000), // zsub2_then_bsub
5252 : LaneBitmask(0x00040000), // zsub2_then_dsub
5253 : LaneBitmask(0x00040000), // zsub2_then_hsub
5254 : LaneBitmask(0x00040000), // zsub2_then_ssub
5255 : LaneBitmask(0x00040000), // zsub2_then_zsub
5256 : LaneBitmask(0x00080000), // zsub2_then_zsub_hi
5257 : LaneBitmask(0x00000081), // dsub0_dsub1
5258 : LaneBitmask(0x00000281), // dsub0_dsub1_dsub2
5259 : LaneBitmask(0x00000280), // dsub1_dsub2
5260 : LaneBitmask(0x00000380), // dsub1_dsub2_dsub3
5261 : LaneBitmask(0x00000300), // dsub2_dsub3
5262 : LaneBitmask(0x00000401), // dsub_qsub1_then_dsub
5263 : LaneBitmask(0x00001C01), // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5264 : LaneBitmask(0x00001401), // dsub_qsub1_then_dsub_qsub2_then_dsub
5265 : LaneBitmask(0x00000401), // qsub0_qsub1
5266 : LaneBitmask(0x00001401), // qsub0_qsub1_qsub2
5267 : LaneBitmask(0x00001400), // qsub1_qsub2
5268 : LaneBitmask(0x00001C00), // qsub1_qsub2_qsub3
5269 : LaneBitmask(0x00001800), // qsub2_qsub3
5270 : LaneBitmask(0x00001400), // qsub1_then_dsub_qsub2_then_dsub
5271 : LaneBitmask(0x00001C00), // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5272 : LaneBitmask(0x00001800), // qsub2_then_dsub_qsub3_then_dsub
5273 : LaneBitmask(0x00002008), // sub_32_subo64_then_sub_32
5274 : LaneBitmask(0x00004001), // dsub_zsub1_then_dsub
5275 : LaneBitmask(0x00004001), // zsub_zsub1_then_zsub
5276 : LaneBitmask(0x00054001), // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5277 : LaneBitmask(0x00044001), // dsub_zsub1_then_dsub_zsub2_then_dsub
5278 : LaneBitmask(0x00054001), // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5279 : LaneBitmask(0x00044001), // zsub_zsub1_then_zsub_zsub2_then_zsub
5280 : LaneBitmask(0x0000C041), // zsub0_zsub1
5281 : LaneBitmask(0x000CC041), // zsub0_zsub1_zsub2
5282 : LaneBitmask(0x000CC000), // zsub1_zsub2
5283 : LaneBitmask(0x000FC000), // zsub1_zsub2_zsub3
5284 : LaneBitmask(0x000F0000), // zsub2_zsub3
5285 : LaneBitmask(0x00044000), // zsub1_then_dsub_zsub2_then_dsub
5286 : LaneBitmask(0x00054000), // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5287 : LaneBitmask(0x00044000), // zsub1_then_zsub_zsub2_then_zsub
5288 : LaneBitmask(0x00054000), // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5289 : LaneBitmask(0x00050000), // zsub2_then_dsub_zsub3_then_dsub
5290 : LaneBitmask(0x00050000), // zsub2_then_zsub_zsub3_then_zsub
5291 : };
5292 :
5293 :
5294 :
5295 : static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
5296 : // Mode = 0 (Default)
5297 : { 8, 8, 8, VTLists+52 }, // FPR8
5298 : { 16, 16, 16, VTLists+5 }, // FPR16
5299 : { 16, 16, 16, VTLists+7 }, // PPR
5300 : { 16, 16, 16, VTLists+7 }, // PPR_3b
5301 : { 32, 32, 32, VTLists+1 }, // GPR32all
5302 : { 32, 32, 32, VTLists+0 }, // FPR32
5303 : { 32, 32, 32, VTLists+1 }, // GPR32
5304 : { 32, 32, 32, VTLists+1 }, // GPR32sp
5305 : { 32, 32, 32, VTLists+1 }, // GPR32common
5306 : { 32, 32, 32, VTLists+1 }, // CCR
5307 : { 32, 32, 32, VTLists+1 }, // GPR32sponly
5308 : { 64, 64, 32, VTLists+52 }, // WSeqPairsClass
5309 : { 64, 64, 32, VTLists+52 }, // WSeqPairsClass_with_sube32_in_GPR32common
5310 : { 64, 64, 32, VTLists+52 }, // WSeqPairsClass_with_subo32_in_GPR32common
5311 : { 64, 64, 32, VTLists+52 }, // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
5312 : { 64, 64, 64, VTLists+3 }, // GPR64all
5313 : { 64, 64, 64, VTLists+12 }, // FPR64
5314 : { 64, 64, 64, VTLists+3 }, // GPR64
5315 : { 64, 64, 64, VTLists+3 }, // GPR64sp
5316 : { 64, 64, 64, VTLists+3 }, // GPR64common
5317 : { 64, 64, 64, VTLists+3 }, // tcGPR64
5318 : { 64, 64, 64, VTLists+3 }, // rtcGPR64
5319 : { 64, 64, 64, VTLists+3 }, // GPR64sponly
5320 : { 128, 128, 64, VTLists+52 }, // DD
5321 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass
5322 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_sub_32_in_GPR32common
5323 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_subo64_in_GPR64common
5324 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common
5325 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_sube64_in_tcGPR64
5326 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_subo64_in_tcGPR64
5327 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64
5328 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_sube64_in_rtcGPR64
5329 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_subo64_in_rtcGPR64
5330 : { 128, 128, 64, VTLists+52 }, // XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64
5331 : { 128, 128, 128, VTLists+22 }, // FPR128
5332 : { 128, 128, 128, VTLists+39 }, // ZPR
5333 : { 128, 128, 128, VTLists+31 }, // FPR128_lo
5334 : { 128, 128, 128, VTLists+39 }, // ZPR_4b
5335 : { 128, 128, 128, VTLists+39 }, // ZPR_3b
5336 : { 192, 192, 64, VTLists+52 }, // DDD
5337 : { 256, 256, 64, VTLists+52 }, // DDDD
5338 : { 256, 256, 128, VTLists+52 }, // QQ
5339 : { 256, 256, 128, VTLists+52 }, // ZPR2
5340 : { 256, 256, 128, VTLists+52 }, // QQ_with_qsub0_in_FPR128_lo
5341 : { 256, 256, 128, VTLists+52 }, // QQ_with_qsub1_in_FPR128_lo
5342 : { 256, 256, 128, VTLists+52 }, // ZPR2_with_zsub1_in_ZPR_4b
5343 : { 256, 256, 128, VTLists+52 }, // ZPR2_with_zsub_in_FPR128_lo
5344 : { 256, 256, 128, VTLists+52 }, // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
5345 : { 256, 256, 128, VTLists+52 }, // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
5346 : { 256, 256, 128, VTLists+52 }, // ZPR2_with_zsub0_in_ZPR_3b
5347 : { 256, 256, 128, VTLists+52 }, // ZPR2_with_zsub1_in_ZPR_3b
5348 : { 256, 256, 128, VTLists+52 }, // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
5349 : { 384, 384, 128, VTLists+52 }, // QQQ
5350 : { 384, 384, 128, VTLists+52 }, // ZPR3
5351 : { 384, 384, 128, VTLists+52 }, // QQQ_with_qsub0_in_FPR128_lo
5352 : { 384, 384, 128, VTLists+52 }, // QQQ_with_qsub1_in_FPR128_lo
5353 : { 384, 384, 128, VTLists+52 }, // QQQ_with_qsub2_in_FPR128_lo
5354 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub1_in_ZPR_4b
5355 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub2_in_ZPR_4b
5356 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub_in_FPR128_lo
5357 : { 384, 384, 128, VTLists+52 }, // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
5358 : { 384, 384, 128, VTLists+52 }, // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
5359 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
5360 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
5361 : { 384, 384, 128, VTLists+52 }, // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
5362 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
5363 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub0_in_ZPR_3b
5364 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub1_in_ZPR_3b
5365 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub2_in_ZPR_3b
5366 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
5367 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
5368 : { 384, 384, 128, VTLists+52 }, // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
5369 : { 512, 512, 128, VTLists+52 }, // QQQQ
5370 : { 512, 512, 128, VTLists+52 }, // ZPR4
5371 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub0_in_FPR128_lo
5372 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub1_in_FPR128_lo
5373 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub2_in_FPR128_lo
5374 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub3_in_FPR128_lo
5375 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub1_in_ZPR_4b
5376 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub2_in_ZPR_4b
5377 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub3_in_ZPR_4b
5378 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub_in_FPR128_lo
5379 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
5380 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
5381 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
5382 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
5383 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
5384 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
5385 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
5386 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
5387 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
5388 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
5389 : { 512, 512, 128, VTLists+52 }, // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
5390 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
5391 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub0_in_ZPR_3b
5392 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub1_in_ZPR_3b
5393 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub2_in_ZPR_3b
5394 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub3_in_ZPR_3b
5395 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
5396 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
5397 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
5398 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
5399 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
5400 : { 512, 512, 128, VTLists+52 }, // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
5401 : };
5402 :
5403 : static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
5404 :
5405 : static const uint32_t FPR8SubClassMask[] = {
5406 : 0x00000001, 0x00000000, 0x00000000, 0x00000000,
5407 : 0x00810022, 0xfffffffc, 0xffffffff, 0x000000ff, // bsub
5408 : 0x00800000, 0x00000180, 0x00000000, 0x00000000, // dsub1_then_bsub
5409 : 0x00000000, 0x00000100, 0x00000000, 0x00000000, // dsub3_then_bsub
5410 : 0x00000000, 0x00000180, 0x00000000, 0x00000000, // dsub2_then_bsub
5411 : 0x00000000, 0x31d09a00, 0x131c3d01, 0x00000000, // qsub1_then_bsub
5412 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub3_then_bsub
5413 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub2_then_bsub
5414 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub1_then_bsub
5415 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub3_then_bsub
5416 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub2_then_bsub
5417 : };
5418 :
5419 : static const uint32_t FPR16SubClassMask[] = {
5420 : 0x00000002, 0x00000000, 0x00000000, 0x00000000,
5421 : 0x00810020, 0xfffffffc, 0xffffffff, 0x000000ff, // hsub
5422 : 0x00800000, 0x00000180, 0x00000000, 0x00000000, // dsub1_then_hsub
5423 : 0x00000000, 0x00000100, 0x00000000, 0x00000000, // dsub3_then_hsub
5424 : 0x00000000, 0x00000180, 0x00000000, 0x00000000, // dsub2_then_hsub
5425 : 0x00000000, 0x31d09a00, 0x131c3d01, 0x00000000, // qsub1_then_hsub
5426 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub3_then_hsub
5427 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub2_then_hsub
5428 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub1_then_hsub
5429 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub3_then_hsub
5430 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub2_then_hsub
5431 : };
5432 :
5433 : static const uint32_t PPRSubClassMask[] = {
5434 : 0x0000000c, 0x00000000, 0x00000000, 0x00000000,
5435 : };
5436 :
5437 : static const uint32_t PPR_3bSubClassMask[] = {
5438 : 0x00000008, 0x00000000, 0x00000000, 0x00000000,
5439 : };
5440 :
5441 : static const uint32_t GPR32allSubClassMask[] = {
5442 : 0x000005d0, 0x00000000, 0x00000000, 0x00000000,
5443 : 0xff7e8000, 0x00000003, 0x00000000, 0x00000000, // sub_32
5444 : 0x00007800, 0x00000000, 0x00000000, 0x00000000, // sube32
5445 : 0x00007800, 0x00000000, 0x00000000, 0x00000000, // subo32
5446 : 0xff000000, 0x00000003, 0x00000000, 0x00000000, // subo64_then_sub_32
5447 : };
5448 :
5449 : static const uint32_t FPR32SubClassMask[] = {
5450 : 0x00000020, 0x00000000, 0x00000000, 0x00000000,
5451 : 0x00810000, 0xfffffffc, 0xffffffff, 0x000000ff, // ssub
5452 : 0x00800000, 0x00000180, 0x00000000, 0x00000000, // dsub1_then_ssub
5453 : 0x00000000, 0x00000100, 0x00000000, 0x00000000, // dsub3_then_ssub
5454 : 0x00000000, 0x00000180, 0x00000000, 0x00000000, // dsub2_then_ssub
5455 : 0x00000000, 0x31d09a00, 0x131c3d01, 0x00000000, // qsub1_then_ssub
5456 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub3_then_ssub
5457 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub2_then_ssub
5458 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub1_then_ssub
5459 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub3_then_ssub
5460 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub2_then_ssub
5461 : };
5462 :
5463 : static const uint32_t GPR32SubClassMask[] = {
5464 : 0x00000140, 0x00000000, 0x00000000, 0x00000000,
5465 : 0xff3a0000, 0x00000003, 0x00000000, 0x00000000, // sub_32
5466 : 0x00007800, 0x00000000, 0x00000000, 0x00000000, // sube32
5467 : 0x00007800, 0x00000000, 0x00000000, 0x00000000, // subo32
5468 : 0xff000000, 0x00000003, 0x00000000, 0x00000000, // subo64_then_sub_32
5469 : };
5470 :
5471 : static const uint32_t GPR32spSubClassMask[] = {
5472 : 0x00000580, 0x00000000, 0x00000000, 0x00000000,
5473 : 0xda7c0000, 0x00000003, 0x00000000, 0x00000000, // sub_32
5474 : 0x00005000, 0x00000000, 0x00000000, 0x00000000, // sube32
5475 : 0x00006000, 0x00000000, 0x00000000, 0x00000000, // subo32
5476 : 0xfc000000, 0x00000003, 0x00000000, 0x00000000, // subo64_then_sub_32
5477 : };
5478 :
5479 : static const uint32_t GPR32commonSubClassMask[] = {
5480 : 0x00000100, 0x00000000, 0x00000000, 0x00000000,
5481 : 0xda380000, 0x00000003, 0x00000000, 0x00000000, // sub_32
5482 : 0x00005000, 0x00000000, 0x00000000, 0x00000000, // sube32
5483 : 0x00006000, 0x00000000, 0x00000000, 0x00000000, // subo32
5484 : 0xfc000000, 0x00000003, 0x00000000, 0x00000000, // subo64_then_sub_32
5485 : };
5486 :
5487 : static const uint32_t CCRSubClassMask[] = {
5488 : 0x00000200, 0x00000000, 0x00000000, 0x00000000,
5489 : };
5490 :
5491 : static const uint32_t GPR32sponlySubClassMask[] = {
5492 : 0x00000400, 0x00000000, 0x00000000, 0x00000000,
5493 : 0x00400000, 0x00000000, 0x00000000, 0x00000000, // sub_32
5494 : };
5495 :
5496 : static const uint32_t WSeqPairsClassSubClassMask[] = {
5497 : 0x00007800, 0x00000000, 0x00000000, 0x00000000,
5498 : 0xff000000, 0x00000003, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
5499 : };
5500 :
5501 : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask[] = {
5502 : 0x00005000, 0x00000000, 0x00000000, 0x00000000,
5503 : 0xda000000, 0x00000003, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
5504 : };
5505 :
5506 : static const uint32_t WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
5507 : 0x00006000, 0x00000000, 0x00000000, 0x00000000,
5508 : 0xfc000000, 0x00000003, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
5509 : };
5510 :
5511 : static const uint32_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
5512 : 0x00004000, 0x00000000, 0x00000000, 0x00000000,
5513 : 0xd8000000, 0x00000003, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
5514 : };
5515 :
5516 : static const uint32_t GPR64allSubClassMask[] = {
5517 : 0x007e8000, 0x00000000, 0x00000000, 0x00000000,
5518 : 0xff000000, 0x00000003, 0x00000000, 0x00000000, // sube64
5519 : 0xff000000, 0x00000003, 0x00000000, 0x00000000, // subo64
5520 : };
5521 :
5522 : static const uint32_t FPR64SubClassMask[] = {
5523 : 0x00010000, 0x00000000, 0x00000000, 0x00000000,
5524 : 0x00000000, 0xfffffe7c, 0xffffffff, 0x000000ff, // dsub
5525 : 0x00800000, 0x00000180, 0x00000000, 0x00000000, // dsub0
5526 : 0x00800000, 0x00000180, 0x00000000, 0x00000000, // dsub1
5527 : 0x00000000, 0x00000180, 0x00000000, 0x00000000, // dsub2
5528 : 0x00000000, 0x00000100, 0x00000000, 0x00000000, // dsub3
5529 : 0x00000000, 0x31d09a00, 0x131c3d01, 0x00000000, // qsub1_then_dsub
5530 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub3_then_dsub
5531 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub2_then_dsub
5532 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub1_then_dsub
5533 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub3_then_dsub
5534 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub2_then_dsub
5535 : };
5536 :
5537 : static const uint32_t GPR64SubClassMask[] = {
5538 : 0x003a0000, 0x00000000, 0x00000000, 0x00000000,
5539 : 0xff000000, 0x00000003, 0x00000000, 0x00000000, // sube64
5540 : 0xff000000, 0x00000003, 0x00000000, 0x00000000, // subo64
5541 : };
5542 :
5543 : static const uint32_t GPR64spSubClassMask[] = {
5544 : 0x007c0000, 0x00000000, 0x00000000, 0x00000000,
5545 : 0xda000000, 0x00000003, 0x00000000, 0x00000000, // sube64
5546 : 0xfc000000, 0x00000003, 0x00000000, 0x00000000, // subo64
5547 : };
5548 :
5549 : static const uint32_t GPR64commonSubClassMask[] = {
5550 : 0x00380000, 0x00000000, 0x00000000, 0x00000000,
5551 : 0xda000000, 0x00000003, 0x00000000, 0x00000000, // sube64
5552 : 0xfc000000, 0x00000003, 0x00000000, 0x00000000, // subo64
5553 : };
5554 :
5555 : static const uint32_t tcGPR64SubClassMask[] = {
5556 : 0x00300000, 0x00000000, 0x00000000, 0x00000000,
5557 : 0xd0000000, 0x00000003, 0x00000000, 0x00000000, // sube64
5558 : 0xe0000000, 0x00000003, 0x00000000, 0x00000000, // subo64
5559 : };
5560 :
5561 : static const uint32_t rtcGPR64SubClassMask[] = {
5562 : 0x00200000, 0x00000000, 0x00000000, 0x00000000,
5563 : 0x80000000, 0x00000002, 0x00000000, 0x00000000, // sube64
5564 : 0x00000000, 0x00000003, 0x00000000, 0x00000000, // subo64
5565 : };
5566 :
5567 : static const uint32_t GPR64sponlySubClassMask[] = {
5568 : 0x00400000, 0x00000000, 0x00000000, 0x00000000,
5569 : };
5570 :
5571 : static const uint32_t DDSubClassMask[] = {
5572 : 0x00800000, 0x00000000, 0x00000000, 0x00000000,
5573 : 0x00000000, 0x00000180, 0x00000000, 0x00000000, // dsub0_dsub1
5574 : 0x00000000, 0x00000180, 0x00000000, 0x00000000, // dsub1_dsub2
5575 : 0x00000000, 0x00000100, 0x00000000, 0x00000000, // dsub2_dsub3
5576 : 0x00000000, 0x31d09a00, 0x131c3d01, 0x00000000, // dsub_qsub1_then_dsub
5577 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub1_then_dsub_qsub2_then_dsub
5578 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub2_then_dsub_qsub3_then_dsub
5579 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // dsub_zsub1_then_dsub
5580 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub1_then_dsub_zsub2_then_dsub
5581 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub2_then_dsub_zsub3_then_dsub
5582 : };
5583 :
5584 : static const uint32_t XSeqPairsClassSubClassMask[] = {
5585 : 0xff000000, 0x00000003, 0x00000000, 0x00000000,
5586 : };
5587 :
5588 : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask[] = {
5589 : 0xda000000, 0x00000003, 0x00000000, 0x00000000,
5590 : };
5591 :
5592 : static const uint32_t XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
5593 : 0xfc000000, 0x00000003, 0x00000000, 0x00000000,
5594 : };
5595 :
5596 : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
5597 : 0xd8000000, 0x00000003, 0x00000000, 0x00000000,
5598 : };
5599 :
5600 : static const uint32_t XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask[] = {
5601 : 0xd0000000, 0x00000003, 0x00000000, 0x00000000,
5602 : };
5603 :
5604 : static const uint32_t XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
5605 : 0xe0000000, 0x00000003, 0x00000000, 0x00000000,
5606 : };
5607 :
5608 : static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
5609 : 0xc0000000, 0x00000003, 0x00000000, 0x00000000,
5610 : };
5611 :
5612 : static const uint32_t XSeqPairsClass_with_sube64_in_rtcGPR64SubClassMask[] = {
5613 : 0x80000000, 0x00000002, 0x00000000, 0x00000000,
5614 : };
5615 :
5616 : static const uint32_t XSeqPairsClass_with_subo64_in_rtcGPR64SubClassMask[] = {
5617 : 0x00000000, 0x00000003, 0x00000000, 0x00000000,
5618 : };
5619 :
5620 : static const uint32_t XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64SubClassMask[] = {
5621 : 0x00000000, 0x00000002, 0x00000000, 0x00000000,
5622 : };
5623 :
5624 : static const uint32_t FPR128SubClassMask[] = {
5625 : 0x00000000, 0x00000014, 0x00000000, 0x00000000,
5626 : 0x00000000, 0x31d09a00, 0x131c3d01, 0x00000000, // qsub0
5627 : 0x00000000, 0x31d09a00, 0x131c3d01, 0x00000000, // qsub1
5628 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub2
5629 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub3
5630 : 0x00000000, 0xce2f6468, 0xece3c2fe, 0x000000ff, // zsub
5631 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub1_then_zsub
5632 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub3_then_zsub
5633 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub2_then_zsub
5634 : };
5635 :
5636 : static const uint32_t ZPRSubClassMask[] = {
5637 : 0x00000000, 0x00000068, 0x00000000, 0x00000000,
5638 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub0
5639 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub1
5640 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub2
5641 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub3
5642 : };
5643 :
5644 : static const uint32_t FPR128_loSubClassMask[] = {
5645 : 0x00000000, 0x00000010, 0x00000000, 0x00000000,
5646 : 0x00000000, 0x10408800, 0x11040401, 0x00000000, // qsub0
5647 : 0x00000000, 0x30809000, 0x130c0801, 0x00000000, // qsub1
5648 : 0x00000000, 0x21000000, 0x13181001, 0x00000000, // qsub2
5649 : 0x00000000, 0x00000000, 0x12102000, 0x00000000, // qsub3
5650 : 0x00000000, 0x880b4060, 0x688200c6, 0x000000d0, // zsub
5651 : 0x00000000, 0xc20f2000, 0xeca040ee, 0x000000f4, // zsub1_then_zsub
5652 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff, // zsub3_then_zsub
5653 : 0x00000000, 0x44000000, 0xec6080fe, 0x000000fd, // zsub2_then_zsub
5654 : };
5655 :
5656 : static const uint32_t ZPR_4bSubClassMask[] = {
5657 : 0x00000000, 0x00000060, 0x00000000, 0x00000000,
5658 : 0x00000000, 0x880b4000, 0x688200c6, 0x000000d0, // zsub0
5659 : 0x00000000, 0xc20f2000, 0xeca040ee, 0x000000f4, // zsub1
5660 : 0x00000000, 0x44000000, 0xec6080fe, 0x000000fd, // zsub2
5661 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff, // zsub3
5662 : };
5663 :
5664 : static const uint32_t ZPR_3bSubClassMask[] = {
5665 : 0x00000000, 0x00000040, 0x00000000, 0x00000000,
5666 : 0x00000000, 0x000a0000, 0x400000c4, 0x000000d0, // zsub0
5667 : 0x00000000, 0x000c0000, 0x800000e8, 0x000000f4, // zsub1
5668 : 0x00000000, 0x00000000, 0x000000b0, 0x000000ed, // zsub2
5669 : 0x00000000, 0x00000000, 0x00000000, 0x000000aa, // zsub3
5670 : };
5671 :
5672 : static const uint32_t DDDSubClassMask[] = {
5673 : 0x00000000, 0x00000080, 0x00000000, 0x00000000,
5674 : 0x00000000, 0x00000100, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2
5675 : 0x00000000, 0x00000100, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3
5676 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // dsub_qsub1_then_dsub_qsub2_then_dsub
5677 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5678 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // dsub_zsub1_then_dsub_zsub2_then_dsub
5679 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5680 : };
5681 :
5682 : static const uint32_t DDDDSubClassMask[] = {
5683 : 0x00000000, 0x00000100, 0x00000000, 0x00000000,
5684 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5685 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5686 : };
5687 :
5688 : static const uint32_t QQSubClassMask[] = {
5689 : 0x00000000, 0x00009a00, 0x00000000, 0x00000000,
5690 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub0_qsub1
5691 : 0x00000000, 0x31d00000, 0x131c3d01, 0x00000000, // qsub1_qsub2
5692 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub2_qsub3
5693 : 0x00000000, 0xce2f6400, 0xece3c2fe, 0x000000ff, // zsub_zsub1_then_zsub
5694 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub1_then_zsub_zsub2_then_zsub
5695 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub2_then_zsub_zsub3_then_zsub
5696 : };
5697 :
5698 : static const uint32_t ZPR2SubClassMask[] = {
5699 : 0x00000000, 0x000f6400, 0x00000000, 0x00000000,
5700 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub0_zsub1
5701 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub1_zsub2
5702 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub2_zsub3
5703 : };
5704 :
5705 : static const uint32_t QQ_with_qsub0_in_FPR128_loSubClassMask[] = {
5706 : 0x00000000, 0x00008800, 0x00000000, 0x00000000,
5707 : 0x00000000, 0x10400000, 0x11040401, 0x00000000, // qsub0_qsub1
5708 : 0x00000000, 0x30800000, 0x130c0801, 0x00000000, // qsub1_qsub2
5709 : 0x00000000, 0x00000000, 0x13181000, 0x00000000, // qsub2_qsub3
5710 : 0x00000000, 0x880b4000, 0x688200c6, 0x000000d0, // zsub_zsub1_then_zsub
5711 : 0x00000000, 0xc2000000, 0xeca040ee, 0x000000f4, // zsub1_then_zsub_zsub2_then_zsub
5712 : 0x00000000, 0x00000000, 0xec608000, 0x000000fd, // zsub2_then_zsub_zsub3_then_zsub
5713 : };
5714 :
5715 : static const uint32_t QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5716 : 0x00000000, 0x00009000, 0x00000000, 0x00000000,
5717 : 0x00000000, 0x30800000, 0x130c0801, 0x00000000, // qsub0_qsub1
5718 : 0x00000000, 0x21000000, 0x13181001, 0x00000000, // qsub1_qsub2
5719 : 0x00000000, 0x00000000, 0x12102000, 0x00000000, // qsub2_qsub3
5720 : 0x00000000, 0xc20f2000, 0xeca040ee, 0x000000f4, // zsub_zsub1_then_zsub
5721 : 0x00000000, 0x44000000, 0xec6080fe, 0x000000fd, // zsub1_then_zsub_zsub2_then_zsub
5722 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff, // zsub2_then_zsub_zsub3_then_zsub
5723 : };
5724 :
5725 : static const uint32_t ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = {
5726 : 0x00000000, 0x000f2000, 0x00000000, 0x00000000,
5727 : 0x00000000, 0xc2000000, 0xeca040ee, 0x000000f4, // zsub0_zsub1
5728 : 0x00000000, 0x44000000, 0xec6080fe, 0x000000fd, // zsub1_zsub2
5729 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff, // zsub2_zsub3
5730 : };
5731 :
5732 : static const uint32_t ZPR2_with_zsub_in_FPR128_loSubClassMask[] = {
5733 : 0x00000000, 0x000b4000, 0x00000000, 0x00000000,
5734 : 0x00000000, 0x88000000, 0x688200c6, 0x000000d0, // zsub0_zsub1
5735 : 0x00000000, 0xc2000000, 0xeca040ee, 0x000000f4, // zsub1_zsub2
5736 : 0x00000000, 0x00000000, 0xec608000, 0x000000fd, // zsub2_zsub3
5737 : };
5738 :
5739 : static const uint32_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5740 : 0x00000000, 0x00008000, 0x00000000, 0x00000000,
5741 : 0x00000000, 0x10000000, 0x11040001, 0x00000000, // qsub0_qsub1
5742 : 0x00000000, 0x20000000, 0x13080001, 0x00000000, // qsub1_qsub2
5743 : 0x00000000, 0x00000000, 0x12100000, 0x00000000, // qsub2_qsub3
5744 : 0x00000000, 0x800b0000, 0x688000c6, 0x000000d0, // zsub_zsub1_then_zsub
5745 : 0x00000000, 0x40000000, 0xec2000ee, 0x000000f4, // zsub1_then_zsub_zsub2_then_zsub
5746 : 0x00000000, 0x00000000, 0xe4400000, 0x000000fd, // zsub2_then_zsub_zsub3_then_zsub
5747 : };
5748 :
5749 : static const uint32_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = {
5750 : 0x00000000, 0x000b0000, 0x00000000, 0x00000000,
5751 : 0x00000000, 0x80000000, 0x688000c6, 0x000000d0, // zsub0_zsub1
5752 : 0x00000000, 0x40000000, 0xec2000ee, 0x000000f4, // zsub1_zsub2
5753 : 0x00000000, 0x00000000, 0xe4400000, 0x000000fd, // zsub2_zsub3
5754 : };
5755 :
5756 : static const uint32_t ZPR2_with_zsub0_in_ZPR_3bSubClassMask[] = {
5757 : 0x00000000, 0x000a0000, 0x00000000, 0x00000000,
5758 : 0x00000000, 0x00000000, 0x400000c4, 0x000000d0, // zsub0_zsub1
5759 : 0x00000000, 0x00000000, 0x800000e8, 0x000000f4, // zsub1_zsub2
5760 : 0x00000000, 0x00000000, 0x00000000, 0x000000ed, // zsub2_zsub3
5761 : };
5762 :
5763 : static const uint32_t ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = {
5764 : 0x00000000, 0x000c0000, 0x00000000, 0x00000000,
5765 : 0x00000000, 0x00000000, 0x800000e8, 0x000000f4, // zsub0_zsub1
5766 : 0x00000000, 0x00000000, 0x000000b0, 0x000000ed, // zsub1_zsub2
5767 : 0x00000000, 0x00000000, 0x00000000, 0x000000aa, // zsub2_zsub3
5768 : };
5769 :
5770 : static const uint32_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = {
5771 : 0x00000000, 0x00080000, 0x00000000, 0x00000000,
5772 : 0x00000000, 0x00000000, 0x000000c0, 0x000000d0, // zsub0_zsub1
5773 : 0x00000000, 0x00000000, 0x000000a0, 0x000000e4, // zsub1_zsub2
5774 : 0x00000000, 0x00000000, 0x00000000, 0x000000a8, // zsub2_zsub3
5775 : };
5776 :
5777 : static const uint32_t QQQSubClassMask[] = {
5778 : 0x00000000, 0x31d00000, 0x00000001, 0x00000000,
5779 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub0_qsub1_qsub2
5780 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000, // qsub1_qsub2_qsub3
5781 : 0x00000000, 0xce200000, 0xece3c2fe, 0x000000ff, // zsub_zsub1_then_zsub_zsub2_then_zsub
5782 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5783 : };
5784 :
5785 : static const uint32_t ZPR3SubClassMask[] = {
5786 : 0x00000000, 0xce200000, 0x000000fe, 0x00000000,
5787 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub0_zsub1_zsub2
5788 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub1_zsub2_zsub3
5789 : };
5790 :
5791 : static const uint32_t QQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
5792 : 0x00000000, 0x10400000, 0x00000001, 0x00000000,
5793 : 0x00000000, 0x00000000, 0x11040400, 0x00000000, // qsub0_qsub1_qsub2
5794 : 0x00000000, 0x00000000, 0x130c0800, 0x00000000, // qsub1_qsub2_qsub3
5795 : 0x00000000, 0x88000000, 0x688200c6, 0x000000d0, // zsub_zsub1_then_zsub_zsub2_then_zsub
5796 : 0x00000000, 0x00000000, 0xeca04000, 0x000000f4, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5797 : };
5798 :
5799 : static const uint32_t QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5800 : 0x00000000, 0x30800000, 0x00000001, 0x00000000,
5801 : 0x00000000, 0x00000000, 0x130c0800, 0x00000000, // qsub0_qsub1_qsub2
5802 : 0x00000000, 0x00000000, 0x13181000, 0x00000000, // qsub1_qsub2_qsub3
5803 : 0x00000000, 0xc2000000, 0xeca040ee, 0x000000f4, // zsub_zsub1_then_zsub_zsub2_then_zsub
5804 : 0x00000000, 0x00000000, 0xec608000, 0x000000fd, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5805 : };
5806 :
5807 : static const uint32_t QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5808 : 0x00000000, 0x21000000, 0x00000001, 0x00000000,
5809 : 0x00000000, 0x00000000, 0x13181000, 0x00000000, // qsub0_qsub1_qsub2
5810 : 0x00000000, 0x00000000, 0x12102000, 0x00000000, // qsub1_qsub2_qsub3
5811 : 0x00000000, 0x44000000, 0xec6080fe, 0x000000fd, // zsub_zsub1_then_zsub_zsub2_then_zsub
5812 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5813 : };
5814 :
5815 : static const uint32_t ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = {
5816 : 0x00000000, 0xc2000000, 0x000000ee, 0x00000000,
5817 : 0x00000000, 0x00000000, 0xeca04000, 0x000000f4, // zsub0_zsub1_zsub2
5818 : 0x00000000, 0x00000000, 0xec608000, 0x000000fd, // zsub1_zsub2_zsub3
5819 : };
5820 :
5821 : static const uint32_t ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
5822 : 0x00000000, 0x44000000, 0x000000fe, 0x00000000,
5823 : 0x00000000, 0x00000000, 0xec608000, 0x000000fd, // zsub0_zsub1_zsub2
5824 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff, // zsub1_zsub2_zsub3
5825 : };
5826 :
5827 : static const uint32_t ZPR3_with_zsub_in_FPR128_loSubClassMask[] = {
5828 : 0x00000000, 0x88000000, 0x000000c6, 0x00000000,
5829 : 0x00000000, 0x00000000, 0x68820000, 0x000000d0, // zsub0_zsub1_zsub2
5830 : 0x00000000, 0x00000000, 0xeca04000, 0x000000f4, // zsub1_zsub2_zsub3
5831 : };
5832 :
5833 : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5834 : 0x00000000, 0x10000000, 0x00000001, 0x00000000,
5835 : 0x00000000, 0x00000000, 0x11040000, 0x00000000, // qsub0_qsub1_qsub2
5836 : 0x00000000, 0x00000000, 0x13080000, 0x00000000, // qsub1_qsub2_qsub3
5837 : 0x00000000, 0x80000000, 0x688000c6, 0x000000d0, // zsub_zsub1_then_zsub_zsub2_then_zsub
5838 : 0x00000000, 0x00000000, 0xec200000, 0x000000f4, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5839 : };
5840 :
5841 : static const uint32_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5842 : 0x00000000, 0x20000000, 0x00000001, 0x00000000,
5843 : 0x00000000, 0x00000000, 0x13080000, 0x00000000, // qsub0_qsub1_qsub2
5844 : 0x00000000, 0x00000000, 0x12100000, 0x00000000, // qsub1_qsub2_qsub3
5845 : 0x00000000, 0x40000000, 0xec2000ee, 0x000000f4, // zsub_zsub1_then_zsub_zsub2_then_zsub
5846 : 0x00000000, 0x00000000, 0xe4400000, 0x000000fd, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5847 : };
5848 :
5849 : static const uint32_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
5850 : 0x00000000, 0x40000000, 0x000000ee, 0x00000000,
5851 : 0x00000000, 0x00000000, 0xec200000, 0x000000f4, // zsub0_zsub1_zsub2
5852 : 0x00000000, 0x00000000, 0xe4400000, 0x000000fd, // zsub1_zsub2_zsub3
5853 : };
5854 :
5855 : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = {
5856 : 0x00000000, 0x80000000, 0x000000c6, 0x00000000,
5857 : 0x00000000, 0x00000000, 0x68800000, 0x000000d0, // zsub0_zsub1_zsub2
5858 : 0x00000000, 0x00000000, 0xec200000, 0x000000f4, // zsub1_zsub2_zsub3
5859 : };
5860 :
5861 : static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5862 : 0x00000000, 0x00000000, 0x00000001, 0x00000000,
5863 : 0x00000000, 0x00000000, 0x11000000, 0x00000000, // qsub0_qsub1_qsub2
5864 : 0x00000000, 0x00000000, 0x12000000, 0x00000000, // qsub1_qsub2_qsub3
5865 : 0x00000000, 0x00000000, 0x680000c6, 0x000000d0, // zsub_zsub1_then_zsub_zsub2_then_zsub
5866 : 0x00000000, 0x00000000, 0xe4000000, 0x000000f4, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5867 : };
5868 :
5869 : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
5870 : 0x00000000, 0x00000000, 0x000000c6, 0x00000000,
5871 : 0x00000000, 0x00000000, 0x68000000, 0x000000d0, // zsub0_zsub1_zsub2
5872 : 0x00000000, 0x00000000, 0xe4000000, 0x000000f4, // zsub1_zsub2_zsub3
5873 : };
5874 :
5875 : static const uint32_t ZPR3_with_zsub0_in_ZPR_3bSubClassMask[] = {
5876 : 0x00000000, 0x00000000, 0x000000c4, 0x00000000,
5877 : 0x00000000, 0x00000000, 0x40000000, 0x000000d0, // zsub0_zsub1_zsub2
5878 : 0x00000000, 0x00000000, 0x80000000, 0x000000f4, // zsub1_zsub2_zsub3
5879 : };
5880 :
5881 : static const uint32_t ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = {
5882 : 0x00000000, 0x00000000, 0x000000e8, 0x00000000,
5883 : 0x00000000, 0x00000000, 0x80000000, 0x000000f4, // zsub0_zsub1_zsub2
5884 : 0x00000000, 0x00000000, 0x00000000, 0x000000ed, // zsub1_zsub2_zsub3
5885 : };
5886 :
5887 : static const uint32_t ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
5888 : 0x00000000, 0x00000000, 0x000000b0, 0x00000000,
5889 : 0x00000000, 0x00000000, 0x00000000, 0x000000ed, // zsub0_zsub1_zsub2
5890 : 0x00000000, 0x00000000, 0x00000000, 0x000000aa, // zsub1_zsub2_zsub3
5891 : };
5892 :
5893 : static const uint32_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
5894 : 0x00000000, 0x00000000, 0x000000a0, 0x00000000,
5895 : 0x00000000, 0x00000000, 0x00000000, 0x000000e4, // zsub0_zsub1_zsub2
5896 : 0x00000000, 0x00000000, 0x00000000, 0x000000a8, // zsub1_zsub2_zsub3
5897 : };
5898 :
5899 : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = {
5900 : 0x00000000, 0x00000000, 0x000000c0, 0x00000000,
5901 : 0x00000000, 0x00000000, 0x00000000, 0x000000d0, // zsub0_zsub1_zsub2
5902 : 0x00000000, 0x00000000, 0x00000000, 0x000000e4, // zsub1_zsub2_zsub3
5903 : };
5904 :
5905 : static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
5906 : 0x00000000, 0x00000000, 0x00000080, 0x00000000,
5907 : 0x00000000, 0x00000000, 0x00000000, 0x000000c0, // zsub0_zsub1_zsub2
5908 : 0x00000000, 0x00000000, 0x00000000, 0x000000a0, // zsub1_zsub2_zsub3
5909 : };
5910 :
5911 : static const uint32_t QQQQSubClassMask[] = {
5912 : 0x00000000, 0x00000000, 0x131c3d00, 0x00000000,
5913 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5914 : };
5915 :
5916 : static const uint32_t ZPR4SubClassMask[] = {
5917 : 0x00000000, 0x00000000, 0xece3c200, 0x000000ff,
5918 : };
5919 :
5920 : static const uint32_t QQQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
5921 : 0x00000000, 0x00000000, 0x11040400, 0x00000000,
5922 : 0x00000000, 0x00000000, 0x68820000, 0x000000d0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5923 : };
5924 :
5925 : static const uint32_t QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5926 : 0x00000000, 0x00000000, 0x130c0800, 0x00000000,
5927 : 0x00000000, 0x00000000, 0xeca04000, 0x000000f4, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5928 : };
5929 :
5930 : static const uint32_t QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5931 : 0x00000000, 0x00000000, 0x13181000, 0x00000000,
5932 : 0x00000000, 0x00000000, 0xec608000, 0x000000fd, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5933 : };
5934 :
5935 : static const uint32_t QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
5936 : 0x00000000, 0x00000000, 0x12102000, 0x00000000,
5937 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5938 : };
5939 :
5940 : static const uint32_t ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = {
5941 : 0x00000000, 0x00000000, 0xeca04000, 0x000000f4,
5942 : };
5943 :
5944 : static const uint32_t ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
5945 : 0x00000000, 0x00000000, 0xec608000, 0x000000fd,
5946 : };
5947 :
5948 : static const uint32_t ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
5949 : 0x00000000, 0x00000000, 0xe4410000, 0x000000ff,
5950 : };
5951 :
5952 : static const uint32_t ZPR4_with_zsub_in_FPR128_loSubClassMask[] = {
5953 : 0x00000000, 0x00000000, 0x68820000, 0x000000d0,
5954 : };
5955 :
5956 : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5957 : 0x00000000, 0x00000000, 0x11040000, 0x00000000,
5958 : 0x00000000, 0x00000000, 0x68800000, 0x000000d0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5959 : };
5960 :
5961 : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5962 : 0x00000000, 0x00000000, 0x13080000, 0x00000000,
5963 : 0x00000000, 0x00000000, 0xec200000, 0x000000f4, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5964 : };
5965 :
5966 : static const uint32_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
5967 : 0x00000000, 0x00000000, 0x12100000, 0x00000000,
5968 : 0x00000000, 0x00000000, 0xe4400000, 0x000000fd, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5969 : };
5970 :
5971 : static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
5972 : 0x00000000, 0x00000000, 0xec200000, 0x000000f4,
5973 : };
5974 :
5975 : static const uint32_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
5976 : 0x00000000, 0x00000000, 0xe4400000, 0x000000fd,
5977 : };
5978 :
5979 : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = {
5980 : 0x00000000, 0x00000000, 0x68800000, 0x000000d0,
5981 : };
5982 :
5983 : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5984 : 0x00000000, 0x00000000, 0x11000000, 0x00000000,
5985 : 0x00000000, 0x00000000, 0x68000000, 0x000000d0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5986 : };
5987 :
5988 : static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
5989 : 0x00000000, 0x00000000, 0x12000000, 0x00000000,
5990 : 0x00000000, 0x00000000, 0xe4000000, 0x000000f4, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5991 : };
5992 :
5993 : static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
5994 : 0x00000000, 0x00000000, 0xe4000000, 0x000000f4,
5995 : };
5996 :
5997 : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
5998 : 0x00000000, 0x00000000, 0x68000000, 0x000000d0,
5999 : };
6000 :
6001 : static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
6002 : 0x00000000, 0x00000000, 0x10000000, 0x00000000,
6003 : 0x00000000, 0x00000000, 0x60000000, 0x000000d0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
6004 : };
6005 :
6006 : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
6007 : 0x00000000, 0x00000000, 0x60000000, 0x000000d0,
6008 : };
6009 :
6010 : static const uint32_t ZPR4_with_zsub0_in_ZPR_3bSubClassMask[] = {
6011 : 0x00000000, 0x00000000, 0x40000000, 0x000000d0,
6012 : };
6013 :
6014 : static const uint32_t ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = {
6015 : 0x00000000, 0x00000000, 0x80000000, 0x000000f4,
6016 : };
6017 :
6018 : static const uint32_t ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
6019 : 0x00000000, 0x00000000, 0x00000000, 0x000000ed,
6020 : };
6021 :
6022 : static const uint32_t ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6023 : 0x00000000, 0x00000000, 0x00000000, 0x000000aa,
6024 : };
6025 :
6026 : static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
6027 : 0x00000000, 0x00000000, 0x00000000, 0x000000e4,
6028 : };
6029 :
6030 : static const uint32_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6031 : 0x00000000, 0x00000000, 0x00000000, 0x000000a8,
6032 : };
6033 :
6034 : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = {
6035 : 0x00000000, 0x00000000, 0x00000000, 0x000000d0,
6036 : };
6037 :
6038 : static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6039 : 0x00000000, 0x00000000, 0x00000000, 0x000000a0,
6040 : };
6041 :
6042 : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
6043 : 0x00000000, 0x00000000, 0x00000000, 0x000000c0,
6044 : };
6045 :
6046 : static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6047 : 0x00000000, 0x00000000, 0x00000000, 0x00000080,
6048 : };
6049 :
6050 : static const uint16_t SuperRegIdxSeqs[] = {
6051 : /* 0 */ 15, 0,
6052 : /* 2 */ 17, 19, 0,
6053 : /* 5 */ 21, 22, 23, 24, 0,
6054 : /* 10 */ 15, 16, 18, 47, 0,
6055 : /* 15 */ 1, 26, 29, 32, 35, 39, 43, 48, 54, 60, 0,
6056 : /* 26 */ 2, 3, 4, 5, 6, 36, 40, 44, 49, 55, 61, 0,
6057 : /* 38 */ 7, 27, 30, 33, 37, 41, 45, 50, 56, 62, 0,
6058 : /* 49 */ 14, 28, 31, 34, 38, 42, 46, 51, 57, 63, 0,
6059 : /* 60 */ 10, 11, 12, 13, 20, 52, 58, 64, 0,
6060 : /* 69 */ 82, 0,
6061 : /* 71 */ 72, 85, 0,
6062 : /* 74 */ 87, 0,
6063 : /* 76 */ 90, 92, 0,
6064 : /* 79 */ 89, 91, 93, 0,
6065 : /* 83 */ 67, 69, 73, 80, 86, 95, 0,
6066 : /* 90 */ 75, 77, 88, 97, 0,
6067 : /* 95 */ 66, 68, 70, 71, 79, 81, 83, 94, 98, 0,
6068 : /* 105 */ 74, 76, 78, 84, 96, 99, 0,
6069 : };
6070 :
6071 : static const TargetRegisterClass *const PPR_3bSuperclasses[] = {
6072 : &AArch64::PPRRegClass,
6073 : nullptr
6074 : };
6075 :
6076 : static const TargetRegisterClass *const GPR32Superclasses[] = {
6077 : &AArch64::GPR32allRegClass,
6078 : nullptr
6079 : };
6080 :
6081 : static const TargetRegisterClass *const GPR32spSuperclasses[] = {
6082 : &AArch64::GPR32allRegClass,
6083 : nullptr
6084 : };
6085 :
6086 : static const TargetRegisterClass *const GPR32commonSuperclasses[] = {
6087 : &AArch64::GPR32allRegClass,
6088 : &AArch64::GPR32RegClass,
6089 : &AArch64::GPR32spRegClass,
6090 : nullptr
6091 : };
6092 :
6093 : static const TargetRegisterClass *const GPR32sponlySuperclasses[] = {
6094 : &AArch64::GPR32allRegClass,
6095 : &AArch64::GPR32spRegClass,
6096 : nullptr
6097 : };
6098 :
6099 : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses[] = {
6100 : &AArch64::WSeqPairsClassRegClass,
6101 : nullptr
6102 : };
6103 :
6104 : static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
6105 : &AArch64::WSeqPairsClassRegClass,
6106 : nullptr
6107 : };
6108 :
6109 : static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
6110 : &AArch64::WSeqPairsClassRegClass,
6111 : &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
6112 : &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
6113 : nullptr
6114 : };
6115 :
6116 : static const TargetRegisterClass *const GPR64Superclasses[] = {
6117 : &AArch64::GPR64allRegClass,
6118 : nullptr
6119 : };
6120 :
6121 : static const TargetRegisterClass *const GPR64spSuperclasses[] = {
6122 : &AArch64::GPR64allRegClass,
6123 : nullptr
6124 : };
6125 :
6126 : static const TargetRegisterClass *const GPR64commonSuperclasses[] = {
6127 : &AArch64::GPR64allRegClass,
6128 : &AArch64::GPR64RegClass,
6129 : &AArch64::GPR64spRegClass,
6130 : nullptr
6131 : };
6132 :
6133 : static const TargetRegisterClass *const tcGPR64Superclasses[] = {
6134 : &AArch64::GPR64allRegClass,
6135 : &AArch64::GPR64RegClass,
6136 : &AArch64::GPR64spRegClass,
6137 : &AArch64::GPR64commonRegClass,
6138 : nullptr
6139 : };
6140 :
6141 : static const TargetRegisterClass *const rtcGPR64Superclasses[] = {
6142 : &AArch64::GPR64allRegClass,
6143 : &AArch64::GPR64RegClass,
6144 : &AArch64::GPR64spRegClass,
6145 : &AArch64::GPR64commonRegClass,
6146 : &AArch64::tcGPR64RegClass,
6147 : nullptr
6148 : };
6149 :
6150 : static const TargetRegisterClass *const GPR64sponlySuperclasses[] = {
6151 : &AArch64::GPR64allRegClass,
6152 : &AArch64::GPR64spRegClass,
6153 : nullptr
6154 : };
6155 :
6156 : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses[] = {
6157 : &AArch64::XSeqPairsClassRegClass,
6158 : nullptr
6159 : };
6160 :
6161 : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
6162 : &AArch64::XSeqPairsClassRegClass,
6163 : nullptr
6164 : };
6165 :
6166 : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
6167 : &AArch64::XSeqPairsClassRegClass,
6168 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
6169 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6170 : nullptr
6171 : };
6172 :
6173 : static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = {
6174 : &AArch64::XSeqPairsClassRegClass,
6175 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
6176 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6177 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6178 : nullptr
6179 : };
6180 :
6181 : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
6182 : &AArch64::XSeqPairsClassRegClass,
6183 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6184 : nullptr
6185 : };
6186 :
6187 : static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
6188 : &AArch64::XSeqPairsClassRegClass,
6189 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
6190 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6191 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6192 : &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6193 : &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6194 : nullptr
6195 : };
6196 :
6197 : static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_rtcGPR64Superclasses[] = {
6198 : &AArch64::XSeqPairsClassRegClass,
6199 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
6200 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6201 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6202 : &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6203 : &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6204 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6205 : nullptr
6206 : };
6207 :
6208 : static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_rtcGPR64Superclasses[] = {
6209 : &AArch64::XSeqPairsClassRegClass,
6210 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
6211 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6212 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6213 : &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6214 : &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6215 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6216 : nullptr
6217 : };
6218 :
6219 : static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Superclasses[] = {
6220 : &AArch64::XSeqPairsClassRegClass,
6221 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
6222 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6223 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6224 : &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6225 : &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6226 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6227 : &AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClass,
6228 : &AArch64::XSeqPairsClass_with_subo64_in_rtcGPR64RegClass,
6229 : nullptr
6230 : };
6231 :
6232 : static const TargetRegisterClass *const FPR128_loSuperclasses[] = {
6233 : &AArch64::FPR128RegClass,
6234 : nullptr
6235 : };
6236 :
6237 : static const TargetRegisterClass *const ZPR_4bSuperclasses[] = {
6238 : &AArch64::ZPRRegClass,
6239 : nullptr
6240 : };
6241 :
6242 : static const TargetRegisterClass *const ZPR_3bSuperclasses[] = {
6243 : &AArch64::ZPRRegClass,
6244 : &AArch64::ZPR_4bRegClass,
6245 : nullptr
6246 : };
6247 :
6248 : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6249 : &AArch64::QQRegClass,
6250 : nullptr
6251 : };
6252 :
6253 : static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6254 : &AArch64::QQRegClass,
6255 : nullptr
6256 : };
6257 :
6258 : static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
6259 : &AArch64::ZPR2RegClass,
6260 : nullptr
6261 : };
6262 :
6263 : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_loSuperclasses[] = {
6264 : &AArch64::ZPR2RegClass,
6265 : nullptr
6266 : };
6267 :
6268 : static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6269 : &AArch64::QQRegClass,
6270 : &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
6271 : &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
6272 : nullptr
6273 : };
6274 :
6275 : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
6276 : &AArch64::ZPR2RegClass,
6277 : &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6278 : &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
6279 : nullptr
6280 : };
6281 :
6282 : static const TargetRegisterClass *const ZPR2_with_zsub0_in_ZPR_3bSuperclasses[] = {
6283 : &AArch64::ZPR2RegClass,
6284 : &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6285 : &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
6286 : &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
6287 : nullptr
6288 : };
6289 :
6290 : static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
6291 : &AArch64::ZPR2RegClass,
6292 : &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6293 : nullptr
6294 : };
6295 :
6296 : static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
6297 : &AArch64::ZPR2RegClass,
6298 : &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6299 : &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
6300 : &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
6301 : &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass,
6302 : &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass,
6303 : nullptr
6304 : };
6305 :
6306 : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6307 : &AArch64::QQQRegClass,
6308 : nullptr
6309 : };
6310 :
6311 : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6312 : &AArch64::QQQRegClass,
6313 : nullptr
6314 : };
6315 :
6316 : static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6317 : &AArch64::QQQRegClass,
6318 : nullptr
6319 : };
6320 :
6321 : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
6322 : &AArch64::ZPR3RegClass,
6323 : nullptr
6324 : };
6325 :
6326 : static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6327 : &AArch64::ZPR3RegClass,
6328 : nullptr
6329 : };
6330 :
6331 : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_loSuperclasses[] = {
6332 : &AArch64::ZPR3RegClass,
6333 : nullptr
6334 : };
6335 :
6336 : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6337 : &AArch64::QQQRegClass,
6338 : &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
6339 : &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
6340 : nullptr
6341 : };
6342 :
6343 : static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6344 : &AArch64::QQQRegClass,
6345 : &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
6346 : &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
6347 : nullptr
6348 : };
6349 :
6350 : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6351 : &AArch64::ZPR3RegClass,
6352 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6353 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6354 : nullptr
6355 : };
6356 :
6357 : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
6358 : &AArch64::ZPR3RegClass,
6359 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6360 : &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6361 : nullptr
6362 : };
6363 :
6364 : static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6365 : &AArch64::QQQRegClass,
6366 : &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
6367 : &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
6368 : &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
6369 : &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
6370 : &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
6371 : nullptr
6372 : };
6373 :
6374 : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6375 : &AArch64::ZPR3RegClass,
6376 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6377 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6378 : &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6379 : &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6380 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6381 : nullptr
6382 : };
6383 :
6384 : static const TargetRegisterClass *const ZPR3_with_zsub0_in_ZPR_3bSuperclasses[] = {
6385 : &AArch64::ZPR3RegClass,
6386 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6387 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6388 : &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6389 : &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6390 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6391 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6392 : nullptr
6393 : };
6394 :
6395 : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
6396 : &AArch64::ZPR3RegClass,
6397 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6398 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6399 : &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6400 : nullptr
6401 : };
6402 :
6403 : static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6404 : &AArch64::ZPR3RegClass,
6405 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6406 : nullptr
6407 : };
6408 :
6409 : static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6410 : &AArch64::ZPR3RegClass,
6411 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6412 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6413 : &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6414 : &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
6415 : &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
6416 : nullptr
6417 : };
6418 :
6419 : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
6420 : &AArch64::ZPR3RegClass,
6421 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6422 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6423 : &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6424 : &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6425 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6426 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6427 : &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
6428 : &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
6429 : nullptr
6430 : };
6431 :
6432 : static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6433 : &AArch64::ZPR3RegClass,
6434 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6435 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6436 : &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6437 : &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6438 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6439 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6440 : &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
6441 : &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
6442 : &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
6443 : &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
6444 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass,
6445 : nullptr
6446 : };
6447 :
6448 : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6449 : &AArch64::QQQQRegClass,
6450 : nullptr
6451 : };
6452 :
6453 : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6454 : &AArch64::QQQQRegClass,
6455 : nullptr
6456 : };
6457 :
6458 : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6459 : &AArch64::QQQQRegClass,
6460 : nullptr
6461 : };
6462 :
6463 : static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6464 : &AArch64::QQQQRegClass,
6465 : nullptr
6466 : };
6467 :
6468 : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
6469 : &AArch64::ZPR4RegClass,
6470 : nullptr
6471 : };
6472 :
6473 : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6474 : &AArch64::ZPR4RegClass,
6475 : nullptr
6476 : };
6477 :
6478 : static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6479 : &AArch64::ZPR4RegClass,
6480 : nullptr
6481 : };
6482 :
6483 : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_loSuperclasses[] = {
6484 : &AArch64::ZPR4RegClass,
6485 : nullptr
6486 : };
6487 :
6488 : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6489 : &AArch64::QQQQRegClass,
6490 : &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
6491 : &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6492 : nullptr
6493 : };
6494 :
6495 : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6496 : &AArch64::QQQQRegClass,
6497 : &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6498 : &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6499 : nullptr
6500 : };
6501 :
6502 : static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6503 : &AArch64::QQQQRegClass,
6504 : &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6505 : &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
6506 : nullptr
6507 : };
6508 :
6509 : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6510 : &AArch64::ZPR4RegClass,
6511 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6512 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6513 : nullptr
6514 : };
6515 :
6516 : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6517 : &AArch64::ZPR4RegClass,
6518 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6519 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6520 : nullptr
6521 : };
6522 :
6523 : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
6524 : &AArch64::ZPR4RegClass,
6525 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6526 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6527 : nullptr
6528 : };
6529 :
6530 : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6531 : &AArch64::QQQQRegClass,
6532 : &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
6533 : &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6534 : &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6535 : &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
6536 : &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6537 : nullptr
6538 : };
6539 :
6540 : static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6541 : &AArch64::QQQQRegClass,
6542 : &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6543 : &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6544 : &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
6545 : &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6546 : &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
6547 : nullptr
6548 : };
6549 :
6550 : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6551 : &AArch64::ZPR4RegClass,
6552 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6553 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6554 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6555 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6556 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6557 : nullptr
6558 : };
6559 :
6560 : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6561 : &AArch64::ZPR4RegClass,
6562 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6563 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6564 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6565 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6566 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6567 : nullptr
6568 : };
6569 :
6570 : static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6571 : &AArch64::QQQQRegClass,
6572 : &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
6573 : &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6574 : &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6575 : &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
6576 : &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
6577 : &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6578 : &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
6579 : &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6580 : &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
6581 : nullptr
6582 : };
6583 :
6584 : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6585 : &AArch64::ZPR4RegClass,
6586 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6587 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6588 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6589 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6590 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6591 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6592 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6593 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6594 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6595 : nullptr
6596 : };
6597 :
6598 : static const TargetRegisterClass *const ZPR4_with_zsub0_in_ZPR_3bSuperclasses[] = {
6599 : &AArch64::ZPR4RegClass,
6600 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6601 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6602 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6603 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6604 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6605 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6606 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6607 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6608 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6609 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6610 : nullptr
6611 : };
6612 :
6613 : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
6614 : &AArch64::ZPR4RegClass,
6615 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6616 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6617 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6618 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6619 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6620 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6621 : nullptr
6622 : };
6623 :
6624 : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6625 : &AArch64::ZPR4RegClass,
6626 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6627 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6628 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6629 : nullptr
6630 : };
6631 :
6632 : static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6633 : &AArch64::ZPR4RegClass,
6634 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6635 : nullptr
6636 : };
6637 :
6638 : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6639 : &AArch64::ZPR4RegClass,
6640 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6641 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6642 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6643 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6644 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6645 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6646 : &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6647 : &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6648 : nullptr
6649 : };
6650 :
6651 : static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6652 : &AArch64::ZPR4RegClass,
6653 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6654 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6655 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6656 : &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6657 : &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
6658 : nullptr
6659 : };
6660 :
6661 : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
6662 : &AArch64::ZPR4RegClass,
6663 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6664 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6665 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6666 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6667 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6668 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6669 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6670 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6671 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6672 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6673 : &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
6674 : &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6675 : nullptr
6676 : };
6677 :
6678 : static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6679 : &AArch64::ZPR4RegClass,
6680 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6681 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6682 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6683 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6684 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6685 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6686 : &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6687 : &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6688 : &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
6689 : &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6690 : &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
6691 : nullptr
6692 : };
6693 :
6694 : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6695 : &AArch64::ZPR4RegClass,
6696 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6697 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6698 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6699 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6700 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6701 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6702 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6703 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6704 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6705 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6706 : &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
6707 : &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6708 : &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6709 : &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6710 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
6711 : nullptr
6712 : };
6713 :
6714 : static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6715 : &AArch64::ZPR4RegClass,
6716 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6717 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6718 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6719 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6720 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6721 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6722 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6723 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6724 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6725 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6726 : &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
6727 : &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6728 : &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6729 : &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
6730 : &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6731 : &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
6732 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
6733 : &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
6734 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6735 : nullptr
6736 : };
6737 :
6738 :
6739 0 : static inline unsigned GPR32AltOrderSelect(const MachineFunction &MF) { return 1; }
6740 :
6741 612 : static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) {
6742 : static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6743 : const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
6744 : const ArrayRef<MCPhysReg> Order[] = {
6745 : makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6746 : makeArrayRef(AltOrder1)
6747 : };
6748 : const unsigned Select = GPR32AltOrderSelect(MF);
6749 : assert(Select < 2);
6750 612 : return Order[Select];
6751 : }
6752 :
6753 0 : static inline unsigned GPR32spAltOrderSelect(const MachineFunction &MF) { return 1; }
6754 :
6755 99 : static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) {
6756 : static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6757 : const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
6758 : const ArrayRef<MCPhysReg> Order[] = {
6759 : makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6760 : makeArrayRef(AltOrder1)
6761 : };
6762 : const unsigned Select = GPR32spAltOrderSelect(MF);
6763 : assert(Select < 2);
6764 99 : return Order[Select];
6765 : }
6766 :
6767 0 : static inline unsigned GPR32commonAltOrderSelect(const MachineFunction &MF) { return 1; }
6768 :
6769 258 : static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) {
6770 : static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6771 : const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
6772 : const ArrayRef<MCPhysReg> Order[] = {
6773 : makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6774 : makeArrayRef(AltOrder1)
6775 : };
6776 : const unsigned Select = GPR32commonAltOrderSelect(MF);
6777 : assert(Select < 2);
6778 258 : return Order[Select];
6779 : }
6780 :
6781 0 : static inline unsigned GPR64AltOrderSelect(const MachineFunction &MF) { return 1; }
6782 :
6783 831 : static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) {
6784 : static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6785 : const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
6786 : const ArrayRef<MCPhysReg> Order[] = {
6787 : makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6788 : makeArrayRef(AltOrder1)
6789 : };
6790 : const unsigned Select = GPR64AltOrderSelect(MF);
6791 : assert(Select < 2);
6792 831 : return Order[Select];
6793 : }
6794 :
6795 0 : static inline unsigned GPR64spAltOrderSelect(const MachineFunction &MF) { return 1; }
6796 :
6797 184 : static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) {
6798 : static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6799 : const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
6800 : const ArrayRef<MCPhysReg> Order[] = {
6801 : makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6802 : makeArrayRef(AltOrder1)
6803 : };
6804 : const unsigned Select = GPR64spAltOrderSelect(MF);
6805 : assert(Select < 2);
6806 184 : return Order[Select];
6807 : }
6808 :
6809 0 : static inline unsigned GPR64commonAltOrderSelect(const MachineFunction &MF) { return 1; }
6810 :
6811 835 : static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) {
6812 : static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6813 : const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
6814 : const ArrayRef<MCPhysReg> Order[] = {
6815 : makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6816 : makeArrayRef(AltOrder1)
6817 : };
6818 : const unsigned Select = GPR64commonAltOrderSelect(MF);
6819 : assert(Select < 2);
6820 835 : return Order[Select];
6821 : }
6822 :
6823 : namespace AArch64 { // Register class instances
6824 : extern const TargetRegisterClass FPR8RegClass = {
6825 : &AArch64MCRegisterClasses[FPR8RegClassID],
6826 : FPR8SubClassMask,
6827 : SuperRegIdxSeqs + 15,
6828 : LaneBitmask(0x00000001),
6829 : 0,
6830 : false, /* HasDisjunctSubRegs */
6831 : false, /* CoveredBySubRegs */
6832 : NullRegClasses,
6833 : nullptr
6834 : };
6835 :
6836 : extern const TargetRegisterClass FPR16RegClass = {
6837 : &AArch64MCRegisterClasses[FPR16RegClassID],
6838 : FPR16SubClassMask,
6839 : SuperRegIdxSeqs + 38,
6840 : LaneBitmask(0x00000001),
6841 : 0,
6842 : false, /* HasDisjunctSubRegs */
6843 : false, /* CoveredBySubRegs */
6844 : NullRegClasses,
6845 : nullptr
6846 : };
6847 :
6848 : extern const TargetRegisterClass PPRRegClass = {
6849 : &AArch64MCRegisterClasses[PPRRegClassID],
6850 : PPRSubClassMask,
6851 : SuperRegIdxSeqs + 1,
6852 : LaneBitmask(0x00000001),
6853 : 0,
6854 : false, /* HasDisjunctSubRegs */
6855 : false, /* CoveredBySubRegs */
6856 : NullRegClasses,
6857 : nullptr
6858 : };
6859 :
6860 : extern const TargetRegisterClass PPR_3bRegClass = {
6861 : &AArch64MCRegisterClasses[PPR_3bRegClassID],
6862 : PPR_3bSubClassMask,
6863 : SuperRegIdxSeqs + 1,
6864 : LaneBitmask(0x00000001),
6865 : 0,
6866 : false, /* HasDisjunctSubRegs */
6867 : false, /* CoveredBySubRegs */
6868 : PPR_3bSuperclasses,
6869 : nullptr
6870 : };
6871 :
6872 : extern const TargetRegisterClass GPR32allRegClass = {
6873 : &AArch64MCRegisterClasses[GPR32allRegClassID],
6874 : GPR32allSubClassMask,
6875 : SuperRegIdxSeqs + 10,
6876 : LaneBitmask(0x00000001),
6877 : 0,
6878 : false, /* HasDisjunctSubRegs */
6879 : false, /* CoveredBySubRegs */
6880 : NullRegClasses,
6881 : nullptr
6882 : };
6883 :
6884 : extern const TargetRegisterClass FPR32RegClass = {
6885 : &AArch64MCRegisterClasses[FPR32RegClassID],
6886 : FPR32SubClassMask,
6887 : SuperRegIdxSeqs + 49,
6888 : LaneBitmask(0x00000001),
6889 : 0,
6890 : false, /* HasDisjunctSubRegs */
6891 : false, /* CoveredBySubRegs */
6892 : NullRegClasses,
6893 : nullptr
6894 : };
6895 :
6896 : extern const TargetRegisterClass GPR32RegClass = {
6897 : &AArch64MCRegisterClasses[GPR32RegClassID],
6898 : GPR32SubClassMask,
6899 : SuperRegIdxSeqs + 10,
6900 : LaneBitmask(0x00000001),
6901 : 0,
6902 : false, /* HasDisjunctSubRegs */
6903 : false, /* CoveredBySubRegs */
6904 : GPR32Superclasses,
6905 : GPR32GetRawAllocationOrder
6906 : };
6907 :
6908 : extern const TargetRegisterClass GPR32spRegClass = {
6909 : &AArch64MCRegisterClasses[GPR32spRegClassID],
6910 : GPR32spSubClassMask,
6911 : SuperRegIdxSeqs + 10,
6912 : LaneBitmask(0x00000001),
6913 : 0,
6914 : false, /* HasDisjunctSubRegs */
6915 : false, /* CoveredBySubRegs */
6916 : GPR32spSuperclasses,
6917 : GPR32spGetRawAllocationOrder
6918 : };
6919 :
6920 : extern const TargetRegisterClass GPR32commonRegClass = {
6921 : &AArch64MCRegisterClasses[GPR32commonRegClassID],
6922 : GPR32commonSubClassMask,
6923 : SuperRegIdxSeqs + 10,
6924 : LaneBitmask(0x00000001),
6925 : 0,
6926 : false, /* HasDisjunctSubRegs */
6927 : false, /* CoveredBySubRegs */
6928 : GPR32commonSuperclasses,
6929 : GPR32commonGetRawAllocationOrder
6930 : };
6931 :
6932 : extern const TargetRegisterClass CCRRegClass = {
6933 : &AArch64MCRegisterClasses[CCRRegClassID],
6934 : CCRSubClassMask,
6935 : SuperRegIdxSeqs + 1,
6936 : LaneBitmask(0x00000001),
6937 : 0,
6938 : false, /* HasDisjunctSubRegs */
6939 : false, /* CoveredBySubRegs */
6940 : NullRegClasses,
6941 : nullptr
6942 : };
6943 :
6944 : extern const TargetRegisterClass GPR32sponlyRegClass = {
6945 : &AArch64MCRegisterClasses[GPR32sponlyRegClassID],
6946 : GPR32sponlySubClassMask,
6947 : SuperRegIdxSeqs + 0,
6948 : LaneBitmask(0x00000001),
6949 : 0,
6950 : false, /* HasDisjunctSubRegs */
6951 : false, /* CoveredBySubRegs */
6952 : GPR32sponlySuperclasses,
6953 : nullptr
6954 : };
6955 :
6956 : extern const TargetRegisterClass WSeqPairsClassRegClass = {
6957 : &AArch64MCRegisterClasses[WSeqPairsClassRegClassID],
6958 : WSeqPairsClassSubClassMask,
6959 : SuperRegIdxSeqs + 69,
6960 : LaneBitmask(0x00000030),
6961 : 0,
6962 : true, /* HasDisjunctSubRegs */
6963 : true, /* CoveredBySubRegs */
6964 : NullRegClasses,
6965 : nullptr
6966 : };
6967 :
6968 : extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32commonRegClass = {
6969 : &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32commonRegClassID],
6970 : WSeqPairsClass_with_sube32_in_GPR32commonSubClassMask,
6971 : SuperRegIdxSeqs + 69,
6972 : LaneBitmask(0x00000030),
6973 : 0,
6974 : true, /* HasDisjunctSubRegs */
6975 : true, /* CoveredBySubRegs */
6976 : WSeqPairsClass_with_sube32_in_GPR32commonSuperclasses,
6977 : nullptr
6978 : };
6979 :
6980 : extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
6981 : &AArch64MCRegisterClasses[WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
6982 : WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
6983 : SuperRegIdxSeqs + 69,
6984 : LaneBitmask(0x00000030),
6985 : 0,
6986 : true, /* HasDisjunctSubRegs */
6987 : true, /* CoveredBySubRegs */
6988 : WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
6989 : nullptr
6990 : };
6991 :
6992 : extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
6993 : &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
6994 : WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
6995 : SuperRegIdxSeqs + 69,
6996 : LaneBitmask(0x00000030),
6997 : 0,
6998 : true, /* HasDisjunctSubRegs */
6999 : true, /* CoveredBySubRegs */
7000 : WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
7001 : nullptr
7002 : };
7003 :
7004 : extern const TargetRegisterClass GPR64allRegClass = {
7005 : &AArch64MCRegisterClasses[GPR64allRegClassID],
7006 : GPR64allSubClassMask,
7007 : SuperRegIdxSeqs + 2,
7008 : LaneBitmask(0x00000008),
7009 : 0,
7010 : false, /* HasDisjunctSubRegs */
7011 : false, /* CoveredBySubRegs */
7012 : NullRegClasses,
7013 : nullptr
7014 : };
7015 :
7016 : extern const TargetRegisterClass FPR64RegClass = {
7017 : &AArch64MCRegisterClasses[FPR64RegClassID],
7018 : FPR64SubClassMask,
7019 : SuperRegIdxSeqs + 26,
7020 : LaneBitmask(0x00000001),
7021 : 0,
7022 : false, /* HasDisjunctSubRegs */
7023 : false, /* CoveredBySubRegs */
7024 : NullRegClasses,
7025 : nullptr
7026 : };
7027 :
7028 : extern const TargetRegisterClass GPR64RegClass = {
7029 : &AArch64MCRegisterClasses[GPR64RegClassID],
7030 : GPR64SubClassMask,
7031 : SuperRegIdxSeqs + 2,
7032 : LaneBitmask(0x00000008),
7033 : 0,
7034 : false, /* HasDisjunctSubRegs */
7035 : false, /* CoveredBySubRegs */
7036 : GPR64Superclasses,
7037 : GPR64GetRawAllocationOrder
7038 : };
7039 :
7040 : extern const TargetRegisterClass GPR64spRegClass = {
7041 : &AArch64MCRegisterClasses[GPR64spRegClassID],
7042 : GPR64spSubClassMask,
7043 : SuperRegIdxSeqs + 2,
7044 : LaneBitmask(0x00000008),
7045 : 0,
7046 : false, /* HasDisjunctSubRegs */
7047 : false, /* CoveredBySubRegs */
7048 : GPR64spSuperclasses,
7049 : GPR64spGetRawAllocationOrder
7050 : };
7051 :
7052 : extern const TargetRegisterClass GPR64commonRegClass = {
7053 : &AArch64MCRegisterClasses[GPR64commonRegClassID],
7054 : GPR64commonSubClassMask,
7055 : SuperRegIdxSeqs + 2,
7056 : LaneBitmask(0x00000008),
7057 : 0,
7058 : false, /* HasDisjunctSubRegs */
7059 : false, /* CoveredBySubRegs */
7060 : GPR64commonSuperclasses,
7061 : GPR64commonGetRawAllocationOrder
7062 : };
7063 :
7064 : extern const TargetRegisterClass tcGPR64RegClass = {
7065 : &AArch64MCRegisterClasses[tcGPR64RegClassID],
7066 : tcGPR64SubClassMask,
7067 : SuperRegIdxSeqs + 2,
7068 : LaneBitmask(0x00000008),
7069 : 0,
7070 : false, /* HasDisjunctSubRegs */
7071 : false, /* CoveredBySubRegs */
7072 : tcGPR64Superclasses,
7073 : nullptr
7074 : };
7075 :
7076 : extern const TargetRegisterClass rtcGPR64RegClass = {
7077 : &AArch64MCRegisterClasses[rtcGPR64RegClassID],
7078 : rtcGPR64SubClassMask,
7079 : SuperRegIdxSeqs + 2,
7080 : LaneBitmask(0x00000008),
7081 : 0,
7082 : false, /* HasDisjunctSubRegs */
7083 : false, /* CoveredBySubRegs */
7084 : rtcGPR64Superclasses,
7085 : nullptr
7086 : };
7087 :
7088 : extern const TargetRegisterClass GPR64sponlyRegClass = {
7089 : &AArch64MCRegisterClasses[GPR64sponlyRegClassID],
7090 : GPR64sponlySubClassMask,
7091 : SuperRegIdxSeqs + 1,
7092 : LaneBitmask(0x00000008),
7093 : 0,
7094 : false, /* HasDisjunctSubRegs */
7095 : false, /* CoveredBySubRegs */
7096 : GPR64sponlySuperclasses,
7097 : nullptr
7098 : };
7099 :
7100 : extern const TargetRegisterClass DDRegClass = {
7101 : &AArch64MCRegisterClasses[DDRegClassID],
7102 : DDSubClassMask,
7103 : SuperRegIdxSeqs + 95,
7104 : LaneBitmask(0x00000081),
7105 : 0,
7106 : true, /* HasDisjunctSubRegs */
7107 : true, /* CoveredBySubRegs */
7108 : NullRegClasses,
7109 : nullptr
7110 : };
7111 :
7112 : extern const TargetRegisterClass XSeqPairsClassRegClass = {
7113 : &AArch64MCRegisterClasses[XSeqPairsClassRegClassID],
7114 : XSeqPairsClassSubClassMask,
7115 : SuperRegIdxSeqs + 1,
7116 : LaneBitmask(0x00002008),
7117 : 0,
7118 : true, /* HasDisjunctSubRegs */
7119 : true, /* CoveredBySubRegs */
7120 : NullRegClasses,
7121 : nullptr
7122 : };
7123 :
7124 : extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32commonRegClass = {
7125 : &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID],
7126 : XSeqPairsClass_with_sub_32_in_GPR32commonSubClassMask,
7127 : SuperRegIdxSeqs + 1,
7128 : LaneBitmask(0x00002008),
7129 : 0,
7130 : true, /* HasDisjunctSubRegs */
7131 : true, /* CoveredBySubRegs */
7132 : XSeqPairsClass_with_sub_32_in_GPR32commonSuperclasses,
7133 : nullptr
7134 : };
7135 :
7136 : extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
7137 : &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
7138 : XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
7139 : SuperRegIdxSeqs + 1,
7140 : LaneBitmask(0x00002008),
7141 : 0,
7142 : true, /* HasDisjunctSubRegs */
7143 : true, /* CoveredBySubRegs */
7144 : XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
7145 : nullptr
7146 : };
7147 :
7148 : extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
7149 : &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
7150 : XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
7151 : SuperRegIdxSeqs + 1,
7152 : LaneBitmask(0x00002008),
7153 : 0,
7154 : true, /* HasDisjunctSubRegs */
7155 : true, /* CoveredBySubRegs */
7156 : XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
7157 : nullptr
7158 : };
7159 :
7160 : extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = {
7161 : &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_tcGPR64RegClassID],
7162 : XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask,
7163 : SuperRegIdxSeqs + 1,
7164 : LaneBitmask(0x00002008),
7165 : 0,
7166 : true, /* HasDisjunctSubRegs */
7167 : true, /* CoveredBySubRegs */
7168 : XSeqPairsClass_with_sube64_in_tcGPR64Superclasses,
7169 : nullptr
7170 : };
7171 :
7172 : extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
7173 : &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
7174 : XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
7175 : SuperRegIdxSeqs + 1,
7176 : LaneBitmask(0x00002008),
7177 : 0,
7178 : true, /* HasDisjunctSubRegs */
7179 : true, /* CoveredBySubRegs */
7180 : XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
7181 : nullptr
7182 : };
7183 :
7184 : extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
7185 : &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
7186 : XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
7187 : SuperRegIdxSeqs + 1,
7188 : LaneBitmask(0x00002008),
7189 : 0,
7190 : true, /* HasDisjunctSubRegs */
7191 : true, /* CoveredBySubRegs */
7192 : XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
7193 : nullptr
7194 : };
7195 :
7196 : extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass = {
7197 : &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID],
7198 : XSeqPairsClass_with_sube64_in_rtcGPR64SubClassMask,
7199 : SuperRegIdxSeqs + 1,
7200 : LaneBitmask(0x00002008),
7201 : 0,
7202 : true, /* HasDisjunctSubRegs */
7203 : true, /* CoveredBySubRegs */
7204 : XSeqPairsClass_with_sube64_in_rtcGPR64Superclasses,
7205 : nullptr
7206 : };
7207 :
7208 : extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_rtcGPR64RegClass = {
7209 : &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID],
7210 : XSeqPairsClass_with_subo64_in_rtcGPR64SubClassMask,
7211 : SuperRegIdxSeqs + 1,
7212 : LaneBitmask(0x00002008),
7213 : 0,
7214 : true, /* HasDisjunctSubRegs */
7215 : true, /* CoveredBySubRegs */
7216 : XSeqPairsClass_with_subo64_in_rtcGPR64Superclasses,
7217 : nullptr
7218 : };
7219 :
7220 : extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClass = {
7221 : &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClassID],
7222 : XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64SubClassMask,
7223 : SuperRegIdxSeqs + 1,
7224 : LaneBitmask(0x00002008),
7225 : 0,
7226 : true, /* HasDisjunctSubRegs */
7227 : true, /* CoveredBySubRegs */
7228 : XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64Superclasses,
7229 : nullptr
7230 : };
7231 :
7232 : extern const TargetRegisterClass FPR128RegClass = {
7233 : &AArch64MCRegisterClasses[FPR128RegClassID],
7234 : FPR128SubClassMask,
7235 : SuperRegIdxSeqs + 60,
7236 : LaneBitmask(0x00000001),
7237 : 0,
7238 : false, /* HasDisjunctSubRegs */
7239 : false, /* CoveredBySubRegs */
7240 : NullRegClasses,
7241 : nullptr
7242 : };
7243 :
7244 : extern const TargetRegisterClass ZPRRegClass = {
7245 : &AArch64MCRegisterClasses[ZPRRegClassID],
7246 : ZPRSubClassMask,
7247 : SuperRegIdxSeqs + 5,
7248 : LaneBitmask(0x00000041),
7249 : 0,
7250 : true, /* HasDisjunctSubRegs */
7251 : false, /* CoveredBySubRegs */
7252 : NullRegClasses,
7253 : nullptr
7254 : };
7255 :
7256 : extern const TargetRegisterClass FPR128_loRegClass = {
7257 : &AArch64MCRegisterClasses[FPR128_loRegClassID],
7258 : FPR128_loSubClassMask,
7259 : SuperRegIdxSeqs + 60,
7260 : LaneBitmask(0x00000001),
7261 : 0,
7262 : false, /* HasDisjunctSubRegs */
7263 : false, /* CoveredBySubRegs */
7264 : FPR128_loSuperclasses,
7265 : nullptr
7266 : };
7267 :
7268 : extern const TargetRegisterClass ZPR_4bRegClass = {
7269 : &AArch64MCRegisterClasses[ZPR_4bRegClassID],
7270 : ZPR_4bSubClassMask,
7271 : SuperRegIdxSeqs + 5,
7272 : LaneBitmask(0x00000041),
7273 : 0,
7274 : true, /* HasDisjunctSubRegs */
7275 : false, /* CoveredBySubRegs */
7276 : ZPR_4bSuperclasses,
7277 : nullptr
7278 : };
7279 :
7280 : extern const TargetRegisterClass ZPR_3bRegClass = {
7281 : &AArch64MCRegisterClasses[ZPR_3bRegClassID],
7282 : ZPR_3bSubClassMask,
7283 : SuperRegIdxSeqs + 5,
7284 : LaneBitmask(0x00000041),
7285 : 0,
7286 : true, /* HasDisjunctSubRegs */
7287 : false, /* CoveredBySubRegs */
7288 : ZPR_3bSuperclasses,
7289 : nullptr
7290 : };
7291 :
7292 : extern const TargetRegisterClass DDDRegClass = {
7293 : &AArch64MCRegisterClasses[DDDRegClassID],
7294 : DDDSubClassMask,
7295 : SuperRegIdxSeqs + 83,
7296 : LaneBitmask(0x00000281),
7297 : 0,
7298 : true, /* HasDisjunctSubRegs */
7299 : true, /* CoveredBySubRegs */
7300 : NullRegClasses,
7301 : nullptr
7302 : };
7303 :
7304 : extern const TargetRegisterClass DDDDRegClass = {
7305 : &AArch64MCRegisterClasses[DDDDRegClassID],
7306 : DDDDSubClassMask,
7307 : SuperRegIdxSeqs + 71,
7308 : LaneBitmask(0x00000381),
7309 : 0,
7310 : true, /* HasDisjunctSubRegs */
7311 : true, /* CoveredBySubRegs */
7312 : NullRegClasses,
7313 : nullptr
7314 : };
7315 :
7316 : extern const TargetRegisterClass QQRegClass = {
7317 : &AArch64MCRegisterClasses[QQRegClassID],
7318 : QQSubClassMask,
7319 : SuperRegIdxSeqs + 105,
7320 : LaneBitmask(0x00000401),
7321 : 0,
7322 : true, /* HasDisjunctSubRegs */
7323 : true, /* CoveredBySubRegs */
7324 : NullRegClasses,
7325 : nullptr
7326 : };
7327 :
7328 : extern const TargetRegisterClass ZPR2RegClass = {
7329 : &AArch64MCRegisterClasses[ZPR2RegClassID],
7330 : ZPR2SubClassMask,
7331 : SuperRegIdxSeqs + 79,
7332 : LaneBitmask(0x0000C041),
7333 : 0,
7334 : true, /* HasDisjunctSubRegs */
7335 : true, /* CoveredBySubRegs */
7336 : NullRegClasses,
7337 : nullptr
7338 : };
7339 :
7340 : extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass = {
7341 : &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_loRegClassID],
7342 : QQ_with_qsub0_in_FPR128_loSubClassMask,
7343 : SuperRegIdxSeqs + 105,
7344 : LaneBitmask(0x00000401),
7345 : 0,
7346 : true, /* HasDisjunctSubRegs */
7347 : true, /* CoveredBySubRegs */
7348 : QQ_with_qsub0_in_FPR128_loSuperclasses,
7349 : nullptr
7350 : };
7351 :
7352 : extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = {
7353 : &AArch64MCRegisterClasses[QQ_with_qsub1_in_FPR128_loRegClassID],
7354 : QQ_with_qsub1_in_FPR128_loSubClassMask,
7355 : SuperRegIdxSeqs + 105,
7356 : LaneBitmask(0x00000401),
7357 : 0,
7358 : true, /* HasDisjunctSubRegs */
7359 : true, /* CoveredBySubRegs */
7360 : QQ_with_qsub1_in_FPR128_loSuperclasses,
7361 : nullptr
7362 : };
7363 :
7364 : extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass = {
7365 : &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_4bRegClassID],
7366 : ZPR2_with_zsub1_in_ZPR_4bSubClassMask,
7367 : SuperRegIdxSeqs + 79,
7368 : LaneBitmask(0x0000C041),
7369 : 0,
7370 : true, /* HasDisjunctSubRegs */
7371 : true, /* CoveredBySubRegs */
7372 : ZPR2_with_zsub1_in_ZPR_4bSuperclasses,
7373 : nullptr
7374 : };
7375 :
7376 : extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass = {
7377 : &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_loRegClassID],
7378 : ZPR2_with_zsub_in_FPR128_loSubClassMask,
7379 : SuperRegIdxSeqs + 79,
7380 : LaneBitmask(0x0000C041),
7381 : 0,
7382 : true, /* HasDisjunctSubRegs */
7383 : true, /* CoveredBySubRegs */
7384 : ZPR2_with_zsub_in_FPR128_loSuperclasses,
7385 : nullptr
7386 : };
7387 :
7388 : extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = {
7389 : &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID],
7390 : QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask,
7391 : SuperRegIdxSeqs + 105,
7392 : LaneBitmask(0x00000401),
7393 : 0,
7394 : true, /* HasDisjunctSubRegs */
7395 : true, /* CoveredBySubRegs */
7396 : QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses,
7397 : nullptr
7398 : };
7399 :
7400 : extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass = {
7401 : &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID],
7402 : ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask,
7403 : SuperRegIdxSeqs + 79,
7404 : LaneBitmask(0x0000C041),
7405 : 0,
7406 : true, /* HasDisjunctSubRegs */
7407 : true, /* CoveredBySubRegs */
7408 : ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses,
7409 : nullptr
7410 : };
7411 :
7412 : extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass = {
7413 : &AArch64MCRegisterClasses[ZPR2_with_zsub0_in_ZPR_3bRegClassID],
7414 : ZPR2_with_zsub0_in_ZPR_3bSubClassMask,
7415 : SuperRegIdxSeqs + 79,
7416 : LaneBitmask(0x0000C041),
7417 : 0,
7418 : true, /* HasDisjunctSubRegs */
7419 : true, /* CoveredBySubRegs */
7420 : ZPR2_with_zsub0_in_ZPR_3bSuperclasses,
7421 : nullptr
7422 : };
7423 :
7424 : extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass = {
7425 : &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_3bRegClassID],
7426 : ZPR2_with_zsub1_in_ZPR_3bSubClassMask,
7427 : SuperRegIdxSeqs + 79,
7428 : LaneBitmask(0x0000C041),
7429 : 0,
7430 : true, /* HasDisjunctSubRegs */
7431 : true, /* CoveredBySubRegs */
7432 : ZPR2_with_zsub1_in_ZPR_3bSuperclasses,
7433 : nullptr
7434 : };
7435 :
7436 : extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass = {
7437 : &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID],
7438 : ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask,
7439 : SuperRegIdxSeqs + 79,
7440 : LaneBitmask(0x0000C041),
7441 : 0,
7442 : true, /* HasDisjunctSubRegs */
7443 : true, /* CoveredBySubRegs */
7444 : ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses,
7445 : nullptr
7446 : };
7447 :
7448 : extern const TargetRegisterClass QQQRegClass = {
7449 : &AArch64MCRegisterClasses[QQQRegClassID],
7450 : QQQSubClassMask,
7451 : SuperRegIdxSeqs + 90,
7452 : LaneBitmask(0x00001401),
7453 : 0,
7454 : true, /* HasDisjunctSubRegs */
7455 : true, /* CoveredBySubRegs */
7456 : NullRegClasses,
7457 : nullptr
7458 : };
7459 :
7460 : extern const TargetRegisterClass ZPR3RegClass = {
7461 : &AArch64MCRegisterClasses[ZPR3RegClassID],
7462 : ZPR3SubClassMask,
7463 : SuperRegIdxSeqs + 76,
7464 : LaneBitmask(0x000CC041),
7465 : 0,
7466 : true, /* HasDisjunctSubRegs */
7467 : true, /* CoveredBySubRegs */
7468 : NullRegClasses,
7469 : nullptr
7470 : };
7471 :
7472 : extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass = {
7473 : &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_loRegClassID],
7474 : QQQ_with_qsub0_in_FPR128_loSubClassMask,
7475 : SuperRegIdxSeqs + 90,
7476 : LaneBitmask(0x00001401),
7477 : 0,
7478 : true, /* HasDisjunctSubRegs */
7479 : true, /* CoveredBySubRegs */
7480 : QQQ_with_qsub0_in_FPR128_loSuperclasses,
7481 : nullptr
7482 : };
7483 :
7484 : extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = {
7485 : &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_loRegClassID],
7486 : QQQ_with_qsub1_in_FPR128_loSubClassMask,
7487 : SuperRegIdxSeqs + 90,
7488 : LaneBitmask(0x00001401),
7489 : 0,
7490 : true, /* HasDisjunctSubRegs */
7491 : true, /* CoveredBySubRegs */
7492 : QQQ_with_qsub1_in_FPR128_loSuperclasses,
7493 : nullptr
7494 : };
7495 :
7496 : extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = {
7497 : &AArch64MCRegisterClasses[QQQ_with_qsub2_in_FPR128_loRegClassID],
7498 : QQQ_with_qsub2_in_FPR128_loSubClassMask,
7499 : SuperRegIdxSeqs + 90,
7500 : LaneBitmask(0x00001401),
7501 : 0,
7502 : true, /* HasDisjunctSubRegs */
7503 : true, /* CoveredBySubRegs */
7504 : QQQ_with_qsub2_in_FPR128_loSuperclasses,
7505 : nullptr
7506 : };
7507 :
7508 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass = {
7509 : &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4bRegClassID],
7510 : ZPR3_with_zsub1_in_ZPR_4bSubClassMask,
7511 : SuperRegIdxSeqs + 76,
7512 : LaneBitmask(0x000CC041),
7513 : 0,
7514 : true, /* HasDisjunctSubRegs */
7515 : true, /* CoveredBySubRegs */
7516 : ZPR3_with_zsub1_in_ZPR_4bSuperclasses,
7517 : nullptr
7518 : };
7519 :
7520 : extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7521 : &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_4bRegClassID],
7522 : ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
7523 : SuperRegIdxSeqs + 76,
7524 : LaneBitmask(0x000CC041),
7525 : 0,
7526 : true, /* HasDisjunctSubRegs */
7527 : true, /* CoveredBySubRegs */
7528 : ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
7529 : nullptr
7530 : };
7531 :
7532 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass = {
7533 : &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_loRegClassID],
7534 : ZPR3_with_zsub_in_FPR128_loSubClassMask,
7535 : SuperRegIdxSeqs + 76,
7536 : LaneBitmask(0x000CC041),
7537 : 0,
7538 : true, /* HasDisjunctSubRegs */
7539 : true, /* CoveredBySubRegs */
7540 : ZPR3_with_zsub_in_FPR128_loSuperclasses,
7541 : nullptr
7542 : };
7543 :
7544 : extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = {
7545 : &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID],
7546 : QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask,
7547 : SuperRegIdxSeqs + 90,
7548 : LaneBitmask(0x00001401),
7549 : 0,
7550 : true, /* HasDisjunctSubRegs */
7551 : true, /* CoveredBySubRegs */
7552 : QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses,
7553 : nullptr
7554 : };
7555 :
7556 : extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
7557 : &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
7558 : QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
7559 : SuperRegIdxSeqs + 90,
7560 : LaneBitmask(0x00001401),
7561 : 0,
7562 : true, /* HasDisjunctSubRegs */
7563 : true, /* CoveredBySubRegs */
7564 : QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
7565 : nullptr
7566 : };
7567 :
7568 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7569 : &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID],
7570 : ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
7571 : SuperRegIdxSeqs + 76,
7572 : LaneBitmask(0x000CC041),
7573 : 0,
7574 : true, /* HasDisjunctSubRegs */
7575 : true, /* CoveredBySubRegs */
7576 : ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
7577 : nullptr
7578 : };
7579 :
7580 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass = {
7581 : &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID],
7582 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask,
7583 : SuperRegIdxSeqs + 76,
7584 : LaneBitmask(0x000CC041),
7585 : 0,
7586 : true, /* HasDisjunctSubRegs */
7587 : true, /* CoveredBySubRegs */
7588 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses,
7589 : nullptr
7590 : };
7591 :
7592 : extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
7593 : &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
7594 : QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
7595 : SuperRegIdxSeqs + 90,
7596 : LaneBitmask(0x00001401),
7597 : 0,
7598 : true, /* HasDisjunctSubRegs */
7599 : true, /* CoveredBySubRegs */
7600 : QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
7601 : nullptr
7602 : };
7603 :
7604 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7605 : &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID],
7606 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
7607 : SuperRegIdxSeqs + 76,
7608 : LaneBitmask(0x000CC041),
7609 : 0,
7610 : true, /* HasDisjunctSubRegs */
7611 : true, /* CoveredBySubRegs */
7612 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
7613 : nullptr
7614 : };
7615 :
7616 : extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass = {
7617 : &AArch64MCRegisterClasses[ZPR3_with_zsub0_in_ZPR_3bRegClassID],
7618 : ZPR3_with_zsub0_in_ZPR_3bSubClassMask,
7619 : SuperRegIdxSeqs + 76,
7620 : LaneBitmask(0x000CC041),
7621 : 0,
7622 : true, /* HasDisjunctSubRegs */
7623 : true, /* CoveredBySubRegs */
7624 : ZPR3_with_zsub0_in_ZPR_3bSuperclasses,
7625 : nullptr
7626 : };
7627 :
7628 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass = {
7629 : &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3bRegClassID],
7630 : ZPR3_with_zsub1_in_ZPR_3bSubClassMask,
7631 : SuperRegIdxSeqs + 76,
7632 : LaneBitmask(0x000CC041),
7633 : 0,
7634 : true, /* HasDisjunctSubRegs */
7635 : true, /* CoveredBySubRegs */
7636 : ZPR3_with_zsub1_in_ZPR_3bSuperclasses,
7637 : nullptr
7638 : };
7639 :
7640 : extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7641 : &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_3bRegClassID],
7642 : ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
7643 : SuperRegIdxSeqs + 76,
7644 : LaneBitmask(0x000CC041),
7645 : 0,
7646 : true, /* HasDisjunctSubRegs */
7647 : true, /* CoveredBySubRegs */
7648 : ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
7649 : nullptr
7650 : };
7651 :
7652 : extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7653 : &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID],
7654 : ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
7655 : SuperRegIdxSeqs + 76,
7656 : LaneBitmask(0x000CC041),
7657 : 0,
7658 : true, /* HasDisjunctSubRegs */
7659 : true, /* CoveredBySubRegs */
7660 : ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
7661 : nullptr
7662 : };
7663 :
7664 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass = {
7665 : &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID],
7666 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask,
7667 : SuperRegIdxSeqs + 76,
7668 : LaneBitmask(0x000CC041),
7669 : 0,
7670 : true, /* HasDisjunctSubRegs */
7671 : true, /* CoveredBySubRegs */
7672 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses,
7673 : nullptr
7674 : };
7675 :
7676 : extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7677 : &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID],
7678 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
7679 : SuperRegIdxSeqs + 76,
7680 : LaneBitmask(0x000CC041),
7681 : 0,
7682 : true, /* HasDisjunctSubRegs */
7683 : true, /* CoveredBySubRegs */
7684 : ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
7685 : nullptr
7686 : };
7687 :
7688 : extern const TargetRegisterClass QQQQRegClass = {
7689 : &AArch64MCRegisterClasses[QQQQRegClassID],
7690 : QQQQSubClassMask,
7691 : SuperRegIdxSeqs + 74,
7692 : LaneBitmask(0x00001C01),
7693 : 0,
7694 : true, /* HasDisjunctSubRegs */
7695 : true, /* CoveredBySubRegs */
7696 : NullRegClasses,
7697 : nullptr
7698 : };
7699 :
7700 : extern const TargetRegisterClass ZPR4RegClass = {
7701 : &AArch64MCRegisterClasses[ZPR4RegClassID],
7702 : ZPR4SubClassMask,
7703 : SuperRegIdxSeqs + 1,
7704 : LaneBitmask(0x000FC041),
7705 : 0,
7706 : true, /* HasDisjunctSubRegs */
7707 : true, /* CoveredBySubRegs */
7708 : NullRegClasses,
7709 : nullptr
7710 : };
7711 :
7712 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass = {
7713 : &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_loRegClassID],
7714 : QQQQ_with_qsub0_in_FPR128_loSubClassMask,
7715 : SuperRegIdxSeqs + 74,
7716 : LaneBitmask(0x00001C01),
7717 : 0,
7718 : true, /* HasDisjunctSubRegs */
7719 : true, /* CoveredBySubRegs */
7720 : QQQQ_with_qsub0_in_FPR128_loSuperclasses,
7721 : nullptr
7722 : };
7723 :
7724 : extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = {
7725 : &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_loRegClassID],
7726 : QQQQ_with_qsub1_in_FPR128_loSubClassMask,
7727 : SuperRegIdxSeqs + 74,
7728 : LaneBitmask(0x00001C01),
7729 : 0,
7730 : true, /* HasDisjunctSubRegs */
7731 : true, /* CoveredBySubRegs */
7732 : QQQQ_with_qsub1_in_FPR128_loSuperclasses,
7733 : nullptr
7734 : };
7735 :
7736 : extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = {
7737 : &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_loRegClassID],
7738 : QQQQ_with_qsub2_in_FPR128_loSubClassMask,
7739 : SuperRegIdxSeqs + 74,
7740 : LaneBitmask(0x00001C01),
7741 : 0,
7742 : true, /* HasDisjunctSubRegs */
7743 : true, /* CoveredBySubRegs */
7744 : QQQQ_with_qsub2_in_FPR128_loSuperclasses,
7745 : nullptr
7746 : };
7747 :
7748 : extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = {
7749 : &AArch64MCRegisterClasses[QQQQ_with_qsub3_in_FPR128_loRegClassID],
7750 : QQQQ_with_qsub3_in_FPR128_loSubClassMask,
7751 : SuperRegIdxSeqs + 74,
7752 : LaneBitmask(0x00001C01),
7753 : 0,
7754 : true, /* HasDisjunctSubRegs */
7755 : true, /* CoveredBySubRegs */
7756 : QQQQ_with_qsub3_in_FPR128_loSuperclasses,
7757 : nullptr
7758 : };
7759 :
7760 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass = {
7761 : &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4bRegClassID],
7762 : ZPR4_with_zsub1_in_ZPR_4bSubClassMask,
7763 : SuperRegIdxSeqs + 1,
7764 : LaneBitmask(0x000FC041),
7765 : 0,
7766 : true, /* HasDisjunctSubRegs */
7767 : true, /* CoveredBySubRegs */
7768 : ZPR4_with_zsub1_in_ZPR_4bSuperclasses,
7769 : nullptr
7770 : };
7771 :
7772 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass = {
7773 : &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4bRegClassID],
7774 : ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
7775 : SuperRegIdxSeqs + 1,
7776 : LaneBitmask(0x000FC041),
7777 : 0,
7778 : true, /* HasDisjunctSubRegs */
7779 : true, /* CoveredBySubRegs */
7780 : ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
7781 : nullptr
7782 : };
7783 :
7784 : extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7785 : &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_4bRegClassID],
7786 : ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
7787 : SuperRegIdxSeqs + 1,
7788 : LaneBitmask(0x000FC041),
7789 : 0,
7790 : true, /* HasDisjunctSubRegs */
7791 : true, /* CoveredBySubRegs */
7792 : ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
7793 : nullptr
7794 : };
7795 :
7796 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass = {
7797 : &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_loRegClassID],
7798 : ZPR4_with_zsub_in_FPR128_loSubClassMask,
7799 : SuperRegIdxSeqs + 1,
7800 : LaneBitmask(0x000FC041),
7801 : 0,
7802 : true, /* HasDisjunctSubRegs */
7803 : true, /* CoveredBySubRegs */
7804 : ZPR4_with_zsub_in_FPR128_loSuperclasses,
7805 : nullptr
7806 : };
7807 :
7808 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = {
7809 : &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID],
7810 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask,
7811 : SuperRegIdxSeqs + 74,
7812 : LaneBitmask(0x00001C01),
7813 : 0,
7814 : true, /* HasDisjunctSubRegs */
7815 : true, /* CoveredBySubRegs */
7816 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses,
7817 : nullptr
7818 : };
7819 :
7820 : extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
7821 : &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
7822 : QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
7823 : SuperRegIdxSeqs + 74,
7824 : LaneBitmask(0x00001C01),
7825 : 0,
7826 : true, /* HasDisjunctSubRegs */
7827 : true, /* CoveredBySubRegs */
7828 : QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
7829 : nullptr
7830 : };
7831 :
7832 : extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
7833 : &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
7834 : QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
7835 : SuperRegIdxSeqs + 74,
7836 : LaneBitmask(0x00001C01),
7837 : 0,
7838 : true, /* HasDisjunctSubRegs */
7839 : true, /* CoveredBySubRegs */
7840 : QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
7841 : nullptr
7842 : };
7843 :
7844 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
7845 : &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID],
7846 : ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
7847 : SuperRegIdxSeqs + 1,
7848 : LaneBitmask(0x000FC041),
7849 : 0,
7850 : true, /* HasDisjunctSubRegs */
7851 : true, /* CoveredBySubRegs */
7852 : ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
7853 : nullptr
7854 : };
7855 :
7856 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7857 : &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
7858 : ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
7859 : SuperRegIdxSeqs + 1,
7860 : LaneBitmask(0x000FC041),
7861 : 0,
7862 : true, /* HasDisjunctSubRegs */
7863 : true, /* CoveredBySubRegs */
7864 : ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
7865 : nullptr
7866 : };
7867 :
7868 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass = {
7869 : &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID],
7870 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask,
7871 : SuperRegIdxSeqs + 1,
7872 : LaneBitmask(0x000FC041),
7873 : 0,
7874 : true, /* HasDisjunctSubRegs */
7875 : true, /* CoveredBySubRegs */
7876 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses,
7877 : nullptr
7878 : };
7879 :
7880 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
7881 : &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
7882 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
7883 : SuperRegIdxSeqs + 74,
7884 : LaneBitmask(0x00001C01),
7885 : 0,
7886 : true, /* HasDisjunctSubRegs */
7887 : true, /* CoveredBySubRegs */
7888 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
7889 : nullptr
7890 : };
7891 :
7892 : extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
7893 : &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
7894 : QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
7895 : SuperRegIdxSeqs + 74,
7896 : LaneBitmask(0x00001C01),
7897 : 0,
7898 : true, /* HasDisjunctSubRegs */
7899 : true, /* CoveredBySubRegs */
7900 : QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
7901 : nullptr
7902 : };
7903 :
7904 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7905 : &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
7906 : ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
7907 : SuperRegIdxSeqs + 1,
7908 : LaneBitmask(0x000FC041),
7909 : 0,
7910 : true, /* HasDisjunctSubRegs */
7911 : true, /* CoveredBySubRegs */
7912 : ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
7913 : nullptr
7914 : };
7915 :
7916 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
7917 : &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID],
7918 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
7919 : SuperRegIdxSeqs + 1,
7920 : LaneBitmask(0x000FC041),
7921 : 0,
7922 : true, /* HasDisjunctSubRegs */
7923 : true, /* CoveredBySubRegs */
7924 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
7925 : nullptr
7926 : };
7927 :
7928 : extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
7929 : &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
7930 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
7931 : SuperRegIdxSeqs + 74,
7932 : LaneBitmask(0x00001C01),
7933 : 0,
7934 : true, /* HasDisjunctSubRegs */
7935 : true, /* CoveredBySubRegs */
7936 : QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
7937 : nullptr
7938 : };
7939 :
7940 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7941 : &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
7942 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
7943 : SuperRegIdxSeqs + 1,
7944 : LaneBitmask(0x000FC041),
7945 : 0,
7946 : true, /* HasDisjunctSubRegs */
7947 : true, /* CoveredBySubRegs */
7948 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
7949 : nullptr
7950 : };
7951 :
7952 : extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass = {
7953 : &AArch64MCRegisterClasses[ZPR4_with_zsub0_in_ZPR_3bRegClassID],
7954 : ZPR4_with_zsub0_in_ZPR_3bSubClassMask,
7955 : SuperRegIdxSeqs + 1,
7956 : LaneBitmask(0x000FC041),
7957 : 0,
7958 : true, /* HasDisjunctSubRegs */
7959 : true, /* CoveredBySubRegs */
7960 : ZPR4_with_zsub0_in_ZPR_3bSuperclasses,
7961 : nullptr
7962 : };
7963 :
7964 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass = {
7965 : &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3bRegClassID],
7966 : ZPR4_with_zsub1_in_ZPR_3bSubClassMask,
7967 : SuperRegIdxSeqs + 1,
7968 : LaneBitmask(0x000FC041),
7969 : 0,
7970 : true, /* HasDisjunctSubRegs */
7971 : true, /* CoveredBySubRegs */
7972 : ZPR4_with_zsub1_in_ZPR_3bSuperclasses,
7973 : nullptr
7974 : };
7975 :
7976 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass = {
7977 : &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3bRegClassID],
7978 : ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
7979 : SuperRegIdxSeqs + 1,
7980 : LaneBitmask(0x000FC041),
7981 : 0,
7982 : true, /* HasDisjunctSubRegs */
7983 : true, /* CoveredBySubRegs */
7984 : ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
7985 : nullptr
7986 : };
7987 :
7988 : extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass = {
7989 : &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_3bRegClassID],
7990 : ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
7991 : SuperRegIdxSeqs + 1,
7992 : LaneBitmask(0x000FC041),
7993 : 0,
7994 : true, /* HasDisjunctSubRegs */
7995 : true, /* CoveredBySubRegs */
7996 : ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
7997 : nullptr
7998 : };
7999 :
8000 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8001 : &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID],
8002 : ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
8003 : SuperRegIdxSeqs + 1,
8004 : LaneBitmask(0x000FC041),
8005 : 0,
8006 : true, /* HasDisjunctSubRegs */
8007 : true, /* CoveredBySubRegs */
8008 : ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
8009 : nullptr
8010 : };
8011 :
8012 : extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8013 : &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
8014 : ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
8015 : SuperRegIdxSeqs + 1,
8016 : LaneBitmask(0x000FC041),
8017 : 0,
8018 : true, /* HasDisjunctSubRegs */
8019 : true, /* CoveredBySubRegs */
8020 : ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
8021 : nullptr
8022 : };
8023 :
8024 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass = {
8025 : &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID],
8026 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask,
8027 : SuperRegIdxSeqs + 1,
8028 : LaneBitmask(0x000FC041),
8029 : 0,
8030 : true, /* HasDisjunctSubRegs */
8031 : true, /* CoveredBySubRegs */
8032 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses,
8033 : nullptr
8034 : };
8035 :
8036 : extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8037 : &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
8038 : ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
8039 : SuperRegIdxSeqs + 1,
8040 : LaneBitmask(0x000FC041),
8041 : 0,
8042 : true, /* HasDisjunctSubRegs */
8043 : true, /* CoveredBySubRegs */
8044 : ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
8045 : nullptr
8046 : };
8047 :
8048 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8049 : &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID],
8050 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
8051 : SuperRegIdxSeqs + 1,
8052 : LaneBitmask(0x000FC041),
8053 : 0,
8054 : true, /* HasDisjunctSubRegs */
8055 : true, /* CoveredBySubRegs */
8056 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
8057 : nullptr
8058 : };
8059 :
8060 : extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8061 : &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
8062 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
8063 : SuperRegIdxSeqs + 1,
8064 : LaneBitmask(0x000FC041),
8065 : 0,
8066 : true, /* HasDisjunctSubRegs */
8067 : true, /* CoveredBySubRegs */
8068 : ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
8069 : nullptr
8070 : };
8071 :
8072 : } // end namespace AArch64
8073 :
8074 : namespace {
8075 : const TargetRegisterClass* const RegisterClasses[] = {
8076 : &AArch64::FPR8RegClass,
8077 : &AArch64::FPR16RegClass,
8078 : &AArch64::PPRRegClass,
8079 : &AArch64::PPR_3bRegClass,
8080 : &AArch64::GPR32allRegClass,
8081 : &AArch64::FPR32RegClass,
8082 : &AArch64::GPR32RegClass,
8083 : &AArch64::GPR32spRegClass,
8084 : &AArch64::GPR32commonRegClass,
8085 : &AArch64::CCRRegClass,
8086 : &AArch64::GPR32sponlyRegClass,
8087 : &AArch64::WSeqPairsClassRegClass,
8088 : &AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClass,
8089 : &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
8090 : &AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
8091 : &AArch64::GPR64allRegClass,
8092 : &AArch64::FPR64RegClass,
8093 : &AArch64::GPR64RegClass,
8094 : &AArch64::GPR64spRegClass,
8095 : &AArch64::GPR64commonRegClass,
8096 : &AArch64::tcGPR64RegClass,
8097 : &AArch64::rtcGPR64RegClass,
8098 : &AArch64::GPR64sponlyRegClass,
8099 : &AArch64::DDRegClass,
8100 : &AArch64::XSeqPairsClassRegClass,
8101 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClass,
8102 : &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
8103 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
8104 : &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
8105 : &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
8106 : &AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
8107 : &AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClass,
8108 : &AArch64::XSeqPairsClass_with_subo64_in_rtcGPR64RegClass,
8109 : &AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64_and_XSeqPairsClass_with_subo64_in_rtcGPR64RegClass,
8110 : &AArch64::FPR128RegClass,
8111 : &AArch64::ZPRRegClass,
8112 : &AArch64::FPR128_loRegClass,
8113 : &AArch64::ZPR_4bRegClass,
8114 : &AArch64::ZPR_3bRegClass,
8115 : &AArch64::DDDRegClass,
8116 : &AArch64::DDDDRegClass,
8117 : &AArch64::QQRegClass,
8118 : &AArch64::ZPR2RegClass,
8119 : &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
8120 : &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
8121 : &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
8122 : &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
8123 : &AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass,
8124 : &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
8125 : &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass,
8126 : &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass,
8127 : &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass,
8128 : &AArch64::QQQRegClass,
8129 : &AArch64::ZPR3RegClass,
8130 : &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
8131 : &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
8132 : &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
8133 : &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
8134 : &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
8135 : &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
8136 : &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
8137 : &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
8138 : &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
8139 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
8140 : &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
8141 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
8142 : &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
8143 : &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
8144 : &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
8145 : &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
8146 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass,
8147 : &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
8148 : &AArch64::QQQQRegClass,
8149 : &AArch64::ZPR4RegClass,
8150 : &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
8151 : &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
8152 : &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
8153 : &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
8154 : &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
8155 : &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
8156 : &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
8157 : &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
8158 : &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
8159 : &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
8160 : &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
8161 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
8162 : &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
8163 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
8164 : &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
8165 : &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
8166 : &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
8167 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
8168 : &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
8169 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
8170 : &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
8171 : &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
8172 : &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
8173 : &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
8174 : &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
8175 : &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
8176 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
8177 : &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
8178 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
8179 : &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
8180 : };
8181 : } // end anonymous namespace
8182 :
8183 : static const TargetRegisterInfoDesc AArch64RegInfoDesc[] = { // Extra Descriptors
8184 : { 0, false },
8185 : { 0, false },
8186 : { 0, true },
8187 : { 0, true },
8188 : { 0, false },
8189 : { 0, true },
8190 : { 0, true },
8191 : { 0, true },
8192 : { 0, true },
8193 : { 0, true },
8194 : { 0, true },
8195 : { 0, true },
8196 : { 0, true },
8197 : { 0, true },
8198 : { 0, true },
8199 : { 0, true },
8200 : { 0, true },
8201 : { 0, true },
8202 : { 0, true },
8203 : { 0, true },
8204 : { 0, true },
8205 : { 0, true },
8206 : { 0, true },
8207 : { 0, true },
8208 : { 0, true },
8209 : { 0, true },
8210 : { 0, true },
8211 : { 0, true },
8212 : { 0, true },
8213 : { 0, true },
8214 : { 0, true },
8215 : { 0, true },
8216 : { 0, true },
8217 : { 0, true },
8218 : { 0, true },
8219 : { 0, true },
8220 : { 0, true },
8221 : { 0, true },
8222 : { 0, true },
8223 : { 0, true },
8224 : { 0, true },
8225 : { 0, true },
8226 : { 0, true },
8227 : { 0, true },
8228 : { 0, true },
8229 : { 0, true },
8230 : { 0, true },
8231 : { 0, true },
8232 : { 0, true },
8233 : { 0, true },
8234 : { 0, true },
8235 : { 0, true },
8236 : { 0, true },
8237 : { 0, true },
8238 : { 0, true },
8239 : { 0, true },
8240 : { 0, true },
8241 : { 0, true },
8242 : { 0, true },
8243 : { 0, true },
8244 : { 0, true },
8245 : { 0, true },
8246 : { 0, true },
8247 : { 0, true },
8248 : { 0, true },
8249 : { 0, true },
8250 : { 0, true },
8251 : { 0, true },
8252 : { 0, true },
8253 : { 0, true },
8254 : { 0, true },
8255 : { 0, true },
8256 : { 0, true },
8257 : { 0, true },
8258 : { 0, true },
8259 : { 0, true },
8260 : { 0, true },
8261 : { 0, true },
8262 : { 0, true },
8263 : { 0, true },
8264 : { 0, true },
8265 : { 0, true },
8266 : { 0, true },
8267 : { 0, true },
8268 : { 0, true },
8269 : { 0, true },
8270 : { 0, true },
8271 : { 0, true },
8272 : { 0, true },
8273 : { 0, true },
8274 : { 0, true },
8275 : { 0, true },
8276 : { 0, true },
8277 : { 0, true },
8278 : { 0, true },
8279 : { 0, true },
8280 : { 0, true },
8281 : { 0, true },
8282 : { 0, true },
8283 : { 0, true },
8284 : { 0, true },
8285 : { 0, true },
8286 : { 0, true },
8287 : { 0, true },
8288 : { 0, true },
8289 : { 0, true },
8290 : { 0, true },
8291 : { 0, true },
8292 : { 0, true },
8293 : { 0, true },
8294 : { 0, true },
8295 : { 0, true },
8296 : { 0, true },
8297 : { 0, true },
8298 : { 0, true },
8299 : { 0, true },
8300 : { 0, true },
8301 : { 0, true },
8302 : { 0, true },
8303 : { 0, true },
8304 : { 0, true },
8305 : { 0, true },
8306 : { 0, true },
8307 : { 0, true },
8308 : { 0, true },
8309 : { 0, true },
8310 : { 0, true },
8311 : { 0, true },
8312 : { 0, true },
8313 : { 0, true },
8314 : { 0, true },
8315 : { 0, true },
8316 : { 0, true },
8317 : { 0, true },
8318 : { 0, true },
8319 : { 0, true },
8320 : { 0, true },
8321 : { 0, true },
8322 : { 0, true },
8323 : { 0, true },
8324 : { 0, true },
8325 : { 0, true },
8326 : { 0, true },
8327 : { 0, true },
8328 : { 0, true },
8329 : { 0, true },
8330 : { 0, true },
8331 : { 0, true },
8332 : { 0, true },
8333 : { 0, true },
8334 : { 0, true },
8335 : { 0, true },
8336 : { 0, true },
8337 : { 0, true },
8338 : { 0, true },
8339 : { 0, true },
8340 : { 0, true },
8341 : { 0, true },
8342 : { 0, true },
8343 : { 0, true },
8344 : { 0, true },
8345 : { 0, true },
8346 : { 0, true },
8347 : { 0, true },
8348 : { 0, true },
8349 : { 0, true },
8350 : { 0, true },
8351 : { 0, true },
8352 : { 0, true },
8353 : { 0, true },
8354 : { 0, true },
8355 : { 0, true },
8356 : { 0, true },
8357 : { 0, true },
8358 : { 0, true },
8359 : { 0, true },
8360 : { 0, true },
8361 : { 0, true },
8362 : { 0, true },
8363 : { 0, true },
8364 : { 0, true },
8365 : { 0, true },
8366 : { 0, true },
8367 : { 0, true },
8368 : { 0, true },
8369 : { 0, true },
8370 : { 0, true },
8371 : { 0, true },
8372 : { 0, true },
8373 : { 0, true },
8374 : { 0, true },
8375 : { 0, true },
8376 : { 0, true },
8377 : { 0, true },
8378 : { 0, true },
8379 : { 0, true },
8380 : { 0, true },
8381 : { 0, true },
8382 : { 0, true },
8383 : { 0, true },
8384 : { 0, true },
8385 : { 0, true },
8386 : { 0, true },
8387 : { 0, true },
8388 : { 0, true },
8389 : { 0, true },
8390 : { 0, true },
8391 : { 0, true },
8392 : { 0, true },
8393 : { 0, true },
8394 : { 0, true },
8395 : { 0, true },
8396 : { 0, true },
8397 : { 0, true },
8398 : { 0, true },
8399 : { 0, true },
8400 : { 0, true },
8401 : { 0, true },
8402 : { 0, true },
8403 : { 0, true },
8404 : { 0, true },
8405 : { 0, true },
8406 : { 0, true },
8407 : { 0, true },
8408 : { 0, true },
8409 : { 0, true },
8410 : { 0, true },
8411 : { 0, true },
8412 : { 0, true },
8413 : { 0, true },
8414 : { 0, true },
8415 : { 0, true },
8416 : { 0, true },
8417 : { 0, true },
8418 : { 0, true },
8419 : { 0, true },
8420 : { 0, true },
8421 : { 0, true },
8422 : { 0, true },
8423 : { 0, true },
8424 : { 0, true },
8425 : { 0, true },
8426 : { 0, true },
8427 : { 0, true },
8428 : { 0, true },
8429 : { 0, true },
8430 : { 0, true },
8431 : { 0, true },
8432 : { 0, true },
8433 : { 0, true },
8434 : { 0, true },
8435 : { 0, true },
8436 : { 0, true },
8437 : { 0, true },
8438 : { 0, true },
8439 : { 0, true },
8440 : { 0, true },
8441 : { 0, true },
8442 : { 0, true },
8443 : { 0, true },
8444 : { 0, true },
8445 : { 0, true },
8446 : { 0, true },
8447 : { 0, true },
8448 : { 0, true },
8449 : { 0, true },
8450 : { 0, true },
8451 : { 0, true },
8452 : { 0, true },
8453 : { 0, true },
8454 : { 0, true },
8455 : { 0, true },
8456 : { 0, true },
8457 : { 0, true },
8458 : { 0, true },
8459 : { 0, true },
8460 : { 0, true },
8461 : { 0, false },
8462 : { 0, false },
8463 : { 0, false },
8464 : { 0, false },
8465 : { 0, false },
8466 : { 0, false },
8467 : { 0, false },
8468 : { 0, false },
8469 : { 0, false },
8470 : { 0, false },
8471 : { 0, false },
8472 : { 0, false },
8473 : { 0, false },
8474 : { 0, false },
8475 : { 0, false },
8476 : { 0, false },
8477 : { 0, false },
8478 : { 0, false },
8479 : { 0, false },
8480 : { 0, false },
8481 : { 0, false },
8482 : { 0, false },
8483 : { 0, false },
8484 : { 0, false },
8485 : { 0, false },
8486 : { 0, false },
8487 : { 0, false },
8488 : { 0, false },
8489 : { 0, false },
8490 : { 0, false },
8491 : { 0, false },
8492 : { 0, false },
8493 : { 0, true },
8494 : { 0, true },
8495 : { 0, true },
8496 : { 0, true },
8497 : { 0, true },
8498 : { 0, true },
8499 : { 0, true },
8500 : { 0, true },
8501 : { 0, true },
8502 : { 0, true },
8503 : { 0, true },
8504 : { 0, true },
8505 : { 0, true },
8506 : { 0, true },
8507 : { 0, true },
8508 : { 0, true },
8509 : { 0, true },
8510 : { 0, true },
8511 : { 0, true },
8512 : { 0, true },
8513 : { 0, true },
8514 : { 0, true },
8515 : { 0, true },
8516 : { 0, true },
8517 : { 0, true },
8518 : { 0, true },
8519 : { 0, true },
8520 : { 0, true },
8521 : { 0, true },
8522 : { 0, true },
8523 : { 0, true },
8524 : { 0, true },
8525 : { 0, true },
8526 : { 0, true },
8527 : { 0, true },
8528 : { 0, true },
8529 : { 0, true },
8530 : { 0, true },
8531 : { 0, true },
8532 : { 0, true },
8533 : { 0, true },
8534 : { 0, true },
8535 : { 0, true },
8536 : { 0, true },
8537 : { 0, true },
8538 : { 0, true },
8539 : { 0, true },
8540 : { 0, true },
8541 : { 0, true },
8542 : { 0, true },
8543 : { 0, true },
8544 : { 0, true },
8545 : { 0, true },
8546 : { 0, true },
8547 : { 0, true },
8548 : { 0, true },
8549 : { 0, true },
8550 : { 0, true },
8551 : { 0, true },
8552 : { 0, true },
8553 : { 0, true },
8554 : { 0, true },
8555 : { 0, true },
8556 : { 0, true },
8557 : { 0, true },
8558 : { 0, true },
8559 : { 0, true },
8560 : { 0, true },
8561 : { 0, true },
8562 : { 0, true },
8563 : { 0, true },
8564 : { 0, true },
8565 : { 0, true },
8566 : { 0, true },
8567 : { 0, true },
8568 : { 0, true },
8569 : { 0, true },
8570 : { 0, true },
8571 : { 0, true },
8572 : { 0, true },
8573 : { 0, true },
8574 : { 0, true },
8575 : { 0, true },
8576 : { 0, true },
8577 : { 0, true },
8578 : { 0, true },
8579 : { 0, true },
8580 : { 0, true },
8581 : { 0, true },
8582 : { 0, true },
8583 : { 0, true },
8584 : { 0, true },
8585 : { 0, true },
8586 : { 0, true },
8587 : { 0, true },
8588 : { 0, true },
8589 : { 0, true },
8590 : { 0, true },
8591 : { 0, true },
8592 : { 0, true },
8593 : { 0, true },
8594 : { 0, true },
8595 : { 0, true },
8596 : { 0, true },
8597 : { 0, true },
8598 : { 0, true },
8599 : { 0, true },
8600 : { 0, true },
8601 : { 0, true },
8602 : { 0, true },
8603 : { 0, true },
8604 : { 0, true },
8605 : { 0, true },
8606 : { 0, true },
8607 : { 0, true },
8608 : { 0, true },
8609 : { 0, true },
8610 : { 0, true },
8611 : { 0, true },
8612 : { 0, true },
8613 : { 0, true },
8614 : { 0, true },
8615 : { 0, true },
8616 : { 0, true },
8617 : { 0, true },
8618 : { 0, true },
8619 : { 0, true },
8620 : { 0, true },
8621 : { 0, true },
8622 : { 0, true },
8623 : { 0, true },
8624 : { 0, true },
8625 : { 0, true },
8626 : { 0, true },
8627 : { 0, true },
8628 : { 0, true },
8629 : { 0, true },
8630 : { 0, true },
8631 : { 0, true },
8632 : { 0, true },
8633 : { 0, true },
8634 : { 0, true },
8635 : { 0, true },
8636 : { 0, true },
8637 : { 0, true },
8638 : { 0, true },
8639 : { 0, true },
8640 : { 0, true },
8641 : { 0, true },
8642 : { 0, true },
8643 : { 0, true },
8644 : { 0, true },
8645 : { 0, true },
8646 : { 0, true },
8647 : { 0, true },
8648 : { 0, true },
8649 : { 0, true },
8650 : { 0, true },
8651 : { 0, true },
8652 : { 0, true },
8653 : { 0, true },
8654 : { 0, true },
8655 : { 0, true },
8656 : { 0, true },
8657 : { 0, true },
8658 : { 0, true },
8659 : { 0, true },
8660 : { 0, true },
8661 : { 0, true },
8662 : { 0, true },
8663 : { 0, true },
8664 : { 0, true },
8665 : { 0, true },
8666 : { 0, true },
8667 : { 0, true },
8668 : { 0, true },
8669 : { 0, true },
8670 : { 0, true },
8671 : { 0, true },
8672 : { 0, true },
8673 : { 0, true },
8674 : { 0, true },
8675 : { 0, true },
8676 : { 0, true },
8677 : { 0, true },
8678 : { 0, true },
8679 : { 0, true },
8680 : { 0, true },
8681 : { 0, true },
8682 : { 0, true },
8683 : { 0, true },
8684 : { 0, true },
8685 : { 0, true },
8686 : { 0, true },
8687 : { 0, true },
8688 : { 0, true },
8689 : { 0, true },
8690 : { 0, true },
8691 : { 0, true },
8692 : { 0, true },
8693 : { 0, true },
8694 : { 0, true },
8695 : { 0, true },
8696 : { 0, true },
8697 : { 0, true },
8698 : { 0, true },
8699 : { 0, true },
8700 : { 0, true },
8701 : { 0, true },
8702 : { 0, true },
8703 : { 0, true },
8704 : { 0, true },
8705 : { 0, true },
8706 : { 0, true },
8707 : { 0, true },
8708 : { 0, true },
8709 : { 0, true },
8710 : { 0, true },
8711 : { 0, true },
8712 : { 0, true },
8713 : { 0, true },
8714 : { 0, true },
8715 : { 0, true },
8716 : { 0, true },
8717 : { 0, true },
8718 : { 0, true },
8719 : { 0, true },
8720 : { 0, true },
8721 : { 0, true },
8722 : { 0, true },
8723 : { 0, true },
8724 : { 0, true },
8725 : { 0, true },
8726 : { 0, true },
8727 : { 0, true },
8728 : { 0, true },
8729 : { 0, true },
8730 : { 0, true },
8731 : { 0, true },
8732 : { 0, true },
8733 : { 0, true },
8734 : { 0, true },
8735 : { 0, true },
8736 : { 0, true },
8737 : { 0, true },
8738 : { 0, true },
8739 : { 0, true },
8740 : { 0, true },
8741 : { 0, true },
8742 : { 0, true },
8743 : { 0, true },
8744 : { 0, true },
8745 : { 0, true },
8746 : { 0, true },
8747 : { 0, true },
8748 : { 0, true },
8749 : { 0, true },
8750 : { 0, true },
8751 : { 0, true },
8752 : { 0, true },
8753 : { 0, true },
8754 : { 0, true },
8755 : { 0, true },
8756 : { 0, true },
8757 : { 0, true },
8758 : { 0, true },
8759 : { 0, true },
8760 : { 0, true },
8761 : { 0, true },
8762 : { 0, true },
8763 : { 0, true },
8764 : { 0, true },
8765 : { 0, true },
8766 : { 0, true },
8767 : { 0, true },
8768 : { 0, true },
8769 : { 0, true },
8770 : { 0, true },
8771 : { 0, true },
8772 : { 0, true },
8773 : { 0, true },
8774 : { 0, true },
8775 : { 0, true },
8776 : { 0, true },
8777 : { 0, true },
8778 : { 0, true },
8779 : { 0, true },
8780 : { 0, true },
8781 : { 0, true },
8782 : { 0, true },
8783 : { 0, true },
8784 : { 0, true },
8785 : { 0, true },
8786 : { 0, true },
8787 : { 0, true },
8788 : { 0, true },
8789 : { 0, true },
8790 : { 0, true },
8791 : { 0, true },
8792 : { 0, true },
8793 : { 0, true },
8794 : { 0, true },
8795 : { 0, true },
8796 : { 0, true },
8797 : { 0, true },
8798 : { 0, true },
8799 : { 0, true },
8800 : { 0, true },
8801 : { 0, true },
8802 : { 0, true },
8803 : { 0, true },
8804 : { 0, true },
8805 : { 0, true },
8806 : { 0, true },
8807 : { 0, true },
8808 : { 0, true },
8809 : { 0, true },
8810 : { 0, true },
8811 : { 0, true },
8812 : { 0, true },
8813 : { 0, true },
8814 : { 0, true },
8815 : { 0, true },
8816 : { 0, true },
8817 : { 0, true },
8818 : { 0, true },
8819 : { 0, true },
8820 : { 0, true },
8821 : { 0, true },
8822 : { 0, true },
8823 : { 0, true },
8824 : { 0, true },
8825 : { 0, true },
8826 : { 0, true },
8827 : { 0, true },
8828 : { 0, true },
8829 : { 0, true },
8830 : { 0, true },
8831 : { 0, true },
8832 : { 0, true },
8833 : { 0, true },
8834 : { 0, true },
8835 : { 0, true },
8836 : { 0, true },
8837 : { 0, true },
8838 : { 0, true },
8839 : { 0, true },
8840 : { 0, true },
8841 : { 0, true },
8842 : { 0, true },
8843 : { 0, true },
8844 : { 0, true },
8845 : };
8846 1126 : unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
8847 : static const uint8_t RowMap[99] = {
8848 : 0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 4, 5, 6, 0, 0, 0, 0, 0, 1, 0, 0, 7, 8, 9, 0, 0, 1, 1, 0, 3, 3, 0, 2, 2, 0, 4, 4, 4, 0, 6, 6, 6, 0, 5, 5, 5, 0, 0, 7, 7, 7, 7, 0, 0, 9, 9, 9, 9, 0, 0, 8, 8, 8, 8, 0, 0, 0, 1, 1, 2, 10, 10, 10, 0, 0, 4, 4, 5, 4, 4, 5, 0, 11, 10, 11, 11, 10, 10, 0, 0, 7, 7, 8, 7, 7, 7, 7, 8, 8,
8849 : };
8850 : static const uint8_t Rows[12][99] = {
8851 : { 1, 2, 3, 4, 5, 0, 7, 0, 0, 10, 11, 12, 0, 14, 15, 15, 0, 47, 0, 20, 21, 22, 23, 0, 25, 26, 27, 28, 0, 0, 0, 32, 33, 34, 35, 36, 37, 38, 0, 0, 0, 0, 43, 44, 45, 46, 0, 48, 49, 50, 51, 52, 53, 0, 0, 0, 0, 0, 0, 60, 61, 62, 63, 64, 65, 66, 0, 68, 0, 0, 71, 0, 73, 74, 0, 76, 0, 0, 79, 0, 0, 0, 83, 84, 0, 86, 0, 88, 89, 0, 91, 0, 0, 94, 0, 96, 0, 0, 0, },
8852 : { 26, 0, 4, 5, 6, 0, 27, 0, 0, 0, 0, 0, 0, 28, 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 33, 34, 0, 0, 0, 29, 30, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 68, 0, 70, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8853 : { 32, 0, 5, 6, 0, 0, 33, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8854 : { 29, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8855 : { 35, 36, 36, 44, 40, 0, 37, 0, 0, 11, 12, 13, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 45, 46, 0, 0, 0, 39, 41, 42, 43, 44, 45, 46, 0, 0, 0, 0, 39, 40, 41, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79, 0, 81, 0, 0, 79, 0, 80, 76, 0, 78, 0, 0, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8856 : { 43, 44, 44, 40, 0, 0, 45, 0, 0, 12, 13, 0, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 41, 42, 0, 0, 0, 0, 0, 0, 39, 40, 41, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8857 : { 39, 40, 0, 0, 0, 0, 41, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8858 : { 48, 49, 49, 61, 55, 0, 50, 0, 0, 52, 64, 58, 0, 51, 0, 0, 0, 0, 0, 52, 22, 23, 24, 0, 53, 60, 62, 63, 0, 0, 0, 54, 56, 57, 60, 61, 62, 63, 0, 0, 0, 0, 54, 55, 56, 57, 0, 60, 61, 62, 63, 64, 65, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 58, 59, 94, 0, 98, 0, 0, 94, 0, 95, 96, 0, 99, 0, 0, 98, 0, 0, 0, 94, 96, 0, 95, 0, 97, 91, 0, 93, 0, 0, 98, 0, 99, 0, 0, 0, },
8859 : { 60, 61, 61, 55, 0, 0, 62, 0, 0, 64, 58, 0, 0, 63, 0, 0, 0, 0, 0, 64, 23, 24, 0, 0, 65, 54, 56, 57, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 54, 55, 56, 57, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8860 : { 54, 55, 0, 0, 0, 0, 56, 0, 0, 0, 0, 0, 0, 57, 0, 0, 0, 0, 0, 58, 0, 0, 0, 0, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8861 : { 1, 2, 2, 36, 44, 40, 7, 0, 0, 20, 52, 64, 58, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35, 37, 38, 39, 41, 42, 43, 45, 46, 48, 49, 50, 51, 54, 55, 56, 57, 60, 61, 62, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 71, 73, 79, 80, 81, 83, 85, 86, 84, 88, 96, 97, 99, 94, 95, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8862 : { 1, 0, 2, 49, 61, 55, 7, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48, 50, 51, 54, 56, 57, 60, 62, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 83, 86, 94, 95, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8863 : };
8864 :
8865 1126 : --IdxA; assert(IdxA < 99);
8866 1126 : --IdxB; assert(IdxB < 99);
8867 1126 : return Rows[RowMap[IdxA]][IdxB];
8868 : }
8869 :
8870 : struct MaskRolOp {
8871 : LaneBitmask Mask;
8872 : uint8_t RotateLeft;
8873 : };
8874 : static const MaskRolOp LaneMaskComposeSequences[] = {
8875 : { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
8876 : { LaneBitmask(0xFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
8877 : { LaneBitmask(0xFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
8878 : { LaneBitmask(0xFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
8879 : { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
8880 : { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
8881 : { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 12
8882 : { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 14
8883 : { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 16
8884 : { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 18
8885 : { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 20
8886 : { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 22
8887 : { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 24
8888 : { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 27
8889 : { LaneBitmask(0x00000001), 16 }, { LaneBitmask(0x00000040), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 30
8890 : { LaneBitmask(0xFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 33
8891 : { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 35
8892 : { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 37
8893 : { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 39
8894 : { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 41
8895 : { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }, // Sequence 43
8896 : { LaneBitmask(0xFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 }, // Sequence 45
8897 : { LaneBitmask(0xFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 }, // Sequence 47
8898 : { LaneBitmask(0x00000001), 7 }, { LaneBitmask(0x00000080), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 49
8899 : { LaneBitmask(0x00000001), 7 }, { LaneBitmask(0x00000080), 2 }, { LaneBitmask(0x00000200), 31 }, { LaneBitmask::getNone(), 0 }, // Sequence 52
8900 : { LaneBitmask(0x00000001), 9 }, { LaneBitmask(0x00000080), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 56
8901 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000080), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 59
8902 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000380), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 62
8903 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000280), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 65
8904 : { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 68
8905 : { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400), 2 }, { LaneBitmask(0x00001000), 31 }, { LaneBitmask::getNone(), 0 }, // Sequence 71
8906 : { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000400), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 75
8907 : { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 78
8908 : { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080), 5 }, { LaneBitmask(0x00000200), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 81
8909 : { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000080), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 85
8910 : { LaneBitmask(0x00000010), 31 }, { LaneBitmask(0x00000020), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 88
8911 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000080), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 91
8912 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000400), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 94
8913 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000080), 7 }, { LaneBitmask(0x00000100), 8 }, { LaneBitmask(0x00000200), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 97
8914 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000080), 7 }, { LaneBitmask(0x00000200), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 102
8915 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000400), 4 }, { LaneBitmask(0x00000800), 5 }, { LaneBitmask(0x00001000), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 106
8916 : { LaneBitmask(0x00000001), 0 }, { LaneBitmask(0x00000400), 4 }, { LaneBitmask(0x00001000), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 111
8917 : { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040), 9 }, { LaneBitmask(0x0000C000), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 115
8918 : { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040), 9 }, { LaneBitmask(0x0000C000), 4 }, { LaneBitmask(0x000C0000), 30 }, { LaneBitmask::getNone(), 0 }, // Sequence 119
8919 : { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask(0x0000C000), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 124
8920 : { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 128
8921 : { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask(0x00000200), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 131
8922 : { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 135
8923 : { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400), 8 }, { LaneBitmask(0x00001000), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 138
8924 : { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000080), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 142
8925 : { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000400), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 145
8926 : };
8927 : static const MaskRolOp *const CompositeSequences[] = {
8928 : &LaneMaskComposeSequences[0], // to bsub
8929 : &LaneMaskComposeSequences[0], // to dsub
8930 : &LaneMaskComposeSequences[0], // to dsub0
8931 : &LaneMaskComposeSequences[2], // to dsub1
8932 : &LaneMaskComposeSequences[4], // to dsub2
8933 : &LaneMaskComposeSequences[6], // to dsub3
8934 : &LaneMaskComposeSequences[0], // to hsub
8935 : &LaneMaskComposeSequences[8], // to qhisub
8936 : &LaneMaskComposeSequences[10], // to qsub
8937 : &LaneMaskComposeSequences[0], // to qsub0
8938 : &LaneMaskComposeSequences[12], // to qsub1
8939 : &LaneMaskComposeSequences[14], // to qsub2
8940 : &LaneMaskComposeSequences[16], // to qsub3
8941 : &LaneMaskComposeSequences[0], // to ssub
8942 : &LaneMaskComposeSequences[18], // to sub_32
8943 : &LaneMaskComposeSequences[20], // to sube32
8944 : &LaneMaskComposeSequences[0], // to sube64
8945 : &LaneMaskComposeSequences[22], // to subo32
8946 : &LaneMaskComposeSequences[12], // to subo64
8947 : &LaneMaskComposeSequences[0], // to zsub
8948 : &LaneMaskComposeSequences[0], // to zsub0
8949 : &LaneMaskComposeSequences[24], // to zsub1
8950 : &LaneMaskComposeSequences[27], // to zsub2
8951 : &LaneMaskComposeSequences[30], // to zsub3
8952 : &LaneMaskComposeSequences[33], // to zsub_hi
8953 : &LaneMaskComposeSequences[2], // to dsub1_then_bsub
8954 : &LaneMaskComposeSequences[2], // to dsub1_then_hsub
8955 : &LaneMaskComposeSequences[2], // to dsub1_then_ssub
8956 : &LaneMaskComposeSequences[6], // to dsub3_then_bsub
8957 : &LaneMaskComposeSequences[6], // to dsub3_then_hsub
8958 : &LaneMaskComposeSequences[6], // to dsub3_then_ssub
8959 : &LaneMaskComposeSequences[4], // to dsub2_then_bsub
8960 : &LaneMaskComposeSequences[4], // to dsub2_then_hsub
8961 : &LaneMaskComposeSequences[4], // to dsub2_then_ssub
8962 : &LaneMaskComposeSequences[12], // to qsub1_then_bsub
8963 : &LaneMaskComposeSequences[12], // to qsub1_then_dsub
8964 : &LaneMaskComposeSequences[12], // to qsub1_then_hsub
8965 : &LaneMaskComposeSequences[12], // to qsub1_then_ssub
8966 : &LaneMaskComposeSequences[16], // to qsub3_then_bsub
8967 : &LaneMaskComposeSequences[16], // to qsub3_then_dsub
8968 : &LaneMaskComposeSequences[16], // to qsub3_then_hsub
8969 : &LaneMaskComposeSequences[16], // to qsub3_then_ssub
8970 : &LaneMaskComposeSequences[14], // to qsub2_then_bsub
8971 : &LaneMaskComposeSequences[14], // to qsub2_then_dsub
8972 : &LaneMaskComposeSequences[14], // to qsub2_then_hsub
8973 : &LaneMaskComposeSequences[14], // to qsub2_then_ssub
8974 : &LaneMaskComposeSequences[35], // to subo64_then_sub_32
8975 : &LaneMaskComposeSequences[37], // to zsub1_then_bsub
8976 : &LaneMaskComposeSequences[37], // to zsub1_then_dsub
8977 : &LaneMaskComposeSequences[37], // to zsub1_then_hsub
8978 : &LaneMaskComposeSequences[37], // to zsub1_then_ssub
8979 : &LaneMaskComposeSequences[37], // to zsub1_then_zsub
8980 : &LaneMaskComposeSequences[39], // to zsub1_then_zsub_hi
8981 : &LaneMaskComposeSequences[41], // to zsub3_then_bsub
8982 : &LaneMaskComposeSequences[41], // to zsub3_then_dsub
8983 : &LaneMaskComposeSequences[41], // to zsub3_then_hsub
8984 : &LaneMaskComposeSequences[41], // to zsub3_then_ssub
8985 : &LaneMaskComposeSequences[41], // to zsub3_then_zsub
8986 : &LaneMaskComposeSequences[43], // to zsub3_then_zsub_hi
8987 : &LaneMaskComposeSequences[45], // to zsub2_then_bsub
8988 : &LaneMaskComposeSequences[45], // to zsub2_then_dsub
8989 : &LaneMaskComposeSequences[45], // to zsub2_then_hsub
8990 : &LaneMaskComposeSequences[45], // to zsub2_then_ssub
8991 : &LaneMaskComposeSequences[45], // to zsub2_then_zsub
8992 : &LaneMaskComposeSequences[47], // to zsub2_then_zsub_hi
8993 : &LaneMaskComposeSequences[0], // to dsub0_dsub1
8994 : &LaneMaskComposeSequences[0], // to dsub0_dsub1_dsub2
8995 : &LaneMaskComposeSequences[49], // to dsub1_dsub2
8996 : &LaneMaskComposeSequences[52], // to dsub1_dsub2_dsub3
8997 : &LaneMaskComposeSequences[56], // to dsub2_dsub3
8998 : &LaneMaskComposeSequences[59], // to dsub_qsub1_then_dsub
8999 : &LaneMaskComposeSequences[62], // to dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9000 : &LaneMaskComposeSequences[65], // to dsub_qsub1_then_dsub_qsub2_then_dsub
9001 : &LaneMaskComposeSequences[0], // to qsub0_qsub1
9002 : &LaneMaskComposeSequences[0], // to qsub0_qsub1_qsub2
9003 : &LaneMaskComposeSequences[68], // to qsub1_qsub2
9004 : &LaneMaskComposeSequences[71], // to qsub1_qsub2_qsub3
9005 : &LaneMaskComposeSequences[75], // to qsub2_qsub3
9006 : &LaneMaskComposeSequences[78], // to qsub1_then_dsub_qsub2_then_dsub
9007 : &LaneMaskComposeSequences[81], // to qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9008 : &LaneMaskComposeSequences[85], // to qsub2_then_dsub_qsub3_then_dsub
9009 : &LaneMaskComposeSequences[88], // to sub_32_subo64_then_sub_32
9010 : &LaneMaskComposeSequences[91], // to dsub_zsub1_then_dsub
9011 : &LaneMaskComposeSequences[94], // to zsub_zsub1_then_zsub
9012 : &LaneMaskComposeSequences[97], // to dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9013 : &LaneMaskComposeSequences[102], // to dsub_zsub1_then_dsub_zsub2_then_dsub
9014 : &LaneMaskComposeSequences[106], // to zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9015 : &LaneMaskComposeSequences[111], // to zsub_zsub1_then_zsub_zsub2_then_zsub
9016 : &LaneMaskComposeSequences[0], // to zsub0_zsub1
9017 : &LaneMaskComposeSequences[0], // to zsub0_zsub1_zsub2
9018 : &LaneMaskComposeSequences[115], // to zsub1_zsub2
9019 : &LaneMaskComposeSequences[119], // to zsub1_zsub2_zsub3
9020 : &LaneMaskComposeSequences[124], // to zsub2_zsub3
9021 : &LaneMaskComposeSequences[128], // to zsub1_then_dsub_zsub2_then_dsub
9022 : &LaneMaskComposeSequences[131], // to zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9023 : &LaneMaskComposeSequences[135], // to zsub1_then_zsub_zsub2_then_zsub
9024 : &LaneMaskComposeSequences[138], // to zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9025 : &LaneMaskComposeSequences[142], // to zsub2_then_dsub_zsub3_then_dsub
9026 : &LaneMaskComposeSequences[145] // to zsub2_then_zsub_zsub3_then_zsub
9027 : };
9028 :
9029 0 : LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9030 0 : --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
9031 : LaneBitmask Result;
9032 0 : for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
9033 0 : LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
9034 0 : if (unsigned S = Ops->RotateLeft)
9035 0 : Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
9036 : else
9037 : Result |= LaneBitmask(M);
9038 : }
9039 0 : return Result;
9040 : }
9041 :
9042 0 : LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9043 0 : LaneMask &= getSubRegIndexLaneMask(IdxA);
9044 0 : --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
9045 : LaneBitmask Result;
9046 0 : for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
9047 : LaneBitmask::Type M = LaneMask.getAsInteger();
9048 0 : if (unsigned S = Ops->RotateLeft)
9049 0 : Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
9050 : else
9051 : Result |= LaneBitmask(M);
9052 : }
9053 0 : return Result;
9054 : }
9055 :
9056 33886 : const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
9057 : static const uint8_t Table[104][99] = {
9058 : { // FPR8
9059 : 0, // bsub
9060 : 0, // dsub
9061 : 0, // dsub0
9062 : 0, // dsub1
9063 : 0, // dsub2
9064 : 0, // dsub3
9065 : 0, // hsub
9066 : 0, // qhisub
9067 : 0, // qsub
9068 : 0, // qsub0
9069 : 0, // qsub1
9070 : 0, // qsub2
9071 : 0, // qsub3
9072 : 0, // ssub
9073 : 0, // sub_32
9074 : 0, // sube32
9075 : 0, // sube64
9076 : 0, // subo32
9077 : 0, // subo64
9078 : 0, // zsub
9079 : 0, // zsub0
9080 : 0, // zsub1
9081 : 0, // zsub2
9082 : 0, // zsub3
9083 : 0, // zsub_hi
9084 : 0, // dsub1_then_bsub
9085 : 0, // dsub1_then_hsub
9086 : 0, // dsub1_then_ssub
9087 : 0, // dsub3_then_bsub
9088 : 0, // dsub3_then_hsub
9089 : 0, // dsub3_then_ssub
9090 : 0, // dsub2_then_bsub
9091 : 0, // dsub2_then_hsub
9092 : 0, // dsub2_then_ssub
9093 : 0, // qsub1_then_bsub
9094 : 0, // qsub1_then_dsub
9095 : 0, // qsub1_then_hsub
9096 : 0, // qsub1_then_ssub
9097 : 0, // qsub3_then_bsub
9098 : 0, // qsub3_then_dsub
9099 : 0, // qsub3_then_hsub
9100 : 0, // qsub3_then_ssub
9101 : 0, // qsub2_then_bsub
9102 : 0, // qsub2_then_dsub
9103 : 0, // qsub2_then_hsub
9104 : 0, // qsub2_then_ssub
9105 : 0, // subo64_then_sub_32
9106 : 0, // zsub1_then_bsub
9107 : 0, // zsub1_then_dsub
9108 : 0, // zsub1_then_hsub
9109 : 0, // zsub1_then_ssub
9110 : 0, // zsub1_then_zsub
9111 : 0, // zsub1_then_zsub_hi
9112 : 0, // zsub3_then_bsub
9113 : 0, // zsub3_then_dsub
9114 : 0, // zsub3_then_hsub
9115 : 0, // zsub3_then_ssub
9116 : 0, // zsub3_then_zsub
9117 : 0, // zsub3_then_zsub_hi
9118 : 0, // zsub2_then_bsub
9119 : 0, // zsub2_then_dsub
9120 : 0, // zsub2_then_hsub
9121 : 0, // zsub2_then_ssub
9122 : 0, // zsub2_then_zsub
9123 : 0, // zsub2_then_zsub_hi
9124 : 0, // dsub0_dsub1
9125 : 0, // dsub0_dsub1_dsub2
9126 : 0, // dsub1_dsub2
9127 : 0, // dsub1_dsub2_dsub3
9128 : 0, // dsub2_dsub3
9129 : 0, // dsub_qsub1_then_dsub
9130 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9131 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9132 : 0, // qsub0_qsub1
9133 : 0, // qsub0_qsub1_qsub2
9134 : 0, // qsub1_qsub2
9135 : 0, // qsub1_qsub2_qsub3
9136 : 0, // qsub2_qsub3
9137 : 0, // qsub1_then_dsub_qsub2_then_dsub
9138 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9139 : 0, // qsub2_then_dsub_qsub3_then_dsub
9140 : 0, // sub_32_subo64_then_sub_32
9141 : 0, // dsub_zsub1_then_dsub
9142 : 0, // zsub_zsub1_then_zsub
9143 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9144 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9145 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9146 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9147 : 0, // zsub0_zsub1
9148 : 0, // zsub0_zsub1_zsub2
9149 : 0, // zsub1_zsub2
9150 : 0, // zsub1_zsub2_zsub3
9151 : 0, // zsub2_zsub3
9152 : 0, // zsub1_then_dsub_zsub2_then_dsub
9153 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9154 : 0, // zsub1_then_zsub_zsub2_then_zsub
9155 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9156 : 0, // zsub2_then_dsub_zsub3_then_dsub
9157 : 0, // zsub2_then_zsub_zsub3_then_zsub
9158 : },
9159 : { // FPR16
9160 : 2, // bsub -> FPR16
9161 : 0, // dsub
9162 : 0, // dsub0
9163 : 0, // dsub1
9164 : 0, // dsub2
9165 : 0, // dsub3
9166 : 0, // hsub
9167 : 0, // qhisub
9168 : 0, // qsub
9169 : 0, // qsub0
9170 : 0, // qsub1
9171 : 0, // qsub2
9172 : 0, // qsub3
9173 : 0, // ssub
9174 : 0, // sub_32
9175 : 0, // sube32
9176 : 0, // sube64
9177 : 0, // subo32
9178 : 0, // subo64
9179 : 0, // zsub
9180 : 0, // zsub0
9181 : 0, // zsub1
9182 : 0, // zsub2
9183 : 0, // zsub3
9184 : 0, // zsub_hi
9185 : 0, // dsub1_then_bsub
9186 : 0, // dsub1_then_hsub
9187 : 0, // dsub1_then_ssub
9188 : 0, // dsub3_then_bsub
9189 : 0, // dsub3_then_hsub
9190 : 0, // dsub3_then_ssub
9191 : 0, // dsub2_then_bsub
9192 : 0, // dsub2_then_hsub
9193 : 0, // dsub2_then_ssub
9194 : 0, // qsub1_then_bsub
9195 : 0, // qsub1_then_dsub
9196 : 0, // qsub1_then_hsub
9197 : 0, // qsub1_then_ssub
9198 : 0, // qsub3_then_bsub
9199 : 0, // qsub3_then_dsub
9200 : 0, // qsub3_then_hsub
9201 : 0, // qsub3_then_ssub
9202 : 0, // qsub2_then_bsub
9203 : 0, // qsub2_then_dsub
9204 : 0, // qsub2_then_hsub
9205 : 0, // qsub2_then_ssub
9206 : 0, // subo64_then_sub_32
9207 : 0, // zsub1_then_bsub
9208 : 0, // zsub1_then_dsub
9209 : 0, // zsub1_then_hsub
9210 : 0, // zsub1_then_ssub
9211 : 0, // zsub1_then_zsub
9212 : 0, // zsub1_then_zsub_hi
9213 : 0, // zsub3_then_bsub
9214 : 0, // zsub3_then_dsub
9215 : 0, // zsub3_then_hsub
9216 : 0, // zsub3_then_ssub
9217 : 0, // zsub3_then_zsub
9218 : 0, // zsub3_then_zsub_hi
9219 : 0, // zsub2_then_bsub
9220 : 0, // zsub2_then_dsub
9221 : 0, // zsub2_then_hsub
9222 : 0, // zsub2_then_ssub
9223 : 0, // zsub2_then_zsub
9224 : 0, // zsub2_then_zsub_hi
9225 : 0, // dsub0_dsub1
9226 : 0, // dsub0_dsub1_dsub2
9227 : 0, // dsub1_dsub2
9228 : 0, // dsub1_dsub2_dsub3
9229 : 0, // dsub2_dsub3
9230 : 0, // dsub_qsub1_then_dsub
9231 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9232 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9233 : 0, // qsub0_qsub1
9234 : 0, // qsub0_qsub1_qsub2
9235 : 0, // qsub1_qsub2
9236 : 0, // qsub1_qsub2_qsub3
9237 : 0, // qsub2_qsub3
9238 : 0, // qsub1_then_dsub_qsub2_then_dsub
9239 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9240 : 0, // qsub2_then_dsub_qsub3_then_dsub
9241 : 0, // sub_32_subo64_then_sub_32
9242 : 0, // dsub_zsub1_then_dsub
9243 : 0, // zsub_zsub1_then_zsub
9244 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9245 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9246 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9247 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9248 : 0, // zsub0_zsub1
9249 : 0, // zsub0_zsub1_zsub2
9250 : 0, // zsub1_zsub2
9251 : 0, // zsub1_zsub2_zsub3
9252 : 0, // zsub2_zsub3
9253 : 0, // zsub1_then_dsub_zsub2_then_dsub
9254 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9255 : 0, // zsub1_then_zsub_zsub2_then_zsub
9256 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9257 : 0, // zsub2_then_dsub_zsub3_then_dsub
9258 : 0, // zsub2_then_zsub_zsub3_then_zsub
9259 : },
9260 : { // PPR
9261 : 0, // bsub
9262 : 0, // dsub
9263 : 0, // dsub0
9264 : 0, // dsub1
9265 : 0, // dsub2
9266 : 0, // dsub3
9267 : 0, // hsub
9268 : 0, // qhisub
9269 : 0, // qsub
9270 : 0, // qsub0
9271 : 0, // qsub1
9272 : 0, // qsub2
9273 : 0, // qsub3
9274 : 0, // ssub
9275 : 0, // sub_32
9276 : 0, // sube32
9277 : 0, // sube64
9278 : 0, // subo32
9279 : 0, // subo64
9280 : 0, // zsub
9281 : 0, // zsub0
9282 : 0, // zsub1
9283 : 0, // zsub2
9284 : 0, // zsub3
9285 : 0, // zsub_hi
9286 : 0, // dsub1_then_bsub
9287 : 0, // dsub1_then_hsub
9288 : 0, // dsub1_then_ssub
9289 : 0, // dsub3_then_bsub
9290 : 0, // dsub3_then_hsub
9291 : 0, // dsub3_then_ssub
9292 : 0, // dsub2_then_bsub
9293 : 0, // dsub2_then_hsub
9294 : 0, // dsub2_then_ssub
9295 : 0, // qsub1_then_bsub
9296 : 0, // qsub1_then_dsub
9297 : 0, // qsub1_then_hsub
9298 : 0, // qsub1_then_ssub
9299 : 0, // qsub3_then_bsub
9300 : 0, // qsub3_then_dsub
9301 : 0, // qsub3_then_hsub
9302 : 0, // qsub3_then_ssub
9303 : 0, // qsub2_then_bsub
9304 : 0, // qsub2_then_dsub
9305 : 0, // qsub2_then_hsub
9306 : 0, // qsub2_then_ssub
9307 : 0, // subo64_then_sub_32
9308 : 0, // zsub1_then_bsub
9309 : 0, // zsub1_then_dsub
9310 : 0, // zsub1_then_hsub
9311 : 0, // zsub1_then_ssub
9312 : 0, // zsub1_then_zsub
9313 : 0, // zsub1_then_zsub_hi
9314 : 0, // zsub3_then_bsub
9315 : 0, // zsub3_then_dsub
9316 : 0, // zsub3_then_hsub
9317 : 0, // zsub3_then_ssub
9318 : 0, // zsub3_then_zsub
9319 : 0, // zsub3_then_zsub_hi
9320 : 0, // zsub2_then_bsub
9321 : 0, // zsub2_then_dsub
9322 : 0, // zsub2_then_hsub
9323 : 0, // zsub2_then_ssub
9324 : 0, // zsub2_then_zsub
9325 : 0, // zsub2_then_zsub_hi
9326 : 0, // dsub0_dsub1
9327 : 0, // dsub0_dsub1_dsub2
9328 : 0, // dsub1_dsub2
9329 : 0, // dsub1_dsub2_dsub3
9330 : 0, // dsub2_dsub3
9331 : 0, // dsub_qsub1_then_dsub
9332 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9333 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9334 : 0, // qsub0_qsub1
9335 : 0, // qsub0_qsub1_qsub2
9336 : 0, // qsub1_qsub2
9337 : 0, // qsub1_qsub2_qsub3
9338 : 0, // qsub2_qsub3
9339 : 0, // qsub1_then_dsub_qsub2_then_dsub
9340 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9341 : 0, // qsub2_then_dsub_qsub3_then_dsub
9342 : 0, // sub_32_subo64_then_sub_32
9343 : 0, // dsub_zsub1_then_dsub
9344 : 0, // zsub_zsub1_then_zsub
9345 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9346 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9347 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9348 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9349 : 0, // zsub0_zsub1
9350 : 0, // zsub0_zsub1_zsub2
9351 : 0, // zsub1_zsub2
9352 : 0, // zsub1_zsub2_zsub3
9353 : 0, // zsub2_zsub3
9354 : 0, // zsub1_then_dsub_zsub2_then_dsub
9355 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9356 : 0, // zsub1_then_zsub_zsub2_then_zsub
9357 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9358 : 0, // zsub2_then_dsub_zsub3_then_dsub
9359 : 0, // zsub2_then_zsub_zsub3_then_zsub
9360 : },
9361 : { // PPR_3b
9362 : 0, // bsub
9363 : 0, // dsub
9364 : 0, // dsub0
9365 : 0, // dsub1
9366 : 0, // dsub2
9367 : 0, // dsub3
9368 : 0, // hsub
9369 : 0, // qhisub
9370 : 0, // qsub
9371 : 0, // qsub0
9372 : 0, // qsub1
9373 : 0, // qsub2
9374 : 0, // qsub3
9375 : 0, // ssub
9376 : 0, // sub_32
9377 : 0, // sube32
9378 : 0, // sube64
9379 : 0, // subo32
9380 : 0, // subo64
9381 : 0, // zsub
9382 : 0, // zsub0
9383 : 0, // zsub1
9384 : 0, // zsub2
9385 : 0, // zsub3
9386 : 0, // zsub_hi
9387 : 0, // dsub1_then_bsub
9388 : 0, // dsub1_then_hsub
9389 : 0, // dsub1_then_ssub
9390 : 0, // dsub3_then_bsub
9391 : 0, // dsub3_then_hsub
9392 : 0, // dsub3_then_ssub
9393 : 0, // dsub2_then_bsub
9394 : 0, // dsub2_then_hsub
9395 : 0, // dsub2_then_ssub
9396 : 0, // qsub1_then_bsub
9397 : 0, // qsub1_then_dsub
9398 : 0, // qsub1_then_hsub
9399 : 0, // qsub1_then_ssub
9400 : 0, // qsub3_then_bsub
9401 : 0, // qsub3_then_dsub
9402 : 0, // qsub3_then_hsub
9403 : 0, // qsub3_then_ssub
9404 : 0, // qsub2_then_bsub
9405 : 0, // qsub2_then_dsub
9406 : 0, // qsub2_then_hsub
9407 : 0, // qsub2_then_ssub
9408 : 0, // subo64_then_sub_32
9409 : 0, // zsub1_then_bsub
9410 : 0, // zsub1_then_dsub
9411 : 0, // zsub1_then_hsub
9412 : 0, // zsub1_then_ssub
9413 : 0, // zsub1_then_zsub
9414 : 0, // zsub1_then_zsub_hi
9415 : 0, // zsub3_then_bsub
9416 : 0, // zsub3_then_dsub
9417 : 0, // zsub3_then_hsub
9418 : 0, // zsub3_then_ssub
9419 : 0, // zsub3_then_zsub
9420 : 0, // zsub3_then_zsub_hi
9421 : 0, // zsub2_then_bsub
9422 : 0, // zsub2_then_dsub
9423 : 0, // zsub2_then_hsub
9424 : 0, // zsub2_then_ssub
9425 : 0, // zsub2_then_zsub
9426 : 0, // zsub2_then_zsub_hi
9427 : 0, // dsub0_dsub1
9428 : 0, // dsub0_dsub1_dsub2
9429 : 0, // dsub1_dsub2
9430 : 0, // dsub1_dsub2_dsub3
9431 : 0, // dsub2_dsub3
9432 : 0, // dsub_qsub1_then_dsub
9433 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9434 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9435 : 0, // qsub0_qsub1
9436 : 0, // qsub0_qsub1_qsub2
9437 : 0, // qsub1_qsub2
9438 : 0, // qsub1_qsub2_qsub3
9439 : 0, // qsub2_qsub3
9440 : 0, // qsub1_then_dsub_qsub2_then_dsub
9441 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9442 : 0, // qsub2_then_dsub_qsub3_then_dsub
9443 : 0, // sub_32_subo64_then_sub_32
9444 : 0, // dsub_zsub1_then_dsub
9445 : 0, // zsub_zsub1_then_zsub
9446 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9447 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9448 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9449 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9450 : 0, // zsub0_zsub1
9451 : 0, // zsub0_zsub1_zsub2
9452 : 0, // zsub1_zsub2
9453 : 0, // zsub1_zsub2_zsub3
9454 : 0, // zsub2_zsub3
9455 : 0, // zsub1_then_dsub_zsub2_then_dsub
9456 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9457 : 0, // zsub1_then_zsub_zsub2_then_zsub
9458 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9459 : 0, // zsub2_then_dsub_zsub3_then_dsub
9460 : 0, // zsub2_then_zsub_zsub3_then_zsub
9461 : },
9462 : { // GPR32all
9463 : 0, // bsub
9464 : 0, // dsub
9465 : 0, // dsub0
9466 : 0, // dsub1
9467 : 0, // dsub2
9468 : 0, // dsub3
9469 : 0, // hsub
9470 : 0, // qhisub
9471 : 0, // qsub
9472 : 0, // qsub0
9473 : 0, // qsub1
9474 : 0, // qsub2
9475 : 0, // qsub3
9476 : 0, // ssub
9477 : 0, // sub_32
9478 : 0, // sube32
9479 : 0, // sube64
9480 : 0, // subo32
9481 : 0, // subo64
9482 : 0, // zsub
9483 : 0, // zsub0
9484 : 0, // zsub1
9485 : 0, // zsub2
9486 : 0, // zsub3
9487 : 0, // zsub_hi
9488 : 0, // dsub1_then_bsub
9489 : 0, // dsub1_then_hsub
9490 : 0, // dsub1_then_ssub
9491 : 0, // dsub3_then_bsub
9492 : 0, // dsub3_then_hsub
9493 : 0, // dsub3_then_ssub
9494 : 0, // dsub2_then_bsub
9495 : 0, // dsub2_then_hsub
9496 : 0, // dsub2_then_ssub
9497 : 0, // qsub1_then_bsub
9498 : 0, // qsub1_then_dsub
9499 : 0, // qsub1_then_hsub
9500 : 0, // qsub1_then_ssub
9501 : 0, // qsub3_then_bsub
9502 : 0, // qsub3_then_dsub
9503 : 0, // qsub3_then_hsub
9504 : 0, // qsub3_then_ssub
9505 : 0, // qsub2_then_bsub
9506 : 0, // qsub2_then_dsub
9507 : 0, // qsub2_then_hsub
9508 : 0, // qsub2_then_ssub
9509 : 0, // subo64_then_sub_32
9510 : 0, // zsub1_then_bsub
9511 : 0, // zsub1_then_dsub
9512 : 0, // zsub1_then_hsub
9513 : 0, // zsub1_then_ssub
9514 : 0, // zsub1_then_zsub
9515 : 0, // zsub1_then_zsub_hi
9516 : 0, // zsub3_then_bsub
9517 : 0, // zsub3_then_dsub
9518 : 0, // zsub3_then_hsub
9519 : 0, // zsub3_then_ssub
9520 : 0, // zsub3_then_zsub
9521 : 0, // zsub3_then_zsub_hi
9522 : 0, // zsub2_then_bsub
9523 : 0, // zsub2_then_dsub
9524 : 0, // zsub2_then_hsub
9525 : 0, // zsub2_then_ssub
9526 : 0, // zsub2_then_zsub
9527 : 0, // zsub2_then_zsub_hi
9528 : 0, // dsub0_dsub1
9529 : 0, // dsub0_dsub1_dsub2
9530 : 0, // dsub1_dsub2
9531 : 0, // dsub1_dsub2_dsub3
9532 : 0, // dsub2_dsub3
9533 : 0, // dsub_qsub1_then_dsub
9534 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9535 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9536 : 0, // qsub0_qsub1
9537 : 0, // qsub0_qsub1_qsub2
9538 : 0, // qsub1_qsub2
9539 : 0, // qsub1_qsub2_qsub3
9540 : 0, // qsub2_qsub3
9541 : 0, // qsub1_then_dsub_qsub2_then_dsub
9542 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9543 : 0, // qsub2_then_dsub_qsub3_then_dsub
9544 : 0, // sub_32_subo64_then_sub_32
9545 : 0, // dsub_zsub1_then_dsub
9546 : 0, // zsub_zsub1_then_zsub
9547 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9548 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9549 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9550 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9551 : 0, // zsub0_zsub1
9552 : 0, // zsub0_zsub1_zsub2
9553 : 0, // zsub1_zsub2
9554 : 0, // zsub1_zsub2_zsub3
9555 : 0, // zsub2_zsub3
9556 : 0, // zsub1_then_dsub_zsub2_then_dsub
9557 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9558 : 0, // zsub1_then_zsub_zsub2_then_zsub
9559 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9560 : 0, // zsub2_then_dsub_zsub3_then_dsub
9561 : 0, // zsub2_then_zsub_zsub3_then_zsub
9562 : },
9563 : { // FPR32
9564 : 6, // bsub -> FPR32
9565 : 0, // dsub
9566 : 0, // dsub0
9567 : 0, // dsub1
9568 : 0, // dsub2
9569 : 0, // dsub3
9570 : 6, // hsub -> FPR32
9571 : 0, // qhisub
9572 : 0, // qsub
9573 : 0, // qsub0
9574 : 0, // qsub1
9575 : 0, // qsub2
9576 : 0, // qsub3
9577 : 0, // ssub
9578 : 0, // sub_32
9579 : 0, // sube32
9580 : 0, // sube64
9581 : 0, // subo32
9582 : 0, // subo64
9583 : 0, // zsub
9584 : 0, // zsub0
9585 : 0, // zsub1
9586 : 0, // zsub2
9587 : 0, // zsub3
9588 : 0, // zsub_hi
9589 : 0, // dsub1_then_bsub
9590 : 0, // dsub1_then_hsub
9591 : 0, // dsub1_then_ssub
9592 : 0, // dsub3_then_bsub
9593 : 0, // dsub3_then_hsub
9594 : 0, // dsub3_then_ssub
9595 : 0, // dsub2_then_bsub
9596 : 0, // dsub2_then_hsub
9597 : 0, // dsub2_then_ssub
9598 : 0, // qsub1_then_bsub
9599 : 0, // qsub1_then_dsub
9600 : 0, // qsub1_then_hsub
9601 : 0, // qsub1_then_ssub
9602 : 0, // qsub3_then_bsub
9603 : 0, // qsub3_then_dsub
9604 : 0, // qsub3_then_hsub
9605 : 0, // qsub3_then_ssub
9606 : 0, // qsub2_then_bsub
9607 : 0, // qsub2_then_dsub
9608 : 0, // qsub2_then_hsub
9609 : 0, // qsub2_then_ssub
9610 : 0, // subo64_then_sub_32
9611 : 0, // zsub1_then_bsub
9612 : 0, // zsub1_then_dsub
9613 : 0, // zsub1_then_hsub
9614 : 0, // zsub1_then_ssub
9615 : 0, // zsub1_then_zsub
9616 : 0, // zsub1_then_zsub_hi
9617 : 0, // zsub3_then_bsub
9618 : 0, // zsub3_then_dsub
9619 : 0, // zsub3_then_hsub
9620 : 0, // zsub3_then_ssub
9621 : 0, // zsub3_then_zsub
9622 : 0, // zsub3_then_zsub_hi
9623 : 0, // zsub2_then_bsub
9624 : 0, // zsub2_then_dsub
9625 : 0, // zsub2_then_hsub
9626 : 0, // zsub2_then_ssub
9627 : 0, // zsub2_then_zsub
9628 : 0, // zsub2_then_zsub_hi
9629 : 0, // dsub0_dsub1
9630 : 0, // dsub0_dsub1_dsub2
9631 : 0, // dsub1_dsub2
9632 : 0, // dsub1_dsub2_dsub3
9633 : 0, // dsub2_dsub3
9634 : 0, // dsub_qsub1_then_dsub
9635 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9636 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9637 : 0, // qsub0_qsub1
9638 : 0, // qsub0_qsub1_qsub2
9639 : 0, // qsub1_qsub2
9640 : 0, // qsub1_qsub2_qsub3
9641 : 0, // qsub2_qsub3
9642 : 0, // qsub1_then_dsub_qsub2_then_dsub
9643 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9644 : 0, // qsub2_then_dsub_qsub3_then_dsub
9645 : 0, // sub_32_subo64_then_sub_32
9646 : 0, // dsub_zsub1_then_dsub
9647 : 0, // zsub_zsub1_then_zsub
9648 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9649 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9650 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9651 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9652 : 0, // zsub0_zsub1
9653 : 0, // zsub0_zsub1_zsub2
9654 : 0, // zsub1_zsub2
9655 : 0, // zsub1_zsub2_zsub3
9656 : 0, // zsub2_zsub3
9657 : 0, // zsub1_then_dsub_zsub2_then_dsub
9658 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9659 : 0, // zsub1_then_zsub_zsub2_then_zsub
9660 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9661 : 0, // zsub2_then_dsub_zsub3_then_dsub
9662 : 0, // zsub2_then_zsub_zsub3_then_zsub
9663 : },
9664 : { // GPR32
9665 : 0, // bsub
9666 : 0, // dsub
9667 : 0, // dsub0
9668 : 0, // dsub1
9669 : 0, // dsub2
9670 : 0, // dsub3
9671 : 0, // hsub
9672 : 0, // qhisub
9673 : 0, // qsub
9674 : 0, // qsub0
9675 : 0, // qsub1
9676 : 0, // qsub2
9677 : 0, // qsub3
9678 : 0, // ssub
9679 : 0, // sub_32
9680 : 0, // sube32
9681 : 0, // sube64
9682 : 0, // subo32
9683 : 0, // subo64
9684 : 0, // zsub
9685 : 0, // zsub0
9686 : 0, // zsub1
9687 : 0, // zsub2
9688 : 0, // zsub3
9689 : 0, // zsub_hi
9690 : 0, // dsub1_then_bsub
9691 : 0, // dsub1_then_hsub
9692 : 0, // dsub1_then_ssub
9693 : 0, // dsub3_then_bsub
9694 : 0, // dsub3_then_hsub
9695 : 0, // dsub3_then_ssub
9696 : 0, // dsub2_then_bsub
9697 : 0, // dsub2_then_hsub
9698 : 0, // dsub2_then_ssub
9699 : 0, // qsub1_then_bsub
9700 : 0, // qsub1_then_dsub
9701 : 0, // qsub1_then_hsub
9702 : 0, // qsub1_then_ssub
9703 : 0, // qsub3_then_bsub
9704 : 0, // qsub3_then_dsub
9705 : 0, // qsub3_then_hsub
9706 : 0, // qsub3_then_ssub
9707 : 0, // qsub2_then_bsub
9708 : 0, // qsub2_then_dsub
9709 : 0, // qsub2_then_hsub
9710 : 0, // qsub2_then_ssub
9711 : 0, // subo64_then_sub_32
9712 : 0, // zsub1_then_bsub
9713 : 0, // zsub1_then_dsub
9714 : 0, // zsub1_then_hsub
9715 : 0, // zsub1_then_ssub
9716 : 0, // zsub1_then_zsub
9717 : 0, // zsub1_then_zsub_hi
9718 : 0, // zsub3_then_bsub
9719 : 0, // zsub3_then_dsub
9720 : 0, // zsub3_then_hsub
9721 : 0, // zsub3_then_ssub
9722 : 0, // zsub3_then_zsub
9723 : 0, // zsub3_then_zsub_hi
9724 : 0, // zsub2_then_bsub
9725 : 0, // zsub2_then_dsub
9726 : 0, // zsub2_then_hsub
9727 : 0, // zsub2_then_ssub
9728 : 0, // zsub2_then_zsub
9729 : 0, // zsub2_then_zsub_hi
9730 : 0, // dsub0_dsub1
9731 : 0, // dsub0_dsub1_dsub2
9732 : 0, // dsub1_dsub2
9733 : 0, // dsub1_dsub2_dsub3
9734 : 0, // dsub2_dsub3
9735 : 0, // dsub_qsub1_then_dsub
9736 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9737 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9738 : 0, // qsub0_qsub1
9739 : 0, // qsub0_qsub1_qsub2
9740 : 0, // qsub1_qsub2
9741 : 0, // qsub1_qsub2_qsub3
9742 : 0, // qsub2_qsub3
9743 : 0, // qsub1_then_dsub_qsub2_then_dsub
9744 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9745 : 0, // qsub2_then_dsub_qsub3_then_dsub
9746 : 0, // sub_32_subo64_then_sub_32
9747 : 0, // dsub_zsub1_then_dsub
9748 : 0, // zsub_zsub1_then_zsub
9749 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9750 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9751 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9752 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9753 : 0, // zsub0_zsub1
9754 : 0, // zsub0_zsub1_zsub2
9755 : 0, // zsub1_zsub2
9756 : 0, // zsub1_zsub2_zsub3
9757 : 0, // zsub2_zsub3
9758 : 0, // zsub1_then_dsub_zsub2_then_dsub
9759 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9760 : 0, // zsub1_then_zsub_zsub2_then_zsub
9761 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9762 : 0, // zsub2_then_dsub_zsub3_then_dsub
9763 : 0, // zsub2_then_zsub_zsub3_then_zsub
9764 : },
9765 : { // GPR32sp
9766 : 0, // bsub
9767 : 0, // dsub
9768 : 0, // dsub0
9769 : 0, // dsub1
9770 : 0, // dsub2
9771 : 0, // dsub3
9772 : 0, // hsub
9773 : 0, // qhisub
9774 : 0, // qsub
9775 : 0, // qsub0
9776 : 0, // qsub1
9777 : 0, // qsub2
9778 : 0, // qsub3
9779 : 0, // ssub
9780 : 0, // sub_32
9781 : 0, // sube32
9782 : 0, // sube64
9783 : 0, // subo32
9784 : 0, // subo64
9785 : 0, // zsub
9786 : 0, // zsub0
9787 : 0, // zsub1
9788 : 0, // zsub2
9789 : 0, // zsub3
9790 : 0, // zsub_hi
9791 : 0, // dsub1_then_bsub
9792 : 0, // dsub1_then_hsub
9793 : 0, // dsub1_then_ssub
9794 : 0, // dsub3_then_bsub
9795 : 0, // dsub3_then_hsub
9796 : 0, // dsub3_then_ssub
9797 : 0, // dsub2_then_bsub
9798 : 0, // dsub2_then_hsub
9799 : 0, // dsub2_then_ssub
9800 : 0, // qsub1_then_bsub
9801 : 0, // qsub1_then_dsub
9802 : 0, // qsub1_then_hsub
9803 : 0, // qsub1_then_ssub
9804 : 0, // qsub3_then_bsub
9805 : 0, // qsub3_then_dsub
9806 : 0, // qsub3_then_hsub
9807 : 0, // qsub3_then_ssub
9808 : 0, // qsub2_then_bsub
9809 : 0, // qsub2_then_dsub
9810 : 0, // qsub2_then_hsub
9811 : 0, // qsub2_then_ssub
9812 : 0, // subo64_then_sub_32
9813 : 0, // zsub1_then_bsub
9814 : 0, // zsub1_then_dsub
9815 : 0, // zsub1_then_hsub
9816 : 0, // zsub1_then_ssub
9817 : 0, // zsub1_then_zsub
9818 : 0, // zsub1_then_zsub_hi
9819 : 0, // zsub3_then_bsub
9820 : 0, // zsub3_then_dsub
9821 : 0, // zsub3_then_hsub
9822 : 0, // zsub3_then_ssub
9823 : 0, // zsub3_then_zsub
9824 : 0, // zsub3_then_zsub_hi
9825 : 0, // zsub2_then_bsub
9826 : 0, // zsub2_then_dsub
9827 : 0, // zsub2_then_hsub
9828 : 0, // zsub2_then_ssub
9829 : 0, // zsub2_then_zsub
9830 : 0, // zsub2_then_zsub_hi
9831 : 0, // dsub0_dsub1
9832 : 0, // dsub0_dsub1_dsub2
9833 : 0, // dsub1_dsub2
9834 : 0, // dsub1_dsub2_dsub3
9835 : 0, // dsub2_dsub3
9836 : 0, // dsub_qsub1_then_dsub
9837 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9838 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9839 : 0, // qsub0_qsub1
9840 : 0, // qsub0_qsub1_qsub2
9841 : 0, // qsub1_qsub2
9842 : 0, // qsub1_qsub2_qsub3
9843 : 0, // qsub2_qsub3
9844 : 0, // qsub1_then_dsub_qsub2_then_dsub
9845 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9846 : 0, // qsub2_then_dsub_qsub3_then_dsub
9847 : 0, // sub_32_subo64_then_sub_32
9848 : 0, // dsub_zsub1_then_dsub
9849 : 0, // zsub_zsub1_then_zsub
9850 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9851 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9852 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9853 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9854 : 0, // zsub0_zsub1
9855 : 0, // zsub0_zsub1_zsub2
9856 : 0, // zsub1_zsub2
9857 : 0, // zsub1_zsub2_zsub3
9858 : 0, // zsub2_zsub3
9859 : 0, // zsub1_then_dsub_zsub2_then_dsub
9860 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9861 : 0, // zsub1_then_zsub_zsub2_then_zsub
9862 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9863 : 0, // zsub2_then_dsub_zsub3_then_dsub
9864 : 0, // zsub2_then_zsub_zsub3_then_zsub
9865 : },
9866 : { // GPR32common
9867 : 0, // bsub
9868 : 0, // dsub
9869 : 0, // dsub0
9870 : 0, // dsub1
9871 : 0, // dsub2
9872 : 0, // dsub3
9873 : 0, // hsub
9874 : 0, // qhisub
9875 : 0, // qsub
9876 : 0, // qsub0
9877 : 0, // qsub1
9878 : 0, // qsub2
9879 : 0, // qsub3
9880 : 0, // ssub
9881 : 0, // sub_32
9882 : 0, // sube32
9883 : 0, // sube64
9884 : 0, // subo32
9885 : 0, // subo64
9886 : 0, // zsub
9887 : 0, // zsub0
9888 : 0, // zsub1
9889 : 0, // zsub2
9890 : 0, // zsub3
9891 : 0, // zsub_hi
9892 : 0, // dsub1_then_bsub
9893 : 0, // dsub1_then_hsub
9894 : 0, // dsub1_then_ssub
9895 : 0, // dsub3_then_bsub
9896 : 0, // dsub3_then_hsub
9897 : 0, // dsub3_then_ssub
9898 : 0, // dsub2_then_bsub
9899 : 0, // dsub2_then_hsub
9900 : 0, // dsub2_then_ssub
9901 : 0, // qsub1_then_bsub
9902 : 0, // qsub1_then_dsub
9903 : 0, // qsub1_then_hsub
9904 : 0, // qsub1_then_ssub
9905 : 0, // qsub3_then_bsub
9906 : 0, // qsub3_then_dsub
9907 : 0, // qsub3_then_hsub
9908 : 0, // qsub3_then_ssub
9909 : 0, // qsub2_then_bsub
9910 : 0, // qsub2_then_dsub
9911 : 0, // qsub2_then_hsub
9912 : 0, // qsub2_then_ssub
9913 : 0, // subo64_then_sub_32
9914 : 0, // zsub1_then_bsub
9915 : 0, // zsub1_then_dsub
9916 : 0, // zsub1_then_hsub
9917 : 0, // zsub1_then_ssub
9918 : 0, // zsub1_then_zsub
9919 : 0, // zsub1_then_zsub_hi
9920 : 0, // zsub3_then_bsub
9921 : 0, // zsub3_then_dsub
9922 : 0, // zsub3_then_hsub
9923 : 0, // zsub3_then_ssub
9924 : 0, // zsub3_then_zsub
9925 : 0, // zsub3_then_zsub_hi
9926 : 0, // zsub2_then_bsub
9927 : 0, // zsub2_then_dsub
9928 : 0, // zsub2_then_hsub
9929 : 0, // zsub2_then_ssub
9930 : 0, // zsub2_then_zsub
9931 : 0, // zsub2_then_zsub_hi
9932 : 0, // dsub0_dsub1
9933 : 0, // dsub0_dsub1_dsub2
9934 : 0, // dsub1_dsub2
9935 : 0, // dsub1_dsub2_dsub3
9936 : 0, // dsub2_dsub3
9937 : 0, // dsub_qsub1_then_dsub
9938 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9939 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
9940 : 0, // qsub0_qsub1
9941 : 0, // qsub0_qsub1_qsub2
9942 : 0, // qsub1_qsub2
9943 : 0, // qsub1_qsub2_qsub3
9944 : 0, // qsub2_qsub3
9945 : 0, // qsub1_then_dsub_qsub2_then_dsub
9946 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9947 : 0, // qsub2_then_dsub_qsub3_then_dsub
9948 : 0, // sub_32_subo64_then_sub_32
9949 : 0, // dsub_zsub1_then_dsub
9950 : 0, // zsub_zsub1_then_zsub
9951 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9952 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
9953 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9954 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
9955 : 0, // zsub0_zsub1
9956 : 0, // zsub0_zsub1_zsub2
9957 : 0, // zsub1_zsub2
9958 : 0, // zsub1_zsub2_zsub3
9959 : 0, // zsub2_zsub3
9960 : 0, // zsub1_then_dsub_zsub2_then_dsub
9961 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9962 : 0, // zsub1_then_zsub_zsub2_then_zsub
9963 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9964 : 0, // zsub2_then_dsub_zsub3_then_dsub
9965 : 0, // zsub2_then_zsub_zsub3_then_zsub
9966 : },
9967 : { // CCR
9968 : 0, // bsub
9969 : 0, // dsub
9970 : 0, // dsub0
9971 : 0, // dsub1
9972 : 0, // dsub2
9973 : 0, // dsub3
9974 : 0, // hsub
9975 : 0, // qhisub
9976 : 0, // qsub
9977 : 0, // qsub0
9978 : 0, // qsub1
9979 : 0, // qsub2
9980 : 0, // qsub3
9981 : 0, // ssub
9982 : 0, // sub_32
9983 : 0, // sube32
9984 : 0, // sube64
9985 : 0, // subo32
9986 : 0, // subo64
9987 : 0, // zsub
9988 : 0, // zsub0
9989 : 0, // zsub1
9990 : 0, // zsub2
9991 : 0, // zsub3
9992 : 0, // zsub_hi
9993 : 0, // dsub1_then_bsub
9994 : 0, // dsub1_then_hsub
9995 : 0, // dsub1_then_ssub
9996 : 0, // dsub3_then_bsub
9997 : 0, // dsub3_then_hsub
9998 : 0, // dsub3_then_ssub
9999 : 0, // dsub2_then_bsub
10000 : 0, // dsub2_then_hsub
10001 : 0, // dsub2_then_ssub
10002 : 0, // qsub1_then_bsub
10003 : 0, // qsub1_then_dsub
10004 : 0, // qsub1_then_hsub
10005 : 0, // qsub1_then_ssub
10006 : 0, // qsub3_then_bsub
10007 : 0, // qsub3_then_dsub
10008 : 0, // qsub3_then_hsub
10009 : 0, // qsub3_then_ssub
10010 : 0, // qsub2_then_bsub
10011 : 0, // qsub2_then_dsub
10012 : 0, // qsub2_then_hsub
10013 : 0, // qsub2_then_ssub
10014 : 0, // subo64_then_sub_32
10015 : 0, // zsub1_then_bsub
10016 : 0, // zsub1_then_dsub
10017 : 0, // zsub1_then_hsub
10018 : 0, // zsub1_then_ssub
10019 : 0, // zsub1_then_zsub
10020 : 0, // zsub1_then_zsub_hi
10021 : 0, // zsub3_then_bsub
10022 : 0, // zsub3_then_dsub
10023 : 0, // zsub3_then_hsub
10024 : 0, // zsub3_then_ssub
10025 : 0, // zsub3_then_zsub
10026 : 0, // zsub3_then_zsub_hi
10027 : 0, // zsub2_then_bsub
10028 : 0, // zsub2_then_dsub
10029 : 0, // zsub2_then_hsub
10030 : 0, // zsub2_then_ssub
10031 : 0, // zsub2_then_zsub
10032 : 0, // zsub2_then_zsub_hi
10033 : 0, // dsub0_dsub1
10034 : 0, // dsub0_dsub1_dsub2
10035 : 0, // dsub1_dsub2
10036 : 0, // dsub1_dsub2_dsub3
10037 : 0, // dsub2_dsub3
10038 : 0, // dsub_qsub1_then_dsub
10039 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10040 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10041 : 0, // qsub0_qsub1
10042 : 0, // qsub0_qsub1_qsub2
10043 : 0, // qsub1_qsub2
10044 : 0, // qsub1_qsub2_qsub3
10045 : 0, // qsub2_qsub3
10046 : 0, // qsub1_then_dsub_qsub2_then_dsub
10047 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10048 : 0, // qsub2_then_dsub_qsub3_then_dsub
10049 : 0, // sub_32_subo64_then_sub_32
10050 : 0, // dsub_zsub1_then_dsub
10051 : 0, // zsub_zsub1_then_zsub
10052 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10053 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10054 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10055 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10056 : 0, // zsub0_zsub1
10057 : 0, // zsub0_zsub1_zsub2
10058 : 0, // zsub1_zsub2
10059 : 0, // zsub1_zsub2_zsub3
10060 : 0, // zsub2_zsub3
10061 : 0, // zsub1_then_dsub_zsub2_then_dsub
10062 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10063 : 0, // zsub1_then_zsub_zsub2_then_zsub
10064 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10065 : 0, // zsub2_then_dsub_zsub3_then_dsub
10066 : 0, // zsub2_then_zsub_zsub3_then_zsub
10067 : },
10068 : { // GPR32sponly
10069 : 0, // bsub
10070 : 0, // dsub
10071 : 0, // dsub0
10072 : 0, // dsub1
10073 : 0, // dsub2
10074 : 0, // dsub3
10075 : 0, // hsub
10076 : 0, // qhisub
10077 : 0, // qsub
10078 : 0, // qsub0
10079 : 0, // qsub1
10080 : 0, // qsub2
10081 : 0, // qsub3
10082 : 0, // ssub
10083 : 0, // sub_32
10084 : 0, // sube32
10085 : 0, // sube64
10086 : 0, // subo32
10087 : 0, // subo64
10088 : 0, // zsub
10089 : 0, // zsub0
10090 : 0, // zsub1
10091 : 0, // zsub2
10092 : 0, // zsub3
10093 : 0, // zsub_hi
10094 : 0, // dsub1_then_bsub
10095 : 0, // dsub1_then_hsub
10096 : 0, // dsub1_then_ssub
10097 : 0, // dsub3_then_bsub
10098 : 0, // dsub3_then_hsub
10099 : 0, // dsub3_then_ssub
10100 : 0, // dsub2_then_bsub
10101 : 0, // dsub2_then_hsub
10102 : 0, // dsub2_then_ssub
10103 : 0, // qsub1_then_bsub
10104 : 0, // qsub1_then_dsub
10105 : 0, // qsub1_then_hsub
10106 : 0, // qsub1_then_ssub
10107 : 0, // qsub3_then_bsub
10108 : 0, // qsub3_then_dsub
10109 : 0, // qsub3_then_hsub
10110 : 0, // qsub3_then_ssub
10111 : 0, // qsub2_then_bsub
10112 : 0, // qsub2_then_dsub
10113 : 0, // qsub2_then_hsub
10114 : 0, // qsub2_then_ssub
10115 : 0, // subo64_then_sub_32
10116 : 0, // zsub1_then_bsub
10117 : 0, // zsub1_then_dsub
10118 : 0, // zsub1_then_hsub
10119 : 0, // zsub1_then_ssub
10120 : 0, // zsub1_then_zsub
10121 : 0, // zsub1_then_zsub_hi
10122 : 0, // zsub3_then_bsub
10123 : 0, // zsub3_then_dsub
10124 : 0, // zsub3_then_hsub
10125 : 0, // zsub3_then_ssub
10126 : 0, // zsub3_then_zsub
10127 : 0, // zsub3_then_zsub_hi
10128 : 0, // zsub2_then_bsub
10129 : 0, // zsub2_then_dsub
10130 : 0, // zsub2_then_hsub
10131 : 0, // zsub2_then_ssub
10132 : 0, // zsub2_then_zsub
10133 : 0, // zsub2_then_zsub_hi
10134 : 0, // dsub0_dsub1
10135 : 0, // dsub0_dsub1_dsub2
10136 : 0, // dsub1_dsub2
10137 : 0, // dsub1_dsub2_dsub3
10138 : 0, // dsub2_dsub3
10139 : 0, // dsub_qsub1_then_dsub
10140 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10141 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10142 : 0, // qsub0_qsub1
10143 : 0, // qsub0_qsub1_qsub2
10144 : 0, // qsub1_qsub2
10145 : 0, // qsub1_qsub2_qsub3
10146 : 0, // qsub2_qsub3
10147 : 0, // qsub1_then_dsub_qsub2_then_dsub
10148 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10149 : 0, // qsub2_then_dsub_qsub3_then_dsub
10150 : 0, // sub_32_subo64_then_sub_32
10151 : 0, // dsub_zsub1_then_dsub
10152 : 0, // zsub_zsub1_then_zsub
10153 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10154 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10155 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10156 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10157 : 0, // zsub0_zsub1
10158 : 0, // zsub0_zsub1_zsub2
10159 : 0, // zsub1_zsub2
10160 : 0, // zsub1_zsub2_zsub3
10161 : 0, // zsub2_zsub3
10162 : 0, // zsub1_then_dsub_zsub2_then_dsub
10163 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10164 : 0, // zsub1_then_zsub_zsub2_then_zsub
10165 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10166 : 0, // zsub2_then_dsub_zsub3_then_dsub
10167 : 0, // zsub2_then_zsub_zsub3_then_zsub
10168 : },
10169 : { // WSeqPairsClass
10170 : 0, // bsub
10171 : 0, // dsub
10172 : 0, // dsub0
10173 : 0, // dsub1
10174 : 0, // dsub2
10175 : 0, // dsub3
10176 : 0, // hsub
10177 : 0, // qhisub
10178 : 0, // qsub
10179 : 0, // qsub0
10180 : 0, // qsub1
10181 : 0, // qsub2
10182 : 0, // qsub3
10183 : 0, // ssub
10184 : 0, // sub_32
10185 : 12, // sube32 -> WSeqPairsClass
10186 : 0, // sube64
10187 : 12, // subo32 -> WSeqPairsClass
10188 : 0, // subo64
10189 : 0, // zsub
10190 : 0, // zsub0
10191 : 0, // zsub1
10192 : 0, // zsub2
10193 : 0, // zsub3
10194 : 0, // zsub_hi
10195 : 0, // dsub1_then_bsub
10196 : 0, // dsub1_then_hsub
10197 : 0, // dsub1_then_ssub
10198 : 0, // dsub3_then_bsub
10199 : 0, // dsub3_then_hsub
10200 : 0, // dsub3_then_ssub
10201 : 0, // dsub2_then_bsub
10202 : 0, // dsub2_then_hsub
10203 : 0, // dsub2_then_ssub
10204 : 0, // qsub1_then_bsub
10205 : 0, // qsub1_then_dsub
10206 : 0, // qsub1_then_hsub
10207 : 0, // qsub1_then_ssub
10208 : 0, // qsub3_then_bsub
10209 : 0, // qsub3_then_dsub
10210 : 0, // qsub3_then_hsub
10211 : 0, // qsub3_then_ssub
10212 : 0, // qsub2_then_bsub
10213 : 0, // qsub2_then_dsub
10214 : 0, // qsub2_then_hsub
10215 : 0, // qsub2_then_ssub
10216 : 0, // subo64_then_sub_32
10217 : 0, // zsub1_then_bsub
10218 : 0, // zsub1_then_dsub
10219 : 0, // zsub1_then_hsub
10220 : 0, // zsub1_then_ssub
10221 : 0, // zsub1_then_zsub
10222 : 0, // zsub1_then_zsub_hi
10223 : 0, // zsub3_then_bsub
10224 : 0, // zsub3_then_dsub
10225 : 0, // zsub3_then_hsub
10226 : 0, // zsub3_then_ssub
10227 : 0, // zsub3_then_zsub
10228 : 0, // zsub3_then_zsub_hi
10229 : 0, // zsub2_then_bsub
10230 : 0, // zsub2_then_dsub
10231 : 0, // zsub2_then_hsub
10232 : 0, // zsub2_then_ssub
10233 : 0, // zsub2_then_zsub
10234 : 0, // zsub2_then_zsub_hi
10235 : 0, // dsub0_dsub1
10236 : 0, // dsub0_dsub1_dsub2
10237 : 0, // dsub1_dsub2
10238 : 0, // dsub1_dsub2_dsub3
10239 : 0, // dsub2_dsub3
10240 : 0, // dsub_qsub1_then_dsub
10241 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10242 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10243 : 0, // qsub0_qsub1
10244 : 0, // qsub0_qsub1_qsub2
10245 : 0, // qsub1_qsub2
10246 : 0, // qsub1_qsub2_qsub3
10247 : 0, // qsub2_qsub3
10248 : 0, // qsub1_then_dsub_qsub2_then_dsub
10249 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10250 : 0, // qsub2_then_dsub_qsub3_then_dsub
10251 : 0, // sub_32_subo64_then_sub_32
10252 : 0, // dsub_zsub1_then_dsub
10253 : 0, // zsub_zsub1_then_zsub
10254 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10255 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10256 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10257 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10258 : 0, // zsub0_zsub1
10259 : 0, // zsub0_zsub1_zsub2
10260 : 0, // zsub1_zsub2
10261 : 0, // zsub1_zsub2_zsub3
10262 : 0, // zsub2_zsub3
10263 : 0, // zsub1_then_dsub_zsub2_then_dsub
10264 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10265 : 0, // zsub1_then_zsub_zsub2_then_zsub
10266 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10267 : 0, // zsub2_then_dsub_zsub3_then_dsub
10268 : 0, // zsub2_then_zsub_zsub3_then_zsub
10269 : },
10270 : { // WSeqPairsClass_with_sube32_in_GPR32common
10271 : 0, // bsub
10272 : 0, // dsub
10273 : 0, // dsub0
10274 : 0, // dsub1
10275 : 0, // dsub2
10276 : 0, // dsub3
10277 : 0, // hsub
10278 : 0, // qhisub
10279 : 0, // qsub
10280 : 0, // qsub0
10281 : 0, // qsub1
10282 : 0, // qsub2
10283 : 0, // qsub3
10284 : 0, // ssub
10285 : 0, // sub_32
10286 : 13, // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common
10287 : 0, // sube64
10288 : 13, // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common
10289 : 0, // subo64
10290 : 0, // zsub
10291 : 0, // zsub0
10292 : 0, // zsub1
10293 : 0, // zsub2
10294 : 0, // zsub3
10295 : 0, // zsub_hi
10296 : 0, // dsub1_then_bsub
10297 : 0, // dsub1_then_hsub
10298 : 0, // dsub1_then_ssub
10299 : 0, // dsub3_then_bsub
10300 : 0, // dsub3_then_hsub
10301 : 0, // dsub3_then_ssub
10302 : 0, // dsub2_then_bsub
10303 : 0, // dsub2_then_hsub
10304 : 0, // dsub2_then_ssub
10305 : 0, // qsub1_then_bsub
10306 : 0, // qsub1_then_dsub
10307 : 0, // qsub1_then_hsub
10308 : 0, // qsub1_then_ssub
10309 : 0, // qsub3_then_bsub
10310 : 0, // qsub3_then_dsub
10311 : 0, // qsub3_then_hsub
10312 : 0, // qsub3_then_ssub
10313 : 0, // qsub2_then_bsub
10314 : 0, // qsub2_then_dsub
10315 : 0, // qsub2_then_hsub
10316 : 0, // qsub2_then_ssub
10317 : 0, // subo64_then_sub_32
10318 : 0, // zsub1_then_bsub
10319 : 0, // zsub1_then_dsub
10320 : 0, // zsub1_then_hsub
10321 : 0, // zsub1_then_ssub
10322 : 0, // zsub1_then_zsub
10323 : 0, // zsub1_then_zsub_hi
10324 : 0, // zsub3_then_bsub
10325 : 0, // zsub3_then_dsub
10326 : 0, // zsub3_then_hsub
10327 : 0, // zsub3_then_ssub
10328 : 0, // zsub3_then_zsub
10329 : 0, // zsub3_then_zsub_hi
10330 : 0, // zsub2_then_bsub
10331 : 0, // zsub2_then_dsub
10332 : 0, // zsub2_then_hsub
10333 : 0, // zsub2_then_ssub
10334 : 0, // zsub2_then_zsub
10335 : 0, // zsub2_then_zsub_hi
10336 : 0, // dsub0_dsub1
10337 : 0, // dsub0_dsub1_dsub2
10338 : 0, // dsub1_dsub2
10339 : 0, // dsub1_dsub2_dsub3
10340 : 0, // dsub2_dsub3
10341 : 0, // dsub_qsub1_then_dsub
10342 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10343 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10344 : 0, // qsub0_qsub1
10345 : 0, // qsub0_qsub1_qsub2
10346 : 0, // qsub1_qsub2
10347 : 0, // qsub1_qsub2_qsub3
10348 : 0, // qsub2_qsub3
10349 : 0, // qsub1_then_dsub_qsub2_then_dsub
10350 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10351 : 0, // qsub2_then_dsub_qsub3_then_dsub
10352 : 0, // sub_32_subo64_then_sub_32
10353 : 0, // dsub_zsub1_then_dsub
10354 : 0, // zsub_zsub1_then_zsub
10355 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10356 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10357 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10358 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10359 : 0, // zsub0_zsub1
10360 : 0, // zsub0_zsub1_zsub2
10361 : 0, // zsub1_zsub2
10362 : 0, // zsub1_zsub2_zsub3
10363 : 0, // zsub2_zsub3
10364 : 0, // zsub1_then_dsub_zsub2_then_dsub
10365 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10366 : 0, // zsub1_then_zsub_zsub2_then_zsub
10367 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10368 : 0, // zsub2_then_dsub_zsub3_then_dsub
10369 : 0, // zsub2_then_zsub_zsub3_then_zsub
10370 : },
10371 : { // WSeqPairsClass_with_subo32_in_GPR32common
10372 : 0, // bsub
10373 : 0, // dsub
10374 : 0, // dsub0
10375 : 0, // dsub1
10376 : 0, // dsub2
10377 : 0, // dsub3
10378 : 0, // hsub
10379 : 0, // qhisub
10380 : 0, // qsub
10381 : 0, // qsub0
10382 : 0, // qsub1
10383 : 0, // qsub2
10384 : 0, // qsub3
10385 : 0, // ssub
10386 : 0, // sub_32
10387 : 14, // sube32 -> WSeqPairsClass_with_subo32_in_GPR32common
10388 : 0, // sube64
10389 : 14, // subo32 -> WSeqPairsClass_with_subo32_in_GPR32common
10390 : 0, // subo64
10391 : 0, // zsub
10392 : 0, // zsub0
10393 : 0, // zsub1
10394 : 0, // zsub2
10395 : 0, // zsub3
10396 : 0, // zsub_hi
10397 : 0, // dsub1_then_bsub
10398 : 0, // dsub1_then_hsub
10399 : 0, // dsub1_then_ssub
10400 : 0, // dsub3_then_bsub
10401 : 0, // dsub3_then_hsub
10402 : 0, // dsub3_then_ssub
10403 : 0, // dsub2_then_bsub
10404 : 0, // dsub2_then_hsub
10405 : 0, // dsub2_then_ssub
10406 : 0, // qsub1_then_bsub
10407 : 0, // qsub1_then_dsub
10408 : 0, // qsub1_then_hsub
10409 : 0, // qsub1_then_ssub
10410 : 0, // qsub3_then_bsub
10411 : 0, // qsub3_then_dsub
10412 : 0, // qsub3_then_hsub
10413 : 0, // qsub3_then_ssub
10414 : 0, // qsub2_then_bsub
10415 : 0, // qsub2_then_dsub
10416 : 0, // qsub2_then_hsub
10417 : 0, // qsub2_then_ssub
10418 : 0, // subo64_then_sub_32
10419 : 0, // zsub1_then_bsub
10420 : 0, // zsub1_then_dsub
10421 : 0, // zsub1_then_hsub
10422 : 0, // zsub1_then_ssub
10423 : 0, // zsub1_then_zsub
10424 : 0, // zsub1_then_zsub_hi
10425 : 0, // zsub3_then_bsub
10426 : 0, // zsub3_then_dsub
10427 : 0, // zsub3_then_hsub
10428 : 0, // zsub3_then_ssub
10429 : 0, // zsub3_then_zsub
10430 : 0, // zsub3_then_zsub_hi
10431 : 0, // zsub2_then_bsub
10432 : 0, // zsub2_then_dsub
10433 : 0, // zsub2_then_hsub
10434 : 0, // zsub2_then_ssub
10435 : 0, // zsub2_then_zsub
10436 : 0, // zsub2_then_zsub_hi
10437 : 0, // dsub0_dsub1
10438 : 0, // dsub0_dsub1_dsub2
10439 : 0, // dsub1_dsub2
10440 : 0, // dsub1_dsub2_dsub3
10441 : 0, // dsub2_dsub3
10442 : 0, // dsub_qsub1_then_dsub
10443 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10444 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10445 : 0, // qsub0_qsub1
10446 : 0, // qsub0_qsub1_qsub2
10447 : 0, // qsub1_qsub2
10448 : 0, // qsub1_qsub2_qsub3
10449 : 0, // qsub2_qsub3
10450 : 0, // qsub1_then_dsub_qsub2_then_dsub
10451 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10452 : 0, // qsub2_then_dsub_qsub3_then_dsub
10453 : 0, // sub_32_subo64_then_sub_32
10454 : 0, // dsub_zsub1_then_dsub
10455 : 0, // zsub_zsub1_then_zsub
10456 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10457 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10458 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10459 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10460 : 0, // zsub0_zsub1
10461 : 0, // zsub0_zsub1_zsub2
10462 : 0, // zsub1_zsub2
10463 : 0, // zsub1_zsub2_zsub3
10464 : 0, // zsub2_zsub3
10465 : 0, // zsub1_then_dsub_zsub2_then_dsub
10466 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10467 : 0, // zsub1_then_zsub_zsub2_then_zsub
10468 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10469 : 0, // zsub2_then_dsub_zsub3_then_dsub
10470 : 0, // zsub2_then_zsub_zsub3_then_zsub
10471 : },
10472 : { // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
10473 : 0, // bsub
10474 : 0, // dsub
10475 : 0, // dsub0
10476 : 0, // dsub1
10477 : 0, // dsub2
10478 : 0, // dsub3
10479 : 0, // hsub
10480 : 0, // qhisub
10481 : 0, // qsub
10482 : 0, // qsub0
10483 : 0, // qsub1
10484 : 0, // qsub2
10485 : 0, // qsub3
10486 : 0, // ssub
10487 : 0, // sub_32
10488 : 15, // sube32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
10489 : 0, // sube64
10490 : 15, // subo32 -> WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common
10491 : 0, // subo64
10492 : 0, // zsub
10493 : 0, // zsub0
10494 : 0, // zsub1
10495 : 0, // zsub2
10496 : 0, // zsub3
10497 : 0, // zsub_hi
10498 : 0, // dsub1_then_bsub
10499 : 0, // dsub1_then_hsub
10500 : 0, // dsub1_then_ssub
10501 : 0, // dsub3_then_bsub
10502 : 0, // dsub3_then_hsub
10503 : 0, // dsub3_then_ssub
10504 : 0, // dsub2_then_bsub
10505 : 0, // dsub2_then_hsub
10506 : 0, // dsub2_then_ssub
10507 : 0, // qsub1_then_bsub
10508 : 0, // qsub1_then_dsub
10509 : 0, // qsub1_then_hsub
10510 : 0, // qsub1_then_ssub
10511 : 0, // qsub3_then_bsub
10512 : 0, // qsub3_then_dsub
10513 : 0, // qsub3_then_hsub
10514 : 0, // qsub3_then_ssub
10515 : 0, // qsub2_then_bsub
10516 : 0, // qsub2_then_dsub
10517 : 0, // qsub2_then_hsub
10518 : 0, // qsub2_then_ssub
10519 : 0, // subo64_then_sub_32
10520 : 0, // zsub1_then_bsub
10521 : 0, // zsub1_then_dsub
10522 : 0, // zsub1_then_hsub
10523 : 0, // zsub1_then_ssub
10524 : 0, // zsub1_then_zsub
10525 : 0, // zsub1_then_zsub_hi
10526 : 0, // zsub3_then_bsub
10527 : 0, // zsub3_then_dsub
10528 : 0, // zsub3_then_hsub
10529 : 0, // zsub3_then_ssub
10530 : 0, // zsub3_then_zsub
10531 : 0, // zsub3_then_zsub_hi
10532 : 0, // zsub2_then_bsub
10533 : 0, // zsub2_then_dsub
10534 : 0, // zsub2_then_hsub
10535 : 0, // zsub2_then_ssub
10536 : 0, // zsub2_then_zsub
10537 : 0, // zsub2_then_zsub_hi
10538 : 0, // dsub0_dsub1
10539 : 0, // dsub0_dsub1_dsub2
10540 : 0, // dsub1_dsub2
10541 : 0, // dsub1_dsub2_dsub3
10542 : 0, // dsub2_dsub3
10543 : 0, // dsub_qsub1_then_dsub
10544 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10545 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10546 : 0, // qsub0_qsub1
10547 : 0, // qsub0_qsub1_qsub2
10548 : 0, // qsub1_qsub2
10549 : 0, // qsub1_qsub2_qsub3
10550 : 0, // qsub2_qsub3
10551 : 0, // qsub1_then_dsub_qsub2_then_dsub
10552 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10553 : 0, // qsub2_then_dsub_qsub3_then_dsub
10554 : 0, // sub_32_subo64_then_sub_32
10555 : 0, // dsub_zsub1_then_dsub
10556 : 0, // zsub_zsub1_then_zsub
10557 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10558 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10559 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10560 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10561 : 0, // zsub0_zsub1
10562 : 0, // zsub0_zsub1_zsub2
10563 : 0, // zsub1_zsub2
10564 : 0, // zsub1_zsub2_zsub3
10565 : 0, // zsub2_zsub3
10566 : 0, // zsub1_then_dsub_zsub2_then_dsub
10567 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10568 : 0, // zsub1_then_zsub_zsub2_then_zsub
10569 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10570 : 0, // zsub2_then_dsub_zsub3_then_dsub
10571 : 0, // zsub2_then_zsub_zsub3_then_zsub
10572 : },
10573 : { // GPR64all
10574 : 0, // bsub
10575 : 0, // dsub
10576 : 0, // dsub0
10577 : 0, // dsub1
10578 : 0, // dsub2
10579 : 0, // dsub3
10580 : 0, // hsub
10581 : 0, // qhisub
10582 : 0, // qsub
10583 : 0, // qsub0
10584 : 0, // qsub1
10585 : 0, // qsub2
10586 : 0, // qsub3
10587 : 0, // ssub
10588 : 16, // sub_32 -> GPR64all
10589 : 0, // sube32
10590 : 0, // sube64
10591 : 0, // subo32
10592 : 0, // subo64
10593 : 0, // zsub
10594 : 0, // zsub0
10595 : 0, // zsub1
10596 : 0, // zsub2
10597 : 0, // zsub3
10598 : 0, // zsub_hi
10599 : 0, // dsub1_then_bsub
10600 : 0, // dsub1_then_hsub
10601 : 0, // dsub1_then_ssub
10602 : 0, // dsub3_then_bsub
10603 : 0, // dsub3_then_hsub
10604 : 0, // dsub3_then_ssub
10605 : 0, // dsub2_then_bsub
10606 : 0, // dsub2_then_hsub
10607 : 0, // dsub2_then_ssub
10608 : 0, // qsub1_then_bsub
10609 : 0, // qsub1_then_dsub
10610 : 0, // qsub1_then_hsub
10611 : 0, // qsub1_then_ssub
10612 : 0, // qsub3_then_bsub
10613 : 0, // qsub3_then_dsub
10614 : 0, // qsub3_then_hsub
10615 : 0, // qsub3_then_ssub
10616 : 0, // qsub2_then_bsub
10617 : 0, // qsub2_then_dsub
10618 : 0, // qsub2_then_hsub
10619 : 0, // qsub2_then_ssub
10620 : 0, // subo64_then_sub_32
10621 : 0, // zsub1_then_bsub
10622 : 0, // zsub1_then_dsub
10623 : 0, // zsub1_then_hsub
10624 : 0, // zsub1_then_ssub
10625 : 0, // zsub1_then_zsub
10626 : 0, // zsub1_then_zsub_hi
10627 : 0, // zsub3_then_bsub
10628 : 0, // zsub3_then_dsub
10629 : 0, // zsub3_then_hsub
10630 : 0, // zsub3_then_ssub
10631 : 0, // zsub3_then_zsub
10632 : 0, // zsub3_then_zsub_hi
10633 : 0, // zsub2_then_bsub
10634 : 0, // zsub2_then_dsub
10635 : 0, // zsub2_then_hsub
10636 : 0, // zsub2_then_ssub
10637 : 0, // zsub2_then_zsub
10638 : 0, // zsub2_then_zsub_hi
10639 : 0, // dsub0_dsub1
10640 : 0, // dsub0_dsub1_dsub2
10641 : 0, // dsub1_dsub2
10642 : 0, // dsub1_dsub2_dsub3
10643 : 0, // dsub2_dsub3
10644 : 0, // dsub_qsub1_then_dsub
10645 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10646 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10647 : 0, // qsub0_qsub1
10648 : 0, // qsub0_qsub1_qsub2
10649 : 0, // qsub1_qsub2
10650 : 0, // qsub1_qsub2_qsub3
10651 : 0, // qsub2_qsub3
10652 : 0, // qsub1_then_dsub_qsub2_then_dsub
10653 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10654 : 0, // qsub2_then_dsub_qsub3_then_dsub
10655 : 0, // sub_32_subo64_then_sub_32
10656 : 0, // dsub_zsub1_then_dsub
10657 : 0, // zsub_zsub1_then_zsub
10658 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10659 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10660 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10661 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10662 : 0, // zsub0_zsub1
10663 : 0, // zsub0_zsub1_zsub2
10664 : 0, // zsub1_zsub2
10665 : 0, // zsub1_zsub2_zsub3
10666 : 0, // zsub2_zsub3
10667 : 0, // zsub1_then_dsub_zsub2_then_dsub
10668 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10669 : 0, // zsub1_then_zsub_zsub2_then_zsub
10670 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10671 : 0, // zsub2_then_dsub_zsub3_then_dsub
10672 : 0, // zsub2_then_zsub_zsub3_then_zsub
10673 : },
10674 : { // FPR64
10675 : 17, // bsub -> FPR64
10676 : 0, // dsub
10677 : 0, // dsub0
10678 : 0, // dsub1
10679 : 0, // dsub2
10680 : 0, // dsub3
10681 : 17, // hsub -> FPR64
10682 : 0, // qhisub
10683 : 0, // qsub
10684 : 0, // qsub0
10685 : 0, // qsub1
10686 : 0, // qsub2
10687 : 0, // qsub3
10688 : 17, // ssub -> FPR64
10689 : 0, // sub_32
10690 : 0, // sube32
10691 : 0, // sube64
10692 : 0, // subo32
10693 : 0, // subo64
10694 : 0, // zsub
10695 : 0, // zsub0
10696 : 0, // zsub1
10697 : 0, // zsub2
10698 : 0, // zsub3
10699 : 0, // zsub_hi
10700 : 0, // dsub1_then_bsub
10701 : 0, // dsub1_then_hsub
10702 : 0, // dsub1_then_ssub
10703 : 0, // dsub3_then_bsub
10704 : 0, // dsub3_then_hsub
10705 : 0, // dsub3_then_ssub
10706 : 0, // dsub2_then_bsub
10707 : 0, // dsub2_then_hsub
10708 : 0, // dsub2_then_ssub
10709 : 0, // qsub1_then_bsub
10710 : 0, // qsub1_then_dsub
10711 : 0, // qsub1_then_hsub
10712 : 0, // qsub1_then_ssub
10713 : 0, // qsub3_then_bsub
10714 : 0, // qsub3_then_dsub
10715 : 0, // qsub3_then_hsub
10716 : 0, // qsub3_then_ssub
10717 : 0, // qsub2_then_bsub
10718 : 0, // qsub2_then_dsub
10719 : 0, // qsub2_then_hsub
10720 : 0, // qsub2_then_ssub
10721 : 0, // subo64_then_sub_32
10722 : 0, // zsub1_then_bsub
10723 : 0, // zsub1_then_dsub
10724 : 0, // zsub1_then_hsub
10725 : 0, // zsub1_then_ssub
10726 : 0, // zsub1_then_zsub
10727 : 0, // zsub1_then_zsub_hi
10728 : 0, // zsub3_then_bsub
10729 : 0, // zsub3_then_dsub
10730 : 0, // zsub3_then_hsub
10731 : 0, // zsub3_then_ssub
10732 : 0, // zsub3_then_zsub
10733 : 0, // zsub3_then_zsub_hi
10734 : 0, // zsub2_then_bsub
10735 : 0, // zsub2_then_dsub
10736 : 0, // zsub2_then_hsub
10737 : 0, // zsub2_then_ssub
10738 : 0, // zsub2_then_zsub
10739 : 0, // zsub2_then_zsub_hi
10740 : 0, // dsub0_dsub1
10741 : 0, // dsub0_dsub1_dsub2
10742 : 0, // dsub1_dsub2
10743 : 0, // dsub1_dsub2_dsub3
10744 : 0, // dsub2_dsub3
10745 : 0, // dsub_qsub1_then_dsub
10746 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10747 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10748 : 0, // qsub0_qsub1
10749 : 0, // qsub0_qsub1_qsub2
10750 : 0, // qsub1_qsub2
10751 : 0, // qsub1_qsub2_qsub3
10752 : 0, // qsub2_qsub3
10753 : 0, // qsub1_then_dsub_qsub2_then_dsub
10754 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10755 : 0, // qsub2_then_dsub_qsub3_then_dsub
10756 : 0, // sub_32_subo64_then_sub_32
10757 : 0, // dsub_zsub1_then_dsub
10758 : 0, // zsub_zsub1_then_zsub
10759 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10760 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10761 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10762 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10763 : 0, // zsub0_zsub1
10764 : 0, // zsub0_zsub1_zsub2
10765 : 0, // zsub1_zsub2
10766 : 0, // zsub1_zsub2_zsub3
10767 : 0, // zsub2_zsub3
10768 : 0, // zsub1_then_dsub_zsub2_then_dsub
10769 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10770 : 0, // zsub1_then_zsub_zsub2_then_zsub
10771 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10772 : 0, // zsub2_then_dsub_zsub3_then_dsub
10773 : 0, // zsub2_then_zsub_zsub3_then_zsub
10774 : },
10775 : { // GPR64
10776 : 0, // bsub
10777 : 0, // dsub
10778 : 0, // dsub0
10779 : 0, // dsub1
10780 : 0, // dsub2
10781 : 0, // dsub3
10782 : 0, // hsub
10783 : 0, // qhisub
10784 : 0, // qsub
10785 : 0, // qsub0
10786 : 0, // qsub1
10787 : 0, // qsub2
10788 : 0, // qsub3
10789 : 0, // ssub
10790 : 18, // sub_32 -> GPR64
10791 : 0, // sube32
10792 : 0, // sube64
10793 : 0, // subo32
10794 : 0, // subo64
10795 : 0, // zsub
10796 : 0, // zsub0
10797 : 0, // zsub1
10798 : 0, // zsub2
10799 : 0, // zsub3
10800 : 0, // zsub_hi
10801 : 0, // dsub1_then_bsub
10802 : 0, // dsub1_then_hsub
10803 : 0, // dsub1_then_ssub
10804 : 0, // dsub3_then_bsub
10805 : 0, // dsub3_then_hsub
10806 : 0, // dsub3_then_ssub
10807 : 0, // dsub2_then_bsub
10808 : 0, // dsub2_then_hsub
10809 : 0, // dsub2_then_ssub
10810 : 0, // qsub1_then_bsub
10811 : 0, // qsub1_then_dsub
10812 : 0, // qsub1_then_hsub
10813 : 0, // qsub1_then_ssub
10814 : 0, // qsub3_then_bsub
10815 : 0, // qsub3_then_dsub
10816 : 0, // qsub3_then_hsub
10817 : 0, // qsub3_then_ssub
10818 : 0, // qsub2_then_bsub
10819 : 0, // qsub2_then_dsub
10820 : 0, // qsub2_then_hsub
10821 : 0, // qsub2_then_ssub
10822 : 0, // subo64_then_sub_32
10823 : 0, // zsub1_then_bsub
10824 : 0, // zsub1_then_dsub
10825 : 0, // zsub1_then_hsub
10826 : 0, // zsub1_then_ssub
10827 : 0, // zsub1_then_zsub
10828 : 0, // zsub1_then_zsub_hi
10829 : 0, // zsub3_then_bsub
10830 : 0, // zsub3_then_dsub
10831 : 0, // zsub3_then_hsub
10832 : 0, // zsub3_then_ssub
10833 : 0, // zsub3_then_zsub
10834 : 0, // zsub3_then_zsub_hi
10835 : 0, // zsub2_then_bsub
10836 : 0, // zsub2_then_dsub
10837 : 0, // zsub2_then_hsub
10838 : 0, // zsub2_then_ssub
10839 : 0, // zsub2_then_zsub
10840 : 0, // zsub2_then_zsub_hi
10841 : 0, // dsub0_dsub1
10842 : 0, // dsub0_dsub1_dsub2
10843 : 0, // dsub1_dsub2
10844 : 0, // dsub1_dsub2_dsub3
10845 : 0, // dsub2_dsub3
10846 : 0, // dsub_qsub1_then_dsub
10847 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10848 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10849 : 0, // qsub0_qsub1
10850 : 0, // qsub0_qsub1_qsub2
10851 : 0, // qsub1_qsub2
10852 : 0, // qsub1_qsub2_qsub3
10853 : 0, // qsub2_qsub3
10854 : 0, // qsub1_then_dsub_qsub2_then_dsub
10855 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10856 : 0, // qsub2_then_dsub_qsub3_then_dsub
10857 : 0, // sub_32_subo64_then_sub_32
10858 : 0, // dsub_zsub1_then_dsub
10859 : 0, // zsub_zsub1_then_zsub
10860 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10861 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10862 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10863 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10864 : 0, // zsub0_zsub1
10865 : 0, // zsub0_zsub1_zsub2
10866 : 0, // zsub1_zsub2
10867 : 0, // zsub1_zsub2_zsub3
10868 : 0, // zsub2_zsub3
10869 : 0, // zsub1_then_dsub_zsub2_then_dsub
10870 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10871 : 0, // zsub1_then_zsub_zsub2_then_zsub
10872 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10873 : 0, // zsub2_then_dsub_zsub3_then_dsub
10874 : 0, // zsub2_then_zsub_zsub3_then_zsub
10875 : },
10876 : { // GPR64sp
10877 : 0, // bsub
10878 : 0, // dsub
10879 : 0, // dsub0
10880 : 0, // dsub1
10881 : 0, // dsub2
10882 : 0, // dsub3
10883 : 0, // hsub
10884 : 0, // qhisub
10885 : 0, // qsub
10886 : 0, // qsub0
10887 : 0, // qsub1
10888 : 0, // qsub2
10889 : 0, // qsub3
10890 : 0, // ssub
10891 : 19, // sub_32 -> GPR64sp
10892 : 0, // sube32
10893 : 0, // sube64
10894 : 0, // subo32
10895 : 0, // subo64
10896 : 0, // zsub
10897 : 0, // zsub0
10898 : 0, // zsub1
10899 : 0, // zsub2
10900 : 0, // zsub3
10901 : 0, // zsub_hi
10902 : 0, // dsub1_then_bsub
10903 : 0, // dsub1_then_hsub
10904 : 0, // dsub1_then_ssub
10905 : 0, // dsub3_then_bsub
10906 : 0, // dsub3_then_hsub
10907 : 0, // dsub3_then_ssub
10908 : 0, // dsub2_then_bsub
10909 : 0, // dsub2_then_hsub
10910 : 0, // dsub2_then_ssub
10911 : 0, // qsub1_then_bsub
10912 : 0, // qsub1_then_dsub
10913 : 0, // qsub1_then_hsub
10914 : 0, // qsub1_then_ssub
10915 : 0, // qsub3_then_bsub
10916 : 0, // qsub3_then_dsub
10917 : 0, // qsub3_then_hsub
10918 : 0, // qsub3_then_ssub
10919 : 0, // qsub2_then_bsub
10920 : 0, // qsub2_then_dsub
10921 : 0, // qsub2_then_hsub
10922 : 0, // qsub2_then_ssub
10923 : 0, // subo64_then_sub_32
10924 : 0, // zsub1_then_bsub
10925 : 0, // zsub1_then_dsub
10926 : 0, // zsub1_then_hsub
10927 : 0, // zsub1_then_ssub
10928 : 0, // zsub1_then_zsub
10929 : 0, // zsub1_then_zsub_hi
10930 : 0, // zsub3_then_bsub
10931 : 0, // zsub3_then_dsub
10932 : 0, // zsub3_then_hsub
10933 : 0, // zsub3_then_ssub
10934 : 0, // zsub3_then_zsub
10935 : 0, // zsub3_then_zsub_hi
10936 : 0, // zsub2_then_bsub
10937 : 0, // zsub2_then_dsub
10938 : 0, // zsub2_then_hsub
10939 : 0, // zsub2_then_ssub
10940 : 0, // zsub2_then_zsub
10941 : 0, // zsub2_then_zsub_hi
10942 : 0, // dsub0_dsub1
10943 : 0, // dsub0_dsub1_dsub2
10944 : 0, // dsub1_dsub2
10945 : 0, // dsub1_dsub2_dsub3
10946 : 0, // dsub2_dsub3
10947 : 0, // dsub_qsub1_then_dsub
10948 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10949 : 0, // dsub_qsub1_then_dsub_qsub2_then_dsub
10950 : 0, // qsub0_qsub1
10951 : 0, // qsub0_qsub1_qsub2
10952 : 0, // qsub1_qsub2
10953 : 0, // qsub1_qsub2_qsub3
10954 : 0, // qsub2_qsub3
10955 : 0, // qsub1_then_dsub_qsub2_then_dsub
10956 : 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10957 : 0, // qsub2_then_dsub_qsub3_then_dsub
10958 : 0, // sub_32_subo64_then_sub_32
10959 : 0, // dsub_zsub1_then_dsub
10960 : 0, // zsub_zsub1_then_zsub
10961 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10962 : 0, // dsub_zsub1_then_dsub_zsub2_then_dsub
10963 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10964 : 0, // zsub_zsub1_then_zsub_zsub2_then_zsub
10965 : 0, // zsub0_zsub1
10966 : 0, // zsub0_zsub1_zsub2
10967 : 0, // zsub1_zsub2
10968 : 0, // zsub1_zsub2_zsub3
10969 : 0, // zsub2_zsub3
10970 : 0, // zsub1_then_dsub_zsub2_then_dsub
10971 : 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10972 : 0, // zsub1_then_zsub_zsub2_then_zsub
10973 : 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10974 : 0, // zsub2_then_dsub_zsub3_then_dsub
10975 : 0, // zsub2_then_zsub_zsub3_then_zsub
10976 : },
10977 : { // GPR64common
10978 : 0, // bsub
10979 : 0, // dsub
10980 : 0, // dsub0
10981 : 0, // dsub1
10982 : 0, // dsub2
10983 : 0, // dsub3
10984 : 0, // hsub
10985 : 0, // qhisub
10986 : 0, // qsub
10987 : 0, // qsub0
10988 : 0, // qsub1
10989 : 0, // qsub2
10990 : 0, // qsub3
10991 : 0, // ssub
10992 : 20, // sub_32 -> GPR64common
10993 : 0, // sube32
10994 : 0, // sube64
10995 : 0, // subo32
10996 : 0, // subo64
10997 : 0, // zsub
10998 : 0, // zsub0
10999 : 0, // zsub1
11000 : 0, // zsub2
11001 < |
