LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenAsmMatcher.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 673 4491 15.0 %
Date: 2018-10-20 13:21:21 Functions: 10 19 52.6 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Assembly Matcher Source Fragment                                           *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : 
      10             : #ifdef GET_ASSEMBLER_HEADER
      11             : #undef GET_ASSEMBLER_HEADER
      12             :   // This should be included into the middle of the declaration of
      13             :   // your subclasses implementation of MCTargetAsmParser.
      14             :   uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
      15             :   void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
      16             :                        const OperandVector &Operands,
      17             :                        const SmallBitVector &OptionalOperandsMask);
      18             :   void convertToMapAndConstraints(unsigned Kind,
      19             :                            const OperandVector &Operands) override;
      20             :   unsigned MatchInstructionImpl(const OperandVector &Operands,
      21             :                                 MCInst &Inst,
      22             :                                 uint64_t &ErrorInfo,
      23             :                                 bool matchingInlineAsm,
      24             :                                 unsigned VariantID = 0);
      25             :   OperandMatchResultTy MatchOperandParserImpl(
      26             :     OperandVector &Operands,
      27             :     StringRef Mnemonic,
      28             :     bool ParseForAllFeatures = false);
      29             :   OperandMatchResultTy tryCustomParseOperand(
      30             :     OperandVector &Operands,
      31             :     unsigned MCK);
      32             : 
      33             : #endif // GET_ASSEMBLER_HEADER_INFO
      34             : 
      35             : 
      36             : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
      37             : #undef GET_OPERAND_DIAGNOSTIC_TYPES
      38             : 
      39             : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
      40             : 
      41             : 
      42             : #ifdef GET_REGISTER_MATCHER
      43             : #undef GET_REGISTER_MATCHER
      44             : 
      45             : // Flags for subtarget features that participate in instruction matching.
      46             : enum SubtargetFeatureFlag : uint64_t {
      47             :   Feature_isSICI = (1ULL << 30),
      48             :   Feature_isVI = (1ULL << 31),
      49             :   Feature_isGFX9 = (1ULL << 28),
      50             :   Feature_isCIVI = (1ULL << 26),
      51             :   Feature_HasFlatAddressSpace = (1ULL << 8),
      52             :   Feature_HasFlatGlobalInsts = (1ULL << 9),
      53             :   Feature_HasFlatScratchInsts = (1ULL << 10),
      54             :   Feature_HasD16LoadStore = (1ULL << 4),
      55             :   Feature_HasUnpackedD16VMem = (1ULL << 20),
      56             :   Feature_HasPackedD16VMem = (1ULL << 15),
      57             :   Feature_D16PreservesUnusedBits = (1ULL << 0),
      58             :   Feature_HasDSAddTid = (1ULL << 7),
      59             :   Feature_HasAddNoCarryInsts = (1ULL << 3),
      60             :   Feature_NotHasAddNoCarryInsts = (1ULL << 23),
      61             :   Feature_Has16BitInsts = (1ULL << 2),
      62             :   Feature_HasVOP3PInsts = (1ULL << 22),
      63             :   Feature_NotHasVOP3PInsts = (1ULL << 24),
      64             :   Feature_HasSDWA = (1ULL << 17),
      65             :   Feature_HasSDWA9 = (1ULL << 18),
      66             :   Feature_HasDPP = (1ULL << 6),
      67             :   Feature_HasR128A16 = (1ULL << 16),
      68             :   Feature_HasIntClamp = (1ULL << 12),
      69             :   Feature_HasMadMixInsts = (1ULL << 13),
      70             :   Feature_HasScalarAtomics = (1ULL << 19),
      71             :   Feature_HasVGPRIndexMode = (1ULL << 21),
      72             :   Feature_HasMovrel = (1ULL << 14),
      73             :   Feature_HasFmaMixInsts = (1ULL << 11),
      74             :   Feature_HasDLInsts = (1ULL << 5),
      75             :   Feature_isCIOnly = (1ULL << 25),
      76             :   Feature_isVIOnly = (1ULL << 32),
      77             :   Feature_DisableInst = (1ULL << 1),
      78             :   Feature_isGCN = (1ULL << 27),
      79             :   Feature_isSI = (1ULL << 29),
      80             :   Feature_None = 0
      81             : };
      82             : 
      83             : #endif // GET_REGISTER_MATCHER
      84             : 
      85             : 
      86             : #ifdef GET_SUBTARGET_FEATURE_NAME
      87             : #undef GET_SUBTARGET_FEATURE_NAME
      88             : 
      89             : // User-level names for subtarget features that participate in
      90             : // instruction matching.
      91             : static const char *getSubtargetFeatureName(uint64_t Val) {
      92             :   switch(Val) {
      93             :   case Feature_isSICI: return "";
      94             :   case Feature_isVI: return "";
      95             :   case Feature_isGFX9: return "";
      96             :   case Feature_isCIVI: return "";
      97             :   case Feature_HasFlatAddressSpace: return "";
      98             :   case Feature_HasFlatGlobalInsts: return "";
      99             :   case Feature_HasFlatScratchInsts: return "";
     100             :   case Feature_HasD16LoadStore: return "";
     101             :   case Feature_HasUnpackedD16VMem: return "";
     102             :   case Feature_HasPackedD16VMem: return "";
     103             :   case Feature_D16PreservesUnusedBits: return "";
     104             :   case Feature_HasDSAddTid: return "";
     105             :   case Feature_HasAddNoCarryInsts: return "";
     106             :   case Feature_NotHasAddNoCarryInsts: return "";
     107             :   case Feature_Has16BitInsts: return "";
     108             :   case Feature_HasVOP3PInsts: return "";
     109             :   case Feature_NotHasVOP3PInsts: return "";
     110             :   case Feature_HasSDWA: return "";
     111             :   case Feature_HasSDWA9: return "";
     112             :   case Feature_HasDPP: return "";
     113             :   case Feature_HasR128A16: return "";
     114             :   case Feature_HasIntClamp: return "";
     115             :   case Feature_HasMadMixInsts: return "";
     116             :   case Feature_HasScalarAtomics: return "";
     117             :   case Feature_HasVGPRIndexMode: return "";
     118             :   case Feature_HasMovrel: return "";
     119             :   case Feature_HasFmaMixInsts: return "";
     120             :   case Feature_HasDLInsts: return "";
     121             :   case Feature_isCIOnly: return "";
     122             :   case Feature_isVIOnly: return "";
     123             :   case Feature_DisableInst: return "";
     124             :   case Feature_isGCN: return "";
     125             :   case Feature_isSI: return "";
     126             :   default: return "(unknown)";
     127             :   }
     128             : }
     129             : 
     130             : #endif // GET_SUBTARGET_FEATURE_NAME
     131             : 
     132             : 
     133             : #ifdef GET_MATCHER_IMPLEMENTATION
     134             : #undef GET_MATCHER_IMPLEMENTATION
     135             : 
     136      216633 : static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
     137      216633 :   switch (VariantID) {
     138             :     case 0:
     139             :       switch (Mnemonic.size()) {
     140             :       default: break;
     141             :       case 9:    // 1 string to match.
     142       14496 :         if (memcmp(Mnemonic.data()+0, "v_nop_e32", 9) != 0)
     143             :           break;
     144           0 :         Mnemonic = "v_nop";    // "v_nop_e32"
     145           0 :         return;
     146             :       case 10:   // 1 string to match.
     147        9017 :         if (memcmp(Mnemonic.data()+0, "v_swap_b32", 10) != 0)
     148             :           break;
     149          29 :         Mnemonic = "v_swap_b32";       // "v_swap_b32"
     150          29 :         return;
     151             :       case 11:   // 2 strings to match.
     152        5021 :         if (memcmp(Mnemonic.data()+0, "v_mad", 5) != 0)
     153             :           break;
     154             :         switch (Mnemonic[5]) {
     155             :         default: break;
     156             :         case 'a':        // 1 string to match.
     157          93 :           if (memcmp(Mnemonic.data()+6, "k_f16", 5) != 0)
     158             :             break;
     159          35 :           Mnemonic = "v_madak_f16";    // "v_madak_f16"
     160          35 :           return;
     161             :         case 'm':        // 1 string to match.
     162          83 :           if (memcmp(Mnemonic.data()+6, "k_f16", 5) != 0)
     163             :             break;
     164          39 :           Mnemonic = "v_madmk_f16";    // "v_madmk_f16"
     165          39 :           return;
     166             :         }
     167             :         break;
     168             :       case 12:   // 1 string to match.
     169       11824 :         if (memcmp(Mnemonic.data()+0, "v_or_b32_e32", 12) != 0)
     170             :           break;
     171           0 :         if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_or_b32_e32"
     172           0 :           Mnemonic = "v_or_b32";
     173             :         return;
     174             :       case 13:   // 46 strings to match.
     175       13990 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
     176             :           break;
     177             :         switch (Mnemonic[2]) {
     178             :         default: break;
     179         304 :         case 'a':        // 6 strings to match.
     180             :           switch (Mnemonic[3]) {
     181             :           default: break;
     182             :           case 'd':      // 5 strings to match.
     183          18 :             if (memcmp(Mnemonic.data()+4, "d_", 2) != 0)
     184             :               break;
     185             :             switch (Mnemonic[6]) {
     186             :             default: break;
     187           0 :             case 'f':    // 2 strings to match.
     188             :               switch (Mnemonic[7]) {
     189             :               default: break;
     190             :               case '1':  // 1 string to match.
     191           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     192             :                   break;
     193           0 :                 Mnemonic = "v_add_f16";        // "v_add_f16_e32"
     194           0 :                 return;
     195             :               case '3':  // 1 string to match.
     196           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     197             :                   break;
     198           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_add_f32_e32"
     199           0 :                   Mnemonic = "v_add_f32";
     200             :                 return;
     201             :               }
     202             :               break;
     203             :             case 'i':    // 1 string to match.
     204           0 :               if (memcmp(Mnemonic.data()+7, "32_e32", 6) != 0)
     205             :                 break;
     206           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_add_i32_e32"
     207           0 :                 Mnemonic = "v_add_i32";
     208             :               return;
     209           0 :             case 'u':    // 2 strings to match.
     210             :               switch (Mnemonic[7]) {
     211             :               default: break;
     212             :               case '1':  // 1 string to match.
     213           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     214             :                   break;
     215           0 :                 Mnemonic = "v_add_u16";        // "v_add_u16_e32"
     216           0 :                 return;
     217             :               case '3':  // 1 string to match.
     218           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     219             :                   break;
     220           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_add_u32_e32"
     221           0 :                   Mnemonic = "v_add_u32";
     222             :                 return;
     223             :               }
     224             :               break;
     225             :             }
     226             :             break;
     227             :           case 'n':      // 1 string to match.
     228           0 :             if (memcmp(Mnemonic.data()+4, "d_b32_e32", 9) != 0)
     229             :               break;
     230           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_and_b32_e32"
     231           0 :               Mnemonic = "v_and_b32";
     232             :             return;
     233             :           }
     234             :           break;
     235             :         case 'b':        // 1 string to match.
     236           0 :           if (memcmp(Mnemonic.data()+3, "fm_b32_e32", 10) != 0)
     237             :             break;
     238           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_bfm_b32_e32"
     239           0 :             Mnemonic = "v_bfm_b32";
     240             :           return;
     241        7160 :         case 'c':        // 3 strings to match.
     242             :           switch (Mnemonic[3]) {
     243             :           default: break;
     244             :           case 'l':      // 1 string to match.
     245           0 :             if (memcmp(Mnemonic.data()+4, "rexcp_e32", 9) != 0)
     246             :               break;
     247           0 :             Mnemonic = "v_clrexcp";    // "v_clrexcp_e32"
     248           0 :             return;
     249             :           case 'o':      // 2 strings to match.
     250           0 :             if (memcmp(Mnemonic.data()+4, "s_f", 3) != 0)
     251             :               break;
     252             :             switch (Mnemonic[7]) {
     253             :             default: break;
     254             :             case '1':    // 1 string to match.
     255           0 :               if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     256             :                 break;
     257           0 :               Mnemonic = "v_cos_f16";  // "v_cos_f16_e32"
     258           0 :               return;
     259             :             case '3':    // 1 string to match.
     260           0 :               if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     261             :                 break;
     262           0 :               Mnemonic = "v_cos_f32";  // "v_cos_f32_e32"
     263           0 :               return;
     264             :             }
     265             :             break;
     266             :           }
     267             :           break;
     268             :         case 'e':        // 2 strings to match.
     269           0 :           if (memcmp(Mnemonic.data()+3, "xp_f", 4) != 0)
     270             :             break;
     271             :           switch (Mnemonic[7]) {
     272             :           default: break;
     273             :           case '1':      // 1 string to match.
     274           0 :             if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     275             :               break;
     276           0 :             Mnemonic = "v_exp_f16";    // "v_exp_f16_e32"
     277           0 :             return;
     278             :           case '3':      // 1 string to match.
     279           0 :             if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     280             :               break;
     281           0 :             Mnemonic = "v_exp_f32";    // "v_exp_f32_e32"
     282           0 :             return;
     283             :           }
     284             :           break;
     285             :         case 'l':        // 2 strings to match.
     286         666 :           if (memcmp(Mnemonic.data()+3, "og_f", 4) != 0)
     287             :             break;
     288             :           switch (Mnemonic[7]) {
     289             :           default: break;
     290             :           case '1':      // 1 string to match.
     291           0 :             if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     292             :               break;
     293           0 :             Mnemonic = "v_log_f16";    // "v_log_f16_e32"
     294           0 :             return;
     295             :           case '3':      // 1 string to match.
     296           0 :             if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     297             :               break;
     298           0 :             Mnemonic = "v_log_f32";    // "v_log_f32_e32"
     299           0 :             return;
     300             :           }
     301             :           break;
     302        1734 :         case 'm':        // 17 strings to match.
     303             :           switch (Mnemonic[3]) {
     304             :           default: break;
     305        1258 :           case 'a':      // 8 strings to match.
     306             :             switch (Mnemonic[4]) {
     307             :             default: break;
     308             :             case 'c':    // 2 strings to match.
     309           0 :               if (memcmp(Mnemonic.data()+5, "_f", 2) != 0)
     310             :                 break;
     311             :               switch (Mnemonic[7]) {
     312             :               default: break;
     313             :               case '1':  // 1 string to match.
     314           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     315             :                   break;
     316           0 :                 Mnemonic = "v_mac_f16";        // "v_mac_f16_e32"
     317           0 :                 return;
     318             :               case '3':  // 1 string to match.
     319           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     320             :                   break;
     321           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mac_f32_e32"
     322           0 :                   Mnemonic = "v_mac_f32";
     323             :                 return;
     324             :               }
     325             :               break;
     326           0 :             case 'x':    // 6 strings to match.
     327           0 :               if (Mnemonic[5] != '_')
     328             :                 break;
     329             :               switch (Mnemonic[6]) {
     330             :               default: break;
     331           0 :               case 'f':  // 2 strings to match.
     332             :                 switch (Mnemonic[7]) {
     333             :                 default: break;
     334             :                 case '1':        // 1 string to match.
     335           0 :                   if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     336             :                     break;
     337           0 :                   Mnemonic = "v_max_f16";      // "v_max_f16_e32"
     338           0 :                   return;
     339             :                 case '3':        // 1 string to match.
     340           0 :                   if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     341             :                     break;
     342           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_f32_e32"
     343           0 :                     Mnemonic = "v_max_f32";
     344             :                   return;
     345             :                 }
     346             :                 break;
     347           0 :               case 'i':  // 2 strings to match.
     348             :                 switch (Mnemonic[7]) {
     349             :                 default: break;
     350             :                 case '1':        // 1 string to match.
     351           0 :                   if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     352             :                     break;
     353           0 :                   Mnemonic = "v_max_i16";      // "v_max_i16_e32"
     354           0 :                   return;
     355             :                 case '3':        // 1 string to match.
     356           0 :                   if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     357             :                     break;
     358           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_i32_e32"
     359           0 :                     Mnemonic = "v_max_i32";
     360             :                   return;
     361             :                 }
     362             :                 break;
     363           0 :               case 'u':  // 2 strings to match.
     364             :                 switch (Mnemonic[7]) {
     365             :                 default: break;
     366             :                 case '1':        // 1 string to match.
     367           0 :                   if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     368             :                     break;
     369           0 :                   Mnemonic = "v_max_u16";      // "v_max_u16_e32"
     370           0 :                   return;
     371             :                 case '3':        // 1 string to match.
     372           0 :                   if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     373             :                     break;
     374           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_u32_e32"
     375           0 :                     Mnemonic = "v_max_u32";
     376             :                   return;
     377             :                 }
     378             :                 break;
     379             :               }
     380             :               break;
     381             :             }
     382             :             break;
     383             :           case 'i':      // 6 strings to match.
     384           0 :             if (memcmp(Mnemonic.data()+4, "n_", 2) != 0)
     385             :               break;
     386             :             switch (Mnemonic[6]) {
     387             :             default: break;
     388           0 :             case 'f':    // 2 strings to match.
     389             :               switch (Mnemonic[7]) {
     390             :               default: break;
     391             :               case '1':  // 1 string to match.
     392           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     393             :                   break;
     394           0 :                 Mnemonic = "v_min_f16";        // "v_min_f16_e32"
     395           0 :                 return;
     396             :               case '3':  // 1 string to match.
     397           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     398             :                   break;
     399           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_f32_e32"
     400           0 :                   Mnemonic = "v_min_f32";
     401             :                 return;
     402             :               }
     403             :               break;
     404           0 :             case 'i':    // 2 strings to match.
     405             :               switch (Mnemonic[7]) {
     406             :               default: break;
     407             :               case '1':  // 1 string to match.
     408           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     409             :                   break;
     410           0 :                 Mnemonic = "v_min_i16";        // "v_min_i16_e32"
     411           0 :                 return;
     412             :               case '3':  // 1 string to match.
     413           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     414             :                   break;
     415           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_i32_e32"
     416           0 :                   Mnemonic = "v_min_i32";
     417             :                 return;
     418             :               }
     419             :               break;
     420           0 :             case 'u':    // 2 strings to match.
     421             :               switch (Mnemonic[7]) {
     422             :               default: break;
     423             :               case '1':  // 1 string to match.
     424           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     425             :                   break;
     426           0 :                 Mnemonic = "v_min_u16";        // "v_min_u16_e32"
     427           0 :                 return;
     428             :               case '3':  // 1 string to match.
     429           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     430             :                   break;
     431           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_u32_e32"
     432           0 :                   Mnemonic = "v_min_u32";
     433             :                 return;
     434             :               }
     435             :               break;
     436             :             }
     437             :             break;
     438             :           case 'o':      // 1 string to match.
     439         164 :             if (memcmp(Mnemonic.data()+4, "v_b32_e32", 9) != 0)
     440             :               break;
     441           0 :             Mnemonic = "v_mov_b32";    // "v_mov_b32_e32"
     442           0 :             return;
     443             :           case 'u':      // 2 strings to match.
     444         312 :             if (memcmp(Mnemonic.data()+4, "l_f", 3) != 0)
     445             :               break;
     446             :             switch (Mnemonic[7]) {
     447             :             default: break;
     448             :             case '1':    // 1 string to match.
     449           0 :               if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     450             :                 break;
     451           0 :               Mnemonic = "v_mul_f16";  // "v_mul_f16_e32"
     452           0 :               return;
     453             :             case '3':    // 1 string to match.
     454           0 :               if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     455             :                 break;
     456           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_f32_e32"
     457           0 :                 Mnemonic = "v_mul_f32";
     458             :               return;
     459             :             }
     460             :             break;
     461             :           }
     462             :           break;
     463             :         case 'n':        // 1 string to match.
     464           0 :           if (memcmp(Mnemonic.data()+3, "ot_b32_e32", 10) != 0)
     465             :             break;
     466           0 :           Mnemonic = "v_not_b32";      // "v_not_b32_e32"
     467           0 :           return;
     468           0 :         case 'r':        // 6 strings to match.
     469             :           switch (Mnemonic[3]) {
     470             :           default: break;
     471             :           case 'c':      // 3 strings to match.
     472           0 :             if (memcmp(Mnemonic.data()+4, "p_f", 3) != 0)
     473             :               break;
     474             :             switch (Mnemonic[7]) {
     475             :             default: break;
     476             :             case '1':    // 1 string to match.
     477           0 :               if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     478             :                 break;
     479           0 :               Mnemonic = "v_rcp_f16";  // "v_rcp_f16_e32"
     480           0 :               return;
     481             :             case '3':    // 1 string to match.
     482           0 :               if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     483             :                 break;
     484           0 :               Mnemonic = "v_rcp_f32";  // "v_rcp_f32_e32"
     485           0 :               return;
     486             :             case '6':    // 1 string to match.
     487           0 :               if (memcmp(Mnemonic.data()+8, "4_e32", 5) != 0)
     488             :                 break;
     489           0 :               Mnemonic = "v_rcp_f64";  // "v_rcp_f64_e32"
     490           0 :               return;
     491             :             }
     492             :             break;
     493             :           case 's':      // 3 strings to match.
     494           0 :             if (memcmp(Mnemonic.data()+4, "q_f", 3) != 0)
     495             :               break;
     496             :             switch (Mnemonic[7]) {
     497             :             default: break;
     498             :             case '1':    // 1 string to match.
     499           0 :               if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     500             :                 break;
     501           0 :               Mnemonic = "v_rsq_f16";  // "v_rsq_f16_e32"
     502           0 :               return;
     503             :             case '3':    // 1 string to match.
     504           0 :               if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     505             :                 break;
     506           0 :               Mnemonic = "v_rsq_f32";  // "v_rsq_f32_e32"
     507           0 :               return;
     508             :             case '6':    // 1 string to match.
     509           0 :               if (memcmp(Mnemonic.data()+8, "4_e32", 5) != 0)
     510             :                 break;
     511           0 :               Mnemonic = "v_rsq_f64";  // "v_rsq_f64_e32"
     512           0 :               return;
     513             :             }
     514             :             break;
     515             :           }
     516             :           break;
     517          52 :         case 's':        // 7 strings to match.
     518             :           switch (Mnemonic[3]) {
     519             :           default: break;
     520             :           case 'i':      // 2 strings to match.
     521           0 :             if (memcmp(Mnemonic.data()+4, "n_f", 3) != 0)
     522             :               break;
     523             :             switch (Mnemonic[7]) {
     524             :             default: break;
     525             :             case '1':    // 1 string to match.
     526           0 :               if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     527             :                 break;
     528           0 :               Mnemonic = "v_sin_f16";  // "v_sin_f16_e32"
     529           0 :               return;
     530             :             case '3':    // 1 string to match.
     531           0 :               if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     532             :                 break;
     533           0 :               Mnemonic = "v_sin_f32";  // "v_sin_f32_e32"
     534           0 :               return;
     535             :             }
     536             :             break;
     537             :           case 'u':      // 5 strings to match.
     538          52 :             if (memcmp(Mnemonic.data()+4, "b_", 2) != 0)
     539             :               break;
     540             :             switch (Mnemonic[6]) {
     541             :             default: break;
     542           0 :             case 'f':    // 2 strings to match.
     543             :               switch (Mnemonic[7]) {
     544             :               default: break;
     545             :               case '1':  // 1 string to match.
     546           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     547             :                   break;
     548           0 :                 Mnemonic = "v_sub_f16";        // "v_sub_f16_e32"
     549           0 :                 return;
     550             :               case '3':  // 1 string to match.
     551           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     552             :                   break;
     553           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_sub_f32_e32"
     554           0 :                   Mnemonic = "v_sub_f32";
     555             :                 return;
     556             :               }
     557             :               break;
     558             :             case 'i':    // 1 string to match.
     559           0 :               if (memcmp(Mnemonic.data()+7, "32_e32", 6) != 0)
     560             :                 break;
     561           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_sub_i32_e32"
     562           0 :                 Mnemonic = "v_sub_i32";
     563             :               return;
     564           0 :             case 'u':    // 2 strings to match.
     565             :               switch (Mnemonic[7]) {
     566             :               default: break;
     567             :               case '1':  // 1 string to match.
     568           0 :                 if (memcmp(Mnemonic.data()+8, "6_e32", 5) != 0)
     569             :                   break;
     570           0 :                 Mnemonic = "v_sub_u16";        // "v_sub_u16_e32"
     571           0 :                 return;
     572             :               case '3':  // 1 string to match.
     573           0 :                 if (memcmp(Mnemonic.data()+8, "2_e32", 5) != 0)
     574             :                   break;
     575           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_sub_u32_e32"
     576           0 :                   Mnemonic = "v_sub_u32";
     577             :                 return;
     578             :               }
     579             :               break;
     580             :             }
     581             :             break;
     582             :           }
     583             :           break;
     584             :         case 'x':        // 1 string to match.
     585           0 :           if (memcmp(Mnemonic.data()+3, "or_b32_e32", 10) != 0)
     586             :             break;
     587           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_xor_b32_e32"
     588           0 :             Mnemonic = "v_xor_b32";
     589             :           return;
     590             :         }
     591             :         break;
     592             :       case 14:   // 16 strings to match.
     593        6128 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
     594             :           break;
     595             :         switch (Mnemonic[2]) {
     596             :         default: break;
     597         274 :         case 'a':        // 2 strings to match.
     598             :           switch (Mnemonic[3]) {
     599             :           default: break;
     600             :           case 'd':      // 1 string to match.
     601          92 :             if (memcmp(Mnemonic.data()+4, "dc_u32_e32", 10) != 0)
     602             :               break;
     603           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_addc_u32_e32"
     604           0 :               Mnemonic = "v_addc_u32";
     605             :             return;
     606             :           case 's':      // 1 string to match.
     607           0 :             if (memcmp(Mnemonic.data()+4, "hr_i32_e32", 10) != 0)
     608             :               break;
     609           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_ashr_i32_e32"
     610           0 :               Mnemonic = "v_ashr_i32";
     611             :             return;
     612             :           }
     613             :           break;
     614             :         case 'c':        // 3 strings to match.
     615        2003 :           if (memcmp(Mnemonic.data()+3, "eil_f", 5) != 0)
     616             :             break;
     617             :           switch (Mnemonic[8]) {
     618             :           default: break;
     619             :           case '1':      // 1 string to match.
     620           0 :             if (memcmp(Mnemonic.data()+9, "6_e32", 5) != 0)
     621             :               break;
     622           0 :             Mnemonic = "v_ceil_f16";   // "v_ceil_f16_e32"
     623           0 :             return;
     624             :           case '3':      // 1 string to match.
     625           0 :             if (memcmp(Mnemonic.data()+9, "2_e32", 5) != 0)
     626             :               break;
     627           0 :             Mnemonic = "v_ceil_f32";   // "v_ceil_f32_e32"
     628           0 :             return;
     629             :           case '6':      // 1 string to match.
     630           0 :             if (memcmp(Mnemonic.data()+9, "4_e32", 5) != 0)
     631             :               break;
     632           0 :             Mnemonic = "v_ceil_f64";   // "v_ceil_f64_e32"
     633           0 :             return;
     634             :           }
     635             :           break;
     636           0 :         case 'f':        // 4 strings to match.
     637             :           switch (Mnemonic[3]) {
     638             :           default: break;
     639           0 :           case 'f':      // 3 strings to match.
     640           0 :             if (Mnemonic[4] != 'b')
     641             :               break;
     642             :             switch (Mnemonic[5]) {
     643             :             default: break;
     644           0 :             case 'h':    // 2 strings to match.
     645           0 :               if (Mnemonic[6] != '_')
     646             :                 break;
     647             :               switch (Mnemonic[7]) {
     648             :               default: break;
     649             :               case 'i':  // 1 string to match.
     650           0 :                 if (memcmp(Mnemonic.data()+8, "32_e32", 6) != 0)
     651             :                   break;
     652           0 :                 Mnemonic = "v_ffbh_i32";       // "v_ffbh_i32_e32"
     653           0 :                 return;
     654             :               case 'u':  // 1 string to match.
     655           0 :                 if (memcmp(Mnemonic.data()+8, "32_e32", 6) != 0)
     656             :                   break;
     657           0 :                 Mnemonic = "v_ffbh_u32";       // "v_ffbh_u32_e32"
     658           0 :                 return;
     659             :               }
     660             :               break;
     661             :             case 'l':    // 1 string to match.
     662           0 :               if (memcmp(Mnemonic.data()+6, "_b32_e32", 8) != 0)
     663             :                 break;
     664           0 :               Mnemonic = "v_ffbl_b32";         // "v_ffbl_b32_e32"
     665           0 :               return;
     666             :             }
     667             :             break;
     668             :           case 'm':      // 1 string to match.
     669           0 :             if (memcmp(Mnemonic.data()+4, "ac_f32_e32", 10) != 0)
     670             :               break;
     671           0 :             Mnemonic = "v_fmac_f32";   // "v_fmac_f32_e32"
     672           0 :             return;
     673             :           }
     674             :           break;
     675             :         case 'l':        // 2 strings to match.
     676          92 :           if (memcmp(Mnemonic.data()+3, "sh", 2) != 0)
     677             :             break;
     678             :           switch (Mnemonic[5]) {
     679             :           default: break;
     680             :           case 'l':      // 1 string to match.
     681          92 :             if (memcmp(Mnemonic.data()+6, "_b32_e32", 8) != 0)
     682             :               break;
     683           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_lshl_b32_e32"
     684           0 :               Mnemonic = "v_lshl_b32";
     685             :             return;
     686             :           case 'r':      // 1 string to match.
     687           0 :             if (memcmp(Mnemonic.data()+6, "_b32_e32", 8) != 0)
     688             :               break;
     689           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_lshr_b32_e32"
     690           0 :               Mnemonic = "v_lshr_b32";
     691             :             return;
     692             :           }
     693             :           break;
     694           0 :         case 's':        // 4 strings to match.
     695             :           switch (Mnemonic[3]) {
     696             :           default: break;
     697             :           case 'q':      // 3 strings to match.
     698           0 :             if (memcmp(Mnemonic.data()+4, "rt_f", 4) != 0)
     699             :               break;
     700             :             switch (Mnemonic[8]) {
     701             :             default: break;
     702             :             case '1':    // 1 string to match.
     703           0 :               if (memcmp(Mnemonic.data()+9, "6_e32", 5) != 0)
     704             :                 break;
     705           0 :               Mnemonic = "v_sqrt_f16";         // "v_sqrt_f16_e32"
     706           0 :               return;
     707             :             case '3':    // 1 string to match.
     708           0 :               if (memcmp(Mnemonic.data()+9, "2_e32", 5) != 0)
     709             :                 break;
     710           0 :               Mnemonic = "v_sqrt_f32";         // "v_sqrt_f32_e32"
     711           0 :               return;
     712             :             case '6':    // 1 string to match.
     713           0 :               if (memcmp(Mnemonic.data()+9, "4_e32", 5) != 0)
     714             :                 break;
     715           0 :               Mnemonic = "v_sqrt_f64";         // "v_sqrt_f64_e32"
     716           0 :               return;
     717             :             }
     718             :             break;
     719             :           case 'u':      // 1 string to match.
     720           0 :             if (memcmp(Mnemonic.data()+4, "bb_u32_e32", 10) != 0)
     721             :               break;
     722           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_subb_u32_e32"
     723           0 :               Mnemonic = "v_subb_u32";
     724             :             return;
     725             :           }
     726             :           break;
     727             :         case 'x':        // 1 string to match.
     728           0 :           if (memcmp(Mnemonic.data()+3, "nor_b32_e32", 11) != 0)
     729             :             break;
     730           0 :           Mnemonic = "v_xnor_b32";     // "v_xnor_b32_e32"
     731           0 :           return;
     732             :         }
     733             :         break;
     734             :       case 15:   // 17 strings to match.
     735        5889 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
     736             :           break;
     737             :         switch (Mnemonic[2]) {
     738             :         default: break;
     739             :         case 'b':        // 1 string to match.
     740           0 :           if (memcmp(Mnemonic.data()+3, "frev_b32_e32", 12) != 0)
     741             :             break;
     742           0 :           Mnemonic = "v_bfrev_b32";    // "v_bfrev_b32_e32"
     743           0 :           return;
     744          22 :         case 'f':        // 6 strings to match.
     745             :           switch (Mnemonic[3]) {
     746             :           default: break;
     747             :           case 'l':      // 3 strings to match.
     748           0 :             if (memcmp(Mnemonic.data()+4, "oor_f", 5) != 0)
     749             :               break;
     750             :             switch (Mnemonic[9]) {
     751             :             default: break;
     752             :             case '1':    // 1 string to match.
     753           0 :               if (memcmp(Mnemonic.data()+10, "6_e32", 5) != 0)
     754             :                 break;
     755           0 :               Mnemonic = "v_floor_f16";        // "v_floor_f16_e32"
     756           0 :               return;
     757             :             case '3':    // 1 string to match.
     758           0 :               if (memcmp(Mnemonic.data()+10, "2_e32", 5) != 0)
     759             :                 break;
     760           0 :               Mnemonic = "v_floor_f32";        // "v_floor_f32_e32"
     761           0 :               return;
     762             :             case '6':    // 1 string to match.
     763           0 :               if (memcmp(Mnemonic.data()+10, "4_e32", 5) != 0)
     764             :                 break;
     765           0 :               Mnemonic = "v_floor_f64";        // "v_floor_f64_e32"
     766           0 :               return;
     767             :             }
     768             :             break;
     769             :           case 'r':      // 3 strings to match.
     770           0 :             if (memcmp(Mnemonic.data()+4, "act_f", 5) != 0)
     771             :               break;
     772             :             switch (Mnemonic[9]) {
     773             :             default: break;
     774             :             case '1':    // 1 string to match.
     775           0 :               if (memcmp(Mnemonic.data()+10, "6_e32", 5) != 0)
     776             :                 break;
     777           0 :               Mnemonic = "v_fract_f16";        // "v_fract_f16_e32"
     778           0 :               return;
     779             :             case '3':    // 1 string to match.
     780           0 :               if (memcmp(Mnemonic.data()+10, "2_e32", 5) != 0)
     781             :                 break;
     782           0 :               Mnemonic = "v_fract_f32";        // "v_fract_f32_e32"
     783           0 :               return;
     784             :             case '6':    // 1 string to match.
     785           0 :               if (memcmp(Mnemonic.data()+10, "4_e32", 5) != 0)
     786             :                 break;
     787           0 :               Mnemonic = "v_fract_f64";        // "v_fract_f64_e32"
     788           0 :               return;
     789             :             }
     790             :             break;
     791             :           }
     792             :           break;
     793             :         case 'l':        // 2 strings to match.
     794          39 :           if (memcmp(Mnemonic.data()+3, "dexp_f", 6) != 0)
     795             :             break;
     796             :           switch (Mnemonic[9]) {
     797             :           default: break;
     798             :           case '1':      // 1 string to match.
     799           0 :             if (memcmp(Mnemonic.data()+10, "6_e32", 5) != 0)
     800             :               break;
     801           0 :             Mnemonic = "v_ldexp_f16";  // "v_ldexp_f16_e32"
     802           0 :             return;
     803             :           case '3':      // 1 string to match.
     804           0 :             if (memcmp(Mnemonic.data()+10, "2_e32", 5) != 0)
     805             :               break;
     806           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_ldexp_f32_e32"
     807           0 :               Mnemonic = "v_ldexp_f32";
     808             :             return;
     809             :           }
     810             :           break;
     811             :         case 'm':        // 2 strings to match.
     812         272 :           if (memcmp(Mnemonic.data()+3, "ad", 2) != 0)
     813             :             break;
     814             :           switch (Mnemonic[5]) {
     815             :           default: break;
     816             :           case 'a':      // 1 string to match.
     817           0 :             if (memcmp(Mnemonic.data()+6, "k_f32_e32", 9) != 0)
     818             :               break;
     819           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_madak_f32_e32"
     820           0 :               Mnemonic = "v_madak_f32";
     821             :             return;
     822             :           case 'm':      // 1 string to match.
     823           0 :             if (memcmp(Mnemonic.data()+6, "k_f32_e32", 9) != 0)
     824             :               break;
     825           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_madmk_f32_e32"
     826           0 :               Mnemonic = "v_madmk_f32";
     827             :             return;
     828             :           }
     829             :           break;
     830             :         case 'r':        // 3 strings to match.
     831         215 :           if (memcmp(Mnemonic.data()+3, "ndne_f", 6) != 0)
     832             :             break;
     833             :           switch (Mnemonic[9]) {
     834             :           default: break;
     835             :           case '1':      // 1 string to match.
     836           0 :             if (memcmp(Mnemonic.data()+10, "6_e32", 5) != 0)
     837             :               break;
     838           0 :             Mnemonic = "v_rndne_f16";  // "v_rndne_f16_e32"
     839           0 :             return;
     840             :           case '3':      // 1 string to match.
     841           0 :             if (memcmp(Mnemonic.data()+10, "2_e32", 5) != 0)
     842             :               break;
     843           0 :             Mnemonic = "v_rndne_f32";  // "v_rndne_f32_e32"
     844           0 :             return;
     845             :           case '6':      // 1 string to match.
     846           0 :             if (memcmp(Mnemonic.data()+10, "4_e32", 5) != 0)
     847             :               break;
     848           0 :             Mnemonic = "v_rndne_f64";  // "v_rndne_f64_e32"
     849           0 :             return;
     850             :           }
     851             :           break;
     852             :         case 't':        // 3 strings to match.
     853           0 :           if (memcmp(Mnemonic.data()+3, "runc_f", 6) != 0)
     854             :             break;
     855             :           switch (Mnemonic[9]) {
     856             :           default: break;
     857             :           case '1':      // 1 string to match.
     858           0 :             if (memcmp(Mnemonic.data()+10, "6_e32", 5) != 0)
     859             :               break;
     860           0 :             Mnemonic = "v_trunc_f16";  // "v_trunc_f16_e32"
     861           0 :             return;
     862             :           case '3':      // 1 string to match.
     863           0 :             if (memcmp(Mnemonic.data()+10, "2_e32", 5) != 0)
     864             :               break;
     865           0 :             Mnemonic = "v_trunc_f32";  // "v_trunc_f32_e32"
     866           0 :             return;
     867             :           case '6':      // 1 string to match.
     868           0 :             if (memcmp(Mnemonic.data()+10, "4_e32", 5) != 0)
     869             :               break;
     870           0 :             Mnemonic = "v_trunc_f64";  // "v_trunc_f64_e32"
     871           0 :             return;
     872             :           }
     873             :           break;
     874             :         }
     875             :         break;
     876             :       case 16:   // 6 strings to match.
     877        5049 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
     878             :           break;
     879             :         switch (Mnemonic[2]) {
     880             :         default: break;
     881             :         case 'm':        // 1 string to match.
     882         937 :           if (memcmp(Mnemonic.data()+3, "ul_lo_u16_e32", 13) != 0)
     883             :             break;
     884           0 :           Mnemonic = "v_mul_lo_u16";   // "v_mul_lo_u16_e32"
     885           0 :           return;
     886             :         case 's':        // 5 strings to match.
     887          18 :           if (memcmp(Mnemonic.data()+3, "ubrev_", 6) != 0)
     888             :             break;
     889             :           switch (Mnemonic[9]) {
     890             :           default: break;
     891           0 :           case 'f':      // 2 strings to match.
     892             :             switch (Mnemonic[10]) {
     893             :             default: break;
     894             :             case '1':    // 1 string to match.
     895           0 :               if (memcmp(Mnemonic.data()+11, "6_e32", 5) != 0)
     896             :                 break;
     897           0 :               Mnemonic = "v_subrev_f16";       // "v_subrev_f16_e32"
     898           0 :               return;
     899             :             case '3':    // 1 string to match.
     900           0 :               if (memcmp(Mnemonic.data()+11, "2_e32", 5) != 0)
     901             :                 break;
     902           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_subrev_f32_e32"
     903           0 :                 Mnemonic = "v_subrev_f32";
     904             :               return;
     905             :             }
     906             :             break;
     907             :           case 'i':      // 1 string to match.
     908           0 :             if (memcmp(Mnemonic.data()+10, "32_e32", 6) != 0)
     909             :               break;
     910           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_subrev_i32_e32"
     911           0 :               Mnemonic = "v_subrev_i32";
     912             :             return;
     913           0 :           case 'u':      // 2 strings to match.
     914             :             switch (Mnemonic[10]) {
     915             :             default: break;
     916             :             case '1':    // 1 string to match.
     917           0 :               if (memcmp(Mnemonic.data()+11, "6_e32", 5) != 0)
     918             :                 break;
     919           0 :               Mnemonic = "v_subrev_u16";       // "v_subrev_u16_e32"
     920           0 :               return;
     921             :             case '3':    // 1 string to match.
     922           0 :               if (memcmp(Mnemonic.data()+11, "2_e32", 5) != 0)
     923             :                 break;
     924           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_subrev_u32_e32"
     925           0 :                 Mnemonic = "v_subrev_u32";
     926             :               return;
     927             :             }
     928             :             break;
     929             :           }
     930             :           break;
     931             :         }
     932             :         break;
     933             :       case 17:   // 29 strings to match.
     934        3793 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
     935             :           break;
     936             :         switch (Mnemonic[2]) {
     937             :         default: break;
     938             :         case 'a':        // 2 strings to match.
     939           0 :           if (memcmp(Mnemonic.data()+3, "shrrev_i", 8) != 0)
     940             :             break;
     941             :           switch (Mnemonic[11]) {
     942             :           default: break;
     943             :           case '1':      // 1 string to match.
     944           0 :             if (memcmp(Mnemonic.data()+12, "6_e32", 5) != 0)
     945             :               break;
     946           0 :             Mnemonic = "v_ashrrev_i16";        // "v_ashrrev_i16_e32"
     947           0 :             return;
     948             :           case '3':      // 1 string to match.
     949           0 :             if (memcmp(Mnemonic.data()+12, "2_e32", 5) != 0)
     950             :               break;
     951           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_ashrrev_i32_e32"
     952           0 :               Mnemonic = "v_ashrrev_i32";
     953             :             return;
     954             :           }
     955             :           break;
     956         210 :         case 'c':        // 17 strings to match.
     957             :           switch (Mnemonic[3]) {
     958             :           default: break;
     959             :           case 'n':      // 1 string to match.
     960           0 :             if (memcmp(Mnemonic.data()+4, "dmask_b32_e32", 13) != 0)
     961             :               break;
     962           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_cndmask_b32_e32"
     963           0 :               Mnemonic = "v_cndmask_b32";
     964             :             return;
     965             :           case 'v':      // 16 strings to match.
     966         210 :             if (memcmp(Mnemonic.data()+4, "t_", 2) != 0)
     967             :               break;
     968             :             switch (Mnemonic[6]) {
     969             :             default: break;
     970         109 :             case 'f':    // 10 strings to match.
     971             :               switch (Mnemonic[7]) {
     972             :               default: break;
     973             :               case '1':  // 3 strings to match.
     974           0 :                 if (memcmp(Mnemonic.data()+8, "6_", 2) != 0)
     975             :                   break;
     976             :                 switch (Mnemonic[10]) {
     977             :                 default: break;
     978             :                 case 'f':        // 1 string to match.
     979           0 :                   if (memcmp(Mnemonic.data()+11, "32_e32", 6) != 0)
     980             :                     break;
     981           0 :                   Mnemonic = "v_cvt_f16_f32";  // "v_cvt_f16_f32_e32"
     982           0 :                   return;
     983             :                 case 'i':        // 1 string to match.
     984           0 :                   if (memcmp(Mnemonic.data()+11, "16_e32", 6) != 0)
     985             :                     break;
     986           0 :                   Mnemonic = "v_cvt_f16_i16";  // "v_cvt_f16_i16_e32"
     987           0 :                   return;
     988             :                 case 'u':        // 1 string to match.
     989           0 :                   if (memcmp(Mnemonic.data()+11, "16_e32", 6) != 0)
     990             :                     break;
     991           0 :                   Mnemonic = "v_cvt_f16_u16";  // "v_cvt_f16_u16_e32"
     992           0 :                   return;
     993             :                 }
     994             :                 break;
     995             :               case '3':  // 4 strings to match.
     996           0 :                 if (memcmp(Mnemonic.data()+8, "2_", 2) != 0)
     997             :                   break;
     998             :                 switch (Mnemonic[10]) {
     999             :                 default: break;
    1000           0 :                 case 'f':        // 2 strings to match.
    1001             :                   switch (Mnemonic[11]) {
    1002             :                   default: break;
    1003             :                   case '1':      // 1 string to match.
    1004           0 :                     if (memcmp(Mnemonic.data()+12, "6_e32", 5) != 0)
    1005             :                       break;
    1006           0 :                     Mnemonic = "v_cvt_f32_f16";        // "v_cvt_f32_f16_e32"
    1007           0 :                     return;
    1008             :                   case '6':      // 1 string to match.
    1009           0 :                     if (memcmp(Mnemonic.data()+12, "4_e32", 5) != 0)
    1010             :                       break;
    1011           0 :                     Mnemonic = "v_cvt_f32_f64";        // "v_cvt_f32_f64_e32"
    1012           0 :                     return;
    1013             :                   }
    1014             :                   break;
    1015             :                 case 'i':        // 1 string to match.
    1016           0 :                   if (memcmp(Mnemonic.data()+11, "32_e32", 6) != 0)
    1017             :                     break;
    1018           0 :                   Mnemonic = "v_cvt_f32_i32";  // "v_cvt_f32_i32_e32"
    1019           0 :                   return;
    1020             :                 case 'u':        // 1 string to match.
    1021           0 :                   if (memcmp(Mnemonic.data()+11, "32_e32", 6) != 0)
    1022             :                     break;
    1023           0 :                   Mnemonic = "v_cvt_f32_u32";  // "v_cvt_f32_u32_e32"
    1024           0 :                   return;
    1025             :                 }
    1026             :                 break;
    1027             :               case '6':  // 3 strings to match.
    1028           0 :                 if (memcmp(Mnemonic.data()+8, "4_", 2) != 0)
    1029             :                   break;
    1030             :                 switch (Mnemonic[10]) {
    1031             :                 default: break;
    1032             :                 case 'f':        // 1 string to match.
    1033           0 :                   if (memcmp(Mnemonic.data()+11, "32_e32", 6) != 0)
    1034             :                     break;
    1035           0 :                   Mnemonic = "v_cvt_f64_f32";  // "v_cvt_f64_f32_e32"
    1036           0 :                   return;
    1037             :                 case 'i':        // 1 string to match.
    1038           0 :                   if (memcmp(Mnemonic.data()+11, "32_e32", 6) != 0)
    1039             :                     break;
    1040           0 :                   Mnemonic = "v_cvt_f64_i32";  // "v_cvt_f64_i32_e32"
    1041           0 :                   return;
    1042             :                 case 'u':        // 1 string to match.
    1043           0 :                   if (memcmp(Mnemonic.data()+11, "32_e32", 6) != 0)
    1044             :                     break;
    1045           0 :                   Mnemonic = "v_cvt_f64_u32";  // "v_cvt_f64_u32_e32"
    1046           0 :                   return;
    1047             :                 }
    1048             :                 break;
    1049             :               }
    1050             :               break;
    1051           0 :             case 'i':    // 3 strings to match.
    1052             :               switch (Mnemonic[7]) {
    1053             :               default: break;
    1054             :               case '1':  // 1 string to match.
    1055           0 :                 if (memcmp(Mnemonic.data()+8, "6_f16_e32", 9) != 0)
    1056             :                   break;
    1057           0 :                 Mnemonic = "v_cvt_i16_f16";    // "v_cvt_i16_f16_e32"
    1058           0 :                 return;
    1059             :               case '3':  // 2 strings to match.
    1060           0 :                 if (memcmp(Mnemonic.data()+8, "2_f", 3) != 0)
    1061             :                   break;
    1062             :                 switch (Mnemonic[11]) {
    1063             :                 default: break;
    1064             :                 case '3':        // 1 string to match.
    1065           0 :                   if (memcmp(Mnemonic.data()+12, "2_e32", 5) != 0)
    1066             :                     break;
    1067           0 :                   Mnemonic = "v_cvt_i32_f32";  // "v_cvt_i32_f32_e32"
    1068           0 :                   return;
    1069             :                 case '6':        // 1 string to match.
    1070           0 :                   if (memcmp(Mnemonic.data()+12, "4_e32", 5) != 0)
    1071             :                     break;
    1072           0 :                   Mnemonic = "v_cvt_i32_f64";  // "v_cvt_i32_f64_e32"
    1073           0 :                   return;
    1074             :                 }
    1075             :                 break;
    1076             :               }
    1077             :               break;
    1078           0 :             case 'u':    // 3 strings to match.
    1079             :               switch (Mnemonic[7]) {
    1080             :               default: break;
    1081             :               case '1':  // 1 string to match.
    1082           0 :                 if (memcmp(Mnemonic.data()+8, "6_f16_e32", 9) != 0)
    1083             :                   break;
    1084           0 :                 Mnemonic = "v_cvt_u16_f16";    // "v_cvt_u16_f16_e32"
    1085           0 :                 return;
    1086             :               case '3':  // 2 strings to match.
    1087           0 :                 if (memcmp(Mnemonic.data()+8, "2_f", 3) != 0)
    1088             :                   break;
    1089             :                 switch (Mnemonic[11]) {
    1090             :                 default: break;
    1091             :                 case '3':        // 1 string to match.
    1092           0 :                   if (memcmp(Mnemonic.data()+12, "2_e32", 5) != 0)
    1093             :                     break;
    1094           0 :                   Mnemonic = "v_cvt_u32_f32";  // "v_cvt_u32_f32_e32"
    1095           0 :                   return;
    1096             :                 case '6':        // 1 string to match.
    1097           0 :                   if (memcmp(Mnemonic.data()+12, "4_e32", 5) != 0)
    1098             :                     break;
    1099           0 :                   Mnemonic = "v_cvt_u32_f64";  // "v_cvt_u32_f64_e32"
    1100           0 :                   return;
    1101             :                 }
    1102             :                 break;
    1103             :               }
    1104             :               break;
    1105             :             }
    1106             :             break;
    1107             :           }
    1108             :           break;
    1109             :         case 'l':        // 4 strings to match.
    1110           0 :           if (memcmp(Mnemonic.data()+3, "sh", 2) != 0)
    1111             :             break;
    1112             :           switch (Mnemonic[5]) {
    1113             :           default: break;
    1114             :           case 'l':      // 2 strings to match.
    1115           0 :             if (memcmp(Mnemonic.data()+6, "rev_b", 5) != 0)
    1116             :               break;
    1117             :             switch (Mnemonic[11]) {
    1118             :             default: break;
    1119             :             case '1':    // 1 string to match.
    1120           0 :               if (memcmp(Mnemonic.data()+12, "6_e32", 5) != 0)
    1121             :                 break;
    1122           0 :               Mnemonic = "v_lshlrev_b16";      // "v_lshlrev_b16_e32"
    1123           0 :               return;
    1124             :             case '3':    // 1 string to match.
    1125           0 :               if (memcmp(Mnemonic.data()+12, "2_e32", 5) != 0)
    1126             :                 break;
    1127           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_lshlrev_b32_e32"
    1128           0 :                 Mnemonic = "v_lshlrev_b32";
    1129             :               return;
    1130             :             }
    1131             :             break;
    1132             :           case 'r':      // 2 strings to match.
    1133           0 :             if (memcmp(Mnemonic.data()+6, "rev_b", 5) != 0)
    1134             :               break;
    1135             :             switch (Mnemonic[11]) {
    1136             :             default: break;
    1137             :             case '1':    // 1 string to match.
    1138           0 :               if (memcmp(Mnemonic.data()+12, "6_e32", 5) != 0)
    1139             :                 break;
    1140           0 :               Mnemonic = "v_lshrrev_b16";      // "v_lshrrev_b16_e32"
    1141           0 :               return;
    1142             :             case '3':    // 1 string to match.
    1143           0 :               if (memcmp(Mnemonic.data()+12, "2_e32", 5) != 0)
    1144             :                 break;
    1145           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_lshrrev_b32_e32"
    1146           0 :                 Mnemonic = "v_lshrrev_b32";
    1147             :               return;
    1148             :             }
    1149             :             break;
    1150             :           }
    1151             :           break;
    1152         211 :         case 'm':        // 5 strings to match.
    1153             :           switch (Mnemonic[3]) {
    1154             :           default: break;
    1155           0 :           case 'o':      // 3 strings to match.
    1156           0 :             if (Mnemonic[4] != 'v')
    1157             :               break;
    1158             :             switch (Mnemonic[5]) {
    1159             :             default: break;
    1160             :             case '_':    // 1 string to match.
    1161           0 :               if (memcmp(Mnemonic.data()+6, "fed_b32_e32", 11) != 0)
    1162             :                 break;
    1163           0 :               Mnemonic = "v_mov_fed_b32";      // "v_mov_fed_b32_e32"
    1164           0 :               return;
    1165             :             case 'r':    // 2 strings to match.
    1166           0 :               if (memcmp(Mnemonic.data()+6, "el", 2) != 0)
    1167             :                 break;
    1168             :               switch (Mnemonic[8]) {
    1169             :               default: break;
    1170             :               case 'd':  // 1 string to match.
    1171           0 :                 if (memcmp(Mnemonic.data()+9, "_b32_e32", 8) != 0)
    1172             :                   break;
    1173           0 :                 Mnemonic = "v_movreld_b32";    // "v_movreld_b32_e32"
    1174           0 :                 return;
    1175             :               case 's':  // 1 string to match.
    1176           0 :                 if (memcmp(Mnemonic.data()+9, "_b32_e32", 8) != 0)
    1177             :                   break;
    1178           0 :                 Mnemonic = "v_movrels_b32";    // "v_movrels_b32_e32"
    1179           0 :                 return;
    1180             :               }
    1181             :               break;
    1182             :             }
    1183             :             break;
    1184             :           case 'u':      // 2 strings to match.
    1185           0 :             if (memcmp(Mnemonic.data()+4, "l_", 2) != 0)
    1186             :               break;
    1187             :             switch (Mnemonic[6]) {
    1188             :             default: break;
    1189             :             case 'i':    // 1 string to match.
    1190           0 :               if (memcmp(Mnemonic.data()+7, "32_i24_e32", 10) != 0)
    1191             :                 break;
    1192           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_i32_i24_e32"
    1193           0 :                 Mnemonic = "v_mul_i32_i24";
    1194             :               return;
    1195             :             case 'u':    // 1 string to match.
    1196           0 :               if (memcmp(Mnemonic.data()+7, "32_u24_e32", 10) != 0)
    1197             :                 break;
    1198           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_u32_u24_e32"
    1199           0 :                 Mnemonic = "v_mul_u32_u24";
    1200             :               return;
    1201             :             }
    1202             :             break;
    1203             :           }
    1204             :           break;
    1205             :         case 's':        // 1 string to match.
    1206           0 :           if (memcmp(Mnemonic.data()+3, "ubbrev_u32_e32", 14) != 0)
    1207             :             break;
    1208           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_subbrev_u32_e32"
    1209           0 :             Mnemonic = "v_subbrev_u32";
    1210             :           return;
    1211             :         }
    1212             :         break;
    1213             :       case 18:   // 3 strings to match.
    1214        2576 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    1215             :           break;
    1216             :         switch (Mnemonic[2]) {
    1217             :         default: break;
    1218             :         case 'b':        // 1 string to match.
    1219           0 :           if (memcmp(Mnemonic.data()+3, "cnt_u32_b32_e32", 15) != 0)
    1220             :             break;
    1221           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_bcnt_u32_b32_e32"
    1222           0 :             Mnemonic = "v_bcnt_u32_b32";
    1223             :           return;
    1224             :         case 'm':        // 1 string to match.
    1225         264 :           if (memcmp(Mnemonic.data()+3, "ovrelsd_b32_e32", 15) != 0)
    1226             :             break;
    1227           0 :           Mnemonic = "v_movrelsd_b32";         // "v_movrelsd_b32_e32"
    1228           0 :           return;
    1229             :         case 'r':        // 1 string to match.
    1230           0 :           if (memcmp(Mnemonic.data()+3, "eadlane_b32_e32", 15) != 0)
    1231             :             break;
    1232           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_readlane_b32_e32"
    1233           0 :             Mnemonic = "v_readlane_b32";
    1234             :           return;
    1235             :         }
    1236             :         break;
    1237             :       case 19:   // 8 strings to match.
    1238        2102 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    1239             :           break;
    1240             :         switch (Mnemonic[2]) {
    1241             :         default: break;
    1242             :         case 'l':        // 1 string to match.
    1243           0 :           if (memcmp(Mnemonic.data()+3, "og_clamp_f32_e32", 16) != 0)
    1244             :             break;
    1245           0 :           Mnemonic = "v_log_clamp_f32";        // "v_log_clamp_f32_e32"
    1246           0 :           return;
    1247          44 :         case 'r':        // 5 strings to match.
    1248             :           switch (Mnemonic[3]) {
    1249             :           default: break;
    1250             :           case 'c':      // 3 strings to match.
    1251           0 :             if (memcmp(Mnemonic.data()+4, "p_", 2) != 0)
    1252             :               break;
    1253             :             switch (Mnemonic[6]) {
    1254             :             default: break;
    1255             :             case 'c':    // 2 strings to match.
    1256           0 :               if (memcmp(Mnemonic.data()+7, "lamp_f", 6) != 0)
    1257             :                 break;
    1258             :               switch (Mnemonic[13]) {
    1259             :               default: break;
    1260             :               case '3':  // 1 string to match.
    1261           0 :                 if (memcmp(Mnemonic.data()+14, "2_e32", 5) != 0)
    1262             :                   break;
    1263           0 :                 Mnemonic = "v_rcp_clamp_f32";  // "v_rcp_clamp_f32_e32"
    1264           0 :                 return;
    1265             :               case '6':  // 1 string to match.
    1266           0 :                 if (memcmp(Mnemonic.data()+14, "4_e32", 5) != 0)
    1267             :                   break;
    1268           0 :                 Mnemonic = "v_rcp_clamp_f64";  // "v_rcp_clamp_f64_e32"
    1269           0 :                 return;
    1270             :               }
    1271             :               break;
    1272             :             case 'i':    // 1 string to match.
    1273           0 :               if (memcmp(Mnemonic.data()+7, "flag_f32_e32", 12) != 0)
    1274             :                 break;
    1275           0 :               Mnemonic = "v_rcp_iflag_f32";    // "v_rcp_iflag_f32_e32"
    1276           0 :               return;
    1277             :             }
    1278             :             break;
    1279             :           case 's':      // 2 strings to match.
    1280           0 :             if (memcmp(Mnemonic.data()+4, "q_clamp_f", 9) != 0)
    1281             :               break;
    1282             :             switch (Mnemonic[13]) {
    1283             :             default: break;
    1284             :             case '3':    // 1 string to match.
    1285           0 :               if (memcmp(Mnemonic.data()+14, "2_e32", 5) != 0)
    1286             :                 break;
    1287           0 :               Mnemonic = "v_rsq_clamp_f32";    // "v_rsq_clamp_f32_e32"
    1288           0 :               return;
    1289             :             case '6':    // 1 string to match.
    1290           0 :               if (memcmp(Mnemonic.data()+14, "4_e32", 5) != 0)
    1291             :                 break;
    1292           0 :               Mnemonic = "v_rsq_clamp_f64";    // "v_rsq_clamp_f64_e32"
    1293           0 :               return;
    1294             :             }
    1295             :             break;
    1296             :           }
    1297             :           break;
    1298             :         case 's':        // 1 string to match.
    1299           0 :           if (memcmp(Mnemonic.data()+3, "at_pk_u8_i16_e32", 16) != 0)
    1300             :             break;
    1301           0 :           Mnemonic = "v_sat_pk_u8_i16";        // "v_sat_pk_u8_i16_e32"
    1302           0 :           return;
    1303             :         case 'w':        // 1 string to match.
    1304           0 :           if (memcmp(Mnemonic.data()+3, "ritelane_b32_e32", 16) != 0)
    1305             :             break;
    1306           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_writelane_b32_e32"
    1307           0 :             Mnemonic = "v_writelane_b32";
    1308             :           return;
    1309             :         }
    1310             :         break;
    1311             :       case 20:   // 20 strings to match.
    1312        2014 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    1313             :           break;
    1314             :         switch (Mnemonic[2]) {
    1315             :         default: break;
    1316             :         case 'c':        // 7 strings to match.
    1317         629 :           if (memcmp(Mnemonic.data()+3, "vt_", 3) != 0)
    1318             :             break;
    1319             :           switch (Mnemonic[6]) {
    1320             :           default: break;
    1321             :           case 'f':      // 4 strings to match.
    1322           0 :             if (memcmp(Mnemonic.data()+7, "32_ubyte", 8) != 0)
    1323             :               break;
    1324             :             switch (Mnemonic[15]) {
    1325             :             default: break;
    1326             :             case '0':    // 1 string to match.
    1327           0 :               if (memcmp(Mnemonic.data()+16, "_e32", 4) != 0)
    1328             :                 break;
    1329           0 :               Mnemonic = "v_cvt_f32_ubyte0";   // "v_cvt_f32_ubyte0_e32"
    1330           0 :               return;
    1331             :             case '1':    // 1 string to match.
    1332           0 :               if (memcmp(Mnemonic.data()+16, "_e32", 4) != 0)
    1333             :                 break;
    1334           0 :               Mnemonic = "v_cvt_f32_ubyte1";   // "v_cvt_f32_ubyte1_e32"
    1335           0 :               return;
    1336             :             case '2':    // 1 string to match.
    1337           0 :               if (memcmp(Mnemonic.data()+16, "_e32", 4) != 0)
    1338             :                 break;
    1339           0 :               Mnemonic = "v_cvt_f32_ubyte2";   // "v_cvt_f32_ubyte2_e32"
    1340           0 :               return;
    1341             :             case '3':    // 1 string to match.
    1342           0 :               if (memcmp(Mnemonic.data()+16, "_e32", 4) != 0)
    1343             :                 break;
    1344           0 :               Mnemonic = "v_cvt_f32_ubyte3";   // "v_cvt_f32_ubyte3_e32"
    1345           0 :               return;
    1346             :             }
    1347             :             break;
    1348             :           case 'o':      // 1 string to match.
    1349           0 :             if (memcmp(Mnemonic.data()+7, "ff_f32_i4_e32", 13) != 0)
    1350             :               break;
    1351           0 :             Mnemonic = "v_cvt_off_f32_i4";     // "v_cvt_off_f32_i4_e32"
    1352           0 :             return;
    1353             :           case 'p':      // 2 strings to match.
    1354         629 :             if (memcmp(Mnemonic.data()+7, "k_", 2) != 0)
    1355             :               break;
    1356             :             switch (Mnemonic[9]) {
    1357             :             default: break;
    1358             :             case 'i':    // 1 string to match.
    1359           0 :               if (memcmp(Mnemonic.data()+10, "16_i32_e32", 10) != 0)
    1360             :                 break;
    1361           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_cvt_pk_i16_i32_e32"
    1362           0 :                 Mnemonic = "v_cvt_pk_i16_i32";
    1363             :               return;
    1364             :             case 'u':    // 1 string to match.
    1365           0 :               if (memcmp(Mnemonic.data()+10, "16_u32_e32", 10) != 0)
    1366             :                 break;
    1367           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_cvt_pk_u16_u32_e32"
    1368           0 :                 Mnemonic = "v_cvt_pk_u16_u32";
    1369             :               return;
    1370             :             }
    1371             :             break;
    1372             :           }
    1373             :           break;
    1374             :         case 'e':        // 1 string to match.
    1375           0 :           if (memcmp(Mnemonic.data()+3, "xp_legacy_f32_e32", 17) != 0)
    1376             :             break;
    1377           0 :           Mnemonic = "v_exp_legacy_f32";       // "v_exp_legacy_f32_e32"
    1378           0 :           return;
    1379             :         case 'f':        // 3 strings to match.
    1380           0 :           if (memcmp(Mnemonic.data()+3, "rexp_mant_f", 11) != 0)
    1381             :             break;
    1382             :           switch (Mnemonic[14]) {
    1383             :           default: break;
    1384             :           case '1':      // 1 string to match.
    1385           0 :             if (memcmp(Mnemonic.data()+15, "6_e32", 5) != 0)
    1386             :               break;
    1387           0 :             Mnemonic = "v_frexp_mant_f16";     // "v_frexp_mant_f16_e32"
    1388           0 :             return;
    1389             :           case '3':      // 1 string to match.
    1390           0 :             if (memcmp(Mnemonic.data()+15, "2_e32", 5) != 0)
    1391             :               break;
    1392           0 :             Mnemonic = "v_frexp_mant_f32";     // "v_frexp_mant_f32_e32"
    1393           0 :             return;
    1394             :           case '6':      // 1 string to match.
    1395           0 :             if (memcmp(Mnemonic.data()+15, "4_e32", 5) != 0)
    1396             :               break;
    1397           0 :             Mnemonic = "v_frexp_mant_f64";     // "v_frexp_mant_f64_e32"
    1398           0 :             return;
    1399             :           }
    1400             :           break;
    1401             :         case 'l':        // 1 string to match.
    1402           0 :           if (memcmp(Mnemonic.data()+3, "og_legacy_f32_e32", 17) != 0)
    1403             :             break;
    1404           0 :           Mnemonic = "v_log_legacy_f32";       // "v_log_legacy_f32_e32"
    1405           0 :           return;
    1406           0 :         case 'm':        // 6 strings to match.
    1407             :           switch (Mnemonic[3]) {
    1408             :           default: break;
    1409           0 :           case 'a':      // 2 strings to match.
    1410             :             switch (Mnemonic[4]) {
    1411             :             default: break;
    1412             :             case 'c':    // 1 string to match.
    1413           0 :               if (memcmp(Mnemonic.data()+5, "_legacy_f32_e32", 15) != 0)
    1414             :                 break;
    1415           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_mac_legacy_f32_e32"
    1416           0 :                 Mnemonic = "v_mac_legacy_f32";
    1417             :               return;
    1418             :             case 'x':    // 1 string to match.
    1419           0 :               if (memcmp(Mnemonic.data()+5, "_legacy_f32_e32", 15) != 0)
    1420             :                 break;
    1421           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_max_legacy_f32_e32"
    1422           0 :                 Mnemonic = "v_max_legacy_f32";
    1423             :               return;
    1424             :             }
    1425             :             break;
    1426             :           case 'i':      // 1 string to match.
    1427           0 :             if (memcmp(Mnemonic.data()+4, "n_legacy_f32_e32", 16) != 0)
    1428             :               break;
    1429           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_min_legacy_f32_e32"
    1430           0 :               Mnemonic = "v_min_legacy_f32";
    1431             :             return;
    1432             :           case 'u':      // 3 strings to match.
    1433           0 :             if (memcmp(Mnemonic.data()+4, "l_", 2) != 0)
    1434             :               break;
    1435             :             switch (Mnemonic[6]) {
    1436             :             default: break;
    1437             :             case 'h':    // 2 strings to match.
    1438           0 :               if (memcmp(Mnemonic.data()+7, "i_", 2) != 0)
    1439             :                 break;
    1440             :               switch (Mnemonic[9]) {
    1441             :               default: break;
    1442             :               case 'i':  // 1 string to match.
    1443           0 :                 if (memcmp(Mnemonic.data()+10, "32_i24_e32", 10) != 0)
    1444             :                   break;
    1445           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mul_hi_i32_i24_e32"
    1446           0 :                   Mnemonic = "v_mul_hi_i32_i24";
    1447             :                 return;
    1448             :               case 'u':  // 1 string to match.
    1449           0 :                 if (memcmp(Mnemonic.data()+10, "32_u24_e32", 10) != 0)
    1450             :                   break;
    1451           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mul_hi_u32_u24_e32"
    1452           0 :                   Mnemonic = "v_mul_hi_u32_u24";
    1453             :                 return;
    1454             :               }
    1455             :               break;
    1456             :             case 'l':    // 1 string to match.
    1457           0 :               if (memcmp(Mnemonic.data()+7, "egacy_f32_e32", 13) != 0)
    1458             :                 break;
    1459           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_legacy_f32_e32"
    1460           0 :                 Mnemonic = "v_mul_legacy_f32";
    1461             :               return;
    1462             :             }
    1463             :             break;
    1464             :           }
    1465             :           break;
    1466           0 :         case 'r':        // 2 strings to match.
    1467             :           switch (Mnemonic[3]) {
    1468             :           default: break;
    1469             :           case 'c':      // 1 string to match.
    1470           0 :             if (memcmp(Mnemonic.data()+4, "p_legacy_f32_e32", 16) != 0)
    1471             :               break;
    1472           0 :             Mnemonic = "v_rcp_legacy_f32";     // "v_rcp_legacy_f32_e32"
    1473           0 :             return;
    1474             :           case 's':      // 1 string to match.
    1475           0 :             if (memcmp(Mnemonic.data()+4, "q_legacy_f32_e32", 16) != 0)
    1476             :               break;
    1477           0 :             Mnemonic = "v_rsq_legacy_f32";     // "v_rsq_legacy_f32_e32"
    1478           0 :             return;
    1479             :           }
    1480             :           break;
    1481             :         }
    1482             :         break;
    1483             :       case 21:   // 2 strings to match.
    1484        1237 :         if (memcmp(Mnemonic.data()+0, "v_cvt_", 6) != 0)
    1485             :           break;
    1486             :         switch (Mnemonic[6]) {
    1487             :         default: break;
    1488             :         case 'f':        // 1 string to match.
    1489           0 :           if (memcmp(Mnemonic.data()+7, "lr_i32_f32_e32", 14) != 0)
    1490             :             break;
    1491           0 :           Mnemonic = "v_cvt_flr_i32_f32";      // "v_cvt_flr_i32_f32_e32"
    1492           0 :           return;
    1493             :         case 'r':        // 1 string to match.
    1494           0 :           if (memcmp(Mnemonic.data()+7, "pi_i32_f32_e32", 14) != 0)
    1495             :             break;
    1496           0 :           Mnemonic = "v_cvt_rpi_i32_f32";      // "v_cvt_rpi_i32_f32_e32"
    1497           0 :           return;
    1498             :         }
    1499             :         break;
    1500             :       case 22:   // 4 strings to match.
    1501         994 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    1502             :           break;
    1503             :         switch (Mnemonic[2]) {
    1504             :         default: break;
    1505             :         case 'c':        // 2 strings to match.
    1506           0 :           if (memcmp(Mnemonic.data()+3, "vt_norm_", 8) != 0)
    1507             :             break;
    1508             :           switch (Mnemonic[11]) {
    1509             :           default: break;
    1510             :           case 'i':      // 1 string to match.
    1511           0 :             if (memcmp(Mnemonic.data()+12, "16_f16_e32", 10) != 0)
    1512             :               break;
    1513           0 :             Mnemonic = "v_cvt_norm_i16_f16";   // "v_cvt_norm_i16_f16_e32"
    1514           0 :             return;
    1515             :           case 'u':      // 1 string to match.
    1516           0 :             if (memcmp(Mnemonic.data()+12, "16_f16_e32", 10) != 0)
    1517             :               break;
    1518           0 :             Mnemonic = "v_cvt_norm_u16_f16";   // "v_cvt_norm_u16_f16_e32"
    1519           0 :             return;
    1520             :           }
    1521             :           break;
    1522             :         case 'm':        // 2 strings to match.
    1523           0 :           if (memcmp(Mnemonic.data()+3, "bcnt_", 5) != 0)
    1524             :             break;
    1525             :           switch (Mnemonic[8]) {
    1526             :           default: break;
    1527             :           case 'h':      // 1 string to match.
    1528           0 :             if (memcmp(Mnemonic.data()+9, "i_u32_b32_e32", 13) != 0)
    1529             :               break;
    1530           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_mbcnt_hi_u32_b32_e32"
    1531           0 :               Mnemonic = "v_mbcnt_hi_u32_b32";
    1532             :             return;
    1533             :           case 'l':      // 1 string to match.
    1534           0 :             if (memcmp(Mnemonic.data()+9, "o_u32_b32_e32", 13) != 0)
    1535             :               break;
    1536           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_mbcnt_lo_u32_b32_e32"
    1537           0 :               Mnemonic = "v_mbcnt_lo_u32_b32";
    1538             :             return;
    1539             :           }
    1540             :           break;
    1541             :         }
    1542             :         break;
    1543             :       case 23:   // 4 strings to match.
    1544         301 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    1545             :           break;
    1546             :         switch (Mnemonic[2]) {
    1547             :         default: break;
    1548             :         case 'c':        // 1 string to match.
    1549           0 :           if (memcmp(Mnemonic.data()+3, "vt_pkrtz_f16_f32_e32", 20) != 0)
    1550             :             break;
    1551           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_cvt_pkrtz_f16_f32_e32"
    1552           0 :             Mnemonic = "v_cvt_pkrtz_f16_f32";
    1553             :           return;
    1554             :         case 'f':        // 3 strings to match.
    1555           0 :           if (memcmp(Mnemonic.data()+3, "rexp_exp_i", 10) != 0)
    1556             :             break;
    1557             :           switch (Mnemonic[13]) {
    1558             :           default: break;
    1559             :           case '1':      // 1 string to match.
    1560           0 :             if (memcmp(Mnemonic.data()+14, "6_f16_e32", 9) != 0)
    1561             :               break;
    1562           0 :             Mnemonic = "v_frexp_exp_i16_f16";  // "v_frexp_exp_i16_f16_e32"
    1563           0 :             return;
    1564             :           case '3':      // 2 strings to match.
    1565           0 :             if (memcmp(Mnemonic.data()+14, "2_f", 3) != 0)
    1566             :               break;
    1567             :             switch (Mnemonic[17]) {
    1568             :             default: break;
    1569             :             case '3':    // 1 string to match.
    1570           0 :               if (memcmp(Mnemonic.data()+18, "2_e32", 5) != 0)
    1571             :                 break;
    1572           0 :               Mnemonic = "v_frexp_exp_i32_f32";        // "v_frexp_exp_i32_f32_e32"
    1573           0 :               return;
    1574             :             case '6':    // 1 string to match.
    1575           0 :               if (memcmp(Mnemonic.data()+18, "4_e32", 5) != 0)
    1576             :                 break;
    1577           0 :               Mnemonic = "v_frexp_exp_i32_f64";        // "v_frexp_exp_i32_f64_e32"
    1578           0 :               return;
    1579             :             }
    1580             :             break;
    1581             :           }
    1582             :           break;
    1583             :         }
    1584             :         break;
    1585             :       case 24:   // 3 strings to match.
    1586         409 :         if (memcmp(Mnemonic.data()+0, "v_cvt_pk", 8) != 0)
    1587             :           break;
    1588             :         switch (Mnemonic[8]) {
    1589             :         default: break;
    1590             :         case 'a':        // 1 string to match.
    1591           0 :           if (memcmp(Mnemonic.data()+9, "ccum_u8_f32_e32", 15) != 0)
    1592             :             break;
    1593           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_cvt_pkaccum_u8_f32_e32"
    1594           0 :             Mnemonic = "v_cvt_pkaccum_u8_f32";
    1595             :           return;
    1596             :         case 'n':        // 2 strings to match.
    1597           0 :           if (memcmp(Mnemonic.data()+9, "orm_", 4) != 0)
    1598             :             break;
    1599             :           switch (Mnemonic[13]) {
    1600             :           default: break;
    1601             :           case 'i':      // 1 string to match.
    1602           0 :             if (memcmp(Mnemonic.data()+14, "16_f32_e32", 10) != 0)
    1603             :               break;
    1604           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_cvt_pknorm_i16_f32_e32"
    1605           0 :               Mnemonic = "v_cvt_pknorm_i16_f32";
    1606             :             return;
    1607             :           case 'u':      // 1 string to match.
    1608           0 :             if (memcmp(Mnemonic.data()+14, "16_f32_e32", 10) != 0)
    1609             :               break;
    1610           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_cvt_pknorm_u16_f32_e32"
    1611           0 :               Mnemonic = "v_cvt_pknorm_u16_f32";
    1612             :             return;
    1613             :           }
    1614             :           break;
    1615             :         }
    1616             :         break;
    1617             :       case 30:   // 1 string to match.
    1618           0 :         if (memcmp(Mnemonic.data()+0, "v_screen_partition_4se_b32_e32", 30) != 0)
    1619             :           break;
    1620           0 :         Mnemonic = "v_screen_partition_4se_b32";       // "v_screen_partition_4se_b32_e32"
    1621           0 :         return;
    1622             :       }
    1623             :     break;
    1624             :     case 1:
    1625             :       switch (Mnemonic.size()) {
    1626             :       default: break;
    1627             :       case 9:    // 1 string to match.
    1628       10282 :         if (memcmp(Mnemonic.data()+0, "v_nop_e64", 9) != 0)
    1629             :           break;
    1630           0 :         Mnemonic = "v_nop";    // "v_nop_e64"
    1631           0 :         return;
    1632             :       case 12:   // 2 strings to match.
    1633       14357 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    1634             :           break;
    1635             :         switch (Mnemonic[2]) {
    1636             :         default: break;
    1637             :         case 'o':        // 1 string to match.
    1638           0 :           if (memcmp(Mnemonic.data()+3, "r_b32_e64", 9) != 0)
    1639             :             break;
    1640           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_or_b32_e64"
    1641           0 :             Mnemonic = "v_or_b32";
    1642             :           return;
    1643             :         case 's':        // 1 string to match.
    1644         708 :           if (memcmp(Mnemonic.data()+3, "ad_u8_e64", 9) != 0)
    1645             :             break;
    1646           0 :           Mnemonic = "v_sad_u8";       // "v_sad_u8_e64"
    1647           0 :           return;
    1648             :         }
    1649             :         break;
    1650             :       case 13:   // 68 strings to match.
    1651       16254 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    1652             :           break;
    1653             :         switch (Mnemonic[2]) {
    1654             :         default: break;
    1655         393 :         case 'a':        // 8 strings to match.
    1656             :           switch (Mnemonic[3]) {
    1657             :           default: break;
    1658             :           case 'd':      // 7 strings to match.
    1659          42 :             if (memcmp(Mnemonic.data()+4, "d_", 2) != 0)
    1660             :               break;
    1661             :             switch (Mnemonic[6]) {
    1662             :             default: break;
    1663           0 :             case 'f':    // 3 strings to match.
    1664             :               switch (Mnemonic[7]) {
    1665             :               default: break;
    1666             :               case '1':  // 1 string to match.
    1667           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1668             :                   break;
    1669           0 :                 Mnemonic = "v_add_f16";        // "v_add_f16_e64"
    1670           0 :                 return;
    1671             :               case '3':  // 1 string to match.
    1672           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1673             :                   break;
    1674           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_add_f32_e64"
    1675           0 :                   Mnemonic = "v_add_f32";
    1676             :                 return;
    1677             :               case '6':  // 1 string to match.
    1678           0 :                 if (memcmp(Mnemonic.data()+8, "4_e64", 5) != 0)
    1679             :                   break;
    1680           0 :                 Mnemonic = "v_add_f64";        // "v_add_f64_e64"
    1681           0 :                 return;
    1682             :               }
    1683             :               break;
    1684           0 :             case 'i':    // 2 strings to match.
    1685             :               switch (Mnemonic[7]) {
    1686             :               default: break;
    1687             :               case '1':  // 1 string to match.
    1688           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1689             :                   break;
    1690           0 :                 Mnemonic = "v_add_i16";        // "v_add_i16_e64"
    1691           0 :                 return;
    1692             :               case '3':  // 1 string to match.
    1693           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1694             :                   break;
    1695           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_add_i32_e64"
    1696           0 :                   Mnemonic = "v_add_i32";
    1697             :                 return;
    1698             :               }
    1699             :               break;
    1700           0 :             case 'u':    // 2 strings to match.
    1701             :               switch (Mnemonic[7]) {
    1702             :               default: break;
    1703             :               case '1':  // 1 string to match.
    1704           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1705             :                   break;
    1706           0 :                 Mnemonic = "v_add_u16";        // "v_add_u16_e64"
    1707           0 :                 return;
    1708             :               case '3':  // 1 string to match.
    1709           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1710             :                   break;
    1711           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_add_u32_e64"
    1712           0 :                   Mnemonic = "v_add_u32";
    1713             :                 return;
    1714             :               }
    1715             :               break;
    1716             :             }
    1717             :             break;
    1718             :           case 'n':      // 1 string to match.
    1719           0 :             if (memcmp(Mnemonic.data()+4, "d_b32_e64", 9) != 0)
    1720             :               break;
    1721           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_and_b32_e64"
    1722           0 :               Mnemonic = "v_and_b32";
    1723             :             return;
    1724             :           }
    1725             :           break;
    1726           0 :         case 'b':        // 4 strings to match.
    1727           0 :           if (Mnemonic[3] != 'f')
    1728             :             break;
    1729             :           switch (Mnemonic[4]) {
    1730             :           default: break;
    1731           0 :           case 'e':      // 2 strings to match.
    1732           0 :             if (Mnemonic[5] != '_')
    1733             :               break;
    1734             :             switch (Mnemonic[6]) {
    1735             :             default: break;
    1736             :             case 'i':    // 1 string to match.
    1737           0 :               if (memcmp(Mnemonic.data()+7, "32_e64", 6) != 0)
    1738             :                 break;
    1739           0 :               Mnemonic = "v_bfe_i32";  // "v_bfe_i32_e64"
    1740           0 :               return;
    1741             :             case 'u':    // 1 string to match.
    1742           0 :               if (memcmp(Mnemonic.data()+7, "32_e64", 6) != 0)
    1743             :                 break;
    1744           0 :               Mnemonic = "v_bfe_u32";  // "v_bfe_u32_e64"
    1745           0 :               return;
    1746             :             }
    1747             :             break;
    1748             :           case 'i':      // 1 string to match.
    1749           0 :             if (memcmp(Mnemonic.data()+5, "_b32_e64", 8) != 0)
    1750             :               break;
    1751           0 :             Mnemonic = "v_bfi_b32";    // "v_bfi_b32_e64"
    1752           0 :             return;
    1753             :           case 'm':      // 1 string to match.
    1754           0 :             if (memcmp(Mnemonic.data()+5, "_b32_e64", 8) != 0)
    1755             :               break;
    1756           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_bfm_b32_e64"
    1757           0 :               Mnemonic = "v_bfm_b32";
    1758             :             return;
    1759             :           }
    1760             :           break;
    1761       12931 :         case 'c':        // 3 strings to match.
    1762             :           switch (Mnemonic[3]) {
    1763             :           default: break;
    1764             :           case 'l':      // 1 string to match.
    1765           0 :             if (memcmp(Mnemonic.data()+4, "rexcp_e64", 9) != 0)
    1766             :               break;
    1767           0 :             Mnemonic = "v_clrexcp";    // "v_clrexcp_e64"
    1768           0 :             return;
    1769             :           case 'o':      // 2 strings to match.
    1770           0 :             if (memcmp(Mnemonic.data()+4, "s_f", 3) != 0)
    1771             :               break;
    1772             :             switch (Mnemonic[7]) {
    1773             :             default: break;
    1774             :             case '1':    // 1 string to match.
    1775           0 :               if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1776             :                 break;
    1777           0 :               Mnemonic = "v_cos_f16";  // "v_cos_f16_e64"
    1778           0 :               return;
    1779             :             case '3':    // 1 string to match.
    1780           0 :               if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1781             :                 break;
    1782           0 :               Mnemonic = "v_cos_f32";  // "v_cos_f32_e64"
    1783           0 :               return;
    1784             :             }
    1785             :             break;
    1786             :           }
    1787             :           break;
    1788             :         case 'e':        // 2 strings to match.
    1789           0 :           if (memcmp(Mnemonic.data()+3, "xp_f", 4) != 0)
    1790             :             break;
    1791             :           switch (Mnemonic[7]) {
    1792             :           default: break;
    1793             :           case '1':      // 1 string to match.
    1794           0 :             if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1795             :               break;
    1796           0 :             Mnemonic = "v_exp_f16";    // "v_exp_f16_e64"
    1797           0 :             return;
    1798             :           case '3':      // 1 string to match.
    1799           0 :             if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1800             :               break;
    1801           0 :             Mnemonic = "v_exp_f32";    // "v_exp_f32_e64"
    1802           0 :             return;
    1803             :           }
    1804             :           break;
    1805             :         case 'f':        // 3 strings to match.
    1806          51 :           if (memcmp(Mnemonic.data()+3, "ma_f", 4) != 0)
    1807             :             break;
    1808             :           switch (Mnemonic[7]) {
    1809             :           default: break;
    1810             :           case '1':      // 1 string to match.
    1811           0 :             if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1812             :               break;
    1813           0 :             Mnemonic = "v_fma_f16";    // "v_fma_f16_e64"
    1814           0 :             return;
    1815             :           case '3':      // 1 string to match.
    1816           0 :             if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1817             :               break;
    1818           0 :             Mnemonic = "v_fma_f32";    // "v_fma_f32_e64"
    1819           0 :             return;
    1820             :           case '6':      // 1 string to match.
    1821           0 :             if (memcmp(Mnemonic.data()+8, "4_e64", 5) != 0)
    1822             :               break;
    1823           0 :             Mnemonic = "v_fma_f64";    // "v_fma_f64_e64"
    1824           0 :             return;
    1825             :           }
    1826             :           break;
    1827         795 :         case 'l':        // 3 strings to match.
    1828             :           switch (Mnemonic[3]) {
    1829             :           default: break;
    1830             :           case 'e':      // 1 string to match.
    1831           0 :             if (memcmp(Mnemonic.data()+4, "rp_u8_e64", 9) != 0)
    1832             :               break;
    1833           0 :             Mnemonic = "v_lerp_u8";    // "v_lerp_u8_e64"
    1834           0 :             return;
    1835             :           case 'o':      // 2 strings to match.
    1836           0 :             if (memcmp(Mnemonic.data()+4, "g_f", 3) != 0)
    1837             :               break;
    1838             :             switch (Mnemonic[7]) {
    1839             :             default: break;
    1840             :             case '1':    // 1 string to match.
    1841           0 :               if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1842             :                 break;
    1843           0 :               Mnemonic = "v_log_f16";  // "v_log_f16_e64"
    1844           0 :               return;
    1845             :             case '3':    // 1 string to match.
    1846           0 :               if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1847             :                 break;
    1848           0 :               Mnemonic = "v_log_f32";  // "v_log_f32_e64"
    1849           0 :               return;
    1850             :             }
    1851             :             break;
    1852             :           }
    1853             :           break;
    1854        1740 :         case 'm':        // 25 strings to match.
    1855             :           switch (Mnemonic[3]) {
    1856             :           default: break;
    1857        1258 :           case 'a':      // 13 strings to match.
    1858             :             switch (Mnemonic[4]) {
    1859             :             default: break;
    1860             :             case 'c':    // 2 strings to match.
    1861           0 :               if (memcmp(Mnemonic.data()+5, "_f", 2) != 0)
    1862             :                 break;
    1863             :               switch (Mnemonic[7]) {
    1864             :               default: break;
    1865             :               case '1':  // 1 string to match.
    1866           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1867             :                   break;
    1868           0 :                 Mnemonic = "v_mac_f16";        // "v_mac_f16_e64"
    1869           0 :                 return;
    1870             :               case '3':  // 1 string to match.
    1871           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1872             :                   break;
    1873           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mac_f32_e64"
    1874           0 :                   Mnemonic = "v_mac_f32";
    1875             :                 return;
    1876             :               }
    1877             :               break;
    1878        1258 :             case 'd':    // 4 strings to match.
    1879        1258 :               if (Mnemonic[5] != '_')
    1880             :                 break;
    1881             :               switch (Mnemonic[6]) {
    1882             :               default: break;
    1883           0 :               case 'f':  // 2 strings to match.
    1884             :                 switch (Mnemonic[7]) {
    1885             :                 default: break;
    1886             :                 case '1':        // 1 string to match.
    1887           0 :                   if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1888             :                     break;
    1889           0 :                   Mnemonic = "v_mad_f16";      // "v_mad_f16_e64"
    1890           0 :                   return;
    1891             :                 case '3':        // 1 string to match.
    1892           0 :                   if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1893             :                     break;
    1894           0 :                   Mnemonic = "v_mad_f32";      // "v_mad_f32_e64"
    1895           0 :                   return;
    1896             :                 }
    1897             :                 break;
    1898             :               case 'i':  // 1 string to match.
    1899         543 :                 if (memcmp(Mnemonic.data()+7, "16_e64", 6) != 0)
    1900             :                   break;
    1901           0 :                 Mnemonic = "v_mad_i16";        // "v_mad_i16_e64"
    1902           0 :                 return;
    1903             :               case 'u':  // 1 string to match.
    1904         547 :                 if (memcmp(Mnemonic.data()+7, "16_e64", 6) != 0)
    1905             :                   break;
    1906           0 :                 Mnemonic = "v_mad_u16";        // "v_mad_u16_e64"
    1907           0 :                 return;
    1908             :               }
    1909             :               break;
    1910           0 :             case 'x':    // 7 strings to match.
    1911           0 :               if (Mnemonic[5] != '_')
    1912             :                 break;
    1913             :               switch (Mnemonic[6]) {
    1914             :               default: break;
    1915           0 :               case 'f':  // 3 strings to match.
    1916             :                 switch (Mnemonic[7]) {
    1917             :                 default: break;
    1918             :                 case '1':        // 1 string to match.
    1919           0 :                   if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1920             :                     break;
    1921           0 :                   Mnemonic = "v_max_f16";      // "v_max_f16_e64"
    1922           0 :                   return;
    1923             :                 case '3':        // 1 string to match.
    1924           0 :                   if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1925             :                     break;
    1926           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_f32_e64"
    1927           0 :                     Mnemonic = "v_max_f32";
    1928             :                   return;
    1929             :                 case '6':        // 1 string to match.
    1930           0 :                   if (memcmp(Mnemonic.data()+8, "4_e64", 5) != 0)
    1931             :                     break;
    1932           0 :                   Mnemonic = "v_max_f64";      // "v_max_f64_e64"
    1933           0 :                   return;
    1934             :                 }
    1935             :                 break;
    1936           0 :               case 'i':  // 2 strings to match.
    1937             :                 switch (Mnemonic[7]) {
    1938             :                 default: break;
    1939             :                 case '1':        // 1 string to match.
    1940           0 :                   if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1941             :                     break;
    1942           0 :                   Mnemonic = "v_max_i16";      // "v_max_i16_e64"
    1943           0 :                   return;
    1944             :                 case '3':        // 1 string to match.
    1945           0 :                   if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1946             :                     break;
    1947           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_i32_e64"
    1948           0 :                     Mnemonic = "v_max_i32";
    1949             :                   return;
    1950             :                 }
    1951             :                 break;
    1952           0 :               case 'u':  // 2 strings to match.
    1953             :                 switch (Mnemonic[7]) {
    1954             :                 default: break;
    1955             :                 case '1':        // 1 string to match.
    1956           0 :                   if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1957             :                     break;
    1958           0 :                   Mnemonic = "v_max_u16";      // "v_max_u16_e64"
    1959           0 :                   return;
    1960             :                 case '3':        // 1 string to match.
    1961           0 :                   if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1962             :                     break;
    1963           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_u32_e64"
    1964           0 :                     Mnemonic = "v_max_u32";
    1965             :                   return;
    1966             :                 }
    1967             :                 break;
    1968             :               }
    1969             :               break;
    1970             :             }
    1971             :             break;
    1972             :           case 'i':      // 7 strings to match.
    1973           0 :             if (memcmp(Mnemonic.data()+4, "n_", 2) != 0)
    1974             :               break;
    1975             :             switch (Mnemonic[6]) {
    1976             :             default: break;
    1977           0 :             case 'f':    // 3 strings to match.
    1978             :               switch (Mnemonic[7]) {
    1979             :               default: break;
    1980             :               case '1':  // 1 string to match.
    1981           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    1982             :                   break;
    1983           0 :                 Mnemonic = "v_min_f16";        // "v_min_f16_e64"
    1984           0 :                 return;
    1985             :               case '3':  // 1 string to match.
    1986           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    1987             :                   break;
    1988           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_f32_e64"
    1989           0 :                   Mnemonic = "v_min_f32";
    1990             :                 return;
    1991             :               case '6':  // 1 string to match.
    1992           0 :                 if (memcmp(Mnemonic.data()+8, "4_e64", 5) != 0)
    1993             :                   break;
    1994           0 :                 Mnemonic = "v_min_f64";        // "v_min_f64_e64"
    1995           0 :                 return;
    1996             :               }
    1997             :               break;
    1998           0 :             case 'i':    // 2 strings to match.
    1999             :               switch (Mnemonic[7]) {
    2000             :               default: break;
    2001             :               case '1':  // 1 string to match.
    2002           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2003             :                   break;
    2004           0 :                 Mnemonic = "v_min_i16";        // "v_min_i16_e64"
    2005           0 :                 return;
    2006             :               case '3':  // 1 string to match.
    2007           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2008             :                   break;
    2009           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_i32_e64"
    2010           0 :                   Mnemonic = "v_min_i32";
    2011             :                 return;
    2012             :               }
    2013             :               break;
    2014           0 :             case 'u':    // 2 strings to match.
    2015             :               switch (Mnemonic[7]) {
    2016             :               default: break;
    2017             :               case '1':  // 1 string to match.
    2018           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2019             :                   break;
    2020           0 :                 Mnemonic = "v_min_u16";        // "v_min_u16_e64"
    2021           0 :                 return;
    2022             :               case '3':  // 1 string to match.
    2023           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2024             :                   break;
    2025           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_u32_e64"
    2026           0 :                   Mnemonic = "v_min_u32";
    2027             :                 return;
    2028             :               }
    2029             :               break;
    2030             :             }
    2031             :             break;
    2032             :           case 'o':      // 1 string to match.
    2033         102 :             if (memcmp(Mnemonic.data()+4, "v_b32_e64", 9) != 0)
    2034             :               break;
    2035           0 :             Mnemonic = "v_mov_b32";    // "v_mov_b32_e64"
    2036           0 :             return;
    2037             :           case 's':      // 1 string to match.
    2038           0 :             if (memcmp(Mnemonic.data()+4, "ad_u8_e64", 9) != 0)
    2039             :               break;
    2040           0 :             Mnemonic = "v_msad_u8";    // "v_msad_u8_e64"
    2041           0 :             return;
    2042             :           case 'u':      // 3 strings to match.
    2043         380 :             if (memcmp(Mnemonic.data()+4, "l_f", 3) != 0)
    2044             :               break;
    2045             :             switch (Mnemonic[7]) {
    2046             :             default: break;
    2047             :             case '1':    // 1 string to match.
    2048           0 :               if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2049             :                 break;
    2050           0 :               Mnemonic = "v_mul_f16";  // "v_mul_f16_e64"
    2051           0 :               return;
    2052             :             case '3':    // 1 string to match.
    2053           0 :               if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2054             :                 break;
    2055           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_f32_e64"
    2056           0 :                 Mnemonic = "v_mul_f32";
    2057             :               return;
    2058             :             case '6':    // 1 string to match.
    2059           0 :               if (memcmp(Mnemonic.data()+8, "4_e64", 5) != 0)
    2060             :                 break;
    2061           0 :               Mnemonic = "v_mul_f64";  // "v_mul_f64_e64"
    2062           0 :               return;
    2063             :             }
    2064             :             break;
    2065             :           }
    2066             :           break;
    2067             :         case 'n':        // 1 string to match.
    2068           0 :           if (memcmp(Mnemonic.data()+3, "ot_b32_e64", 10) != 0)
    2069             :             break;
    2070           0 :           Mnemonic = "v_not_b32";      // "v_not_b32_e64"
    2071           0 :           return;
    2072             :         case 'o':        // 1 string to match.
    2073           0 :           if (memcmp(Mnemonic.data()+3, "r3_b32_e64", 10) != 0)
    2074             :             break;
    2075           0 :           Mnemonic = "v_or3_b32";      // "v_or3_b32_e64"
    2076           0 :           return;
    2077           0 :         case 'r':        // 6 strings to match.
    2078             :           switch (Mnemonic[3]) {
    2079             :           default: break;
    2080             :           case 'c':      // 3 strings to match.
    2081           0 :             if (memcmp(Mnemonic.data()+4, "p_f", 3) != 0)
    2082             :               break;
    2083             :             switch (Mnemonic[7]) {
    2084             :             default: break;
    2085             :             case '1':    // 1 string to match.
    2086           0 :               if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2087             :                 break;
    2088           0 :               Mnemonic = "v_rcp_f16";  // "v_rcp_f16_e64"
    2089           0 :               return;
    2090             :             case '3':    // 1 string to match.
    2091           0 :               if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2092             :                 break;
    2093           0 :               Mnemonic = "v_rcp_f32";  // "v_rcp_f32_e64"
    2094           0 :               return;
    2095             :             case '6':    // 1 string to match.
    2096           0 :               if (memcmp(Mnemonic.data()+8, "4_e64", 5) != 0)
    2097             :                 break;
    2098           0 :               Mnemonic = "v_rcp_f64";  // "v_rcp_f64_e64"
    2099           0 :               return;
    2100             :             }
    2101             :             break;
    2102             :           case 's':      // 3 strings to match.
    2103           0 :             if (memcmp(Mnemonic.data()+4, "q_f", 3) != 0)
    2104             :               break;
    2105             :             switch (Mnemonic[7]) {
    2106             :             default: break;
    2107             :             case '1':    // 1 string to match.
    2108           0 :               if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2109             :                 break;
    2110           0 :               Mnemonic = "v_rsq_f16";  // "v_rsq_f16_e64"
    2111           0 :               return;
    2112             :             case '3':    // 1 string to match.
    2113           0 :               if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2114             :                 break;
    2115           0 :               Mnemonic = "v_rsq_f32";  // "v_rsq_f32_e64"
    2116           0 :               return;
    2117             :             case '6':    // 1 string to match.
    2118           0 :               if (memcmp(Mnemonic.data()+8, "4_e64", 5) != 0)
    2119             :                 break;
    2120           0 :               Mnemonic = "v_rsq_f64";  // "v_rsq_f64_e64"
    2121           0 :               return;
    2122             :             }
    2123             :             break;
    2124             :           }
    2125             :           break;
    2126         104 :         case 's':        // 10 strings to match.
    2127             :           switch (Mnemonic[3]) {
    2128             :           default: break;
    2129             :           case 'a':      // 2 strings to match.
    2130           0 :             if (memcmp(Mnemonic.data()+4, "d_u", 3) != 0)
    2131             :               break;
    2132             :             switch (Mnemonic[7]) {
    2133             :             default: break;
    2134             :             case '1':    // 1 string to match.
    2135           0 :               if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2136             :                 break;
    2137           0 :               Mnemonic = "v_sad_u16";  // "v_sad_u16_e64"
    2138           0 :               return;
    2139             :             case '3':    // 1 string to match.
    2140           0 :               if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2141             :                 break;
    2142           0 :               Mnemonic = "v_sad_u32";  // "v_sad_u32_e64"
    2143           0 :               return;
    2144             :             }
    2145             :             break;
    2146             :           case 'i':      // 2 strings to match.
    2147           0 :             if (memcmp(Mnemonic.data()+4, "n_f", 3) != 0)
    2148             :               break;
    2149             :             switch (Mnemonic[7]) {
    2150             :             default: break;
    2151             :             case '1':    // 1 string to match.
    2152           0 :               if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2153             :                 break;
    2154           0 :               Mnemonic = "v_sin_f16";  // "v_sin_f16_e64"
    2155           0 :               return;
    2156             :             case '3':    // 1 string to match.
    2157           0 :               if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2158             :                 break;
    2159           0 :               Mnemonic = "v_sin_f32";  // "v_sin_f32_e64"
    2160           0 :               return;
    2161             :             }
    2162             :             break;
    2163             :           case 'u':      // 6 strings to match.
    2164         104 :             if (memcmp(Mnemonic.data()+4, "b_", 2) != 0)
    2165             :               break;
    2166             :             switch (Mnemonic[6]) {
    2167             :             default: break;
    2168           0 :             case 'f':    // 2 strings to match.
    2169             :               switch (Mnemonic[7]) {
    2170             :               default: break;
    2171             :               case '1':  // 1 string to match.
    2172           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2173             :                   break;
    2174           0 :                 Mnemonic = "v_sub_f16";        // "v_sub_f16_e64"
    2175           0 :                 return;
    2176             :               case '3':  // 1 string to match.
    2177           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2178             :                   break;
    2179           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_sub_f32_e64"
    2180           0 :                   Mnemonic = "v_sub_f32";
    2181             :                 return;
    2182             :               }
    2183             :               break;
    2184           0 :             case 'i':    // 2 strings to match.
    2185             :               switch (Mnemonic[7]) {
    2186             :               default: break;
    2187             :               case '1':  // 1 string to match.
    2188           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2189             :                   break;
    2190           0 :                 Mnemonic = "v_sub_i16";        // "v_sub_i16_e64"
    2191           0 :                 return;
    2192             :               case '3':  // 1 string to match.
    2193           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2194             :                   break;
    2195           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_sub_i32_e64"
    2196           0 :                   Mnemonic = "v_sub_i32";
    2197             :                 return;
    2198             :               }
    2199             :               break;
    2200           0 :             case 'u':    // 2 strings to match.
    2201             :               switch (Mnemonic[7]) {
    2202             :               default: break;
    2203             :               case '1':  // 1 string to match.
    2204           0 :                 if (memcmp(Mnemonic.data()+8, "6_e64", 5) != 0)
    2205             :                   break;
    2206           0 :                 Mnemonic = "v_sub_u16";        // "v_sub_u16_e64"
    2207           0 :                 return;
    2208             :               case '3':  // 1 string to match.
    2209           0 :                 if (memcmp(Mnemonic.data()+8, "2_e64", 5) != 0)
    2210             :                   break;
    2211           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_sub_u32_e64"
    2212           0 :                   Mnemonic = "v_sub_u32";
    2213             :                 return;
    2214             :               }
    2215             :               break;
    2216             :             }
    2217             :             break;
    2218             :           }
    2219             :           break;
    2220           0 :         case 'x':        // 2 strings to match.
    2221             :           switch (Mnemonic[3]) {
    2222             :           default: break;
    2223             :           case 'a':      // 1 string to match.
    2224           0 :             if (memcmp(Mnemonic.data()+4, "d_u32_e64", 9) != 0)
    2225             :               break;
    2226           0 :             Mnemonic = "v_xad_u32";    // "v_xad_u32_e64"
    2227           0 :             return;
    2228             :           case 'o':      // 1 string to match.
    2229           0 :             if (memcmp(Mnemonic.data()+4, "r_b32_e64", 9) != 0)
    2230             :               break;
    2231           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_xor_b32_e64"
    2232           0 :               Mnemonic = "v_xor_b32";
    2233             :             return;
    2234             :           }
    2235             :           break;
    2236             :         }
    2237             :         break;
    2238             :       case 14:   // 39 strings to match.
    2239        5597 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    2240             :           break;
    2241             :         switch (Mnemonic[2]) {
    2242             :         default: break;
    2243         274 :         case 'a':        // 4 strings to match.
    2244             :           switch (Mnemonic[3]) {
    2245             :           default: break;
    2246          92 :           case 'd':      // 2 strings to match.
    2247          92 :             if (Mnemonic[4] != 'd')
    2248             :               break;
    2249             :             switch (Mnemonic[5]) {
    2250             :             default: break;
    2251             :             case '3':    // 1 string to match.
    2252           0 :               if (memcmp(Mnemonic.data()+6, "_u32_e64", 8) != 0)
    2253             :                 break;
    2254           0 :               Mnemonic = "v_add3_u32";         // "v_add3_u32_e64"
    2255           0 :               return;
    2256             :             case 'c':    // 1 string to match.
    2257           0 :               if (memcmp(Mnemonic.data()+6, "_u32_e64", 8) != 0)
    2258             :                 break;
    2259           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_addc_u32_e64"
    2260           0 :                 Mnemonic = "v_addc_u32";
    2261             :               return;
    2262             :             }
    2263             :             break;
    2264             :           case 's':      // 2 strings to match.
    2265           0 :             if (memcmp(Mnemonic.data()+4, "hr_i", 4) != 0)
    2266             :               break;
    2267             :             switch (Mnemonic[8]) {
    2268             :             default: break;
    2269             :             case '3':    // 1 string to match.
    2270           0 :               if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2271             :                 break;
    2272           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_ashr_i32_e64"
    2273           0 :                 Mnemonic = "v_ashr_i32";
    2274             :               return;
    2275             :             case '6':    // 1 string to match.
    2276           0 :               if (memcmp(Mnemonic.data()+9, "4_e64", 5) != 0)
    2277             :                 break;
    2278           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_ashr_i64_e64"
    2279           0 :                 Mnemonic = "v_ashr_i64";
    2280             :               return;
    2281             :             }
    2282             :             break;
    2283             :           }
    2284             :           break;
    2285             :         case 'c':        // 3 strings to match.
    2286        4266 :           if (memcmp(Mnemonic.data()+3, "eil_f", 5) != 0)
    2287             :             break;
    2288             :           switch (Mnemonic[8]) {
    2289             :           default: break;
    2290             :           case '1':      // 1 string to match.
    2291           0 :             if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2292             :               break;
    2293           0 :             Mnemonic = "v_ceil_f16";   // "v_ceil_f16_e64"
    2294           0 :             return;
    2295             :           case '3':      // 1 string to match.
    2296           0 :             if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2297             :               break;
    2298           0 :             Mnemonic = "v_ceil_f32";   // "v_ceil_f32_e64"
    2299           0 :             return;
    2300             :           case '6':      // 1 string to match.
    2301           0 :             if (memcmp(Mnemonic.data()+9, "4_e64", 5) != 0)
    2302             :               break;
    2303           0 :             Mnemonic = "v_ceil_f64";   // "v_ceil_f64_e64"
    2304           0 :             return;
    2305             :           }
    2306             :           break;
    2307           0 :         case 'f':        // 4 strings to match.
    2308             :           switch (Mnemonic[3]) {
    2309             :           default: break;
    2310           0 :           case 'f':      // 3 strings to match.
    2311           0 :             if (Mnemonic[4] != 'b')
    2312             :               break;
    2313             :             switch (Mnemonic[5]) {
    2314             :             default: break;
    2315           0 :             case 'h':    // 2 strings to match.
    2316           0 :               if (Mnemonic[6] != '_')
    2317             :                 break;
    2318             :               switch (Mnemonic[7]) {
    2319             :               default: break;
    2320             :               case 'i':  // 1 string to match.
    2321           0 :                 if (memcmp(Mnemonic.data()+8, "32_e64", 6) != 0)
    2322             :                   break;
    2323           0 :                 Mnemonic = "v_ffbh_i32";       // "v_ffbh_i32_e64"
    2324           0 :                 return;
    2325             :               case 'u':  // 1 string to match.
    2326           0 :                 if (memcmp(Mnemonic.data()+8, "32_e64", 6) != 0)
    2327             :                   break;
    2328           0 :                 Mnemonic = "v_ffbh_u32";       // "v_ffbh_u32_e64"
    2329           0 :                 return;
    2330             :               }
    2331             :               break;
    2332             :             case 'l':    // 1 string to match.
    2333           0 :               if (memcmp(Mnemonic.data()+6, "_b32_e64", 8) != 0)
    2334             :                 break;
    2335           0 :               Mnemonic = "v_ffbl_b32";         // "v_ffbl_b32_e64"
    2336           0 :               return;
    2337             :             }
    2338             :             break;
    2339             :           case 'm':      // 1 string to match.
    2340           0 :             if (memcmp(Mnemonic.data()+4, "ac_f32_e64", 10) != 0)
    2341             :               break;
    2342           0 :             Mnemonic = "v_fmac_f32";   // "v_fmac_f32_e64"
    2343           0 :             return;
    2344             :           }
    2345             :           break;
    2346             :         case 'l':        // 4 strings to match.
    2347          92 :           if (memcmp(Mnemonic.data()+3, "sh", 2) != 0)
    2348             :             break;
    2349             :           switch (Mnemonic[5]) {
    2350             :           default: break;
    2351             :           case 'l':      // 2 strings to match.
    2352          92 :             if (memcmp(Mnemonic.data()+6, "_b", 2) != 0)
    2353             :               break;
    2354             :             switch (Mnemonic[8]) {
    2355             :             default: break;
    2356             :             case '3':    // 1 string to match.
    2357           0 :               if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2358             :                 break;
    2359           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_lshl_b32_e64"
    2360           0 :                 Mnemonic = "v_lshl_b32";
    2361             :               return;
    2362             :             case '6':    // 1 string to match.
    2363           0 :               if (memcmp(Mnemonic.data()+9, "4_e64", 5) != 0)
    2364             :                 break;
    2365           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_lshl_b64_e64"
    2366           0 :                 Mnemonic = "v_lshl_b64";
    2367             :               return;
    2368             :             }
    2369             :             break;
    2370             :           case 'r':      // 2 strings to match.
    2371           0 :             if (memcmp(Mnemonic.data()+6, "_b", 2) != 0)
    2372             :               break;
    2373             :             switch (Mnemonic[8]) {
    2374             :             default: break;
    2375             :             case '3':    // 1 string to match.
    2376           0 :               if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2377             :                 break;
    2378           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_lshr_b32_e64"
    2379           0 :                 Mnemonic = "v_lshr_b32";
    2380             :               return;
    2381             :             case '6':    // 1 string to match.
    2382           0 :               if (memcmp(Mnemonic.data()+9, "4_e64", 5) != 0)
    2383             :                 break;
    2384           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_lshr_b64_e64"
    2385           0 :                 Mnemonic = "v_lshr_b64";
    2386             :               return;
    2387             :             }
    2388             :             break;
    2389             :           }
    2390             :           break;
    2391         133 :         case 'm':        // 18 strings to match.
    2392             :           switch (Mnemonic[3]) {
    2393             :           default: break;
    2394             :           case 'a':      // 6 strings to match.
    2395           0 :             if (memcmp(Mnemonic.data()+4, "x3_", 3) != 0)
    2396             :               break;
    2397             :             switch (Mnemonic[7]) {
    2398             :             default: break;
    2399           0 :             case 'f':    // 2 strings to match.
    2400             :               switch (Mnemonic[8]) {
    2401             :               default: break;
    2402             :               case '1':  // 1 string to match.
    2403           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2404             :                   break;
    2405           0 :                 Mnemonic = "v_max3_f16";       // "v_max3_f16_e64"
    2406           0 :                 return;
    2407             :               case '3':  // 1 string to match.
    2408           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2409             :                   break;
    2410           0 :                 Mnemonic = "v_max3_f32";       // "v_max3_f32_e64"
    2411           0 :                 return;
    2412             :               }
    2413             :               break;
    2414           0 :             case 'i':    // 2 strings to match.
    2415             :               switch (Mnemonic[8]) {
    2416             :               default: break;
    2417             :               case '1':  // 1 string to match.
    2418           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2419             :                   break;
    2420           0 :                 Mnemonic = "v_max3_i16";       // "v_max3_i16_e64"
    2421           0 :                 return;
    2422             :               case '3':  // 1 string to match.
    2423           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2424             :                   break;
    2425           0 :                 Mnemonic = "v_max3_i32";       // "v_max3_i32_e64"
    2426           0 :                 return;
    2427             :               }
    2428             :               break;
    2429           0 :             case 'u':    // 2 strings to match.
    2430             :               switch (Mnemonic[8]) {
    2431             :               default: break;
    2432             :               case '1':  // 1 string to match.
    2433           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2434             :                   break;
    2435           0 :                 Mnemonic = "v_max3_u16";       // "v_max3_u16_e64"
    2436           0 :                 return;
    2437             :               case '3':  // 1 string to match.
    2438           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2439             :                   break;
    2440           0 :                 Mnemonic = "v_max3_u32";       // "v_max3_u32_e64"
    2441           0 :                 return;
    2442             :               }
    2443             :               break;
    2444             :             }
    2445             :             break;
    2446             :           case 'e':      // 6 strings to match.
    2447           0 :             if (memcmp(Mnemonic.data()+4, "d3_", 3) != 0)
    2448             :               break;
    2449             :             switch (Mnemonic[7]) {
    2450             :             default: break;
    2451           0 :             case 'f':    // 2 strings to match.
    2452             :               switch (Mnemonic[8]) {
    2453             :               default: break;
    2454             :               case '1':  // 1 string to match.
    2455           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2456             :                   break;
    2457           0 :                 Mnemonic = "v_med3_f16";       // "v_med3_f16_e64"
    2458           0 :                 return;
    2459             :               case '3':  // 1 string to match.
    2460           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2461             :                   break;
    2462           0 :                 Mnemonic = "v_med3_f32";       // "v_med3_f32_e64"
    2463           0 :                 return;
    2464             :               }
    2465             :               break;
    2466           0 :             case 'i':    // 2 strings to match.
    2467             :               switch (Mnemonic[8]) {
    2468             :               default: break;
    2469             :               case '1':  // 1 string to match.
    2470           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2471             :                   break;
    2472           0 :                 Mnemonic = "v_med3_i16";       // "v_med3_i16_e64"
    2473           0 :                 return;
    2474             :               case '3':  // 1 string to match.
    2475           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2476             :                   break;
    2477           0 :                 Mnemonic = "v_med3_i32";       // "v_med3_i32_e64"
    2478           0 :                 return;
    2479             :               }
    2480             :               break;
    2481           0 :             case 'u':    // 2 strings to match.
    2482             :               switch (Mnemonic[8]) {
    2483             :               default: break;
    2484             :               case '1':  // 1 string to match.
    2485           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2486             :                   break;
    2487           0 :                 Mnemonic = "v_med3_u16";       // "v_med3_u16_e64"
    2488           0 :                 return;
    2489             :               case '3':  // 1 string to match.
    2490           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2491             :                   break;
    2492           0 :                 Mnemonic = "v_med3_u32";       // "v_med3_u32_e64"
    2493           0 :                 return;
    2494             :               }
    2495             :               break;
    2496             :             }
    2497             :             break;
    2498             :           case 'i':      // 6 strings to match.
    2499           0 :             if (memcmp(Mnemonic.data()+4, "n3_", 3) != 0)
    2500             :               break;
    2501             :             switch (Mnemonic[7]) {
    2502             :             default: break;
    2503           0 :             case 'f':    // 2 strings to match.
    2504             :               switch (Mnemonic[8]) {
    2505             :               default: break;
    2506             :               case '1':  // 1 string to match.
    2507           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2508             :                   break;
    2509           0 :                 Mnemonic = "v_min3_f16";       // "v_min3_f16_e64"
    2510           0 :                 return;
    2511             :               case '3':  // 1 string to match.
    2512           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2513             :                   break;
    2514           0 :                 Mnemonic = "v_min3_f32";       // "v_min3_f32_e64"
    2515           0 :                 return;
    2516             :               }
    2517             :               break;
    2518           0 :             case 'i':    // 2 strings to match.
    2519             :               switch (Mnemonic[8]) {
    2520             :               default: break;
    2521             :               case '1':  // 1 string to match.
    2522           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2523             :                   break;
    2524           0 :                 Mnemonic = "v_min3_i16";       // "v_min3_i16_e64"
    2525           0 :                 return;
    2526             :               case '3':  // 1 string to match.
    2527           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2528             :                   break;
    2529           0 :                 Mnemonic = "v_min3_i32";       // "v_min3_i32_e64"
    2530           0 :                 return;
    2531             :               }
    2532             :               break;
    2533           0 :             case 'u':    // 2 strings to match.
    2534             :               switch (Mnemonic[8]) {
    2535             :               default: break;
    2536             :               case '1':  // 1 string to match.
    2537           0 :                 if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2538             :                   break;
    2539           0 :                 Mnemonic = "v_min3_u16";       // "v_min3_u16_e64"
    2540           0 :                 return;
    2541             :               case '3':  // 1 string to match.
    2542           0 :                 if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2543             :                   break;
    2544           0 :                 Mnemonic = "v_min3_u32";       // "v_min3_u32_e64"
    2545           0 :                 return;
    2546             :               }
    2547             :               break;
    2548             :             }
    2549             :             break;
    2550             :           }
    2551             :           break;
    2552             :         case 'p':        // 1 string to match.
    2553          89 :           if (memcmp(Mnemonic.data()+3, "erm_b32_e64", 11) != 0)
    2554             :             break;
    2555           0 :           Mnemonic = "v_perm_b32";     // "v_perm_b32_e64"
    2556           0 :           return;
    2557           0 :         case 's':        // 4 strings to match.
    2558             :           switch (Mnemonic[3]) {
    2559             :           default: break;
    2560             :           case 'q':      // 3 strings to match.
    2561           0 :             if (memcmp(Mnemonic.data()+4, "rt_f", 4) != 0)
    2562             :               break;
    2563             :             switch (Mnemonic[8]) {
    2564             :             default: break;
    2565             :             case '1':    // 1 string to match.
    2566           0 :               if (memcmp(Mnemonic.data()+9, "6_e64", 5) != 0)
    2567             :                 break;
    2568           0 :               Mnemonic = "v_sqrt_f16";         // "v_sqrt_f16_e64"
    2569           0 :               return;
    2570             :             case '3':    // 1 string to match.
    2571           0 :               if (memcmp(Mnemonic.data()+9, "2_e64", 5) != 0)
    2572             :                 break;
    2573           0 :               Mnemonic = "v_sqrt_f32";         // "v_sqrt_f32_e64"
    2574           0 :               return;
    2575             :             case '6':    // 1 string to match.
    2576           0 :               if (memcmp(Mnemonic.data()+9, "4_e64", 5) != 0)
    2577             :                 break;
    2578           0 :               Mnemonic = "v_sqrt_f64";         // "v_sqrt_f64_e64"
    2579           0 :               return;
    2580             :             }
    2581             :             break;
    2582             :           case 'u':      // 1 string to match.
    2583           0 :             if (memcmp(Mnemonic.data()+4, "bb_u32_e64", 10) != 0)
    2584             :               break;
    2585           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_subb_u32_e64"
    2586           0 :               Mnemonic = "v_subb_u32";
    2587             :             return;
    2588             :           }
    2589             :           break;
    2590             :         case 'x':        // 1 string to match.
    2591           0 :           if (memcmp(Mnemonic.data()+3, "nor_b32_e64", 11) != 0)
    2592             :             break;
    2593           0 :           Mnemonic = "v_xnor_b32";     // "v_xnor_b32_e64"
    2594           0 :           return;
    2595             :         }
    2596             :         break;
    2597             :       case 15:   // 38 strings to match.
    2598        3771 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    2599             :           break;
    2600             :         switch (Mnemonic[2]) {
    2601             :         default: break;
    2602             :         case 'b':        // 1 string to match.
    2603           0 :           if (memcmp(Mnemonic.data()+3, "frev_b32_e64", 12) != 0)
    2604             :             break;
    2605           0 :           Mnemonic = "v_bfrev_b32";    // "v_bfrev_b32_e64"
    2606           0 :           return;
    2607             :         case 'c':        // 21 strings to match.
    2608        1271 :           if (memcmp(Mnemonic.data()+3, "mp_", 3) != 0)
    2609             :             break;
    2610             :           switch (Mnemonic[6]) {
    2611             :           default: break;
    2612           0 :           case 'f':      // 9 strings to match.
    2613           0 :             if (Mnemonic[7] != '_')
    2614             :               break;
    2615             :             switch (Mnemonic[8]) {
    2616             :             default: break;
    2617           0 :             case 'f':    // 3 strings to match.
    2618             :               switch (Mnemonic[9]) {
    2619             :               default: break;
    2620             :               case '1':  // 1 string to match.
    2621           0 :                 if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2622             :                   break;
    2623           0 :                 Mnemonic = "v_cmp_f_f16";      // "v_cmp_f_f16_e64"
    2624           0 :                 return;
    2625             :               case '3':  // 1 string to match.
    2626           0 :                 if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2627             :                   break;
    2628           0 :                 Mnemonic = "v_cmp_f_f32";      // "v_cmp_f_f32_e64"
    2629           0 :                 return;
    2630             :               case '6':  // 1 string to match.
    2631           0 :                 if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2632             :                   break;
    2633           0 :                 Mnemonic = "v_cmp_f_f64";      // "v_cmp_f_f64_e64"
    2634           0 :                 return;
    2635             :               }
    2636             :               break;
    2637           0 :             case 'i':    // 3 strings to match.
    2638             :               switch (Mnemonic[9]) {
    2639             :               default: break;
    2640             :               case '1':  // 1 string to match.
    2641           0 :                 if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2642             :                   break;
    2643           0 :                 Mnemonic = "v_cmp_f_i16";      // "v_cmp_f_i16_e64"
    2644           0 :                 return;
    2645             :               case '3':  // 1 string to match.
    2646           0 :                 if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2647             :                   break;
    2648           0 :                 Mnemonic = "v_cmp_f_i32";      // "v_cmp_f_i32_e64"
    2649           0 :                 return;
    2650             :               case '6':  // 1 string to match.
    2651           0 :                 if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2652             :                   break;
    2653           0 :                 Mnemonic = "v_cmp_f_i64";      // "v_cmp_f_i64_e64"
    2654           0 :                 return;
    2655             :               }
    2656             :               break;
    2657           0 :             case 'u':    // 3 strings to match.
    2658             :               switch (Mnemonic[9]) {
    2659             :               default: break;
    2660             :               case '1':  // 1 string to match.
    2661           0 :                 if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2662             :                   break;
    2663           0 :                 Mnemonic = "v_cmp_f_u16";      // "v_cmp_f_u16_e64"
    2664           0 :                 return;
    2665             :               case '3':  // 1 string to match.
    2666           0 :                 if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2667             :                   break;
    2668           0 :                 Mnemonic = "v_cmp_f_u32";      // "v_cmp_f_u32_e64"
    2669           0 :                 return;
    2670             :               case '6':  // 1 string to match.
    2671           0 :                 if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2672             :                   break;
    2673           0 :                 Mnemonic = "v_cmp_f_u64";      // "v_cmp_f_u64_e64"
    2674           0 :                 return;
    2675             :               }
    2676             :               break;
    2677             :             }
    2678             :             break;
    2679             :           case 'o':      // 3 strings to match.
    2680           0 :             if (memcmp(Mnemonic.data()+7, "_f", 2) != 0)
    2681             :               break;
    2682             :             switch (Mnemonic[9]) {
    2683             :             default: break;
    2684             :             case '1':    // 1 string to match.
    2685           0 :               if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2686             :                 break;
    2687           0 :               Mnemonic = "v_cmp_o_f16";        // "v_cmp_o_f16_e64"
    2688           0 :               return;
    2689             :             case '3':    // 1 string to match.
    2690           0 :               if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2691             :                 break;
    2692           0 :               Mnemonic = "v_cmp_o_f32";        // "v_cmp_o_f32_e64"
    2693           0 :               return;
    2694             :             case '6':    // 1 string to match.
    2695           0 :               if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2696             :                 break;
    2697           0 :               Mnemonic = "v_cmp_o_f64";        // "v_cmp_o_f64_e64"
    2698           0 :               return;
    2699             :             }
    2700             :             break;
    2701           0 :           case 't':      // 6 strings to match.
    2702           0 :             if (Mnemonic[7] != '_')
    2703             :               break;
    2704             :             switch (Mnemonic[8]) {
    2705             :             default: break;
    2706           0 :             case 'i':    // 3 strings to match.
    2707             :               switch (Mnemonic[9]) {
    2708             :               default: break;
    2709             :               case '1':  // 1 string to match.
    2710           0 :                 if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2711             :                   break;
    2712           0 :                 Mnemonic = "v_cmp_t_i16";      // "v_cmp_t_i16_e64"
    2713           0 :                 return;
    2714             :               case '3':  // 1 string to match.
    2715           0 :                 if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2716             :                   break;
    2717           0 :                 Mnemonic = "v_cmp_t_i32";      // "v_cmp_t_i32_e64"
    2718           0 :                 return;
    2719             :               case '6':  // 1 string to match.
    2720           0 :                 if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2721             :                   break;
    2722           0 :                 Mnemonic = "v_cmp_t_i64";      // "v_cmp_t_i64_e64"
    2723           0 :                 return;
    2724             :               }
    2725             :               break;
    2726           0 :             case 'u':    // 3 strings to match.
    2727             :               switch (Mnemonic[9]) {
    2728             :               default: break;
    2729             :               case '1':  // 1 string to match.
    2730           0 :                 if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2731             :                   break;
    2732           0 :                 Mnemonic = "v_cmp_t_u16";      // "v_cmp_t_u16_e64"
    2733           0 :                 return;
    2734             :               case '3':  // 1 string to match.
    2735           0 :                 if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2736             :                   break;
    2737           0 :                 Mnemonic = "v_cmp_t_u32";      // "v_cmp_t_u32_e64"
    2738           0 :                 return;
    2739             :               case '6':  // 1 string to match.
    2740           0 :                 if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2741             :                   break;
    2742           0 :                 Mnemonic = "v_cmp_t_u64";      // "v_cmp_t_u64_e64"
    2743           0 :                 return;
    2744             :               }
    2745             :               break;
    2746             :             }
    2747             :             break;
    2748             :           case 'u':      // 3 strings to match.
    2749           0 :             if (memcmp(Mnemonic.data()+7, "_f", 2) != 0)
    2750             :               break;
    2751             :             switch (Mnemonic[9]) {
    2752             :             default: break;
    2753             :             case '1':    // 1 string to match.
    2754           0 :               if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2755             :                 break;
    2756           0 :               Mnemonic = "v_cmp_u_f16";        // "v_cmp_u_f16_e64"
    2757           0 :               return;
    2758             :             case '3':    // 1 string to match.
    2759           0 :               if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2760             :                 break;
    2761           0 :               Mnemonic = "v_cmp_u_f32";        // "v_cmp_u_f32_e64"
    2762           0 :               return;
    2763             :             case '6':    // 1 string to match.
    2764           0 :               if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2765             :                 break;
    2766           0 :               Mnemonic = "v_cmp_u_f64";        // "v_cmp_u_f64_e64"
    2767           0 :               return;
    2768             :             }
    2769             :             break;
    2770             :           }
    2771             :           break;
    2772          22 :         case 'f':        // 6 strings to match.
    2773             :           switch (Mnemonic[3]) {
    2774             :           default: break;
    2775             :           case 'l':      // 3 strings to match.
    2776           0 :             if (memcmp(Mnemonic.data()+4, "oor_f", 5) != 0)
    2777             :               break;
    2778             :             switch (Mnemonic[9]) {
    2779             :             default: break;
    2780             :             case '1':    // 1 string to match.
    2781           0 :               if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2782             :                 break;
    2783           0 :               Mnemonic = "v_floor_f16";        // "v_floor_f16_e64"
    2784           0 :               return;
    2785             :             case '3':    // 1 string to match.
    2786           0 :               if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2787             :                 break;
    2788           0 :               Mnemonic = "v_floor_f32";        // "v_floor_f32_e64"
    2789           0 :               return;
    2790             :             case '6':    // 1 string to match.
    2791           0 :               if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2792             :                 break;
    2793           0 :               Mnemonic = "v_floor_f64";        // "v_floor_f64_e64"
    2794           0 :               return;
    2795             :             }
    2796             :             break;
    2797             :           case 'r':      // 3 strings to match.
    2798           0 :             if (memcmp(Mnemonic.data()+4, "act_f", 5) != 0)
    2799             :               break;
    2800             :             switch (Mnemonic[9]) {
    2801             :             default: break;
    2802             :             case '1':    // 1 string to match.
    2803           0 :               if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2804             :                 break;
    2805           0 :               Mnemonic = "v_fract_f16";        // "v_fract_f16_e64"
    2806           0 :               return;
    2807             :             case '3':    // 1 string to match.
    2808           0 :               if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2809             :                 break;
    2810           0 :               Mnemonic = "v_fract_f32";        // "v_fract_f32_e64"
    2811           0 :               return;
    2812             :             case '6':    // 1 string to match.
    2813           0 :               if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2814             :                 break;
    2815           0 :               Mnemonic = "v_fract_f64";        // "v_fract_f64_e64"
    2816           0 :               return;
    2817             :             }
    2818             :             break;
    2819             :           }
    2820             :           break;
    2821             :         case 'l':        // 3 strings to match.
    2822          29 :           if (memcmp(Mnemonic.data()+3, "dexp_f", 6) != 0)
    2823             :             break;
    2824             :           switch (Mnemonic[9]) {
    2825             :           default: break;
    2826             :           case '1':      // 1 string to match.
    2827           0 :             if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2828             :               break;
    2829           0 :             Mnemonic = "v_ldexp_f16";  // "v_ldexp_f16_e64"
    2830           0 :             return;
    2831             :           case '3':      // 1 string to match.
    2832           0 :             if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2833             :               break;
    2834           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_ldexp_f32_e64"
    2835           0 :               Mnemonic = "v_ldexp_f32";
    2836             :             return;
    2837             :           case '6':      // 1 string to match.
    2838           0 :             if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2839             :               break;
    2840           0 :             Mnemonic = "v_ldexp_f64";  // "v_ldexp_f64_e64"
    2841           0 :             return;
    2842             :           }
    2843             :           break;
    2844             :         case 'r':        // 3 strings to match.
    2845         213 :           if (memcmp(Mnemonic.data()+3, "ndne_f", 6) != 0)
    2846             :             break;
    2847             :           switch (Mnemonic[9]) {
    2848             :           default: break;
    2849             :           case '1':      // 1 string to match.
    2850           0 :             if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2851             :               break;
    2852           0 :             Mnemonic = "v_rndne_f16";  // "v_rndne_f16_e64"
    2853           0 :             return;
    2854             :           case '3':      // 1 string to match.
    2855           0 :             if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2856             :               break;
    2857           0 :             Mnemonic = "v_rndne_f32";  // "v_rndne_f32_e64"
    2858           0 :             return;
    2859             :           case '6':      // 1 string to match.
    2860           0 :             if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2861             :               break;
    2862           0 :             Mnemonic = "v_rndne_f64";  // "v_rndne_f64_e64"
    2863           0 :             return;
    2864             :           }
    2865             :           break;
    2866             :         case 's':        // 1 string to match.
    2867          87 :           if (memcmp(Mnemonic.data()+3, "ad_hi_u8_e64", 12) != 0)
    2868             :             break;
    2869           0 :           Mnemonic = "v_sad_hi_u8";    // "v_sad_hi_u8_e64"
    2870           0 :           return;
    2871             :         case 't':        // 3 strings to match.
    2872           0 :           if (memcmp(Mnemonic.data()+3, "runc_f", 6) != 0)
    2873             :             break;
    2874             :           switch (Mnemonic[9]) {
    2875             :           default: break;
    2876             :           case '1':      // 1 string to match.
    2877           0 :             if (memcmp(Mnemonic.data()+10, "6_e64", 5) != 0)
    2878             :               break;
    2879           0 :             Mnemonic = "v_trunc_f16";  // "v_trunc_f16_e64"
    2880           0 :             return;
    2881             :           case '3':      // 1 string to match.
    2882           0 :             if (memcmp(Mnemonic.data()+10, "2_e64", 5) != 0)
    2883             :               break;
    2884           0 :             Mnemonic = "v_trunc_f32";  // "v_trunc_f32_e64"
    2885           0 :             return;
    2886             :           case '6':      // 1 string to match.
    2887           0 :             if (memcmp(Mnemonic.data()+10, "4_e64", 5) != 0)
    2888             :               break;
    2889           0 :             Mnemonic = "v_trunc_f64";  // "v_trunc_f64_e64"
    2890           0 :             return;
    2891             :           }
    2892             :           break;
    2893             :         }
    2894             :         break;
    2895             :       case 16:   // 112 strings to match.
    2896        3859 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    2897             :           break;
    2898             :         switch (Mnemonic[2]) {
    2899             :         default: break;
    2900             :         case 'a':        // 1 string to match.
    2901           0 :           if (memcmp(Mnemonic.data()+3, "nd_or_b32_e64", 13) != 0)
    2902             :             break;
    2903           0 :           Mnemonic = "v_and_or_b32";   // "v_and_or_b32_e64"
    2904           0 :           return;
    2905        1266 :         case 'c':        // 85 strings to match.
    2906             :           switch (Mnemonic[3]) {
    2907             :           default: break;
    2908         457 :           case 'm':      // 81 strings to match.
    2909         457 :             if (Mnemonic[4] != 'p')
    2910             :               break;
    2911             :             switch (Mnemonic[5]) {
    2912             :             default: break;
    2913           0 :             case '_':    // 54 strings to match.
    2914             :               switch (Mnemonic[6]) {
    2915             :               default: break;
    2916             :               case 'e':  // 9 strings to match.
    2917           0 :                 if (memcmp(Mnemonic.data()+7, "q_", 2) != 0)
    2918             :                   break;
    2919             :                 switch (Mnemonic[9]) {
    2920             :                 default: break;
    2921           0 :                 case 'f':        // 3 strings to match.
    2922             :                   switch (Mnemonic[10]) {
    2923             :                   default: break;
    2924             :                   case '1':      // 1 string to match.
    2925           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    2926             :                       break;
    2927           0 :                     Mnemonic = "v_cmp_eq_f16";         // "v_cmp_eq_f16_e64"
    2928           0 :                     return;
    2929             :                   case '3':      // 1 string to match.
    2930           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    2931             :                       break;
    2932           0 :                     Mnemonic = "v_cmp_eq_f32";         // "v_cmp_eq_f32_e64"
    2933           0 :                     return;
    2934             :                   case '6':      // 1 string to match.
    2935           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    2936             :                       break;
    2937           0 :                     Mnemonic = "v_cmp_eq_f64";         // "v_cmp_eq_f64_e64"
    2938           0 :                     return;
    2939             :                   }
    2940             :                   break;
    2941           0 :                 case 'i':        // 3 strings to match.
    2942             :                   switch (Mnemonic[10]) {
    2943             :                   default: break;
    2944             :                   case '1':      // 1 string to match.
    2945           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    2946             :                       break;
    2947           0 :                     Mnemonic = "v_cmp_eq_i16";         // "v_cmp_eq_i16_e64"
    2948           0 :                     return;
    2949             :                   case '3':      // 1 string to match.
    2950           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    2951             :                       break;
    2952           0 :                     Mnemonic = "v_cmp_eq_i32";         // "v_cmp_eq_i32_e64"
    2953           0 :                     return;
    2954             :                   case '6':      // 1 string to match.
    2955           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    2956             :                       break;
    2957           0 :                     Mnemonic = "v_cmp_eq_i64";         // "v_cmp_eq_i64_e64"
    2958           0 :                     return;
    2959             :                   }
    2960             :                   break;
    2961           0 :                 case 'u':        // 3 strings to match.
    2962             :                   switch (Mnemonic[10]) {
    2963             :                   default: break;
    2964             :                   case '1':      // 1 string to match.
    2965           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    2966             :                       break;
    2967           0 :                     Mnemonic = "v_cmp_eq_u16";         // "v_cmp_eq_u16_e64"
    2968           0 :                     return;
    2969             :                   case '3':      // 1 string to match.
    2970           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    2971             :                       break;
    2972           0 :                     Mnemonic = "v_cmp_eq_u32";         // "v_cmp_eq_u32_e64"
    2973           0 :                     return;
    2974             :                   case '6':      // 1 string to match.
    2975           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    2976             :                       break;
    2977           0 :                     Mnemonic = "v_cmp_eq_u64";         // "v_cmp_eq_u64_e64"
    2978           0 :                     return;
    2979             :                   }
    2980             :                   break;
    2981             :                 }
    2982             :                 break;
    2983           0 :               case 'g':  // 18 strings to match.
    2984             :                 switch (Mnemonic[7]) {
    2985             :                 default: break;
    2986           0 :                 case 'e':        // 9 strings to match.
    2987           0 :                   if (Mnemonic[8] != '_')
    2988             :                     break;
    2989             :                   switch (Mnemonic[9]) {
    2990             :                   default: break;
    2991           0 :                   case 'f':      // 3 strings to match.
    2992             :                     switch (Mnemonic[10]) {
    2993             :                     default: break;
    2994             :                     case '1':    // 1 string to match.
    2995           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    2996             :                         break;
    2997           0 :                       Mnemonic = "v_cmp_ge_f16";       // "v_cmp_ge_f16_e64"
    2998           0 :                       return;
    2999             :                     case '3':    // 1 string to match.
    3000           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3001             :                         break;
    3002           0 :                       Mnemonic = "v_cmp_ge_f32";       // "v_cmp_ge_f32_e64"
    3003           0 :                       return;
    3004             :                     case '6':    // 1 string to match.
    3005           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3006             :                         break;
    3007           0 :                       Mnemonic = "v_cmp_ge_f64";       // "v_cmp_ge_f64_e64"
    3008           0 :                       return;
    3009             :                     }
    3010             :                     break;
    3011           0 :                   case 'i':      // 3 strings to match.
    3012             :                     switch (Mnemonic[10]) {
    3013             :                     default: break;
    3014             :                     case '1':    // 1 string to match.
    3015           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3016             :                         break;
    3017           0 :                       Mnemonic = "v_cmp_ge_i16";       // "v_cmp_ge_i16_e64"
    3018           0 :                       return;
    3019             :                     case '3':    // 1 string to match.
    3020           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3021             :                         break;
    3022           0 :                       Mnemonic = "v_cmp_ge_i32";       // "v_cmp_ge_i32_e64"
    3023           0 :                       return;
    3024             :                     case '6':    // 1 string to match.
    3025           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3026             :                         break;
    3027           0 :                       Mnemonic = "v_cmp_ge_i64";       // "v_cmp_ge_i64_e64"
    3028           0 :                       return;
    3029             :                     }
    3030             :                     break;
    3031           0 :                   case 'u':      // 3 strings to match.
    3032             :                     switch (Mnemonic[10]) {
    3033             :                     default: break;
    3034             :                     case '1':    // 1 string to match.
    3035           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3036             :                         break;
    3037           0 :                       Mnemonic = "v_cmp_ge_u16";       // "v_cmp_ge_u16_e64"
    3038           0 :                       return;
    3039             :                     case '3':    // 1 string to match.
    3040           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3041             :                         break;
    3042           0 :                       Mnemonic = "v_cmp_ge_u32";       // "v_cmp_ge_u32_e64"
    3043           0 :                       return;
    3044             :                     case '6':    // 1 string to match.
    3045           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3046             :                         break;
    3047           0 :                       Mnemonic = "v_cmp_ge_u64";       // "v_cmp_ge_u64_e64"
    3048           0 :                       return;
    3049             :                     }
    3050             :                     break;
    3051             :                   }
    3052             :                   break;
    3053           0 :                 case 't':        // 9 strings to match.
    3054           0 :                   if (Mnemonic[8] != '_')
    3055             :                     break;
    3056             :                   switch (Mnemonic[9]) {
    3057             :                   default: break;
    3058           0 :                   case 'f':      // 3 strings to match.
    3059             :                     switch (Mnemonic[10]) {
    3060             :                     default: break;
    3061             :                     case '1':    // 1 string to match.
    3062           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3063             :                         break;
    3064           0 :                       Mnemonic = "v_cmp_gt_f16";       // "v_cmp_gt_f16_e64"
    3065           0 :                       return;
    3066             :                     case '3':    // 1 string to match.
    3067           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3068             :                         break;
    3069           0 :                       Mnemonic = "v_cmp_gt_f32";       // "v_cmp_gt_f32_e64"
    3070           0 :                       return;
    3071             :                     case '6':    // 1 string to match.
    3072           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3073             :                         break;
    3074           0 :                       Mnemonic = "v_cmp_gt_f64";       // "v_cmp_gt_f64_e64"
    3075           0 :                       return;
    3076             :                     }
    3077             :                     break;
    3078           0 :                   case 'i':      // 3 strings to match.
    3079             :                     switch (Mnemonic[10]) {
    3080             :                     default: break;
    3081             :                     case '1':    // 1 string to match.
    3082           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3083             :                         break;
    3084           0 :                       Mnemonic = "v_cmp_gt_i16";       // "v_cmp_gt_i16_e64"
    3085           0 :                       return;
    3086             :                     case '3':    // 1 string to match.
    3087           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3088             :                         break;
    3089           0 :                       Mnemonic = "v_cmp_gt_i32";       // "v_cmp_gt_i32_e64"
    3090           0 :                       return;
    3091             :                     case '6':    // 1 string to match.
    3092           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3093             :                         break;
    3094           0 :                       Mnemonic = "v_cmp_gt_i64";       // "v_cmp_gt_i64_e64"
    3095           0 :                       return;
    3096             :                     }
    3097             :                     break;
    3098           0 :                   case 'u':      // 3 strings to match.
    3099             :                     switch (Mnemonic[10]) {
    3100             :                     default: break;
    3101             :                     case '1':    // 1 string to match.
    3102           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3103             :                         break;
    3104           0 :                       Mnemonic = "v_cmp_gt_u16";       // "v_cmp_gt_u16_e64"
    3105           0 :                       return;
    3106             :                     case '3':    // 1 string to match.
    3107           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3108             :                         break;
    3109           0 :                       Mnemonic = "v_cmp_gt_u32";       // "v_cmp_gt_u32_e64"
    3110           0 :                       return;
    3111             :                     case '6':    // 1 string to match.
    3112           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3113             :                         break;
    3114           0 :                       Mnemonic = "v_cmp_gt_u64";       // "v_cmp_gt_u64_e64"
    3115           0 :                       return;
    3116             :                     }
    3117             :                     break;
    3118             :                   }
    3119             :                   break;
    3120             :                 }
    3121             :                 break;
    3122           0 :               case 'l':  // 21 strings to match.
    3123             :                 switch (Mnemonic[7]) {
    3124             :                 default: break;
    3125           0 :                 case 'e':        // 9 strings to match.
    3126           0 :                   if (Mnemonic[8] != '_')
    3127             :                     break;
    3128             :                   switch (Mnemonic[9]) {
    3129             :                   default: break;
    3130           0 :                   case 'f':      // 3 strings to match.
    3131             :                     switch (Mnemonic[10]) {
    3132             :                     default: break;
    3133             :                     case '1':    // 1 string to match.
    3134           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3135             :                         break;
    3136           0 :                       Mnemonic = "v_cmp_le_f16";       // "v_cmp_le_f16_e64"
    3137           0 :                       return;
    3138             :                     case '3':    // 1 string to match.
    3139           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3140             :                         break;
    3141           0 :                       Mnemonic = "v_cmp_le_f32";       // "v_cmp_le_f32_e64"
    3142           0 :                       return;
    3143             :                     case '6':    // 1 string to match.
    3144           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3145             :                         break;
    3146           0 :                       Mnemonic = "v_cmp_le_f64";       // "v_cmp_le_f64_e64"
    3147           0 :                       return;
    3148             :                     }
    3149             :                     break;
    3150           0 :                   case 'i':      // 3 strings to match.
    3151             :                     switch (Mnemonic[10]) {
    3152             :                     default: break;
    3153             :                     case '1':    // 1 string to match.
    3154           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3155             :                         break;
    3156           0 :                       Mnemonic = "v_cmp_le_i16";       // "v_cmp_le_i16_e64"
    3157           0 :                       return;
    3158             :                     case '3':    // 1 string to match.
    3159           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3160             :                         break;
    3161           0 :                       Mnemonic = "v_cmp_le_i32";       // "v_cmp_le_i32_e64"
    3162           0 :                       return;
    3163             :                     case '6':    // 1 string to match.
    3164           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3165             :                         break;
    3166           0 :                       Mnemonic = "v_cmp_le_i64";       // "v_cmp_le_i64_e64"
    3167           0 :                       return;
    3168             :                     }
    3169             :                     break;
    3170           0 :                   case 'u':      // 3 strings to match.
    3171             :                     switch (Mnemonic[10]) {
    3172             :                     default: break;
    3173             :                     case '1':    // 1 string to match.
    3174           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3175             :                         break;
    3176           0 :                       Mnemonic = "v_cmp_le_u16";       // "v_cmp_le_u16_e64"
    3177           0 :                       return;
    3178             :                     case '3':    // 1 string to match.
    3179           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3180             :                         break;
    3181           0 :                       Mnemonic = "v_cmp_le_u32";       // "v_cmp_le_u32_e64"
    3182           0 :                       return;
    3183             :                     case '6':    // 1 string to match.
    3184           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3185             :                         break;
    3186           0 :                       Mnemonic = "v_cmp_le_u64";       // "v_cmp_le_u64_e64"
    3187           0 :                       return;
    3188             :                     }
    3189             :                     break;
    3190             :                   }
    3191             :                   break;
    3192             :                 case 'g':        // 3 strings to match.
    3193           0 :                   if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    3194             :                     break;
    3195             :                   switch (Mnemonic[10]) {
    3196             :                   default: break;
    3197             :                   case '1':      // 1 string to match.
    3198           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3199             :                       break;
    3200           0 :                     Mnemonic = "v_cmp_lg_f16";         // "v_cmp_lg_f16_e64"
    3201           0 :                     return;
    3202             :                   case '3':      // 1 string to match.
    3203           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3204             :                       break;
    3205           0 :                     Mnemonic = "v_cmp_lg_f32";         // "v_cmp_lg_f32_e64"
    3206           0 :                     return;
    3207             :                   case '6':      // 1 string to match.
    3208           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3209             :                       break;
    3210           0 :                     Mnemonic = "v_cmp_lg_f64";         // "v_cmp_lg_f64_e64"
    3211           0 :                     return;
    3212             :                   }
    3213             :                   break;
    3214           0 :                 case 't':        // 9 strings to match.
    3215           0 :                   if (Mnemonic[8] != '_')
    3216             :                     break;
    3217             :                   switch (Mnemonic[9]) {
    3218             :                   default: break;
    3219           0 :                   case 'f':      // 3 strings to match.
    3220             :                     switch (Mnemonic[10]) {
    3221             :                     default: break;
    3222             :                     case '1':    // 1 string to match.
    3223           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3224             :                         break;
    3225           0 :                       Mnemonic = "v_cmp_lt_f16";       // "v_cmp_lt_f16_e64"
    3226           0 :                       return;
    3227             :                     case '3':    // 1 string to match.
    3228           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3229             :                         break;
    3230           0 :                       Mnemonic = "v_cmp_lt_f32";       // "v_cmp_lt_f32_e64"
    3231           0 :                       return;
    3232             :                     case '6':    // 1 string to match.
    3233           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3234             :                         break;
    3235           0 :                       Mnemonic = "v_cmp_lt_f64";       // "v_cmp_lt_f64_e64"
    3236           0 :                       return;
    3237             :                     }
    3238             :                     break;
    3239           0 :                   case 'i':      // 3 strings to match.
    3240             :                     switch (Mnemonic[10]) {
    3241             :                     default: break;
    3242             :                     case '1':    // 1 string to match.
    3243           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3244             :                         break;
    3245           0 :                       Mnemonic = "v_cmp_lt_i16";       // "v_cmp_lt_i16_e64"
    3246           0 :                       return;
    3247             :                     case '3':    // 1 string to match.
    3248           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3249             :                         break;
    3250           0 :                       Mnemonic = "v_cmp_lt_i32";       // "v_cmp_lt_i32_e64"
    3251           0 :                       return;
    3252             :                     case '6':    // 1 string to match.
    3253           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3254             :                         break;
    3255           0 :                       Mnemonic = "v_cmp_lt_i64";       // "v_cmp_lt_i64_e64"
    3256           0 :                       return;
    3257             :                     }
    3258             :                     break;
    3259           0 :                   case 'u':      // 3 strings to match.
    3260             :                     switch (Mnemonic[10]) {
    3261             :                     default: break;
    3262             :                     case '1':    // 1 string to match.
    3263           0 :                       if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3264             :                         break;
    3265           0 :                       Mnemonic = "v_cmp_lt_u16";       // "v_cmp_lt_u16_e64"
    3266           0 :                       return;
    3267             :                     case '3':    // 1 string to match.
    3268           0 :                       if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3269             :                         break;
    3270           0 :                       Mnemonic = "v_cmp_lt_u32";       // "v_cmp_lt_u32_e64"
    3271           0 :                       return;
    3272             :                     case '6':    // 1 string to match.
    3273           0 :                       if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3274             :                         break;
    3275           0 :                       Mnemonic = "v_cmp_lt_u64";       // "v_cmp_lt_u64_e64"
    3276           0 :                       return;
    3277             :                     }
    3278             :                     break;
    3279             :                   }
    3280             :                   break;
    3281             :                 }
    3282             :                 break;
    3283             :               case 'n':  // 6 strings to match.
    3284           0 :                 if (memcmp(Mnemonic.data()+7, "e_", 2) != 0)
    3285             :                   break;
    3286             :                 switch (Mnemonic[9]) {
    3287             :                 default: break;
    3288           0 :                 case 'i':        // 3 strings to match.
    3289             :                   switch (Mnemonic[10]) {
    3290             :                   default: break;
    3291             :                   case '1':      // 1 string to match.
    3292           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3293             :                       break;
    3294           0 :                     Mnemonic = "v_cmp_ne_i16";         // "v_cmp_ne_i16_e64"
    3295           0 :                     return;
    3296             :                   case '3':      // 1 string to match.
    3297           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3298             :                       break;
    3299           0 :                     Mnemonic = "v_cmp_ne_i32";         // "v_cmp_ne_i32_e64"
    3300           0 :                     return;
    3301             :                   case '6':      // 1 string to match.
    3302           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3303             :                       break;
    3304           0 :                     Mnemonic = "v_cmp_ne_i64";         // "v_cmp_ne_i64_e64"
    3305           0 :                     return;
    3306             :                   }
    3307             :                   break;
    3308           0 :                 case 'u':        // 3 strings to match.
    3309             :                   switch (Mnemonic[10]) {
    3310             :                   default: break;
    3311             :                   case '1':      // 1 string to match.
    3312           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3313             :                       break;
    3314           0 :                     Mnemonic = "v_cmp_ne_u16";         // "v_cmp_ne_u16_e64"
    3315           0 :                     return;
    3316             :                   case '3':      // 1 string to match.
    3317           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3318             :                       break;
    3319           0 :                     Mnemonic = "v_cmp_ne_u32";         // "v_cmp_ne_u32_e64"
    3320           0 :                     return;
    3321             :                   case '6':      // 1 string to match.
    3322           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3323             :                       break;
    3324           0 :                     Mnemonic = "v_cmp_ne_u64";         // "v_cmp_ne_u64_e64"
    3325           0 :                     return;
    3326             :                   }
    3327             :                   break;
    3328             :                 }
    3329             :                 break;
    3330             :               }
    3331             :               break;
    3332           0 :             case 's':    // 6 strings to match.
    3333           0 :               if (Mnemonic[6] != '_')
    3334             :                 break;
    3335             :               switch (Mnemonic[7]) {
    3336             :               default: break;
    3337             :               case 'f':  // 2 strings to match.
    3338           0 :                 if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    3339             :                   break;
    3340             :                 switch (Mnemonic[10]) {
    3341             :                 default: break;
    3342             :                 case '3':        // 1 string to match.
    3343           0 :                   if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3344             :                     break;
    3345           0 :                   Mnemonic = "v_cmps_f_f32";   // "v_cmps_f_f32_e64"
    3346           0 :                   return;
    3347             :                 case '6':        // 1 string to match.
    3348           0 :                   if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3349             :                     break;
    3350           0 :                   Mnemonic = "v_cmps_f_f64";   // "v_cmps_f_f64_e64"
    3351           0 :                   return;
    3352             :                 }
    3353             :                 break;
    3354             :               case 'o':  // 2 strings to match.
    3355           0 :                 if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    3356             :                   break;
    3357             :                 switch (Mnemonic[10]) {
    3358             :                 default: break;
    3359             :                 case '3':        // 1 string to match.
    3360           0 :                   if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3361             :                     break;
    3362           0 :                   Mnemonic = "v_cmps_o_f32";   // "v_cmps_o_f32_e64"
    3363           0 :                   return;
    3364             :                 case '6':        // 1 string to match.
    3365           0 :                   if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3366             :                     break;
    3367           0 :                   Mnemonic = "v_cmps_o_f64";   // "v_cmps_o_f64_e64"
    3368           0 :                   return;
    3369             :                 }
    3370             :                 break;
    3371             :               case 'u':  // 2 strings to match.
    3372           0 :                 if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    3373             :                   break;
    3374             :                 switch (Mnemonic[10]) {
    3375             :                 default: break;
    3376             :                 case '3':        // 1 string to match.
    3377           0 :                   if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3378             :                     break;
    3379           0 :                   Mnemonic = "v_cmps_u_f32";   // "v_cmps_u_f32_e64"
    3380           0 :                   return;
    3381             :                 case '6':        // 1 string to match.
    3382           0 :                   if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3383             :                     break;
    3384           0 :                   Mnemonic = "v_cmps_u_f64";   // "v_cmps_u_f64_e64"
    3385           0 :                   return;
    3386             :                 }
    3387             :                 break;
    3388             :               }
    3389             :               break;
    3390         457 :             case 'x':    // 21 strings to match.
    3391         457 :               if (Mnemonic[6] != '_')
    3392             :                 break;
    3393             :               switch (Mnemonic[7]) {
    3394             :               default: break;
    3395           0 :               case 'f':  // 9 strings to match.
    3396           0 :                 if (Mnemonic[8] != '_')
    3397             :                   break;
    3398             :                 switch (Mnemonic[9]) {
    3399             :                 default: break;
    3400           0 :                 case 'f':        // 3 strings to match.
    3401             :                   switch (Mnemonic[10]) {
    3402             :                   default: break;
    3403             :                   case '1':      // 1 string to match.
    3404           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3405             :                       break;
    3406           0 :                     Mnemonic = "v_cmpx_f_f16";         // "v_cmpx_f_f16_e64"
    3407           0 :                     return;
    3408             :                   case '3':      // 1 string to match.
    3409           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3410             :                       break;
    3411           0 :                     Mnemonic = "v_cmpx_f_f32";         // "v_cmpx_f_f32_e64"
    3412           0 :                     return;
    3413             :                   case '6':      // 1 string to match.
    3414           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3415             :                       break;
    3416           0 :                     Mnemonic = "v_cmpx_f_f64";         // "v_cmpx_f_f64_e64"
    3417           0 :                     return;
    3418             :                   }
    3419             :                   break;
    3420           0 :                 case 'i':        // 3 strings to match.
    3421             :                   switch (Mnemonic[10]) {
    3422             :                   default: break;
    3423             :                   case '1':      // 1 string to match.
    3424           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3425             :                       break;
    3426           0 :                     Mnemonic = "v_cmpx_f_i16";         // "v_cmpx_f_i16_e64"
    3427           0 :                     return;
    3428             :                   case '3':      // 1 string to match.
    3429           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3430             :                       break;
    3431           0 :                     Mnemonic = "v_cmpx_f_i32";         // "v_cmpx_f_i32_e64"
    3432           0 :                     return;
    3433             :                   case '6':      // 1 string to match.
    3434           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3435             :                       break;
    3436           0 :                     Mnemonic = "v_cmpx_f_i64";         // "v_cmpx_f_i64_e64"
    3437           0 :                     return;
    3438             :                   }
    3439             :                   break;
    3440           0 :                 case 'u':        // 3 strings to match.
    3441             :                   switch (Mnemonic[10]) {
    3442             :                   default: break;
    3443             :                   case '1':      // 1 string to match.
    3444           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3445             :                       break;
    3446           0 :                     Mnemonic = "v_cmpx_f_u16";         // "v_cmpx_f_u16_e64"
    3447           0 :                     return;
    3448             :                   case '3':      // 1 string to match.
    3449           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3450             :                       break;
    3451           0 :                     Mnemonic = "v_cmpx_f_u32";         // "v_cmpx_f_u32_e64"
    3452           0 :                     return;
    3453             :                   case '6':      // 1 string to match.
    3454           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3455             :                       break;
    3456           0 :                     Mnemonic = "v_cmpx_f_u64";         // "v_cmpx_f_u64_e64"
    3457           0 :                     return;
    3458             :                   }
    3459             :                   break;
    3460             :                 }
    3461             :                 break;
    3462             :               case 'o':  // 3 strings to match.
    3463           0 :                 if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    3464             :                   break;
    3465             :                 switch (Mnemonic[10]) {
    3466             :                 default: break;
    3467             :                 case '1':        // 1 string to match.
    3468           0 :                   if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3469             :                     break;
    3470           0 :                   Mnemonic = "v_cmpx_o_f16";   // "v_cmpx_o_f16_e64"
    3471           0 :                   return;
    3472             :                 case '3':        // 1 string to match.
    3473           0 :                   if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3474             :                     break;
    3475           0 :                   Mnemonic = "v_cmpx_o_f32";   // "v_cmpx_o_f32_e64"
    3476           0 :                   return;
    3477             :                 case '6':        // 1 string to match.
    3478           0 :                   if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3479             :                     break;
    3480           0 :                   Mnemonic = "v_cmpx_o_f64";   // "v_cmpx_o_f64_e64"
    3481           0 :                   return;
    3482             :                 }
    3483             :                 break;
    3484           0 :               case 't':  // 6 strings to match.
    3485           0 :                 if (Mnemonic[8] != '_')
    3486             :                   break;
    3487             :                 switch (Mnemonic[9]) {
    3488             :                 default: break;
    3489           0 :                 case 'i':        // 3 strings to match.
    3490             :                   switch (Mnemonic[10]) {
    3491             :                   default: break;
    3492             :                   case '1':      // 1 string to match.
    3493           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3494             :                       break;
    3495           0 :                     Mnemonic = "v_cmpx_t_i16";         // "v_cmpx_t_i16_e64"
    3496           0 :                     return;
    3497             :                   case '3':      // 1 string to match.
    3498           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3499             :                       break;
    3500           0 :                     Mnemonic = "v_cmpx_t_i32";         // "v_cmpx_t_i32_e64"
    3501           0 :                     return;
    3502             :                   case '6':      // 1 string to match.
    3503           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3504             :                       break;
    3505           0 :                     Mnemonic = "v_cmpx_t_i64";         // "v_cmpx_t_i64_e64"
    3506           0 :                     return;
    3507             :                   }
    3508             :                   break;
    3509           0 :                 case 'u':        // 3 strings to match.
    3510             :                   switch (Mnemonic[10]) {
    3511             :                   default: break;
    3512             :                   case '1':      // 1 string to match.
    3513           0 :                     if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3514             :                       break;
    3515           0 :                     Mnemonic = "v_cmpx_t_u16";         // "v_cmpx_t_u16_e64"
    3516           0 :                     return;
    3517             :                   case '3':      // 1 string to match.
    3518           0 :                     if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3519             :                       break;
    3520           0 :                     Mnemonic = "v_cmpx_t_u32";         // "v_cmpx_t_u32_e64"
    3521           0 :                     return;
    3522             :                   case '6':      // 1 string to match.
    3523           0 :                     if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3524             :                       break;
    3525           0 :                     Mnemonic = "v_cmpx_t_u64";         // "v_cmpx_t_u64_e64"
    3526           0 :                     return;
    3527             :                   }
    3528             :                   break;
    3529             :                 }
    3530             :                 break;
    3531             :               case 'u':  // 3 strings to match.
    3532           0 :                 if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    3533             :                   break;
    3534             :                 switch (Mnemonic[10]) {
    3535             :                 default: break;
    3536             :                 case '1':        // 1 string to match.
    3537           0 :                   if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3538             :                     break;
    3539           0 :                   Mnemonic = "v_cmpx_u_f16";   // "v_cmpx_u_f16_e64"
    3540           0 :                   return;
    3541             :                 case '3':        // 1 string to match.
    3542           0 :                   if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3543             :                     break;
    3544           0 :                   Mnemonic = "v_cmpx_u_f32";   // "v_cmpx_u_f32_e64"
    3545           0 :                   return;
    3546             :                 case '6':        // 1 string to match.
    3547           0 :                   if (memcmp(Mnemonic.data()+11, "4_e64", 5) != 0)
    3548             :                     break;
    3549           0 :                   Mnemonic = "v_cmpx_u_f64";   // "v_cmpx_u_f64_e64"
    3550           0 :                   return;
    3551             :                 }
    3552             :                 break;
    3553             :               }
    3554             :               break;
    3555             :             }
    3556             :             break;
    3557             :           case 'u':      // 4 strings to match.
    3558           0 :             if (memcmp(Mnemonic.data()+4, "be", 2) != 0)
    3559             :               break;
    3560             :             switch (Mnemonic[6]) {
    3561             :             default: break;
    3562             :             case 'i':    // 1 string to match.
    3563           0 :               if (memcmp(Mnemonic.data()+7, "d_f32_e64", 9) != 0)
    3564             :                 break;
    3565           0 :               Mnemonic = "v_cubeid_f32";       // "v_cubeid_f32_e64"
    3566           0 :               return;
    3567             :             case 'm':    // 1 string to match.
    3568           0 :               if (memcmp(Mnemonic.data()+7, "a_f32_e64", 9) != 0)
    3569             :                 break;
    3570           0 :               Mnemonic = "v_cubema_f32";       // "v_cubema_f32_e64"
    3571           0 :               return;
    3572             :             case 's':    // 1 string to match.
    3573           0 :               if (memcmp(Mnemonic.data()+7, "c_f32_e64", 9) != 0)
    3574             :                 break;
    3575           0 :               Mnemonic = "v_cubesc_f32";       // "v_cubesc_f32_e64"
    3576           0 :               return;
    3577             :             case 't':    // 1 string to match.
    3578           0 :               if (memcmp(Mnemonic.data()+7, "c_f32_e64", 9) != 0)
    3579             :                 break;
    3580           0 :               Mnemonic = "v_cubetc_f32";       // "v_cubetc_f32_e64"
    3581           0 :               return;
    3582             :             }
    3583             :             break;
    3584             :           }
    3585             :           break;
    3586             :         case 'm':        // 6 strings to match.
    3587        1169 :           if (memcmp(Mnemonic.data()+3, "ul", 2) != 0)
    3588             :             break;
    3589             :           switch (Mnemonic[5]) {
    3590             :           default: break;
    3591         482 :           case '_':      // 5 strings to match.
    3592             :             switch (Mnemonic[6]) {
    3593             :             default: break;
    3594             :             case 'h':    // 2 strings to match.
    3595         296 :               if (memcmp(Mnemonic.data()+7, "i_", 2) != 0)
    3596             :                 break;
    3597             :               switch (Mnemonic[9]) {
    3598             :               default: break;
    3599             :               case 'i':  // 1 string to match.
    3600         148 :                 if (memcmp(Mnemonic.data()+10, "32_e64", 6) != 0)
    3601             :                   break;
    3602           0 :                 Mnemonic = "v_mul_hi_i32";     // "v_mul_hi_i32_e64"
    3603           0 :                 return;
    3604             :               case 'u':  // 1 string to match.
    3605         148 :                 if (memcmp(Mnemonic.data()+10, "32_e64", 6) != 0)
    3606             :                   break;
    3607           0 :                 Mnemonic = "v_mul_hi_u32";     // "v_mul_hi_u32_e64"
    3608           0 :                 return;
    3609             :               }
    3610             :               break;
    3611             :             case 'l':    // 3 strings to match.
    3612         186 :               if (memcmp(Mnemonic.data()+7, "o_", 2) != 0)
    3613             :                 break;
    3614             :               switch (Mnemonic[9]) {
    3615             :               default: break;
    3616             :               case 'i':  // 1 string to match.
    3617           0 :                 if (memcmp(Mnemonic.data()+10, "32_e64", 6) != 0)
    3618             :                   break;
    3619           0 :                 Mnemonic = "v_mul_lo_i32";     // "v_mul_lo_i32_e64"
    3620           0 :                 return;
    3621           0 :               case 'u':  // 2 strings to match.
    3622             :                 switch (Mnemonic[10]) {
    3623             :                 default: break;
    3624             :                 case '1':        // 1 string to match.
    3625           0 :                   if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3626             :                     break;
    3627           0 :                   Mnemonic = "v_mul_lo_u16";   // "v_mul_lo_u16_e64"
    3628           0 :                   return;
    3629             :                 case '3':        // 1 string to match.
    3630           0 :                   if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3631             :                     break;
    3632           0 :                   Mnemonic = "v_mul_lo_u32";   // "v_mul_lo_u32_e64"
    3633           0 :                   return;
    3634             :                 }
    3635             :                 break;
    3636             :               }
    3637             :               break;
    3638             :             }
    3639             :             break;
    3640             :           case 'l':      // 1 string to match.
    3641           0 :             if (memcmp(Mnemonic.data()+6, "it_f32_e64", 10) != 0)
    3642             :               break;
    3643           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_mullit_f32_e64"
    3644           0 :               Mnemonic = "v_mullit_f32";
    3645             :             return;
    3646             :           }
    3647             :           break;
    3648             :         case 'p':        // 15 strings to match.
    3649         183 :           if (memcmp(Mnemonic.data()+3, "k_", 2) != 0)
    3650             :             break;
    3651             :           switch (Mnemonic[5]) {
    3652             :           default: break;
    3653             :           case 'a':      // 3 strings to match.
    3654          61 :             if (memcmp(Mnemonic.data()+6, "dd_", 3) != 0)
    3655             :               break;
    3656             :             switch (Mnemonic[9]) {
    3657             :             default: break;
    3658             :             case 'f':    // 1 string to match.
    3659           0 :               if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3660             :                 break;
    3661           0 :               Mnemonic = "v_pk_add_f16";       // "v_pk_add_f16_e64"
    3662           0 :               return;
    3663             :             case 'i':    // 1 string to match.
    3664           0 :               if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3665             :                 break;
    3666           0 :               Mnemonic = "v_pk_add_i16";       // "v_pk_add_i16_e64"
    3667           0 :               return;
    3668             :             case 'u':    // 1 string to match.
    3669           0 :               if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3670             :                 break;
    3671           0 :               Mnemonic = "v_pk_add_u16";       // "v_pk_add_u16_e64"
    3672           0 :               return;
    3673             :             }
    3674             :             break;
    3675             :           case 'f':      // 1 string to match.
    3676           0 :             if (memcmp(Mnemonic.data()+6, "ma_f16_e64", 10) != 0)
    3677             :               break;
    3678           0 :             Mnemonic = "v_pk_fma_f16";         // "v_pk_fma_f16_e64"
    3679           0 :             return;
    3680           0 :           case 'm':      // 9 strings to match.
    3681             :             switch (Mnemonic[6]) {
    3682             :             default: break;
    3683           0 :             case 'a':    // 5 strings to match.
    3684             :               switch (Mnemonic[7]) {
    3685             :               default: break;
    3686           0 :               case 'd':  // 2 strings to match.
    3687           0 :                 if (Mnemonic[8] != '_')
    3688             :                   break;
    3689             :                 switch (Mnemonic[9]) {
    3690             :                 default: break;
    3691             :                 case 'i':        // 1 string to match.
    3692           0 :                   if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3693             :                     break;
    3694           0 :                   Mnemonic = "v_pk_mad_i16";   // "v_pk_mad_i16_e64"
    3695           0 :                   return;
    3696             :                 case 'u':        // 1 string to match.
    3697           0 :                   if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3698             :                     break;
    3699           0 :                   Mnemonic = "v_pk_mad_u16";   // "v_pk_mad_u16_e64"
    3700           0 :                   return;
    3701             :                 }
    3702             :                 break;
    3703           0 :               case 'x':  // 3 strings to match.
    3704           0 :                 if (Mnemonic[8] != '_')
    3705             :                   break;
    3706             :                 switch (Mnemonic[9]) {
    3707             :                 default: break;
    3708             :                 case 'f':        // 1 string to match.
    3709           0 :                   if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3710             :                     break;
    3711           0 :                   Mnemonic = "v_pk_max_f16";   // "v_pk_max_f16_e64"
    3712           0 :                   return;
    3713             :                 case 'i':        // 1 string to match.
    3714           0 :                   if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3715             :                     break;
    3716           0 :                   Mnemonic = "v_pk_max_i16";   // "v_pk_max_i16_e64"
    3717           0 :                   return;
    3718             :                 case 'u':        // 1 string to match.
    3719           0 :                   if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3720             :                     break;
    3721           0 :                   Mnemonic = "v_pk_max_u16";   // "v_pk_max_u16_e64"
    3722           0 :                   return;
    3723             :                 }
    3724             :                 break;
    3725             :               }
    3726             :               break;
    3727             :             case 'i':    // 3 strings to match.
    3728           0 :               if (memcmp(Mnemonic.data()+7, "n_", 2) != 0)
    3729             :                 break;
    3730             :               switch (Mnemonic[9]) {
    3731             :               default: break;
    3732             :               case 'f':  // 1 string to match.
    3733           0 :                 if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3734             :                   break;
    3735           0 :                 Mnemonic = "v_pk_min_f16";     // "v_pk_min_f16_e64"
    3736           0 :                 return;
    3737             :               case 'i':  // 1 string to match.
    3738           0 :                 if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3739             :                   break;
    3740           0 :                 Mnemonic = "v_pk_min_i16";     // "v_pk_min_i16_e64"
    3741           0 :                 return;
    3742             :               case 'u':  // 1 string to match.
    3743           0 :                 if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3744             :                   break;
    3745           0 :                 Mnemonic = "v_pk_min_u16";     // "v_pk_min_u16_e64"
    3746           0 :                 return;
    3747             :               }
    3748             :               break;
    3749             :             case 'u':    // 1 string to match.
    3750           0 :               if (memcmp(Mnemonic.data()+7, "l_f16_e64", 9) != 0)
    3751             :                 break;
    3752           0 :               Mnemonic = "v_pk_mul_f16";       // "v_pk_mul_f16_e64"
    3753           0 :               return;
    3754             :             }
    3755             :             break;
    3756             :           case 's':      // 2 strings to match.
    3757           0 :             if (memcmp(Mnemonic.data()+6, "ub_", 3) != 0)
    3758             :               break;
    3759             :             switch (Mnemonic[9]) {
    3760             :             default: break;
    3761             :             case 'i':    // 1 string to match.
    3762           0 :               if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3763             :                 break;
    3764           0 :               Mnemonic = "v_pk_sub_i16";       // "v_pk_sub_i16_e64"
    3765           0 :               return;
    3766             :             case 'u':    // 1 string to match.
    3767           0 :               if (memcmp(Mnemonic.data()+10, "16_e64", 6) != 0)
    3768             :                 break;
    3769           0 :               Mnemonic = "v_pk_sub_u16";       // "v_pk_sub_u16_e64"
    3770           0 :               return;
    3771             :             }
    3772             :             break;
    3773             :           }
    3774             :           break;
    3775             :         case 's':        // 5 strings to match.
    3776          42 :           if (memcmp(Mnemonic.data()+3, "ubrev_", 6) != 0)
    3777             :             break;
    3778             :           switch (Mnemonic[9]) {
    3779             :           default: break;
    3780           0 :           case 'f':      // 2 strings to match.
    3781             :             switch (Mnemonic[10]) {
    3782             :             default: break;
    3783             :             case '1':    // 1 string to match.
    3784           0 :               if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3785             :                 break;
    3786           0 :               Mnemonic = "v_subrev_f16";       // "v_subrev_f16_e64"
    3787           0 :               return;
    3788             :             case '3':    // 1 string to match.
    3789           0 :               if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3790             :                 break;
    3791           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_subrev_f32_e64"
    3792           0 :                 Mnemonic = "v_subrev_f32";
    3793             :               return;
    3794             :             }
    3795             :             break;
    3796             :           case 'i':      // 1 string to match.
    3797           0 :             if (memcmp(Mnemonic.data()+10, "32_e64", 6) != 0)
    3798             :               break;
    3799           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_subrev_i32_e64"
    3800           0 :               Mnemonic = "v_subrev_i32";
    3801             :             return;
    3802           0 :           case 'u':      // 2 strings to match.
    3803             :             switch (Mnemonic[10]) {
    3804             :             default: break;
    3805             :             case '1':    // 1 string to match.
    3806           0 :               if (memcmp(Mnemonic.data()+11, "6_e64", 5) != 0)
    3807             :                 break;
    3808           0 :               Mnemonic = "v_subrev_u16";       // "v_subrev_u16_e64"
    3809           0 :               return;
    3810             :             case '3':    // 1 string to match.
    3811           0 :               if (memcmp(Mnemonic.data()+11, "2_e64", 5) != 0)
    3812             :                 break;
    3813           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_subrev_u32_e64"
    3814           0 :                 Mnemonic = "v_subrev_u32";
    3815             :               return;
    3816             :             }
    3817             :             break;
    3818             :           }
    3819             :           break;
    3820             :         }
    3821             :         break;
    3822             :       case 17:   // 138 strings to match.
    3823         686 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    3824             :           break;
    3825             :         switch (Mnemonic[2]) {
    3826             :         default: break;
    3827             :         case 'a':        // 3 strings to match.
    3828           0 :           if (memcmp(Mnemonic.data()+3, "shrrev_i", 8) != 0)
    3829             :             break;
    3830             :           switch (Mnemonic[11]) {
    3831             :           default: break;
    3832             :           case '1':      // 1 string to match.
    3833           0 :             if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    3834             :               break;
    3835           0 :             Mnemonic = "v_ashrrev_i16";        // "v_ashrrev_i16_e64"
    3836           0 :             return;
    3837             :           case '3':      // 1 string to match.
    3838           0 :             if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    3839             :               break;
    3840           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_ashrrev_i32_e64"
    3841           0 :               Mnemonic = "v_ashrrev_i32";
    3842             :             return;
    3843             :           case '6':      // 1 string to match.
    3844           0 :             if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    3845             :               break;
    3846           0 :             Mnemonic = "v_ashrrev_i64";        // "v_ashrrev_i64_e64"
    3847           0 :             return;
    3848             :           }
    3849             :           break;
    3850         186 :         case 'c':        // 110 strings to match.
    3851             :           switch (Mnemonic[3]) {
    3852             :           default: break;
    3853           0 :           case 'm':      // 93 strings to match.
    3854           0 :             if (Mnemonic[4] != 'p')
    3855             :               break;
    3856             :             switch (Mnemonic[5]) {
    3857             :             default: break;
    3858           0 :             case '_':    // 21 strings to match.
    3859             :               switch (Mnemonic[6]) {
    3860             :               default: break;
    3861           0 :               case 'n':  // 18 strings to match.
    3862             :                 switch (Mnemonic[7]) {
    3863             :                 default: break;
    3864             :                 case 'e':        // 3 strings to match.
    3865           0 :                   if (memcmp(Mnemonic.data()+8, "q_f", 3) != 0)
    3866             :                     break;
    3867             :                   switch (Mnemonic[11]) {
    3868             :                   default: break;
    3869             :                   case '1':      // 1 string to match.
    3870           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    3871             :                       break;
    3872           0 :                     Mnemonic = "v_cmp_neq_f16";        // "v_cmp_neq_f16_e64"
    3873           0 :                     return;
    3874             :                   case '3':      // 1 string to match.
    3875           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    3876             :                       break;
    3877           0 :                     Mnemonic = "v_cmp_neq_f32";        // "v_cmp_neq_f32_e64"
    3878           0 :                     return;
    3879             :                   case '6':      // 1 string to match.
    3880           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    3881             :                       break;
    3882           0 :                     Mnemonic = "v_cmp_neq_f64";        // "v_cmp_neq_f64_e64"
    3883           0 :                     return;
    3884             :                   }
    3885             :                   break;
    3886           0 :                 case 'g':        // 6 strings to match.
    3887             :                   switch (Mnemonic[8]) {
    3888             :                   default: break;
    3889             :                   case 'e':      // 3 strings to match.
    3890           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    3891             :                       break;
    3892             :                     switch (Mnemonic[11]) {
    3893             :                     default: break;
    3894             :                     case '1':    // 1 string to match.
    3895           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    3896             :                         break;
    3897           0 :                       Mnemonic = "v_cmp_nge_f16";      // "v_cmp_nge_f16_e64"
    3898           0 :                       return;
    3899             :                     case '3':    // 1 string to match.
    3900           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    3901             :                         break;
    3902           0 :                       Mnemonic = "v_cmp_nge_f32";      // "v_cmp_nge_f32_e64"
    3903           0 :                       return;
    3904             :                     case '6':    // 1 string to match.
    3905           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    3906             :                         break;
    3907           0 :                       Mnemonic = "v_cmp_nge_f64";      // "v_cmp_nge_f64_e64"
    3908           0 :                       return;
    3909             :                     }
    3910             :                     break;
    3911             :                   case 't':      // 3 strings to match.
    3912           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    3913             :                       break;
    3914             :                     switch (Mnemonic[11]) {
    3915             :                     default: break;
    3916             :                     case '1':    // 1 string to match.
    3917           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    3918             :                         break;
    3919           0 :                       Mnemonic = "v_cmp_ngt_f16";      // "v_cmp_ngt_f16_e64"
    3920           0 :                       return;
    3921             :                     case '3':    // 1 string to match.
    3922           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    3923             :                         break;
    3924           0 :                       Mnemonic = "v_cmp_ngt_f32";      // "v_cmp_ngt_f32_e64"
    3925           0 :                       return;
    3926             :                     case '6':    // 1 string to match.
    3927           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    3928             :                         break;
    3929           0 :                       Mnemonic = "v_cmp_ngt_f64";      // "v_cmp_ngt_f64_e64"
    3930           0 :                       return;
    3931             :                     }
    3932             :                     break;
    3933             :                   }
    3934             :                   break;
    3935           0 :                 case 'l':        // 9 strings to match.
    3936             :                   switch (Mnemonic[8]) {
    3937             :                   default: break;
    3938             :                   case 'e':      // 3 strings to match.
    3939           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    3940             :                       break;
    3941             :                     switch (Mnemonic[11]) {
    3942             :                     default: break;
    3943             :                     case '1':    // 1 string to match.
    3944           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    3945             :                         break;
    3946           0 :                       Mnemonic = "v_cmp_nle_f16";      // "v_cmp_nle_f16_e64"
    3947           0 :                       return;
    3948             :                     case '3':    // 1 string to match.
    3949           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    3950             :                         break;
    3951           0 :                       Mnemonic = "v_cmp_nle_f32";      // "v_cmp_nle_f32_e64"
    3952           0 :                       return;
    3953             :                     case '6':    // 1 string to match.
    3954           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    3955             :                         break;
    3956           0 :                       Mnemonic = "v_cmp_nle_f64";      // "v_cmp_nle_f64_e64"
    3957           0 :                       return;
    3958             :                     }
    3959             :                     break;
    3960             :                   case 'g':      // 3 strings to match.
    3961           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    3962             :                       break;
    3963             :                     switch (Mnemonic[11]) {
    3964             :                     default: break;
    3965             :                     case '1':    // 1 string to match.
    3966           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    3967             :                         break;
    3968           0 :                       Mnemonic = "v_cmp_nlg_f16";      // "v_cmp_nlg_f16_e64"
    3969           0 :                       return;
    3970             :                     case '3':    // 1 string to match.
    3971           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    3972             :                         break;
    3973           0 :                       Mnemonic = "v_cmp_nlg_f32";      // "v_cmp_nlg_f32_e64"
    3974           0 :                       return;
    3975             :                     case '6':    // 1 string to match.
    3976           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    3977             :                         break;
    3978           0 :                       Mnemonic = "v_cmp_nlg_f64";      // "v_cmp_nlg_f64_e64"
    3979           0 :                       return;
    3980             :                     }
    3981             :                     break;
    3982             :                   case 't':      // 3 strings to match.
    3983           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    3984             :                       break;
    3985             :                     switch (Mnemonic[11]) {
    3986             :                     default: break;
    3987             :                     case '1':    // 1 string to match.
    3988           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    3989             :                         break;
    3990           0 :                       Mnemonic = "v_cmp_nlt_f16";      // "v_cmp_nlt_f16_e64"
    3991           0 :                       return;
    3992             :                     case '3':    // 1 string to match.
    3993           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    3994             :                         break;
    3995           0 :                       Mnemonic = "v_cmp_nlt_f32";      // "v_cmp_nlt_f32_e64"
    3996           0 :                       return;
    3997             :                     case '6':    // 1 string to match.
    3998           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    3999             :                         break;
    4000           0 :                       Mnemonic = "v_cmp_nlt_f64";      // "v_cmp_nlt_f64_e64"
    4001           0 :                       return;
    4002             :                     }
    4003             :                     break;
    4004             :                   }
    4005             :                   break;
    4006             :                 }
    4007             :                 break;
    4008             :               case 't':  // 3 strings to match.
    4009           0 :                 if (memcmp(Mnemonic.data()+7, "ru_f", 4) != 0)
    4010             :                   break;
    4011             :                 switch (Mnemonic[11]) {
    4012             :                 default: break;
    4013             :                 case '1':        // 1 string to match.
    4014           0 :                   if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4015             :                     break;
    4016           0 :                   Mnemonic = "v_cmp_tru_f16";  // "v_cmp_tru_f16_e64"
    4017           0 :                   return;
    4018             :                 case '3':        // 1 string to match.
    4019           0 :                   if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4020             :                     break;
    4021           0 :                   Mnemonic = "v_cmp_tru_f32";  // "v_cmp_tru_f32_e64"
    4022           0 :                   return;
    4023             :                 case '6':        // 1 string to match.
    4024           0 :                   if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4025             :                     break;
    4026           0 :                   Mnemonic = "v_cmp_tru_f64";  // "v_cmp_tru_f64_e64"
    4027           0 :                   return;
    4028             :                 }
    4029             :                 break;
    4030             :               }
    4031             :               break;
    4032           0 :             case 's':    // 18 strings to match.
    4033             :               switch (Mnemonic[6]) {
    4034             :               default: break;
    4035           0 :               case '_':  // 12 strings to match.
    4036             :                 switch (Mnemonic[7]) {
    4037             :                 default: break;
    4038             :                 case 'e':        // 2 strings to match.
    4039           0 :                   if (memcmp(Mnemonic.data()+8, "q_f", 3) != 0)
    4040             :                     break;
    4041             :                   switch (Mnemonic[11]) {
    4042             :                   default: break;
    4043             :                   case '3':      // 1 string to match.
    4044           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4045             :                       break;
    4046           0 :                     Mnemonic = "v_cmps_eq_f32";        // "v_cmps_eq_f32_e64"
    4047           0 :                     return;
    4048             :                   case '6':      // 1 string to match.
    4049           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4050             :                       break;
    4051           0 :                     Mnemonic = "v_cmps_eq_f64";        // "v_cmps_eq_f64_e64"
    4052           0 :                     return;
    4053             :                   }
    4054             :                   break;
    4055           0 :                 case 'g':        // 4 strings to match.
    4056             :                   switch (Mnemonic[8]) {
    4057             :                   default: break;
    4058             :                   case 'e':      // 2 strings to match.
    4059           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4060             :                       break;
    4061             :                     switch (Mnemonic[11]) {
    4062             :                     default: break;
    4063             :                     case '3':    // 1 string to match.
    4064           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4065             :                         break;
    4066           0 :                       Mnemonic = "v_cmps_ge_f32";      // "v_cmps_ge_f32_e64"
    4067           0 :                       return;
    4068             :                     case '6':    // 1 string to match.
    4069           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4070             :                         break;
    4071           0 :                       Mnemonic = "v_cmps_ge_f64";      // "v_cmps_ge_f64_e64"
    4072           0 :                       return;
    4073             :                     }
    4074             :                     break;
    4075             :                   case 't':      // 2 strings to match.
    4076           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4077             :                       break;
    4078             :                     switch (Mnemonic[11]) {
    4079             :                     default: break;
    4080             :                     case '3':    // 1 string to match.
    4081           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4082             :                         break;
    4083           0 :                       Mnemonic = "v_cmps_gt_f32";      // "v_cmps_gt_f32_e64"
    4084           0 :                       return;
    4085             :                     case '6':    // 1 string to match.
    4086           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4087             :                         break;
    4088           0 :                       Mnemonic = "v_cmps_gt_f64";      // "v_cmps_gt_f64_e64"
    4089           0 :                       return;
    4090             :                     }
    4091             :                     break;
    4092             :                   }
    4093             :                   break;
    4094           0 :                 case 'l':        // 6 strings to match.
    4095             :                   switch (Mnemonic[8]) {
    4096             :                   default: break;
    4097             :                   case 'e':      // 2 strings to match.
    4098           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4099             :                       break;
    4100             :                     switch (Mnemonic[11]) {
    4101             :                     default: break;
    4102             :                     case '3':    // 1 string to match.
    4103           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4104             :                         break;
    4105           0 :                       Mnemonic = "v_cmps_le_f32";      // "v_cmps_le_f32_e64"
    4106           0 :                       return;
    4107             :                     case '6':    // 1 string to match.
    4108           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4109             :                         break;
    4110           0 :                       Mnemonic = "v_cmps_le_f64";      // "v_cmps_le_f64_e64"
    4111           0 :                       return;
    4112             :                     }
    4113             :                     break;
    4114             :                   case 'g':      // 2 strings to match.
    4115           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4116             :                       break;
    4117             :                     switch (Mnemonic[11]) {
    4118             :                     default: break;
    4119             :                     case '3':    // 1 string to match.
    4120           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4121             :                         break;
    4122           0 :                       Mnemonic = "v_cmps_lg_f32";      // "v_cmps_lg_f32_e64"
    4123           0 :                       return;
    4124             :                     case '6':    // 1 string to match.
    4125           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4126             :                         break;
    4127           0 :                       Mnemonic = "v_cmps_lg_f64";      // "v_cmps_lg_f64_e64"
    4128           0 :                       return;
    4129             :                     }
    4130             :                     break;
    4131             :                   case 't':      // 2 strings to match.
    4132           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4133             :                       break;
    4134             :                     switch (Mnemonic[11]) {
    4135             :                     default: break;
    4136             :                     case '3':    // 1 string to match.
    4137           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4138             :                         break;
    4139           0 :                       Mnemonic = "v_cmps_lt_f32";      // "v_cmps_lt_f32_e64"
    4140           0 :                       return;
    4141             :                     case '6':    // 1 string to match.
    4142           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4143             :                         break;
    4144           0 :                       Mnemonic = "v_cmps_lt_f64";      // "v_cmps_lt_f64_e64"
    4145           0 :                       return;
    4146             :                     }
    4147             :                     break;
    4148             :                   }
    4149             :                   break;
    4150             :                 }
    4151             :                 break;
    4152           0 :               case 'x':  // 6 strings to match.
    4153           0 :                 if (Mnemonic[7] != '_')
    4154             :                   break;
    4155             :                 switch (Mnemonic[8]) {
    4156             :                 default: break;
    4157             :                 case 'f':        // 2 strings to match.
    4158           0 :                   if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4159             :                     break;
    4160             :                   switch (Mnemonic[11]) {
    4161             :                   default: break;
    4162             :                   case '3':      // 1 string to match.
    4163           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4164             :                       break;
    4165           0 :                     Mnemonic = "v_cmpsx_f_f32";        // "v_cmpsx_f_f32_e64"
    4166           0 :                     return;
    4167             :                   case '6':      // 1 string to match.
    4168           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4169             :                       break;
    4170           0 :                     Mnemonic = "v_cmpsx_f_f64";        // "v_cmpsx_f_f64_e64"
    4171           0 :                     return;
    4172             :                   }
    4173             :                   break;
    4174             :                 case 'o':        // 2 strings to match.
    4175           0 :                   if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4176             :                     break;
    4177             :                   switch (Mnemonic[11]) {
    4178             :                   default: break;
    4179             :                   case '3':      // 1 string to match.
    4180           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4181             :                       break;
    4182           0 :                     Mnemonic = "v_cmpsx_o_f32";        // "v_cmpsx_o_f32_e64"
    4183           0 :                     return;
    4184             :                   case '6':      // 1 string to match.
    4185           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4186             :                       break;
    4187           0 :                     Mnemonic = "v_cmpsx_o_f64";        // "v_cmpsx_o_f64_e64"
    4188           0 :                     return;
    4189             :                   }
    4190             :                   break;
    4191             :                 case 'u':        // 2 strings to match.
    4192           0 :                   if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4193             :                     break;
    4194             :                   switch (Mnemonic[11]) {
    4195             :                   default: break;
    4196             :                   case '3':      // 1 string to match.
    4197           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4198             :                       break;
    4199           0 :                     Mnemonic = "v_cmpsx_u_f32";        // "v_cmpsx_u_f32_e64"
    4200           0 :                     return;
    4201             :                   case '6':      // 1 string to match.
    4202           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4203             :                       break;
    4204           0 :                     Mnemonic = "v_cmpsx_u_f64";        // "v_cmpsx_u_f64_e64"
    4205           0 :                     return;
    4206             :                   }
    4207             :                   break;
    4208             :                 }
    4209             :                 break;
    4210             :               }
    4211             :               break;
    4212           0 :             case 'x':    // 54 strings to match.
    4213           0 :               if (Mnemonic[6] != '_')
    4214             :                 break;
    4215             :               switch (Mnemonic[7]) {
    4216             :               default: break;
    4217             :               case 'e':  // 9 strings to match.
    4218           0 :                 if (memcmp(Mnemonic.data()+8, "q_", 2) != 0)
    4219             :                   break;
    4220             :                 switch (Mnemonic[10]) {
    4221             :                 default: break;
    4222           0 :                 case 'f':        // 3 strings to match.
    4223             :                   switch (Mnemonic[11]) {
    4224             :                   default: break;
    4225             :                   case '1':      // 1 string to match.
    4226           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4227             :                       break;
    4228           0 :                     Mnemonic = "v_cmpx_eq_f16";        // "v_cmpx_eq_f16_e64"
    4229           0 :                     return;
    4230             :                   case '3':      // 1 string to match.
    4231           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4232             :                       break;
    4233           0 :                     Mnemonic = "v_cmpx_eq_f32";        // "v_cmpx_eq_f32_e64"
    4234           0 :                     return;
    4235             :                   case '6':      // 1 string to match.
    4236           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4237             :                       break;
    4238           0 :                     Mnemonic = "v_cmpx_eq_f64";        // "v_cmpx_eq_f64_e64"
    4239           0 :                     return;
    4240             :                   }
    4241             :                   break;
    4242           0 :                 case 'i':        // 3 strings to match.
    4243             :                   switch (Mnemonic[11]) {
    4244             :                   default: break;
    4245             :                   case '1':      // 1 string to match.
    4246           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4247             :                       break;
    4248           0 :                     Mnemonic = "v_cmpx_eq_i16";        // "v_cmpx_eq_i16_e64"
    4249           0 :                     return;
    4250             :                   case '3':      // 1 string to match.
    4251           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4252             :                       break;
    4253           0 :                     Mnemonic = "v_cmpx_eq_i32";        // "v_cmpx_eq_i32_e64"
    4254           0 :                     return;
    4255             :                   case '6':      // 1 string to match.
    4256           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4257             :                       break;
    4258           0 :                     Mnemonic = "v_cmpx_eq_i64";        // "v_cmpx_eq_i64_e64"
    4259           0 :                     return;
    4260             :                   }
    4261             :                   break;
    4262           0 :                 case 'u':        // 3 strings to match.
    4263             :                   switch (Mnemonic[11]) {
    4264             :                   default: break;
    4265             :                   case '1':      // 1 string to match.
    4266           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4267             :                       break;
    4268           0 :                     Mnemonic = "v_cmpx_eq_u16";        // "v_cmpx_eq_u16_e64"
    4269           0 :                     return;
    4270             :                   case '3':      // 1 string to match.
    4271           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4272             :                       break;
    4273           0 :                     Mnemonic = "v_cmpx_eq_u32";        // "v_cmpx_eq_u32_e64"
    4274           0 :                     return;
    4275             :                   case '6':      // 1 string to match.
    4276           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4277             :                       break;
    4278           0 :                     Mnemonic = "v_cmpx_eq_u64";        // "v_cmpx_eq_u64_e64"
    4279           0 :                     return;
    4280             :                   }
    4281             :                   break;
    4282             :                 }
    4283             :                 break;
    4284           0 :               case 'g':  // 18 strings to match.
    4285             :                 switch (Mnemonic[8]) {
    4286             :                 default: break;
    4287           0 :                 case 'e':        // 9 strings to match.
    4288           0 :                   if (Mnemonic[9] != '_')
    4289             :                     break;
    4290             :                   switch (Mnemonic[10]) {
    4291             :                   default: break;
    4292           0 :                   case 'f':      // 3 strings to match.
    4293             :                     switch (Mnemonic[11]) {
    4294             :                     default: break;
    4295             :                     case '1':    // 1 string to match.
    4296           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4297             :                         break;
    4298           0 :                       Mnemonic = "v_cmpx_ge_f16";      // "v_cmpx_ge_f16_e64"
    4299           0 :                       return;
    4300             :                     case '3':    // 1 string to match.
    4301           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4302             :                         break;
    4303           0 :                       Mnemonic = "v_cmpx_ge_f32";      // "v_cmpx_ge_f32_e64"
    4304           0 :                       return;
    4305             :                     case '6':    // 1 string to match.
    4306           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4307             :                         break;
    4308           0 :                       Mnemonic = "v_cmpx_ge_f64";      // "v_cmpx_ge_f64_e64"
    4309           0 :                       return;
    4310             :                     }
    4311             :                     break;
    4312           0 :                   case 'i':      // 3 strings to match.
    4313             :                     switch (Mnemonic[11]) {
    4314             :                     default: break;
    4315             :                     case '1':    // 1 string to match.
    4316           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4317             :                         break;
    4318           0 :                       Mnemonic = "v_cmpx_ge_i16";      // "v_cmpx_ge_i16_e64"
    4319           0 :                       return;
    4320             :                     case '3':    // 1 string to match.
    4321           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4322             :                         break;
    4323           0 :                       Mnemonic = "v_cmpx_ge_i32";      // "v_cmpx_ge_i32_e64"
    4324           0 :                       return;
    4325             :                     case '6':    // 1 string to match.
    4326           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4327             :                         break;
    4328           0 :                       Mnemonic = "v_cmpx_ge_i64";      // "v_cmpx_ge_i64_e64"
    4329           0 :                       return;
    4330             :                     }
    4331             :                     break;
    4332           0 :                   case 'u':      // 3 strings to match.
    4333             :                     switch (Mnemonic[11]) {
    4334             :                     default: break;
    4335             :                     case '1':    // 1 string to match.
    4336           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4337             :                         break;
    4338           0 :                       Mnemonic = "v_cmpx_ge_u16";      // "v_cmpx_ge_u16_e64"
    4339           0 :                       return;
    4340             :                     case '3':    // 1 string to match.
    4341           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4342             :                         break;
    4343           0 :                       Mnemonic = "v_cmpx_ge_u32";      // "v_cmpx_ge_u32_e64"
    4344           0 :                       return;
    4345             :                     case '6':    // 1 string to match.
    4346           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4347             :                         break;
    4348           0 :                       Mnemonic = "v_cmpx_ge_u64";      // "v_cmpx_ge_u64_e64"
    4349           0 :                       return;
    4350             :                     }
    4351             :                     break;
    4352             :                   }
    4353             :                   break;
    4354           0 :                 case 't':        // 9 strings to match.
    4355           0 :                   if (Mnemonic[9] != '_')
    4356             :                     break;
    4357             :                   switch (Mnemonic[10]) {
    4358             :                   default: break;
    4359           0 :                   case 'f':      // 3 strings to match.
    4360             :                     switch (Mnemonic[11]) {
    4361             :                     default: break;
    4362             :                     case '1':    // 1 string to match.
    4363           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4364             :                         break;
    4365           0 :                       Mnemonic = "v_cmpx_gt_f16";      // "v_cmpx_gt_f16_e64"
    4366           0 :                       return;
    4367             :                     case '3':    // 1 string to match.
    4368           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4369             :                         break;
    4370           0 :                       Mnemonic = "v_cmpx_gt_f32";      // "v_cmpx_gt_f32_e64"
    4371           0 :                       return;
    4372             :                     case '6':    // 1 string to match.
    4373           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4374             :                         break;
    4375           0 :                       Mnemonic = "v_cmpx_gt_f64";      // "v_cmpx_gt_f64_e64"
    4376           0 :                       return;
    4377             :                     }
    4378             :                     break;
    4379           0 :                   case 'i':      // 3 strings to match.
    4380             :                     switch (Mnemonic[11]) {
    4381             :                     default: break;
    4382             :                     case '1':    // 1 string to match.
    4383           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4384             :                         break;
    4385           0 :                       Mnemonic = "v_cmpx_gt_i16";      // "v_cmpx_gt_i16_e64"
    4386           0 :                       return;
    4387             :                     case '3':    // 1 string to match.
    4388           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4389             :                         break;
    4390           0 :                       Mnemonic = "v_cmpx_gt_i32";      // "v_cmpx_gt_i32_e64"
    4391           0 :                       return;
    4392             :                     case '6':    // 1 string to match.
    4393           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4394             :                         break;
    4395           0 :                       Mnemonic = "v_cmpx_gt_i64";      // "v_cmpx_gt_i64_e64"
    4396           0 :                       return;
    4397             :                     }
    4398             :                     break;
    4399           0 :                   case 'u':      // 3 strings to match.
    4400             :                     switch (Mnemonic[11]) {
    4401             :                     default: break;
    4402             :                     case '1':    // 1 string to match.
    4403           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4404             :                         break;
    4405           0 :                       Mnemonic = "v_cmpx_gt_u16";      // "v_cmpx_gt_u16_e64"
    4406           0 :                       return;
    4407             :                     case '3':    // 1 string to match.
    4408           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4409             :                         break;
    4410           0 :                       Mnemonic = "v_cmpx_gt_u32";      // "v_cmpx_gt_u32_e64"
    4411           0 :                       return;
    4412             :                     case '6':    // 1 string to match.
    4413           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4414             :                         break;
    4415           0 :                       Mnemonic = "v_cmpx_gt_u64";      // "v_cmpx_gt_u64_e64"
    4416           0 :                       return;
    4417             :                     }
    4418             :                     break;
    4419             :                   }
    4420             :                   break;
    4421             :                 }
    4422             :                 break;
    4423           0 :               case 'l':  // 21 strings to match.
    4424             :                 switch (Mnemonic[8]) {
    4425             :                 default: break;
    4426           0 :                 case 'e':        // 9 strings to match.
    4427           0 :                   if (Mnemonic[9] != '_')
    4428             :                     break;
    4429             :                   switch (Mnemonic[10]) {
    4430             :                   default: break;
    4431           0 :                   case 'f':      // 3 strings to match.
    4432             :                     switch (Mnemonic[11]) {
    4433             :                     default: break;
    4434             :                     case '1':    // 1 string to match.
    4435           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4436             :                         break;
    4437           0 :                       Mnemonic = "v_cmpx_le_f16";      // "v_cmpx_le_f16_e64"
    4438           0 :                       return;
    4439             :                     case '3':    // 1 string to match.
    4440           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4441             :                         break;
    4442           0 :                       Mnemonic = "v_cmpx_le_f32";      // "v_cmpx_le_f32_e64"
    4443           0 :                       return;
    4444             :                     case '6':    // 1 string to match.
    4445           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4446             :                         break;
    4447           0 :                       Mnemonic = "v_cmpx_le_f64";      // "v_cmpx_le_f64_e64"
    4448           0 :                       return;
    4449             :                     }
    4450             :                     break;
    4451           0 :                   case 'i':      // 3 strings to match.
    4452             :                     switch (Mnemonic[11]) {
    4453             :                     default: break;
    4454             :                     case '1':    // 1 string to match.
    4455           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4456             :                         break;
    4457           0 :                       Mnemonic = "v_cmpx_le_i16";      // "v_cmpx_le_i16_e64"
    4458           0 :                       return;
    4459             :                     case '3':    // 1 string to match.
    4460           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4461             :                         break;
    4462           0 :                       Mnemonic = "v_cmpx_le_i32";      // "v_cmpx_le_i32_e64"
    4463           0 :                       return;
    4464             :                     case '6':    // 1 string to match.
    4465           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4466             :                         break;
    4467           0 :                       Mnemonic = "v_cmpx_le_i64";      // "v_cmpx_le_i64_e64"
    4468           0 :                       return;
    4469             :                     }
    4470             :                     break;
    4471           0 :                   case 'u':      // 3 strings to match.
    4472             :                     switch (Mnemonic[11]) {
    4473             :                     default: break;
    4474             :                     case '1':    // 1 string to match.
    4475           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4476             :                         break;
    4477           0 :                       Mnemonic = "v_cmpx_le_u16";      // "v_cmpx_le_u16_e64"
    4478           0 :                       return;
    4479             :                     case '3':    // 1 string to match.
    4480           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4481             :                         break;
    4482           0 :                       Mnemonic = "v_cmpx_le_u32";      // "v_cmpx_le_u32_e64"
    4483           0 :                       return;
    4484             :                     case '6':    // 1 string to match.
    4485           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4486             :                         break;
    4487           0 :                       Mnemonic = "v_cmpx_le_u64";      // "v_cmpx_le_u64_e64"
    4488           0 :                       return;
    4489             :                     }
    4490             :                     break;
    4491             :                   }
    4492             :                   break;
    4493             :                 case 'g':        // 3 strings to match.
    4494           0 :                   if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    4495             :                     break;
    4496             :                   switch (Mnemonic[11]) {
    4497             :                   default: break;
    4498             :                   case '1':      // 1 string to match.
    4499           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4500             :                       break;
    4501           0 :                     Mnemonic = "v_cmpx_lg_f16";        // "v_cmpx_lg_f16_e64"
    4502           0 :                     return;
    4503             :                   case '3':      // 1 string to match.
    4504           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4505             :                       break;
    4506           0 :                     Mnemonic = "v_cmpx_lg_f32";        // "v_cmpx_lg_f32_e64"
    4507           0 :                     return;
    4508             :                   case '6':      // 1 string to match.
    4509           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4510             :                       break;
    4511           0 :                     Mnemonic = "v_cmpx_lg_f64";        // "v_cmpx_lg_f64_e64"
    4512           0 :                     return;
    4513             :                   }
    4514             :                   break;
    4515           0 :                 case 't':        // 9 strings to match.
    4516           0 :                   if (Mnemonic[9] != '_')
    4517             :                     break;
    4518             :                   switch (Mnemonic[10]) {
    4519             :                   default: break;
    4520           0 :                   case 'f':      // 3 strings to match.
    4521             :                     switch (Mnemonic[11]) {
    4522             :                     default: break;
    4523             :                     case '1':    // 1 string to match.
    4524           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4525             :                         break;
    4526           0 :                       Mnemonic = "v_cmpx_lt_f16";      // "v_cmpx_lt_f16_e64"
    4527           0 :                       return;
    4528             :                     case '3':    // 1 string to match.
    4529           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4530             :                         break;
    4531           0 :                       Mnemonic = "v_cmpx_lt_f32";      // "v_cmpx_lt_f32_e64"
    4532           0 :                       return;
    4533             :                     case '6':    // 1 string to match.
    4534           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4535             :                         break;
    4536           0 :                       Mnemonic = "v_cmpx_lt_f64";      // "v_cmpx_lt_f64_e64"
    4537           0 :                       return;
    4538             :                     }
    4539             :                     break;
    4540           0 :                   case 'i':      // 3 strings to match.
    4541             :                     switch (Mnemonic[11]) {
    4542             :                     default: break;
    4543             :                     case '1':    // 1 string to match.
    4544           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4545             :                         break;
    4546           0 :                       Mnemonic = "v_cmpx_lt_i16";      // "v_cmpx_lt_i16_e64"
    4547           0 :                       return;
    4548             :                     case '3':    // 1 string to match.
    4549           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4550             :                         break;
    4551           0 :                       Mnemonic = "v_cmpx_lt_i32";      // "v_cmpx_lt_i32_e64"
    4552           0 :                       return;
    4553             :                     case '6':    // 1 string to match.
    4554           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4555             :                         break;
    4556           0 :                       Mnemonic = "v_cmpx_lt_i64";      // "v_cmpx_lt_i64_e64"
    4557           0 :                       return;
    4558             :                     }
    4559             :                     break;
    4560           0 :                   case 'u':      // 3 strings to match.
    4561             :                     switch (Mnemonic[11]) {
    4562             :                     default: break;
    4563             :                     case '1':    // 1 string to match.
    4564           0 :                       if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4565             :                         break;
    4566           0 :                       Mnemonic = "v_cmpx_lt_u16";      // "v_cmpx_lt_u16_e64"
    4567           0 :                       return;
    4568             :                     case '3':    // 1 string to match.
    4569           0 :                       if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4570             :                         break;
    4571           0 :                       Mnemonic = "v_cmpx_lt_u32";      // "v_cmpx_lt_u32_e64"
    4572           0 :                       return;
    4573             :                     case '6':    // 1 string to match.
    4574           0 :                       if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4575             :                         break;
    4576           0 :                       Mnemonic = "v_cmpx_lt_u64";      // "v_cmpx_lt_u64_e64"
    4577           0 :                       return;
    4578             :                     }
    4579             :                     break;
    4580             :                   }
    4581             :                   break;
    4582             :                 }
    4583             :                 break;
    4584             :               case 'n':  // 6 strings to match.
    4585           0 :                 if (memcmp(Mnemonic.data()+8, "e_", 2) != 0)
    4586             :                   break;
    4587             :                 switch (Mnemonic[10]) {
    4588             :                 default: break;
    4589           0 :                 case 'i':        // 3 strings to match.
    4590             :                   switch (Mnemonic[11]) {
    4591             :                   default: break;
    4592             :                   case '1':      // 1 string to match.
    4593           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4594             :                       break;
    4595           0 :                     Mnemonic = "v_cmpx_ne_i16";        // "v_cmpx_ne_i16_e64"
    4596           0 :                     return;
    4597             :                   case '3':      // 1 string to match.
    4598           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4599             :                       break;
    4600           0 :                     Mnemonic = "v_cmpx_ne_i32";        // "v_cmpx_ne_i32_e64"
    4601           0 :                     return;
    4602             :                   case '6':      // 1 string to match.
    4603           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4604             :                       break;
    4605           0 :                     Mnemonic = "v_cmpx_ne_i64";        // "v_cmpx_ne_i64_e64"
    4606           0 :                     return;
    4607             :                   }
    4608             :                   break;
    4609           0 :                 case 'u':        // 3 strings to match.
    4610             :                   switch (Mnemonic[11]) {
    4611             :                   default: break;
    4612             :                   case '1':      // 1 string to match.
    4613           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4614             :                       break;
    4615           0 :                     Mnemonic = "v_cmpx_ne_u16";        // "v_cmpx_ne_u16_e64"
    4616           0 :                     return;
    4617             :                   case '3':      // 1 string to match.
    4618           0 :                     if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4619             :                       break;
    4620           0 :                     Mnemonic = "v_cmpx_ne_u32";        // "v_cmpx_ne_u32_e64"
    4621           0 :                     return;
    4622             :                   case '6':      // 1 string to match.
    4623           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4624             :                       break;
    4625           0 :                     Mnemonic = "v_cmpx_ne_u64";        // "v_cmpx_ne_u64_e64"
    4626           0 :                     return;
    4627             :                   }
    4628             :                   break;
    4629             :                 }
    4630             :                 break;
    4631             :               }
    4632             :               break;
    4633             :             }
    4634             :             break;
    4635             :           case 'n':      // 1 string to match.
    4636           0 :             if (memcmp(Mnemonic.data()+4, "dmask_b32_e64", 13) != 0)
    4637             :               break;
    4638           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_cndmask_b32_e64"
    4639           0 :               Mnemonic = "v_cndmask_b32";
    4640             :             return;
    4641             :           case 'v':      // 16 strings to match.
    4642         186 :             if (memcmp(Mnemonic.data()+4, "t_", 2) != 0)
    4643             :               break;
    4644             :             switch (Mnemonic[6]) {
    4645             :             default: break;
    4646          93 :             case 'f':    // 10 strings to match.
    4647             :               switch (Mnemonic[7]) {
    4648             :               default: break;
    4649             :               case '1':  // 3 strings to match.
    4650           0 :                 if (memcmp(Mnemonic.data()+8, "6_", 2) != 0)
    4651             :                   break;
    4652             :                 switch (Mnemonic[10]) {
    4653             :                 default: break;
    4654             :                 case 'f':        // 1 string to match.
    4655           0 :                   if (memcmp(Mnemonic.data()+11, "32_e64", 6) != 0)
    4656             :                     break;
    4657           0 :                   Mnemonic = "v_cvt_f16_f32";  // "v_cvt_f16_f32_e64"
    4658           0 :                   return;
    4659             :                 case 'i':        // 1 string to match.
    4660           0 :                   if (memcmp(Mnemonic.data()+11, "16_e64", 6) != 0)
    4661             :                     break;
    4662           0 :                   Mnemonic = "v_cvt_f16_i16";  // "v_cvt_f16_i16_e64"
    4663           0 :                   return;
    4664             :                 case 'u':        // 1 string to match.
    4665           0 :                   if (memcmp(Mnemonic.data()+11, "16_e64", 6) != 0)
    4666             :                     break;
    4667           0 :                   Mnemonic = "v_cvt_f16_u16";  // "v_cvt_f16_u16_e64"
    4668           0 :                   return;
    4669             :                 }
    4670             :                 break;
    4671             :               case '3':  // 4 strings to match.
    4672           0 :                 if (memcmp(Mnemonic.data()+8, "2_", 2) != 0)
    4673             :                   break;
    4674             :                 switch (Mnemonic[10]) {
    4675             :                 default: break;
    4676           0 :                 case 'f':        // 2 strings to match.
    4677             :                   switch (Mnemonic[11]) {
    4678             :                   default: break;
    4679             :                   case '1':      // 1 string to match.
    4680           0 :                     if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4681             :                       break;
    4682           0 :                     Mnemonic = "v_cvt_f32_f16";        // "v_cvt_f32_f16_e64"
    4683           0 :                     return;
    4684             :                   case '6':      // 1 string to match.
    4685           0 :                     if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4686             :                       break;
    4687           0 :                     Mnemonic = "v_cvt_f32_f64";        // "v_cvt_f32_f64_e64"
    4688           0 :                     return;
    4689             :                   }
    4690             :                   break;
    4691             :                 case 'i':        // 1 string to match.
    4692           0 :                   if (memcmp(Mnemonic.data()+11, "32_e64", 6) != 0)
    4693             :                     break;
    4694           0 :                   Mnemonic = "v_cvt_f32_i32";  // "v_cvt_f32_i32_e64"
    4695           0 :                   return;
    4696             :                 case 'u':        // 1 string to match.
    4697           0 :                   if (memcmp(Mnemonic.data()+11, "32_e64", 6) != 0)
    4698             :                     break;
    4699           0 :                   Mnemonic = "v_cvt_f32_u32";  // "v_cvt_f32_u32_e64"
    4700           0 :                   return;
    4701             :                 }
    4702             :                 break;
    4703             :               case '6':  // 3 strings to match.
    4704           0 :                 if (memcmp(Mnemonic.data()+8, "4_", 2) != 0)
    4705             :                   break;
    4706             :                 switch (Mnemonic[10]) {
    4707             :                 default: break;
    4708             :                 case 'f':        // 1 string to match.
    4709           0 :                   if (memcmp(Mnemonic.data()+11, "32_e64", 6) != 0)
    4710             :                     break;
    4711           0 :                   Mnemonic = "v_cvt_f64_f32";  // "v_cvt_f64_f32_e64"
    4712           0 :                   return;
    4713             :                 case 'i':        // 1 string to match.
    4714           0 :                   if (memcmp(Mnemonic.data()+11, "32_e64", 6) != 0)
    4715             :                     break;
    4716           0 :                   Mnemonic = "v_cvt_f64_i32";  // "v_cvt_f64_i32_e64"
    4717           0 :                   return;
    4718             :                 case 'u':        // 1 string to match.
    4719           0 :                   if (memcmp(Mnemonic.data()+11, "32_e64", 6) != 0)
    4720             :                     break;
    4721           0 :                   Mnemonic = "v_cvt_f64_u32";  // "v_cvt_f64_u32_e64"
    4722           0 :                   return;
    4723             :                 }
    4724             :                 break;
    4725             :               }
    4726             :               break;
    4727           0 :             case 'i':    // 3 strings to match.
    4728             :               switch (Mnemonic[7]) {
    4729             :               default: break;
    4730             :               case '1':  // 1 string to match.
    4731           0 :                 if (memcmp(Mnemonic.data()+8, "6_f16_e64", 9) != 0)
    4732             :                   break;
    4733           0 :                 Mnemonic = "v_cvt_i16_f16";    // "v_cvt_i16_f16_e64"
    4734           0 :                 return;
    4735             :               case '3':  // 2 strings to match.
    4736           0 :                 if (memcmp(Mnemonic.data()+8, "2_f", 3) != 0)
    4737             :                   break;
    4738             :                 switch (Mnemonic[11]) {
    4739             :                 default: break;
    4740             :                 case '3':        // 1 string to match.
    4741           0 :                   if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4742             :                     break;
    4743           0 :                   Mnemonic = "v_cvt_i32_f32";  // "v_cvt_i32_f32_e64"
    4744           0 :                   return;
    4745             :                 case '6':        // 1 string to match.
    4746           0 :                   if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4747             :                     break;
    4748           0 :                   Mnemonic = "v_cvt_i32_f64";  // "v_cvt_i32_f64_e64"
    4749           0 :                   return;
    4750             :                 }
    4751             :                 break;
    4752             :               }
    4753             :               break;
    4754           0 :             case 'u':    // 3 strings to match.
    4755             :               switch (Mnemonic[7]) {
    4756             :               default: break;
    4757             :               case '1':  // 1 string to match.
    4758           0 :                 if (memcmp(Mnemonic.data()+8, "6_f16_e64", 9) != 0)
    4759             :                   break;
    4760           0 :                 Mnemonic = "v_cvt_u16_f16";    // "v_cvt_u16_f16_e64"
    4761           0 :                 return;
    4762             :               case '3':  // 2 strings to match.
    4763           0 :                 if (memcmp(Mnemonic.data()+8, "2_f", 3) != 0)
    4764             :                   break;
    4765             :                 switch (Mnemonic[11]) {
    4766             :                 default: break;
    4767             :                 case '3':        // 1 string to match.
    4768           0 :                   if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4769             :                     break;
    4770           0 :                   Mnemonic = "v_cvt_u32_f32";  // "v_cvt_u32_f32_e64"
    4771           0 :                   return;
    4772             :                 case '6':        // 1 string to match.
    4773           0 :                   if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4774             :                     break;
    4775           0 :                   Mnemonic = "v_cvt_u32_f64";  // "v_cvt_u32_f64_e64"
    4776           0 :                   return;
    4777             :                 }
    4778             :                 break;
    4779             :               }
    4780             :               break;
    4781             :             }
    4782             :             break;
    4783             :           }
    4784             :           break;
    4785             :         case 'd':        // 4 strings to match.
    4786           0 :           if (memcmp(Mnemonic.data()+3, "ot", 2) != 0)
    4787             :             break;
    4788             :           switch (Mnemonic[5]) {
    4789             :           default: break;
    4790           0 :           case '4':      // 2 strings to match.
    4791           0 :             if (Mnemonic[6] != '_')
    4792             :               break;
    4793             :             switch (Mnemonic[7]) {
    4794             :             default: break;
    4795             :             case 'i':    // 1 string to match.
    4796           0 :               if (memcmp(Mnemonic.data()+8, "32_i8_e64", 9) != 0)
    4797             :                 break;
    4798           0 :               Mnemonic = "v_dot4_i32_i8";      // "v_dot4_i32_i8_e64"
    4799           0 :               return;
    4800             :             case 'u':    // 1 string to match.
    4801           0 :               if (memcmp(Mnemonic.data()+8, "32_u8_e64", 9) != 0)
    4802             :                 break;
    4803           0 :               Mnemonic = "v_dot4_u32_u8";      // "v_dot4_u32_u8_e64"
    4804           0 :               return;
    4805             :             }
    4806             :             break;
    4807           0 :           case '8':      // 2 strings to match.
    4808           0 :             if (Mnemonic[6] != '_')
    4809             :               break;
    4810             :             switch (Mnemonic[7]) {
    4811             :             default: break;
    4812             :             case 'i':    // 1 string to match.
    4813           0 :               if (memcmp(Mnemonic.data()+8, "32_i4_e64", 9) != 0)
    4814             :                 break;
    4815           0 :               Mnemonic = "v_dot8_i32_i4";      // "v_dot8_i32_i4_e64"
    4816           0 :               return;
    4817             :             case 'u':    // 1 string to match.
    4818           0 :               if (memcmp(Mnemonic.data()+8, "32_u4_e64", 9) != 0)
    4819             :                 break;
    4820           0 :               Mnemonic = "v_dot8_u32_u4";      // "v_dot8_u32_u4_e64"
    4821           0 :               return;
    4822             :             }
    4823             :             break;
    4824             :           }
    4825             :           break;
    4826             :         case 'f':        // 1 string to match.
    4827           0 :           if (memcmp(Mnemonic.data()+3, "ma_mix_f32_e64", 14) != 0)
    4828             :             break;
    4829           0 :           Mnemonic = "v_fma_mix_f32";  // "v_fma_mix_f32_e64"
    4830           0 :           return;
    4831             :         case 'l':        // 7 strings to match.
    4832           0 :           if (memcmp(Mnemonic.data()+3, "sh", 2) != 0)
    4833             :             break;
    4834             :           switch (Mnemonic[5]) {
    4835             :           default: break;
    4836           0 :           case 'l':      // 4 strings to match.
    4837             :             switch (Mnemonic[6]) {
    4838             :             default: break;
    4839             :             case '_':    // 1 string to match.
    4840           0 :               if (memcmp(Mnemonic.data()+7, "or_b32_e64", 10) != 0)
    4841             :                 break;
    4842           0 :               Mnemonic = "v_lshl_or_b32";      // "v_lshl_or_b32_e64"
    4843           0 :               return;
    4844             :             case 'r':    // 3 strings to match.
    4845           0 :               if (memcmp(Mnemonic.data()+7, "ev_b", 4) != 0)
    4846             :                 break;
    4847             :               switch (Mnemonic[11]) {
    4848             :               default: break;
    4849             :               case '1':  // 1 string to match.
    4850           0 :                 if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4851             :                   break;
    4852           0 :                 Mnemonic = "v_lshlrev_b16";    // "v_lshlrev_b16_e64"
    4853           0 :                 return;
    4854             :               case '3':  // 1 string to match.
    4855           0 :                 if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4856             :                   break;
    4857           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_lshlrev_b32_e64"
    4858           0 :                   Mnemonic = "v_lshlrev_b32";
    4859             :                 return;
    4860             :               case '6':  // 1 string to match.
    4861           0 :                 if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4862             :                   break;
    4863           0 :                 Mnemonic = "v_lshlrev_b64";    // "v_lshlrev_b64_e64"
    4864           0 :                 return;
    4865             :               }
    4866             :               break;
    4867             :             }
    4868             :             break;
    4869             :           case 'r':      // 3 strings to match.
    4870           0 :             if (memcmp(Mnemonic.data()+6, "rev_b", 5) != 0)
    4871             :               break;
    4872             :             switch (Mnemonic[11]) {
    4873             :             default: break;
    4874             :             case '1':    // 1 string to match.
    4875           0 :               if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4876             :                 break;
    4877           0 :               Mnemonic = "v_lshrrev_b16";      // "v_lshrrev_b16_e64"
    4878           0 :               return;
    4879             :             case '3':    // 1 string to match.
    4880           0 :               if (memcmp(Mnemonic.data()+12, "2_e64", 5) != 0)
    4881             :                 break;
    4882           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_lshrrev_b32_e64"
    4883           0 :                 Mnemonic = "v_lshrrev_b32";
    4884             :               return;
    4885             :             case '6':    // 1 string to match.
    4886           0 :               if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4887             :                 break;
    4888           0 :               Mnemonic = "v_lshrrev_b64";      // "v_lshrrev_b64_e64"
    4889           0 :               return;
    4890             :             }
    4891             :             break;
    4892             :           }
    4893             :           break;
    4894         211 :         case 'm':        // 12 strings to match.
    4895             :           switch (Mnemonic[3]) {
    4896             :           default: break;
    4897             :           case 'a':      // 7 strings to match.
    4898           0 :             if (memcmp(Mnemonic.data()+4, "d_", 2) != 0)
    4899             :               break;
    4900             :             switch (Mnemonic[6]) {
    4901             :             default: break;
    4902           0 :             case 'i':    // 3 strings to match.
    4903             :               switch (Mnemonic[7]) {
    4904             :               default: break;
    4905             :               case '3':  // 2 strings to match.
    4906           0 :                 if (memcmp(Mnemonic.data()+8, "2_i", 3) != 0)
    4907             :                   break;
    4908             :                 switch (Mnemonic[11]) {
    4909             :                 default: break;
    4910             :                 case '1':        // 1 string to match.
    4911           0 :                   if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4912             :                     break;
    4913           0 :                   Mnemonic = "v_mad_i32_i16";  // "v_mad_i32_i16_e64"
    4914           0 :                   return;
    4915             :                 case '2':        // 1 string to match.
    4916           0 :                   if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4917             :                     break;
    4918           0 :                   Mnemonic = "v_mad_i32_i24";  // "v_mad_i32_i24_e64"
    4919           0 :                   return;
    4920             :                 }
    4921             :                 break;
    4922             :               case '6':  // 1 string to match.
    4923           0 :                 if (memcmp(Mnemonic.data()+8, "4_i32_e64", 9) != 0)
    4924             :                   break;
    4925           0 :                 Mnemonic = "v_mad_i64_i32";    // "v_mad_i64_i32_e64"
    4926           0 :                 return;
    4927             :               }
    4928             :               break;
    4929             :             case 'm':    // 1 string to match.
    4930           0 :               if (memcmp(Mnemonic.data()+7, "ix_f32_e64", 10) != 0)
    4931             :                 break;
    4932           0 :               Mnemonic = "v_mad_mix_f32";      // "v_mad_mix_f32_e64"
    4933           0 :               return;
    4934           0 :             case 'u':    // 3 strings to match.
    4935             :               switch (Mnemonic[7]) {
    4936             :               default: break;
    4937             :               case '3':  // 2 strings to match.
    4938           0 :                 if (memcmp(Mnemonic.data()+8, "2_u", 3) != 0)
    4939             :                   break;
    4940             :                 switch (Mnemonic[11]) {
    4941             :                 default: break;
    4942             :                 case '1':        // 1 string to match.
    4943           0 :                   if (memcmp(Mnemonic.data()+12, "6_e64", 5) != 0)
    4944             :                     break;
    4945           0 :                   Mnemonic = "v_mad_u32_u16";  // "v_mad_u32_u16_e64"
    4946           0 :                   return;
    4947             :                 case '2':        // 1 string to match.
    4948           0 :                   if (memcmp(Mnemonic.data()+12, "4_e64", 5) != 0)
    4949             :                     break;
    4950           0 :                   Mnemonic = "v_mad_u32_u24";  // "v_mad_u32_u24_e64"
    4951           0 :                   return;
    4952             :                 }
    4953             :                 break;
    4954             :               case '6':  // 1 string to match.
    4955           0 :                 if (memcmp(Mnemonic.data()+8, "4_u32_e64", 9) != 0)
    4956             :                   break;
    4957           0 :                 Mnemonic = "v_mad_u64_u32";    // "v_mad_u64_u32_e64"
    4958           0 :                 return;
    4959             :               }
    4960             :               break;
    4961             :             }
    4962             :             break;
    4963           0 :           case 'o':      // 3 strings to match.
    4964           0 :             if (Mnemonic[4] != 'v')
    4965             :               break;
    4966             :             switch (Mnemonic[5]) {
    4967             :             default: break;
    4968             :             case '_':    // 1 string to match.
    4969           0 :               if (memcmp(Mnemonic.data()+6, "fed_b32_e64", 11) != 0)
    4970             :                 break;
    4971           0 :               Mnemonic = "v_mov_fed_b32";      // "v_mov_fed_b32_e64"
    4972           0 :               return;
    4973             :             case 'r':    // 2 strings to match.
    4974           0 :               if (memcmp(Mnemonic.data()+6, "el", 2) != 0)
    4975             :                 break;
    4976             :               switch (Mnemonic[8]) {
    4977             :               default: break;
    4978             :               case 'd':  // 1 string to match.
    4979           0 :                 if (memcmp(Mnemonic.data()+9, "_b32_e64", 8) != 0)
    4980             :                   break;
    4981           0 :                 Mnemonic = "v_movreld_b32";    // "v_movreld_b32_e64"
    4982           0 :                 return;
    4983             :               case 's':  // 1 string to match.
    4984           0 :                 if (memcmp(Mnemonic.data()+9, "_b32_e64", 8) != 0)
    4985             :                   break;
    4986           0 :                 Mnemonic = "v_movrels_b32";    // "v_movrels_b32_e64"
    4987           0 :                 return;
    4988             :               }
    4989             :               break;
    4990             :             }
    4991             :             break;
    4992             :           case 'u':      // 2 strings to match.
    4993           0 :             if (memcmp(Mnemonic.data()+4, "l_", 2) != 0)
    4994             :               break;
    4995             :             switch (Mnemonic[6]) {
    4996             :             default: break;
    4997             :             case 'i':    // 1 string to match.
    4998           0 :               if (memcmp(Mnemonic.data()+7, "32_i24_e64", 10) != 0)
    4999             :                 break;
    5000           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_i32_i24_e64"
    5001           0 :                 Mnemonic = "v_mul_i32_i24";
    5002             :               return;
    5003             :             case 'u':    // 1 string to match.
    5004           0 :               if (memcmp(Mnemonic.data()+7, "32_u24_e64", 10) != 0)
    5005             :                 break;
    5006           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_u32_u24_e64"
    5007           0 :                 Mnemonic = "v_mul_u32_u24";
    5008             :               return;
    5009             :             }
    5010             :             break;
    5011             :           }
    5012             :           break;
    5013             :         case 's':        // 1 string to match.
    5014           0 :           if (memcmp(Mnemonic.data()+3, "ubbrev_u32_e64", 14) != 0)
    5015             :             break;
    5016           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_subbrev_u32_e64"
    5017           0 :             Mnemonic = "v_subbrev_u32";
    5018             :           return;
    5019             :         }
    5020             :         break;
    5021             :       case 18:   // 65 strings to match.
    5022         447 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    5023             :           break;
    5024             :         switch (Mnemonic[2]) {
    5025             :         default: break;
    5026           0 :         case 'a':        // 3 strings to match.
    5027             :           switch (Mnemonic[3]) {
    5028             :           default: break;
    5029             :           case 'd':      // 2 strings to match.
    5030           0 :             if (memcmp(Mnemonic.data()+4, "d_", 2) != 0)
    5031             :               break;
    5032             :             switch (Mnemonic[6]) {
    5033             :             default: break;
    5034             :             case 'i':    // 1 string to match.
    5035           0 :               if (memcmp(Mnemonic.data()+7, "32_gfx9_e64", 11) != 0)
    5036             :                 break;
    5037           0 :               Mnemonic = "v_add_i32_gfx9";     // "v_add_i32_gfx9_e64"
    5038           0 :               return;
    5039             :             case 'l':    // 1 string to match.
    5040           0 :               if (memcmp(Mnemonic.data()+7, "shl_u32_e64", 11) != 0)
    5041             :                 break;
    5042           0 :               Mnemonic = "v_add_lshl_u32";     // "v_add_lshl_u32_e64"
    5043           0 :               return;
    5044             :             }
    5045             :             break;
    5046             :           case 'l':      // 1 string to match.
    5047           0 :             if (memcmp(Mnemonic.data()+4, "ignbit_b32_e64", 14) != 0)
    5048             :               break;
    5049           0 :             Mnemonic = "v_alignbit_b32";       // "v_alignbit_b32_e64"
    5050           0 :             return;
    5051             :           }
    5052             :           break;
    5053             :         case 'b':        // 1 string to match.
    5054           0 :           if (memcmp(Mnemonic.data()+3, "cnt_u32_b32_e64", 15) != 0)
    5055             :             break;
    5056           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_bcnt_u32_b32_e64"
    5057           0 :             Mnemonic = "v_bcnt_u32_b32";
    5058             :           return;
    5059             :         case 'c':        // 47 strings to match.
    5060          24 :           if (memcmp(Mnemonic.data()+3, "mp", 2) != 0)
    5061             :             break;
    5062             :           switch (Mnemonic[5]) {
    5063             :           default: break;
    5064           0 :           case 's':      // 26 strings to match.
    5065             :             switch (Mnemonic[6]) {
    5066             :             default: break;
    5067           0 :             case '_':    // 14 strings to match.
    5068             :               switch (Mnemonic[7]) {
    5069             :               default: break;
    5070           0 :               case 'n':  // 12 strings to match.
    5071             :                 switch (Mnemonic[8]) {
    5072             :                 default: break;
    5073             :                 case 'e':        // 2 strings to match.
    5074           0 :                   if (memcmp(Mnemonic.data()+9, "q_f", 3) != 0)
    5075             :                     break;
    5076             :                   switch (Mnemonic[12]) {
    5077             :                   default: break;
    5078             :                   case '3':      // 1 string to match.
    5079           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5080             :                       break;
    5081           0 :                     Mnemonic = "v_cmps_neq_f32";       // "v_cmps_neq_f32_e64"
    5082           0 :                     return;
    5083             :                   case '6':      // 1 string to match.
    5084           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5085             :                       break;
    5086           0 :                     Mnemonic = "v_cmps_neq_f64";       // "v_cmps_neq_f64_e64"
    5087           0 :                     return;
    5088             :                   }
    5089             :                   break;
    5090           0 :                 case 'g':        // 4 strings to match.
    5091             :                   switch (Mnemonic[9]) {
    5092             :                   default: break;
    5093             :                   case 'e':      // 2 strings to match.
    5094           0 :                     if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5095             :                       break;
    5096             :                     switch (Mnemonic[12]) {
    5097             :                     default: break;
    5098             :                     case '3':    // 1 string to match.
    5099           0 :                       if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5100             :                         break;
    5101           0 :                       Mnemonic = "v_cmps_nge_f32";     // "v_cmps_nge_f32_e64"
    5102           0 :                       return;
    5103             :                     case '6':    // 1 string to match.
    5104           0 :                       if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5105             :                         break;
    5106           0 :                       Mnemonic = "v_cmps_nge_f64";     // "v_cmps_nge_f64_e64"
    5107           0 :                       return;
    5108             :                     }
    5109             :                     break;
    5110             :                   case 't':      // 2 strings to match.
    5111           0 :                     if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5112             :                       break;
    5113             :                     switch (Mnemonic[12]) {
    5114             :                     default: break;
    5115             :                     case '3':    // 1 string to match.
    5116           0 :                       if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5117             :                         break;
    5118           0 :                       Mnemonic = "v_cmps_ngt_f32";     // "v_cmps_ngt_f32_e64"
    5119           0 :                       return;
    5120             :                     case '6':    // 1 string to match.
    5121           0 :                       if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5122             :                         break;
    5123           0 :                       Mnemonic = "v_cmps_ngt_f64";     // "v_cmps_ngt_f64_e64"
    5124           0 :                       return;
    5125             :                     }
    5126             :                     break;
    5127             :                   }
    5128             :                   break;
    5129           0 :                 case 'l':        // 6 strings to match.
    5130             :                   switch (Mnemonic[9]) {
    5131             :                   default: break;
    5132             :                   case 'e':      // 2 strings to match.
    5133           0 :                     if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5134             :                       break;
    5135             :                     switch (Mnemonic[12]) {
    5136             :                     default: break;
    5137             :                     case '3':    // 1 string to match.
    5138           0 :                       if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5139             :                         break;
    5140           0 :                       Mnemonic = "v_cmps_nle_f32";     // "v_cmps_nle_f32_e64"
    5141           0 :                       return;
    5142             :                     case '6':    // 1 string to match.
    5143           0 :                       if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5144             :                         break;
    5145           0 :                       Mnemonic = "v_cmps_nle_f64";     // "v_cmps_nle_f64_e64"
    5146           0 :                       return;
    5147             :                     }
    5148             :                     break;
    5149             :                   case 'g':      // 2 strings to match.
    5150           0 :                     if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5151             :                       break;
    5152             :                     switch (Mnemonic[12]) {
    5153             :                     default: break;
    5154             :                     case '3':    // 1 string to match.
    5155           0 :                       if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5156             :                         break;
    5157           0 :                       Mnemonic = "v_cmps_nlg_f32";     // "v_cmps_nlg_f32_e64"
    5158           0 :                       return;
    5159             :                     case '6':    // 1 string to match.
    5160           0 :                       if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5161             :                         break;
    5162           0 :                       Mnemonic = "v_cmps_nlg_f64";     // "v_cmps_nlg_f64_e64"
    5163           0 :                       return;
    5164             :                     }
    5165             :                     break;
    5166             :                   case 't':      // 2 strings to match.
    5167           0 :                     if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5168             :                       break;
    5169             :                     switch (Mnemonic[12]) {
    5170             :                     default: break;
    5171             :                     case '3':    // 1 string to match.
    5172           0 :                       if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5173             :                         break;
    5174           0 :                       Mnemonic = "v_cmps_nlt_f32";     // "v_cmps_nlt_f32_e64"
    5175           0 :                       return;
    5176             :                     case '6':    // 1 string to match.
    5177           0 :                       if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5178             :                         break;
    5179           0 :                       Mnemonic = "v_cmps_nlt_f64";     // "v_cmps_nlt_f64_e64"
    5180           0 :                       return;
    5181             :                     }
    5182             :                     break;
    5183             :                   }
    5184             :                   break;
    5185             :                 }
    5186             :                 break;
    5187             :               case 't':  // 2 strings to match.
    5188           0 :                 if (memcmp(Mnemonic.data()+8, "ru_f", 4) != 0)
    5189             :                   break;
    5190             :                 switch (Mnemonic[12]) {
    5191             :                 default: break;
    5192             :                 case '3':        // 1 string to match.
    5193           0 :                   if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5194             :                     break;
    5195           0 :                   Mnemonic = "v_cmps_tru_f32";         // "v_cmps_tru_f32_e64"
    5196           0 :                   return;
    5197             :                 case '6':        // 1 string to match.
    5198           0 :                   if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5199             :                     break;
    5200           0 :                   Mnemonic = "v_cmps_tru_f64";         // "v_cmps_tru_f64_e64"
    5201           0 :                   return;
    5202             :                 }
    5203             :                 break;
    5204             :               }
    5205             :               break;
    5206           0 :             case 'x':    // 12 strings to match.
    5207           0 :               if (Mnemonic[7] != '_')
    5208             :                 break;
    5209             :               switch (Mnemonic[8]) {
    5210             :               default: break;
    5211             :               case 'e':  // 2 strings to match.
    5212           0 :                 if (memcmp(Mnemonic.data()+9, "q_f", 3) != 0)
    5213             :                   break;
    5214             :                 switch (Mnemonic[12]) {
    5215             :                 default: break;
    5216             :                 case '3':        // 1 string to match.
    5217           0 :                   if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5218             :                     break;
    5219           0 :                   Mnemonic = "v_cmpsx_eq_f32";         // "v_cmpsx_eq_f32_e64"
    5220           0 :                   return;
    5221             :                 case '6':        // 1 string to match.
    5222           0 :                   if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5223             :                     break;
    5224           0 :                   Mnemonic = "v_cmpsx_eq_f64";         // "v_cmpsx_eq_f64_e64"
    5225           0 :                   return;
    5226             :                 }
    5227             :                 break;
    5228           0 :               case 'g':  // 4 strings to match.
    5229             :                 switch (Mnemonic[9]) {
    5230             :                 default: break;
    5231             :                 case 'e':        // 2 strings to match.
    5232           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5233             :                     break;
    5234             :                   switch (Mnemonic[12]) {
    5235             :                   default: break;
    5236             :                   case '3':      // 1 string to match.
    5237           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5238             :                       break;
    5239           0 :                     Mnemonic = "v_cmpsx_ge_f32";       // "v_cmpsx_ge_f32_e64"
    5240           0 :                     return;
    5241             :                   case '6':      // 1 string to match.
    5242           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5243             :                       break;
    5244           0 :                     Mnemonic = "v_cmpsx_ge_f64";       // "v_cmpsx_ge_f64_e64"
    5245           0 :                     return;
    5246             :                   }
    5247             :                   break;
    5248             :                 case 't':        // 2 strings to match.
    5249           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5250             :                     break;
    5251             :                   switch (Mnemonic[12]) {
    5252             :                   default: break;
    5253             :                   case '3':      // 1 string to match.
    5254           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5255             :                       break;
    5256           0 :                     Mnemonic = "v_cmpsx_gt_f32";       // "v_cmpsx_gt_f32_e64"
    5257           0 :                     return;
    5258             :                   case '6':      // 1 string to match.
    5259           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5260             :                       break;
    5261           0 :                     Mnemonic = "v_cmpsx_gt_f64";       // "v_cmpsx_gt_f64_e64"
    5262           0 :                     return;
    5263             :                   }
    5264             :                   break;
    5265             :                 }
    5266             :                 break;
    5267           0 :               case 'l':  // 6 strings to match.
    5268             :                 switch (Mnemonic[9]) {
    5269             :                 default: break;
    5270             :                 case 'e':        // 2 strings to match.
    5271           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5272             :                     break;
    5273             :                   switch (Mnemonic[12]) {
    5274             :                   default: break;
    5275             :                   case '3':      // 1 string to match.
    5276           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5277             :                       break;
    5278           0 :                     Mnemonic = "v_cmpsx_le_f32";       // "v_cmpsx_le_f32_e64"
    5279           0 :                     return;
    5280             :                   case '6':      // 1 string to match.
    5281           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5282             :                       break;
    5283           0 :                     Mnemonic = "v_cmpsx_le_f64";       // "v_cmpsx_le_f64_e64"
    5284           0 :                     return;
    5285             :                   }
    5286             :                   break;
    5287             :                 case 'g':        // 2 strings to match.
    5288           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5289             :                     break;
    5290             :                   switch (Mnemonic[12]) {
    5291             :                   default: break;
    5292             :                   case '3':      // 1 string to match.
    5293           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5294             :                       break;
    5295           0 :                     Mnemonic = "v_cmpsx_lg_f32";       // "v_cmpsx_lg_f32_e64"
    5296           0 :                     return;
    5297             :                   case '6':      // 1 string to match.
    5298           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5299             :                       break;
    5300           0 :                     Mnemonic = "v_cmpsx_lg_f64";       // "v_cmpsx_lg_f64_e64"
    5301           0 :                     return;
    5302             :                   }
    5303             :                   break;
    5304             :                 case 't':        // 2 strings to match.
    5305           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5306             :                     break;
    5307             :                   switch (Mnemonic[12]) {
    5308             :                   default: break;
    5309             :                   case '3':      // 1 string to match.
    5310           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5311             :                       break;
    5312           0 :                     Mnemonic = "v_cmpsx_lt_f32";       // "v_cmpsx_lt_f32_e64"
    5313           0 :                     return;
    5314             :                   case '6':      // 1 string to match.
    5315           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5316             :                       break;
    5317           0 :                     Mnemonic = "v_cmpsx_lt_f64";       // "v_cmpsx_lt_f64_e64"
    5318           0 :                     return;
    5319             :                   }
    5320             :                   break;
    5321             :                 }
    5322             :                 break;
    5323             :               }
    5324             :               break;
    5325             :             }
    5326             :             break;
    5327           0 :           case 'x':      // 21 strings to match.
    5328           0 :             if (Mnemonic[6] != '_')
    5329             :               break;
    5330             :             switch (Mnemonic[7]) {
    5331             :             default: break;
    5332           0 :             case 'n':    // 18 strings to match.
    5333             :               switch (Mnemonic[8]) {
    5334             :               default: break;
    5335             :               case 'e':  // 3 strings to match.
    5336           0 :                 if (memcmp(Mnemonic.data()+9, "q_f", 3) != 0)
    5337             :                   break;
    5338             :                 switch (Mnemonic[12]) {
    5339             :                 default: break;
    5340             :                 case '1':        // 1 string to match.
    5341           0 :                   if (memcmp(Mnemonic.data()+13, "6_e64", 5) != 0)
    5342             :                     break;
    5343           0 :                   Mnemonic = "v_cmpx_neq_f16";         // "v_cmpx_neq_f16_e64"
    5344           0 :                   return;
    5345             :                 case '3':        // 1 string to match.
    5346           0 :                   if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5347             :                     break;
    5348           0 :                   Mnemonic = "v_cmpx_neq_f32";         // "v_cmpx_neq_f32_e64"
    5349           0 :                   return;
    5350             :                 case '6':        // 1 string to match.
    5351           0 :                   if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5352             :                     break;
    5353           0 :                   Mnemonic = "v_cmpx_neq_f64";         // "v_cmpx_neq_f64_e64"
    5354           0 :                   return;
    5355             :                 }
    5356             :                 break;
    5357           0 :               case 'g':  // 6 strings to match.
    5358             :                 switch (Mnemonic[9]) {
    5359             :                 default: break;
    5360             :                 case 'e':        // 3 strings to match.
    5361           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5362             :                     break;
    5363             :                   switch (Mnemonic[12]) {
    5364             :                   default: break;
    5365             :                   case '1':      // 1 string to match.
    5366           0 :                     if (memcmp(Mnemonic.data()+13, "6_e64", 5) != 0)
    5367             :                       break;
    5368           0 :                     Mnemonic = "v_cmpx_nge_f16";       // "v_cmpx_nge_f16_e64"
    5369           0 :                     return;
    5370             :                   case '3':      // 1 string to match.
    5371           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5372             :                       break;
    5373           0 :                     Mnemonic = "v_cmpx_nge_f32";       // "v_cmpx_nge_f32_e64"
    5374           0 :                     return;
    5375             :                   case '6':      // 1 string to match.
    5376           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5377             :                       break;
    5378           0 :                     Mnemonic = "v_cmpx_nge_f64";       // "v_cmpx_nge_f64_e64"
    5379           0 :                     return;
    5380             :                   }
    5381             :                   break;
    5382             :                 case 't':        // 3 strings to match.
    5383           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5384             :                     break;
    5385             :                   switch (Mnemonic[12]) {
    5386             :                   default: break;
    5387             :                   case '1':      // 1 string to match.
    5388           0 :                     if (memcmp(Mnemonic.data()+13, "6_e64", 5) != 0)
    5389             :                       break;
    5390           0 :                     Mnemonic = "v_cmpx_ngt_f16";       // "v_cmpx_ngt_f16_e64"
    5391           0 :                     return;
    5392             :                   case '3':      // 1 string to match.
    5393           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5394             :                       break;
    5395           0 :                     Mnemonic = "v_cmpx_ngt_f32";       // "v_cmpx_ngt_f32_e64"
    5396           0 :                     return;
    5397             :                   case '6':      // 1 string to match.
    5398           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5399             :                       break;
    5400           0 :                     Mnemonic = "v_cmpx_ngt_f64";       // "v_cmpx_ngt_f64_e64"
    5401           0 :                     return;
    5402             :                   }
    5403             :                   break;
    5404             :                 }
    5405             :                 break;
    5406           0 :               case 'l':  // 9 strings to match.
    5407             :                 switch (Mnemonic[9]) {
    5408             :                 default: break;
    5409             :                 case 'e':        // 3 strings to match.
    5410           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5411             :                     break;
    5412             :                   switch (Mnemonic[12]) {
    5413             :                   default: break;
    5414             :                   case '1':      // 1 string to match.
    5415           0 :                     if (memcmp(Mnemonic.data()+13, "6_e64", 5) != 0)
    5416             :                       break;
    5417           0 :                     Mnemonic = "v_cmpx_nle_f16";       // "v_cmpx_nle_f16_e64"
    5418           0 :                     return;
    5419             :                   case '3':      // 1 string to match.
    5420           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5421             :                       break;
    5422           0 :                     Mnemonic = "v_cmpx_nle_f32";       // "v_cmpx_nle_f32_e64"
    5423           0 :                     return;
    5424             :                   case '6':      // 1 string to match.
    5425           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5426             :                       break;
    5427           0 :                     Mnemonic = "v_cmpx_nle_f64";       // "v_cmpx_nle_f64_e64"
    5428           0 :                     return;
    5429             :                   }
    5430             :                   break;
    5431             :                 case 'g':        // 3 strings to match.
    5432           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5433             :                     break;
    5434             :                   switch (Mnemonic[12]) {
    5435             :                   default: break;
    5436             :                   case '1':      // 1 string to match.
    5437           0 :                     if (memcmp(Mnemonic.data()+13, "6_e64", 5) != 0)
    5438             :                       break;
    5439           0 :                     Mnemonic = "v_cmpx_nlg_f16";       // "v_cmpx_nlg_f16_e64"
    5440           0 :                     return;
    5441             :                   case '3':      // 1 string to match.
    5442           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5443             :                       break;
    5444           0 :                     Mnemonic = "v_cmpx_nlg_f32";       // "v_cmpx_nlg_f32_e64"
    5445           0 :                     return;
    5446             :                   case '6':      // 1 string to match.
    5447           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5448             :                       break;
    5449           0 :                     Mnemonic = "v_cmpx_nlg_f64";       // "v_cmpx_nlg_f64_e64"
    5450           0 :                     return;
    5451             :                   }
    5452             :                   break;
    5453             :                 case 't':        // 3 strings to match.
    5454           0 :                   if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    5455             :                     break;
    5456             :                   switch (Mnemonic[12]) {
    5457             :                   default: break;
    5458             :                   case '1':      // 1 string to match.
    5459           0 :                     if (memcmp(Mnemonic.data()+13, "6_e64", 5) != 0)
    5460             :                       break;
    5461           0 :                     Mnemonic = "v_cmpx_nlt_f16";       // "v_cmpx_nlt_f16_e64"
    5462           0 :                     return;
    5463             :                   case '3':      // 1 string to match.
    5464           0 :                     if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5465             :                       break;
    5466           0 :                     Mnemonic = "v_cmpx_nlt_f32";       // "v_cmpx_nlt_f32_e64"
    5467           0 :                     return;
    5468             :                   case '6':      // 1 string to match.
    5469           0 :                     if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5470             :                       break;
    5471           0 :                     Mnemonic = "v_cmpx_nlt_f64";       // "v_cmpx_nlt_f64_e64"
    5472           0 :                     return;
    5473             :                   }
    5474             :                   break;
    5475             :                 }
    5476             :                 break;
    5477             :               }
    5478             :               break;
    5479             :             case 't':    // 3 strings to match.
    5480           0 :               if (memcmp(Mnemonic.data()+8, "ru_f", 4) != 0)
    5481             :                 break;
    5482             :               switch (Mnemonic[12]) {
    5483             :               default: break;
    5484             :               case '1':  // 1 string to match.
    5485           0 :                 if (memcmp(Mnemonic.data()+13, "6_e64", 5) != 0)
    5486             :                   break;
    5487           0 :                 Mnemonic = "v_cmpx_tru_f16";   // "v_cmpx_tru_f16_e64"
    5488           0 :                 return;
    5489             :               case '3':  // 1 string to match.
    5490           0 :                 if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5491             :                   break;
    5492           0 :                 Mnemonic = "v_cmpx_tru_f32";   // "v_cmpx_tru_f32_e64"
    5493           0 :                 return;
    5494             :               case '6':  // 1 string to match.
    5495           0 :                 if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5496             :                   break;
    5497           0 :                 Mnemonic = "v_cmpx_tru_f64";   // "v_cmpx_tru_f64_e64"
    5498           0 :                 return;
    5499             :               }
    5500             :               break;
    5501             :             }
    5502             :             break;
    5503             :           }
    5504             :           break;
    5505           0 :         case 'd':        // 5 strings to match.
    5506             :           switch (Mnemonic[3]) {
    5507             :           default: break;
    5508             :           case 'i':      // 2 strings to match.
    5509           0 :             if (memcmp(Mnemonic.data()+4, "v_fmas_f", 8) != 0)
    5510             :               break;
    5511             :             switch (Mnemonic[12]) {
    5512             :             default: break;
    5513             :             case '3':    // 1 string to match.
    5514           0 :               if (memcmp(Mnemonic.data()+13, "2_e64", 5) != 0)
    5515             :                 break;
    5516           0 :               Mnemonic = "v_div_fmas_f32";     // "v_div_fmas_f32_e64"
    5517           0 :               return;
    5518             :             case '6':    // 1 string to match.
    5519           0 :               if (memcmp(Mnemonic.data()+13, "4_e64", 5) != 0)
    5520             :                 break;
    5521           0 :               Mnemonic = "v_div_fmas_f64";     // "v_div_fmas_f64_e64"
    5522           0 :               return;
    5523             :             }
    5524             :             break;
    5525             :           case 'o':      // 3 strings to match.
    5526           0 :             if (memcmp(Mnemonic.data()+4, "t2_", 3) != 0)
    5527             :               break;
    5528             :             switch (Mnemonic[7]) {
    5529             :             default: break;
    5530             :             case 'f':    // 1 string to match.
    5531           0 :               if (memcmp(Mnemonic.data()+8, "32_f16_e64", 10) != 0)
    5532             :                 break;
    5533           0 :               Mnemonic = "v_dot2_f32_f16";     // "v_dot2_f32_f16_e64"
    5534           0 :               return;
    5535             :             case 'i':    // 1 string to match.
    5536           0 :               if (memcmp(Mnemonic.data()+8, "32_i16_e64", 10) != 0)
    5537             :                 break;
    5538           0 :               Mnemonic = "v_dot2_i32_i16";     // "v_dot2_i32_i16_e64"
    5539           0 :               return;
    5540             :             case 'u':    // 1 string to match.
    5541           0 :               if (memcmp(Mnemonic.data()+8, "32_u16_e64", 10) != 0)
    5542             :                 break;
    5543           0 :               Mnemonic = "v_dot2_u32_u16";     // "v_dot2_u32_u16_e64"
    5544           0 :               return;
    5545             :             }
    5546             :             break;
    5547             :           }
    5548             :           break;
    5549             :         case 'f':        // 1 string to match.
    5550           0 :           if (memcmp(Mnemonic.data()+3, "ma_f16_gfx9_e64", 15) != 0)
    5551             :             break;
    5552           0 :           Mnemonic = "v_fma_f16_gfx9";         // "v_fma_f16_gfx9_e64"
    5553           0 :           return;
    5554             :         case 'l':        // 1 string to match.
    5555           0 :           if (memcmp(Mnemonic.data()+3, "shl_add_u32_e64", 15) != 0)
    5556             :             break;
    5557           0 :           Mnemonic = "v_lshl_add_u32";         // "v_lshl_add_u32_e64"
    5558           0 :           return;
    5559         300 :         case 'm':        // 5 strings to match.
    5560             :           switch (Mnemonic[3]) {
    5561             :           default: break;
    5562             :           case 'a':      // 3 strings to match.
    5563           0 :             if (memcmp(Mnemonic.data()+4, "d_", 2) != 0)
    5564             :               break;
    5565             :             switch (Mnemonic[6]) {
    5566             :             default: break;
    5567             :             case 'f':    // 1 string to match.
    5568           0 :               if (memcmp(Mnemonic.data()+7, "16_gfx9_e64", 11) != 0)
    5569             :                 break;
    5570           0 :               Mnemonic = "v_mad_f16_gfx9";     // "v_mad_f16_gfx9_e64"
    5571           0 :               return;
    5572             :             case 'i':    // 1 string to match.
    5573           0 :               if (memcmp(Mnemonic.data()+7, "16_gfx9_e64", 11) != 0)
    5574             :                 break;
    5575           0 :               Mnemonic = "v_mad_i16_gfx9";     // "v_mad_i16_gfx9_e64"
    5576           0 :               return;
    5577             :             case 'u':    // 1 string to match.
    5578           0 :               if (memcmp(Mnemonic.data()+7, "16_gfx9_e64", 11) != 0)
    5579             :                 break;
    5580           0 :               Mnemonic = "v_mad_u16_gfx9";     // "v_mad_u16_gfx9_e64"
    5581           0 :               return;
    5582             :             }
    5583             :             break;
    5584             :           case 'o':      // 1 string to match.
    5585           0 :             if (memcmp(Mnemonic.data()+4, "vrelsd_b32_e64", 14) != 0)
    5586             :               break;
    5587           0 :             Mnemonic = "v_movrelsd_b32";       // "v_movrelsd_b32_e64"
    5588           0 :             return;
    5589             :           case 'q':      // 1 string to match.
    5590           0 :             if (memcmp(Mnemonic.data()+4, "sad_u32_u8_e64", 14) != 0)
    5591             :               break;
    5592           0 :             Mnemonic = "v_mqsad_u32_u8";       // "v_mqsad_u32_u8_e64"
    5593           0 :             return;
    5594             :           }
    5595             :           break;
    5596             :         case 'p':        // 1 string to match.
    5597           0 :           if (memcmp(Mnemonic.data()+3, "ack_b32_f16_e64", 15) != 0)
    5598             :             break;
    5599           0 :           Mnemonic = "v_pack_b32_f16";         // "v_pack_b32_f16_e64"
    5600           0 :           return;
    5601             :         case 's':        // 1 string to match.
    5602           0 :           if (memcmp(Mnemonic.data()+3, "ub_i32_gfx9_e64", 15) != 0)
    5603             :             break;
    5604           0 :           Mnemonic = "v_sub_i32_gfx9";         // "v_sub_i32_gfx9_e64"
    5605           0 :           return;
    5606             :         }
    5607             :         break;
    5608             :       case 19:   // 39 strings to match.
    5609         609 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    5610             :           break;
    5611             :         switch (Mnemonic[2]) {
    5612             :         default: break;
    5613             :         case 'a':        // 1 string to match.
    5614           0 :           if (memcmp(Mnemonic.data()+3, "lignbyte_b32_e64", 16) != 0)
    5615             :             break;
    5616           0 :           Mnemonic = "v_alignbyte_b32";        // "v_alignbyte_b32_e64"
    5617           0 :           return;
    5618         166 :         case 'c':        // 18 strings to match.
    5619             :           switch (Mnemonic[3]) {
    5620             :           default: break;
    5621           0 :           case 'm':      // 17 strings to match.
    5622           0 :             if (Mnemonic[4] != 'p')
    5623             :               break;
    5624             :             switch (Mnemonic[5]) {
    5625             :             default: break;
    5626             :             case '_':    // 3 strings to match.
    5627           0 :               if (memcmp(Mnemonic.data()+6, "class_f", 7) != 0)
    5628             :                 break;
    5629             :               switch (Mnemonic[13]) {
    5630             :               default: break;
    5631             :               case '1':  // 1 string to match.
    5632           0 :                 if (memcmp(Mnemonic.data()+14, "6_e64", 5) != 0)
    5633             :                   break;
    5634           0 :                 Mnemonic = "v_cmp_class_f16";  // "v_cmp_class_f16_e64"
    5635           0 :                 return;
    5636             :               case '3':  // 1 string to match.
    5637           0 :                 if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5638             :                   break;
    5639           0 :                 Mnemonic = "v_cmp_class_f32";  // "v_cmp_class_f32_e64"
    5640           0 :                 return;
    5641             :               case '6':  // 1 string to match.
    5642           0 :                 if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5643             :                   break;
    5644           0 :                 Mnemonic = "v_cmp_class_f64";  // "v_cmp_class_f64_e64"
    5645           0 :                 return;
    5646             :               }
    5647             :               break;
    5648             :             case 's':    // 14 strings to match.
    5649           0 :               if (memcmp(Mnemonic.data()+6, "x_", 2) != 0)
    5650             :                 break;
    5651             :               switch (Mnemonic[8]) {
    5652             :               default: break;
    5653           0 :               case 'n':  // 12 strings to match.
    5654             :                 switch (Mnemonic[9]) {
    5655             :                 default: break;
    5656             :                 case 'e':        // 2 strings to match.
    5657           0 :                   if (memcmp(Mnemonic.data()+10, "q_f", 3) != 0)
    5658             :                     break;
    5659             :                   switch (Mnemonic[13]) {
    5660             :                   default: break;
    5661             :                   case '3':      // 1 string to match.
    5662           0 :                     if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5663             :                       break;
    5664           0 :                     Mnemonic = "v_cmpsx_neq_f32";      // "v_cmpsx_neq_f32_e64"
    5665           0 :                     return;
    5666             :                   case '6':      // 1 string to match.
    5667           0 :                     if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5668             :                       break;
    5669           0 :                     Mnemonic = "v_cmpsx_neq_f64";      // "v_cmpsx_neq_f64_e64"
    5670           0 :                     return;
    5671             :                   }
    5672             :                   break;
    5673           0 :                 case 'g':        // 4 strings to match.
    5674             :                   switch (Mnemonic[10]) {
    5675             :                   default: break;
    5676             :                   case 'e':      // 2 strings to match.
    5677           0 :                     if (memcmp(Mnemonic.data()+11, "_f", 2) != 0)
    5678             :                       break;
    5679             :                     switch (Mnemonic[13]) {
    5680             :                     default: break;
    5681             :                     case '3':    // 1 string to match.
    5682           0 :                       if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5683             :                         break;
    5684           0 :                       Mnemonic = "v_cmpsx_nge_f32";    // "v_cmpsx_nge_f32_e64"
    5685           0 :                       return;
    5686             :                     case '6':    // 1 string to match.
    5687           0 :                       if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5688             :                         break;
    5689           0 :                       Mnemonic = "v_cmpsx_nge_f64";    // "v_cmpsx_nge_f64_e64"
    5690           0 :                       return;
    5691             :                     }
    5692             :                     break;
    5693             :                   case 't':      // 2 strings to match.
    5694           0 :                     if (memcmp(Mnemonic.data()+11, "_f", 2) != 0)
    5695             :                       break;
    5696             :                     switch (Mnemonic[13]) {
    5697             :                     default: break;
    5698             :                     case '3':    // 1 string to match.
    5699           0 :                       if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5700             :                         break;
    5701           0 :                       Mnemonic = "v_cmpsx_ngt_f32";    // "v_cmpsx_ngt_f32_e64"
    5702           0 :                       return;
    5703             :                     case '6':    // 1 string to match.
    5704           0 :                       if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5705             :                         break;
    5706           0 :                       Mnemonic = "v_cmpsx_ngt_f64";    // "v_cmpsx_ngt_f64_e64"
    5707           0 :                       return;
    5708             :                     }
    5709             :                     break;
    5710             :                   }
    5711             :                   break;
    5712           0 :                 case 'l':        // 6 strings to match.
    5713             :                   switch (Mnemonic[10]) {
    5714             :                   default: break;
    5715             :                   case 'e':      // 2 strings to match.
    5716           0 :                     if (memcmp(Mnemonic.data()+11, "_f", 2) != 0)
    5717             :                       break;
    5718             :                     switch (Mnemonic[13]) {
    5719             :                     default: break;
    5720             :                     case '3':    // 1 string to match.
    5721           0 :                       if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5722             :                         break;
    5723           0 :                       Mnemonic = "v_cmpsx_nle_f32";    // "v_cmpsx_nle_f32_e64"
    5724           0 :                       return;
    5725             :                     case '6':    // 1 string to match.
    5726           0 :                       if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5727             :                         break;
    5728           0 :                       Mnemonic = "v_cmpsx_nle_f64";    // "v_cmpsx_nle_f64_e64"
    5729           0 :                       return;
    5730             :                     }
    5731             :                     break;
    5732             :                   case 'g':      // 2 strings to match.
    5733           0 :                     if (memcmp(Mnemonic.data()+11, "_f", 2) != 0)
    5734             :                       break;
    5735             :                     switch (Mnemonic[13]) {
    5736             :                     default: break;
    5737             :                     case '3':    // 1 string to match.
    5738           0 :                       if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5739             :                         break;
    5740           0 :                       Mnemonic = "v_cmpsx_nlg_f32";    // "v_cmpsx_nlg_f32_e64"
    5741           0 :                       return;
    5742             :                     case '6':    // 1 string to match.
    5743           0 :                       if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5744             :                         break;
    5745           0 :                       Mnemonic = "v_cmpsx_nlg_f64";    // "v_cmpsx_nlg_f64_e64"
    5746           0 :                       return;
    5747             :                     }
    5748             :                     break;
    5749             :                   case 't':      // 2 strings to match.
    5750           0 :                     if (memcmp(Mnemonic.data()+11, "_f", 2) != 0)
    5751             :                       break;
    5752             :                     switch (Mnemonic[13]) {
    5753             :                     default: break;
    5754             :                     case '3':    // 1 string to match.
    5755           0 :                       if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5756             :                         break;
    5757           0 :                       Mnemonic = "v_cmpsx_nlt_f32";    // "v_cmpsx_nlt_f32_e64"
    5758           0 :                       return;
    5759             :                     case '6':    // 1 string to match.
    5760           0 :                       if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5761             :                         break;
    5762           0 :                       Mnemonic = "v_cmpsx_nlt_f64";    // "v_cmpsx_nlt_f64_e64"
    5763           0 :                       return;
    5764             :                     }
    5765             :                     break;
    5766             :                   }
    5767             :                   break;
    5768             :                 }
    5769             :                 break;
    5770             :               case 't':  // 2 strings to match.
    5771           0 :                 if (memcmp(Mnemonic.data()+9, "ru_f", 4) != 0)
    5772             :                   break;
    5773             :                 switch (Mnemonic[13]) {
    5774             :                 default: break;
    5775             :                 case '3':        // 1 string to match.
    5776           0 :                   if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5777             :                     break;
    5778           0 :                   Mnemonic = "v_cmpsx_tru_f32";        // "v_cmpsx_tru_f32_e64"
    5779           0 :                   return;
    5780             :                 case '6':        // 1 string to match.
    5781           0 :                   if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5782             :                     break;
    5783           0 :                   Mnemonic = "v_cmpsx_tru_f64";        // "v_cmpsx_tru_f64_e64"
    5784           0 :                   return;
    5785             :                 }
    5786             :                 break;
    5787             :               }
    5788             :               break;
    5789             :             }
    5790             :             break;
    5791             :           case 'v':      // 1 string to match.
    5792         166 :             if (memcmp(Mnemonic.data()+4, "t_pk_u8_f32_e64", 15) != 0)
    5793             :               break;
    5794           0 :             Mnemonic = "v_cvt_pk_u8_f32";      // "v_cvt_pk_u8_f32_e64"
    5795           0 :             return;
    5796             :           }
    5797             :           break;
    5798             :         case 'd':        // 5 strings to match.
    5799           0 :           if (memcmp(Mnemonic.data()+3, "iv_", 3) != 0)
    5800             :             break;
    5801             :           switch (Mnemonic[6]) {
    5802             :           default: break;
    5803             :           case 'f':      // 3 strings to match.
    5804           0 :             if (memcmp(Mnemonic.data()+7, "ixup_f", 6) != 0)
    5805             :               break;
    5806             :             switch (Mnemonic[13]) {
    5807             :             default: break;
    5808             :             case '1':    // 1 string to match.
    5809           0 :               if (memcmp(Mnemonic.data()+14, "6_e64", 5) != 0)
    5810             :                 break;
    5811           0 :               if ((Features & (Feature_Has16BitInsts|Feature_isVIOnly)) == (Feature_Has16BitInsts|Feature_isVIOnly))         // "v_div_fixup_f16_e64"
    5812           0 :                 Mnemonic = "v_div_fixup_f16";
    5813             :               return;
    5814             :             case '3':    // 1 string to match.
    5815           0 :               if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5816             :                 break;
    5817           0 :               Mnemonic = "v_div_fixup_f32";    // "v_div_fixup_f32_e64"
    5818           0 :               return;
    5819             :             case '6':    // 1 string to match.
    5820           0 :               if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5821             :                 break;
    5822           0 :               Mnemonic = "v_div_fixup_f64";    // "v_div_fixup_f64_e64"
    5823           0 :               return;
    5824             :             }
    5825             :             break;
    5826             :           case 's':      // 2 strings to match.
    5827           0 :             if (memcmp(Mnemonic.data()+7, "cale_f", 6) != 0)
    5828             :               break;
    5829             :             switch (Mnemonic[13]) {
    5830             :             default: break;
    5831             :             case '3':    // 1 string to match.
    5832           0 :               if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5833             :                 break;
    5834           0 :               Mnemonic = "v_div_scale_f32";    // "v_div_scale_f32_e64"
    5835           0 :               return;
    5836             :             case '6':    // 1 string to match.
    5837           0 :               if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5838             :                 break;
    5839           0 :               Mnemonic = "v_div_scale_f64";    // "v_div_scale_f64_e64"
    5840           0 :               return;
    5841             :             }
    5842             :             break;
    5843             :           }
    5844             :           break;
    5845             :         case 'f':        // 2 strings to match.
    5846         230 :           if (memcmp(Mnemonic.data()+3, "ma_mix", 6) != 0)
    5847             :             break;
    5848             :           switch (Mnemonic[9]) {
    5849             :           default: break;
    5850             :           case 'h':      // 1 string to match.
    5851           0 :             if (memcmp(Mnemonic.data()+10, "i_f16_e64", 9) != 0)
    5852             :               break;
    5853           0 :             Mnemonic = "v_fma_mixhi_f16";      // "v_fma_mixhi_f16_e64"
    5854           0 :             return;
    5855             :           case 'l':      // 1 string to match.
    5856           0 :             if (memcmp(Mnemonic.data()+10, "o_f16_e64", 9) != 0)
    5857             :               break;
    5858           0 :             Mnemonic = "v_fma_mixlo_f16";      // "v_fma_mixlo_f16_e64"
    5859           0 :             return;
    5860             :           }
    5861             :           break;
    5862             :         case 'i':        // 3 strings to match.
    5863           0 :           if (memcmp(Mnemonic.data()+3, "nterp_p", 7) != 0)
    5864             :             break;
    5865             :           switch (Mnemonic[10]) {
    5866             :           default: break;
    5867             :           case '1':      // 1 string to match.
    5868           0 :             if (memcmp(Mnemonic.data()+11, "_f32_e64", 8) != 0)
    5869             :               break;
    5870           0 :             Mnemonic = "v_interp_p1_f32";      // "v_interp_p1_f32_e64"
    5871           0 :             return;
    5872             :           case '2':      // 2 strings to match.
    5873           0 :             if (memcmp(Mnemonic.data()+11, "_f", 2) != 0)
    5874             :               break;
    5875             :             switch (Mnemonic[13]) {
    5876             :             default: break;
    5877             :             case '1':    // 1 string to match.
    5878           0 :               if (memcmp(Mnemonic.data()+14, "6_e64", 5) != 0)
    5879             :                 break;
    5880           0 :               Mnemonic = "v_interp_p2_f16";    // "v_interp_p2_f16_e64"
    5881           0 :               return;
    5882             :             case '3':    // 1 string to match.
    5883           0 :               if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5884             :                 break;
    5885           0 :               Mnemonic = "v_interp_p2_f32";    // "v_interp_p2_f32_e64"
    5886           0 :               return;
    5887             :             }
    5888             :             break;
    5889             :           }
    5890             :           break;
    5891             :         case 'l':        // 1 string to match.
    5892           0 :           if (memcmp(Mnemonic.data()+3, "og_clamp_f32_e64", 16) != 0)
    5893             :             break;
    5894           0 :           Mnemonic = "v_log_clamp_f32";        // "v_log_clamp_f32_e64"
    5895           0 :           return;
    5896             :         case 'm':        // 2 strings to match.
    5897           0 :           if (memcmp(Mnemonic.data()+3, "ad_mix", 6) != 0)
    5898             :             break;
    5899             :           switch (Mnemonic[9]) {
    5900             :           default: break;
    5901             :           case 'h':      // 1 string to match.
    5902           0 :             if (memcmp(Mnemonic.data()+10, "i_f16_e64", 9) != 0)
    5903             :               break;
    5904           0 :             Mnemonic = "v_mad_mixhi_f16";      // "v_mad_mixhi_f16_e64"
    5905           0 :             return;
    5906             :           case 'l':      // 1 string to match.
    5907           0 :             if (memcmp(Mnemonic.data()+10, "o_f16_e64", 9) != 0)
    5908             :               break;
    5909           0 :             Mnemonic = "v_mad_mixlo_f16";      // "v_mad_mixlo_f16_e64"
    5910           0 :             return;
    5911             :           }
    5912             :           break;
    5913             :         case 'p':        // 1 string to match.
    5914           0 :           if (memcmp(Mnemonic.data()+3, "k_mul_lo_u16_e64", 16) != 0)
    5915             :             break;
    5916           0 :           Mnemonic = "v_pk_mul_lo_u16";        // "v_pk_mul_lo_u16_e64"
    5917           0 :           return;
    5918           0 :         case 'r':        // 5 strings to match.
    5919             :           switch (Mnemonic[3]) {
    5920             :           default: break;
    5921             :           case 'c':      // 3 strings to match.
    5922           0 :             if (memcmp(Mnemonic.data()+4, "p_", 2) != 0)
    5923             :               break;
    5924             :             switch (Mnemonic[6]) {
    5925             :             default: break;
    5926             :             case 'c':    // 2 strings to match.
    5927           0 :               if (memcmp(Mnemonic.data()+7, "lamp_f", 6) != 0)
    5928             :                 break;
    5929             :               switch (Mnemonic[13]) {
    5930             :               default: break;
    5931             :               case '3':  // 1 string to match.
    5932           0 :                 if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5933             :                   break;
    5934           0 :                 Mnemonic = "v_rcp_clamp_f32";  // "v_rcp_clamp_f32_e64"
    5935           0 :                 return;
    5936             :               case '6':  // 1 string to match.
    5937           0 :                 if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5938             :                   break;
    5939           0 :                 Mnemonic = "v_rcp_clamp_f64";  // "v_rcp_clamp_f64_e64"
    5940           0 :                 return;
    5941             :               }
    5942             :               break;
    5943             :             case 'i':    // 1 string to match.
    5944           0 :               if (memcmp(Mnemonic.data()+7, "flag_f32_e64", 12) != 0)
    5945             :                 break;
    5946           0 :               Mnemonic = "v_rcp_iflag_f32";    // "v_rcp_iflag_f32_e64"
    5947           0 :               return;
    5948             :             }
    5949             :             break;
    5950             :           case 's':      // 2 strings to match.
    5951           0 :             if (memcmp(Mnemonic.data()+4, "q_clamp_f", 9) != 0)
    5952             :               break;
    5953             :             switch (Mnemonic[13]) {
    5954             :             default: break;
    5955             :             case '3':    // 1 string to match.
    5956           0 :               if (memcmp(Mnemonic.data()+14, "2_e64", 5) != 0)
    5957             :                 break;
    5958           0 :               Mnemonic = "v_rsq_clamp_f32";    // "v_rsq_clamp_f32_e64"
    5959           0 :               return;
    5960             :             case '6':    // 1 string to match.
    5961           0 :               if (memcmp(Mnemonic.data()+14, "4_e64", 5) != 0)
    5962             :                 break;
    5963           0 :               Mnemonic = "v_rsq_clamp_f64";    // "v_rsq_clamp_f64_e64"
    5964           0 :               return;
    5965             :             }
    5966             :             break;
    5967             :           }
    5968             :           break;
    5969             :         case 's':        // 1 string to match.
    5970           0 :           if (memcmp(Mnemonic.data()+3, "at_pk_u8_i16_e64", 16) != 0)
    5971             :             break;
    5972           0 :           Mnemonic = "v_sat_pk_u8_i16";        // "v_sat_pk_u8_i16_e64"
    5973           0 :           return;
    5974             :         }
    5975             :         break;
    5976             :       case 20:   // 30 strings to match.
    5977         791 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    5978             :           break;
    5979             :         switch (Mnemonic[2]) {
    5980             :         default: break;
    5981         673 :         case 'c':        // 10 strings to match.
    5982             :           switch (Mnemonic[3]) {
    5983             :           default: break;
    5984             :           case 'm':      // 3 strings to match.
    5985           0 :             if (memcmp(Mnemonic.data()+4, "px_class_f", 10) != 0)
    5986             :               break;
    5987             :             switch (Mnemonic[14]) {
    5988             :             default: break;
    5989             :             case '1':    // 1 string to match.
    5990           0 :               if (memcmp(Mnemonic.data()+15, "6_e64", 5) != 0)
    5991             :                 break;
    5992           0 :               Mnemonic = "v_cmpx_class_f16";   // "v_cmpx_class_f16_e64"
    5993           0 :               return;
    5994             :             case '3':    // 1 string to match.
    5995           0 :               if (memcmp(Mnemonic.data()+15, "2_e64", 5) != 0)
    5996             :                 break;
    5997           0 :               Mnemonic = "v_cmpx_class_f32";   // "v_cmpx_class_f32_e64"
    5998           0 :               return;
    5999             :             case '6':    // 1 string to match.
    6000           0 :               if (memcmp(Mnemonic.data()+15, "4_e64", 5) != 0)
    6001             :                 break;
    6002           0 :               Mnemonic = "v_cmpx_class_f64";   // "v_cmpx_class_f64_e64"
    6003           0 :               return;
    6004             :             }
    6005             :             break;
    6006             :           case 'v':      // 7 strings to match.
    6007         673 :             if (memcmp(Mnemonic.data()+4, "t_", 2) != 0)
    6008             :               break;
    6009             :             switch (Mnemonic[6]) {
    6010             :             default: break;
    6011             :             case 'f':    // 4 strings to match.
    6012           0 :               if (memcmp(Mnemonic.data()+7, "32_ubyte", 8) != 0)
    6013             :                 break;
    6014             :               switch (Mnemonic[15]) {
    6015             :               default: break;
    6016             :               case '0':  // 1 string to match.
    6017           0 :                 if (memcmp(Mnemonic.data()+16, "_e64", 4) != 0)
    6018             :                   break;
    6019           0 :                 Mnemonic = "v_cvt_f32_ubyte0";         // "v_cvt_f32_ubyte0_e64"
    6020           0 :                 return;
    6021             :               case '1':  // 1 string to match.
    6022           0 :                 if (memcmp(Mnemonic.data()+16, "_e64", 4) != 0)
    6023             :                   break;
    6024           0 :                 Mnemonic = "v_cvt_f32_ubyte1";         // "v_cvt_f32_ubyte1_e64"
    6025           0 :                 return;
    6026             :               case '2':  // 1 string to match.
    6027           0 :                 if (memcmp(Mnemonic.data()+16, "_e64", 4) != 0)
    6028             :                   break;
    6029           0 :                 Mnemonic = "v_cvt_f32_ubyte2";         // "v_cvt_f32_ubyte2_e64"
    6030           0 :                 return;
    6031             :               case '3':  // 1 string to match.
    6032           0 :                 if (memcmp(Mnemonic.data()+16, "_e64", 4) != 0)
    6033             :                   break;
    6034           0 :                 Mnemonic = "v_cvt_f32_ubyte3";         // "v_cvt_f32_ubyte3_e64"
    6035           0 :                 return;
    6036             :               }
    6037             :               break;
    6038             :             case 'o':    // 1 string to match.
    6039           0 :               if (memcmp(Mnemonic.data()+7, "ff_f32_i4_e64", 13) != 0)
    6040             :                 break;
    6041           0 :               Mnemonic = "v_cvt_off_f32_i4";   // "v_cvt_off_f32_i4_e64"
    6042           0 :               return;
    6043             :             case 'p':    // 2 strings to match.
    6044         673 :               if (memcmp(Mnemonic.data()+7, "k_", 2) != 0)
    6045             :                 break;
    6046             :               switch (Mnemonic[9]) {
    6047             :               default: break;
    6048             :               case 'i':  // 1 string to match.
    6049           0 :                 if (memcmp(Mnemonic.data()+10, "16_i32_e64", 10) != 0)
    6050             :                   break;
    6051           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_cvt_pk_i16_i32_e64"
    6052           0 :                   Mnemonic = "v_cvt_pk_i16_i32";
    6053             :                 return;
    6054             :               case 'u':  // 1 string to match.
    6055           0 :                 if (memcmp(Mnemonic.data()+10, "16_u32_e64", 10) != 0)
    6056             :                   break;
    6057           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_cvt_pk_u16_u32_e64"
    6058           0 :                   Mnemonic = "v_cvt_pk_u16_u32";
    6059             :                 return;
    6060             :               }
    6061             :               break;
    6062             :             }
    6063             :             break;
    6064             :           }
    6065             :           break;
    6066             :         case 'e':        // 1 string to match.
    6067           0 :           if (memcmp(Mnemonic.data()+3, "xp_legacy_f32_e64", 17) != 0)
    6068             :             break;
    6069           0 :           Mnemonic = "v_exp_legacy_f32";       // "v_exp_legacy_f32_e64"
    6070           0 :           return;
    6071             :         case 'f':        // 3 strings to match.
    6072           0 :           if (memcmp(Mnemonic.data()+3, "rexp_mant_f", 11) != 0)
    6073             :             break;
    6074             :           switch (Mnemonic[14]) {
    6075             :           default: break;
    6076             :           case '1':      // 1 string to match.
    6077           0 :             if (memcmp(Mnemonic.data()+15, "6_e64", 5) != 0)
    6078             :               break;
    6079           0 :             Mnemonic = "v_frexp_mant_f16";     // "v_frexp_mant_f16_e64"
    6080           0 :             return;
    6081             :           case '3':      // 1 string to match.
    6082           0 :             if (memcmp(Mnemonic.data()+15, "2_e64", 5) != 0)
    6083             :               break;
    6084           0 :             Mnemonic = "v_frexp_mant_f32";     // "v_frexp_mant_f32_e64"
    6085           0 :             return;
    6086             :           case '6':      // 1 string to match.
    6087           0 :             if (memcmp(Mnemonic.data()+15, "4_e64", 5) != 0)
    6088             :               break;
    6089           0 :             Mnemonic = "v_frexp_mant_f64";     // "v_frexp_mant_f64_e64"
    6090           0 :             return;
    6091             :           }
    6092             :           break;
    6093             :         case 'i':        // 1 string to match.
    6094           0 :           if (memcmp(Mnemonic.data()+3, "nterp_mov_f32_e64", 17) != 0)
    6095             :             break;
    6096           0 :           Mnemonic = "v_interp_mov_f32";       // "v_interp_mov_f32_e64"
    6097           0 :           return;
    6098             :         case 'l':        // 1 string to match.
    6099           0 :           if (memcmp(Mnemonic.data()+3, "og_legacy_f32_e64", 17) != 0)
    6100             :             break;
    6101           0 :           Mnemonic = "v_log_legacy_f32";       // "v_log_legacy_f32_e64"
    6102           0 :           return;
    6103           0 :         case 'm':        // 7 strings to match.
    6104             :           switch (Mnemonic[3]) {
    6105             :           default: break;
    6106           0 :           case 'a':      // 3 strings to match.
    6107             :             switch (Mnemonic[4]) {
    6108             :             default: break;
    6109             :             case 'c':    // 1 string to match.
    6110           0 :               if (memcmp(Mnemonic.data()+5, "_legacy_f32_e64", 15) != 0)
    6111             :                 break;
    6112           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_mac_legacy_f32_e64"
    6113           0 :                 Mnemonic = "v_mac_legacy_f32";
    6114             :               return;
    6115             :             case 'd':    // 1 string to match.
    6116           0 :               if (memcmp(Mnemonic.data()+5, "_legacy_f32_e64", 15) != 0)
    6117             :                 break;
    6118           0 :               Mnemonic = "v_mad_legacy_f32";   // "v_mad_legacy_f32_e64"
    6119           0 :               return;
    6120             :             case 'x':    // 1 string to match.
    6121           0 :               if (memcmp(Mnemonic.data()+5, "_legacy_f32_e64", 15) != 0)
    6122             :                 break;
    6123           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_max_legacy_f32_e64"
    6124           0 :                 Mnemonic = "v_max_legacy_f32";
    6125             :               return;
    6126             :             }
    6127             :             break;
    6128             :           case 'i':      // 1 string to match.
    6129           0 :             if (memcmp(Mnemonic.data()+4, "n_legacy_f32_e64", 16) != 0)
    6130             :               break;
    6131           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_min_legacy_f32_e64"
    6132           0 :               Mnemonic = "v_min_legacy_f32";
    6133             :             return;
    6134             :           case 'u':      // 3 strings to match.
    6135           0 :             if (memcmp(Mnemonic.data()+4, "l_", 2) != 0)
    6136             :               break;
    6137             :             switch (Mnemonic[6]) {
    6138             :             default: break;
    6139             :             case 'h':    // 2 strings to match.
    6140           0 :               if (memcmp(Mnemonic.data()+7, "i_", 2) != 0)
    6141             :                 break;
    6142             :               switch (Mnemonic[9]) {
    6143             :               default: break;
    6144             :               case 'i':  // 1 string to match.
    6145           0 :                 if (memcmp(Mnemonic.data()+10, "32_i24_e64", 10) != 0)
    6146             :                   break;
    6147           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mul_hi_i32_i24_e64"
    6148           0 :                   Mnemonic = "v_mul_hi_i32_i24";
    6149             :                 return;
    6150             :               case 'u':  // 1 string to match.
    6151           0 :                 if (memcmp(Mnemonic.data()+10, "32_u24_e64", 10) != 0)
    6152             :                   break;
    6153           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mul_hi_u32_u24_e64"
    6154           0 :                   Mnemonic = "v_mul_hi_u32_u24";
    6155             :                 return;
    6156             :               }
    6157             :               break;
    6158             :             case 'l':    // 1 string to match.
    6159           0 :               if (memcmp(Mnemonic.data()+7, "egacy_f32_e64", 13) != 0)
    6160             :                 break;
    6161           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_legacy_f32_e64"
    6162           0 :                 Mnemonic = "v_mul_legacy_f32";
    6163             :               return;
    6164             :             }
    6165             :             break;
    6166             :           }
    6167             :           break;
    6168             :         case 'p':        // 3 strings to match.
    6169           0 :           if (memcmp(Mnemonic.data()+3, "k_", 2) != 0)
    6170             :             break;
    6171             :           switch (Mnemonic[5]) {
    6172             :           default: break;
    6173             :           case 'a':      // 1 string to match.
    6174           0 :             if (memcmp(Mnemonic.data()+6, "shrrev_i16_e64", 14) != 0)
    6175             :               break;
    6176           0 :             Mnemonic = "v_pk_ashrrev_i16";     // "v_pk_ashrrev_i16_e64"
    6177           0 :             return;
    6178             :           case 'l':      // 2 strings to match.
    6179           0 :             if (memcmp(Mnemonic.data()+6, "sh", 2) != 0)
    6180             :               break;
    6181             :             switch (Mnemonic[8]) {
    6182             :             default: break;
    6183             :             case 'l':    // 1 string to match.
    6184           0 :               if (memcmp(Mnemonic.data()+9, "rev_b16_e64", 11) != 0)
    6185             :                 break;
    6186           0 :               Mnemonic = "v_pk_lshlrev_b16";   // "v_pk_lshlrev_b16_e64"
    6187           0 :               return;
    6188             :             case 'r':    // 1 string to match.
    6189           0 :               if (memcmp(Mnemonic.data()+9, "rev_b16_e64", 11) != 0)
    6190             :                 break;
    6191           0 :               Mnemonic = "v_pk_lshrrev_b16";   // "v_pk_lshrrev_b16_e64"
    6192           0 :               return;
    6193             :             }
    6194             :             break;
    6195             :           }
    6196             :           break;
    6197             :         case 'q':        // 1 string to match.
    6198           0 :           if (memcmp(Mnemonic.data()+3, "sad_pk_u16_u8_e64", 17) != 0)
    6199             :             break;
    6200           0 :           Mnemonic = "v_qsad_pk_u16_u8";       // "v_qsad_pk_u16_u8_e64"
    6201           0 :           return;
    6202           0 :         case 'r':        // 2 strings to match.
    6203             :           switch (Mnemonic[3]) {
    6204             :           default: break;
    6205             :           case 'c':      // 1 string to match.
    6206           0 :             if (memcmp(Mnemonic.data()+4, "p_legacy_f32_e64", 16) != 0)
    6207             :               break;
    6208           0 :             Mnemonic = "v_rcp_legacy_f32";     // "v_rcp_legacy_f32_e64"
    6209           0 :             return;
    6210             :           case 's':      // 1 string to match.
    6211           0 :             if (memcmp(Mnemonic.data()+4, "q_legacy_f32_e64", 16) != 0)
    6212             :               break;
    6213           0 :             Mnemonic = "v_rsq_legacy_f32";     // "v_rsq_legacy_f32_e64"
    6214           0 :             return;
    6215             :           }
    6216             :           break;
    6217             :         case 't':        // 1 string to match.
    6218           0 :           if (memcmp(Mnemonic.data()+3, "rig_preop_f64_e64", 17) != 0)
    6219             :             break;
    6220           0 :           Mnemonic = "v_trig_preop_f64";       // "v_trig_preop_f64_e64"
    6221           0 :           return;
    6222             :         }
    6223             :         break;
    6224             :       case 21:   // 5 strings to match.
    6225          37 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    6226             :           break;
    6227             :         switch (Mnemonic[2]) {
    6228             :         default: break;
    6229             :         case 'c':        // 2 strings to match.
    6230           0 :           if (memcmp(Mnemonic.data()+3, "vt_", 3) != 0)
    6231             :             break;
    6232             :           switch (Mnemonic[6]) {
    6233             :           default: break;
    6234             :           case 'f':      // 1 string to match.
    6235           0 :             if (memcmp(Mnemonic.data()+7, "lr_i32_f32_e64", 14) != 0)
    6236             :               break;
    6237           0 :             Mnemonic = "v_cvt_flr_i32_f32";    // "v_cvt_flr_i32_f32_e64"
    6238           0 :             return;
    6239             :           case 'r':      // 1 string to match.
    6240           0 :             if (memcmp(Mnemonic.data()+7, "pi_i32_f32_e64", 14) != 0)
    6241             :               break;
    6242           0 :             Mnemonic = "v_cvt_rpi_i32_f32";    // "v_cvt_rpi_i32_f32_e64"
    6243           0 :             return;
    6244             :           }
    6245             :           break;
    6246             :         case 'i':        // 2 strings to match.
    6247           0 :           if (memcmp(Mnemonic.data()+3, "nterp_p1l", 9) != 0)
    6248             :             break;
    6249             :           switch (Mnemonic[12]) {
    6250             :           default: break;
    6251             :           case 'l':      // 1 string to match.
    6252           0 :             if (memcmp(Mnemonic.data()+13, "_f16_e64", 8) != 0)
    6253             :               break;
    6254           0 :             Mnemonic = "v_interp_p1ll_f16";    // "v_interp_p1ll_f16_e64"
    6255           0 :             return;
    6256             :           case 'v':      // 1 string to match.
    6257           0 :             if (memcmp(Mnemonic.data()+13, "_f16_e64", 8) != 0)
    6258             :               break;
    6259           0 :             Mnemonic = "v_interp_p1lv_f16";    // "v_interp_p1lv_f16_e64"
    6260           0 :             return;
    6261             :           }
    6262             :           break;
    6263             :         case 'm':        // 1 string to match.
    6264           0 :           if (memcmp(Mnemonic.data()+3, "qsad_pk_u16_u8_e64", 18) != 0)
    6265             :             break;
    6266           0 :           Mnemonic = "v_mqsad_pk_u16_u8";      // "v_mqsad_pk_u16_u8_e64"
    6267           0 :           return;
    6268             :         }
    6269             :         break;
    6270             :       case 22:   // 4 strings to match.
    6271         270 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    6272             :           break;
    6273             :         switch (Mnemonic[2]) {
    6274             :         default: break;
    6275             :         case 'c':        // 2 strings to match.
    6276           0 :           if (memcmp(Mnemonic.data()+3, "vt_norm_", 8) != 0)
    6277             :             break;
    6278             :           switch (Mnemonic[11]) {
    6279             :           default: break;
    6280             :           case 'i':      // 1 string to match.
    6281           0 :             if (memcmp(Mnemonic.data()+12, "16_f16_e64", 10) != 0)
    6282             :               break;
    6283           0 :             Mnemonic = "v_cvt_norm_i16_f16";   // "v_cvt_norm_i16_f16_e64"
    6284           0 :             return;
    6285             :           case 'u':      // 1 string to match.
    6286           0 :             if (memcmp(Mnemonic.data()+12, "16_f16_e64", 10) != 0)
    6287             :               break;
    6288           0 :             Mnemonic = "v_cvt_norm_u16_f16";   // "v_cvt_norm_u16_f16_e64"
    6289           0 :             return;
    6290             :           }
    6291             :           break;
    6292             :         case 'm':        // 2 strings to match.
    6293           0 :           if (memcmp(Mnemonic.data()+3, "bcnt_", 5) != 0)
    6294             :             break;
    6295             :           switch (Mnemonic[8]) {
    6296             :           default: break;
    6297             :           case 'h':      // 1 string to match.
    6298           0 :             if (memcmp(Mnemonic.data()+9, "i_u32_b32_e64", 13) != 0)
    6299             :               break;
    6300           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_mbcnt_hi_u32_b32_e64"
    6301           0 :               Mnemonic = "v_mbcnt_hi_u32_b32";
    6302             :             return;
    6303             :           case 'l':      // 1 string to match.
    6304           0 :             if (memcmp(Mnemonic.data()+9, "o_u32_b32_e64", 13) != 0)
    6305             :               break;
    6306           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_mbcnt_lo_u32_b32_e64"
    6307           0 :               Mnemonic = "v_mbcnt_lo_u32_b32";
    6308             :             return;
    6309             :           }
    6310             :           break;
    6311             :         }
    6312             :         break;
    6313             :       case 23:   // 4 strings to match.
    6314          80 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    6315             :           break;
    6316             :         switch (Mnemonic[2]) {
    6317             :         default: break;
    6318             :         case 'c':        // 1 string to match.
    6319           0 :           if (memcmp(Mnemonic.data()+3, "vt_pkrtz_f16_f32_e64", 20) != 0)
    6320             :             break;
    6321           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_cvt_pkrtz_f16_f32_e64"
    6322           0 :             Mnemonic = "v_cvt_pkrtz_f16_f32";
    6323             :           return;
    6324             :         case 'f':        // 3 strings to match.
    6325           0 :           if (memcmp(Mnemonic.data()+3, "rexp_exp_i", 10) != 0)
    6326             :             break;
    6327             :           switch (Mnemonic[13]) {
    6328             :           default: break;
    6329             :           case '1':      // 1 string to match.
    6330           0 :             if (memcmp(Mnemonic.data()+14, "6_f16_e64", 9) != 0)
    6331             :               break;
    6332           0 :             Mnemonic = "v_frexp_exp_i16_f16";  // "v_frexp_exp_i16_f16_e64"
    6333           0 :             return;
    6334             :           case '3':      // 2 strings to match.
    6335           0 :             if (memcmp(Mnemonic.data()+14, "2_f", 3) != 0)
    6336             :               break;
    6337             :             switch (Mnemonic[17]) {
    6338             :             default: break;
    6339             :             case '3':    // 1 string to match.
    6340           0 :               if (memcmp(Mnemonic.data()+18, "2_e64", 5) != 0)
    6341             :                 break;
    6342           0 :               Mnemonic = "v_frexp_exp_i32_f32";        // "v_frexp_exp_i32_f32_e64"
    6343           0 :               return;
    6344             :             case '6':    // 1 string to match.
    6345           0 :               if (memcmp(Mnemonic.data()+18, "4_e64", 5) != 0)
    6346             :                 break;
    6347           0 :               Mnemonic = "v_frexp_exp_i32_f64";        // "v_frexp_exp_i32_f64_e64"
    6348           0 :               return;
    6349             :             }
    6350             :             break;
    6351             :           }
    6352             :           break;
    6353             :         }
    6354             :         break;
    6355             :       case 24:   // 7 strings to match.
    6356          15 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    6357             :           break;
    6358             :         switch (Mnemonic[2]) {
    6359             :         default: break;
    6360             :         case 'c':        // 5 strings to match.
    6361           0 :           if (memcmp(Mnemonic.data()+3, "vt_pk", 5) != 0)
    6362             :             break;
    6363             :           switch (Mnemonic[8]) {
    6364             :           default: break;
    6365             :           case 'a':      // 1 string to match.
    6366           0 :             if (memcmp(Mnemonic.data()+9, "ccum_u8_f32_e64", 15) != 0)
    6367             :               break;
    6368           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_cvt_pkaccum_u8_f32_e64"
    6369           0 :               Mnemonic = "v_cvt_pkaccum_u8_f32";
    6370             :             return;
    6371             :           case 'n':      // 4 strings to match.
    6372           0 :             if (memcmp(Mnemonic.data()+9, "orm_", 4) != 0)
    6373             :               break;
    6374             :             switch (Mnemonic[13]) {
    6375             :             default: break;
    6376             :             case 'i':    // 2 strings to match.
    6377           0 :               if (memcmp(Mnemonic.data()+14, "16_f", 4) != 0)
    6378             :                 break;
    6379             :               switch (Mnemonic[18]) {
    6380             :               default: break;
    6381             :               case '1':  // 1 string to match.
    6382           0 :                 if (memcmp(Mnemonic.data()+19, "6_e64", 5) != 0)
    6383             :                   break;
    6384           0 :                 Mnemonic = "v_cvt_pknorm_i16_f16";     // "v_cvt_pknorm_i16_f16_e64"
    6385           0 :                 return;
    6386             :               case '3':  // 1 string to match.
    6387           0 :                 if (memcmp(Mnemonic.data()+19, "2_e64", 5) != 0)
    6388             :                   break;
    6389           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_cvt_pknorm_i16_f32_e64"
    6390           0 :                   Mnemonic = "v_cvt_pknorm_i16_f32";
    6391             :                 return;
    6392             :               }
    6393             :               break;
    6394             :             case 'u':    // 2 strings to match.
    6395           0 :               if (memcmp(Mnemonic.data()+14, "16_f", 4) != 0)
    6396             :                 break;
    6397             :               switch (Mnemonic[18]) {
    6398             :               default: break;
    6399             :               case '1':  // 1 string to match.
    6400           0 :                 if (memcmp(Mnemonic.data()+19, "6_e64", 5) != 0)
    6401             :                   break;
    6402           0 :                 Mnemonic = "v_cvt_pknorm_u16_f16";     // "v_cvt_pknorm_u16_f16_e64"
    6403           0 :                 return;
    6404             :               case '3':  // 1 string to match.
    6405           0 :                 if (memcmp(Mnemonic.data()+19, "2_e64", 5) != 0)
    6406             :                   break;
    6407           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_cvt_pknorm_u16_f32_e64"
    6408           0 :                   Mnemonic = "v_cvt_pknorm_u16_f32";
    6409             :                 return;
    6410             :               }
    6411             :               break;
    6412             :             }
    6413             :             break;
    6414             :           }
    6415             :           break;
    6416             :         case 'd':        // 1 string to match.
    6417           0 :           if (memcmp(Mnemonic.data()+3, "iv_fixup_f16_gfx9_e64", 21) != 0)
    6418             :             break;
    6419           0 :           if ((Features & (Feature_Has16BitInsts|Feature_isGFX9)) == (Feature_Has16BitInsts|Feature_isGFX9))         // "v_div_fixup_f16_gfx9_e64"
    6420           0 :             Mnemonic = "v_div_fixup_f16_gfx9";
    6421             :           return;
    6422             :         case 'i':        // 1 string to match.
    6423           0 :           if (memcmp(Mnemonic.data()+3, "nterp_p2_f16_gfx9_e64", 21) != 0)
    6424             :             break;
    6425           0 :           Mnemonic = "v_interp_p2_f16_gfx9";   // "v_interp_p2_f16_gfx9_e64"
    6426           0 :           return;
    6427             :         }
    6428             :         break;
    6429             :       case 30:   // 1 string to match.
    6430           0 :         if (memcmp(Mnemonic.data()+0, "v_screen_partition_4se_b32_e64", 30) != 0)
    6431             :           break;
    6432           0 :         Mnemonic = "v_screen_partition_4se_b32";       // "v_screen_partition_4se_b32_e64"
    6433           0 :         return;
    6434             :       }
    6435             :     break;
    6436             :     case 2:
    6437             :       switch (Mnemonic.size()) {
    6438             :       default: break;
    6439             :       case 10:   // 1 string to match.
    6440         938 :         if (memcmp(Mnemonic.data()+0, "v_nop_sdwa", 10) != 0)
    6441             :           break;
    6442           0 :         Mnemonic = "v_nop";    // "v_nop_sdwa"
    6443           0 :         return;
    6444             :       case 13:   // 1 string to match.
    6445        7388 :         if (memcmp(Mnemonic.data()+0, "v_or_b32_sdwa", 13) != 0)
    6446             :           break;
    6447           0 :         if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_or_b32_sdwa"
    6448           0 :           Mnemonic = "v_or_b32";
    6449             :         return;
    6450             :       case 14:   // 42 strings to match.
    6451        1578 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    6452             :           break;
    6453             :         switch (Mnemonic[2]) {
    6454             :         default: break;
    6455           3 :         case 'a':        // 6 strings to match.
    6456             :           switch (Mnemonic[3]) {
    6457             :           default: break;
    6458             :           case 'd':      // 5 strings to match.
    6459           3 :             if (memcmp(Mnemonic.data()+4, "d_", 2) != 0)
    6460             :               break;
    6461             :             switch (Mnemonic[6]) {
    6462             :             default: break;
    6463           0 :             case 'f':    // 2 strings to match.
    6464             :               switch (Mnemonic[7]) {
    6465             :               default: break;
    6466             :               case '1':  // 1 string to match.
    6467           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6468             :                   break;
    6469           0 :                 Mnemonic = "v_add_f16";        // "v_add_f16_sdwa"
    6470           0 :                 return;
    6471             :               case '3':  // 1 string to match.
    6472           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6473             :                   break;
    6474           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_add_f32_sdwa"
    6475           0 :                   Mnemonic = "v_add_f32";
    6476             :                 return;
    6477             :               }
    6478             :               break;
    6479             :             case 'i':    // 1 string to match.
    6480           0 :               if (memcmp(Mnemonic.data()+7, "32_sdwa", 7) != 0)
    6481             :                 break;
    6482           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_add_i32_sdwa"
    6483           0 :                 Mnemonic = "v_add_i32";
    6484             :               return;
    6485           0 :             case 'u':    // 2 strings to match.
    6486             :               switch (Mnemonic[7]) {
    6487             :               default: break;
    6488             :               case '1':  // 1 string to match.
    6489           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6490             :                   break;
    6491           0 :                 Mnemonic = "v_add_u16";        // "v_add_u16_sdwa"
    6492           0 :                 return;
    6493             :               case '3':  // 1 string to match.
    6494           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6495             :                   break;
    6496           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_add_u32_sdwa"
    6497           0 :                   Mnemonic = "v_add_u32";
    6498             :                 return;
    6499             :               }
    6500             :               break;
    6501             :             }
    6502             :             break;
    6503             :           case 'n':      // 1 string to match.
    6504           0 :             if (memcmp(Mnemonic.data()+4, "d_b32_sdwa", 10) != 0)
    6505             :               break;
    6506           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_and_b32_sdwa"
    6507           0 :               Mnemonic = "v_and_b32";
    6508             :             return;
    6509             :           }
    6510             :           break;
    6511             :         case 'c':        // 2 strings to match.
    6512        1393 :           if (memcmp(Mnemonic.data()+3, "os_f", 4) != 0)
    6513             :             break;
    6514             :           switch (Mnemonic[7]) {
    6515             :           default: break;
    6516             :           case '1':      // 1 string to match.
    6517           0 :             if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6518             :               break;
    6519           0 :             Mnemonic = "v_cos_f16";    // "v_cos_f16_sdwa"
    6520           0 :             return;
    6521             :           case '3':      // 1 string to match.
    6522           0 :             if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6523             :               break;
    6524           0 :             Mnemonic = "v_cos_f32";    // "v_cos_f32_sdwa"
    6525           0 :             return;
    6526             :           }
    6527             :           break;
    6528             :         case 'e':        // 2 strings to match.
    6529           0 :           if (memcmp(Mnemonic.data()+3, "xp_f", 4) != 0)
    6530             :             break;
    6531             :           switch (Mnemonic[7]) {
    6532             :           default: break;
    6533             :           case '1':      // 1 string to match.
    6534           0 :             if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6535             :               break;
    6536           0 :             Mnemonic = "v_exp_f16";    // "v_exp_f16_sdwa"
    6537           0 :             return;
    6538             :           case '3':      // 1 string to match.
    6539           0 :             if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6540             :               break;
    6541           0 :             Mnemonic = "v_exp_f32";    // "v_exp_f32_sdwa"
    6542           0 :             return;
    6543             :           }
    6544             :           break;
    6545             :         case 'l':        // 2 strings to match.
    6546           3 :           if (memcmp(Mnemonic.data()+3, "og_f", 4) != 0)
    6547             :             break;
    6548             :           switch (Mnemonic[7]) {
    6549             :           default: break;
    6550             :           case '1':      // 1 string to match.
    6551           0 :             if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6552             :               break;
    6553           0 :             Mnemonic = "v_log_f16";    // "v_log_f16_sdwa"
    6554           0 :             return;
    6555             :           case '3':      // 1 string to match.
    6556           0 :             if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6557             :               break;
    6558           0 :             Mnemonic = "v_log_f32";    // "v_log_f32_sdwa"
    6559           0 :             return;
    6560             :           }
    6561             :           break;
    6562           6 :         case 'm':        // 17 strings to match.
    6563             :           switch (Mnemonic[3]) {
    6564             :           default: break;
    6565           0 :           case 'a':      // 8 strings to match.
    6566             :             switch (Mnemonic[4]) {
    6567             :             default: break;
    6568             :             case 'c':    // 2 strings to match.
    6569           0 :               if (memcmp(Mnemonic.data()+5, "_f", 2) != 0)
    6570             :                 break;
    6571             :               switch (Mnemonic[7]) {
    6572             :               default: break;
    6573             :               case '1':  // 1 string to match.
    6574           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6575             :                   break;
    6576           0 :                 Mnemonic = "v_mac_f16";        // "v_mac_f16_sdwa"
    6577           0 :                 return;
    6578             :               case '3':  // 1 string to match.
    6579           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6580             :                   break;
    6581           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mac_f32_sdwa"
    6582           0 :                   Mnemonic = "v_mac_f32";
    6583             :                 return;
    6584             :               }
    6585             :               break;
    6586           0 :             case 'x':    // 6 strings to match.
    6587           0 :               if (Mnemonic[5] != '_')
    6588             :                 break;
    6589             :               switch (Mnemonic[6]) {
    6590             :               default: break;
    6591           0 :               case 'f':  // 2 strings to match.
    6592             :                 switch (Mnemonic[7]) {
    6593             :                 default: break;
    6594             :                 case '1':        // 1 string to match.
    6595           0 :                   if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6596             :                     break;
    6597           0 :                   Mnemonic = "v_max_f16";      // "v_max_f16_sdwa"
    6598           0 :                   return;
    6599             :                 case '3':        // 1 string to match.
    6600           0 :                   if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6601             :                     break;
    6602           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_f32_sdwa"
    6603           0 :                     Mnemonic = "v_max_f32";
    6604             :                   return;
    6605             :                 }
    6606             :                 break;
    6607           0 :               case 'i':  // 2 strings to match.
    6608             :                 switch (Mnemonic[7]) {
    6609             :                 default: break;
    6610             :                 case '1':        // 1 string to match.
    6611           0 :                   if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6612             :                     break;
    6613           0 :                   Mnemonic = "v_max_i16";      // "v_max_i16_sdwa"
    6614           0 :                   return;
    6615             :                 case '3':        // 1 string to match.
    6616           0 :                   if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6617             :                     break;
    6618           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_i32_sdwa"
    6619           0 :                     Mnemonic = "v_max_i32";
    6620             :                   return;
    6621             :                 }
    6622             :                 break;
    6623           0 :               case 'u':  // 2 strings to match.
    6624             :                 switch (Mnemonic[7]) {
    6625             :                 default: break;
    6626             :                 case '1':        // 1 string to match.
    6627           0 :                   if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6628             :                     break;
    6629           0 :                   Mnemonic = "v_max_u16";      // "v_max_u16_sdwa"
    6630           0 :                   return;
    6631             :                 case '3':        // 1 string to match.
    6632           0 :                   if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6633             :                     break;
    6634           0 :                   if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_max_u32_sdwa"
    6635           0 :                     Mnemonic = "v_max_u32";
    6636             :                   return;
    6637             :                 }
    6638             :                 break;
    6639             :               }
    6640             :               break;
    6641             :             }
    6642             :             break;
    6643             :           case 'i':      // 6 strings to match.
    6644           0 :             if (memcmp(Mnemonic.data()+4, "n_", 2) != 0)
    6645             :               break;
    6646             :             switch (Mnemonic[6]) {
    6647             :             default: break;
    6648           0 :             case 'f':    // 2 strings to match.
    6649             :               switch (Mnemonic[7]) {
    6650             :               default: break;
    6651             :               case '1':  // 1 string to match.
    6652           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6653             :                   break;
    6654           0 :                 Mnemonic = "v_min_f16";        // "v_min_f16_sdwa"
    6655           0 :                 return;
    6656             :               case '3':  // 1 string to match.
    6657           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6658             :                   break;
    6659           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_f32_sdwa"
    6660           0 :                   Mnemonic = "v_min_f32";
    6661             :                 return;
    6662             :               }
    6663             :               break;
    6664           0 :             case 'i':    // 2 strings to match.
    6665             :               switch (Mnemonic[7]) {
    6666             :               default: break;
    6667             :               case '1':  // 1 string to match.
    6668           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6669             :                   break;
    6670           0 :                 Mnemonic = "v_min_i16";        // "v_min_i16_sdwa"
    6671           0 :                 return;
    6672             :               case '3':  // 1 string to match.
    6673           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6674             :                   break;
    6675           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_i32_sdwa"
    6676           0 :                   Mnemonic = "v_min_i32";
    6677             :                 return;
    6678             :               }
    6679             :               break;
    6680           0 :             case 'u':    // 2 strings to match.
    6681             :               switch (Mnemonic[7]) {
    6682             :               default: break;
    6683             :               case '1':  // 1 string to match.
    6684           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6685             :                   break;
    6686           0 :                 Mnemonic = "v_min_u16";        // "v_min_u16_sdwa"
    6687           0 :                 return;
    6688             :               case '3':  // 1 string to match.
    6689           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6690             :                   break;
    6691           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_min_u32_sdwa"
    6692           0 :                   Mnemonic = "v_min_u32";
    6693             :                 return;
    6694             :               }
    6695             :               break;
    6696             :             }
    6697             :             break;
    6698             :           case 'o':      // 1 string to match.
    6699           0 :             if (memcmp(Mnemonic.data()+4, "v_b32_sdwa", 10) != 0)
    6700             :               break;
    6701           0 :             Mnemonic = "v_mov_b32";    // "v_mov_b32_sdwa"
    6702           0 :             return;
    6703             :           case 'u':      // 2 strings to match.
    6704           0 :             if (memcmp(Mnemonic.data()+4, "l_f", 3) != 0)
    6705             :               break;
    6706             :             switch (Mnemonic[7]) {
    6707             :             default: break;
    6708             :             case '1':    // 1 string to match.
    6709           0 :               if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6710             :                 break;
    6711           0 :               Mnemonic = "v_mul_f16";  // "v_mul_f16_sdwa"
    6712           0 :               return;
    6713             :             case '3':    // 1 string to match.
    6714           0 :               if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6715             :                 break;
    6716           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_f32_sdwa"
    6717           0 :                 Mnemonic = "v_mul_f32";
    6718             :               return;
    6719             :             }
    6720             :             break;
    6721             :           }
    6722             :           break;
    6723             :         case 'n':        // 1 string to match.
    6724           0 :           if (memcmp(Mnemonic.data()+3, "ot_b32_sdwa", 11) != 0)
    6725             :             break;
    6726           0 :           Mnemonic = "v_not_b32";      // "v_not_b32_sdwa"
    6727           0 :           return;
    6728           0 :         case 'r':        // 4 strings to match.
    6729             :           switch (Mnemonic[3]) {
    6730             :           default: break;
    6731             :           case 'c':      // 2 strings to match.
    6732           0 :             if (memcmp(Mnemonic.data()+4, "p_f", 3) != 0)
    6733             :               break;
    6734             :             switch (Mnemonic[7]) {
    6735             :             default: break;
    6736             :             case '1':    // 1 string to match.
    6737           0 :               if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6738             :                 break;
    6739           0 :               Mnemonic = "v_rcp_f16";  // "v_rcp_f16_sdwa"
    6740           0 :               return;
    6741             :             case '3':    // 1 string to match.
    6742           0 :               if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6743             :                 break;
    6744           0 :               Mnemonic = "v_rcp_f32";  // "v_rcp_f32_sdwa"
    6745           0 :               return;
    6746             :             }
    6747             :             break;
    6748             :           case 's':      // 2 strings to match.
    6749           0 :             if (memcmp(Mnemonic.data()+4, "q_f", 3) != 0)
    6750             :               break;
    6751             :             switch (Mnemonic[7]) {
    6752             :             default: break;
    6753             :             case '1':    // 1 string to match.
    6754           0 :               if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6755             :                 break;
    6756           0 :               Mnemonic = "v_rsq_f16";  // "v_rsq_f16_sdwa"
    6757           0 :               return;
    6758             :             case '3':    // 1 string to match.
    6759           0 :               if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6760             :                 break;
    6761           0 :               Mnemonic = "v_rsq_f32";  // "v_rsq_f32_sdwa"
    6762           0 :               return;
    6763             :             }
    6764             :             break;
    6765             :           }
    6766             :           break;
    6767           0 :         case 's':        // 7 strings to match.
    6768             :           switch (Mnemonic[3]) {
    6769             :           default: break;
    6770             :           case 'i':      // 2 strings to match.
    6771           0 :             if (memcmp(Mnemonic.data()+4, "n_f", 3) != 0)
    6772             :               break;
    6773             :             switch (Mnemonic[7]) {
    6774             :             default: break;
    6775             :             case '1':    // 1 string to match.
    6776           0 :               if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6777             :                 break;
    6778           0 :               Mnemonic = "v_sin_f16";  // "v_sin_f16_sdwa"
    6779           0 :               return;
    6780             :             case '3':    // 1 string to match.
    6781           0 :               if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6782             :                 break;
    6783           0 :               Mnemonic = "v_sin_f32";  // "v_sin_f32_sdwa"
    6784           0 :               return;
    6785             :             }
    6786             :             break;
    6787             :           case 'u':      // 5 strings to match.
    6788           0 :             if (memcmp(Mnemonic.data()+4, "b_", 2) != 0)
    6789             :               break;
    6790             :             switch (Mnemonic[6]) {
    6791             :             default: break;
    6792           0 :             case 'f':    // 2 strings to match.
    6793             :               switch (Mnemonic[7]) {
    6794             :               default: break;
    6795             :               case '1':  // 1 string to match.
    6796           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6797             :                   break;
    6798           0 :                 Mnemonic = "v_sub_f16";        // "v_sub_f16_sdwa"
    6799           0 :                 return;
    6800             :               case '3':  // 1 string to match.
    6801           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6802             :                   break;
    6803           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_sub_f32_sdwa"
    6804           0 :                   Mnemonic = "v_sub_f32";
    6805             :                 return;
    6806             :               }
    6807             :               break;
    6808             :             case 'i':    // 1 string to match.
    6809           0 :               if (memcmp(Mnemonic.data()+7, "32_sdwa", 7) != 0)
    6810             :                 break;
    6811           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_sub_i32_sdwa"
    6812           0 :                 Mnemonic = "v_sub_i32";
    6813             :               return;
    6814           0 :             case 'u':    // 2 strings to match.
    6815             :               switch (Mnemonic[7]) {
    6816             :               default: break;
    6817             :               case '1':  // 1 string to match.
    6818           0 :                 if (memcmp(Mnemonic.data()+8, "6_sdwa", 6) != 0)
    6819             :                   break;
    6820           0 :                 Mnemonic = "v_sub_u16";        // "v_sub_u16_sdwa"
    6821           0 :                 return;
    6822             :               case '3':  // 1 string to match.
    6823           0 :                 if (memcmp(Mnemonic.data()+8, "2_sdwa", 6) != 0)
    6824             :                   break;
    6825           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_sub_u32_sdwa"
    6826           0 :                   Mnemonic = "v_sub_u32";
    6827             :                 return;
    6828             :               }
    6829             :               break;
    6830             :             }
    6831             :             break;
    6832             :           }
    6833             :           break;
    6834             :         case 'x':        // 1 string to match.
    6835           0 :           if (memcmp(Mnemonic.data()+3, "or_b32_sdwa", 11) != 0)
    6836             :             break;
    6837           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_xor_b32_sdwa"
    6838           0 :             Mnemonic = "v_xor_b32";
    6839             :           return;
    6840             :         }
    6841             :         break;
    6842             :       case 15:   // 14 strings to match.
    6843         748 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    6844             :           break;
    6845             :         switch (Mnemonic[2]) {
    6846             :         default: break;
    6847           0 :         case 'a':        // 2 strings to match.
    6848             :           switch (Mnemonic[3]) {
    6849             :           default: break;
    6850             :           case 'd':      // 1 string to match.
    6851           0 :             if (memcmp(Mnemonic.data()+4, "dc_u32_sdwa", 11) != 0)
    6852             :               break;
    6853           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_addc_u32_sdwa"
    6854           0 :               Mnemonic = "v_addc_u32";
    6855             :             return;
    6856             :           case 's':      // 1 string to match.
    6857           0 :             if (memcmp(Mnemonic.data()+4, "hr_i32_sdwa", 11) != 0)
    6858             :               break;
    6859           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_ashr_i32_sdwa"
    6860           0 :               Mnemonic = "v_ashr_i32";
    6861             :             return;
    6862             :           }
    6863             :           break;
    6864             :         case 'c':        // 2 strings to match.
    6865         198 :           if (memcmp(Mnemonic.data()+3, "eil_f", 5) != 0)
    6866             :             break;
    6867             :           switch (Mnemonic[8]) {
    6868             :           default: break;
    6869             :           case '1':      // 1 string to match.
    6870           0 :             if (memcmp(Mnemonic.data()+9, "6_sdwa", 6) != 0)
    6871             :               break;
    6872           0 :             Mnemonic = "v_ceil_f16";   // "v_ceil_f16_sdwa"
    6873           0 :             return;
    6874             :           case '3':      // 1 string to match.
    6875           0 :             if (memcmp(Mnemonic.data()+9, "2_sdwa", 6) != 0)
    6876             :               break;
    6877           0 :             Mnemonic = "v_ceil_f32";   // "v_ceil_f32_sdwa"
    6878           0 :             return;
    6879             :           }
    6880             :           break;
    6881           6 :         case 'f':        // 4 strings to match.
    6882             :           switch (Mnemonic[3]) {
    6883             :           default: break;
    6884           0 :           case 'f':      // 3 strings to match.
    6885           0 :             if (Mnemonic[4] != 'b')
    6886             :               break;
    6887             :             switch (Mnemonic[5]) {
    6888             :             default: break;
    6889           0 :             case 'h':    // 2 strings to match.
    6890           0 :               if (Mnemonic[6] != '_')
    6891             :                 break;
    6892             :               switch (Mnemonic[7]) {
    6893             :               default: break;
    6894             :               case 'i':  // 1 string to match.
    6895           0 :                 if (memcmp(Mnemonic.data()+8, "32_sdwa", 7) != 0)
    6896             :                   break;
    6897           0 :                 Mnemonic = "v_ffbh_i32";       // "v_ffbh_i32_sdwa"
    6898           0 :                 return;
    6899             :               case 'u':  // 1 string to match.
    6900           0 :                 if (memcmp(Mnemonic.data()+8, "32_sdwa", 7) != 0)
    6901             :                   break;
    6902           0 :                 Mnemonic = "v_ffbh_u32";       // "v_ffbh_u32_sdwa"
    6903           0 :                 return;
    6904             :               }
    6905             :               break;
    6906             :             case 'l':    // 1 string to match.
    6907           0 :               if (memcmp(Mnemonic.data()+6, "_b32_sdwa", 9) != 0)
    6908             :                 break;
    6909           0 :               Mnemonic = "v_ffbl_b32";         // "v_ffbl_b32_sdwa"
    6910           0 :               return;
    6911             :             }
    6912             :             break;
    6913             :           case 'm':      // 1 string to match.
    6914           6 :             if (memcmp(Mnemonic.data()+4, "ac_f32_sdwa", 11) != 0)
    6915             :               break;
    6916           0 :             Mnemonic = "v_fmac_f32";   // "v_fmac_f32_sdwa"
    6917           0 :             return;
    6918             :           }
    6919             :           break;
    6920             :         case 'l':        // 2 strings to match.
    6921           4 :           if (memcmp(Mnemonic.data()+3, "sh", 2) != 0)
    6922             :             break;
    6923             :           switch (Mnemonic[5]) {
    6924             :           default: break;
    6925             :           case 'l':      // 1 string to match.
    6926           0 :             if (memcmp(Mnemonic.data()+6, "_b32_sdwa", 9) != 0)
    6927             :               break;
    6928           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_lshl_b32_sdwa"
    6929           0 :               Mnemonic = "v_lshl_b32";
    6930             :             return;
    6931             :           case 'r':      // 1 string to match.
    6932           0 :             if (memcmp(Mnemonic.data()+6, "_b32_sdwa", 9) != 0)
    6933             :               break;
    6934           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_lshr_b32_sdwa"
    6935           0 :               Mnemonic = "v_lshr_b32";
    6936             :             return;
    6937             :           }
    6938             :           break;
    6939         105 :         case 's':        // 3 strings to match.
    6940             :           switch (Mnemonic[3]) {
    6941             :           default: break;
    6942             :           case 'q':      // 2 strings to match.
    6943           0 :             if (memcmp(Mnemonic.data()+4, "rt_f", 4) != 0)
    6944             :               break;
    6945             :             switch (Mnemonic[8]) {
    6946             :             default: break;
    6947             :             case '1':    // 1 string to match.
    6948           0 :               if (memcmp(Mnemonic.data()+9, "6_sdwa", 6) != 0)
    6949             :                 break;
    6950           0 :               Mnemonic = "v_sqrt_f16";         // "v_sqrt_f16_sdwa"
    6951           0 :               return;
    6952             :             case '3':    // 1 string to match.
    6953           0 :               if (memcmp(Mnemonic.data()+9, "2_sdwa", 6) != 0)
    6954             :                 break;
    6955           0 :               Mnemonic = "v_sqrt_f32";         // "v_sqrt_f32_sdwa"
    6956           0 :               return;
    6957             :             }
    6958             :             break;
    6959             :           case 'u':      // 1 string to match.
    6960          92 :             if (memcmp(Mnemonic.data()+4, "bb_u32_sdwa", 11) != 0)
    6961             :               break;
    6962           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_subb_u32_sdwa"
    6963           0 :               Mnemonic = "v_subb_u32";
    6964             :             return;
    6965             :           }
    6966             :           break;
    6967             :         case 'x':        // 1 string to match.
    6968           0 :           if (memcmp(Mnemonic.data()+3, "nor_b32_sdwa", 12) != 0)
    6969             :             break;
    6970           0 :           Mnemonic = "v_xnor_b32";     // "v_xnor_b32_sdwa"
    6971           0 :           return;
    6972             :         }
    6973             :         break;
    6974             :       case 16:   // 24 strings to match.
    6975        1845 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    6976             :           break;
    6977             :         switch (Mnemonic[2]) {
    6978             :         default: break;
    6979             :         case 'b':        // 1 string to match.
    6980           0 :           if (memcmp(Mnemonic.data()+3, "frev_b32_sdwa", 13) != 0)
    6981             :             break;
    6982           0 :           Mnemonic = "v_bfrev_b32";    // "v_bfrev_b32_sdwa"
    6983           0 :           return;
    6984             :         case 'c':        // 14 strings to match.
    6985         747 :           if (memcmp(Mnemonic.data()+3, "mp_", 3) != 0)
    6986             :             break;
    6987             :           switch (Mnemonic[6]) {
    6988             :           default: break;
    6989           0 :           case 'f':      // 6 strings to match.
    6990           0 :             if (Mnemonic[7] != '_')
    6991             :               break;
    6992             :             switch (Mnemonic[8]) {
    6993             :             default: break;
    6994           0 :             case 'f':    // 2 strings to match.
    6995             :               switch (Mnemonic[9]) {
    6996             :               default: break;
    6997             :               case '1':  // 1 string to match.
    6998           0 :                 if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    6999             :                   break;
    7000           0 :                 Mnemonic = "v_cmp_f_f16";      // "v_cmp_f_f16_sdwa"
    7001           0 :                 return;
    7002             :               case '3':  // 1 string to match.
    7003           0 :                 if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7004             :                   break;
    7005           0 :                 Mnemonic = "v_cmp_f_f32";      // "v_cmp_f_f32_sdwa"
    7006           0 :                 return;
    7007             :               }
    7008             :               break;
    7009           0 :             case 'i':    // 2 strings to match.
    7010             :               switch (Mnemonic[9]) {
    7011             :               default: break;
    7012             :               case '1':  // 1 string to match.
    7013           0 :                 if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7014             :                   break;
    7015           0 :                 Mnemonic = "v_cmp_f_i16";      // "v_cmp_f_i16_sdwa"
    7016           0 :                 return;
    7017             :               case '3':  // 1 string to match.
    7018           0 :                 if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7019             :                   break;
    7020           0 :                 Mnemonic = "v_cmp_f_i32";      // "v_cmp_f_i32_sdwa"
    7021           0 :                 return;
    7022             :               }
    7023             :               break;
    7024           0 :             case 'u':    // 2 strings to match.
    7025             :               switch (Mnemonic[9]) {
    7026             :               default: break;
    7027             :               case '1':  // 1 string to match.
    7028           0 :                 if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7029             :                   break;
    7030           0 :                 Mnemonic = "v_cmp_f_u16";      // "v_cmp_f_u16_sdwa"
    7031           0 :                 return;
    7032             :               case '3':  // 1 string to match.
    7033           0 :                 if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7034             :                   break;
    7035           0 :                 Mnemonic = "v_cmp_f_u32";      // "v_cmp_f_u32_sdwa"
    7036           0 :                 return;
    7037             :               }
    7038             :               break;
    7039             :             }
    7040             :             break;
    7041             :           case 'o':      // 2 strings to match.
    7042           0 :             if (memcmp(Mnemonic.data()+7, "_f", 2) != 0)
    7043             :               break;
    7044             :             switch (Mnemonic[9]) {
    7045             :             default: break;
    7046             :             case '1':    // 1 string to match.
    7047           0 :               if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7048             :                 break;
    7049           0 :               Mnemonic = "v_cmp_o_f16";        // "v_cmp_o_f16_sdwa"
    7050           0 :               return;
    7051             :             case '3':    // 1 string to match.
    7052           0 :               if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7053             :                 break;
    7054           0 :               Mnemonic = "v_cmp_o_f32";        // "v_cmp_o_f32_sdwa"
    7055           0 :               return;
    7056             :             }
    7057             :             break;
    7058           0 :           case 't':      // 4 strings to match.
    7059           0 :             if (Mnemonic[7] != '_')
    7060             :               break;
    7061             :             switch (Mnemonic[8]) {
    7062             :             default: break;
    7063           0 :             case 'i':    // 2 strings to match.
    7064             :               switch (Mnemonic[9]) {
    7065             :               default: break;
    7066             :               case '1':  // 1 string to match.
    7067           0 :                 if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7068             :                   break;
    7069           0 :                 Mnemonic = "v_cmp_t_i16";      // "v_cmp_t_i16_sdwa"
    7070           0 :                 return;
    7071             :               case '3':  // 1 string to match.
    7072           0 :                 if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7073             :                   break;
    7074           0 :                 Mnemonic = "v_cmp_t_i32";      // "v_cmp_t_i32_sdwa"
    7075           0 :                 return;
    7076             :               }
    7077             :               break;
    7078           0 :             case 'u':    // 2 strings to match.
    7079             :               switch (Mnemonic[9]) {
    7080             :               default: break;
    7081             :               case '1':  // 1 string to match.
    7082           0 :                 if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7083             :                   break;
    7084           0 :                 Mnemonic = "v_cmp_t_u16";      // "v_cmp_t_u16_sdwa"
    7085           0 :                 return;
    7086             :               case '3':  // 1 string to match.
    7087           0 :                 if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7088             :                   break;
    7089           0 :                 Mnemonic = "v_cmp_t_u32";      // "v_cmp_t_u32_sdwa"
    7090           0 :                 return;
    7091             :               }
    7092             :               break;
    7093             :             }
    7094             :             break;
    7095             :           case 'u':      // 2 strings to match.
    7096           0 :             if (memcmp(Mnemonic.data()+7, "_f", 2) != 0)
    7097             :               break;
    7098             :             switch (Mnemonic[9]) {
    7099             :             default: break;
    7100             :             case '1':    // 1 string to match.
    7101           0 :               if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7102             :                 break;
    7103           0 :               Mnemonic = "v_cmp_u_f16";        // "v_cmp_u_f16_sdwa"
    7104           0 :               return;
    7105             :             case '3':    // 1 string to match.
    7106           0 :               if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7107             :                 break;
    7108           0 :               Mnemonic = "v_cmp_u_f32";        // "v_cmp_u_f32_sdwa"
    7109           0 :               return;
    7110             :             }
    7111             :             break;
    7112             :           }
    7113             :           break;
    7114         227 :         case 'f':        // 4 strings to match.
    7115             :           switch (Mnemonic[3]) {
    7116             :           default: break;
    7117             :           case 'l':      // 2 strings to match.
    7118           0 :             if (memcmp(Mnemonic.data()+4, "oor_f", 5) != 0)
    7119             :               break;
    7120             :             switch (Mnemonic[9]) {
    7121             :             default: break;
    7122             :             case '1':    // 1 string to match.
    7123           0 :               if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7124             :                 break;
    7125           0 :               Mnemonic = "v_floor_f16";        // "v_floor_f16_sdwa"
    7126           0 :               return;
    7127             :             case '3':    // 1 string to match.
    7128           0 :               if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7129             :                 break;
    7130           0 :               Mnemonic = "v_floor_f32";        // "v_floor_f32_sdwa"
    7131           0 :               return;
    7132             :             }
    7133             :             break;
    7134             :           case 'r':      // 2 strings to match.
    7135         221 :             if (memcmp(Mnemonic.data()+4, "act_f", 5) != 0)
    7136             :               break;
    7137             :             switch (Mnemonic[9]) {
    7138             :             default: break;
    7139             :             case '1':    // 1 string to match.
    7140           0 :               if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7141             :                 break;
    7142           0 :               Mnemonic = "v_fract_f16";        // "v_fract_f16_sdwa"
    7143           0 :               return;
    7144             :             case '3':    // 1 string to match.
    7145           0 :               if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7146             :                 break;
    7147           0 :               Mnemonic = "v_fract_f32";        // "v_fract_f32_sdwa"
    7148           0 :               return;
    7149             :             }
    7150             :             break;
    7151             :           }
    7152             :           break;
    7153             :         case 'l':        // 1 string to match.
    7154         114 :           if (memcmp(Mnemonic.data()+3, "dexp_f16_sdwa", 13) != 0)
    7155             :             break;
    7156           0 :           Mnemonic = "v_ldexp_f16";    // "v_ldexp_f16_sdwa"
    7157           0 :           return;
    7158             :         case 'r':        // 2 strings to match.
    7159           4 :           if (memcmp(Mnemonic.data()+3, "ndne_f", 6) != 0)
    7160             :             break;
    7161             :           switch (Mnemonic[9]) {
    7162             :           default: break;
    7163             :           case '1':      // 1 string to match.
    7164           0 :             if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7165             :               break;
    7166           0 :             Mnemonic = "v_rndne_f16";  // "v_rndne_f16_sdwa"
    7167           0 :             return;
    7168             :           case '3':      // 1 string to match.
    7169           0 :             if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7170             :               break;
    7171           0 :             Mnemonic = "v_rndne_f32";  // "v_rndne_f32_sdwa"
    7172           0 :             return;
    7173             :           }
    7174             :           break;
    7175             :         case 't':        // 2 strings to match.
    7176           0 :           if (memcmp(Mnemonic.data()+3, "runc_f", 6) != 0)
    7177             :             break;
    7178             :           switch (Mnemonic[9]) {
    7179             :           default: break;
    7180             :           case '1':      // 1 string to match.
    7181           0 :             if (memcmp(Mnemonic.data()+10, "6_sdwa", 6) != 0)
    7182             :               break;
    7183           0 :             Mnemonic = "v_trunc_f16";  // "v_trunc_f16_sdwa"
    7184           0 :             return;
    7185             :           case '3':      // 1 string to match.
    7186           0 :             if (memcmp(Mnemonic.data()+10, "2_sdwa", 6) != 0)
    7187             :               break;
    7188           0 :             Mnemonic = "v_trunc_f32";  // "v_trunc_f32_sdwa"
    7189           0 :             return;
    7190             :           }
    7191             :           break;
    7192             :         }
    7193             :         break;
    7194             :       case 17:   // 59 strings to match.
    7195         356 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    7196             :           break;
    7197             :         switch (Mnemonic[2]) {
    7198             :         default: break;
    7199             :         case 'c':        // 53 strings to match.
    7200         206 :           if (memcmp(Mnemonic.data()+3, "mp", 2) != 0)
    7201             :             break;
    7202             :           switch (Mnemonic[5]) {
    7203             :           default: break;
    7204           0 :           case '_':      // 36 strings to match.
    7205             :             switch (Mnemonic[6]) {
    7206             :             default: break;
    7207             :             case 'e':    // 6 strings to match.
    7208           0 :               if (memcmp(Mnemonic.data()+7, "q_", 2) != 0)
    7209             :                 break;
    7210             :               switch (Mnemonic[9]) {
    7211             :               default: break;
    7212           0 :               case 'f':  // 2 strings to match.
    7213             :                 switch (Mnemonic[10]) {
    7214             :                 default: break;
    7215             :                 case '1':        // 1 string to match.
    7216           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7217             :                     break;
    7218           0 :                   Mnemonic = "v_cmp_eq_f16";   // "v_cmp_eq_f16_sdwa"
    7219           0 :                   return;
    7220             :                 case '3':        // 1 string to match.
    7221           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7222             :                     break;
    7223           0 :                   Mnemonic = "v_cmp_eq_f32";   // "v_cmp_eq_f32_sdwa"
    7224           0 :                   return;
    7225             :                 }
    7226             :                 break;
    7227           0 :               case 'i':  // 2 strings to match.
    7228             :                 switch (Mnemonic[10]) {
    7229             :                 default: break;
    7230             :                 case '1':        // 1 string to match.
    7231           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7232             :                     break;
    7233           0 :                   Mnemonic = "v_cmp_eq_i16";   // "v_cmp_eq_i16_sdwa"
    7234           0 :                   return;
    7235             :                 case '3':        // 1 string to match.
    7236           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7237             :                     break;
    7238           0 :                   Mnemonic = "v_cmp_eq_i32";   // "v_cmp_eq_i32_sdwa"
    7239           0 :                   return;
    7240             :                 }
    7241             :                 break;
    7242           0 :               case 'u':  // 2 strings to match.
    7243             :                 switch (Mnemonic[10]) {
    7244             :                 default: break;
    7245             :                 case '1':        // 1 string to match.
    7246           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7247             :                     break;
    7248           0 :                   Mnemonic = "v_cmp_eq_u16";   // "v_cmp_eq_u16_sdwa"
    7249           0 :                   return;
    7250             :                 case '3':        // 1 string to match.
    7251           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7252             :                     break;
    7253           0 :                   Mnemonic = "v_cmp_eq_u32";   // "v_cmp_eq_u32_sdwa"
    7254           0 :                   return;
    7255             :                 }
    7256             :                 break;
    7257             :               }
    7258             :               break;
    7259           0 :             case 'g':    // 12 strings to match.
    7260             :               switch (Mnemonic[7]) {
    7261             :               default: break;
    7262           0 :               case 'e':  // 6 strings to match.
    7263           0 :                 if (Mnemonic[8] != '_')
    7264             :                   break;
    7265             :                 switch (Mnemonic[9]) {
    7266             :                 default: break;
    7267           0 :                 case 'f':        // 2 strings to match.
    7268             :                   switch (Mnemonic[10]) {
    7269             :                   default: break;
    7270             :                   case '1':      // 1 string to match.
    7271           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7272             :                       break;
    7273           0 :                     Mnemonic = "v_cmp_ge_f16";         // "v_cmp_ge_f16_sdwa"
    7274           0 :                     return;
    7275             :                   case '3':      // 1 string to match.
    7276           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7277             :                       break;
    7278           0 :                     Mnemonic = "v_cmp_ge_f32";         // "v_cmp_ge_f32_sdwa"
    7279           0 :                     return;
    7280             :                   }
    7281             :                   break;
    7282           0 :                 case 'i':        // 2 strings to match.
    7283             :                   switch (Mnemonic[10]) {
    7284             :                   default: break;
    7285             :                   case '1':      // 1 string to match.
    7286           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7287             :                       break;
    7288           0 :                     Mnemonic = "v_cmp_ge_i16";         // "v_cmp_ge_i16_sdwa"
    7289           0 :                     return;
    7290             :                   case '3':      // 1 string to match.
    7291           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7292             :                       break;
    7293           0 :                     Mnemonic = "v_cmp_ge_i32";         // "v_cmp_ge_i32_sdwa"
    7294           0 :                     return;
    7295             :                   }
    7296             :                   break;
    7297           0 :                 case 'u':        // 2 strings to match.
    7298             :                   switch (Mnemonic[10]) {
    7299             :                   default: break;
    7300             :                   case '1':      // 1 string to match.
    7301           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7302             :                       break;
    7303           0 :                     Mnemonic = "v_cmp_ge_u16";         // "v_cmp_ge_u16_sdwa"
    7304           0 :                     return;
    7305             :                   case '3':      // 1 string to match.
    7306           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7307             :                       break;
    7308           0 :                     Mnemonic = "v_cmp_ge_u32";         // "v_cmp_ge_u32_sdwa"
    7309           0 :                     return;
    7310             :                   }
    7311             :                   break;
    7312             :                 }
    7313             :                 break;
    7314           0 :               case 't':  // 6 strings to match.
    7315           0 :                 if (Mnemonic[8] != '_')
    7316             :                   break;
    7317             :                 switch (Mnemonic[9]) {
    7318             :                 default: break;
    7319           0 :                 case 'f':        // 2 strings to match.
    7320             :                   switch (Mnemonic[10]) {
    7321             :                   default: break;
    7322             :                   case '1':      // 1 string to match.
    7323           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7324             :                       break;
    7325           0 :                     Mnemonic = "v_cmp_gt_f16";         // "v_cmp_gt_f16_sdwa"
    7326           0 :                     return;
    7327             :                   case '3':      // 1 string to match.
    7328           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7329             :                       break;
    7330           0 :                     Mnemonic = "v_cmp_gt_f32";         // "v_cmp_gt_f32_sdwa"
    7331           0 :                     return;
    7332             :                   }
    7333             :                   break;
    7334           0 :                 case 'i':        // 2 strings to match.
    7335             :                   switch (Mnemonic[10]) {
    7336             :                   default: break;
    7337             :                   case '1':      // 1 string to match.
    7338           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7339             :                       break;
    7340           0 :                     Mnemonic = "v_cmp_gt_i16";         // "v_cmp_gt_i16_sdwa"
    7341           0 :                     return;
    7342             :                   case '3':      // 1 string to match.
    7343           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7344             :                       break;
    7345           0 :                     Mnemonic = "v_cmp_gt_i32";         // "v_cmp_gt_i32_sdwa"
    7346           0 :                     return;
    7347             :                   }
    7348             :                   break;
    7349           0 :                 case 'u':        // 2 strings to match.
    7350             :                   switch (Mnemonic[10]) {
    7351             :                   default: break;
    7352             :                   case '1':      // 1 string to match.
    7353           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7354             :                       break;
    7355           0 :                     Mnemonic = "v_cmp_gt_u16";         // "v_cmp_gt_u16_sdwa"
    7356           0 :                     return;
    7357             :                   case '3':      // 1 string to match.
    7358           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7359             :                       break;
    7360           0 :                     Mnemonic = "v_cmp_gt_u32";         // "v_cmp_gt_u32_sdwa"
    7361           0 :                     return;
    7362             :                   }
    7363             :                   break;
    7364             :                 }
    7365             :                 break;
    7366             :               }
    7367             :               break;
    7368           0 :             case 'l':    // 14 strings to match.
    7369             :               switch (Mnemonic[7]) {
    7370             :               default: break;
    7371           0 :               case 'e':  // 6 strings to match.
    7372           0 :                 if (Mnemonic[8] != '_')
    7373             :                   break;
    7374             :                 switch (Mnemonic[9]) {
    7375             :                 default: break;
    7376           0 :                 case 'f':        // 2 strings to match.
    7377             :                   switch (Mnemonic[10]) {
    7378             :                   default: break;
    7379             :                   case '1':      // 1 string to match.
    7380           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7381             :                       break;
    7382           0 :                     Mnemonic = "v_cmp_le_f16";         // "v_cmp_le_f16_sdwa"
    7383           0 :                     return;
    7384             :                   case '3':      // 1 string to match.
    7385           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7386             :                       break;
    7387           0 :                     Mnemonic = "v_cmp_le_f32";         // "v_cmp_le_f32_sdwa"
    7388           0 :                     return;
    7389             :                   }
    7390             :                   break;
    7391           0 :                 case 'i':        // 2 strings to match.
    7392             :                   switch (Mnemonic[10]) {
    7393             :                   default: break;
    7394             :                   case '1':      // 1 string to match.
    7395           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7396             :                       break;
    7397           0 :                     Mnemonic = "v_cmp_le_i16";         // "v_cmp_le_i16_sdwa"
    7398           0 :                     return;
    7399             :                   case '3':      // 1 string to match.
    7400           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7401             :                       break;
    7402           0 :                     Mnemonic = "v_cmp_le_i32";         // "v_cmp_le_i32_sdwa"
    7403           0 :                     return;
    7404             :                   }
    7405             :                   break;
    7406           0 :                 case 'u':        // 2 strings to match.
    7407             :                   switch (Mnemonic[10]) {
    7408             :                   default: break;
    7409             :                   case '1':      // 1 string to match.
    7410           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7411             :                       break;
    7412           0 :                     Mnemonic = "v_cmp_le_u16";         // "v_cmp_le_u16_sdwa"
    7413           0 :                     return;
    7414             :                   case '3':      // 1 string to match.
    7415           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7416             :                       break;
    7417           0 :                     Mnemonic = "v_cmp_le_u32";         // "v_cmp_le_u32_sdwa"
    7418           0 :                     return;
    7419             :                   }
    7420             :                   break;
    7421             :                 }
    7422             :                 break;
    7423             :               case 'g':  // 2 strings to match.
    7424           0 :                 if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    7425             :                   break;
    7426             :                 switch (Mnemonic[10]) {
    7427             :                 default: break;
    7428             :                 case '1':        // 1 string to match.
    7429           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7430             :                     break;
    7431           0 :                   Mnemonic = "v_cmp_lg_f16";   // "v_cmp_lg_f16_sdwa"
    7432           0 :                   return;
    7433             :                 case '3':        // 1 string to match.
    7434           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7435             :                     break;
    7436           0 :                   Mnemonic = "v_cmp_lg_f32";   // "v_cmp_lg_f32_sdwa"
    7437           0 :                   return;
    7438             :                 }
    7439             :                 break;
    7440           0 :               case 't':  // 6 strings to match.
    7441           0 :                 if (Mnemonic[8] != '_')
    7442             :                   break;
    7443             :                 switch (Mnemonic[9]) {
    7444             :                 default: break;
    7445           0 :                 case 'f':        // 2 strings to match.
    7446             :                   switch (Mnemonic[10]) {
    7447             :                   default: break;
    7448             :                   case '1':      // 1 string to match.
    7449           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7450             :                       break;
    7451           0 :                     Mnemonic = "v_cmp_lt_f16";         // "v_cmp_lt_f16_sdwa"
    7452           0 :                     return;
    7453             :                   case '3':      // 1 string to match.
    7454           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7455             :                       break;
    7456           0 :                     Mnemonic = "v_cmp_lt_f32";         // "v_cmp_lt_f32_sdwa"
    7457           0 :                     return;
    7458             :                   }
    7459             :                   break;
    7460           0 :                 case 'i':        // 2 strings to match.
    7461             :                   switch (Mnemonic[10]) {
    7462             :                   default: break;
    7463             :                   case '1':      // 1 string to match.
    7464           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7465             :                       break;
    7466           0 :                     Mnemonic = "v_cmp_lt_i16";         // "v_cmp_lt_i16_sdwa"
    7467           0 :                     return;
    7468             :                   case '3':      // 1 string to match.
    7469           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7470             :                       break;
    7471           0 :                     Mnemonic = "v_cmp_lt_i32";         // "v_cmp_lt_i32_sdwa"
    7472           0 :                     return;
    7473             :                   }
    7474             :                   break;
    7475           0 :                 case 'u':        // 2 strings to match.
    7476             :                   switch (Mnemonic[10]) {
    7477             :                   default: break;
    7478             :                   case '1':      // 1 string to match.
    7479           0 :                     if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7480             :                       break;
    7481           0 :                     Mnemonic = "v_cmp_lt_u16";         // "v_cmp_lt_u16_sdwa"
    7482           0 :                     return;
    7483             :                   case '3':      // 1 string to match.
    7484           0 :                     if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7485             :                       break;
    7486           0 :                     Mnemonic = "v_cmp_lt_u32";         // "v_cmp_lt_u32_sdwa"
    7487           0 :                     return;
    7488             :                   }
    7489             :                   break;
    7490             :                 }
    7491             :                 break;
    7492             :               }
    7493             :               break;
    7494             :             case 'n':    // 4 strings to match.
    7495           0 :               if (memcmp(Mnemonic.data()+7, "e_", 2) != 0)
    7496             :                 break;
    7497             :               switch (Mnemonic[9]) {
    7498             :               default: break;
    7499           0 :               case 'i':  // 2 strings to match.
    7500             :                 switch (Mnemonic[10]) {
    7501             :                 default: break;
    7502             :                 case '1':        // 1 string to match.
    7503           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7504             :                     break;
    7505           0 :                   Mnemonic = "v_cmp_ne_i16";   // "v_cmp_ne_i16_sdwa"
    7506           0 :                   return;
    7507             :                 case '3':        // 1 string to match.
    7508           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7509             :                     break;
    7510           0 :                   Mnemonic = "v_cmp_ne_i32";   // "v_cmp_ne_i32_sdwa"
    7511           0 :                   return;
    7512             :                 }
    7513             :                 break;
    7514           0 :               case 'u':  // 2 strings to match.
    7515             :                 switch (Mnemonic[10]) {
    7516             :                 default: break;
    7517             :                 case '1':        // 1 string to match.
    7518           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7519             :                     break;
    7520           0 :                   Mnemonic = "v_cmp_ne_u16";   // "v_cmp_ne_u16_sdwa"
    7521           0 :                   return;
    7522             :                 case '3':        // 1 string to match.
    7523           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7524             :                     break;
    7525           0 :                   Mnemonic = "v_cmp_ne_u32";   // "v_cmp_ne_u32_sdwa"
    7526           0 :                   return;
    7527             :                 }
    7528             :                 break;
    7529             :               }
    7530             :               break;
    7531             :             }
    7532             :             break;
    7533           0 :           case 's':      // 3 strings to match.
    7534           0 :             if (Mnemonic[6] != '_')
    7535             :               break;
    7536             :             switch (Mnemonic[7]) {
    7537             :             default: break;
    7538             :             case 'f':    // 1 string to match.
    7539           0 :               if (memcmp(Mnemonic.data()+8, "_f32_sdwa", 9) != 0)
    7540             :                 break;
    7541           0 :               Mnemonic = "v_cmps_f_f32";       // "v_cmps_f_f32_sdwa"
    7542           0 :               return;
    7543             :             case 'o':    // 1 string to match.
    7544           0 :               if (memcmp(Mnemonic.data()+8, "_f32_sdwa", 9) != 0)
    7545             :                 break;
    7546           0 :               Mnemonic = "v_cmps_o_f32";       // "v_cmps_o_f32_sdwa"
    7547           0 :               return;
    7548             :             case 'u':    // 1 string to match.
    7549           0 :               if (memcmp(Mnemonic.data()+8, "_f32_sdwa", 9) != 0)
    7550             :                 break;
    7551           0 :               Mnemonic = "v_cmps_u_f32";       // "v_cmps_u_f32_sdwa"
    7552           0 :               return;
    7553             :             }
    7554             :             break;
    7555           0 :           case 'x':      // 14 strings to match.
    7556           0 :             if (Mnemonic[6] != '_')
    7557             :               break;
    7558             :             switch (Mnemonic[7]) {
    7559             :             default: break;
    7560           0 :             case 'f':    // 6 strings to match.
    7561           0 :               if (Mnemonic[8] != '_')
    7562             :                 break;
    7563             :               switch (Mnemonic[9]) {
    7564             :               default: break;
    7565           0 :               case 'f':  // 2 strings to match.
    7566             :                 switch (Mnemonic[10]) {
    7567             :                 default: break;
    7568             :                 case '1':        // 1 string to match.
    7569           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7570             :                     break;
    7571           0 :                   Mnemonic = "v_cmpx_f_f16";   // "v_cmpx_f_f16_sdwa"
    7572           0 :                   return;
    7573             :                 case '3':        // 1 string to match.
    7574           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7575             :                     break;
    7576           0 :                   Mnemonic = "v_cmpx_f_f32";   // "v_cmpx_f_f32_sdwa"
    7577           0 :                   return;
    7578             :                 }
    7579             :                 break;
    7580           0 :               case 'i':  // 2 strings to match.
    7581             :                 switch (Mnemonic[10]) {
    7582             :                 default: break;
    7583             :                 case '1':        // 1 string to match.
    7584           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7585             :                     break;
    7586           0 :                   Mnemonic = "v_cmpx_f_i16";   // "v_cmpx_f_i16_sdwa"
    7587           0 :                   return;
    7588             :                 case '3':        // 1 string to match.
    7589           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7590             :                     break;
    7591           0 :                   Mnemonic = "v_cmpx_f_i32";   // "v_cmpx_f_i32_sdwa"
    7592           0 :                   return;
    7593             :                 }
    7594             :                 break;
    7595           0 :               case 'u':  // 2 strings to match.
    7596             :                 switch (Mnemonic[10]) {
    7597             :                 default: break;
    7598             :                 case '1':        // 1 string to match.
    7599           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7600             :                     break;
    7601           0 :                   Mnemonic = "v_cmpx_f_u16";   // "v_cmpx_f_u16_sdwa"
    7602           0 :                   return;
    7603             :                 case '3':        // 1 string to match.
    7604           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7605             :                     break;
    7606           0 :                   Mnemonic = "v_cmpx_f_u32";   // "v_cmpx_f_u32_sdwa"
    7607           0 :                   return;
    7608             :                 }
    7609             :                 break;
    7610             :               }
    7611             :               break;
    7612             :             case 'o':    // 2 strings to match.
    7613           0 :               if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    7614             :                 break;
    7615             :               switch (Mnemonic[10]) {
    7616             :               default: break;
    7617             :               case '1':  // 1 string to match.
    7618           0 :                 if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7619             :                   break;
    7620           0 :                 Mnemonic = "v_cmpx_o_f16";     // "v_cmpx_o_f16_sdwa"
    7621           0 :                 return;
    7622             :               case '3':  // 1 string to match.
    7623           0 :                 if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7624             :                   break;
    7625           0 :                 Mnemonic = "v_cmpx_o_f32";     // "v_cmpx_o_f32_sdwa"
    7626           0 :                 return;
    7627             :               }
    7628             :               break;
    7629           0 :             case 't':    // 4 strings to match.
    7630           0 :               if (Mnemonic[8] != '_')
    7631             :                 break;
    7632             :               switch (Mnemonic[9]) {
    7633             :               default: break;
    7634           0 :               case 'i':  // 2 strings to match.
    7635             :                 switch (Mnemonic[10]) {
    7636             :                 default: break;
    7637             :                 case '1':        // 1 string to match.
    7638           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7639             :                     break;
    7640           0 :                   Mnemonic = "v_cmpx_t_i16";   // "v_cmpx_t_i16_sdwa"
    7641           0 :                   return;
    7642             :                 case '3':        // 1 string to match.
    7643           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7644             :                     break;
    7645           0 :                   Mnemonic = "v_cmpx_t_i32";   // "v_cmpx_t_i32_sdwa"
    7646           0 :                   return;
    7647             :                 }
    7648             :                 break;
    7649           0 :               case 'u':  // 2 strings to match.
    7650             :                 switch (Mnemonic[10]) {
    7651             :                 default: break;
    7652             :                 case '1':        // 1 string to match.
    7653           0 :                   if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7654             :                     break;
    7655           0 :                   Mnemonic = "v_cmpx_t_u16";   // "v_cmpx_t_u16_sdwa"
    7656           0 :                   return;
    7657             :                 case '3':        // 1 string to match.
    7658           0 :                   if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7659             :                     break;
    7660           0 :                   Mnemonic = "v_cmpx_t_u32";   // "v_cmpx_t_u32_sdwa"
    7661           0 :                   return;
    7662             :                 }
    7663             :                 break;
    7664             :               }
    7665             :               break;
    7666             :             case 'u':    // 2 strings to match.
    7667           0 :               if (memcmp(Mnemonic.data()+8, "_f", 2) != 0)
    7668             :                 break;
    7669             :               switch (Mnemonic[10]) {
    7670             :               default: break;
    7671             :               case '1':  // 1 string to match.
    7672           0 :                 if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7673             :                   break;
    7674           0 :                 Mnemonic = "v_cmpx_u_f16";     // "v_cmpx_u_f16_sdwa"
    7675           0 :                 return;
    7676             :               case '3':  // 1 string to match.
    7677           0 :                 if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7678             :                   break;
    7679           0 :                 Mnemonic = "v_cmpx_u_f32";     // "v_cmpx_u_f32_sdwa"
    7680           0 :                 return;
    7681             :               }
    7682             :               break;
    7683             :             }
    7684             :             break;
    7685             :           }
    7686             :           break;
    7687             :         case 'm':        // 1 string to match.
    7688           0 :           if (memcmp(Mnemonic.data()+3, "ul_lo_u16_sdwa", 14) != 0)
    7689             :             break;
    7690           0 :           Mnemonic = "v_mul_lo_u16";   // "v_mul_lo_u16_sdwa"
    7691           0 :           return;
    7692             :         case 's':        // 5 strings to match.
    7693           0 :           if (memcmp(Mnemonic.data()+3, "ubrev_", 6) != 0)
    7694             :             break;
    7695             :           switch (Mnemonic[9]) {
    7696             :           default: break;
    7697           0 :           case 'f':      // 2 strings to match.
    7698             :             switch (Mnemonic[10]) {
    7699             :             default: break;
    7700             :             case '1':    // 1 string to match.
    7701           0 :               if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7702             :                 break;
    7703           0 :               Mnemonic = "v_subrev_f16";       // "v_subrev_f16_sdwa"
    7704           0 :               return;
    7705             :             case '3':    // 1 string to match.
    7706           0 :               if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7707             :                 break;
    7708           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_subrev_f32_sdwa"
    7709           0 :                 Mnemonic = "v_subrev_f32";
    7710             :               return;
    7711             :             }
    7712             :             break;
    7713             :           case 'i':      // 1 string to match.
    7714           0 :             if (memcmp(Mnemonic.data()+10, "32_sdwa", 7) != 0)
    7715             :               break;
    7716           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_subrev_i32_sdwa"
    7717           0 :               Mnemonic = "v_subrev_i32";
    7718             :             return;
    7719           0 :           case 'u':      // 2 strings to match.
    7720             :             switch (Mnemonic[10]) {
    7721             :             default: break;
    7722             :             case '1':    // 1 string to match.
    7723           0 :               if (memcmp(Mnemonic.data()+11, "6_sdwa", 6) != 0)
    7724             :                 break;
    7725           0 :               Mnemonic = "v_subrev_u16";       // "v_subrev_u16_sdwa"
    7726           0 :               return;
    7727             :             case '3':    // 1 string to match.
    7728           0 :               if (memcmp(Mnemonic.data()+11, "2_sdwa", 6) != 0)
    7729             :                 break;
    7730           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_subrev_u32_sdwa"
    7731           0 :                 Mnemonic = "v_subrev_u32";
    7732             :               return;
    7733             :             }
    7734             :             break;
    7735             :           }
    7736             :           break;
    7737             :         }
    7738             :         break;
    7739             :       case 18:   // 80 strings to match.
    7740         143 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    7741             :           break;
    7742             :         switch (Mnemonic[2]) {
    7743             :         default: break;
    7744             :         case 'a':        // 2 strings to match.
    7745           0 :           if (memcmp(Mnemonic.data()+3, "shrrev_i", 8) != 0)
    7746             :             break;
    7747             :           switch (Mnemonic[11]) {
    7748             :           default: break;
    7749             :           case '1':      // 1 string to match.
    7750           0 :             if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7751             :               break;
    7752           0 :             Mnemonic = "v_ashrrev_i16";        // "v_ashrrev_i16_sdwa"
    7753           0 :             return;
    7754             :           case '3':      // 1 string to match.
    7755           0 :             if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7756             :               break;
    7757           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_ashrrev_i32_sdwa"
    7758           0 :               Mnemonic = "v_ashrrev_i32";
    7759             :             return;
    7760             :           }
    7761             :           break;
    7762          20 :         case 'c':        // 70 strings to match.
    7763             :           switch (Mnemonic[3]) {
    7764             :           default: break;
    7765           0 :           case 'm':      // 59 strings to match.
    7766           0 :             if (Mnemonic[4] != 'p')
    7767             :               break;
    7768             :             switch (Mnemonic[5]) {
    7769             :             default: break;
    7770           0 :             case '_':    // 14 strings to match.
    7771             :               switch (Mnemonic[6]) {
    7772             :               default: break;
    7773           0 :               case 'n':  // 12 strings to match.
    7774             :                 switch (Mnemonic[7]) {
    7775             :                 default: break;
    7776             :                 case 'e':        // 2 strings to match.
    7777           0 :                   if (memcmp(Mnemonic.data()+8, "q_f", 3) != 0)
    7778             :                     break;
    7779             :                   switch (Mnemonic[11]) {
    7780             :                   default: break;
    7781             :                   case '1':      // 1 string to match.
    7782           0 :                     if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7783             :                       break;
    7784           0 :                     Mnemonic = "v_cmp_neq_f16";        // "v_cmp_neq_f16_sdwa"
    7785           0 :                     return;
    7786             :                   case '3':      // 1 string to match.
    7787           0 :                     if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7788             :                       break;
    7789           0 :                     Mnemonic = "v_cmp_neq_f32";        // "v_cmp_neq_f32_sdwa"
    7790           0 :                     return;
    7791             :                   }
    7792             :                   break;
    7793           0 :                 case 'g':        // 4 strings to match.
    7794             :                   switch (Mnemonic[8]) {
    7795             :                   default: break;
    7796             :                   case 'e':      // 2 strings to match.
    7797           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    7798             :                       break;
    7799             :                     switch (Mnemonic[11]) {
    7800             :                     default: break;
    7801             :                     case '1':    // 1 string to match.
    7802           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7803             :                         break;
    7804           0 :                       Mnemonic = "v_cmp_nge_f16";      // "v_cmp_nge_f16_sdwa"
    7805           0 :                       return;
    7806             :                     case '3':    // 1 string to match.
    7807           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7808             :                         break;
    7809           0 :                       Mnemonic = "v_cmp_nge_f32";      // "v_cmp_nge_f32_sdwa"
    7810           0 :                       return;
    7811             :                     }
    7812             :                     break;
    7813             :                   case 't':      // 2 strings to match.
    7814           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    7815             :                       break;
    7816             :                     switch (Mnemonic[11]) {
    7817             :                     default: break;
    7818             :                     case '1':    // 1 string to match.
    7819           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7820             :                         break;
    7821           0 :                       Mnemonic = "v_cmp_ngt_f16";      // "v_cmp_ngt_f16_sdwa"
    7822           0 :                       return;
    7823             :                     case '3':    // 1 string to match.
    7824           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7825             :                         break;
    7826           0 :                       Mnemonic = "v_cmp_ngt_f32";      // "v_cmp_ngt_f32_sdwa"
    7827           0 :                       return;
    7828             :                     }
    7829             :                     break;
    7830             :                   }
    7831             :                   break;
    7832           0 :                 case 'l':        // 6 strings to match.
    7833             :                   switch (Mnemonic[8]) {
    7834             :                   default: break;
    7835             :                   case 'e':      // 2 strings to match.
    7836           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    7837             :                       break;
    7838             :                     switch (Mnemonic[11]) {
    7839             :                     default: break;
    7840             :                     case '1':    // 1 string to match.
    7841           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7842             :                         break;
    7843           0 :                       Mnemonic = "v_cmp_nle_f16";      // "v_cmp_nle_f16_sdwa"
    7844           0 :                       return;
    7845             :                     case '3':    // 1 string to match.
    7846           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7847             :                         break;
    7848           0 :                       Mnemonic = "v_cmp_nle_f32";      // "v_cmp_nle_f32_sdwa"
    7849           0 :                       return;
    7850             :                     }
    7851             :                     break;
    7852             :                   case 'g':      // 2 strings to match.
    7853           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    7854             :                       break;
    7855             :                     switch (Mnemonic[11]) {
    7856             :                     default: break;
    7857             :                     case '1':    // 1 string to match.
    7858           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7859             :                         break;
    7860           0 :                       Mnemonic = "v_cmp_nlg_f16";      // "v_cmp_nlg_f16_sdwa"
    7861           0 :                       return;
    7862             :                     case '3':    // 1 string to match.
    7863           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7864             :                         break;
    7865           0 :                       Mnemonic = "v_cmp_nlg_f32";      // "v_cmp_nlg_f32_sdwa"
    7866           0 :                       return;
    7867             :                     }
    7868             :                     break;
    7869             :                   case 't':      // 2 strings to match.
    7870           0 :                     if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    7871             :                       break;
    7872             :                     switch (Mnemonic[11]) {
    7873             :                     default: break;
    7874             :                     case '1':    // 1 string to match.
    7875           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7876             :                         break;
    7877           0 :                       Mnemonic = "v_cmp_nlt_f16";      // "v_cmp_nlt_f16_sdwa"
    7878           0 :                       return;
    7879             :                     case '3':    // 1 string to match.
    7880           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7881             :                         break;
    7882           0 :                       Mnemonic = "v_cmp_nlt_f32";      // "v_cmp_nlt_f32_sdwa"
    7883           0 :                       return;
    7884             :                     }
    7885             :                     break;
    7886             :                   }
    7887             :                   break;
    7888             :                 }
    7889             :                 break;
    7890             :               case 't':  // 2 strings to match.
    7891           0 :                 if (memcmp(Mnemonic.data()+7, "ru_f", 4) != 0)
    7892             :                   break;
    7893             :                 switch (Mnemonic[11]) {
    7894             :                 default: break;
    7895             :                 case '1':        // 1 string to match.
    7896           0 :                   if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7897             :                     break;
    7898           0 :                   Mnemonic = "v_cmp_tru_f16";  // "v_cmp_tru_f16_sdwa"
    7899           0 :                   return;
    7900             :                 case '3':        // 1 string to match.
    7901           0 :                   if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    7902             :                     break;
    7903           0 :                   Mnemonic = "v_cmp_tru_f32";  // "v_cmp_tru_f32_sdwa"
    7904           0 :                   return;
    7905             :                 }
    7906             :                 break;
    7907             :               }
    7908             :               break;
    7909           0 :             case 's':    // 9 strings to match.
    7910             :               switch (Mnemonic[6]) {
    7911             :               default: break;
    7912           0 :               case '_':  // 6 strings to match.
    7913             :                 switch (Mnemonic[7]) {
    7914             :                 default: break;
    7915             :                 case 'e':        // 1 string to match.
    7916           0 :                   if (memcmp(Mnemonic.data()+8, "q_f32_sdwa", 10) != 0)
    7917             :                     break;
    7918           0 :                   Mnemonic = "v_cmps_eq_f32";  // "v_cmps_eq_f32_sdwa"
    7919           0 :                   return;
    7920           0 :                 case 'g':        // 2 strings to match.
    7921             :                   switch (Mnemonic[8]) {
    7922             :                   default: break;
    7923             :                   case 'e':      // 1 string to match.
    7924           0 :                     if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7925             :                       break;
    7926           0 :                     Mnemonic = "v_cmps_ge_f32";        // "v_cmps_ge_f32_sdwa"
    7927           0 :                     return;
    7928             :                   case 't':      // 1 string to match.
    7929           0 :                     if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7930             :                       break;
    7931           0 :                     Mnemonic = "v_cmps_gt_f32";        // "v_cmps_gt_f32_sdwa"
    7932           0 :                     return;
    7933             :                   }
    7934             :                   break;
    7935           0 :                 case 'l':        // 3 strings to match.
    7936             :                   switch (Mnemonic[8]) {
    7937             :                   default: break;
    7938             :                   case 'e':      // 1 string to match.
    7939           0 :                     if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7940             :                       break;
    7941           0 :                     Mnemonic = "v_cmps_le_f32";        // "v_cmps_le_f32_sdwa"
    7942           0 :                     return;
    7943             :                   case 'g':      // 1 string to match.
    7944           0 :                     if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7945             :                       break;
    7946           0 :                     Mnemonic = "v_cmps_lg_f32";        // "v_cmps_lg_f32_sdwa"
    7947           0 :                     return;
    7948             :                   case 't':      // 1 string to match.
    7949           0 :                     if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7950             :                       break;
    7951           0 :                     Mnemonic = "v_cmps_lt_f32";        // "v_cmps_lt_f32_sdwa"
    7952           0 :                     return;
    7953             :                   }
    7954             :                   break;
    7955             :                 }
    7956             :                 break;
    7957           0 :               case 'x':  // 3 strings to match.
    7958           0 :                 if (Mnemonic[7] != '_')
    7959             :                   break;
    7960             :                 switch (Mnemonic[8]) {
    7961             :                 default: break;
    7962             :                 case 'f':        // 1 string to match.
    7963           0 :                   if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7964             :                     break;
    7965           0 :                   Mnemonic = "v_cmpsx_f_f32";  // "v_cmpsx_f_f32_sdwa"
    7966           0 :                   return;
    7967             :                 case 'o':        // 1 string to match.
    7968           0 :                   if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7969             :                     break;
    7970           0 :                   Mnemonic = "v_cmpsx_o_f32";  // "v_cmpsx_o_f32_sdwa"
    7971           0 :                   return;
    7972             :                 case 'u':        // 1 string to match.
    7973           0 :                   if (memcmp(Mnemonic.data()+9, "_f32_sdwa", 9) != 0)
    7974             :                     break;
    7975           0 :                   Mnemonic = "v_cmpsx_u_f32";  // "v_cmpsx_u_f32_sdwa"
    7976           0 :                   return;
    7977             :                 }
    7978             :                 break;
    7979             :               }
    7980             :               break;
    7981           0 :             case 'x':    // 36 strings to match.
    7982           0 :               if (Mnemonic[6] != '_')
    7983             :                 break;
    7984             :               switch (Mnemonic[7]) {
    7985             :               default: break;
    7986             :               case 'e':  // 6 strings to match.
    7987           0 :                 if (memcmp(Mnemonic.data()+8, "q_", 2) != 0)
    7988             :                   break;
    7989             :                 switch (Mnemonic[10]) {
    7990             :                 default: break;
    7991           0 :                 case 'f':        // 2 strings to match.
    7992             :                   switch (Mnemonic[11]) {
    7993             :                   default: break;
    7994             :                   case '1':      // 1 string to match.
    7995           0 :                     if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    7996             :                       break;
    7997           0 :                     Mnemonic = "v_cmpx_eq_f16";        // "v_cmpx_eq_f16_sdwa"
    7998           0 :                     return;
    7999             :                   case '3':      // 1 string to match.
    8000           0 :                     if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8001             :                       break;
    8002           0 :                     Mnemonic = "v_cmpx_eq_f32";        // "v_cmpx_eq_f32_sdwa"
    8003           0 :                     return;
    8004             :                   }
    8005             :                   break;
    8006           0 :                 case 'i':        // 2 strings to match.
    8007             :                   switch (Mnemonic[11]) {
    8008             :                   default: break;
    8009             :                   case '1':      // 1 string to match.
    8010           0 :                     if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8011             :                       break;
    8012           0 :                     Mnemonic = "v_cmpx_eq_i16";        // "v_cmpx_eq_i16_sdwa"
    8013           0 :                     return;
    8014             :                   case '3':      // 1 string to match.
    8015           0 :                     if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8016             :                       break;
    8017           0 :                     Mnemonic = "v_cmpx_eq_i32";        // "v_cmpx_eq_i32_sdwa"
    8018           0 :                     return;
    8019             :                   }
    8020             :                   break;
    8021           0 :                 case 'u':        // 2 strings to match.
    8022             :                   switch (Mnemonic[11]) {
    8023             :                   default: break;
    8024             :                   case '1':      // 1 string to match.
    8025           0 :                     if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8026             :                       break;
    8027           0 :                     Mnemonic = "v_cmpx_eq_u16";        // "v_cmpx_eq_u16_sdwa"
    8028           0 :                     return;
    8029             :                   case '3':      // 1 string to match.
    8030           0 :                     if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8031             :                       break;
    8032           0 :                     Mnemonic = "v_cmpx_eq_u32";        // "v_cmpx_eq_u32_sdwa"
    8033           0 :                     return;
    8034             :                   }
    8035             :                   break;
    8036             :                 }
    8037             :                 break;
    8038           0 :               case 'g':  // 12 strings to match.
    8039             :                 switch (Mnemonic[8]) {
    8040             :                 default: break;
    8041           0 :                 case 'e':        // 6 strings to match.
    8042           0 :                   if (Mnemonic[9] != '_')
    8043             :                     break;
    8044             :                   switch (Mnemonic[10]) {
    8045             :                   default: break;
    8046           0 :                   case 'f':      // 2 strings to match.
    8047             :                     switch (Mnemonic[11]) {
    8048             :                     default: break;
    8049             :                     case '1':    // 1 string to match.
    8050           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8051             :                         break;
    8052           0 :                       Mnemonic = "v_cmpx_ge_f16";      // "v_cmpx_ge_f16_sdwa"
    8053           0 :                       return;
    8054             :                     case '3':    // 1 string to match.
    8055           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8056             :                         break;
    8057           0 :                       Mnemonic = "v_cmpx_ge_f32";      // "v_cmpx_ge_f32_sdwa"
    8058           0 :                       return;
    8059             :                     }
    8060             :                     break;
    8061           0 :                   case 'i':      // 2 strings to match.
    8062             :                     switch (Mnemonic[11]) {
    8063             :                     default: break;
    8064             :                     case '1':    // 1 string to match.
    8065           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8066             :                         break;
    8067           0 :                       Mnemonic = "v_cmpx_ge_i16";      // "v_cmpx_ge_i16_sdwa"
    8068           0 :                       return;
    8069             :                     case '3':    // 1 string to match.
    8070           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8071             :                         break;
    8072           0 :                       Mnemonic = "v_cmpx_ge_i32";      // "v_cmpx_ge_i32_sdwa"
    8073           0 :                       return;
    8074             :                     }
    8075             :                     break;
    8076           0 :                   case 'u':      // 2 strings to match.
    8077             :                     switch (Mnemonic[11]) {
    8078             :                     default: break;
    8079             :                     case '1':    // 1 string to match.
    8080           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8081             :                         break;
    8082           0 :                       Mnemonic = "v_cmpx_ge_u16";      // "v_cmpx_ge_u16_sdwa"
    8083           0 :                       return;
    8084             :                     case '3':    // 1 string to match.
    8085           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8086             :                         break;
    8087           0 :                       Mnemonic = "v_cmpx_ge_u32";      // "v_cmpx_ge_u32_sdwa"
    8088           0 :                       return;
    8089             :                     }
    8090             :                     break;
    8091             :                   }
    8092             :                   break;
    8093           0 :                 case 't':        // 6 strings to match.
    8094           0 :                   if (Mnemonic[9] != '_')
    8095             :                     break;
    8096             :                   switch (Mnemonic[10]) {
    8097             :                   default: break;
    8098           0 :                   case 'f':      // 2 strings to match.
    8099             :                     switch (Mnemonic[11]) {
    8100             :                     default: break;
    8101             :                     case '1':    // 1 string to match.
    8102           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8103             :                         break;
    8104           0 :                       Mnemonic = "v_cmpx_gt_f16";      // "v_cmpx_gt_f16_sdwa"
    8105           0 :                       return;
    8106             :                     case '3':    // 1 string to match.
    8107           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8108             :                         break;
    8109           0 :                       Mnemonic = "v_cmpx_gt_f32";      // "v_cmpx_gt_f32_sdwa"
    8110           0 :                       return;
    8111             :                     }
    8112             :                     break;
    8113           0 :                   case 'i':      // 2 strings to match.
    8114             :                     switch (Mnemonic[11]) {
    8115             :                     default: break;
    8116             :                     case '1':    // 1 string to match.
    8117           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8118             :                         break;
    8119           0 :                       Mnemonic = "v_cmpx_gt_i16";      // "v_cmpx_gt_i16_sdwa"
    8120           0 :                       return;
    8121             :                     case '3':    // 1 string to match.
    8122           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8123             :                         break;
    8124           0 :                       Mnemonic = "v_cmpx_gt_i32";      // "v_cmpx_gt_i32_sdwa"
    8125           0 :                       return;
    8126             :                     }
    8127             :                     break;
    8128           0 :                   case 'u':      // 2 strings to match.
    8129             :                     switch (Mnemonic[11]) {
    8130             :                     default: break;
    8131             :                     case '1':    // 1 string to match.
    8132           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8133             :                         break;
    8134           0 :                       Mnemonic = "v_cmpx_gt_u16";      // "v_cmpx_gt_u16_sdwa"
    8135           0 :                       return;
    8136             :                     case '3':    // 1 string to match.
    8137           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8138             :                         break;
    8139           0 :                       Mnemonic = "v_cmpx_gt_u32";      // "v_cmpx_gt_u32_sdwa"
    8140           0 :                       return;
    8141             :                     }
    8142             :                     break;
    8143             :                   }
    8144             :                   break;
    8145             :                 }
    8146             :                 break;
    8147           0 :               case 'l':  // 14 strings to match.
    8148             :                 switch (Mnemonic[8]) {
    8149             :                 default: break;
    8150           0 :                 case 'e':        // 6 strings to match.
    8151           0 :                   if (Mnemonic[9] != '_')
    8152             :                     break;
    8153             :                   switch (Mnemonic[10]) {
    8154             :                   default: break;
    8155           0 :                   case 'f':      // 2 strings to match.
    8156             :                     switch (Mnemonic[11]) {
    8157             :                     default: break;
    8158             :                     case '1':    // 1 string to match.
    8159           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8160             :                         break;
    8161           0 :                       Mnemonic = "v_cmpx_le_f16";      // "v_cmpx_le_f16_sdwa"
    8162           0 :                       return;
    8163             :                     case '3':    // 1 string to match.
    8164           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8165             :                         break;
    8166           0 :                       Mnemonic = "v_cmpx_le_f32";      // "v_cmpx_le_f32_sdwa"
    8167           0 :                       return;
    8168             :                     }
    8169             :                     break;
    8170           0 :                   case 'i':      // 2 strings to match.
    8171             :                     switch (Mnemonic[11]) {
    8172             :                     default: break;
    8173             :                     case '1':    // 1 string to match.
    8174           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8175             :                         break;
    8176           0 :                       Mnemonic = "v_cmpx_le_i16";      // "v_cmpx_le_i16_sdwa"
    8177           0 :                       return;
    8178             :                     case '3':    // 1 string to match.
    8179           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8180             :                         break;
    8181           0 :                       Mnemonic = "v_cmpx_le_i32";      // "v_cmpx_le_i32_sdwa"
    8182           0 :                       return;
    8183             :                     }
    8184             :                     break;
    8185           0 :                   case 'u':      // 2 strings to match.
    8186             :                     switch (Mnemonic[11]) {
    8187             :                     default: break;
    8188             :                     case '1':    // 1 string to match.
    8189           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8190             :                         break;
    8191           0 :                       Mnemonic = "v_cmpx_le_u16";      // "v_cmpx_le_u16_sdwa"
    8192           0 :                       return;
    8193             :                     case '3':    // 1 string to match.
    8194           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8195             :                         break;
    8196           0 :                       Mnemonic = "v_cmpx_le_u32";      // "v_cmpx_le_u32_sdwa"
    8197           0 :                       return;
    8198             :                     }
    8199             :                     break;
    8200             :                   }
    8201             :                   break;
    8202             :                 case 'g':        // 2 strings to match.
    8203           0 :                   if (memcmp(Mnemonic.data()+9, "_f", 2) != 0)
    8204             :                     break;
    8205             :                   switch (Mnemonic[11]) {
    8206             :                   default: break;
    8207             :                   case '1':      // 1 string to match.
    8208           0 :                     if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8209             :                       break;
    8210           0 :                     Mnemonic = "v_cmpx_lg_f16";        // "v_cmpx_lg_f16_sdwa"
    8211           0 :                     return;
    8212             :                   case '3':      // 1 string to match.
    8213           0 :                     if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8214             :                       break;
    8215           0 :                     Mnemonic = "v_cmpx_lg_f32";        // "v_cmpx_lg_f32_sdwa"
    8216           0 :                     return;
    8217             :                   }
    8218             :                   break;
    8219           0 :                 case 't':        // 6 strings to match.
    8220           0 :                   if (Mnemonic[9] != '_')
    8221             :                     break;
    8222             :                   switch (Mnemonic[10]) {
    8223             :                   default: break;
    8224           0 :                   case 'f':      // 2 strings to match.
    8225             :                     switch (Mnemonic[11]) {
    8226             :                     default: break;
    8227             :                     case '1':    // 1 string to match.
    8228           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8229             :                         break;
    8230           0 :                       Mnemonic = "v_cmpx_lt_f16";      // "v_cmpx_lt_f16_sdwa"
    8231           0 :                       return;
    8232             :                     case '3':    // 1 string to match.
    8233           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8234             :                         break;
    8235           0 :                       Mnemonic = "v_cmpx_lt_f32";      // "v_cmpx_lt_f32_sdwa"
    8236           0 :                       return;
    8237             :                     }
    8238             :                     break;
    8239           0 :                   case 'i':      // 2 strings to match.
    8240             :                     switch (Mnemonic[11]) {
    8241             :                     default: break;
    8242             :                     case '1':    // 1 string to match.
    8243           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8244             :                         break;
    8245           0 :                       Mnemonic = "v_cmpx_lt_i16";      // "v_cmpx_lt_i16_sdwa"
    8246           0 :                       return;
    8247             :                     case '3':    // 1 string to match.
    8248           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8249             :                         break;
    8250           0 :                       Mnemonic = "v_cmpx_lt_i32";      // "v_cmpx_lt_i32_sdwa"
    8251           0 :                       return;
    8252             :                     }
    8253             :                     break;
    8254           0 :                   case 'u':      // 2 strings to match.
    8255             :                     switch (Mnemonic[11]) {
    8256             :                     default: break;
    8257             :                     case '1':    // 1 string to match.
    8258           0 :                       if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8259             :                         break;
    8260           0 :                       Mnemonic = "v_cmpx_lt_u16";      // "v_cmpx_lt_u16_sdwa"
    8261           0 :                       return;
    8262             :                     case '3':    // 1 string to match.
    8263           0 :                       if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8264             :                         break;
    8265           0 :                       Mnemonic = "v_cmpx_lt_u32";      // "v_cmpx_lt_u32_sdwa"
    8266           0 :                       return;
    8267             :                     }
    8268             :                     break;
    8269             :                   }
    8270             :                   break;
    8271             :                 }
    8272             :                 break;
    8273             :               case 'n':  // 4 strings to match.
    8274           0 :                 if (memcmp(Mnemonic.data()+8, "e_", 2) != 0)
    8275             :                   break;
    8276             :                 switch (Mnemonic[10]) {
    8277             :                 default: break;
    8278           0 :                 case 'i':        // 2 strings to match.
    8279             :                   switch (Mnemonic[11]) {
    8280             :                   default: break;
    8281             :                   case '1':      // 1 string to match.
    8282           0 :                     if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8283             :                       break;
    8284           0 :                     Mnemonic = "v_cmpx_ne_i16";        // "v_cmpx_ne_i16_sdwa"
    8285           0 :                     return;
    8286             :                   case '3':      // 1 string to match.
    8287           0 :                     if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8288             :                       break;
    8289           0 :                     Mnemonic = "v_cmpx_ne_i32";        // "v_cmpx_ne_i32_sdwa"
    8290           0 :                     return;
    8291             :                   }
    8292             :                   break;
    8293           0 :                 case 'u':        // 2 strings to match.
    8294             :                   switch (Mnemonic[11]) {
    8295             :                   default: break;
    8296             :                   case '1':      // 1 string to match.
    8297           0 :                     if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8298             :                       break;
    8299           0 :                     Mnemonic = "v_cmpx_ne_u16";        // "v_cmpx_ne_u16_sdwa"
    8300           0 :                     return;
    8301             :                   case '3':      // 1 string to match.
    8302           0 :                     if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8303             :                       break;
    8304           0 :                     Mnemonic = "v_cmpx_ne_u32";        // "v_cmpx_ne_u32_sdwa"
    8305           0 :                     return;
    8306             :                   }
    8307             :                   break;
    8308             :                 }
    8309             :                 break;
    8310             :               }
    8311             :               break;
    8312             :             }
    8313             :             break;
    8314             :           case 'n':      // 1 string to match.
    8315           0 :             if (memcmp(Mnemonic.data()+4, "dmask_b32_sdwa", 14) != 0)
    8316             :               break;
    8317           0 :             if ((Features & Feature_isGCN) == Feature_isGCN)         // "v_cndmask_b32_sdwa"
    8318           0 :               Mnemonic = "v_cndmask_b32";
    8319             :             return;
    8320             :           case 'v':      // 10 strings to match.
    8321          20 :             if (memcmp(Mnemonic.data()+4, "t_", 2) != 0)
    8322             :               break;
    8323             :             switch (Mnemonic[6]) {
    8324             :             default: break;
    8325           0 :             case 'f':    // 6 strings to match.
    8326             :               switch (Mnemonic[7]) {
    8327             :               default: break;
    8328             :               case '1':  // 3 strings to match.
    8329           0 :                 if (memcmp(Mnemonic.data()+8, "6_", 2) != 0)
    8330             :                   break;
    8331             :                 switch (Mnemonic[10]) {
    8332             :                 default: break;
    8333             :                 case 'f':        // 1 string to match.
    8334           0 :                   if (memcmp(Mnemonic.data()+11, "32_sdwa", 7) != 0)
    8335             :                     break;
    8336           0 :                   Mnemonic = "v_cvt_f16_f32";  // "v_cvt_f16_f32_sdwa"
    8337           0 :                   return;
    8338             :                 case 'i':        // 1 string to match.
    8339           0 :                   if (memcmp(Mnemonic.data()+11, "16_sdwa", 7) != 0)
    8340             :                     break;
    8341           0 :                   Mnemonic = "v_cvt_f16_i16";  // "v_cvt_f16_i16_sdwa"
    8342           0 :                   return;
    8343             :                 case 'u':        // 1 string to match.
    8344           0 :                   if (memcmp(Mnemonic.data()+11, "16_sdwa", 7) != 0)
    8345             :                     break;
    8346           0 :                   Mnemonic = "v_cvt_f16_u16";  // "v_cvt_f16_u16_sdwa"
    8347           0 :                   return;
    8348             :                 }
    8349             :                 break;
    8350             :               case '3':  // 3 strings to match.
    8351           0 :                 if (memcmp(Mnemonic.data()+8, "2_", 2) != 0)
    8352             :                   break;
    8353             :                 switch (Mnemonic[10]) {
    8354             :                 default: break;
    8355             :                 case 'f':        // 1 string to match.
    8356           0 :                   if (memcmp(Mnemonic.data()+11, "16_sdwa", 7) != 0)
    8357             :                     break;
    8358           0 :                   Mnemonic = "v_cvt_f32_f16";  // "v_cvt_f32_f16_sdwa"
    8359           0 :                   return;
    8360             :                 case 'i':        // 1 string to match.
    8361           0 :                   if (memcmp(Mnemonic.data()+11, "32_sdwa", 7) != 0)
    8362             :                     break;
    8363           0 :                   Mnemonic = "v_cvt_f32_i32";  // "v_cvt_f32_i32_sdwa"
    8364           0 :                   return;
    8365             :                 case 'u':        // 1 string to match.
    8366           0 :                   if (memcmp(Mnemonic.data()+11, "32_sdwa", 7) != 0)
    8367             :                     break;
    8368           0 :                   Mnemonic = "v_cvt_f32_u32";  // "v_cvt_f32_u32_sdwa"
    8369           0 :                   return;
    8370             :                 }
    8371             :                 break;
    8372             :               }
    8373             :               break;
    8374           0 :             case 'i':    // 2 strings to match.
    8375             :               switch (Mnemonic[7]) {
    8376             :               default: break;
    8377             :               case '1':  // 1 string to match.
    8378           0 :                 if (memcmp(Mnemonic.data()+8, "6_f16_sdwa", 10) != 0)
    8379             :                   break;
    8380           0 :                 Mnemonic = "v_cvt_i16_f16";    // "v_cvt_i16_f16_sdwa"
    8381           0 :                 return;
    8382             :               case '3':  // 1 string to match.
    8383           0 :                 if (memcmp(Mnemonic.data()+8, "2_f32_sdwa", 10) != 0)
    8384             :                   break;
    8385           0 :                 Mnemonic = "v_cvt_i32_f32";    // "v_cvt_i32_f32_sdwa"
    8386           0 :                 return;
    8387             :               }
    8388             :               break;
    8389           0 :             case 'u':    // 2 strings to match.
    8390             :               switch (Mnemonic[7]) {
    8391             :               default: break;
    8392             :               case '1':  // 1 string to match.
    8393           0 :                 if (memcmp(Mnemonic.data()+8, "6_f16_sdwa", 10) != 0)
    8394             :                   break;
    8395           0 :                 Mnemonic = "v_cvt_u16_f16";    // "v_cvt_u16_f16_sdwa"
    8396           0 :                 return;
    8397             :               case '3':  // 1 string to match.
    8398           0 :                 if (memcmp(Mnemonic.data()+8, "2_f32_sdwa", 10) != 0)
    8399             :                   break;
    8400           0 :                 Mnemonic = "v_cvt_u32_f32";    // "v_cvt_u32_f32_sdwa"
    8401           0 :                 return;
    8402             :               }
    8403             :               break;
    8404             :             }
    8405             :             break;
    8406             :           }
    8407             :           break;
    8408             :         case 'l':        // 4 strings to match.
    8409           0 :           if (memcmp(Mnemonic.data()+3, "sh", 2) != 0)
    8410             :             break;
    8411             :           switch (Mnemonic[5]) {
    8412             :           default: break;
    8413             :           case 'l':      // 2 strings to match.
    8414           0 :             if (memcmp(Mnemonic.data()+6, "rev_b", 5) != 0)
    8415             :               break;
    8416             :             switch (Mnemonic[11]) {
    8417             :             default: break;
    8418             :             case '1':    // 1 string to match.
    8419           0 :               if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8420             :                 break;
    8421           0 :               Mnemonic = "v_lshlrev_b16";      // "v_lshlrev_b16_sdwa"
    8422           0 :               return;
    8423             :             case '3':    // 1 string to match.
    8424           0 :               if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8425             :                 break;
    8426           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_lshlrev_b32_sdwa"
    8427           0 :                 Mnemonic = "v_lshlrev_b32";
    8428             :               return;
    8429             :             }
    8430             :             break;
    8431             :           case 'r':      // 2 strings to match.
    8432           0 :             if (memcmp(Mnemonic.data()+6, "rev_b", 5) != 0)
    8433             :               break;
    8434             :             switch (Mnemonic[11]) {
    8435             :             default: break;
    8436             :             case '1':    // 1 string to match.
    8437           0 :               if (memcmp(Mnemonic.data()+12, "6_sdwa", 6) != 0)
    8438             :                 break;
    8439           0 :               Mnemonic = "v_lshrrev_b16";      // "v_lshrrev_b16_sdwa"
    8440           0 :               return;
    8441             :             case '3':    // 1 string to match.
    8442           0 :               if (memcmp(Mnemonic.data()+12, "2_sdwa", 6) != 0)
    8443             :                 break;
    8444           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_lshrrev_b32_sdwa"
    8445           0 :                 Mnemonic = "v_lshrrev_b32";
    8446             :               return;
    8447             :             }
    8448             :             break;
    8449             :           }
    8450             :           break;
    8451           0 :         case 'm':        // 3 strings to match.
    8452             :           switch (Mnemonic[3]) {
    8453             :           default: break;
    8454             :           case 'o':      // 1 string to match.
    8455           0 :             if (memcmp(Mnemonic.data()+4, "v_fed_b32_sdwa", 14) != 0)
    8456             :               break;
    8457           0 :             Mnemonic = "v_mov_fed_b32";        // "v_mov_fed_b32_sdwa"
    8458           0 :             return;
    8459             :           case 'u':      // 2 strings to match.
    8460           0 :             if (memcmp(Mnemonic.data()+4, "l_", 2) != 0)
    8461             :               break;
    8462             :             switch (Mnemonic[6]) {
    8463             :             default: break;
    8464             :             case 'i':    // 1 string to match.
    8465           0 :               if (memcmp(Mnemonic.data()+7, "32_i24_sdwa", 11) != 0)
    8466             :                 break;
    8467           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_i32_i24_sdwa"
    8468           0 :                 Mnemonic = "v_mul_i32_i24";
    8469             :               return;
    8470             :             case 'u':    // 1 string to match.
    8471           0 :               if (memcmp(Mnemonic.data()+7, "32_u24_sdwa", 11) != 0)
    8472             :                 break;
    8473           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_u32_u24_sdwa"
    8474           0 :                 Mnemonic = "v_mul_u32_u24";
    8475             :               return;
    8476             :             }
    8477             :             break;
    8478             :           }
    8479             :           break;
    8480             :         case 's':        // 1 string to match.
    8481           0 :           if (memcmp(Mnemonic.data()+3, "ubbrev_u32_sdwa", 15) != 0)
    8482             :             break;
    8483           0 :           if ((Features & Feature_isGCN) == Feature_isGCN)   // "v_subbrev_u32_sdwa"
    8484           0 :             Mnemonic = "v_subbrev_u32";
    8485             :           return;
    8486             :         }
    8487             :         break;
    8488             :       case 19:   // 27 strings to match.
    8489         422 :         if (memcmp(Mnemonic.data()+0, "v_cmp", 5) != 0)
    8490             :           break;
    8491             :         switch (Mnemonic[5]) {
    8492             :         default: break;
    8493           0 :         case 's':        // 13 strings to match.
    8494             :           switch (Mnemonic[6]) {
    8495             :           default: break;
    8496           0 :           case '_':      // 7 strings to match.
    8497             :             switch (Mnemonic[7]) {
    8498             :             default: break;
    8499           0 :             case 'n':    // 6 strings to match.
    8500             :               switch (Mnemonic[8]) {
    8501             :               default: break;
    8502             :               case 'e':  // 1 string to match.
    8503           0 :                 if (memcmp(Mnemonic.data()+9, "q_f32_sdwa", 10) != 0)
    8504             :                   break;
    8505           0 :                 Mnemonic = "v_cmps_neq_f32";   // "v_cmps_neq_f32_sdwa"
    8506           0 :                 return;
    8507           0 :               case 'g':  // 2 strings to match.
    8508             :                 switch (Mnemonic[9]) {
    8509             :                 default: break;
    8510             :                 case 'e':        // 1 string to match.
    8511           0 :                   if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8512             :                     break;
    8513           0 :                   Mnemonic = "v_cmps_nge_f32";         // "v_cmps_nge_f32_sdwa"
    8514           0 :                   return;
    8515             :                 case 't':        // 1 string to match.
    8516           0 :                   if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8517             :                     break;
    8518           0 :                   Mnemonic = "v_cmps_ngt_f32";         // "v_cmps_ngt_f32_sdwa"
    8519           0 :                   return;
    8520             :                 }
    8521             :                 break;
    8522           0 :               case 'l':  // 3 strings to match.
    8523             :                 switch (Mnemonic[9]) {
    8524             :                 default: break;
    8525             :                 case 'e':        // 1 string to match.
    8526           0 :                   if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8527             :                     break;
    8528           0 :                   Mnemonic = "v_cmps_nle_f32";         // "v_cmps_nle_f32_sdwa"
    8529           0 :                   return;
    8530             :                 case 'g':        // 1 string to match.
    8531           0 :                   if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8532             :                     break;
    8533           0 :                   Mnemonic = "v_cmps_nlg_f32";         // "v_cmps_nlg_f32_sdwa"
    8534           0 :                   return;
    8535             :                 case 't':        // 1 string to match.
    8536           0 :                   if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8537             :                     break;
    8538           0 :                   Mnemonic = "v_cmps_nlt_f32";         // "v_cmps_nlt_f32_sdwa"
    8539           0 :                   return;
    8540             :                 }
    8541             :                 break;
    8542             :               }
    8543             :               break;
    8544             :             case 't':    // 1 string to match.
    8545           0 :               if (memcmp(Mnemonic.data()+8, "ru_f32_sdwa", 11) != 0)
    8546             :                 break;
    8547           0 :               Mnemonic = "v_cmps_tru_f32";     // "v_cmps_tru_f32_sdwa"
    8548           0 :               return;
    8549             :             }
    8550             :             break;
    8551           0 :           case 'x':      // 6 strings to match.
    8552           0 :             if (Mnemonic[7] != '_')
    8553             :               break;
    8554             :             switch (Mnemonic[8]) {
    8555             :             default: break;
    8556             :             case 'e':    // 1 string to match.
    8557           0 :               if (memcmp(Mnemonic.data()+9, "q_f32_sdwa", 10) != 0)
    8558             :                 break;
    8559           0 :               Mnemonic = "v_cmpsx_eq_f32";     // "v_cmpsx_eq_f32_sdwa"
    8560           0 :               return;
    8561           0 :             case 'g':    // 2 strings to match.
    8562             :               switch (Mnemonic[9]) {
    8563             :               default: break;
    8564             :               case 'e':  // 1 string to match.
    8565           0 :                 if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8566             :                   break;
    8567           0 :                 Mnemonic = "v_cmpsx_ge_f32";   // "v_cmpsx_ge_f32_sdwa"
    8568           0 :                 return;
    8569             :               case 't':  // 1 string to match.
    8570           0 :                 if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8571             :                   break;
    8572           0 :                 Mnemonic = "v_cmpsx_gt_f32";   // "v_cmpsx_gt_f32_sdwa"
    8573           0 :                 return;
    8574             :               }
    8575             :               break;
    8576           0 :             case 'l':    // 3 strings to match.
    8577             :               switch (Mnemonic[9]) {
    8578             :               default: break;
    8579             :               case 'e':  // 1 string to match.
    8580           0 :                 if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8581             :                   break;
    8582           0 :                 Mnemonic = "v_cmpsx_le_f32";   // "v_cmpsx_le_f32_sdwa"
    8583           0 :                 return;
    8584             :               case 'g':  // 1 string to match.
    8585           0 :                 if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8586             :                   break;
    8587           0 :                 Mnemonic = "v_cmpsx_lg_f32";   // "v_cmpsx_lg_f32_sdwa"
    8588           0 :                 return;
    8589             :               case 't':  // 1 string to match.
    8590           0 :                 if (memcmp(Mnemonic.data()+10, "_f32_sdwa", 9) != 0)
    8591             :                   break;
    8592           0 :                 Mnemonic = "v_cmpsx_lt_f32";   // "v_cmpsx_lt_f32_sdwa"
    8593           0 :                 return;
    8594             :               }
    8595             :               break;
    8596             :             }
    8597             :             break;
    8598             :           }
    8599             :           break;
    8600           0 :         case 'x':        // 14 strings to match.
    8601           0 :           if (Mnemonic[6] != '_')
    8602             :             break;
    8603             :           switch (Mnemonic[7]) {
    8604             :           default: break;
    8605           0 :           case 'n':      // 12 strings to match.
    8606             :             switch (Mnemonic[8]) {
    8607             :             default: break;
    8608             :             case 'e':    // 2 strings to match.
    8609           0 :               if (memcmp(Mnemonic.data()+9, "q_f", 3) != 0)
    8610             :                 break;
    8611             :               switch (Mnemonic[12]) {
    8612             :               default: break;
    8613             :               case '1':  // 1 string to match.
    8614           0 :                 if (memcmp(Mnemonic.data()+13, "6_sdwa", 6) != 0)
    8615             :                   break;
    8616           0 :                 Mnemonic = "v_cmpx_neq_f16";   // "v_cmpx_neq_f16_sdwa"
    8617           0 :                 return;
    8618             :               case '3':  // 1 string to match.
    8619           0 :                 if (memcmp(Mnemonic.data()+13, "2_sdwa", 6) != 0)
    8620             :                   break;
    8621           0 :                 Mnemonic = "v_cmpx_neq_f32";   // "v_cmpx_neq_f32_sdwa"
    8622           0 :                 return;
    8623             :               }
    8624             :               break;
    8625           0 :             case 'g':    // 4 strings to match.
    8626             :               switch (Mnemonic[9]) {
    8627             :               default: break;
    8628             :               case 'e':  // 2 strings to match.
    8629           0 :                 if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    8630             :                   break;
    8631             :                 switch (Mnemonic[12]) {
    8632             :                 default: break;
    8633             :                 case '1':        // 1 string to match.
    8634           0 :                   if (memcmp(Mnemonic.data()+13, "6_sdwa", 6) != 0)
    8635             :                     break;
    8636           0 :                   Mnemonic = "v_cmpx_nge_f16";         // "v_cmpx_nge_f16_sdwa"
    8637           0 :                   return;
    8638             :                 case '3':        // 1 string to match.
    8639           0 :                   if (memcmp(Mnemonic.data()+13, "2_sdwa", 6) != 0)
    8640             :                     break;
    8641           0 :                   Mnemonic = "v_cmpx_nge_f32";         // "v_cmpx_nge_f32_sdwa"
    8642           0 :                   return;
    8643             :                 }
    8644             :                 break;
    8645             :               case 't':  // 2 strings to match.
    8646           0 :                 if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    8647             :                   break;
    8648             :                 switch (Mnemonic[12]) {
    8649             :                 default: break;
    8650             :                 case '1':        // 1 string to match.
    8651           0 :                   if (memcmp(Mnemonic.data()+13, "6_sdwa", 6) != 0)
    8652             :                     break;
    8653           0 :                   Mnemonic = "v_cmpx_ngt_f16";         // "v_cmpx_ngt_f16_sdwa"
    8654           0 :                   return;
    8655             :                 case '3':        // 1 string to match.
    8656           0 :                   if (memcmp(Mnemonic.data()+13, "2_sdwa", 6) != 0)
    8657             :                     break;
    8658           0 :                   Mnemonic = "v_cmpx_ngt_f32";         // "v_cmpx_ngt_f32_sdwa"
    8659           0 :                   return;
    8660             :                 }
    8661             :                 break;
    8662             :               }
    8663             :               break;
    8664           0 :             case 'l':    // 6 strings to match.
    8665             :               switch (Mnemonic[9]) {
    8666             :               default: break;
    8667             :               case 'e':  // 2 strings to match.
    8668           0 :                 if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    8669             :                   break;
    8670             :                 switch (Mnemonic[12]) {
    8671             :                 default: break;
    8672             :                 case '1':        // 1 string to match.
    8673           0 :                   if (memcmp(Mnemonic.data()+13, "6_sdwa", 6) != 0)
    8674             :                     break;
    8675           0 :                   Mnemonic = "v_cmpx_nle_f16";         // "v_cmpx_nle_f16_sdwa"
    8676           0 :                   return;
    8677             :                 case '3':        // 1 string to match.
    8678           0 :                   if (memcmp(Mnemonic.data()+13, "2_sdwa", 6) != 0)
    8679             :                     break;
    8680           0 :                   Mnemonic = "v_cmpx_nle_f32";         // "v_cmpx_nle_f32_sdwa"
    8681           0 :                   return;
    8682             :                 }
    8683             :                 break;
    8684             :               case 'g':  // 2 strings to match.
    8685           0 :                 if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    8686             :                   break;
    8687             :                 switch (Mnemonic[12]) {
    8688             :                 default: break;
    8689             :                 case '1':        // 1 string to match.
    8690           0 :                   if (memcmp(Mnemonic.data()+13, "6_sdwa", 6) != 0)
    8691             :                     break;
    8692           0 :                   Mnemonic = "v_cmpx_nlg_f16";         // "v_cmpx_nlg_f16_sdwa"
    8693           0 :                   return;
    8694             :                 case '3':        // 1 string to match.
    8695           0 :                   if (memcmp(Mnemonic.data()+13, "2_sdwa", 6) != 0)
    8696             :                     break;
    8697           0 :                   Mnemonic = "v_cmpx_nlg_f32";         // "v_cmpx_nlg_f32_sdwa"
    8698           0 :                   return;
    8699             :                 }
    8700             :                 break;
    8701             :               case 't':  // 2 strings to match.
    8702           0 :                 if (memcmp(Mnemonic.data()+10, "_f", 2) != 0)
    8703             :                   break;
    8704             :                 switch (Mnemonic[12]) {
    8705             :                 default: break;
    8706             :                 case '1':        // 1 string to match.
    8707           0 :                   if (memcmp(Mnemonic.data()+13, "6_sdwa", 6) != 0)
    8708             :                     break;
    8709           0 :                   Mnemonic = "v_cmpx_nlt_f16";         // "v_cmpx_nlt_f16_sdwa"
    8710           0 :                   return;
    8711             :                 case '3':        // 1 string to match.
    8712           0 :                   if (memcmp(Mnemonic.data()+13, "2_sdwa", 6) != 0)
    8713             :                     break;
    8714           0 :                   Mnemonic = "v_cmpx_nlt_f32";         // "v_cmpx_nlt_f32_sdwa"
    8715           0 :                   return;
    8716             :                 }
    8717             :                 break;
    8718             :               }
    8719             :               break;
    8720             :             }
    8721             :             break;
    8722             :           case 't':      // 2 strings to match.
    8723           0 :             if (memcmp(Mnemonic.data()+8, "ru_f", 4) != 0)
    8724             :               break;
    8725             :             switch (Mnemonic[12]) {
    8726             :             default: break;
    8727             :             case '1':    // 1 string to match.
    8728           0 :               if (memcmp(Mnemonic.data()+13, "6_sdwa", 6) != 0)
    8729             :                 break;
    8730           0 :               Mnemonic = "v_cmpx_tru_f16";     // "v_cmpx_tru_f16_sdwa"
    8731           0 :               return;
    8732             :             case '3':    // 1 string to match.
    8733           0 :               if (memcmp(Mnemonic.data()+13, "2_sdwa", 6) != 0)
    8734             :                 break;
    8735           0 :               Mnemonic = "v_cmpx_tru_f32";     // "v_cmpx_tru_f32_sdwa"
    8736           0 :               return;
    8737             :             }
    8738             :             break;
    8739             :           }
    8740             :           break;
    8741             :         }
    8742             :         break;
    8743             :       case 20:   // 14 strings to match.
    8744         133 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    8745             :           break;
    8746             :         switch (Mnemonic[2]) {
    8747             :         default: break;
    8748             :         case 'c':        // 9 strings to match.
    8749          15 :           if (memcmp(Mnemonic.data()+3, "mp", 2) != 0)
    8750             :             break;
    8751             :           switch (Mnemonic[5]) {
    8752             :           default: break;
    8753             :           case '_':      // 2 strings to match.
    8754           0 :             if (memcmp(Mnemonic.data()+6, "class_f", 7) != 0)
    8755             :               break;
    8756             :             switch (Mnemonic[13]) {
    8757             :             default: break;
    8758             :             case '1':    // 1 string to match.
    8759           0 :               if (memcmp(Mnemonic.data()+14, "6_sdwa", 6) != 0)
    8760             :                 break;
    8761           0 :               Mnemonic = "v_cmp_class_f16";    // "v_cmp_class_f16_sdwa"
    8762           0 :               return;
    8763             :             case '3':    // 1 string to match.
    8764           0 :               if (memcmp(Mnemonic.data()+14, "2_sdwa", 6) != 0)
    8765             :                 break;
    8766           0 :               Mnemonic = "v_cmp_class_f32";    // "v_cmp_class_f32_sdwa"
    8767           0 :               return;
    8768             :             }
    8769             :             break;
    8770             :           case 's':      // 7 strings to match.
    8771           0 :             if (memcmp(Mnemonic.data()+6, "x_", 2) != 0)
    8772             :               break;
    8773             :             switch (Mnemonic[8]) {
    8774             :             default: break;
    8775           0 :             case 'n':    // 6 strings to match.
    8776             :               switch (Mnemonic[9]) {
    8777             :               default: break;
    8778             :               case 'e':  // 1 string to match.
    8779           0 :                 if (memcmp(Mnemonic.data()+10, "q_f32_sdwa", 10) != 0)
    8780             :                   break;
    8781           0 :                 Mnemonic = "v_cmpsx_neq_f32";  // "v_cmpsx_neq_f32_sdwa"
    8782           0 :                 return;
    8783           0 :               case 'g':  // 2 strings to match.
    8784             :                 switch (Mnemonic[10]) {
    8785             :                 default: break;
    8786             :                 case 'e':        // 1 string to match.
    8787           0 :                   if (memcmp(Mnemonic.data()+11, "_f32_sdwa", 9) != 0)
    8788             :                     break;
    8789           0 :                   Mnemonic = "v_cmpsx_nge_f32";        // "v_cmpsx_nge_f32_sdwa"
    8790           0 :                   return;
    8791             :                 case 't':        // 1 string to match.
    8792           0 :                   if (memcmp(Mnemonic.data()+11, "_f32_sdwa", 9) != 0)
    8793             :                     break;
    8794           0 :                   Mnemonic = "v_cmpsx_ngt_f32";        // "v_cmpsx_ngt_f32_sdwa"
    8795           0 :                   return;
    8796             :                 }
    8797             :                 break;
    8798           0 :               case 'l':  // 3 strings to match.
    8799             :                 switch (Mnemonic[10]) {
    8800             :                 default: break;
    8801             :                 case 'e':        // 1 string to match.
    8802           0 :                   if (memcmp(Mnemonic.data()+11, "_f32_sdwa", 9) != 0)
    8803             :                     break;
    8804           0 :                   Mnemonic = "v_cmpsx_nle_f32";        // "v_cmpsx_nle_f32_sdwa"
    8805           0 :                   return;
    8806             :                 case 'g':        // 1 string to match.
    8807           0 :                   if (memcmp(Mnemonic.data()+11, "_f32_sdwa", 9) != 0)
    8808             :                     break;
    8809           0 :                   Mnemonic = "v_cmpsx_nlg_f32";        // "v_cmpsx_nlg_f32_sdwa"
    8810           0 :                   return;
    8811             :                 case 't':        // 1 string to match.
    8812           0 :                   if (memcmp(Mnemonic.data()+11, "_f32_sdwa", 9) != 0)
    8813             :                     break;
    8814           0 :                   Mnemonic = "v_cmpsx_nlt_f32";        // "v_cmpsx_nlt_f32_sdwa"
    8815           0 :                   return;
    8816             :                 }
    8817             :                 break;
    8818             :               }
    8819             :               break;
    8820             :             case 't':    // 1 string to match.
    8821           0 :               if (memcmp(Mnemonic.data()+9, "ru_f32_sdwa", 11) != 0)
    8822             :                 break;
    8823           0 :               Mnemonic = "v_cmpsx_tru_f32";    // "v_cmpsx_tru_f32_sdwa"
    8824           0 :               return;
    8825             :             }
    8826             :             break;
    8827             :           }
    8828             :           break;
    8829             :         case 'l':        // 1 string to match.
    8830           0 :           if (memcmp(Mnemonic.data()+3, "og_clamp_f32_sdwa", 17) != 0)
    8831             :             break;
    8832           0 :           Mnemonic = "v_log_clamp_f32";        // "v_log_clamp_f32_sdwa"
    8833           0 :           return;
    8834           0 :         case 'r':        // 3 strings to match.
    8835             :           switch (Mnemonic[3]) {
    8836             :           default: break;
    8837             :           case 'c':      // 2 strings to match.
    8838           0 :             if (memcmp(Mnemonic.data()+4, "p_", 2) != 0)
    8839             :               break;
    8840             :             switch (Mnemonic[6]) {
    8841             :             default: break;
    8842             :             case 'c':    // 1 string to match.
    8843           0 :               if (memcmp(Mnemonic.data()+7, "lamp_f32_sdwa", 13) != 0)
    8844             :                 break;
    8845           0 :               Mnemonic = "v_rcp_clamp_f32";    // "v_rcp_clamp_f32_sdwa"
    8846           0 :               return;
    8847             :             case 'i':    // 1 string to match.
    8848           0 :               if (memcmp(Mnemonic.data()+7, "flag_f32_sdwa", 13) != 0)
    8849             :                 break;
    8850           0 :               Mnemonic = "v_rcp_iflag_f32";    // "v_rcp_iflag_f32_sdwa"
    8851           0 :               return;
    8852             :             }
    8853             :             break;
    8854             :           case 's':      // 1 string to match.
    8855           0 :             if (memcmp(Mnemonic.data()+4, "q_clamp_f32_sdwa", 16) != 0)
    8856             :               break;
    8857           0 :             Mnemonic = "v_rsq_clamp_f32";      // "v_rsq_clamp_f32_sdwa"
    8858           0 :             return;
    8859             :           }
    8860             :           break;
    8861             :         case 's':        // 1 string to match.
    8862           0 :           if (memcmp(Mnemonic.data()+3, "at_pk_u8_i16_sdwa", 17) != 0)
    8863             :             break;
    8864           0 :           Mnemonic = "v_sat_pk_u8_i16";        // "v_sat_pk_u8_i16_sdwa"
    8865           0 :           return;
    8866             :         }
    8867             :         break;
    8868             :       case 21:   // 19 strings to match.
    8869          37 :         if (memcmp(Mnemonic.data()+0, "v_", 2) != 0)
    8870             :           break;
    8871             :         switch (Mnemonic[2]) {
    8872             :         default: break;
    8873           0 :         case 'c':        // 7 strings to match.
    8874             :           switch (Mnemonic[3]) {
    8875             :           default: break;
    8876             :           case 'm':      // 2 strings to match.
    8877           0 :             if (memcmp(Mnemonic.data()+4, "px_class_f", 10) != 0)
    8878             :               break;
    8879             :             switch (Mnemonic[14]) {
    8880             :             default: break;
    8881             :             case '1':    // 1 string to match.
    8882           0 :               if (memcmp(Mnemonic.data()+15, "6_sdwa", 6) != 0)
    8883             :                 break;
    8884           0 :               Mnemonic = "v_cmpx_class_f16";   // "v_cmpx_class_f16_sdwa"
    8885           0 :               return;
    8886             :             case '3':    // 1 string to match.
    8887           0 :               if (memcmp(Mnemonic.data()+15, "2_sdwa", 6) != 0)
    8888             :                 break;
    8889           0 :               Mnemonic = "v_cmpx_class_f32";   // "v_cmpx_class_f32_sdwa"
    8890           0 :               return;
    8891             :             }
    8892             :             break;
    8893             :           case 'v':      // 5 strings to match.
    8894           0 :             if (memcmp(Mnemonic.data()+4, "t_", 2) != 0)
    8895             :               break;
    8896             :             switch (Mnemonic[6]) {
    8897             :             default: break;
    8898             :             case 'f':    // 4 strings to match.
    8899           0 :               if (memcmp(Mnemonic.data()+7, "32_ubyte", 8) != 0)
    8900             :                 break;
    8901             :               switch (Mnemonic[15]) {
    8902             :               default: break;
    8903             :               case '0':  // 1 string to match.
    8904           0 :                 if (memcmp(Mnemonic.data()+16, "_sdwa", 5) != 0)
    8905             :                   break;
    8906           0 :                 Mnemonic = "v_cvt_f32_ubyte0";         // "v_cvt_f32_ubyte0_sdwa"
    8907           0 :                 return;
    8908             :               case '1':  // 1 string to match.
    8909           0 :                 if (memcmp(Mnemonic.data()+16, "_sdwa", 5) != 0)
    8910             :                   break;
    8911           0 :                 Mnemonic = "v_cvt_f32_ubyte1";         // "v_cvt_f32_ubyte1_sdwa"
    8912           0 :                 return;
    8913             :               case '2':  // 1 string to match.
    8914           0 :                 if (memcmp(Mnemonic.data()+16, "_sdwa", 5) != 0)
    8915             :                   break;
    8916           0 :                 Mnemonic = "v_cvt_f32_ubyte2";         // "v_cvt_f32_ubyte2_sdwa"
    8917           0 :                 return;
    8918             :               case '3':  // 1 string to match.
    8919           0 :                 if (memcmp(Mnemonic.data()+16, "_sdwa", 5) != 0)
    8920             :                   break;
    8921           0 :                 Mnemonic = "v_cvt_f32_ubyte3";         // "v_cvt_f32_ubyte3_sdwa"
    8922           0 :                 return;
    8923             :               }
    8924             :               break;
    8925             :             case 'o':    // 1 string to match.
    8926           0 :               if (memcmp(Mnemonic.data()+7, "ff_f32_i4_sdwa", 14) != 0)
    8927             :                 break;
    8928           0 :               Mnemonic = "v_cvt_off_f32_i4";   // "v_cvt_off_f32_i4_sdwa"
    8929           0 :               return;
    8930             :             }
    8931             :             break;
    8932             :           }
    8933             :           break;
    8934             :         case 'e':        // 1 string to match.
    8935           0 :           if (memcmp(Mnemonic.data()+3, "xp_legacy_f32_sdwa", 18) != 0)
    8936             :             break;
    8937           0 :           Mnemonic = "v_exp_legacy_f32";       // "v_exp_legacy_f32_sdwa"
    8938           0 :           return;
    8939             :         case 'f':        // 2 strings to match.
    8940           0 :           if (memcmp(Mnemonic.data()+3, "rexp_mant_f", 11) != 0)
    8941             :             break;
    8942             :           switch (Mnemonic[14]) {
    8943             :           default: break;
    8944             :           case '1':      // 1 string to match.
    8945           0 :             if (memcmp(Mnemonic.data()+15, "6_sdwa", 6) != 0)
    8946             :               break;
    8947           0 :             Mnemonic = "v_frexp_mant_f16";     // "v_frexp_mant_f16_sdwa"
    8948           0 :             return;
    8949             :           case '3':      // 1 string to match.
    8950           0 :             if (memcmp(Mnemonic.data()+15, "2_sdwa", 6) != 0)
    8951             :               break;
    8952           0 :             Mnemonic = "v_frexp_mant_f32";     // "v_frexp_mant_f32_sdwa"
    8953           0 :             return;
    8954             :           }
    8955             :           break;
    8956             :         case 'l':        // 1 string to match.
    8957           0 :           if (memcmp(Mnemonic.data()+3, "og_legacy_f32_sdwa", 18) != 0)
    8958             :             break;
    8959           0 :           Mnemonic = "v_log_legacy_f32";       // "v_log_legacy_f32_sdwa"
    8960           0 :           return;
    8961           0 :         case 'm':        // 6 strings to match.
    8962             :           switch (Mnemonic[3]) {
    8963             :           default: break;
    8964           0 :           case 'a':      // 2 strings to match.
    8965             :             switch (Mnemonic[4]) {
    8966             :             default: break;
    8967             :             case 'c':    // 1 string to match.
    8968           0 :               if (memcmp(Mnemonic.data()+5, "_legacy_f32_sdwa", 16) != 0)
    8969             :                 break;
    8970           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_mac_legacy_f32_sdwa"
    8971           0 :                 Mnemonic = "v_mac_legacy_f32";
    8972             :               return;
    8973             :             case 'x':    // 1 string to match.
    8974           0 :               if (memcmp(Mnemonic.data()+5, "_legacy_f32_sdwa", 16) != 0)
    8975             :                 break;
    8976           0 :               if ((Features & Feature_isSICI) == Feature_isSICI)     // "v_max_legacy_f32_sdwa"
    8977           0 :                 Mnemonic = "v_max_legacy_f32";
    8978             :               return;
    8979             :             }
    8980             :             break;
    8981             :           case 'i':      // 1 string to match.
    8982           0 :             if (memcmp(Mnemonic.data()+4, "n_legacy_f32_sdwa", 17) != 0)
    8983             :               break;
    8984           0 :             if ((Features & Feature_isSICI) == Feature_isSICI)       // "v_min_legacy_f32_sdwa"
    8985           0 :               Mnemonic = "v_min_legacy_f32";
    8986             :             return;
    8987             :           case 'u':      // 3 strings to match.
    8988           0 :             if (memcmp(Mnemonic.data()+4, "l_", 2) != 0)
    8989             :               break;
    8990             :             switch (Mnemonic[6]) {
    8991             :             default: break;
    8992             :             case 'h':    // 2 strings to match.
    8993           0 :               if (memcmp(Mnemonic.data()+7, "i_", 2) != 0)
    8994             :                 break;
    8995             :               switch (Mnemonic[9]) {
    8996             :               default: break;
    8997             :               case 'i':  // 1 string to match.
    8998           0 :                 if (memcmp(Mnemonic.data()+10, "32_i24_sdwa", 11) != 0)
    8999             :                   break;
    9000           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mul_hi_i32_i24_sdwa"
    9001           0 :                   Mnemonic = "v_mul_hi_i32_i24";
    9002             :                 return;
    9003             :               case 'u':  // 1 string to match.
    9004           0 :                 if (memcmp(Mnemonic.data()+10, "32_u24_sdwa", 11) != 0)
    9005             :                   break;
    9006           0 :                 if ((Features & Feature_isGCN) == Feature_isGCN)     // "v_mul_hi_u32_u24_sdwa"
    9007           0 :                   Mnemonic = "v_mul_hi_u32_u24";
    9008             :                 return;
    9009             :               }
    9010             :               break;
    9011             :             case 'l':    // 1 string to match.
    9012           0 :               if (memcmp(Mnemonic.data()+7, "egacy_f32_sdwa", 14) != 0)
    9013             :                 break;
    9014           0 :               if ((Features & Feature_isGCN) == Feature_isGCN)       // "v_mul_legacy_f32_sdwa"
    9015           0 :                 Mnemonic = "v_mul_legacy_f32";
    9016             :               return;
    9017             :             }
    9018             :             break;
    9019             :           }
    9020             :           break;
    9021           0 :         case 'r':        // 2 strings to match.
    9022             :           switch (Mnemonic[3]) {
    9023             :           default: break;
    9024             :           case 'c':      // 1 string to match.
    9025           0 :             if (memcmp(Mnemonic.data()+4, "p_legacy_f32_sdwa", 17) != 0)
    9026             :               break;
    9027           0 :             Mnemonic = "v_rcp_legacy_f32";     // "v_rcp_legacy_f32_sdwa"
    9028           0 :             return;
    9029             :           case 's':      // 1 string to match.
    9030           0 :             if (memcmp(Mnemonic.data()+4, "q_legacy_f32_sdwa", 17) != 0)
    9031             :               break;
    9032           0 :             Mnemonic = "v_rsq_legacy_f32";     // "v_rsq_legacy_f32_sdwa"
    9033           0 :             return;
    9034             :           }
    9035             :           break;
    9036             :         }
    9037             :         break;
    9038             :       case 22:   // 2 strings to match.
    9039         141 :         if (memcmp(Mnemonic.data()+0, "v_cvt_", 6) != 0)
    9040             :           break;
    9041             :         switch (Mnemonic[6]) {
    9042             :         default: break;
    9043             :         case 'f':        // 1 string to match.
    9044           0 :           if (memcmp(Mnemonic.data()+7, "lr_i32_f32_sdwa", 15) != 0)
    9045             :             break;
    9046           0 :           Mnemonic = "v_cvt_flr_i32_f32";      // "v_cvt_flr_i32_f32_sdwa"
    9047           0 :           return;
    9048             :         case 'r':        // 1 string to match.
    9049           0 :           if (memcmp(Mnemonic.data()+7, "pi_i32_f32_sdwa", 15) != 0)
    9050             :             break;
    9051           0 :           Mnemonic = "v_cvt_rpi_i32_f32";      // "v_cvt_rpi_i32_f32_sdwa"
    9052           0 :           return;
    9053             :         }
    9054             :         break;
    9055             :       case 23:   // 2 strings to match.
    9056          80 :         if (memcmp(Mnemonic.data()+0, "v_cvt_norm_", 11) != 0)
    9057             :           break;
    9058             :         switch (Mnemonic[11]) {
    9059             :         default: break;
    9060             :         case 'i':        // 1 string to match.
    9061           0 :           if (memcmp(Mnemonic.data()+12, "16_f16_sdwa", 11) != 0)
    9062             :             break;
    9063           0 :           Mnemonic = "v_cvt_norm_i16_f16";     // "v_cvt_norm_i16_f16_sdwa"
    9064           0 :           return;
    9065             :         case 'u':        // 1 string to match.
    9066           0 :           if (memcmp(Mnemonic.data()+12, "16_f16_sdwa", 11) != 0)
    9067             :             break;
    9068           0 :           Mnemonic = "v_cvt_norm_u16_f16";     // "v_cvt_norm_u16_f16_sdwa"
    9069           0 :           return;
    9070             :         }
    9071             :         break;
    9072             :       case 24:   // 2 strings to match.
    9073          15 :         if (memcmp(Mnemonic.data()+0, "v_frexp_exp_i", 13) != 0)
    9074             :           break;
    9075             :         switch (Mnemonic[13]) {
    9076             :         default: break;
    9077             :         case '1':        // 1 string to match.
    9078           0 :           if (memcmp(Mnemonic.data()+14, "6_f16_sdwa", 10) != 0)
    9079             :             break;
    9080           0 :           Mnemonic = "v_frexp_exp_i16_f16";    // "v_frexp_exp_i16_f16_sdwa"
    9081           0 :           return;
    9082             :         case '3':        // 1 string to match.
    9083           0 :           if (memcmp(Mnemonic.data()+14, "2_f32_sdwa", 10) != 0)
    9084             :             break;
    9085           0 :           Mnemonic = "v_frexp_exp_i32_f32";    // "v_frexp_exp_i32_f32_sdwa"
    9086           0 :           return;
    9087             :         }
    9088             :         break;
    9089             :       case 31:   // 1 string to match.
    9090           0 :         if (memcmp(Mnemonic.data()+0, "v_screen_partition_4se_b32_sdwa", 31) != 0)
    9091             :           break;
    9092           0 :         Mnemonic = "v_screen_partition_4se_b32";       // "v_screen_partition_4se_b32_sdwa"
    9093           0 :         return;
    9094             :       }
    9095             :     break;
    9096             :     case 3:
    9097             :     break;
    9098             :     case 4:
    9099             :     break;
    9100             :   }
    9101             : }
    9102             : 
    9103             : enum {
    9104             :   Tie0_1_1,
    9105             :   Tie1_2_2,
    9106             : };
    9107             : 
    9108             : static const uint8_t TiedAsmOperandTable[][3] = {
    9109             :   /* Tie0_1_1 */ { 0, 1, 1 },
    9110             :   /* Tie1_2_2 */ { 1, 2, 2 },
    9111             : };
    9112             : 
    9113             : namespace {
    9114             : enum OperatorConversionKind {
    9115             :   CVT_Done,
    9116             :   CVT_Reg,
    9117             :   CVT_Tied,
    9118             :   CVT_cvtMubufAtomic,
    9119             :   CVT_cvtMubufAtomicReturn,
    9120             :   CVT_cvtMubufLds,
    9121             :   CVT_cvtMubuf,
    9122             :   CVT_cvtDS,
    9123             :   CVT_cvtDSGds,
    9124             :   CVT_cvtDSOffset01,
    9125             :   CVT_cvtExp,
    9126             :   CVT_95_Reg,
    9127             :   CVT_95_addImmOperands_95_defaultOffsetU12,
    9128             :   CVT_95_addImmOperands_95_defaultSLC,
    9129             :   CVT_95_addImmOperands_95_defaultGLC,
    9130             :   CVT_imm_95_0,
    9131             :   CVT_95_addImmOperands_95_defaultOffsetS13,
    9132             :   CVT_cvtMIMGAtomic,
    9133             :   CVT_cvtMIMG,
    9134             :   CVT_95_addRegOrImmOperands,
    9135             :   CVT_95_addImmOperands,
    9136             :   CVT_95_addImmOperands_95_defaultSMRDOffset20,
    9137             :   CVT_95_addSoppBrTargetOperands,
    9138             :   CVT_95_addImmOperands_95_defaultSMRDOffset8,
    9139             :   CVT_95_addImmOperands_95_defaultSMRDLiteralOffset,
    9140             :   CVT_cvtMtbuf,
    9141             :   CVT_95_addImmOperands_95_defaultRowMask,
    9142             :   CVT_95_addImmOperands_95_defaultBankMask,
    9143             :   CVT_95_addImmOperands_95_defaultBoundCtrl,
    9144             :   CVT_cvtSdwaVOP2b,
    9145             :   CVT_cvtVOP3,
    9146             :   CVT_cvtDPP,
    9147             :   CVT_cvtSdwaVOP2,
    9148             :   CVT_cvtVOP3OpSel,
    9149             :   CVT_cvtSdwaVOP1,
    9150             :   CVT_cvtSdwaVOPC,
    9151             :   CVT_cvtVOP3P,
    9152             :   CVT_cvtVOP3Interp,
    9153             :   CVT_95_addKImmFP16Operands,
    9154             :   CVT_95_addKImmFP32Operands,
    9155             :   CVT_NUM_CONVERTERS
    9156             : };
    9157             : 
    9158             : enum InstructionConversionKind {
    9159             :   ConvertCustom_cvtMubufAtomic,
    9160             :   ConvertCustom_cvtMubufAtomicReturn,
    9161             :   ConvertCustom_cvtMubufLds,
    9162             :   ConvertCustom_cvtMubuf,
    9163             :   Convert_NoOperands,
    9164             :   ConvertCustom_cvtDS,
    9165             :   ConvertCustom_cvtDSGds,
    9166             :   ConvertCustom_cvtDSOffset01,
    9167             :   ConvertCustom_cvtExp,
    9168             :   Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3,
    9169             :   Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5,
    9170             :   Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4,
    9171             :   Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0,
    9172             :   Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4,
    9173             :   Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4,
    9174             :   Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6,
    9175             :   Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6,
    9176             :   Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5,
    9177             :   Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5,
    9178             :   Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0,
    9179             :   Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0,
    9180             :   ConvertCustom_cvtMIMGAtomic,
    9181             :   ConvertCustom_cvtMIMG,
    9182             :   Convert__Reg1_0__SSrcB321_1,
    9183             :   Convert__Reg1_0__SSrcB321_1__SSrcB321_2,
    9184             :   Convert__Reg1_0__Tie0_1_1__S16Imm1_1,
    9185             :   Convert__Reg1_0__SSrcB641_1__SSrcB641_2,
    9186             :   Convert__Reg1_0__SSrcB641_1,
    9187             :   Convert__Reg1_0__SSrcB641_1__SSrcB321_2,
    9188             :   Convert__Imm1_0__Reg1_1__Reg1_2,
    9189             :   Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2,
    9190             :   Convert__Reg1_0__Reg1_1__Reg1_2,
    9191             :   Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2,
    9192             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2,
    9193             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2,
    9194             :   Convert__SSrcB321_0__SSrcB321_1,
    9195             :   Convert__SSrcB641_0__SSrcB321_1,
    9196             :   Convert__SoppBrTarget1_0,
    9197             :   Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3,
    9198             :   Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3,
    9199             :   Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3,
    9200             :   Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3,
    9201             :   Convert__Reg1_0__S16Imm1_1,
    9202             :   Convert__SCSrcB641_0__SCSrcB641_1,
    9203             :   Convert__Reg1_0,
    9204             :   Convert__SSrcB641_0__SSrcB641_1,
    9205             :   Convert__Reg1_0__U16Imm1_1,
    9206             :   Convert__Reg1_0__Reg1_1,
    9207             :   Convert__Reg1_0__ImmSMRDOffset201_1,
    9208             :   Convert__Imm1_0,
    9209             :   Convert__Reg1_0__ImmHwreg1_1,
    9210             :   Convert__SendMsg1_0,
    9211             :   Convert__SSrcB321_0,
    9212             :   Convert__GPRIdxMode1_0,
    9213             :   Convert__SSrcB321_0__GPRIdxMode1_1,
    9214             :   Convert__Reg1_1__ImmHwreg1_0,
    9215             :   Convert__Imm1_1__ImmHwreg1_0,
    9216             :   Convert__SWaitCnt1_0,
    9217             :   Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5,
    9218             :   Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5,
    9219             :   Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5,
    9220             :   ConvertCustom_cvtMtbuf,
    9221             :   Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3,
    9222             :   Convert__Reg1_0__VSrcB321_2__Reg1_3,
    9223             :   Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3,
    9224             :   Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7,
    9225             :   ConvertCustom_cvtSdwaVOP2b,
    9226             :   Convert__Reg1_0__VSrcF161_1__Reg1_2,
    9227             :   ConvertCustom_cvtVOP3,
    9228             :   ConvertCustom_cvtDPP,
    9229             :   ConvertCustom_cvtSdwaVOP2,
    9230             :   Convert__Reg1_0__VSrcF321_1__Reg1_2,
    9231             :   ConvertCustom_cvtVOP3OpSel,
    9232             :   Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2,
    9233             :   Convert__Reg1_0__VSrcB161_1__Reg1_2,
    9234             :   Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2,
    9235             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6,
    9236             :   Convert__Reg1_0__VSrcB321_1__Reg1_2,
    9237             :   Convert__Reg1_0__VCSrcB321_2__Reg1_3,
    9238             :   Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4,
    9239             :   Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8,
    9240             :   Convert__Reg1_0__VCSrcB641_1__VCSrcB321_2,
    9241             :   Convert__Reg1_0__VCSrcB321_1__VCSrcB641_2,
    9242             :   Convert__Reg1_0__VSrcB321_1,
    9243             :   Convert__Reg1_0__VCSrcB321_1,
    9244             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5,
    9245             :   ConvertCustom_cvtSdwaVOP1,
    9246             :   Convert__Reg1_0__VSrcF161_1,
    9247             :   Convert__Reg1_0__VSrcF321_1,
    9248             :   Convert__Reg1_0__VSrcF641_1,
    9249             :   Convert__VSrcF161_1__Reg1_2,
    9250             :   ConvertCustom_cvtSdwaVOPC,
    9251             :   Convert__VSrcF321_1__Reg1_2,
    9252             :   Convert__VSrcF641_1__Reg1_2,
    9253             :   Convert__VSrcB161_1__Reg1_2,
    9254             :   Convert__VSrcB321_1__Reg1_2,
    9255             :   Convert__VSrcB641_1__Reg1_2,
    9256             :   Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2,
    9257             :   Convert__Reg1_0__VCSrcB321_1__Reg1_2,
    9258             :   Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__Reg1_3,
    9259             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7,
    9260             :   Convert__Reg1_0__VSrcB161_1,
    9261             :   Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0,
    9262             :   Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0,
    9263             :   Convert__Reg1_0__Reg1_1__VCSrcF321_2__VCSrcF321_3__VCSrcF321_4,
    9264             :   Convert__Reg1_0__Reg1_1__VCSrcF641_2__VCSrcF641_3__VCSrcF641_4,
    9265             :   ConvertCustom_cvtVOP3P,
    9266             :   Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1,
    9267             :   Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3,
    9268             :   ConvertCustom_cvtVOP3Interp,
    9269             :   Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3,
    9270             :   Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3,
    9271             :   Convert__Reg1_0__VSrcF161_1__Reg1_2__Tie0_1_1,
    9272             :   Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP161_3,
    9273             :   Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3,
    9274             :   Convert__Reg1_0__VCSrcF321_1__KImmFP161_2__Reg1_3,
    9275             :   Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3,
    9276             :   Convert__ImmDPPCtrl1_0__ImmRowMask1_1__ImmBankMask1_2__ImmBoundCtrl1_3,
    9277             :   Convert__Reg1_0__Reg1_1__SCSrcB321_2,
    9278             :   Convert__Reg1_0__Reg1_1__Tie1_2_2__Tie0_1_1,
    9279             :   Convert__Reg1_0__SSrcB321_1__SCSrcB321_2__Tie0_1_1,
    9280             :   Convert__Reg1_0__SCSrcB321_1__SCSrcB321_2__Tie0_1_1,
    9281             :   CVT_NUM_SIGNATURES
    9282             : };
    9283             : 
    9284             : } // end anonymous namespace
    9285             : 
    9286             : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
    9287             :   // ConvertCustom_cvtMubufAtomic
    9288             :   { CVT_cvtMubufAtomic, 0, CVT_Done },
    9289             :   // ConvertCustom_cvtMubufAtomicReturn
    9290             :   { CVT_cvtMubufAtomicReturn, 0, CVT_Done },
    9291             :   // ConvertCustom_cvtMubufLds
    9292             :   { CVT_cvtMubufLds, 0, CVT_Done },
    9293             :   // ConvertCustom_cvtMubuf
    9294             :   { CVT_cvtMubuf, 0, CVT_Done },
    9295             :   // Convert_NoOperands
    9296             :   { CVT_Done },
    9297             :   // ConvertCustom_cvtDS
    9298             :   { CVT_cvtDS, 0, CVT_Done },
    9299             :   // ConvertCustom_cvtDSGds
    9300             :   { CVT_cvtDSGds, 0, CVT_Done },
    9301             :   // ConvertCustom_cvtDSOffset01
    9302             :   { CVT_cvtDSOffset01, 0, CVT_Done },
    9303             :   // ConvertCustom_cvtExp
    9304             :   { CVT_cvtExp, 0, CVT_Done },
    9305             :   // Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3
    9306             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultOffsetU12, 3, CVT_95_addImmOperands_95_defaultSLC, 4, CVT_Done },
    9307             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5
    9308             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultOffsetU12, 4, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_Done },
    9309             :   // Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4
    9310             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultOffsetU12, 3, CVT_95_addImmOperands_95_defaultGLC, 4, CVT_95_addImmOperands_95_defaultSLC, 5, CVT_Done },
    9311             :   // Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0
    9312             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultOffsetU12, 3, CVT_95_addImmOperands_95_defaultGLC, 4, CVT_95_addImmOperands_95_defaultSLC, 5, CVT_imm_95_0, 0, CVT_Done },
    9313             :   // Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4
    9314             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultSLC, 5, CVT_Done },
    9315             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4
    9316             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultSLC, 5, CVT_Done },
    9317             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6
    9318             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultOffsetS13, 5, CVT_95_addImmOperands_95_defaultSLC, 7, CVT_Done },
    9319             :   // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6
    9320             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands_95_defaultOffsetS13, 5, CVT_95_addImmOperands_95_defaultSLC, 7, CVT_Done },
    9321             :   // Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5
    9322             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultGLC, 5, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_Done },
    9323             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5
    9324             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultGLC, 5, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_Done },
    9325             :   // Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0
    9326             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultGLC, 5, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_imm_95_0, 0, CVT_Done },
    9327             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0
    9328             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultGLC, 5, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_imm_95_0, 0, CVT_Done },
    9329             :   // ConvertCustom_cvtMIMGAtomic
    9330             :   { CVT_cvtMIMGAtomic, 0, CVT_Done },
    9331             :   // ConvertCustom_cvtMIMG
    9332             :   { CVT_cvtMIMG, 0, CVT_Done },
    9333             :   // Convert__Reg1_0__SSrcB321_1
    9334             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9335             :   // Convert__Reg1_0__SSrcB321_1__SSrcB321_2
    9336             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9337             :   // Convert__Reg1_0__Tie0_1_1__S16Imm1_1
    9338             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
    9339             :   // Convert__Reg1_0__SSrcB641_1__SSrcB641_2
    9340             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9341             :   // Convert__Reg1_0__SSrcB641_1
    9342             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9343             :   // Convert__Reg1_0__SSrcB641_1__SSrcB321_2
    9344             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9345             :   // Convert__Imm1_0__Reg1_1__Reg1_2
    9346             :   { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    9347             :   // Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2
    9348             :   { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultSMRDOffset20, 3, CVT_Done },
    9349             :   // Convert__Reg1_0__Reg1_1__Reg1_2
    9350             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    9351             :   // Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2
    9352             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultSMRDOffset20, 3, CVT_Done },
    9353             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2
    9354             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
    9355             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2
    9356             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultSMRDOffset20, 3, CVT_Done },
    9357             :   // Convert__SSrcB321_0__SSrcB321_1
    9358             :   { CVT_95_addRegOrImmOperands, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9359             :   // Convert__SSrcB641_0__SSrcB321_1
    9360             :   { CVT_95_addRegOrImmOperands, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9361             :   // Convert__SoppBrTarget1_0
    9362             :   { CVT_95_addSoppBrTargetOperands, 1, CVT_Done },
    9363             :   // Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3
    9364             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultGLC, 4, CVT_Done },
    9365             :   // Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3
    9366             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultSMRDOffset8, 3, CVT_95_addImmOperands_95_defaultGLC, 4, CVT_Done },
    9367             :   // Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3
    9368             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultSMRDOffset20, 3, CVT_95_addImmOperands_95_defaultGLC, 4, CVT_Done },
    9369             :   // Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3
    9370             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands_95_defaultSMRDLiteralOffset, 3, CVT_95_addImmOperands_95_defaultGLC, 4, CVT_Done },
    9371             :   // Convert__Reg1_0__S16Imm1_1
    9372             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
    9373             :   // Convert__SCSrcB641_0__SCSrcB641_1
    9374             :   { CVT_95_addRegOrImmOperands, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9375             :   // Convert__Reg1_0
    9376             :   { CVT_95_Reg, 1, CVT_Done },
    9377             :   // Convert__SSrcB641_0__SSrcB641_1
    9378             :   { CVT_95_addRegOrImmOperands, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9379             :   // Convert__Reg1_0__U16Imm1_1
    9380             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
    9381             :   // Convert__Reg1_0__Reg1_1
    9382             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
    9383             :   // Convert__Reg1_0__ImmSMRDOffset201_1
    9384             :   { CVT_95_Reg, 1, CVT_95_addImmOperands_95_defaultSMRDOffset20, 2, CVT_Done },
    9385             :   // Convert__Imm1_0
    9386             :   { CVT_95_addImmOperands, 1, CVT_Done },
    9387             :   // Convert__Reg1_0__ImmHwreg1_1
    9388             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
    9389             :   // Convert__SendMsg1_0
    9390             :   { CVT_95_addImmOperands, 1, CVT_Done },
    9391             :   // Convert__SSrcB321_0
    9392             :   { CVT_95_addRegOrImmOperands, 1, CVT_Done },
    9393             :   // Convert__GPRIdxMode1_0
    9394             :   { CVT_95_addImmOperands, 1, CVT_Done },
    9395             :   // Convert__SSrcB321_0__GPRIdxMode1_1
    9396             :   { CVT_95_addRegOrImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
    9397             :   // Convert__Reg1_1__ImmHwreg1_0
    9398             :   { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
    9399             :   // Convert__Imm1_1__ImmHwreg1_0
    9400             :   { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
    9401             :   // Convert__SWaitCnt1_0
    9402             :   { CVT_95_addImmOperands, 1, CVT_Done },
    9403             :   // Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5
    9404             :   { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultGLC, 5, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_Done },
    9405             :   // Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5
    9406             :   { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultGLC, 5, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_Done },
    9407             :   // Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5
    9408             :   { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands_95_defaultOffsetS13, 4, CVT_95_addImmOperands_95_defaultGLC, 5, CVT_95_addImmOperands_95_defaultSLC, 6, CVT_Done },
    9409             :   // ConvertCustom_cvtMtbuf
    9410             :   { CVT_cvtMtbuf, 0, CVT_Done },
    9411             :   // Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3
    9412             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_95_addRegOrImmOperands, 4, CVT_Done },
    9413             :   // Convert__Reg1_0__VSrcB321_2__Reg1_3
    9414             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
    9415             :   // Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3
    9416             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOrImmOperands, 3, CVT_95_addRegOrImmOperands, 4, CVT_Done },
    9417             :   // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7
    9418             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands_95_defaultRowMask, 6, CVT_95_addImmOperands_95_defaultBankMask, 7, CVT_95_addImmOperands_95_defaultBoundCtrl, 8, CVT_Done },
    9419             :   // ConvertCustom_cvtSdwaVOP2b
    9420             :   { CVT_cvtSdwaVOP2b, 0, CVT_Done },
    9421             :   // Convert__Reg1_0__VSrcF161_1__Reg1_2
    9422             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9423             :   // ConvertCustom_cvtVOP3
    9424             :   { CVT_cvtVOP3, 0, CVT_Done },
    9425             :   // ConvertCustom_cvtDPP
    9426             :   { CVT_cvtDPP, 0, CVT_Done },
    9427             :   // ConvertCustom_cvtSdwaVOP2
    9428             :   { CVT_cvtSdwaVOP2, 0, CVT_Done },
    9429             :   // Convert__Reg1_0__VSrcF321_1__Reg1_2
    9430             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9431             :   // ConvertCustom_cvtVOP3OpSel
    9432             :   { CVT_cvtVOP3OpSel, 0, CVT_Done },
    9433             :   // Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2
    9434             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9435             :   // Convert__Reg1_0__VSrcB161_1__Reg1_2
    9436             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9437             :   // Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2
    9438             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9439             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6
    9440             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands_95_defaultRowMask, 5, CVT_95_addImmOperands_95_defaultBankMask, 6, CVT_95_addImmOperands_95_defaultBoundCtrl, 7, CVT_Done },
    9441             :   // Convert__Reg1_0__VSrcB321_1__Reg1_2
    9442             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9443             :   // Convert__Reg1_0__VCSrcB321_2__Reg1_3
    9444             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
    9445             :   // Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4
    9446             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOrImmOperands, 3, CVT_95_addRegOrImmOperands, 4, CVT_95_Reg, 5, CVT_Done },
    9447             :   // Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8
    9448             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addImmOperands_95_defaultRowMask, 7, CVT_95_addImmOperands_95_defaultBankMask, 8, CVT_95_addImmOperands_95_defaultBoundCtrl, 9, CVT_Done },
    9449             :   // Convert__Reg1_0__VCSrcB641_1__VCSrcB321_2
    9450             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9451             :   // Convert__Reg1_0__VCSrcB321_1__VCSrcB641_2
    9452             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9453             :   // Convert__Reg1_0__VSrcB321_1
    9454             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9455             :   // Convert__Reg1_0__VCSrcB321_1
    9456             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9457             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5
    9458             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands_95_defaultRowMask, 4, CVT_95_addImmOperands_95_defaultBankMask, 5, CVT_95_addImmOperands_95_defaultBoundCtrl, 6, CVT_Done },
    9459             :   // ConvertCustom_cvtSdwaVOP1
    9460             :   { CVT_cvtSdwaVOP1, 0, CVT_Done },
    9461             :   // Convert__Reg1_0__VSrcF161_1
    9462             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9463             :   // Convert__Reg1_0__VSrcF321_1
    9464             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9465             :   // Convert__Reg1_0__VSrcF641_1
    9466             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9467             :   // Convert__VSrcF161_1__Reg1_2
    9468             :   { CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9469             :   // ConvertCustom_cvtSdwaVOPC
    9470             :   { CVT_cvtSdwaVOPC, 0, CVT_Done },
    9471             :   // Convert__VSrcF321_1__Reg1_2
    9472             :   { CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9473             :   // Convert__VSrcF641_1__Reg1_2
    9474             :   { CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9475             :   // Convert__VSrcB161_1__Reg1_2
    9476             :   { CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9477             :   // Convert__VSrcB321_1__Reg1_2
    9478             :   { CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9479             :   // Convert__VSrcB641_1__Reg1_2
    9480             :   { CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9481             :   // Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2
    9482             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9483             :   // Convert__Reg1_0__VCSrcB321_1__Reg1_2
    9484             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Done },
    9485             :   // Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__Reg1_3
    9486             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_95_Reg, 4, CVT_Done },
    9487             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7
    9488             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands_95_defaultRowMask, 6, CVT_95_addImmOperands_95_defaultBankMask, 7, CVT_95_addImmOperands_95_defaultBoundCtrl, 8, CVT_Done },
    9489             :   // Convert__Reg1_0__VSrcB161_1
    9490             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_Done },
    9491             :   // Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0
    9492             :   { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_95_addRegOrImmOperands, 2, CVT_imm_95_0, 0, CVT_95_addRegOrImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
    9493             :   // Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0
    9494             :   { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_95_addRegOrImmOperands, 2, CVT_imm_95_0, 0, CVT_95_addRegOrImmOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
    9495             :   // Convert__Reg1_0__Reg1_1__VCSrcF321_2__VCSrcF321_3__VCSrcF321_4
    9496             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOrImmOperands, 3, CVT_95_addRegOrImmOperands, 4, CVT_95_addRegOrImmOperands, 5, CVT_Done },
    9497             :   // Convert__Reg1_0__Reg1_1__VCSrcF641_2__VCSrcF641_3__VCSrcF641_4
    9498             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOrImmOperands, 3, CVT_95_addRegOrImmOperands, 4, CVT_95_addRegOrImmOperands, 5, CVT_Done },
    9499             :   // ConvertCustom_cvtVOP3P
    9500             :   { CVT_cvtVOP3P, 0, CVT_Done },
    9501             :   // Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1
    9502             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done },
    9503             :   // Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3
    9504             :   { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    9505             :   // ConvertCustom_cvtVOP3Interp
    9506             :   { CVT_cvtVOP3Interp, 0, CVT_Done },
    9507             :   // Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3
    9508             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    9509             :   // Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3
    9510             :   { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
    9511             :   // Convert__Reg1_0__VSrcF161_1__Reg1_2__Tie0_1_1
    9512             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done },
    9513             :   // Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP161_3
    9514             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_95_addKImmFP16Operands, 4, CVT_Done },
    9515             :   // Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3
    9516             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_Reg, 3, CVT_95_addKImmFP32Operands, 4, CVT_Done },
    9517             :   // Convert__Reg1_0__VCSrcF321_1__KImmFP161_2__Reg1_3
    9518             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addKImmFP16Operands, 3, CVT_95_Reg, 4, CVT_Done },
    9519             :   // Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3
    9520             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addKImmFP32Operands, 3, CVT_95_Reg, 4, CVT_Done },
    9521             :   // Convert__ImmDPPCtrl1_0__ImmRowMask1_1__ImmBankMask1_2__ImmBoundCtrl1_3
    9522             :   { CVT_95_addImmOperands, 1, CVT_95_addImmOperands_95_defaultRowMask, 2, CVT_95_addImmOperands_95_defaultBankMask, 3, CVT_95_addImmOperands_95_defaultBoundCtrl, 4, CVT_Done },
    9523             :   // Convert__Reg1_0__Reg1_1__SCSrcB321_2
    9524             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOrImmOperands, 3, CVT_Done },
    9525             :   // Convert__Reg1_0__Reg1_1__Tie1_2_2__Tie0_1_1
    9526             :   { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Tied, Tie0_1_1, CVT_Done },
    9527             :   // Convert__Reg1_0__SSrcB321_1__SCSrcB321_2__Tie0_1_1
    9528             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
    9529             :   // Convert__Reg1_0__SCSrcB321_1__SCSrcB321_2__Tie0_1_1
    9530             :   { CVT_95_Reg, 1, CVT_95_addRegOrImmOperands, 2, CVT_95_addRegOrImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
    9531             : };
    9532             : 
    9533      160392 : void AMDGPUAsmParser::
    9534             : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
    9535             :                 const OperandVector &Operands,
    9536             :                 const SmallBitVector &OptionalOperandsMask) {
    9537             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    9538      160392 :   const uint8_t *Converter = ConversionTable[Kind];
    9539      160392 :   unsigned DefaultsOffset[14] = { 0 };
    9540             :   assert(OptionalOperandsMask.size() == 13);
    9541     2245488 :   for (unsigned i = 0, NumDefaults = 0; i < 13; ++i) {
    9542     2085096 :     DefaultsOffset[i + 1] = NumDefaults;
    9543     2671651 :     NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
    9544             :   }
    9545             :   unsigned OpIdx;
    9546             :   Inst.setOpcode(Opcode);
    9547      476323 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    9548      315931 :     OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
    9549      315931 :     switch (*p) {
    9550           0 :     default: llvm_unreachable("invalid conversion entry!");
    9551           0 :     case CVT_Reg:
    9552           0 :       static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    9553           0 :       break;
    9554        4862 :     case CVT_Tied: {
    9555             :       assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
    9556             :                           std::begin(TiedAsmOperandTable)) &&
    9557             :              "Tied operand not found");
    9558        4862 :       unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
    9559        4862 :       if (TiedResOpnd != (uint8_t) -1)
    9560             :         Inst.addOperand(Inst.getOperand(TiedResOpnd));
    9561             :       break;
    9562             :     }
    9563             :     case CVT_cvtMubufAtomic:
    9564             :       cvtMubufAtomic(Inst, Operands);
    9565             :       break;
    9566             :     case CVT_cvtMubufAtomicReturn:
    9567             :       cvtMubufAtomicReturn(Inst, Operands);
    9568             :       break;
    9569             :     case CVT_cvtMubufLds:
    9570             :       cvtMubufLds(Inst, Operands);
    9571             :       break;
    9572             :     case CVT_cvtMubuf:
    9573             :       cvtMubuf(Inst, Operands);
    9574             :       break;
    9575             :     case CVT_cvtDS:
    9576             :       cvtDS(Inst, Operands);
    9577             :       break;
    9578             :     case CVT_cvtDSGds:
    9579             :       cvtDSGds(Inst, Operands);
    9580             :       break;
    9581         682 :     case CVT_cvtDSOffset01:
    9582         682 :       cvtDSOffset01(Inst, Operands);
    9583         682 :       break;
    9584         170 :     case CVT_cvtExp:
    9585         170 :       cvtExp(Inst, Operands);
    9586         170 :       break;
    9587       94189 :     case CVT_95_Reg:
    9588      188378 :       static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
    9589       94189 :       break;
    9590        1539 :     case CVT_95_addImmOperands_95_defaultOffsetU12:
    9591        1539 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9592        1632 :         defaultOffsetU12()->addImmOperands(Inst, 1);
    9593             :       } else {
    9594        1446 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9595             :       }
    9596             :       break;
    9597        2685 :     case CVT_95_addImmOperands_95_defaultSLC:
    9598        2685 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9599        4832 :         defaultSLC()->addImmOperands(Inst, 1);
    9600             :       } else {
    9601         538 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9602             :       }
    9603             :       break;
    9604        3083 :     case CVT_95_addImmOperands_95_defaultGLC:
    9605        3083 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9606        5696 :         defaultGLC()->addImmOperands(Inst, 1);
    9607             :       } else {
    9608         470 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9609             :       }
    9610             :       break;
    9611             :     case CVT_imm_95_0:
    9612        1890 :       Inst.addOperand(MCOperand::createImm(0));
    9613        1890 :       break;
    9614        1146 :     case CVT_95_addImmOperands_95_defaultOffsetS13:
    9615        1146 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9616         596 :         defaultOffsetS13()->addImmOperands(Inst, 1);
    9617             :       } else {
    9618        1696 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9619             :       }
    9620             :       break;
    9621             :     case CVT_cvtMIMGAtomic:
    9622             :       cvtMIMGAtomic(Inst, Operands);
    9623             :       break;
    9624        3579 :     case CVT_cvtMIMG:
    9625        3579 :       cvtMIMG(Inst, Operands);
    9626        3579 :       break;
    9627      103373 :     case CVT_95_addRegOrImmOperands:
    9628      206746 :       static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addRegOrImmOperands(Inst, 1);
    9629      103373 :       break;
    9630        6351 :     case CVT_95_addImmOperands:
    9631       12702 :       static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9632        6351 :       break;
    9633         122 :     case CVT_95_addImmOperands_95_defaultSMRDOffset20:
    9634         122 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9635           0 :         defaultSMRDOffset20()->addImmOperands(Inst, 1);
    9636             :       } else {
    9637         244 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9638             :       }
    9639             :       break;
    9640         130 :     case CVT_95_addSoppBrTargetOperands:
    9641         260 :       static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addSoppBrTargetOperands(Inst, 1);
    9642         130 :       break;
    9643          78 :     case CVT_95_addImmOperands_95_defaultSMRDOffset8:
    9644          78 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9645           0 :         defaultSMRDOffset8()->addImmOperands(Inst, 1);
    9646             :       } else {
    9647         156 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9648             :       }
    9649             :       break;
    9650          24 :     case CVT_95_addImmOperands_95_defaultSMRDLiteralOffset:
    9651          24 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9652           0 :         defaultSMRDLiteralOffset()->addImmOperands(Inst, 1);
    9653             :       } else {
    9654          48 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9655             :       }
    9656             :       break;
    9657          63 :     case CVT_cvtMtbuf:
    9658          63 :       cvtMtbuf(Inst, Operands);
    9659          63 :       break;
    9660        4368 :     case CVT_95_addImmOperands_95_defaultRowMask:
    9661        4368 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9662         450 :         defaultRowMask()->addImmOperands(Inst, 1);
    9663             :       } else {
    9664        8286 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9665             :       }
    9666             :       break;
    9667        4368 :     case CVT_95_addImmOperands_95_defaultBankMask:
    9668        4368 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9669         450 :         defaultBankMask()->addImmOperands(Inst, 1);
    9670             :       } else {
    9671        8286 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9672             :       }
    9673             :       break;
    9674        4368 :     case CVT_95_addImmOperands_95_defaultBoundCtrl:
    9675        4368 :       if (OptionalOperandsMask[*(p + 1) - 1]) {
    9676        8022 :         defaultBoundCtrl()->addImmOperands(Inst, 1);
    9677             :       } else {
    9678         714 :         static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
    9679             :       }
    9680             :       break;
    9681             :     case CVT_cvtSdwaVOP2b:
    9682             :       cvtSdwaVOP2b(Inst, Operands);
    9683             :       break;
    9684       34456 :     case CVT_cvtVOP3:
    9685       34456 :       cvtVOP3(Inst, Operands);
    9686       34456 :       break;
    9687        5203 :     case CVT_cvtDPP:
    9688        5203 :       cvtDPP(Inst, Operands);
    9689        5203 :       break;
    9690             :     case CVT_cvtSdwaVOP2:
    9691             :       cvtSdwaVOP2(Inst, Operands);
    9692             :       break;
    9693        2197 :     case CVT_cvtVOP3OpSel:
    9694        2197 :       cvtVOP3OpSel(Inst, Operands);
    9695        2197 :       break;
    9696             :     case CVT_cvtSdwaVOP1:
    9697             :       cvtSdwaVOP1(Inst, Operands);
    9698             :       break;
    9699       12564 :     case CVT_cvtSdwaVOPC:
    9700       12564 :       cvtSdwaVOPC(Inst, Operands);
    9701       12564 :       break;
    9702        1834 :     case CVT_cvtVOP3P:
    9703        1834 :       cvtVOP3P(Inst, Operands);
    9704        1834 :       break;
    9705         433 :     case CVT_cvtVOP3Interp:
    9706         433 :       cvtVOP3Interp(Inst, Operands);
    9707         433 :       break;
    9708          62 :     case CVT_95_addKImmFP16Operands:
    9709          62 :       static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addKImmFP16Operands(Inst, 1);
    9710             :       break;
    9711         102 :     case CVT_95_addKImmFP32Operands:
    9712         102 :       static_cast<AMDGPUOperand&>(*Operands[OpIdx]).addKImmFP32Operands(Inst, 1);
    9713             :       break;
    9714             :     }
    9715             :   }
    9716      160392 : }
    9717             : 
    9718           0 : void AMDGPUAsmParser::
    9719             : convertToMapAndConstraints(unsigned Kind,
    9720             :                            const OperandVector &Operands) {
    9721             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
    9722             :   unsigned NumMCOperands = 0;
    9723           0 :   const uint8_t *Converter = ConversionTable[Kind];
    9724           0 :   for (const uint8_t *p = Converter; *p; p+= 2) {
    9725           0 :     switch (*p) {
    9726           0 :     default: llvm_unreachable("invalid conversion entry!");
    9727           0 :     case CVT_Reg:
    9728           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9729           0 :       Operands[*(p + 1)]->setConstraint("r");
    9730           0 :       ++NumMCOperands;
    9731           0 :       break;
    9732           0 :     case CVT_Tied:
    9733           0 :       ++NumMCOperands;
    9734           0 :       break;
    9735           0 :     case CVT_95_Reg:
    9736           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9737           0 :       Operands[*(p + 1)]->setConstraint("r");
    9738           0 :       NumMCOperands += 1;
    9739           0 :       break;
    9740           0 :     case CVT_95_addImmOperands_95_defaultOffsetU12:
    9741           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9742           0 :       Operands[*(p + 1)]->setConstraint("m");
    9743           0 :       NumMCOperands += 1;
    9744           0 :       break;
    9745           0 :     case CVT_95_addImmOperands_95_defaultSLC:
    9746           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9747           0 :       Operands[*(p + 1)]->setConstraint("m");
    9748           0 :       NumMCOperands += 1;
    9749           0 :       break;
    9750           0 :     case CVT_95_addImmOperands_95_defaultGLC:
    9751           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9752           0 :       Operands[*(p + 1)]->setConstraint("m");
    9753           0 :       NumMCOperands += 1;
    9754           0 :       break;
    9755           0 :     case CVT_imm_95_0:
    9756           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9757           0 :       Operands[*(p + 1)]->setConstraint("");
    9758           0 :       ++NumMCOperands;
    9759           0 :       break;
    9760           0 :     case CVT_95_addImmOperands_95_defaultOffsetS13:
    9761           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9762           0 :       Operands[*(p + 1)]->setConstraint("m");
    9763           0 :       NumMCOperands += 1;
    9764           0 :       break;
    9765           0 :     case CVT_95_addRegOrImmOperands:
    9766           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9767           0 :       Operands[*(p + 1)]->setConstraint("m");
    9768           0 :       NumMCOperands += 1;
    9769           0 :       break;
    9770           0 :     case CVT_95_addImmOperands:
    9771           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9772           0 :       Operands[*(p + 1)]->setConstraint("m");
    9773           0 :       NumMCOperands += 1;
    9774           0 :       break;
    9775           0 :     case CVT_95_addImmOperands_95_defaultSMRDOffset20:
    9776           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9777           0 :       Operands[*(p + 1)]->setConstraint("m");
    9778           0 :       NumMCOperands += 1;
    9779           0 :       break;
    9780           0 :     case CVT_95_addSoppBrTargetOperands:
    9781           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9782           0 :       Operands[*(p + 1)]->setConstraint("m");
    9783           0 :       NumMCOperands += 1;
    9784           0 :       break;
    9785           0 :     case CVT_95_addImmOperands_95_defaultSMRDOffset8:
    9786           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9787           0 :       Operands[*(p + 1)]->setConstraint("m");
    9788           0 :       NumMCOperands += 1;
    9789           0 :       break;
    9790           0 :     case CVT_95_addImmOperands_95_defaultSMRDLiteralOffset:
    9791           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9792           0 :       Operands[*(p + 1)]->setConstraint("m");
    9793           0 :       NumMCOperands += 1;
    9794           0 :       break;
    9795           0 :     case CVT_95_addImmOperands_95_defaultRowMask:
    9796           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9797           0 :       Operands[*(p + 1)]->setConstraint("m");
    9798           0 :       NumMCOperands += 1;
    9799           0 :       break;
    9800           0 :     case CVT_95_addImmOperands_95_defaultBankMask:
    9801           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9802           0 :       Operands[*(p + 1)]->setConstraint("m");
    9803           0 :       NumMCOperands += 1;
    9804           0 :       break;
    9805           0 :     case CVT_95_addImmOperands_95_defaultBoundCtrl:
    9806           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9807           0 :       Operands[*(p + 1)]->setConstraint("m");
    9808           0 :       NumMCOperands += 1;
    9809           0 :       break;
    9810           0 :     case CVT_95_addKImmFP16Operands:
    9811           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9812           0 :       Operands[*(p + 1)]->setConstraint("m");
    9813           0 :       NumMCOperands += 1;
    9814           0 :       break;
    9815           0 :     case CVT_95_addKImmFP32Operands:
    9816           0 :       Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
    9817           0 :       Operands[*(p + 1)]->setConstraint("m");
    9818           0 :       NumMCOperands += 1;
    9819           0 :       break;
    9820             :     }
    9821             :   }
    9822           0 : }
    9823             : 
    9824             : namespace {
    9825             : 
    9826             : /// MatchClassKind - The kinds of classes which participate in
    9827             : /// instruction matching.
    9828             : enum MatchClassKind {
    9829             :   InvalidMatchClass = 0,
    9830             :   OptionalMatchClass = 1,
    9831             :   MCK_addr64, // 'addr64'
    9832             :   MCK_done, // 'done'
    9833             :   MCK_gds, // 'gds'
    9834             :   MCK_glc, // 'glc'
    9835             :   MCK_idxen, // 'idxen'
    9836             :   MCK_lds, // 'lds'
    9837             :   MCK_off, // 'off'
    9838             :   MCK_offen, // 'offen'
    9839             :   MCK_LAST_TOKEN = MCK_offen,
    9840             :   MCK_M0_CLASS, // register class 'M0_CLASS'
    9841             :   MCK_Pseudo_SReg_128, // register class 'Pseudo_SReg_128'
    9842             :   MCK_SCC_CLASS, // register class 'SCC_CLASS'
    9843             :   MCK_TTMP_512, // register class 'TTMP_512'
    9844             :   MCK_VCC, // register class 'VCC'
    9845             :   MCK_Pseudo_SReg_32, // register class 'Pseudo_SReg_32'
    9846             :   MCK_TTMP_256, // register class 'TTMP_256'
    9847             :   MCK_TTMP_128, // register class 'TTMP_128'
    9848             :   MCK_TTMP_64, // register class 'TTMP_64'
    9849             :   MCK_TTMP_32, // register class 'TTMP_32'
    9850             :   MCK_SGPR_512, // register class 'SGPR_512'
    9851             :   MCK_SReg_512, // register class 'SReg_512'
    9852             :   MCK_SGPR_256, // register class 'SGPR_256'
    9853             :   MCK_SGPR_128, // register class 'SGPR_128'
    9854             :   MCK_SReg_256, // register class 'SReg_256'
    9855             :   MCK_SReg_128, // register class 'SReg_128'
    9856             :   MCK_SGPR_64, // register class 'SGPR_64'
    9857             :   MCK_SReg_64_XEXEC, // register class 'SReg_64_XEXEC'
    9858             :   MCK_SReg_64, // register class 'SReg_64'
    9859             :   MCK_SGPR_32, // register class 'SGPR_32'
    9860             :   MCK_SReg_32_XM0_XEXEC, // register class 'SReg_32_XM0_XEXEC'
    9861             :   MCK_Reg4, // derived register class
    9862             :   MCK_SReg_32_XEXEC_HI, // register class 'SReg_32_XEXEC_HI'
    9863             :   MCK_SReg_32_XM0, // register class 'SReg_32_XM0'
    9864             :   MCK_SReg_32, // register class 'SReg_32'
    9865             :   MCK_VReg_512, // register class 'VReg_512'
    9866             :   MCK_VReg_256, // register class 'VReg_256'
    9867             :   MCK_VReg_128, // register class 'VReg_128'
    9868             :   MCK_VReg_96, // register class 'VReg_96'
    9869             :   MCK_VReg_64, // register class 'VReg_64'
    9870             :   MCK_VGPR_32, // register class 'VGPR_32,VReg_1'
    9871             :   MCK_VS_64, // register class 'VS_64'
    9872             :   MCK_VS_32, // register class 'VS_32'
    9873             :   MCK_LAST_REGISTER = MCK_VS_32,
    9874             :   MCK_AttrChan, // user defined class 'AttrChanMatchClass'
    9875             :   MCK_Attr, // user defined class 'AttrMatchClass'
    9876             :   MCK_ExpTgt, // user defined class 'ExpTgtMatchClass'
    9877             :   MCK_RegOrImmWithFP16InputMods, // user defined class 'FP16InputModsMatchClass'
    9878             :   MCK_SDWAWithFP16InputMods, // user defined class 'FP16SDWAInputModsMatchClass'
    9879             :   MCK_RegOrImmWithFP32InputMods, // user defined class 'FP32InputModsMatchClass'
    9880             :   MCK_SDWAWithFP32InputMods, // user defined class 'FP32SDWAInputModsMatchClass'
    9881             :   MCK_RegOrImmWithFP64InputMods, // user defined class 'FP64InputModsMatchClass'
    9882             :   MCK_VRegWithFPInputMods, // user defined class 'FPVRegInputModsMatchClass'
    9883             :   MCK_GPRIdxMode, // user defined class 'GPRIdxModeMatchClass'
    9884             :   MCK_Imm, // user defined class 'ImmAsmOperand'
    9885             :   MCK_SDWAWithInt16InputMods, // user defined class 'Int16SDWAInputModsMatchClass'
    9886             :   MCK_RegOrImmWithInt32InputMods, // user defined class 'Int32InputModsMatchClass'
    9887             :   MCK_SDWAWithInt32InputMods, // user defined class 'Int32SDWAInputModsMatchClass'
    9888             :   MCK_RegOrImmWithInt64InputMods, // user defined class 'Int64InputModsMatchClass'
    9889             :   MCK_OpSelMods, // user defined class 'IntOpSelModsMatchClass'
    9890             :   MCK_VRegWithIntInputMods, // user defined class 'IntVRegInputModsMatchClass'
    9891             :   MCK_InterpSlot, // user defined class 'InterpSlotMatchClass'
    9892             :   MCK_KImmFP16, // user defined class 'KImmFP16MatchClass'
    9893             :   MCK_KImmFP32, // user defined class 'KImmFP32MatchClass'
    9894             :   MCK_PackedFP16InputMods, // user defined class 'PackedF16InputModsMatchClass'
    9895             :   MCK_PackedInt16InputMods, // user defined class 'PackedI16InputModsMatchClass'
    9896             :   MCK_SWaitCnt, // user defined class 'SWaitMatchClass'
    9897             :   MCK_SendMsg, // user defined class 'SendMsgMatchClass'
    9898             :   MCK_SoppBrTarget, // user defined class 'SoppBrTarget'
    9899             :   MCK_Swizzle, // user defined class 'SwizzleMatchClass'
    9900             :   MCK_VReg32OrOff, // user defined class 'VReg32OrOffClass'
    9901             :   MCK_SSrcB16, // user defined class 'anonymous_1043'
    9902             :   MCK_SSrcF16, // user defined class 'anonymous_1044'
    9903             :   MCK_SSrcB32, // user defined class 'anonymous_1045'
    9904             :   MCK_SSrcF32, // user defined class 'anonymous_1046'
    9905             :   MCK_SSrcB64, // user defined class 'anonymous_1047'
    9906             :   MCK_SSrcF64, // user defined class 'anonymous_1048'
    9907             :   MCK_SSrcV2B16, // user defined class 'anonymous_1049'
    9908             :   MCK_SSrcV2F16, // user defined class 'anonymous_1050'
    9909             :   MCK_SCSrcB16, // user defined class 'anonymous_1051'
    9910             :   MCK_SCSrcF16, // user defined class 'anonymous_1052'
    9911             :   MCK_SCSrcB32, // user defined class 'anonymous_1053'
    9912             :   MCK_SCSrcF32, // user defined class 'anonymous_1054'
    9913             :   MCK_SCSrcB64, // user defined class 'anonymous_1055'
    9914             :   MCK_SCSrcF64, // user defined class 'anonymous_1056'
    9915             :   MCK_SCSrcV2B16, // user defined class 'anonymous_1057'
    9916             :   MCK_SCSrcV2F16, // user defined class 'anonymous_1058'
    9917             :   MCK_VSrcB16, // user defined class 'anonymous_1059'
    9918             :   MCK_VSrcF16, // user defined class 'anonymous_1060'
    9919             :   MCK_VSrcB32, // user defined class 'anonymous_1061'
    9920             :   MCK_VSrcF32, // user defined class 'anonymous_1062'
    9921             :   MCK_VSrcB64, // user defined class 'anonymous_1063'
    9922             :   MCK_VSrcF64, // user defined class 'anonymous_1064'
    9923             :   MCK_VSrcV2B16, // user defined class 'anonymous_1065'
    9924             :   MCK_VSrcV2F16, // user defined class 'anonymous_1066'
    9925             :   MCK_VCSrcB16, // user defined class 'anonymous_1067'
    9926             :   MCK_VCSrcF16, // user defined class 'anonymous_1068'
    9927             :   MCK_VCSrcB32, // user defined class 'anonymous_1069'
    9928             :   MCK_VCSrcF32, // user defined class 'anonymous_1070'
    9929             :   MCK_VCSrcB64, // user defined class 'anonymous_1071'
    9930             :   MCK_VCSrcF64, // user defined class 'anonymous_1072'
    9931             :   MCK_VCSrcV2B16, // user defined class 'anonymous_1073'
    9932             :   MCK_VCSrcV2F16, // user defined class 'anonymous_1074'
    9933             :   MCK_ImmOffen, // user defined class 'anonymous_1113'
    9934             :   MCK_ImmIdxen, // user defined class 'anonymous_1114'
    9935             :   MCK_ImmAddr64, // user defined class 'anonymous_1115'
    9936             :   MCK_ImmOffsetU12, // user defined class 'anonymous_1116'
    9937             :   MCK_ImmOffsetS13, // user defined class 'anonymous_1117'
    9938             :   MCK_ImmOffset, // user defined class 'anonymous_1118'
    9939             :   MCK_ImmOffset0, // user defined class 'anonymous_1119'
    9940             :   MCK_ImmOffset1, // user defined class 'anonymous_1120'
    9941             :   MCK_ImmGDS, // user defined class 'anonymous_1121'
    9942             :   MCK_ImmOModSI, // user defined class 'anonymous_1122'
    9943             :   MCK_ImmClampSI, // user defined class 'anonymous_1123'
    9944             :   MCK_ImmHigh, // user defined class 'anonymous_1124'
    9945             :   MCK_ImmGLC, // user defined class 'anonymous_1125'
    9946             :   MCK_ImmSLC, // user defined class 'anonymous_1126'
    9947             :   MCK_ImmTFE, // user defined class 'anonymous_1127'
    9948             :   MCK_ImmUNorm, // user defined class 'anonymous_1128'
    9949             :   MCK_ImmDA, // user defined class 'anonymous_1129'
    9950             :   MCK_ImmR128A16, // user defined class 'anonymous_1130'
    9951             :   MCK_ImmD16, // user defined class 'anonymous_1131'
    9952             :   MCK_ImmLWE, // user defined class 'anonymous_1132'
    9953             :   MCK_ImmExpCompr, // user defined class 'anonymous_1133'
    9954             :   MCK_ImmExpVM, // user defined class 'anonymous_1134'
    9955             :   MCK_ImmFORMAT, // user defined class 'anonymous_1135'
    9956             :   MCK_ImmDMask, // user defined class 'anonymous_1136'
    9957             :   MCK_ImmDPPCtrl, // user defined class 'anonymous_1137'
    9958             :   MCK_ImmRowMask, // user defined class 'anonymous_1138'
    9959             :   MCK_ImmBankMask, // user defined class 'anonymous_1139'
    9960             :   MCK_ImmBoundCtrl, // user defined class 'anonymous_1140'
    9961             :   MCK_ImmSDWADstSel, // user defined class 'anonymous_1141'
    9962             :   MCK_ImmSDWASrc0Sel, // user defined class 'anonymous_1142'
    9963             :   MCK_ImmSDWASrc1Sel, // user defined class 'anonymous_1143'
    9964             :   MCK_ImmSDWADstUnused, // user defined class 'anonymous_1144'
    9965             :   MCK_ImmOpSel, // user defined class 'anonymous_1145'
    9966             :   MCK_ImmOpSelHi, // user defined class 'anonymous_1146'
    9967             :   MCK_ImmNegLo, // user defined class 'anonymous_1147'
    9968             :   MCK_ImmNegHi, // user defined class 'anonymous_1148'
    9969             :   MCK_ImmHwreg, // user defined class 'anonymous_1149'
    9970             :   MCK_ImmExpTgt, // user defined class 'anonymous_1150'
    9971             :   MCK_ImmSMRDOffset8, // user defined class 'anonymous_3126'
    9972             :   MCK_ImmSMRDOffset20, // user defined class 'anonymous_3127'
    9973             :   MCK_ImmSMRDLiteralOffset, // user defined class 'anonymous_3128'
    9974             :   MCK_S16Imm, // user defined class 's16ImmTarget'
    9975             :   MCK_U16Imm, // user defined class 'u16ImmTarget'
    9976             :   NumMatchClassKinds
    9977             : };
    9978             : 
    9979             : }
    9980             : 
    9981           0 : static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
    9982           0 :   return MCTargetAsmParser::Match_InvalidOperand;
    9983             : }
    9984             : 
    9985        8215 : static MatchClassKind matchTokenString(StringRef Name) {
    9986        8215 :   switch (Name.size()) {
    9987             :   default: break;
    9988        8157 :   case 3:        // 4 strings to match.
    9989             :     switch (Name[0]) {
    9990             :     default: break;
    9991         318 :     case 'g':    // 2 strings to match.
    9992             :       switch (Name[1]) {
    9993             :       default: break;
    9994           0 :       case 'd':  // 1 string to match.
    9995           0 :         if (Name[2] != 's')
    9996             :           break;
    9997             :         return MCK_gds;  // "gds"
    9998         318 :       case 'l':  // 1 string to match.
    9999         318 :         if (Name[2] != 'c')
   10000             :           break;
   10001             :         return MCK_glc;  // "glc"
   10002             :       }
   10003             :       break;
   10004             :     case 'l':    // 1 string to match.
   10005           4 :       if (memcmp(Name.data()+1, "ds", 2) != 0)
   10006             :         break;
   10007             :       return MCK_lds;    // "lds"
   10008             :     case 'o':    // 1 string to match.
   10009        7835 :       if (memcmp(Name.data()+1, "ff", 2) != 0)
   10010             :         break;
   10011             :       return MCK_off;    // "off"
   10012             :     }
   10013             :     break;
   10014             :   case 4:        // 1 string to match.
   10015          58 :     if (memcmp(Name.data()+0, "done", 4) != 0)
   10016             :       break;
   10017             :     return MCK_done;     // "done"
   10018           0 :   case 5:        // 2 strings to match.
   10019             :     switch (Name[0]) {
   10020             :     default: break;
   10021             :     case 'i':    // 1 string to match.
   10022           0 :       if (memcmp(Name.data()+1, "dxen", 4) != 0)
   10023             :         break;
   10024             :       return MCK_idxen;  // "idxen"
   10025             :     case 'o':    // 1 string to match.
   10026           0 :       if (memcmp(Name.data()+1, "ffen", 4) != 0)
   10027             :         break;
   10028             :       return MCK_offen;  // "offen"
   10029             :     }
   10030             :     break;
   10031             :   case 6:        // 1 string to match.
   10032           0 :     if (memcmp(Name.data()+0, "addr64", 6) != 0)
   10033             :       break;
   10034             :     return MCK_addr64;   // "addr64"
   10035             :   }
   10036             :   return InvalidMatchClass;
   10037             : }
   10038             : 
   10039             : /// isSubclass - Compute whether \p A is a subclass of \p B.
   10040      619717 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
   10041      619717 :   if (A == B)
   10042             :     return true;
   10043             : 
   10044      372870 :   switch (A) {
   10045             :   default:
   10046             :     return false;
   10047             : 
   10048        1008 :   case MCK_M0_CLASS:
   10049             :     switch (B) {
   10050             :     default: return false;
   10051             :     case MCK_SReg_32_XEXEC_HI: return true;
   10052             :     case MCK_SReg_32: return true;
   10053             :     case MCK_VS_32: return true;
   10054             :     }
   10055             : 
   10056           8 :   case MCK_TTMP_512:
   10057           8 :     return B == MCK_SReg_512;
   10058             : 
   10059       13890 :   case MCK_VCC:
   10060             :     switch (B) {
   10061             :     default: return false;
   10062             :     case MCK_SReg_64_XEXEC: return true;
   10063             :     case MCK_SReg_64: return true;
   10064             :     case MCK_VS_64: return true;
   10065             :     }
   10066             : 
   10067         185 :   case MCK_TTMP_256:
   10068         185 :     return B == MCK_SReg_256;
   10069             : 
   10070         656 :   case MCK_TTMP_128:
   10071         656 :     return B == MCK_SReg_128;
   10072             : 
   10073         824 :   case MCK_TTMP_64:
   10074             :     switch (B) {
   10075             :     default: return false;
   10076             :     case MCK_SReg_64_XEXEC: return true;
   10077             :     case MCK_SReg_64: return true;
   10078             :     case MCK_VS_64: return true;
   10079             :     }
   10080             : 
   10081         603 :   case MCK_TTMP_32:
   10082             :     switch (B) {
   10083             :     default: return false;
   10084             :     case MCK_SReg_32_XM0_XEXEC: return true;
   10085             :     case MCK_Reg4: return true;
   10086             :     case MCK_SReg_32_XEXEC_HI: return true;
   10087             :     case MCK_SReg_32_XM0: return true;
   10088             :     case MCK_SReg_32: return true;
   10089             :     case MCK_VS_32: return true;
   10090             :     }
   10091             : 
   10092         345 :   case MCK_SGPR_512:
   10093         345 :     return B == MCK_SReg_512;
   10094             : 
   10095        5069 :   case MCK_SGPR_256:
   10096        5069 :     return B == MCK_SReg_256;
   10097             : 
   10098       15286 :   case MCK_SGPR_128:
   10099       15286 :     return B == MCK_SReg_128;
   10100             : 
   10101       72520 :   case MCK_SGPR_64:
   10102             :     switch (B) {
   10103             :     default: return false;
   10104             :     case MCK_SReg_64_XEXEC: return true;
   10105             :     case MCK_SReg_64: return true;
   10106             :     case MCK_VS_64: return true;
   10107             :     }
   10108             : 
   10109        3537 :   case MCK_SReg_64_XEXEC:
   10110        3537 :     switch (B) {
   10111             :     default: return false;
   10112        3207 :     case MCK_SReg_64: return true;
   10113           0 :     case MCK_VS_64: return true;
   10114             :     }
   10115             : 
   10116         213 :   case MCK_SReg_64:
   10117         213 :     return B == MCK_VS_64;
   10118             : 
   10119       17667 :   case MCK_SGPR_32:
   10120             :     switch (B) {
   10121             :     default: return false;
   10122             :     case MCK_SReg_32_XM0_XEXEC: return true;
   10123             :     case MCK_Reg4: return true;
   10124             :     case MCK_SReg_32_XEXEC_HI: return true;
   10125             :     case MCK_SReg_32_XM0: return true;
   10126             :     case MCK_SReg_32: return true;
   10127             :     case MCK_VS_32: return true;
   10128             :     }
   10129             : 
   10130        3912 :   case MCK_SReg_32_XM0_XEXEC:
   10131             :     switch (B) {
   10132             :     default: return false;
   10133             :     case MCK_Reg4: return true;
   10134             :     case MCK_SReg_32_XEXEC_HI: return true;
   10135             :     case MCK_SReg_32_XM0: return true;
   10136             :     case MCK_SReg_32: return true;
   10137             :     case MCK_VS_32: return true;
   10138             :     }
   10139             : 
   10140         560 :   case MCK_Reg4:
   10141             :     switch (B) {
   10142             :     default: return false;
   10143             :     case MCK_SReg_32_XEXEC_HI: return true;
   10144             :     case MCK_SReg_32_XM0: return true;
   10145             :     case MCK_SReg_32: return true;
   10146             :     case MCK_VS_32: return true;
   10147             :     }
   10148             : 
   10149           6 :   case MCK_SReg_32_XEXEC_HI:
   10150           6 :     switch (B) {
   10151             :     default: return false;
   10152           0 :     case MCK_SReg_32: return true;
   10153           0 :     case MCK_VS_32: return true;
   10154             :     }
   10155             : 
   10156         614 :   case MCK_SReg_32_XM0:
   10157         614 :     switch (B) {
   10158             :     default: return false;
   10159         497 :     case MCK_SReg_32: return true;
   10160           0 :     case MCK_VS_32: return true;
   10161             :     }
   10162             : 
   10163         655 :   case MCK_SReg_32:
   10164         655 :     return B == MCK_VS_32;
   10165             : 
   10166       21880 :   case MCK_VReg_64:
   10167       21880 :     return B == MCK_VS_64;
   10168             : 
   10169       33147 :   case MCK_VGPR_32:
   10170       33147 :     return B == MCK_VS_32;
   10171             : 
   10172          23 :   case MCK_Swizzle:
   10173          23 :     return B == OptionalMatchClass;
   10174             : 
   10175           0 :   case MCK_ImmOffen:
   10176           0 :     return B == OptionalMatchClass;
   10177             : 
   10178           0 :   case MCK_ImmIdxen:
   10179           0 :     return B == OptionalMatchClass;
   10180             : 
   10181           0 :   case MCK_ImmAddr64:
   10182           0 :     return B == OptionalMatchClass;
   10183             : 
   10184        1992 :   case MCK_ImmOffsetU12:
   10185        1992 :     return B == OptionalMatchClass;
   10186             : 
   10187         385 :   case MCK_ImmOffsetS13:
   10188         385 :     return B == OptionalMatchClass;
   10189             : 
   10190        3166 :   case MCK_ImmOffset:
   10191        3166 :     return B == OptionalMatchClass;
   10192             : 
   10193         208 :   case MCK_ImmOffset0:
   10194         208 :     return B == OptionalMatchClass;
   10195             : 
   10196         112 :   case MCK_ImmOffset1:
   10197         112 :     return B == OptionalMatchClass;
   10198             : 
   10199        5540 :   case MCK_ImmGDS:
   10200        5540 :     return B == OptionalMatchClass;
   10201             : 
   10202        6452 :   case MCK_ImmOModSI:
   10203        6452 :     return B == OptionalMatchClass;
   10204             : 
   10205       75147 :   case MCK_ImmClampSI:
   10206       75147 :     return B == OptionalMatchClass;
   10207             : 
   10208         277 :   case MCK_ImmHigh:
   10209         277 :     return B == OptionalMatchClass;
   10210             : 
   10211        9518 :   case MCK_ImmGLC:
   10212        9518 :     return B == OptionalMatchClass;
   10213             : 
   10214        6862 :   case MCK_ImmSLC:
   10215        6862 :     return B == OptionalMatchClass;
   10216             : 
   10217        1152 :   case MCK_ImmTFE:
   10218        1152 :     return B == OptionalMatchClass;
   10219             : 
   10220        3129 :   case MCK_ImmUNorm:
   10221        3129 :     return B == OptionalMatchClass;
   10222             : 
   10223         561 :   case MCK_ImmDA:
   10224         561 :     return B == OptionalMatchClass;
   10225             : 
   10226        1196 :   case MCK_ImmR128A16:
   10227        1196 :     return B == OptionalMatchClass;
   10228             : 
   10229         118 :   case MCK_ImmD16:
   10230         118 :     return B == OptionalMatchClass;
   10231             : 
   10232         676 :   case MCK_ImmLWE:
   10233         676 :     return B == OptionalMatchClass;
   10234             : 
   10235         342 :   case MCK_ImmExpCompr:
   10236         342 :     return B == OptionalMatchClass;
   10237             : 
   10238          92 :   case MCK_ImmExpVM:
   10239          92 :     return B == OptionalMatchClass;
   10240             : 
   10241           0 :   case MCK_ImmFORMAT:
   10242           0 :     return B == OptionalMatchClass;
   10243             : 
   10244         241 :   case MCK_ImmDMask:
   10245         241 :     return B == OptionalMatchClass;
   10246             : 
   10247         399 :   case MCK_ImmRowMask:
   10248         399 :     return B == OptionalMatchClass;
   10249             : 
   10250         329 :   case MCK_ImmBankMask:
   10251         329 :     return B == OptionalMatchClass;
   10252             : 
   10253        8425 :   case MCK_ImmBoundCtrl:
   10254        8425 :     return B == OptionalMatchClass;
   10255             : 
   10256        1770 :   case MCK_ImmSDWADstSel:
   10257        1770 :     return B == OptionalMatchClass;
   10258             : 
   10259        2152 :   case MCK_ImmSDWASrc0Sel:
   10260        2152 :     return B == OptionalMatchClass;
   10261             : 
   10262        1077 :   case MCK_ImmSDWASrc1Sel:
   10263        1077 :     return B == OptionalMatchClass;
   10264             : 
   10265        1758 :   case MCK_ImmSDWADstUnused:
   10266        1758 :     return B == OptionalMatchClass;
   10267             : 
   10268        3563 :   case MCK_ImmOpSel:
   10269        3563 :     return B == OptionalMatchClass;
   10270             : 
   10271         391 :   case MCK_ImmOpSelHi:
   10272         391 :     return B == OptionalMatchClass;
   10273             : 
   10274         361 :   case MCK_ImmNegLo:
   10275         361 :     return B == OptionalMatchClass;
   10276             : 
   10277          80 :   case MCK_ImmNegHi:
   10278          80 :     return B == OptionalMatchClass;
   10279             : 
   10280          58 :   case MCK_ImmSMRDOffset8:
   10281          58 :     return B == OptionalMatchClass;
   10282             : 
   10283         987 :   case MCK_ImmSMRDOffset20:
   10284         987 :     return B == OptionalMatchClass;
   10285             : 
   10286           0 :   case MCK_ImmSMRDLiteralOffset:
   10287           0 :     return B == OptionalMatchClass;
   10288             :   }
   10289             : }
   10290             : 
   10291      997901 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
   10292             :   AMDGPUOperand &Operand = (AMDGPUOperand&)GOp;
   10293      997901 :   if (Kind == InvalidMatchClass)
   10294             :     return MCTargetAsmParser::Match_InvalidOperand;
   10295             : 
   10296        9938 :   if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
   10297        8215 :     return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
   10298             :              MCTargetAsmParser::Match_Success :
   10299             :              MCTargetAsmParser::Match_InvalidOperand;
   10300             : 
   10301      982035 :   switch (Kind) {
   10302             :   default: break;
   10303             :   // 'AttrChan' class
   10304             :   case MCK_AttrChan: {
   10305             :     DiagnosticPredicate DP(Operand.isAttrChan());
   10306         866 :     if (DP.isMatch())
   10307             :       return MCTargetAsmParser::Match_Success;
   10308             :     break;
   10309             :     }
   10310             :   // 'Attr' class
   10311             :   case MCK_Attr: {
   10312             :     DiagnosticPredicate DP(Operand.isInterpAttr());
   10313         986 :     if (DP.isMatch())
   10314             :       return MCTargetAsmParser::Match_Success;
   10315             :     break;
   10316             :     }
   10317             :   // 'ExpTgt' class
   10318             :   case MCK_ExpTgt: {
   10319             :     DiagnosticPredicate DP(Operand.isExpTgt());
   10320           0 :     if (DP.isMatch())
   10321             :       return MCTargetAsmParser::Match_Success;
   10322             :     break;
   10323             :     }
   10324             :   // 'RegOrImmWithFP16InputMods' class
   10325             :   case MCK_RegOrImmWithFP16InputMods: {
   10326             :     DiagnosticPredicate DP(Operand.isRegOrImmWithFP16InputMods());
   10327       19554 :     if (DP.isMatch())
   10328             :       return MCTargetAsmParser::Match_Success;
   10329             :     break;
   10330             :     }
   10331             :   // 'SDWAWithFP16InputMods' class
   10332             :   case MCK_SDWAWithFP16InputMods: {
   10333             :     DiagnosticPredicate DP(Operand.isSDWAFP16Operand());
   10334       13308 :     if (DP.isMatch())
   10335             :       return MCTargetAsmParser::Match_Success;
   10336             :     break;
   10337             :     }
   10338             :   // 'RegOrImmWithFP32InputMods' class
   10339             :   case MCK_RegOrImmWithFP32InputMods: {
   10340             :     DiagnosticPredicate DP(Operand.isRegOrImmWithFP32InputMods());
   10341       51458 :     if (DP.isMatch())
   10342             :       return MCTargetAsmParser::Match_Success;
   10343             :     break;
   10344             :     }
   10345             :   // 'SDWAWithFP32InputMods' class
   10346             :   case MCK_SDWAWithFP32InputMods: {
   10347             :     DiagnosticPredicate DP(Operand.isSDWAFP32Operand());
   10348       15422 :     if (DP.isMatch())
   10349             :       return MCTargetAsmParser::Match_Success;
   10350             :     break;
   10351             :     }
   10352             :   // 'RegOrImmWithFP64InputMods' class
   10353             :   case MCK_RegOrImmWithFP64InputMods: {
   10354             :     DiagnosticPredicate DP(Operand.isRegOrImmWithFP64InputMods());
   10355       26414 :     if (DP.isMatch())
   10356             :       return MCTargetAsmParser::Match_Success;
   10357             :     break;
   10358             :     }
   10359             :   // 'VRegWithFPInputMods' class
   10360        7251 :   case MCK_VRegWithFPInputMods: {
   10361        7251 :     DiagnosticPredicate DP(Operand.isVReg());
   10362        7251 :     if (DP.isMatch())
   10363             :       return MCTargetAsmParser::Match_Success;
   10364             :     break;
   10365             :     }
   10366             :   // 'GPRIdxMode' class
   10367             :   case MCK_GPRIdxMode: {
   10368             :     DiagnosticPredicate DP(Operand.isGPRIdxMode());
   10369          80 :     if (DP.isMatch())
   10370             :       return MCTargetAsmParser::Match_Success;
   10371             :     break;
   10372             :     }
   10373             :   // 'Imm' class
   10374         198 :   case MCK_Imm: {
   10375             :     DiagnosticPredicate DP(Operand.isImm());
   10376         198 :     if (DP.isMatch())
   10377             :       return MCTargetAsmParser::Match_Success;
   10378             :     break;
   10379             :     }
   10380             :   // 'SDWAWithInt16InputMods' class
   10381             :   case MCK_SDWAWithInt16InputMods: {
   10382             :     DiagnosticPredicate DP(Operand.isSDWAInt16Operand());
   10383       11426 :     if (DP.isMatch())
   10384             :       return MCTargetAsmParser::Match_Success;
   10385             :     break;
   10386             :     }
   10387             :   // 'RegOrImmWithInt32InputMods' class
   10388             :   case MCK_RegOrImmWithInt32InputMods: {
   10389             :     DiagnosticPredicate DP(Operand.isRegOrImmWithInt32InputMods());
   10390        1493 :     if (DP.isMatch())
   10391             :       return MCTargetAsmParser::Match_Success;
   10392             :     break;
   10393             :     }
   10394             :   // 'SDWAWithInt32InputMods' class
   10395             :   case MCK_SDWAWithInt32InputMods: {
   10396             :     DiagnosticPredicate DP(Operand.isSDWAInt32Operand());
   10397       18112 :     if (DP.isMatch())
   10398             :       return MCTargetAsmParser::Match_Success;
   10399             :     break;
   10400             :     }
   10401             :   // 'RegOrImmWithInt64InputMods' class
   10402             :   case MCK_RegOrImmWithInt64InputMods: {
   10403             :     DiagnosticPredicate DP(Operand.isRegOrImmWithInt64InputMods());
   10404           0 :     if (DP.isMatch())
   10405             :       return MCTargetAsmParser::Match_Success;
   10406             :     break;
   10407             :     }
   10408             :   // 'OpSelMods' class
   10409             :   case MCK_OpSelMods: {
   10410             :     DiagnosticPredicate DP(Operand.isRegOrImm());
   10411           0 :     if (DP.isMatch())
   10412             :       return MCTargetAsmParser::Match_Success;
   10413             :     break;
   10414             :     }
   10415             :   // 'VRegWithIntInputMods' class
   10416         100 :   case MCK_VRegWithIntInputMods: {
   10417         100 :     DiagnosticPredicate DP(Operand.isVReg());
   10418         100 :     if (DP.isMatch())
   10419             :       return MCTargetAsmParser::Match_Success;
   10420             :     break;
   10421             :     }
   10422             :   // 'InterpSlot' class
   10423             :   case MCK_InterpSlot: {
   10424             :     DiagnosticPredicate DP(Operand.isInterpSlot());
   10425         204 :     if (DP.isMatch())
   10426             :       return MCTargetAsmParser::Match_Success;
   10427             :     break;
   10428             :     }
   10429             :   // 'KImmFP16' class
   10430             :   case MCK_KImmFP16: {
   10431             :     DiagnosticPredicate DP(Operand.isKImmFP16());
   10432          74 :     if (DP.isMatch())
   10433             :       return MCTargetAsmParser::Match_Success;
   10434             :     break;
   10435             :     }
   10436             :   // 'KImmFP32' class
   10437             :   case MCK_KImmFP32: {
   10438             :     DiagnosticPredicate DP(Operand.isKImmFP32());
   10439         167 :     if (DP.isMatch())
   10440             :       return MCTargetAsmParser::Match_Success;
   10441             :     break;
   10442             :     }
   10443             :   // 'PackedFP16InputMods' class
   10444             :   case MCK_PackedFP16InputMods: {
   10445             :     DiagnosticPredicate DP(Operand.isRegOrImm());
   10446           0 :     if (DP.isMatch())
   10447             :       return MCTargetAsmParser::Match_Success;
   10448             :     break;
   10449             :     }
   10450             :   // 'PackedInt16InputMods' class
   10451             :   case MCK_PackedInt16InputMods: {
   10452             :     DiagnosticPredicate DP(Operand.isRegOrImm());
   10453           0 :     if (DP.isMatch())
   10454             :       return MCTargetAsmParser::Match_Success;
   10455             :     break;
   10456             :     }
   10457             :   // 'SWaitCnt' class
   10458         108 :   case MCK_SWaitCnt: {
   10459             :     DiagnosticPredicate DP(Operand.isSWaitCnt());
   10460         108 :     if (DP.isMatch())
   10461             :       return MCTargetAsmParser::Match_Success;
   10462             :     break;
   10463             :     }
   10464             :   // 'SendMsg' class
   10465             :   case MCK_SendMsg: {
   10466             :     DiagnosticPredicate DP(Operand.isSendMsg());
   10467          88 :     if (DP.isMatch())
   10468             :       return MCTargetAsmParser::Match_Success;
   10469             :     break;
   10470             :     }
   10471             :   // 'SoppBrTarget' class
   10472             :   case MCK_SoppBrTarget: {
   10473             :     DiagnosticPredicate DP(Operand.isSoppBrTarget());
   10474         130 :     if (DP.isMatch())
   10475             :       return MCTargetAsmParser::Match_Success;
   10476             :     break;
   10477             :     }
   10478             :   // 'Swizzle' class
   10479             :   case MCK_Swizzle: {
   10480             :     DiagnosticPredicate DP(Operand.isSwizzle());
   10481         314 :     if (DP.isMatch())
   10482             :       return MCTargetAsmParser::Match_Success;
   10483             :     break;
   10484             :     }
   10485             :   // 'VReg32OrOff' class
   10486        1832 :   case MCK_VReg32OrOff: {
   10487        1832 :     DiagnosticPredicate DP(Operand.isVReg32OrOff());
   10488        1832 :     if (DP.isMatch())
   10489             :       return MCTargetAsmParser::Match_Success;
   10490             :     break;
   10491             :     }
   10492             :   // 'SSrcB16' class
   10493           0 :   case MCK_SSrcB16: {
   10494           0 :     DiagnosticPredicate DP(Operand.isSSrcB16());
   10495           0 :     if (DP.isMatch())
   10496             :       return MCTargetAsmParser::Match_Success;
   10497             :     break;
   10498             :     }
   10499             :   // 'SSrcF16' class
   10500           0 :   case MCK_SSrcF16: {
   10501           0 :     DiagnosticPredicate DP(Operand.isSSrcF16());
   10502           0 :     if (DP.isMatch())
   10503             :       return MCTargetAsmParser::Match_Success;
   10504             :     break;
   10505             :     }
   10506             :   // 'SSrcB32' class
   10507       29487 :   case MCK_SSrcB32: {
   10508       29487 :     DiagnosticPredicate DP(Operand.isSSrcB32());
   10509       29487 :     if (DP.isMatch())
   10510             :       return MCTargetAsmParser::Match_Success;
   10511             :     break;
   10512             :     }
   10513             :   // 'SSrcF32' class
   10514           0 :   case MCK_SSrcF32: {
   10515           0 :     DiagnosticPredicate DP(Operand.isSSrcF32());
   10516           0 :     if (DP.isMatch())
   10517             :       return MCTargetAsmParser::Match_Success;
   10518             :     break;
   10519             :     }
   10520             :   // 'SSrcB64' class
   10521       10087 :   case MCK_SSrcB64: {
   10522       10087 :     DiagnosticPredicate DP(Operand.isSSrcB64());
   10523       10087 :     if (DP.isMatch())
   10524             :       return MCTargetAsmParser::Match_Success;
   10525             :     break;
   10526             :     }
   10527             :   // 'SSrcF64' class
   10528           0 :   case MCK_SSrcF64: {
   10529           0 :     DiagnosticPredicate DP(Operand.isSSrcF64());
   10530           0 :     if (DP.isMatch())
   10531             :       return MCTargetAsmParser::Match_Success;
   10532             :     break;
   10533             :     }
   10534             :   // 'SSrcV2B16' class
   10535             :   case MCK_SSrcV2B16: {
   10536             :     DiagnosticPredicate DP(Operand.isSSrcV2B16());
   10537             :     if (DP.isMatch())
   10538             :       return MCTargetAsmParser::Match_Success;
   10539             :     break;
   10540             :     }
   10541             :   // 'SSrcV2F16' class
   10542             :   case MCK_SSrcV2F16: {
   10543             :     DiagnosticPredicate DP(Operand.isSSrcV2F16());
   10544             :     if (DP.isMatch())
   10545             :       return MCTargetAsmParser::Match_Success;
   10546             :     break;
   10547             :     }
   10548             :   // 'SCSrcB16' class
   10549             :   case MCK_SCSrcB16: {
   10550             :     DiagnosticPredicate DP(Operand.isSCSrcB16());
   10551           0 :     if (DP.isMatch())
   10552             :       return MCTargetAsmParser::Match_Success;
   10553             :     break;
   10554             :     }
   10555             :   // 'SCSrcF16' class
   10556             :   case MCK_SCSrcF16: {
   10557             :     DiagnosticPredicate DP(Operand.isSCSrcF16());
   10558           0 :     if (DP.isMatch())
   10559             :       return MCTargetAsmParser::Match_Success;
   10560             :     break;
   10561             :     }
   10562             :   // 'SCSrcB32' class
   10563             :   case MCK_SCSrcB32: {
   10564             :     DiagnosticPredicate DP(Operand.isSCSrcB32());
   10565       10599 :     if (DP.isMatch())
   10566             :       return MCTargetAsmParser::Match_Success;
   10567             :     break;
   10568             :     }
   10569             :   // 'SCSrcF32' class
   10570             :   case MCK_SCSrcF32: {
   10571             :     DiagnosticPredicate DP(Operand.isSCSrcF32());
   10572           0 :     if (DP.isMatch())
   10573             :       return MCTargetAsmParser::Match_Success;
   10574             :     break;
   10575             :     }
   10576             :   // 'SCSrcB64' class
   10577             :   case MCK_SCSrcB64: {
   10578             :     DiagnosticPredicate DP(Operand.isSCSrcB64());
   10579         392 :     if (DP.isMatch())
   10580             :       return MCTargetAsmParser::Match_Success;
   10581             :     break;
   10582             :     }
   10583             :   // 'SCSrcF64' class
   10584             :   case MCK_SCSrcF64: {
   10585             :     DiagnosticPredicate DP(Operand.isSCSrcF64());
   10586           0 :     if (DP.isMatch())
   10587             :       return MCTargetAsmParser::Match_Success;
   10588             :     break;
   10589             :     }
   10590             :   // 'SCSrcV2B16' class
   10591             :   case MCK_SCSrcV2B16: {
   10592             :     DiagnosticPredicate DP(Operand.isSCSrcV2B16());
   10593           0 :     if (DP.isMatch())
   10594             :       return MCTargetAsmParser::Match_Success;
   10595             :     break;
   10596             :     }
   10597             :   // 'SCSrcV2F16' class
   10598             :   case MCK_SCSrcV2F16: {
   10599             :     DiagnosticPredicate DP(Operand.isSCSrcV2F16());
   10600           0 :     if (DP.isMatch())
   10601             :       return MCTargetAsmParser::Match_Success;
   10602             :     break;
   10603             :     }
   10604             :   // 'VSrcB16' class
   10605        3096 :   case MCK_VSrcB16: {
   10606        3096 :     DiagnosticPredicate DP(Operand.isVSrcB16());
   10607        3096 :     if (DP.isMatch())
   10608             :       return MCTargetAsmParser::Match_Success;
   10609             :     break;
   10610             :     }
   10611             :   // 'VSrcF16' class
   10612        4377 :   case MCK_VSrcF16: {
   10613        4377 :     DiagnosticPredicate DP(Operand.isVSrcF16());
   10614        4377 :     if (DP.isMatch())
   10615             :       return MCTargetAsmParser::Match_Success;
   10616             :     break;
   10617             :     }
   10618             :   // 'VSrcB32' class
   10619       12455 :   case MCK_VSrcB32: {
   10620       12455 :     DiagnosticPredicate DP(Operand.isVSrcB32());
   10621       12455 :     if (DP.isMatch())
   10622             :       return MCTargetAsmParser::Match_Success;
   10623             :     break;
   10624             :     }
   10625             :   // 'VSrcF32' class
   10626       12844 :   case MCK_VSrcF32: {
   10627       12844 :     DiagnosticPredicate DP(Operand.isVSrcF32());
   10628       12844 :     if (DP.isMatch())
   10629             :       return MCTargetAsmParser::Match_Success;
   10630             :     break;
   10631             :     }
   10632             :   // 'VSrcB64' class
   10633        3652 :   case MCK_VSrcB64: {
   10634        3652 :     DiagnosticPredicate DP(Operand.isVSrcB64());
   10635        3652 :     if (DP.isMatch())
   10636             :       return MCTargetAsmParser::Match_Success;
   10637             :     break;
   10638             :     }
   10639             :   // 'VSrcF64' class
   10640        6481 :   case MCK_VSrcF64: {
   10641        6481 :     DiagnosticPredicate DP(Operand.isVSrcF64());
   10642        6481 :     if (DP.isMatch())
   10643             :       return MCTargetAsmParser::Match_Success;
   10644             :     break;
   10645             :     }
   10646             :   // 'VSrcV2B16' class
   10647             :   case MCK_VSrcV2B16: {
   10648             :     DiagnosticPredicate DP(Operand.isVSrcV2B16());
   10649             :     if (DP.isMatch())
   10650             :       return MCTargetAsmParser::Match_Success;
   10651             :     break;
   10652             :     }
   10653             :   // 'VSrcV2F16' class
   10654             :   case MCK_VSrcV2F16: {
   10655             :     DiagnosticPredicate DP(Operand.isVSrcV2F16());
   10656             :     if (DP.isMatch())
   10657             :       return MCTargetAsmParser::Match_Success;
   10658             :     break;
   10659             :     }
   10660             :   // 'VCSrcB16' class
   10661             :   case MCK_VCSrcB16: {
   10662             :     DiagnosticPredicate DP(Operand.isVCSrcB16());
   10663       15112 :     if (DP.isMatch())
   10664             :       return MCTargetAsmParser::Match_Success;
   10665             :     break;
   10666             :     }
   10667             :   // 'VCSrcF16' class
   10668             :   case MCK_VCSrcF16: {
   10669             :     DiagnosticPredicate DP(Operand.isVCSrcF16());
   10670           0 :     if (DP.isMatch())
   10671             :       return MCTargetAsmParser::Match_Success;
   10672             :     break;
   10673             :     }
   10674             :   // 'VCSrcB32' class
   10675             :   case MCK_VCSrcB32: {
   10676             :     DiagnosticPredicate DP(Operand.isVCSrcB32());
   10677       63917 :     if (DP.isMatch())
   10678             :       return MCTargetAsmParser::Match_Success;
   10679             :     break;
   10680             :     }
   10681             :   // 'VCSrcF32' class
   10682             :   case MCK_VCSrcF32: {
   10683             :     DiagnosticPredicate DP(Operand.isVCSrcF32());
   10684        3099 :     if (DP.isMatch())
   10685             :       return MCTargetAsmParser::Match_Success;
   10686             :     break;
   10687             :     }
   10688             :   // 'VCSrcB64' class
   10689             :   case MCK_VCSrcB64: {
   10690             :     DiagnosticPredicate DP(Operand.isVCSrcB64());
   10691       16661 :     if (DP.isMatch())
   10692             :       return MCTargetAsmParser::Match_Success;
   10693             :     break;
   10694             :     }
   10695             :   // 'VCSrcF64' class
   10696             :   case MCK_VCSrcF64: {
   10697             :     DiagnosticPredicate DP(Operand.isVCSrcF64());
   10698         864 :     if (DP.isMatch())
   10699             :       return MCTargetAsmParser::Match_Success;
   10700             :     break;
   10701             :     }
   10702             :   // 'VCSrcV2B16' class
   10703             :   case MCK_VCSrcV2B16: {
   10704             :     DiagnosticPredicate DP(Operand.isVCSrcV2B16());
   10705        1766 :     if (DP.isMatch())
   10706             :       return MCTargetAsmParser::Match_Success;
   10707             :     break;
   10708             :     }
   10709             :   // 'VCSrcV2F16' class
   10710             :   case MCK_VCSrcV2F16: {
   10711             :     DiagnosticPredicate DP(Operand.isVCSrcV2F16());
   10712         994 :     if (DP.isMatch())
   10713             :       return MCTargetAsmParser::Match_Success;
   10714             :     break;
   10715             :     }
   10716             :   // 'ImmOffen' class
   10717             :   case MCK_ImmOffen: {
   10718             :     DiagnosticPredicate DP(Operand.isOffen());
   10719           0 :     if (DP.isMatch())
   10720             :       return MCTargetAsmParser::Match_Success;
   10721             :     break;
   10722             :     }
   10723             :   // 'ImmIdxen' class
   10724             :   case MCK_ImmIdxen: {
   10725             :     DiagnosticPredicate DP(Operand.isIdxen());
   10726           0 :     if (DP.isMatch())
   10727             :       return MCTargetAsmParser::Match_Success;
   10728             :     break;
   10729             :     }
   10730             :   // 'ImmAddr64' class
   10731             :   case MCK_ImmAddr64: {
   10732             :     DiagnosticPredicate DP(Operand.isAddr64());
   10733           0 :     if (DP.isMatch())
   10734             :       return MCTargetAsmParser::Match_Success;
   10735             :     break;
   10736             :     }
   10737             :   // 'ImmOffsetU12' class
   10738             :   case MCK_ImmOffsetU12: {
   10739             :     DiagnosticPredicate DP(Operand.isOffsetU12());
   10740        2257 :     if (DP.isMatch())
   10741             :       return MCTargetAsmParser::Match_Success;
   10742             :     break;
   10743             :     }
   10744             :   // 'ImmOffsetS13' class
   10745             :   case MCK_ImmOffsetS13: {
   10746             :     DiagnosticPredicate DP(Operand.isOffsetS13());
   10747         856 :     if (DP.isMatch())
   10748             :       return MCTargetAsmParser::Match_Success;
   10749             :     break;
   10750             :     }
   10751             :   // 'ImmOffset' class
   10752             :   case MCK_ImmOffset: {
   10753             :     DiagnosticPredicate DP(Operand.isOffset());
   10754       13375 :     if (DP.isMatch())
   10755             :       return MCTargetAsmParser::Match_Success;
   10756             :     break;
   10757             :     }
   10758             :   // 'ImmOffset0' class
   10759             :   case MCK_ImmOffset0: {
   10760             :     DiagnosticPredicate DP(Operand.isOffset0());
   10761        1020 :     if (DP.isMatch())
   10762             :       return MCTargetAsmParser::Match_Success;
   10763             :     break;
   10764             :     }
   10765             :   // 'ImmOffset1' class
   10766             :   case MCK_ImmOffset1: {
   10767             :     DiagnosticPredicate DP(Operand.isOffset1());
   10768         920 :     if (DP.isMatch())
   10769             :       return MCTargetAsmParser::Match_Success;
   10770             :     break;
   10771             :     }
   10772             :   // 'ImmGDS' class
   10773             :   case MCK_ImmGDS: {
   10774             :     DiagnosticPredicate DP(Operand.isGDS());
   10775         968 :     if (DP.isMatch())
   10776             :       return MCTargetAsmParser::Match_Success;
   10777             :     break;
   10778             :     }
   10779             :   // 'ImmOModSI' class
   10780             :   case MCK_ImmOModSI: {
   10781             :     DiagnosticPredicate DP(Operand.isOModSI());
   10782        7693 :     if (DP.isMatch())
   10783             :       return MCTargetAsmParser::Match_Success;
   10784             :     break;
   10785             :     }
   10786             :   // 'ImmClampSI' class
   10787             :   case MCK_ImmClampSI: {
   10788             :     DiagnosticPredicate DP(Operand.isClampSI());
   10789       28219 :     if (DP.isMatch())
   10790             :       return MCTargetAsmParser::Match_Success;
   10791             :     break;
   10792             :     }
   10793             :   // 'ImmHigh' class
   10794             :   case MCK_ImmHigh: {
   10795             :     DiagnosticPredicate DP(Operand.isHigh());
   10796          78 :     if (DP.isMatch())
   10797             :       return MCTargetAsmParser::Match_Success;
   10798             :     break;
   10799             :     }
   10800             :   // 'ImmGLC' class
   10801             :   case MCK_ImmGLC: {
   10802             :     DiagnosticPredicate DP(Operand.isGLC());
   10803        3938 :     if (DP.isMatch())
   10804             :       return MCTargetAsmParser::Match_Success;
   10805             :     break;
   10806             :     }
   10807             :   // 'ImmSLC' class
   10808             :   case MCK_ImmSLC: {
   10809             :     DiagnosticPredicate DP(Operand.isSLC());
   10810        4067 :     if (DP.isMatch())
   10811             :       return MCTargetAsmParser::Match_Success;
   10812             :     break;
   10813             :     }
   10814             :   // 'ImmTFE' class
   10815             :   case MCK_ImmTFE: {
   10816             :     DiagnosticPredicate DP(Operand.isTFE());
   10817        1335 :     if (DP.isMatch())
   10818             :       return MCTargetAsmParser::Match_Success;
   10819             :     break;
   10820             :     }
   10821             :   // 'ImmUNorm' class
   10822             :   case MCK_ImmUNorm: {
   10823             :     DiagnosticPredicate DP(Operand.isUNorm());
   10824        2610 :     if (DP.isMatch())
   10825             :       return MCTargetAsmParser::Match_Success;
   10826             :     break;
   10827             :     }
   10828             :   // 'ImmDA' class
   10829             :   case MCK_ImmDA: {
   10830             :     DiagnosticPredicate DP(Operand.isDA());
   10831         623 :     if (DP.isMatch())
   10832             :       return MCTargetAsmParser::Match_Success;
   10833             :     break;
   10834             :     }
   10835             :   // 'ImmR128A16' class
   10836             :   case MCK_ImmR128A16: {
   10837             :     DiagnosticPredicate DP(Operand.isR128A16());
   10838        1039 :     if (DP.isMatch())
   10839             :       return MCTargetAsmParser::Match_Success;
   10840             :     break;
   10841             :     }
   10842             :   // 'ImmD16' class
   10843             :   case MCK_ImmD16: {
   10844             :     DiagnosticPredicate DP(Operand.isD16());
   10845         312 :     if (DP.isMatch())
   10846             :       return MCTargetAsmParser::Match_Success;
   10847             :     break;
   10848             :     }
   10849             :   // 'ImmLWE' class
   10850             :   case MCK_ImmLWE: {
   10851             :     DiagnosticPredicate DP(Operand.isLWE());
   10852         868 :     if (DP.isMatch())
   10853             :       return MCTargetAsmParser::Match_Success;
   10854             :     break;
   10855             :     }
   10856             :   // 'ImmExpCompr' class
   10857             :   case MCK_ImmExpCompr: {
   10858             :     DiagnosticPredicate DP(Operand.isExpCompr());
   10859         105 :     if (DP.isMatch())
   10860             :       return MCTargetAsmParser::Match_Success;
   10861             :     break;
   10862             :     }
   10863             :   // 'ImmExpVM' class
   10864             :   case MCK_ImmExpVM: {
   10865             :     DiagnosticPredicate DP(Operand.isExpVM());
   10866          89 :     if (DP.isMatch())
   10867             :       return MCTargetAsmParser::Match_Success;
   10868             :     break;
   10869             :     }
   10870             :   // 'ImmFORMAT' class
   10871             :   case MCK_ImmFORMAT: {
   10872             :     DiagnosticPredicate DP(Operand.isFORMAT());
   10873          96 :     if (DP.isMatch())
   10874             :       return MCTargetAsmParser::Match_Success;
   10875             :     break;
   10876             :     }
   10877             :   // 'ImmDMask' class
   10878             :   case MCK_ImmDMask: {
   10879             :     DiagnosticPredicate DP(Operand.isDMask());
   10880        4698 :     if (DP.isMatch())
   10881             :       return MCTargetAsmParser::Match_Success;
   10882             :     break;
   10883             :     }
   10884             :   // 'ImmDPPCtrl' class
   10885        9747 :   case MCK_ImmDPPCtrl: {
   10886        9747 :     DiagnosticPredicate DP(Operand.isDPPCtrl());
   10887        9747 :     if (DP.isMatch())
   10888             :       return MCTargetAsmParser::Match_Success;
   10889             :     break;
   10890             :     }
   10891             :   // 'ImmRowMask' class
   10892             :   case MCK_ImmRowMask: {
   10893             :     DiagnosticPredicate DP(Operand.isRowMask());
   10894        9497 :     if (DP.isMatch())
   10895             :       return MCTargetAsmParser::Match_Success;
   10896             :     break;
   10897             :     }
   10898             :   // 'ImmBankMask' class
   10899             :   case MCK_ImmBankMask: {
   10900             :     DiagnosticPredicate DP(Operand.isBankMask());
   10901        9180 :     if (DP.isMatch())
   10902             :       return MCTargetAsmParser::Match_Success;
   10903             :     break;
   10904             :     }
   10905             :   // 'ImmBoundCtrl' class
   10906             :   case MCK_ImmBoundCtrl: {
   10907             :     DiagnosticPredicate DP(Operand.isBoundCtrl());
   10908         755 :     if (DP.isMatch())
   10909             :       return MCTargetAsmParser::Match_Success;
   10910             :     break;
   10911             :     }
   10912             :   // 'ImmSDWADstSel' class
   10913             :   case MCK_ImmSDWADstSel: {
   10914             :     DiagnosticPredicate DP(Operand.isSDWADstSel());
   10915       20552 :     if (DP.isMatch())
   10916             :       return MCTargetAsmParser::Match_Success;
   10917             :     break;
   10918             :     }
   10919             :   // 'ImmSDWASrc0Sel' class
   10920             :   case MCK_ImmSDWASrc0Sel: {
   10921             :     DiagnosticPredicate DP(Operand.isSDWASrc0Sel());
   10922       33139 :     if (DP.isMatch())
   10923             :       return MCTargetAsmParser::Match_Success;
   10924             :     break;
   10925             :     }
   10926             :   // 'ImmSDWASrc1Sel' class
   10927             :   case MCK_ImmSDWASrc1Sel: {
   10928             :     DiagnosticPredicate DP(Operand.isSDWASrc1Sel());
   10929       22357 :     if (DP.isMatch())
   10930             :       return MCTargetAsmParser::Match_Success;
   10931             :     break;
   10932             :     }
   10933             :   // 'ImmSDWADstUnused' class
   10934             :   case MCK_ImmSDWADstUnused: {
   10935             :     DiagnosticPredicate DP(Operand.isSDWADstUnused());
   10936       20546 :     if (DP.isMatch())
   10937             :       return MCTargetAsmParser::Match_Success;
   10938             :     break;
   10939             :     }
   10940             :   // 'ImmOpSel' class
   10941             :   case MCK_ImmOpSel: {
   10942             :     DiagnosticPredicate DP(Operand.isOpSel());
   10943        1088 :     if (DP.isMatch())
   10944             :       return MCTargetAsmParser::Match_Success;
   10945             :     break;
   10946             :     }
   10947             :   // 'ImmOpSelHi' class
   10948             :   case MCK_ImmOpSelHi: {
   10949             :     DiagnosticPredicate DP(Operand.isOpSelHi());
   10950         517 :     if (DP.isMatch())
   10951             :       return MCTargetAsmParser::Match_Success;
   10952             :     break;
   10953             :     }
   10954             :   // 'ImmNegLo' class
   10955             :   case MCK_ImmNegLo: {
   10956             :     DiagnosticPredicate DP(Operand.isNegLo());
   10957         169 :     if (DP.isMatch())
   10958             :       return MCTargetAsmParser::Match_Success;
   10959             :     break;
   10960             :     }
   10961             :   // 'ImmNegHi' class
   10962             :   case MCK_ImmNegHi: {
   10963             :     DiagnosticPredicate DP(Operand.isNegHi());
   10964         131 :     if (DP.isMatch())
   10965             :       return MCTargetAsmParser::Match_Success;
   10966             :     break;
   10967             :     }
   10968             :   // 'ImmHwreg' class
   10969             :   case MCK_ImmHwreg: {
   10970             :     DiagnosticPredicate DP(Operand.isHwreg());
   10971         353 :     if (DP.isMatch())
   10972             :       return MCTargetAsmParser::Match_Success;
   10973             :     break;
   10974             :     }
   10975             :   // 'ImmExpTgt' class
   10976             :   case MCK_ImmExpTgt: {
   10977             :     DiagnosticPredicate DP(Operand.isExpTgt());
   10978         518 :     if (DP.isMatch())
   10979             :       return MCTargetAsmParser::Match_Success;
   10980             :     break;
   10981             :     }
   10982             :   // 'ImmSMRDOffset8' class
   10983             :   case MCK_ImmSMRDOffset8: {
   10984             :     DiagnosticPredicate DP(Operand.isSMRDOffset8());
   10985         186 :     if (DP.isMatch())
   10986             :       return MCTargetAsmParser::Match_Success;
   10987             :     break;
   10988             :     }
   10989             :   // 'ImmSMRDOffset20' class
   10990             :   case MCK_ImmSMRDOffset20: {
   10991             :     DiagnosticPredicate DP(Operand.isSMRDOffset20());
   10992        1302 :     if (DP.isMatch())
   10993             :       return MCTargetAsmParser::Match_Success;
   10994             :     break;
   10995             :     }
   10996             :   // 'ImmSMRDLiteralOffset' class
   10997             :   case MCK_ImmSMRDLiteralOffset: {
   10998             :     DiagnosticPredicate DP(Operand.isSMRDLiteralOffset());
   10999          44 :     if (DP.isMatch())
   11000             :       return MCTargetAsmParser::Match_Success;
   11001             :     break;
   11002             :     }
   11003             :   // 'S16Imm' class
   11004             :   case MCK_S16Imm: {
   11005             :     DiagnosticPredicate DP(Operand.isS16Imm());
   11006        1077 :     if (DP.isMatch())
   11007             :       return MCTargetAsmParser::Match_Success;
   11008             :     break;
   11009             :     }
   11010             :   // 'U16Imm' class
   11011             :   case MCK_U16Imm: {
   11012             :     DiagnosticPredicate DP(Operand.isU16Imm());
   11013         604 :     if (DP.isMatch())
   11014             :       return MCTargetAsmParser::Match_Success;
   11015             :     break;
   11016             :     }
   11017             :   } // end switch (Kind)
   11018             : 
   11019             :   if (Operand.isReg()) {
   11020             :     MatchClassKind OpKind;
   11021             :     switch (Operand.getReg()) {
   11022             :     default: OpKind = InvalidMatchClass; break;
   11023             :     case AMDGPU::VCC_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11024             :     case AMDGPU::VCC_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11025             :     case AMDGPU::PRIVATE_RSRC_REG: OpKind = MCK_Pseudo_SReg_128; break;
   11026             :     case AMDGPU::FP_REG: OpKind = MCK_Pseudo_SReg_32; break;
   11027             :     case AMDGPU::SP_REG: OpKind = MCK_Pseudo_SReg_32; break;
   11028             :     case AMDGPU::SCRATCH_WAVE_OFFSET_REG: OpKind = MCK_Pseudo_SReg_32; break;
   11029             :     case AMDGPU::VCC: OpKind = MCK_VCC; break;
   11030             :     case AMDGPU::EXEC_LO: OpKind = MCK_Reg4; break;
   11031             :     case AMDGPU::EXEC_HI: OpKind = MCK_SReg_32_XM0; break;
   11032             :     case AMDGPU::EXEC: OpKind = MCK_SReg_64; break;
   11033             :     case AMDGPU::SCC: OpKind = MCK_SCC_CLASS; break;
   11034             :     case AMDGPU::M0: OpKind = MCK_M0_CLASS; break;
   11035             :     case AMDGPU::SRC_SHARED_BASE: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11036             :     case AMDGPU::SRC_SHARED_LIMIT: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11037             :     case AMDGPU::SRC_PRIVATE_BASE: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11038             :     case AMDGPU::SRC_PRIVATE_LIMIT: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11039             :     case AMDGPU::XNACK_MASK_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11040             :     case AMDGPU::XNACK_MASK_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11041             :     case AMDGPU::XNACK_MASK: OpKind = MCK_SReg_64_XEXEC; break;
   11042             :     case AMDGPU::TBA_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11043             :     case AMDGPU::TBA_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11044             :     case AMDGPU::TBA: OpKind = MCK_SReg_64_XEXEC; break;
   11045             :     case AMDGPU::TMA_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11046             :     case AMDGPU::TMA_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11047             :     case AMDGPU::TMA: OpKind = MCK_SReg_64_XEXEC; break;
   11048             :     case AMDGPU::TTMP0: OpKind = MCK_TTMP_32; break;
   11049             :     case AMDGPU::TTMP1: OpKind = MCK_TTMP_32; break;
   11050             :     case AMDGPU::TTMP2: OpKind = MCK_TTMP_32; break;
   11051             :     case AMDGPU::TTMP3: OpKind = MCK_TTMP_32; break;
   11052             :     case AMDGPU::TTMP4: OpKind = MCK_TTMP_32; break;
   11053             :     case AMDGPU::TTMP5: OpKind = MCK_TTMP_32; break;
   11054             :     case AMDGPU::TTMP6: OpKind = MCK_TTMP_32; break;
   11055             :     case AMDGPU::TTMP7: OpKind = MCK_TTMP_32; break;
   11056             :     case AMDGPU::TTMP8: OpKind = MCK_TTMP_32; break;
   11057             :     case AMDGPU::TTMP9: OpKind = MCK_TTMP_32; break;
   11058             :     case AMDGPU::TTMP10: OpKind = MCK_TTMP_32; break;
   11059             :     case AMDGPU::TTMP11: OpKind = MCK_TTMP_32; break;
   11060             :     case AMDGPU::TTMP12: OpKind = MCK_TTMP_32; break;
   11061             :     case AMDGPU::TTMP13: OpKind = MCK_TTMP_32; break;
   11062             :     case AMDGPU::TTMP14: OpKind = MCK_TTMP_32; break;
   11063             :     case AMDGPU::TTMP15: OpKind = MCK_TTMP_32; break;
   11064             :     case AMDGPU::FLAT_SCR_LO: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11065             :     case AMDGPU::FLAT_SCR_HI: OpKind = MCK_SReg_32_XM0_XEXEC; break;
   11066             :     case AMDGPU::FLAT_SCR: OpKind = MCK_SReg_64_XEXEC; break;
   11067             :     case AMDGPU::SGPR0: OpKind = MCK_SGPR_32; break;
   11068             :     case AMDGPU::SGPR1: OpKind = MCK_SGPR_32; break;
   11069             :     case AMDGPU::SGPR2: OpKind = MCK_SGPR_32; break;
   11070             :     case AMDGPU::SGPR3: OpKind = MCK_SGPR_32; break;
   11071             :     case AMDGPU::SGPR4: OpKind = MCK_SGPR_32; break;
   11072             :     case AMDGPU::SGPR5: OpKind = MCK_SGPR_32; break;
   11073             :     case AMDGPU::SGPR6: OpKind = MCK_SGPR_32; break;
   11074             :     case AMDGPU::SGPR7: OpKind = MCK_SGPR_32; break;
   11075             :     case AMDGPU::SGPR8: OpKind = MCK_SGPR_32; break;
   11076             :     case AMDGPU::SGPR9: OpKind = MCK_SGPR_32; break;
   11077             :     case AMDGPU::SGPR10: OpKind = MCK_SGPR_32; break;
   11078             :     case AMDGPU::SGPR11: OpKind = MCK_SGPR_32; break;
   11079             :     case AMDGPU::SGPR12: OpKind = MCK_SGPR_32; break;
   11080             :     case AMDGPU::SGPR13: OpKind = MCK_SGPR_32; break;
   11081             :     case AMDGPU::SGPR14: OpKind = MCK_SGPR_32; break;
   11082             :     case AMDGPU::SGPR15: OpKind = MCK_SGPR_32; break;
   11083             :     case AMDGPU::SGPR16: OpKind = MCK_SGPR_32; break;
   11084             :     case AMDGPU::SGPR17: OpKind = MCK_SGPR_32; break;
   11085             :     case AMDGPU::SGPR18: OpKind = MCK_SGPR_32; break;
   11086             :     case AMDGPU::SGPR19: OpKind = MCK_SGPR_32; break;
   11087             :     case AMDGPU::SGPR20: OpKind = MCK_SGPR_32; break;
   11088             :     case AMDGPU::SGPR21: OpKind = MCK_SGPR_32; break;
   11089             :     case AMDGPU::SGPR22: OpKind = MCK_SGPR_32; break;
   11090             :     case AMDGPU::SGPR23: OpKind = MCK_SGPR_32; break;
   11091             :     case AMDGPU::SGPR24: OpKind = MCK_SGPR_32; break;
   11092             :     case AMDGPU::SGPR25: OpKind = MCK_SGPR_32; break;
   11093             :     case AMDGPU::SGPR26: OpKind = MCK_SGPR_32; break;
   11094             :     case AMDGPU::SGPR27: OpKind = MCK_SGPR_32; break;
   11095             :     case AMDGPU::SGPR28: OpKind = MCK_SGPR_32; break;
   11096             :     case AMDGPU::SGPR29: OpKind = MCK_SGPR_32; break;
   11097             :     case AMDGPU::SGPR30: OpKind = MCK_SGPR_32; break;
   11098             :     case AMDGPU::SGPR31: OpKind = MCK_SGPR_32; break;
   11099             :     case AMDGPU::SGPR32: OpKind = MCK_SGPR_32; break;
   11100             :     case AMDGPU::SGPR33: OpKind = MCK_SGPR_32; break;
   11101             :     case AMDGPU::SGPR34: OpKind = MCK_SGPR_32; break;
   11102             :     case AMDGPU::SGPR35: OpKind = MCK_SGPR_32; break;
   11103             :     case AMDGPU::SGPR36: OpKind = MCK_SGPR_32; break;
   11104             :     case AMDGPU::SGPR37: OpKind = MCK_SGPR_32; break;
   11105             :     case AMDGPU::SGPR38: OpKind = MCK_SGPR_32; break;
   11106             :     case AMDGPU::SGPR39: OpKind = MCK_SGPR_32; break;
   11107             :     case AMDGPU::SGPR40: OpKind = MCK_SGPR_32; break;
   11108             :     case AMDGPU::SGPR41: OpKind = MCK_SGPR_32; break;
   11109             :     case AMDGPU::SGPR42: OpKind = MCK_SGPR_32; break;
   11110             :     case AMDGPU::SGPR43: OpKind = MCK_SGPR_32; break;
   11111             :     case AMDGPU::SGPR44: OpKind = MCK_SGPR_32; break;
   11112             :     case AMDGPU::SGPR45: OpKind = MCK_SGPR_32; break;
   11113             :     case AMDGPU::SGPR46: OpKind = MCK_SGPR_32; break;
   11114             :     case AMDGPU::SGPR47: OpKind = MCK_SGPR_32; break;
   11115             :     case AMDGPU::SGPR48: OpKind = MCK_SGPR_32; break;
   11116             :     case AMDGPU::SGPR49: OpKind = MCK_SGPR_32; break;
   11117             :     case AMDGPU::SGPR50: OpKind = MCK_SGPR_32; break;
   11118             :     case AMDGPU::SGPR51: OpKind = MCK_SGPR_32; break;
   11119             :     case AMDGPU::SGPR52: OpKind = MCK_SGPR_32; break;
   11120             :     case AMDGPU::SGPR53: OpKind = MCK_SGPR_32; break;
   11121             :     case AMDGPU::SGPR54: OpKind = MCK_SGPR_32; break;
   11122             :     case AMDGPU::SGPR55: OpKind = MCK_SGPR_32; break;
   11123             :     case AMDGPU::SGPR56: OpKind = MCK_SGPR_32; break;
   11124             :     case AMDGPU::SGPR57: OpKind = MCK_SGPR_32; break;
   11125             :     case AMDGPU::SGPR58: OpKind = MCK_SGPR_32; break;
   11126             :     case AMDGPU::SGPR59: OpKind = MCK_SGPR_32; break;
   11127             :     case AMDGPU::SGPR60: OpKind = MCK_SGPR_32; break;
   11128             :     case AMDGPU::SGPR61: OpKind = MCK_SGPR_32; break;
   11129             :     case AMDGPU::SGPR62: OpKind = MCK_SGPR_32; break;
   11130             :     case AMDGPU::SGPR63: OpKind = MCK_SGPR_32; break;
   11131             :     case AMDGPU::SGPR64: OpKind = MCK_SGPR_32; break;
   11132             :     case AMDGPU::SGPR65: OpKind = MCK_SGPR_32; break;
   11133             :     case AMDGPU::SGPR66: OpKind = MCK_SGPR_32; break;
   11134             :     case AMDGPU::SGPR67: OpKind = MCK_SGPR_32; break;
   11135             :     case AMDGPU::SGPR68: OpKind = MCK_SGPR_32; break;
   11136             :     case AMDGPU::SGPR69: OpKind = MCK_SGPR_32; break;
   11137             :     case AMDGPU::SGPR70: OpKind = MCK_SGPR_32; break;
   11138             :     case AMDGPU::SGPR71: OpKind = MCK_SGPR_32; break;
   11139             :     case AMDGPU::SGPR72: OpKind = MCK_SGPR_32; break;
   11140             :     case AMDGPU::SGPR73: OpKind = MCK_SGPR_32; break;
   11141             :     case AMDGPU::SGPR74: OpKind = MCK_SGPR_32; break;
   11142             :     case AMDGPU::SGPR75: OpKind = MCK_SGPR_32; break;
   11143             :     case AMDGPU::SGPR76: OpKind = MCK_SGPR_32; break;
   11144             :     case AMDGPU::SGPR77: OpKind = MCK_SGPR_32; break;
   11145             :     case AMDGPU::SGPR78: OpKind = MCK_SGPR_32; break;
   11146             :     case AMDGPU::SGPR79: OpKind = MCK_SGPR_32; break;
   11147             :     case AMDGPU::SGPR80: OpKind = MCK_SGPR_32; break;
   11148             :     case AMDGPU::SGPR81: OpKind = MCK_SGPR_32; break;
   11149             :     case AMDGPU::SGPR82: OpKind = MCK_SGPR_32; break;
   11150             :     case AMDGPU::SGPR83: OpKind = MCK_SGPR_32; break;
   11151             :     case AMDGPU::SGPR84: OpKind = MCK_SGPR_32; break;
   11152             :     case AMDGPU::SGPR85: OpKind = MCK_SGPR_32; break;
   11153             :     case AMDGPU::SGPR86: OpKind = MCK_SGPR_32; break;
   11154             :     case AMDGPU::SGPR87: OpKind = MCK_SGPR_32; break;
   11155             :     case AMDGPU::SGPR88: OpKind = MCK_SGPR_32; break;
   11156             :     case AMDGPU::SGPR89: OpKind = MCK_SGPR_32; break;
   11157             :     case AMDGPU::SGPR90: OpKind = MCK_SGPR_32; break;
   11158             :     case AMDGPU::SGPR91: OpKind = MCK_SGPR_32; break;
   11159             :     case AMDGPU::SGPR92: OpKind = MCK_SGPR_32; break;
   11160             :     case AMDGPU::SGPR93: OpKind = MCK_SGPR_32; break;
   11161             :     case AMDGPU::SGPR94: OpKind = MCK_SGPR_32; break;
   11162             :     case AMDGPU::SGPR95: OpKind = MCK_SGPR_32; break;
   11163             :     case AMDGPU::SGPR96: OpKind = MCK_SGPR_32; break;
   11164             :     case AMDGPU::SGPR97: OpKind = MCK_SGPR_32; break;
   11165             :     case AMDGPU::SGPR98: OpKind = MCK_SGPR_32; break;
   11166             :     case AMDGPU::SGPR99: OpKind = MCK_SGPR_32; break;
   11167             :     case AMDGPU::SGPR100: OpKind = MCK_SGPR_32; break;
   11168             :     case AMDGPU::SGPR101: OpKind = MCK_SGPR_32; break;
   11169             :     case AMDGPU::SGPR102: OpKind = MCK_SGPR_32; break;
   11170             :     case AMDGPU::SGPR103: OpKind = MCK_SGPR_32; break;
   11171             :     case AMDGPU::VGPR0: OpKind = MCK_VGPR_32; break;
   11172             :     case AMDGPU::VGPR1: OpKind = MCK_VGPR_32; break;
   11173             :     case AMDGPU::VGPR2: OpKind = MCK_VGPR_32; break;
   11174             :     case AMDGPU::VGPR3: OpKind = MCK_VGPR_32; break;
   11175             :     case AMDGPU::VGPR4: OpKind = MCK_VGPR_32; break;
   11176             :     case AMDGPU::VGPR5: OpKind = MCK_VGPR_32; break;
   11177             :     case AMDGPU::VGPR6: OpKind = MCK_VGPR_32; break;
   11178             :     case AMDGPU::VGPR7: OpKind = MCK_VGPR_32; break;
   11179             :     case AMDGPU::VGPR8: OpKind = MCK_VGPR_32; break;
   11180             :     case AMDGPU::VGPR9: OpKind = MCK_VGPR_32; break;
   11181             :     case AMDGPU::VGPR10: OpKind = MCK_VGPR_32; break;
   11182             :     case AMDGPU::VGPR11: OpKind = MCK_VGPR_32; break;
   11183             :     case AMDGPU::VGPR12: OpKind = MCK_VGPR_32; break;
   11184             :     case AMDGPU::VGPR13: OpKind = MCK_VGPR_32; break;
   11185             :     case AMDGPU::VGPR14: OpKind = MCK_VGPR_32; break;
   11186             :     case AMDGPU::VGPR15: OpKind = MCK_VGPR_32; break;
   11187             :     case AMDGPU::VGPR16: OpKind = MCK_VGPR_32; break;
   11188             :     case AMDGPU::VGPR17: OpKind = MCK_VGPR_32; break;
   11189             :     case AMDGPU::VGPR18: OpKind = MCK_VGPR_32; break;
   11190             :     case AMDGPU::VGPR19: OpKind = MCK_VGPR_32; break;
   11191             :     case AMDGPU::VGPR20: OpKind = MCK_VGPR_32; break;
   11192             :     case AMDGPU::VGPR21: OpKind = MCK_VGPR_32; break;
   11193             :     case AMDGPU::VGPR22: OpKind = MCK_VGPR_32; break;
   11194             :     case AMDGPU::VGPR23: OpKind = MCK_VGPR_32; break;
   11195             :     case AMDGPU::VGPR24: OpKind = MCK_VGPR_32; break;
   11196             :     case AMDGPU::VGPR25: OpKind = MCK_VGPR_32; break;
   11197             :     case AMDGPU::VGPR26: OpKind = MCK_VGPR_32; break;
   11198             :     case AMDGPU::VGPR27: OpKind = MCK_VGPR_32; break;
   11199             :     case AMDGPU::VGPR28: OpKind = MCK_VGPR_32; break;
   11200             :     case AMDGPU::VGPR29: OpKind = MCK_VGPR_32; break;
   11201             :     case AMDGPU::VGPR30: OpKind = MCK_VGPR_32; break;
   11202             :     case AMDGPU::VGPR31: OpKind = MCK_VGPR_32; break;
   11203             :     case AMDGPU::VGPR32: OpKind = MCK_VGPR_32; break;
   11204             :     case AMDGPU::VGPR33: OpKind = MCK_VGPR_32; break;
   11205             :     case AMDGPU::VGPR34: OpKind = MCK_VGPR_32; break;
   11206             :     case AMDGPU::VGPR35: OpKind = MCK_VGPR_32; break;
   11207             :     case AMDGPU::VGPR36: OpKind = MCK_VGPR_32; break;
   11208             :     case AMDGPU::VGPR37: OpKind = MCK_VGPR_32; break;
   11209             :     case AMDGPU::VGPR38: OpKind = MCK_VGPR_32; break;
   11210             :     case AMDGPU::VGPR39: OpKind = MCK_VGPR_32; break;
   11211             :     case AMDGPU::VGPR40: OpKind = MCK_VGPR_32; break;
   11212             :     case AMDGPU::VGPR41: OpKind = MCK_VGPR_32; break;
   11213             :     case AMDGPU::VGPR42: OpKind = MCK_VGPR_32; break;
   11214             :     case AMDGPU::VGPR43: OpKind = MCK_VGPR_32; break;
   11215             :     case AMDGPU::VGPR44: OpKind = MCK_VGPR_32; break;
   11216             :     case AMDGPU::VGPR45: OpKind = MCK_VGPR_32; break;
   11217             :     case AMDGPU::VGPR46: OpKind = MCK_VGPR_32; break;
   11218             :     case AMDGPU::VGPR47: OpKind = MCK_VGPR_32; break;
   11219             :     case AMDGPU::VGPR48: OpKind = MCK_VGPR_32; break;
   11220             :     case AMDGPU::VGPR49: OpKind = MCK_VGPR_32; break;
   11221             :     case AMDGPU::VGPR50: OpKind = MCK_VGPR_32; break;
   11222             :     case AMDGPU::VGPR51: OpKind = MCK_VGPR_32; break;
   11223             :     case AMDGPU::VGPR52: OpKind = MCK_VGPR_32; break;
   11224             :     case AMDGPU::VGPR53: OpKind = MCK_VGPR_32; break;
   11225             :     case AMDGPU::VGPR54: OpKind = MCK_VGPR_32; break;
   11226             :     case AMDGPU::VGPR55: OpKind = MCK_VGPR_32; break;
   11227             :     case AMDGPU::VGPR56: OpKind = MCK_VGPR_32; break;
   11228             :     case AMDGPU::VGPR57: OpKind = MCK_VGPR_32; break;
   11229             :     case AMDGPU::VGPR58: OpKind = MCK_VGPR_32; break;
   11230             :     case AMDGPU::VGPR59: OpKind = MCK_VGPR_32; break;
   11231             :     case AMDGPU::VGPR60: OpKind = MCK_VGPR_32; break;
   11232             :     case AMDGPU::VGPR61: OpKind = MCK_VGPR_32; break;
   11233             :     case AMDGPU::VGPR62: OpKind = MCK_VGPR_32; break;
   11234             :     case AMDGPU::VGPR63: OpKind = MCK_VGPR_32; break;
   11235             :     case AMDGPU::VGPR64: OpKind = MCK_VGPR_32; break;
   11236             :     case AMDGPU::VGPR65: OpKind = MCK_VGPR_32; break;
   11237             :     case AMDGPU::VGPR66: OpKind = MCK_VGPR_32; break;
   11238             :     case AMDGPU::VGPR67: OpKind = MCK_VGPR_32; break;
   11239             :     case AMDGPU::VGPR68: OpKind = MCK_VGPR_32; break;
   11240             :     case AMDGPU::VGPR69: OpKind = MCK_VGPR_32; break;
   11241             :     case AMDGPU::VGPR70: OpKind = MCK_VGPR_32; break;
   11242             :     case AMDGPU::VGPR71: OpKind = MCK_VGPR_32; break;
   11243             :     case AMDGPU::VGPR72: OpKind = MCK_VGPR_32; break;
   11244             :     case AMDGPU::VGPR73: OpKind = MCK_VGPR_32; break;
   11245             :     case AMDGPU::VGPR74: OpKind = MCK_VGPR_32; break;
   11246             :     case AMDGPU::VGPR75: OpKind = MCK_VGPR_32; break;
   11247             :     case AMDGPU::VGPR76: OpKind = MCK_VGPR_32; break;
   11248             :     case AMDGPU::VGPR77: OpKind = MCK_VGPR_32; break;
   11249             :     case AMDGPU::VGPR78: OpKind = MCK_VGPR_32; break;
   11250             :     case AMDGPU::VGPR79: OpKind = MCK_VGPR_32; break;
   11251             :     case AMDGPU::VGPR80: OpKind = MCK_VGPR_32; break;
   11252             :     case AMDGPU::VGPR81: OpKind = MCK_VGPR_32; break;
   11253             :     case AMDGPU::VGPR82: OpKind = MCK_VGPR_32; break;
   11254             :     case AMDGPU::VGPR83: OpKind = MCK_VGPR_32; break;
   11255             :     case AMDGPU::VGPR84: OpKind = MCK_VGPR_32; break;
   11256             :     case AMDGPU::VGPR85: OpKind = MCK_VGPR_32; break;
   11257             :     case AMDGPU::VGPR86: OpKind = MCK_VGPR_32; break;
   11258             :     case AMDGPU::VGPR87: OpKind = MCK_VGPR_32; break;
   11259             :     case AMDGPU::VGPR88: OpKind = MCK_VGPR_32; break;
   11260             :     case AMDGPU::VGPR89: OpKind = MCK_VGPR_32; break;
   11261             :     case AMDGPU::VGPR90: OpKind = MCK_VGPR_32; break;
   11262             :     case AMDGPU::VGPR91: OpKind = MCK_VGPR_32; break;
   11263             :     case AMDGPU::VGPR92: OpKind = MCK_VGPR_32; break;
   11264             :     case AMDGPU::VGPR93: OpKind = MCK_VGPR_32; break;
   11265             :     case AMDGPU::VGPR94: OpKind = MCK_VGPR_32; break;
   11266             :     case AMDGPU::VGPR95: OpKind = MCK_VGPR_32; break;
   11267             :     case AMDGPU::VGPR96: OpKind = MCK_VGPR_32; break;
   11268             :     case AMDGPU::VGPR97: OpKind = MCK_VGPR_32; break;
   11269             :     case AMDGPU::VGPR98: OpKind = MCK_VGPR_32; break;
   11270             :     case AMDGPU::VGPR99: OpKind = MCK_VGPR_32; break;
   11271             :     case AMDGPU::VGPR100: OpKind = MCK_VGPR_32; break;
   11272             :     case AMDGPU::VGPR101: OpKind = MCK_VGPR_32; break;
   11273             :     case AMDGPU::VGPR102: OpKind = MCK_VGPR_32; break;
   11274             :     case AMDGPU::VGPR103: OpKind = MCK_VGPR_32; break;
   11275             :     case AMDGPU::VGPR104: OpKind = MCK_VGPR_32; break;
   11276             :     case AMDGPU::VGPR105: OpKind = MCK_VGPR_32; break;
   11277             :     case AMDGPU::VGPR106: OpKind = MCK_VGPR_32; break;
   11278             :     case AMDGPU::VGPR107: OpKind = MCK_VGPR_32; break;
   11279             :     case AMDGPU::VGPR108: OpKind = MCK_VGPR_32; break;
   11280             :     case AMDGPU::VGPR109: OpKind = MCK_VGPR_32; break;
   11281             :     case AMDGPU::VGPR110: OpKind = MCK_VGPR_32; break;
   11282             :     case AMDGPU::VGPR111: OpKind = MCK_VGPR_32; break;
   11283             :     case AMDGPU::VGPR112: OpKind = MCK_VGPR_32; break;
   11284             :     case AMDGPU::VGPR113: OpKind = MCK_VGPR_32; break;
   11285             :     case AMDGPU::VGPR114: OpKind = MCK_VGPR_32; break;
   11286             :     case AMDGPU::VGPR115: OpKind = MCK_VGPR_32; break;
   11287             :     case AMDGPU::VGPR116: OpKind = MCK_VGPR_32; break;
   11288             :     case AMDGPU::VGPR117: OpKind = MCK_VGPR_32; break;
   11289             :     case AMDGPU::VGPR118: OpKind = MCK_VGPR_32; break;
   11290             :     case AMDGPU::VGPR119: OpKind = MCK_VGPR_32; break;
   11291             :     case AMDGPU::VGPR120: OpKind = MCK_VGPR_32; break;
   11292             :     case AMDGPU::VGPR121: OpKind = MCK_VGPR_32; break;
   11293             :     case AMDGPU::VGPR122: OpKind = MCK_VGPR_32; break;
   11294             :     case AMDGPU::VGPR123: OpKind = MCK_VGPR_32; break;
   11295             :     case AMDGPU::VGPR124: OpKind = MCK_VGPR_32; break;
   11296             :     case AMDGPU::VGPR125: OpKind = MCK_VGPR_32; break;
   11297             :     case AMDGPU::VGPR126: OpKind = MCK_VGPR_32; break;
   11298             :     case AMDGPU::VGPR127: OpKind = MCK_VGPR_32; break;
   11299             :     case AMDGPU::VGPR128: OpKind = MCK_VGPR_32; break;
   11300             :     case AMDGPU::VGPR129: OpKind = MCK_VGPR_32; break;
   11301             :     case AMDGPU::VGPR130: OpKind = MCK_VGPR_32; break;
   11302             :     case AMDGPU::VGPR131: OpKind = MCK_VGPR_32; break;
   11303             :     case AMDGPU::VGPR132: OpKind = MCK_VGPR_32; break;
   11304             :     case AMDGPU::VGPR133: OpKind = MCK_VGPR_32; break;
   11305             :     case AMDGPU::VGPR134: OpKind = MCK_VGPR_32; break;
   11306             :     case AMDGPU::VGPR135: OpKind = MCK_VGPR_32; break;
   11307             :     case AMDGPU::VGPR136: OpKind = MCK_VGPR_32; break;
   11308             :     case AMDGPU::VGPR137: OpKind = MCK_VGPR_32; break;
   11309             :     case AMDGPU::VGPR138: OpKind = MCK_VGPR_32; break;
   11310             :     case AMDGPU::VGPR139: OpKind = MCK_VGPR_32; break;
   11311             :     case AMDGPU::VGPR140: OpKind = MCK_VGPR_32; break;
   11312             :     case AMDGPU::VGPR141: OpKind = MCK_VGPR_32; break;
   11313             :     case AMDGPU::VGPR142: OpKind = MCK_VGPR_32; break;
   11314             :     case AMDGPU::VGPR143: OpKind = MCK_VGPR_32; break;
   11315             :     case AMDGPU::VGPR144: OpKind = MCK_VGPR_32; break;
   11316             :     case AMDGPU::VGPR145: OpKind = MCK_VGPR_32; break;
   11317             :     case AMDGPU::VGPR146: OpKind = MCK_VGPR_32; break;
   11318             :     case AMDGPU::VGPR147: OpKind = MCK_VGPR_32; break;
   11319             :     case AMDGPU::VGPR148: OpKind = MCK_VGPR_32; break;
   11320             :     case AMDGPU::VGPR149: OpKind = MCK_VGPR_32; break;
   11321             :     case AMDGPU::VGPR150: OpKind = MCK_VGPR_32; break;
   11322             :     case AMDGPU::VGPR151: OpKind = MCK_VGPR_32; break;
   11323             :     case AMDGPU::VGPR152: OpKind = MCK_VGPR_32; break;
   11324             :     case AMDGPU::VGPR153: OpKind = MCK_VGPR_32; break;
   11325             :     case AMDGPU::VGPR154: OpKind = MCK_VGPR_32; break;
   11326             :     case AMDGPU::VGPR155: OpKind = MCK_VGPR_32; break;
   11327             :     case AMDGPU::VGPR156: OpKind = MCK_VGPR_32; break;
   11328             :     case AMDGPU::VGPR157: OpKind = MCK_VGPR_32; break;
   11329             :     case AMDGPU::VGPR158: OpKind = MCK_VGPR_32; break;
   11330             :     case AMDGPU::VGPR159: OpKind = MCK_VGPR_32; break;
   11331             :     case AMDGPU::VGPR160: OpKind = MCK_VGPR_32; break;
   11332             :     case AMDGPU::VGPR161: OpKind = MCK_VGPR_32; break;
   11333             :     case AMDGPU::VGPR162: OpKind = MCK_VGPR_32; break;
   11334             :     case AMDGPU::VGPR163: OpKind = MCK_VGPR_32; break;
   11335             :     case AMDGPU::VGPR164: OpKind = MCK_VGPR_32; break;
   11336             :     case AMDGPU::VGPR165: OpKind = MCK_VGPR_32; break;
   11337             :     case AMDGPU::VGPR166: OpKind = MCK_VGPR_32; break;
   11338             :     case AMDGPU::VGPR167: OpKind = MCK_VGPR_32; break;
   11339             :     case AMDGPU::VGPR168: OpKind = MCK_VGPR_32; break;
   11340             :     case AMDGPU::VGPR169: OpKind = MCK_VGPR_32; break;
   11341             :     case AMDGPU::VGPR170: OpKind = MCK_VGPR_32; break;
   11342             :     case AMDGPU::VGPR171: OpKind = MCK_VGPR_32; break;
   11343             :     case AMDGPU::VGPR172: OpKind = MCK_VGPR_32; break;
   11344             :     case AMDGPU::VGPR173: OpKind = MCK_VGPR_32; break;
   11345             :     case AMDGPU::VGPR174: OpKind = MCK_VGPR_32; break;
   11346             :     case AMDGPU::VGPR175: OpKind = MCK_VGPR_32; break;
   11347             :     case AMDGPU::VGPR176: OpKind = MCK_VGPR_32; break;
   11348             :     case AMDGPU::VGPR177: OpKind = MCK_VGPR_32; break;
   11349             :     case AMDGPU::VGPR178: OpKind = MCK_VGPR_32; break;
   11350             :     case AMDGPU::VGPR179: OpKind = MCK_VGPR_32; break;
   11351             :     case AMDGPU::VGPR180: OpKind = MCK_VGPR_32; break;
   11352             :     case AMDGPU::VGPR181: OpKind = MCK_VGPR_32; break;
   11353             :     case AMDGPU::VGPR182: OpKind = MCK_VGPR_32; break;
   11354             :     case AMDGPU::VGPR183: OpKind = MCK_VGPR_32; break;
   11355             :     case AMDGPU::VGPR184: OpKind = MCK_VGPR_32; break;
   11356             :     case AMDGPU::VGPR185: OpKind = MCK_VGPR_32; break;
   11357             :     case AMDGPU::VGPR186: OpKind = MCK_VGPR_32; break;
   11358             :     case AMDGPU::VGPR187: OpKind = MCK_VGPR_32; break;
   11359             :     case AMDGPU::VGPR188: OpKind = MCK_VGPR_32; break;
   11360             :     case AMDGPU::VGPR189: OpKind = MCK_VGPR_32; break;
   11361             :     case AMDGPU::VGPR190: OpKind = MCK_VGPR_32; break;
   11362             :     case AMDGPU::VGPR191: OpKind = MCK_VGPR_32; break;
   11363             :     case AMDGPU::VGPR192: OpKind = MCK_VGPR_32; break;
   11364             :     case AMDGPU::VGPR193: OpKind = MCK_VGPR_32; break;
   11365             :     case AMDGPU::VGPR194: OpKind = MCK_VGPR_32; break;
   11366             :     case AMDGPU::VGPR195: OpKind = MCK_VGPR_32; break;
   11367             :     case AMDGPU::VGPR196: OpKind = MCK_VGPR_32; break;
   11368             :     case AMDGPU::VGPR197: OpKind = MCK_VGPR_32; break;
   11369             :     case AMDGPU::VGPR198: OpKind = MCK_VGPR_32; break;
   11370             :     case AMDGPU::VGPR199: OpKind = MCK_VGPR_32; break;
   11371             :     case AMDGPU::VGPR200: OpKind = MCK_VGPR_32; break;
   11372             :     case AMDGPU::VGPR201: OpKind = MCK_VGPR_32; break;
   11373             :     case AMDGPU::VGPR202: OpKind = MCK_VGPR_32; break;
   11374             :     case AMDGPU::VGPR203: OpKind = MCK_VGPR_32; break;
   11375             :     case AMDGPU::VGPR204: OpKind = MCK_VGPR_32; break;
   11376             :     case AMDGPU::VGPR205: OpKind = MCK_VGPR_32; break;
   11377             :     case AMDGPU::VGPR206: OpKind = MCK_VGPR_32; break;
   11378             :     case AMDGPU::VGPR207: OpKind = MCK_VGPR_32; break;
   11379             :     case AMDGPU::VGPR208: OpKind = MCK_VGPR_32; break;
   11380             :     case AMDGPU::VGPR209: OpKind = MCK_VGPR_32; break;
   11381             :     case AMDGPU::VGPR210: OpKind = MCK_VGPR_32; break;
   11382             :     case AMDGPU::VGPR211: OpKind = MCK_VGPR_32; break;
   11383             :     case AMDGPU::VGPR212: OpKind = MCK_VGPR_32; break;
   11384             :     case AMDGPU::VGPR213: OpKind = MCK_VGPR_32; break;
   11385             :     case AMDGPU::VGPR214: OpKind = MCK_VGPR_32; break;
   11386             :     case AMDGPU::VGPR215: OpKind = MCK_VGPR_32; break;
   11387             :     case AMDGPU::VGPR216: OpKind = MCK_VGPR_32; break;
   11388             :     case AMDGPU::VGPR217: OpKind = MCK_VGPR_32; break;
   11389             :     case AMDGPU::VGPR218: OpKind = MCK_VGPR_32; break;
   11390             :     case AMDGPU::VGPR219: OpKind = MCK_VGPR_32; break;
   11391             :     case AMDGPU::VGPR220: OpKind = MCK_VGPR_32; break;
   11392             :     case AMDGPU::VGPR221: OpKind = MCK_VGPR_32; break;
   11393             :     case AMDGPU::VGPR222: OpKind = MCK_VGPR_32; break;
   11394             :     case AMDGPU::VGPR223: OpKind = MCK_VGPR_32; break;
   11395             :     case AMDGPU::VGPR224: OpKind = MCK_VGPR_32; break;
   11396             :     case AMDGPU::VGPR225: OpKind = MCK_VGPR_32; break;
   11397             :     case AMDGPU::VGPR226: OpKind = MCK_VGPR_32; break;
   11398             :     case AMDGPU::VGPR227: OpKind = MCK_VGPR_32; break;
   11399             :     case AMDGPU::VGPR228: OpKind = MCK_VGPR_32; break;
   11400             :     case AMDGPU::VGPR229: OpKind = MCK_VGPR_32; break;
   11401             :     case AMDGPU::VGPR230: OpKind = MCK_VGPR_32; break;
   11402             :     case AMDGPU::VGPR231: OpKind = MCK_VGPR_32; break;
   11403             :     case AMDGPU::VGPR232: OpKind = MCK_VGPR_32; break;
   11404             :     case AMDGPU::VGPR233: OpKind = MCK_VGPR_32; break;
   11405             :     case AMDGPU::VGPR234: OpKind = MCK_VGPR_32; break;
   11406             :     case AMDGPU::VGPR235: OpKind = MCK_VGPR_32; break;
   11407             :     case AMDGPU::VGPR236: OpKind = MCK_VGPR_32; break;
   11408             :     case AMDGPU::VGPR237: OpKind = MCK_VGPR_32; break;
   11409             :     case AMDGPU::VGPR238: OpKind = MCK_VGPR_32; break;
   11410             :     case AMDGPU::VGPR239: OpKind = MCK_VGPR_32; break;
   11411             :     case AMDGPU::VGPR240: OpKind = MCK_VGPR_32; break;
   11412             :     case AMDGPU::VGPR241: OpKind = MCK_VGPR_32; break;
   11413             :     case AMDGPU::VGPR242: OpKind = MCK_VGPR_32; break;
   11414             :     case AMDGPU::VGPR243: OpKind = MCK_VGPR_32; break;
   11415             :     case AMDGPU::VGPR244: OpKind = MCK_VGPR_32; break;
   11416             :     case AMDGPU::VGPR245: OpKind = MCK_VGPR_32; break;
   11417             :     case AMDGPU::VGPR246: OpKind = MCK_VGPR_32; break;
   11418             :     case AMDGPU::VGPR247: OpKind = MCK_VGPR_32; break;
   11419             :     case AMDGPU::VGPR248: OpKind = MCK_VGPR_32; break;
   11420             :     case AMDGPU::VGPR249: OpKind = MCK_VGPR_32; break;
   11421             :     case AMDGPU::VGPR250: OpKind = MCK_VGPR_32; break;
   11422             :     case AMDGPU::VGPR251: OpKind = MCK_VGPR_32; break;
   11423             :     case AMDGPU::VGPR252: OpKind = MCK_VGPR_32; break;
   11424             :     case AMDGPU::VGPR253: OpKind = MCK_VGPR_32; break;
   11425             :     case AMDGPU::VGPR254: OpKind = MCK_VGPR_32; break;
   11426             :     case AMDGPU::VGPR255: OpKind = MCK_VGPR_32; break;
   11427             :     case AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3: OpKind = MCK_SGPR_128; break;
   11428             :     case AMDGPU::SGPR4_SGPR5_SGPR6_SGPR7: OpKind = MCK_SGPR_128; break;
   11429             :     case AMDGPU::SGPR8_SGPR9_SGPR10_SGPR11: OpKind = MCK_SGPR_128; break;
   11430             :     case AMDGPU::SGPR12_SGPR13_SGPR14_SGPR15: OpKind = MCK_SGPR_128; break;
   11431             :     case AMDGPU::SGPR16_SGPR17_SGPR18_SGPR19: OpKind = MCK_SGPR_128; break;
   11432             :     case AMDGPU::SGPR20_SGPR21_SGPR22_SGPR23: OpKind = MCK_SGPR_128; break;
   11433             :     case AMDGPU::SGPR24_SGPR25_SGPR26_SGPR27: OpKind = MCK_SGPR_128; break;
   11434             :     case AMDGPU::SGPR28_SGPR29_SGPR30_SGPR31: OpKind = MCK_SGPR_128; break;
   11435             :     case AMDGPU::SGPR32_SGPR33_SGPR34_SGPR35: OpKind = MCK_SGPR_128; break;
   11436             :     case AMDGPU::SGPR36_SGPR37_SGPR38_SGPR39: OpKind = MCK_SGPR_128; break;
   11437             :     case AMDGPU::SGPR40_SGPR41_SGPR42_SGPR43: OpKind = MCK_SGPR_128; break;
   11438             :     case AMDGPU::SGPR44_SGPR45_SGPR46_SGPR47: OpKind = MCK_SGPR_128; break;
   11439             :     case AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51: OpKind = MCK_SGPR_128; break;
   11440             :     case AMDGPU::SGPR52_SGPR53_SGPR54_SGPR55: OpKind = MCK_SGPR_128; break;
   11441             :     case AMDGPU::SGPR56_SGPR57_SGPR58_SGPR59: OpKind = MCK_SGPR_128; break;
   11442             :     case AMDGPU::SGPR60_SGPR61_SGPR62_SGPR63: OpKind = MCK_SGPR_128; break;
   11443             :     case AMDGPU::SGPR64_SGPR65_SGPR66_SGPR67: OpKind = MCK_SGPR_128; break;
   11444             :     case AMDGPU::SGPR68_SGPR69_SGPR70_SGPR71: OpKind = MCK_SGPR_128; break;
   11445             :     case AMDGPU::SGPR72_SGPR73_SGPR74_SGPR75: OpKind = MCK_SGPR_128; break;
   11446             :     case AMDGPU::SGPR76_SGPR77_SGPR78_SGPR79: OpKind = MCK_SGPR_128; break;
   11447             :     case AMDGPU::SGPR80_SGPR81_SGPR82_SGPR83: OpKind = MCK_SGPR_128; break;
   11448             :     case AMDGPU::SGPR84_SGPR85_SGPR86_SGPR87: OpKind = MCK_SGPR_128; break;
   11449             :     case AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91: OpKind = MCK_SGPR_128; break;
   11450             :     case AMDGPU::SGPR92_SGPR93_SGPR94_SGPR95: OpKind = MCK_SGPR_128; break;
   11451             :     case AMDGPU::SGPR96_SGPR97_SGPR98_SGPR99: OpKind = MCK_SGPR_128; break;
   11452             :     case AMDGPU::SGPR100_SGPR101_SGPR102_SGPR103: OpKind = MCK_SGPR_128; break;
   11453             :     case AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7: OpKind = MCK_SGPR_256; break;
   11454             :     case AMDGPU::SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11: OpKind = MCK_SGPR_256; break;
   11455             :     case AMDGPU::SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15: OpKind = MCK_SGPR_256; break;
   11456             :     case AMDGPU::SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19: OpKind = MCK_SGPR_256; break;
   11457             :     case AMDGPU::SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23: OpKind = MCK_SGPR_256; break;
   11458             :     case AMDGPU::SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27: OpKind = MCK_SGPR_256; break;
   11459             :     case AMDGPU::SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31: OpKind = MCK_SGPR_256; break;
   11460             :     case AMDGPU::SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35: OpKind = MCK_SGPR_256; break;
   11461             :     case AMDGPU::SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39: OpKind = MCK_SGPR_256; break;
   11462             :     case AMDGPU::SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43: OpKind = MCK_SGPR_256; break;
   11463             :     case AMDGPU::SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47: OpKind = MCK_SGPR_256; break;
   11464             :     case AMDGPU::SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51: OpKind = MCK_SGPR_256; break;
   11465             :     case AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55: OpKind = MCK_SGPR_256; break;
   11466             :     case AMDGPU::SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59: OpKind = MCK_SGPR_256; break;
   11467             :     case AMDGPU::SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63: OpKind = MCK_SGPR_256; break;
   11468             :     case AMDGPU::SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67: OpKind = MCK_SGPR_256; break;
   11469             :     case AMDGPU::SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71: OpKind = MCK_SGPR_256; break;
   11470             :     case AMDGPU::SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75: OpKind = MCK_SGPR_256; break;
   11471             :     case AMDGPU::SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79: OpKind = MCK_SGPR_256; break;
   11472             :     case AMDGPU::SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83: OpKind = MCK_SGPR_256; break;
   11473             :     case AMDGPU::SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87: OpKind = MCK_SGPR_256; break;
   11474             :     case AMDGPU::SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91: OpKind = MCK_SGPR_256; break;
   11475             :     case AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95: OpKind = MCK_SGPR_256; break;
   11476             :     case AMDGPU::SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99: OpKind = MCK_SGPR_256; break;
   11477             :     case AMDGPU::SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103: OpKind = MCK_SGPR_256; break;
   11478             :     case AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15: OpKind = MCK_SGPR_512; break;
   11479             :     case AMDGPU::SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19: OpKind = MCK_SGPR_512; break;
   11480             :     case AMDGPU::SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23: OpKind = MCK_SGPR_512; break;
   11481             :     case AMDGPU::SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27: OpKind = MCK_SGPR_512; break;
   11482             :     case AMDGPU::SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31: OpKind = MCK_SGPR_512; break;
   11483             :     case AMDGPU::SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35: OpKind = MCK_SGPR_512; break;
   11484             :     case AMDGPU::SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39: OpKind = MCK_SGPR_512; break;
   11485             :     case AMDGPU::SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43: OpKind = MCK_SGPR_512; break;
   11486             :     case AMDGPU::SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47: OpKind = MCK_SGPR_512; break;
   11487             :     case AMDGPU::SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51: OpKind = MCK_SGPR_512; break;
   11488             :     case AMDGPU::SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55: OpKind = MCK_SGPR_512; break;
   11489             :     case AMDGPU::SGPR44_SGPR45_SGPR46_SGPR47_SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59: OpKind = MCK_SGPR_512; break;
   11490             :     case AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63: OpKind = MCK_SGPR_512; break;
   11491             :     case AMDGPU::SGPR52_SGPR53_SGPR54_SGPR55_SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67: OpKind = MCK_SGPR_512; break;
   11492             :     case AMDGPU::SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71: OpKind = MCK_SGPR_512; break;
   11493             :     case AMDGPU::SGPR60_SGPR61_SGPR62_SGPR63_SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75: OpKind = MCK_SGPR_512; break;
   11494             :     case AMDGPU::SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79: OpKind = MCK_SGPR_512; break;
   11495             :     case AMDGPU::SGPR68_SGPR69_SGPR70_SGPR71_SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83: OpKind = MCK_SGPR_512; break;
   11496             :     case AMDGPU::SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87: OpKind = MCK_SGPR_512; break;
   11497             :     case AMDGPU::SGPR76_SGPR77_SGPR78_SGPR79_SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91: OpKind = MCK_SGPR_512; break;
   11498             :     case AMDGPU::SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95: OpKind = MCK_SGPR_512; break;
   11499             :     case AMDGPU::SGPR84_SGPR85_SGPR86_SGPR87_SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99: OpKind = MCK_SGPR_512; break;
   11500             :     case AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103: OpKind = MCK_SGPR_512; break;
   11501             :     case AMDGPU::SGPR0_SGPR1: OpKind = MCK_SGPR_64; break;
   11502             :     case AMDGPU::SGPR2_SGPR3: OpKind = MCK_SGPR_64; break;
   11503             :     case AMDGPU::SGPR4_SGPR5: OpKind = MCK_SGPR_64; break;
   11504             :     case AMDGPU::SGPR6_SGPR7: OpKind = MCK_SGPR_64; break;
   11505             :     case AMDGPU::SGPR8_SGPR9: OpKind = MCK_SGPR_64; break;
   11506             :     case AMDGPU::SGPR10_SGPR11: OpKind = MCK_SGPR_64; break;
   11507             :     case AMDGPU::SGPR12_SGPR13: OpKind = MCK_SGPR_64; break;
   11508             :     case AMDGPU::SGPR14_SGPR15: OpKind = MCK_SGPR_64; break;
   11509             :     case AMDGPU::SGPR16_SGPR17: OpKind = MCK_SGPR_64; break;
   11510             :     case AMDGPU::SGPR18_SGPR19: OpKind = MCK_SGPR_64; break;
   11511             :     case AMDGPU::SGPR20_SGPR21: OpKind = MCK_SGPR_64; break;
   11512             :     case AMDGPU::SGPR22_SGPR23: OpKind = MCK_SGPR_64; break;
   11513             :     case AMDGPU::SGPR24_SGPR25: OpKind = MCK_SGPR_64; break;
   11514             :     case AMDGPU::SGPR26_SGPR27: OpKind = MCK_SGPR_64; break;
   11515             :     case AMDGPU::SGPR28_SGPR29: OpKind = MCK_SGPR_64; break;
   11516             :     case AMDGPU::SGPR30_SGPR31: OpKind = MCK_SGPR_64; break;
   11517             :     case AMDGPU::SGPR32_SGPR33: OpKind = MCK_SGPR_64; break;
   11518             :     case AMDGPU::SGPR34_SGPR35: OpKind = MCK_SGPR_64; break;
   11519             :     case AMDGPU::SGPR36_SGPR37: OpKind = MCK_SGPR_64; break;
   11520             :     case AMDGPU::SGPR38_SGPR39: OpKind = MCK_SGPR_64; break;
   11521             :     case AMDGPU::SGPR40_SGPR41: OpKind = MCK_SGPR_64; break;
   11522             :     case AMDGPU::SGPR42_SGPR43: OpKind = MCK_SGPR_64; break;
   11523             :     case AMDGPU::SGPR44_SGPR45: OpKind = MCK_SGPR_64; break;
   11524             :     case AMDGPU::SGPR46_SGPR47: OpKind = MCK_SGPR_64; break;
   11525             :     case AMDGPU::SGPR48_SGPR49: OpKind = MCK_SGPR_64; break;
   11526             :     case AMDGPU::SGPR50_SGPR51: OpKind = MCK_SGPR_64; break;
   11527             :     case AMDGPU::SGPR52_SGPR53: OpKind = MCK_SGPR_64; break;
   11528             :     case AMDGPU::SGPR54_SGPR55: OpKind = MCK_SGPR_64; break;
   11529             :     case AMDGPU::SGPR56_SGPR57: OpKind = MCK_SGPR_64; break;
   11530             :     case AMDGPU::SGPR58_SGPR59: OpKind = MCK_SGPR_64; break;
   11531             :     case AMDGPU::SGPR60_SGPR61: OpKind = MCK_SGPR_64; break;
   11532             :     case AMDGPU::SGPR62_SGPR63: OpKind = MCK_SGPR_64; break;
   11533             :     case AMDGPU::SGPR64_SGPR65: OpKind = MCK_SGPR_64; break;
   11534             :     case AMDGPU::SGPR66_SGPR67: OpKind = MCK_SGPR_64; break;
   11535             :     case AMDGPU::SGPR68_SGPR69: OpKind = MCK_SGPR_64; break;
   11536             :     case AMDGPU::SGPR70_SGPR71: OpKind = MCK_SGPR_64; break;
   11537             :     case AMDGPU::SGPR72_SGPR73: OpKind = MCK_SGPR_64; break;
   11538             :     case AMDGPU::SGPR74_SGPR75: OpKind = MCK_SGPR_64; break;
   11539             :     case AMDGPU::SGPR76_SGPR77: OpKind = MCK_SGPR_64; break;
   11540             :     case AMDGPU::SGPR78_SGPR79: OpKind = MCK_SGPR_64; break;
   11541             :     case AMDGPU::SGPR80_SGPR81: OpKind = MCK_SGPR_64; break;
   11542             :     case AMDGPU::SGPR82_SGPR83: OpKind = MCK_SGPR_64; break;
   11543             :     case AMDGPU::SGPR84_SGPR85: OpKind = MCK_SGPR_64; break;
   11544             :     case AMDGPU::SGPR86_SGPR87: OpKind = MCK_SGPR_64; break;
   11545             :     case AMDGPU::SGPR88_SGPR89: OpKind = MCK_SGPR_64; break;
   11546             :     case AMDGPU::SGPR90_SGPR91: OpKind = MCK_SGPR_64; break;
   11547             :     case AMDGPU::SGPR92_SGPR93: OpKind = MCK_SGPR_64; break;
   11548             :     case AMDGPU::SGPR94_SGPR95: OpKind = MCK_SGPR_64; break;
   11549             :     case AMDGPU::SGPR96_SGPR97: OpKind = MCK_SGPR_64; break;
   11550             :     case AMDGPU::SGPR98_SGPR99: OpKind = MCK_SGPR_64; break;
   11551             :     case AMDGPU::SGPR100_SGPR101: OpKind = MCK_SGPR_64; break;
   11552             :     case AMDGPU::SGPR102_SGPR103: OpKind = MCK_SGPR_64; break;
   11553             :     case AMDGPU::TTMP0_TTMP1_TTMP2_TTMP3: OpKind = MCK_TTMP_128; break;
   11554             :     case AMDGPU::TTMP4_TTMP5_TTMP6_TTMP7: OpKind = MCK_TTMP_128; break;
   11555             :     case AMDGPU::TTMP8_TTMP9_TTMP10_TTMP11: OpKind = MCK_TTMP_128; break;
   11556             :     case AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15: OpKind = MCK_TTMP_128; break;
   11557             :     case AMDGPU::TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7: OpKind = MCK_TTMP_256; break;
   11558             :     case AMDGPU::TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11: OpKind = MCK_TTMP_256; break;
   11559             :     case AMDGPU::TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15: OpKind = MCK_TTMP_256; break;
   11560             :     case AMDGPU::TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15: OpKind = MCK_TTMP_512; break;
   11561             :     case AMDGPU::TTMP0_TTMP1: OpKind = MCK_TTMP_64; break;
   11562             :     case AMDGPU::TTMP2_TTMP3: OpKind = MCK_TTMP_64; break;
   11563             :     case AMDGPU::TTMP4_TTMP5: OpKind = MCK_TTMP_64; break;
   11564             :     case AMDGPU::TTMP6_TTMP7: OpKind = MCK_TTMP_64; break;
   11565             :     case AMDGPU::TTMP8_TTMP9: OpKind = MCK_TTMP_64; break;
   11566             :     case AMDGPU::TTMP10_TTMP11: OpKind = MCK_TTMP_64; break;
   11567             :     case AMDGPU::TTMP12_TTMP13: OpKind = MCK_TTMP_64; break;
   11568             :     case AMDGPU::TTMP14_TTMP15: OpKind = MCK_TTMP_64; break;
   11569             :     case AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3: OpKind = MCK_VReg_128; break;
   11570             :     case AMDGPU::VGPR1_VGPR2_VGPR3_VGPR4: OpKind = MCK_VReg_128; break;
   11571             :     case AMDGPU::VGPR2_VGPR3_VGPR4_VGPR5: OpKind = MCK_VReg_128; break;
   11572             :     case AMDGPU::VGPR3_VGPR4_VGPR5_VGPR6: OpKind = MCK_VReg_128; break;
   11573             :     case AMDGPU::VGPR4_VGPR5_VGPR6_VGPR7: OpKind = MCK_VReg_128; break;
   11574             :     case AMDGPU::VGPR5_VGPR6_VGPR7_VGPR8: OpKind = MCK_VReg_128; break;
   11575             :     case AMDGPU::VGPR6_VGPR7_VGPR8_VGPR9: OpKind = MCK_VReg_128; break;
   11576             :     case AMDGPU::VGPR7_VGPR8_VGPR9_VGPR10: OpKind = MCK_VReg_128; break;
   11577             :     case AMDGPU::VGPR8_VGPR9_VGPR10_VGPR11: OpKind = MCK_VReg_128; break;
   11578             :     case AMDGPU::VGPR9_VGPR10_VGPR11_VGPR12: OpKind = MCK_VReg_128; break;
   11579             :     case AMDGPU::VGPR10_VGPR11_VGPR12_VGPR13: OpKind = MCK_VReg_128; break;
   11580             :     case AMDGPU::VGPR11_VGPR12_VGPR13_VGPR14: OpKind = MCK_VReg_128; break;
   11581             :     case AMDGPU::VGPR12_VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_128; break;
   11582             :     case AMDGPU::VGPR13_VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_128; break;
   11583             :     case AMDGPU::VGPR14_VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_128; break;
   11584             :     case AMDGPU::VGPR15_VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_128; break;
   11585             :     case AMDGPU::VGPR16_VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_128; break;
   11586             :     case AMDGPU::VGPR17_VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_128; break;
   11587             :     case AMDGPU::VGPR18_VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_128; break;
   11588             :     case AMDGPU::VGPR19_VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_128; break;
   11589             :     case AMDGPU::VGPR20_VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_128; break;
   11590             :     case AMDGPU::VGPR21_VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_128; break;
   11591             :     case AMDGPU::VGPR22_VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_128; break;
   11592             :     case AMDGPU::VGPR23_VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_128; break;
   11593             :     case AMDGPU::VGPR24_VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_128; break;
   11594             :     case AMDGPU::VGPR25_VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_128; break;
   11595             :     case AMDGPU::VGPR26_VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_128; break;
   11596             :     case AMDGPU::VGPR27_VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_128; break;
   11597             :     case AMDGPU::VGPR28_VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_128; break;
   11598             :     case AMDGPU::VGPR29_VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_128; break;
   11599             :     case AMDGPU::VGPR30_VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_128; break;
   11600             :     case AMDGPU::VGPR31_VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_128; break;
   11601             :     case AMDGPU::VGPR32_VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_128; break;
   11602             :     case AMDGPU::VGPR33_VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_128; break;
   11603             :     case AMDGPU::VGPR34_VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_128; break;
   11604             :     case AMDGPU::VGPR35_VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_128; break;
   11605             :     case AMDGPU::VGPR36_VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_128; break;
   11606             :     case AMDGPU::VGPR37_VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_128; break;
   11607             :     case AMDGPU::VGPR38_VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_128; break;
   11608             :     case AMDGPU::VGPR39_VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_128; break;
   11609             :     case AMDGPU::VGPR40_VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_128; break;
   11610             :     case AMDGPU::VGPR41_VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_128; break;
   11611             :     case AMDGPU::VGPR42_VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_128; break;
   11612             :     case AMDGPU::VGPR43_VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_128; break;
   11613             :     case AMDGPU::VGPR44_VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_128; break;
   11614             :     case AMDGPU::VGPR45_VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_128; break;
   11615             :     case AMDGPU::VGPR46_VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_128; break;
   11616             :     case AMDGPU::VGPR47_VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_128; break;
   11617             :     case AMDGPU::VGPR48_VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_128; break;
   11618             :     case AMDGPU::VGPR49_VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_128; break;
   11619             :     case AMDGPU::VGPR50_VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_128; break;
   11620             :     case AMDGPU::VGPR51_VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_128; break;
   11621             :     case AMDGPU::VGPR52_VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_128; break;
   11622             :     case AMDGPU::VGPR53_VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_128; break;
   11623             :     case AMDGPU::VGPR54_VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_128; break;
   11624             :     case AMDGPU::VGPR55_VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_128; break;
   11625             :     case AMDGPU::VGPR56_VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_128; break;
   11626             :     case AMDGPU::VGPR57_VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_128; break;
   11627             :     case AMDGPU::VGPR58_VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_128; break;
   11628             :     case AMDGPU::VGPR59_VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_128; break;
   11629             :     case AMDGPU::VGPR60_VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_128; break;
   11630             :     case AMDGPU::VGPR61_VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_128; break;
   11631             :     case AMDGPU::VGPR62_VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_128; break;
   11632             :     case AMDGPU::VGPR63_VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_128; break;
   11633             :     case AMDGPU::VGPR64_VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_128; break;
   11634             :     case AMDGPU::VGPR65_VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_128; break;
   11635             :     case AMDGPU::VGPR66_VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_128; break;
   11636             :     case AMDGPU::VGPR67_VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_128; break;
   11637             :     case AMDGPU::VGPR68_VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_128; break;
   11638             :     case AMDGPU::VGPR69_VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_128; break;
   11639             :     case AMDGPU::VGPR70_VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_128; break;
   11640             :     case AMDGPU::VGPR71_VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_128; break;
   11641             :     case AMDGPU::VGPR72_VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_128; break;
   11642             :     case AMDGPU::VGPR73_VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_128; break;
   11643             :     case AMDGPU::VGPR74_VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_128; break;
   11644             :     case AMDGPU::VGPR75_VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_128; break;
   11645             :     case AMDGPU::VGPR76_VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_128; break;
   11646             :     case AMDGPU::VGPR77_VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_128; break;
   11647             :     case AMDGPU::VGPR78_VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_128; break;
   11648             :     case AMDGPU::VGPR79_VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_128; break;
   11649             :     case AMDGPU::VGPR80_VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_128; break;
   11650             :     case AMDGPU::VGPR81_VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_128; break;
   11651             :     case AMDGPU::VGPR82_VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_128; break;
   11652             :     case AMDGPU::VGPR83_VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_128; break;
   11653             :     case AMDGPU::VGPR84_VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_128; break;
   11654             :     case AMDGPU::VGPR85_VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_128; break;
   11655             :     case AMDGPU::VGPR86_VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_128; break;
   11656             :     case AMDGPU::VGPR87_VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_128; break;
   11657             :     case AMDGPU::VGPR88_VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_128; break;
   11658             :     case AMDGPU::VGPR89_VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_128; break;
   11659             :     case AMDGPU::VGPR90_VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_128; break;
   11660             :     case AMDGPU::VGPR91_VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_128; break;
   11661             :     case AMDGPU::VGPR92_VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_128; break;
   11662             :     case AMDGPU::VGPR93_VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_128; break;
   11663             :     case AMDGPU::VGPR94_VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_128; break;
   11664             :     case AMDGPU::VGPR95_VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_128; break;
   11665             :     case AMDGPU::VGPR96_VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_128; break;
   11666             :     case AMDGPU::VGPR97_VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_128; break;
   11667             :     case AMDGPU::VGPR98_VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_128; break;
   11668             :     case AMDGPU::VGPR99_VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_128; break;
   11669             :     case AMDGPU::VGPR100_VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_128; break;
   11670             :     case AMDGPU::VGPR101_VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_128; break;
   11671             :     case AMDGPU::VGPR102_VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_128; break;
   11672             :     case AMDGPU::VGPR103_VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_128; break;
   11673             :     case AMDGPU::VGPR104_VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_128; break;
   11674             :     case AMDGPU::VGPR105_VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_128; break;
   11675             :     case AMDGPU::VGPR106_VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_128; break;
   11676             :     case AMDGPU::VGPR107_VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_128; break;
   11677             :     case AMDGPU::VGPR108_VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_128; break;
   11678             :     case AMDGPU::VGPR109_VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_128; break;
   11679             :     case AMDGPU::VGPR110_VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_128; break;
   11680             :     case AMDGPU::VGPR111_VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_128; break;
   11681             :     case AMDGPU::VGPR112_VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_128; break;
   11682             :     case AMDGPU::VGPR113_VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_128; break;
   11683             :     case AMDGPU::VGPR114_VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_128; break;
   11684             :     case AMDGPU::VGPR115_VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_128; break;
   11685             :     case AMDGPU::VGPR116_VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_128; break;
   11686             :     case AMDGPU::VGPR117_VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_128; break;
   11687             :     case AMDGPU::VGPR118_VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_128; break;
   11688             :     case AMDGPU::VGPR119_VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_128; break;
   11689             :     case AMDGPU::VGPR120_VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_128; break;
   11690             :     case AMDGPU::VGPR121_VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_128; break;
   11691             :     case AMDGPU::VGPR122_VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_128; break;
   11692             :     case AMDGPU::VGPR123_VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_128; break;
   11693             :     case AMDGPU::VGPR124_VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_128; break;
   11694             :     case AMDGPU::VGPR125_VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_128; break;
   11695             :     case AMDGPU::VGPR126_VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_128; break;
   11696             :     case AMDGPU::VGPR127_VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_128; break;
   11697             :     case AMDGPU::VGPR128_VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_128; break;
   11698             :     case AMDGPU::VGPR129_VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_128; break;
   11699             :     case AMDGPU::VGPR130_VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_128; break;
   11700             :     case AMDGPU::VGPR131_VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_128; break;
   11701             :     case AMDGPU::VGPR132_VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_128; break;
   11702             :     case AMDGPU::VGPR133_VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_128; break;
   11703             :     case AMDGPU::VGPR134_VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_128; break;
   11704             :     case AMDGPU::VGPR135_VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_128; break;
   11705             :     case AMDGPU::VGPR136_VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_128; break;
   11706             :     case AMDGPU::VGPR137_VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_128; break;
   11707             :     case AMDGPU::VGPR138_VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_128; break;
   11708             :     case AMDGPU::VGPR139_VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_128; break;
   11709             :     case AMDGPU::VGPR140_VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_128; break;
   11710             :     case AMDGPU::VGPR141_VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_128; break;
   11711             :     case AMDGPU::VGPR142_VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_128; break;
   11712             :     case AMDGPU::VGPR143_VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_128; break;
   11713             :     case AMDGPU::VGPR144_VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_128; break;
   11714             :     case AMDGPU::VGPR145_VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_128; break;
   11715             :     case AMDGPU::VGPR146_VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_128; break;
   11716             :     case AMDGPU::VGPR147_VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_128; break;
   11717             :     case AMDGPU::VGPR148_VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_128; break;
   11718             :     case AMDGPU::VGPR149_VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_128; break;
   11719             :     case AMDGPU::VGPR150_VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_128; break;
   11720             :     case AMDGPU::VGPR151_VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_128; break;
   11721             :     case AMDGPU::VGPR152_VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_128; break;
   11722             :     case AMDGPU::VGPR153_VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_128; break;
   11723             :     case AMDGPU::VGPR154_VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_128; break;
   11724             :     case AMDGPU::VGPR155_VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_128; break;
   11725             :     case AMDGPU::VGPR156_VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_128; break;
   11726             :     case AMDGPU::VGPR157_VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_128; break;
   11727             :     case AMDGPU::VGPR158_VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_128; break;
   11728             :     case AMDGPU::VGPR159_VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_128; break;
   11729             :     case AMDGPU::VGPR160_VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_128; break;
   11730             :     case AMDGPU::VGPR161_VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_128; break;
   11731             :     case AMDGPU::VGPR162_VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_128; break;
   11732             :     case AMDGPU::VGPR163_VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_128; break;
   11733             :     case AMDGPU::VGPR164_VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_128; break;
   11734             :     case AMDGPU::VGPR165_VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_128; break;
   11735             :     case AMDGPU::VGPR166_VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_128; break;
   11736             :     case AMDGPU::VGPR167_VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_128; break;
   11737             :     case AMDGPU::VGPR168_VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_128; break;
   11738             :     case AMDGPU::VGPR169_VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_128; break;
   11739             :     case AMDGPU::VGPR170_VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_128; break;
   11740             :     case AMDGPU::VGPR171_VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_128; break;
   11741             :     case AMDGPU::VGPR172_VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_128; break;
   11742             :     case AMDGPU::VGPR173_VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_128; break;
   11743             :     case AMDGPU::VGPR174_VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_128; break;
   11744             :     case AMDGPU::VGPR175_VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_128; break;
   11745             :     case AMDGPU::VGPR176_VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_128; break;
   11746             :     case AMDGPU::VGPR177_VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_128; break;
   11747             :     case AMDGPU::VGPR178_VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_128; break;
   11748             :     case AMDGPU::VGPR179_VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_128; break;
   11749             :     case AMDGPU::VGPR180_VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_128; break;
   11750             :     case AMDGPU::VGPR181_VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_128; break;
   11751             :     case AMDGPU::VGPR182_VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_128; break;
   11752             :     case AMDGPU::VGPR183_VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_128; break;
   11753             :     case AMDGPU::VGPR184_VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_128; break;
   11754             :     case AMDGPU::VGPR185_VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_128; break;
   11755             :     case AMDGPU::VGPR186_VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_128; break;
   11756             :     case AMDGPU::VGPR187_VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_128; break;
   11757             :     case AMDGPU::VGPR188_VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_128; break;
   11758             :     case AMDGPU::VGPR189_VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_128; break;
   11759             :     case AMDGPU::VGPR190_VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_128; break;
   11760             :     case AMDGPU::VGPR191_VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_128; break;
   11761             :     case AMDGPU::VGPR192_VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_128; break;
   11762             :     case AMDGPU::VGPR193_VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_128; break;
   11763             :     case AMDGPU::VGPR194_VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_128; break;
   11764             :     case AMDGPU::VGPR195_VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_128; break;
   11765             :     case AMDGPU::VGPR196_VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_128; break;
   11766             :     case AMDGPU::VGPR197_VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_128; break;
   11767             :     case AMDGPU::VGPR198_VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_128; break;
   11768             :     case AMDGPU::VGPR199_VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_128; break;
   11769             :     case AMDGPU::VGPR200_VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_128; break;
   11770             :     case AMDGPU::VGPR201_VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_128; break;
   11771             :     case AMDGPU::VGPR202_VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_128; break;
   11772             :     case AMDGPU::VGPR203_VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_128; break;
   11773             :     case AMDGPU::VGPR204_VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_128; break;
   11774             :     case AMDGPU::VGPR205_VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_128; break;
   11775             :     case AMDGPU::VGPR206_VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_128; break;
   11776             :     case AMDGPU::VGPR207_VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_128; break;
   11777             :     case AMDGPU::VGPR208_VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_128; break;
   11778             :     case AMDGPU::VGPR209_VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_128; break;
   11779             :     case AMDGPU::VGPR210_VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_128; break;
   11780             :     case AMDGPU::VGPR211_VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_128; break;
   11781             :     case AMDGPU::VGPR212_VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_128; break;
   11782             :     case AMDGPU::VGPR213_VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_128; break;
   11783             :     case AMDGPU::VGPR214_VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_128; break;
   11784             :     case AMDGPU::VGPR215_VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_128; break;
   11785             :     case AMDGPU::VGPR216_VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_128; break;
   11786             :     case AMDGPU::VGPR217_VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_128; break;
   11787             :     case AMDGPU::VGPR218_VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_128; break;
   11788             :     case AMDGPU::VGPR219_VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_128; break;
   11789             :     case AMDGPU::VGPR220_VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_128; break;
   11790             :     case AMDGPU::VGPR221_VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_128; break;
   11791             :     case AMDGPU::VGPR222_VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_128; break;
   11792             :     case AMDGPU::VGPR223_VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_128; break;
   11793             :     case AMDGPU::VGPR224_VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_128; break;
   11794             :     case AMDGPU::VGPR225_VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_128; break;
   11795             :     case AMDGPU::VGPR226_VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_128; break;
   11796             :     case AMDGPU::VGPR227_VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_128; break;
   11797             :     case AMDGPU::VGPR228_VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_128; break;
   11798             :     case AMDGPU::VGPR229_VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_128; break;
   11799             :     case AMDGPU::VGPR230_VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_128; break;
   11800             :     case AMDGPU::VGPR231_VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_128; break;
   11801             :     case AMDGPU::VGPR232_VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_128; break;
   11802             :     case AMDGPU::VGPR233_VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_128; break;
   11803             :     case AMDGPU::VGPR234_VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_128; break;
   11804             :     case AMDGPU::VGPR235_VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_128; break;
   11805             :     case AMDGPU::VGPR236_VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_128; break;
   11806             :     case AMDGPU::VGPR237_VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_128; break;
   11807             :     case AMDGPU::VGPR238_VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_128; break;
   11808             :     case AMDGPU::VGPR239_VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_128; break;
   11809             :     case AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_128; break;
   11810             :     case AMDGPU::VGPR241_VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_128; break;
   11811             :     case AMDGPU::VGPR242_VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_128; break;
   11812             :     case AMDGPU::VGPR243_VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_128; break;
   11813             :     case AMDGPU::VGPR244_VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_128; break;
   11814             :     case AMDGPU::VGPR245_VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_128; break;
   11815             :     case AMDGPU::VGPR246_VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_128; break;
   11816             :     case AMDGPU::VGPR247_VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_128; break;
   11817             :     case AMDGPU::VGPR248_VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_128; break;
   11818             :     case AMDGPU::VGPR249_VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_128; break;
   11819             :     case AMDGPU::VGPR250_VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_128; break;
   11820             :     case AMDGPU::VGPR251_VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_128; break;
   11821             :     case AMDGPU::VGPR252_VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_128; break;
   11822             :     case AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7: OpKind = MCK_VReg_256; break;
   11823             :     case AMDGPU::VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8: OpKind = MCK_VReg_256; break;
   11824             :     case AMDGPU::VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9: OpKind = MCK_VReg_256; break;
   11825             :     case AMDGPU::VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10: OpKind = MCK_VReg_256; break;
   11826             :     case AMDGPU::VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11: OpKind = MCK_VReg_256; break;
   11827             :     case AMDGPU::VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12: OpKind = MCK_VReg_256; break;
   11828             :     case AMDGPU::VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13: OpKind = MCK_VReg_256; break;
   11829             :     case AMDGPU::VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14: OpKind = MCK_VReg_256; break;
   11830             :     case AMDGPU::VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_256; break;
   11831             :     case AMDGPU::VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_256; break;
   11832             :     case AMDGPU::VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_256; break;
   11833             :     case AMDGPU::VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_256; break;
   11834             :     case AMDGPU::VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_256; break;
   11835             :     case AMDGPU::VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_256; break;
   11836             :     case AMDGPU::VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_256; break;
   11837             :     case AMDGPU::VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_256; break;
   11838             :     case AMDGPU::VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_256; break;
   11839             :     case AMDGPU::VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_256; break;
   11840             :     case AMDGPU::VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_256; break;
   11841             :     case AMDGPU::VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_256; break;
   11842             :     case AMDGPU::VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_256; break;
   11843             :     case AMDGPU::VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_256; break;
   11844             :     case AMDGPU::VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_256; break;
   11845             :     case AMDGPU::VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_256; break;
   11846             :     case AMDGPU::VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_256; break;
   11847             :     case AMDGPU::VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_256; break;
   11848             :     case AMDGPU::VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_256; break;
   11849             :     case AMDGPU::VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_256; break;
   11850             :     case AMDGPU::VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_256; break;
   11851             :     case AMDGPU::VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_256; break;
   11852             :     case AMDGPU::VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_256; break;
   11853             :     case AMDGPU::VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_256; break;
   11854             :     case AMDGPU::VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_256; break;
   11855             :     case AMDGPU::VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_256; break;
   11856             :     case AMDGPU::VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_256; break;
   11857             :     case AMDGPU::VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_256; break;
   11858             :     case AMDGPU::VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_256; break;
   11859             :     case AMDGPU::VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_256; break;
   11860             :     case AMDGPU::VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_256; break;
   11861             :     case AMDGPU::VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_256; break;
   11862             :     case AMDGPU::VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_256; break;
   11863             :     case AMDGPU::VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_256; break;
   11864             :     case AMDGPU::VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_256; break;
   11865             :     case AMDGPU::VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_256; break;
   11866             :     case AMDGPU::VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_256; break;
   11867             :     case AMDGPU::VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_256; break;
   11868             :     case AMDGPU::VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_256; break;
   11869             :     case AMDGPU::VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_256; break;
   11870             :     case AMDGPU::VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_256; break;
   11871             :     case AMDGPU::VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_256; break;
   11872             :     case AMDGPU::VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_256; break;
   11873             :     case AMDGPU::VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_256; break;
   11874             :     case AMDGPU::VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_256; break;
   11875             :     case AMDGPU::VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_256; break;
   11876             :     case AMDGPU::VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_256; break;
   11877             :     case AMDGPU::VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_256; break;
   11878             :     case AMDGPU::VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_256; break;
   11879             :     case AMDGPU::VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_256; break;
   11880             :     case AMDGPU::VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_256; break;
   11881             :     case AMDGPU::VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_256; break;
   11882             :     case AMDGPU::VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_256; break;
   11883             :     case AMDGPU::VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_256; break;
   11884             :     case AMDGPU::VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_256; break;
   11885             :     case AMDGPU::VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_256; break;
   11886             :     case AMDGPU::VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_256; break;
   11887             :     case AMDGPU::VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_256; break;
   11888             :     case AMDGPU::VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_256; break;
   11889             :     case AMDGPU::VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_256; break;
   11890             :     case AMDGPU::VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_256; break;
   11891             :     case AMDGPU::VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_256; break;
   11892             :     case AMDGPU::VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_256; break;
   11893             :     case AMDGPU::VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_256; break;
   11894             :     case AMDGPU::VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_256; break;
   11895             :     case AMDGPU::VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_256; break;
   11896             :     case AMDGPU::VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_256; break;
   11897             :     case AMDGPU::VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_256; break;
   11898             :     case AMDGPU::VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_256; break;
   11899             :     case AMDGPU::VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_256; break;
   11900             :     case AMDGPU::VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_256; break;
   11901             :     case AMDGPU::VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_256; break;
   11902             :     case AMDGPU::VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_256; break;
   11903             :     case AMDGPU::VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_256; break;
   11904             :     case AMDGPU::VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_256; break;
   11905             :     case AMDGPU::VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_256; break;
   11906             :     case AMDGPU::VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_256; break;
   11907             :     case AMDGPU::VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_256; break;
   11908             :     case AMDGPU::VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_256; break;
   11909             :     case AMDGPU::VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_256; break;
   11910             :     case AMDGPU::VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_256; break;
   11911             :     case AMDGPU::VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_256; break;
   11912             :     case AMDGPU::VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_256; break;
   11913             :     case AMDGPU::VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_256; break;
   11914             :     case AMDGPU::VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_256; break;
   11915             :     case AMDGPU::VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_256; break;
   11916             :     case AMDGPU::VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_256; break;
   11917             :     case AMDGPU::VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_256; break;
   11918             :     case AMDGPU::VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_256; break;
   11919             :     case AMDGPU::VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_256; break;
   11920             :     case AMDGPU::VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_256; break;
   11921             :     case AMDGPU::VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_256; break;
   11922             :     case AMDGPU::VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_256; break;
   11923             :     case AMDGPU::VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_256; break;
   11924             :     case AMDGPU::VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_256; break;
   11925             :     case AMDGPU::VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_256; break;
   11926             :     case AMDGPU::VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_256; break;
   11927             :     case AMDGPU::VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_256; break;
   11928             :     case AMDGPU::VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_256; break;
   11929             :     case AMDGPU::VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_256; break;
   11930             :     case AMDGPU::VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_256; break;
   11931             :     case AMDGPU::VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_256; break;
   11932             :     case AMDGPU::VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_256; break;
   11933             :     case AMDGPU::VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_256; break;
   11934             :     case AMDGPU::VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_256; break;
   11935             :     case AMDGPU::VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_256; break;
   11936             :     case AMDGPU::VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_256; break;
   11937             :     case AMDGPU::VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_256; break;
   11938             :     case AMDGPU::VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_256; break;
   11939             :     case AMDGPU::VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_256; break;
   11940             :     case AMDGPU::VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_256; break;
   11941             :     case AMDGPU::VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_256; break;
   11942             :     case AMDGPU::VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_256; break;
   11943             :     case AMDGPU::VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_256; break;
   11944             :     case AMDGPU::VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_256; break;
   11945             :     case AMDGPU::VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_256; break;
   11946             :     case AMDGPU::VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_256; break;
   11947             :     case AMDGPU::VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_256; break;
   11948             :     case AMDGPU::VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_256; break;
   11949             :     case AMDGPU::VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_256; break;
   11950             :     case AMDGPU::VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_256; break;
   11951             :     case AMDGPU::VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_256; break;
   11952             :     case AMDGPU::VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_256; break;
   11953             :     case AMDGPU::VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_256; break;
   11954             :     case AMDGPU::VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_256; break;
   11955             :     case AMDGPU::VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_256; break;
   11956             :     case AMDGPU::VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_256; break;
   11957             :     case AMDGPU::VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_256; break;
   11958             :     case AMDGPU::VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_256; break;
   11959             :     case AMDGPU::VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_256; break;
   11960             :     case AMDGPU::VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_256; break;
   11961             :     case AMDGPU::VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_256; break;
   11962             :     case AMDGPU::VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_256; break;
   11963             :     case AMDGPU::VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_256; break;
   11964             :     case AMDGPU::VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_256; break;
   11965             :     case AMDGPU::VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_256; break;
   11966             :     case AMDGPU::VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_256; break;
   11967             :     case AMDGPU::VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_256; break;
   11968             :     case AMDGPU::VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_256; break;
   11969             :     case AMDGPU::VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_256; break;
   11970             :     case AMDGPU::VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_256; break;
   11971             :     case AMDGPU::VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_256; break;
   11972             :     case AMDGPU::VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_256; break;
   11973             :     case AMDGPU::VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_256; break;
   11974             :     case AMDGPU::VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_256; break;
   11975             :     case AMDGPU::VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_256; break;
   11976             :     case AMDGPU::VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_256; break;
   11977             :     case AMDGPU::VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_256; break;
   11978             :     case AMDGPU::VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_256; break;
   11979             :     case AMDGPU::VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_256; break;
   11980             :     case AMDGPU::VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_256; break;
   11981             :     case AMDGPU::VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_256; break;
   11982             :     case AMDGPU::VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_256; break;
   11983             :     case AMDGPU::VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_256; break;
   11984             :     case AMDGPU::VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_256; break;
   11985             :     case AMDGPU::VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_256; break;
   11986             :     case AMDGPU::VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_256; break;
   11987             :     case AMDGPU::VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_256; break;
   11988             :     case AMDGPU::VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_256; break;
   11989             :     case AMDGPU::VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_256; break;
   11990             :     case AMDGPU::VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_256; break;
   11991             :     case AMDGPU::VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_256; break;
   11992             :     case AMDGPU::VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_256; break;
   11993             :     case AMDGPU::VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_256; break;
   11994             :     case AMDGPU::VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_256; break;
   11995             :     case AMDGPU::VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_256; break;
   11996             :     case AMDGPU::VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_256; break;
   11997             :     case AMDGPU::VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_256; break;
   11998             :     case AMDGPU::VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_256; break;
   11999             :     case AMDGPU::VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_256; break;
   12000             :     case AMDGPU::VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_256; break;
   12001             :     case AMDGPU::VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_256; break;
   12002             :     case AMDGPU::VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_256; break;
   12003             :     case AMDGPU::VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_256; break;
   12004             :     case AMDGPU::VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_256; break;
   12005             :     case AMDGPU::VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_256; break;
   12006             :     case AMDGPU::VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_256; break;
   12007             :     case AMDGPU::VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_256; break;
   12008             :     case AMDGPU::VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_256; break;
   12009             :     case AMDGPU::VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_256; break;
   12010             :     case AMDGPU::VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_256; break;
   12011             :     case AMDGPU::VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_256; break;
   12012             :     case AMDGPU::VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_256; break;
   12013             :     case AMDGPU::VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_256; break;
   12014             :     case AMDGPU::VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_256; break;
   12015             :     case AMDGPU::VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_256; break;
   12016             :     case AMDGPU::VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_256; break;
   12017             :     case AMDGPU::VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_256; break;
   12018             :     case AMDGPU::VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_256; break;
   12019             :     case AMDGPU::VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_256; break;
   12020             :     case AMDGPU::VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_256; break;
   12021             :     case AMDGPU::VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_256; break;
   12022             :     case AMDGPU::VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_256; break;
   12023             :     case AMDGPU::VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_256; break;
   12024             :     case AMDGPU::VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_256; break;
   12025             :     case AMDGPU::VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_256; break;
   12026             :     case AMDGPU::VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_256; break;
   12027             :     case AMDGPU::VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_256; break;
   12028             :     case AMDGPU::VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_256; break;
   12029             :     case AMDGPU::VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_256; break;
   12030             :     case AMDGPU::VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_256; break;
   12031             :     case AMDGPU::VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_256; break;
   12032             :     case AMDGPU::VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_256; break;
   12033             :     case AMDGPU::VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_256; break;
   12034             :     case AMDGPU::VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_256; break;
   12035             :     case AMDGPU::VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_256; break;
   12036             :     case AMDGPU::VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_256; break;
   12037             :     case AMDGPU::VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_256; break;
   12038             :     case AMDGPU::VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_256; break;
   12039             :     case AMDGPU::VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_256; break;
   12040             :     case AMDGPU::VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_256; break;
   12041             :     case AMDGPU::VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_256; break;
   12042             :     case AMDGPU::VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_256; break;
   12043             :     case AMDGPU::VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_256; break;
   12044             :     case AMDGPU::VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_256; break;
   12045             :     case AMDGPU::VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_256; break;
   12046             :     case AMDGPU::VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_256; break;
   12047             :     case AMDGPU::VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_256; break;
   12048             :     case AMDGPU::VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_256; break;
   12049             :     case AMDGPU::VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_256; break;
   12050             :     case AMDGPU::VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_256; break;
   12051             :     case AMDGPU::VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_256; break;
   12052             :     case AMDGPU::VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_256; break;
   12053             :     case AMDGPU::VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_256; break;
   12054             :     case AMDGPU::VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_256; break;
   12055             :     case AMDGPU::VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_256; break;
   12056             :     case AMDGPU::VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_256; break;
   12057             :     case AMDGPU::VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_256; break;
   12058             :     case AMDGPU::VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_256; break;
   12059             :     case AMDGPU::VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_256; break;
   12060             :     case AMDGPU::VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_256; break;
   12061             :     case AMDGPU::VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_256; break;
   12062             :     case AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_256; break;
   12063             :     case AMDGPU::VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_256; break;
   12064             :     case AMDGPU::VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_256; break;
   12065             :     case AMDGPU::VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_256; break;
   12066             :     case AMDGPU::VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_256; break;
   12067             :     case AMDGPU::VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_256; break;
   12068             :     case AMDGPU::VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_256; break;
   12069             :     case AMDGPU::VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_256; break;
   12070             :     case AMDGPU::VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_256; break;
   12071             :     case AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_512; break;
   12072             :     case AMDGPU::VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_512; break;
   12073             :     case AMDGPU::VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_512; break;
   12074             :     case AMDGPU::VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_512; break;
   12075             :     case AMDGPU::VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_512; break;
   12076             :     case AMDGPU::VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_512; break;
   12077             :     case AMDGPU::VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_512; break;
   12078             :     case AMDGPU::VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_512; break;
   12079             :     case AMDGPU::VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_512; break;
   12080             :     case AMDGPU::VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_512; break;
   12081             :     case AMDGPU::VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_512; break;
   12082             :     case AMDGPU::VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_512; break;
   12083             :     case AMDGPU::VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_512; break;
   12084             :     case AMDGPU::VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_512; break;
   12085             :     case AMDGPU::VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_512; break;
   12086             :     case AMDGPU::VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_512; break;
   12087             :     case AMDGPU::VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_512; break;
   12088             :     case AMDGPU::VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_512; break;
   12089             :     case AMDGPU::VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_512; break;
   12090             :     case AMDGPU::VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_512; break;
   12091             :     case AMDGPU::VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_512; break;
   12092             :     case AMDGPU::VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_512; break;
   12093             :     case AMDGPU::VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_512; break;
   12094             :     case AMDGPU::VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_512; break;
   12095             :     case AMDGPU::VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_512; break;
   12096             :     case AMDGPU::VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_512; break;
   12097             :     case AMDGPU::VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_512; break;
   12098             :     case AMDGPU::VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_512; break;
   12099             :     case AMDGPU::VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_512; break;
   12100             :     case AMDGPU::VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_512; break;
   12101             :     case AMDGPU::VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_512; break;
   12102             :     case AMDGPU::VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_512; break;
   12103             :     case AMDGPU::VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_512; break;
   12104             :     case AMDGPU::VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_512; break;
   12105             :     case AMDGPU::VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_512; break;
   12106             :     case AMDGPU::VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_512; break;
   12107             :     case AMDGPU::VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_512; break;
   12108             :     case AMDGPU::VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_512; break;
   12109             :     case AMDGPU::VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_512; break;
   12110             :     case AMDGPU::VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_512; break;
   12111             :     case AMDGPU::VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_512; break;
   12112             :     case AMDGPU::VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_512; break;
   12113             :     case AMDGPU::VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_512; break;
   12114             :     case AMDGPU::VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_512; break;
   12115             :     case AMDGPU::VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_512; break;
   12116             :     case AMDGPU::VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_512; break;
   12117             :     case AMDGPU::VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_512; break;
   12118             :     case AMDGPU::VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_512; break;
   12119             :     case AMDGPU::VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_512; break;
   12120             :     case AMDGPU::VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_512; break;
   12121             :     case AMDGPU::VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_512; break;
   12122             :     case AMDGPU::VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_512; break;
   12123             :     case AMDGPU::VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_512; break;
   12124             :     case AMDGPU::VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_512; break;
   12125             :     case AMDGPU::VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_512; break;
   12126             :     case AMDGPU::VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_512; break;
   12127             :     case AMDGPU::VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_512; break;
   12128             :     case AMDGPU::VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_512; break;
   12129             :     case AMDGPU::VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_512; break;
   12130             :     case AMDGPU::VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_512; break;
   12131             :     case AMDGPU::VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_512; break;
   12132             :     case AMDGPU::VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_512; break;
   12133             :     case AMDGPU::VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_512; break;
   12134             :     case AMDGPU::VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_512; break;
   12135             :     case AMDGPU::VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_512; break;
   12136             :     case AMDGPU::VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_512; break;
   12137             :     case AMDGPU::VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_512; break;
   12138             :     case AMDGPU::VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_512; break;
   12139             :     case AMDGPU::VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_512; break;
   12140             :     case AMDGPU::VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_512; break;
   12141             :     case AMDGPU::VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_512; break;
   12142             :     case AMDGPU::VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_512; break;
   12143             :     case AMDGPU::VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_512; break;
   12144             :     case AMDGPU::VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_512; break;
   12145             :     case AMDGPU::VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_512; break;
   12146             :     case AMDGPU::VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_512; break;
   12147             :     case AMDGPU::VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_512; break;
   12148             :     case AMDGPU::VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_512; break;
   12149             :     case AMDGPU::VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_512; break;
   12150             :     case AMDGPU::VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_512; break;
   12151             :     case AMDGPU::VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_512; break;
   12152             :     case AMDGPU::VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_512; break;
   12153             :     case AMDGPU::VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_512; break;
   12154             :     case AMDGPU::VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_512; break;
   12155             :     case AMDGPU::VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_512; break;
   12156             :     case AMDGPU::VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_512; break;
   12157             :     case AMDGPU::VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_512; break;
   12158             :     case AMDGPU::VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_512; break;
   12159             :     case AMDGPU::VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_512; break;
   12160             :     case AMDGPU::VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_512; break;
   12161             :     case AMDGPU::VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_512; break;
   12162             :     case AMDGPU::VGPR91_VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_512; break;
   12163             :     case AMDGPU::VGPR92_VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_512; break;
   12164             :     case AMDGPU::VGPR93_VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_512; break;
   12165             :     case AMDGPU::VGPR94_VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_512; break;
   12166             :     case AMDGPU::VGPR95_VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_512; break;
   12167             :     case AMDGPU::VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_512; break;
   12168             :     case AMDGPU::VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_512; break;
   12169             :     case AMDGPU::VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_512; break;
   12170             :     case AMDGPU::VGPR99_VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_512; break;
   12171             :     case AMDGPU::VGPR100_VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_512; break;
   12172             :     case AMDGPU::VGPR101_VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_512; break;
   12173             :     case AMDGPU::VGPR102_VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_512; break;
   12174             :     case AMDGPU::VGPR103_VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_512; break;
   12175             :     case AMDGPU::VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_512; break;
   12176             :     case AMDGPU::VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_512; break;
   12177             :     case AMDGPU::VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_512; break;
   12178             :     case AMDGPU::VGPR107_VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_512; break;
   12179             :     case AMDGPU::VGPR108_VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_512; break;
   12180             :     case AMDGPU::VGPR109_VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_512; break;
   12181             :     case AMDGPU::VGPR110_VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_512; break;
   12182             :     case AMDGPU::VGPR111_VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_512; break;
   12183             :     case AMDGPU::VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_512; break;
   12184             :     case AMDGPU::VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_512; break;
   12185             :     case AMDGPU::VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_512; break;
   12186             :     case AMDGPU::VGPR115_VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_512; break;
   12187             :     case AMDGPU::VGPR116_VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_512; break;
   12188             :     case AMDGPU::VGPR117_VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_512; break;
   12189             :     case AMDGPU::VGPR118_VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_512; break;
   12190             :     case AMDGPU::VGPR119_VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_512; break;
   12191             :     case AMDGPU::VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_512; break;
   12192             :     case AMDGPU::VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_512; break;
   12193             :     case AMDGPU::VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_512; break;
   12194             :     case AMDGPU::VGPR123_VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_512; break;
   12195             :     case AMDGPU::VGPR124_VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_512; break;
   12196             :     case AMDGPU::VGPR125_VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_512; break;
   12197             :     case AMDGPU::VGPR126_VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_512; break;
   12198             :     case AMDGPU::VGPR127_VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_512; break;
   12199             :     case AMDGPU::VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_512; break;
   12200             :     case AMDGPU::VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_512; break;
   12201             :     case AMDGPU::VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_512; break;
   12202             :     case AMDGPU::VGPR131_VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_512; break;
   12203             :     case AMDGPU::VGPR132_VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_512; break;
   12204             :     case AMDGPU::VGPR133_VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_512; break;
   12205             :     case AMDGPU::VGPR134_VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_512; break;
   12206             :     case AMDGPU::VGPR135_VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_512; break;
   12207             :     case AMDGPU::VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_512; break;
   12208             :     case AMDGPU::VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_512; break;
   12209             :     case AMDGPU::VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_512; break;
   12210             :     case AMDGPU::VGPR139_VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_512; break;
   12211             :     case AMDGPU::VGPR140_VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_512; break;
   12212             :     case AMDGPU::VGPR141_VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_512; break;
   12213             :     case AMDGPU::VGPR142_VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_512; break;
   12214             :     case AMDGPU::VGPR143_VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_512; break;
   12215             :     case AMDGPU::VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_512; break;
   12216             :     case AMDGPU::VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_512; break;
   12217             :     case AMDGPU::VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_512; break;
   12218             :     case AMDGPU::VGPR147_VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_512; break;
   12219             :     case AMDGPU::VGPR148_VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_512; break;
   12220             :     case AMDGPU::VGPR149_VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_512; break;
   12221             :     case AMDGPU::VGPR150_VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_512; break;
   12222             :     case AMDGPU::VGPR151_VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_512; break;
   12223             :     case AMDGPU::VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_512; break;
   12224             :     case AMDGPU::VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_512; break;
   12225             :     case AMDGPU::VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_512; break;
   12226             :     case AMDGPU::VGPR155_VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_512; break;
   12227             :     case AMDGPU::VGPR156_VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_512; break;
   12228             :     case AMDGPU::VGPR157_VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_512; break;
   12229             :     case AMDGPU::VGPR158_VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_512; break;
   12230             :     case AMDGPU::VGPR159_VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_512; break;
   12231             :     case AMDGPU::VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_512; break;
   12232             :     case AMDGPU::VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_512; break;
   12233             :     case AMDGPU::VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_512; break;
   12234             :     case AMDGPU::VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_512; break;
   12235             :     case AMDGPU::VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_512; break;
   12236             :     case AMDGPU::VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_512; break;
   12237             :     case AMDGPU::VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_512; break;
   12238             :     case AMDGPU::VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_512; break;
   12239             :     case AMDGPU::VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_512; break;
   12240             :     case AMDGPU::VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_512; break;
   12241             :     case AMDGPU::VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_512; break;
   12242             :     case AMDGPU::VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_512; break;
   12243             :     case AMDGPU::VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_512; break;
   12244             :     case AMDGPU::VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_512; break;
   12245             :     case AMDGPU::VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_512; break;
   12246             :     case AMDGPU::VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_512; break;
   12247             :     case AMDGPU::VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_512; break;
   12248             :     case AMDGPU::VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_512; break;
   12249             :     case AMDGPU::VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_512; break;
   12250             :     case AMDGPU::VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_512; break;
   12251             :     case AMDGPU::VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_512; break;
   12252             :     case AMDGPU::VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_512; break;
   12253             :     case AMDGPU::VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_512; break;
   12254             :     case AMDGPU::VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_512; break;
   12255             :     case AMDGPU::VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_512; break;
   12256             :     case AMDGPU::VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_512; break;
   12257             :     case AMDGPU::VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_512; break;
   12258             :     case AMDGPU::VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_512; break;
   12259             :     case AMDGPU::VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_512; break;
   12260             :     case AMDGPU::VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_512; break;
   12261             :     case AMDGPU::VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_512; break;
   12262             :     case AMDGPU::VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_512; break;
   12263             :     case AMDGPU::VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_512; break;
   12264             :     case AMDGPU::VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_512; break;
   12265             :     case AMDGPU::VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_512; break;
   12266             :     case AMDGPU::VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_512; break;
   12267             :     case AMDGPU::VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_512; break;
   12268             :     case AMDGPU::VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_512; break;
   12269             :     case AMDGPU::VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_512; break;
   12270             :     case AMDGPU::VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_512; break;
   12271             :     case AMDGPU::VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_512; break;
   12272             :     case AMDGPU::VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_512; break;
   12273             :     case AMDGPU::VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_512; break;
   12274             :     case AMDGPU::VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_512; break;
   12275             :     case AMDGPU::VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_512; break;
   12276             :     case AMDGPU::VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_512; break;
   12277             :     case AMDGPU::VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_512; break;
   12278             :     case AMDGPU::VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_512; break;
   12279             :     case AMDGPU::VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_512; break;
   12280             :     case AMDGPU::VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_512; break;
   12281             :     case AMDGPU::VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_512; break;
   12282             :     case AMDGPU::VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_512; break;
   12283             :     case AMDGPU::VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_512; break;
   12284             :     case AMDGPU::VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_512; break;
   12285             :     case AMDGPU::VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_512; break;
   12286             :     case AMDGPU::VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_512; break;
   12287             :     case AMDGPU::VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_512; break;
   12288             :     case AMDGPU::VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_512; break;
   12289             :     case AMDGPU::VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_512; break;
   12290             :     case AMDGPU::VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_512; break;
   12291             :     case AMDGPU::VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_512; break;
   12292             :     case AMDGPU::VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_512; break;
   12293             :     case AMDGPU::VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_512; break;
   12294             :     case AMDGPU::VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_512; break;
   12295             :     case AMDGPU::VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_512; break;
   12296             :     case AMDGPU::VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_512; break;
   12297             :     case AMDGPU::VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_512; break;
   12298             :     case AMDGPU::VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_512; break;
   12299             :     case AMDGPU::VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_512; break;
   12300             :     case AMDGPU::VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_512; break;
   12301             :     case AMDGPU::VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_512; break;
   12302             :     case AMDGPU::VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_512; break;
   12303             :     case AMDGPU::VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_512; break;
   12304             :     case AMDGPU::VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_512; break;
   12305             :     case AMDGPU::VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_512; break;
   12306             :     case AMDGPU::VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_512; break;
   12307             :     case AMDGPU::VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_512; break;
   12308             :     case AMDGPU::VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_512; break;
   12309             :     case AMDGPU::VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_512; break;
   12310             :     case AMDGPU::VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_512; break;
   12311             :     case AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_512; break;
   12312             :     case AMDGPU::VGPR0_VGPR1: OpKind = MCK_VReg_64; break;
   12313             :     case AMDGPU::VGPR1_VGPR2: OpKind = MCK_VReg_64; break;
   12314             :     case AMDGPU::VGPR2_VGPR3: OpKind = MCK_VReg_64; break;
   12315             :     case AMDGPU::VGPR3_VGPR4: OpKind = MCK_VReg_64; break;
   12316             :     case AMDGPU::VGPR4_VGPR5: OpKind = MCK_VReg_64; break;
   12317             :     case AMDGPU::VGPR5_VGPR6: OpKind = MCK_VReg_64; break;
   12318             :     case AMDGPU::VGPR6_VGPR7: OpKind = MCK_VReg_64; break;
   12319             :     case AMDGPU::VGPR7_VGPR8: OpKind = MCK_VReg_64; break;
   12320             :     case AMDGPU::VGPR8_VGPR9: OpKind = MCK_VReg_64; break;
   12321             :     case AMDGPU::VGPR9_VGPR10: OpKind = MCK_VReg_64; break;
   12322             :     case AMDGPU::VGPR10_VGPR11: OpKind = MCK_VReg_64; break;
   12323             :     case AMDGPU::VGPR11_VGPR12: OpKind = MCK_VReg_64; break;
   12324             :     case AMDGPU::VGPR12_VGPR13: OpKind = MCK_VReg_64; break;
   12325             :     case AMDGPU::VGPR13_VGPR14: OpKind = MCK_VReg_64; break;
   12326             :     case AMDGPU::VGPR14_VGPR15: OpKind = MCK_VReg_64; break;
   12327             :     case AMDGPU::VGPR15_VGPR16: OpKind = MCK_VReg_64; break;
   12328             :     case AMDGPU::VGPR16_VGPR17: OpKind = MCK_VReg_64; break;
   12329             :     case AMDGPU::VGPR17_VGPR18: OpKind = MCK_VReg_64; break;
   12330             :     case AMDGPU::VGPR18_VGPR19: OpKind = MCK_VReg_64; break;
   12331             :     case AMDGPU::VGPR19_VGPR20: OpKind = MCK_VReg_64; break;
   12332             :     case AMDGPU::VGPR20_VGPR21: OpKind = MCK_VReg_64; break;
   12333             :     case AMDGPU::VGPR21_VGPR22: OpKind = MCK_VReg_64; break;
   12334             :     case AMDGPU::VGPR22_VGPR23: OpKind = MCK_VReg_64; break;
   12335             :     case AMDGPU::VGPR23_VGPR24: OpKind = MCK_VReg_64; break;
   12336             :     case AMDGPU::VGPR24_VGPR25: OpKind = MCK_VReg_64; break;
   12337             :     case AMDGPU::VGPR25_VGPR26: OpKind = MCK_VReg_64; break;
   12338             :     case AMDGPU::VGPR26_VGPR27: OpKind = MCK_VReg_64; break;
   12339             :     case AMDGPU::VGPR27_VGPR28: OpKind = MCK_VReg_64; break;
   12340             :     case AMDGPU::VGPR28_VGPR29: OpKind = MCK_VReg_64; break;
   12341             :     case AMDGPU::VGPR29_VGPR30: OpKind = MCK_VReg_64; break;
   12342             :     case AMDGPU::VGPR30_VGPR31: OpKind = MCK_VReg_64; break;
   12343             :     case AMDGPU::VGPR31_VGPR32: OpKind = MCK_VReg_64; break;
   12344             :     case AMDGPU::VGPR32_VGPR33: OpKind = MCK_VReg_64; break;
   12345             :     case AMDGPU::VGPR33_VGPR34: OpKind = MCK_VReg_64; break;
   12346             :     case AMDGPU::VGPR34_VGPR35: OpKind = MCK_VReg_64; break;
   12347             :     case AMDGPU::VGPR35_VGPR36: OpKind = MCK_VReg_64; break;
   12348             :     case AMDGPU::VGPR36_VGPR37: OpKind = MCK_VReg_64; break;
   12349             :     case AMDGPU::VGPR37_VGPR38: OpKind = MCK_VReg_64; break;
   12350             :     case AMDGPU::VGPR38_VGPR39: OpKind = MCK_VReg_64; break;
   12351             :     case AMDGPU::VGPR39_VGPR40: OpKind = MCK_VReg_64; break;
   12352             :     case AMDGPU::VGPR40_VGPR41: OpKind = MCK_VReg_64; break;
   12353             :     case AMDGPU::VGPR41_VGPR42: OpKind = MCK_VReg_64; break;
   12354             :     case AMDGPU::VGPR42_VGPR43: OpKind = MCK_VReg_64; break;
   12355             :     case AMDGPU::VGPR43_VGPR44: OpKind = MCK_VReg_64; break;
   12356             :     case AMDGPU::VGPR44_VGPR45: OpKind = MCK_VReg_64; break;
   12357             :     case AMDGPU::VGPR45_VGPR46: OpKind = MCK_VReg_64; break;
   12358             :     case AMDGPU::VGPR46_VGPR47: OpKind = MCK_VReg_64; break;
   12359             :     case AMDGPU::VGPR47_VGPR48: OpKind = MCK_VReg_64; break;
   12360             :     case AMDGPU::VGPR48_VGPR49: OpKind = MCK_VReg_64; break;
   12361             :     case AMDGPU::VGPR49_VGPR50: OpKind = MCK_VReg_64; break;
   12362             :     case AMDGPU::VGPR50_VGPR51: OpKind = MCK_VReg_64; break;
   12363             :     case AMDGPU::VGPR51_VGPR52: OpKind = MCK_VReg_64; break;
   12364             :     case AMDGPU::VGPR52_VGPR53: OpKind = MCK_VReg_64; break;
   12365             :     case AMDGPU::VGPR53_VGPR54: OpKind = MCK_VReg_64; break;
   12366             :     case AMDGPU::VGPR54_VGPR55: OpKind = MCK_VReg_64; break;
   12367             :     case AMDGPU::VGPR55_VGPR56: OpKind = MCK_VReg_64; break;
   12368             :     case AMDGPU::VGPR56_VGPR57: OpKind = MCK_VReg_64; break;
   12369             :     case AMDGPU::VGPR57_VGPR58: OpKind = MCK_VReg_64; break;
   12370             :     case AMDGPU::VGPR58_VGPR59: OpKind = MCK_VReg_64; break;
   12371             :     case AMDGPU::VGPR59_VGPR60: OpKind = MCK_VReg_64; break;
   12372             :     case AMDGPU::VGPR60_VGPR61: OpKind = MCK_VReg_64; break;
   12373             :     case AMDGPU::VGPR61_VGPR62: OpKind = MCK_VReg_64; break;
   12374             :     case AMDGPU::VGPR62_VGPR63: OpKind = MCK_VReg_64; break;
   12375             :     case AMDGPU::VGPR63_VGPR64: OpKind = MCK_VReg_64; break;
   12376             :     case AMDGPU::VGPR64_VGPR65: OpKind = MCK_VReg_64; break;
   12377             :     case AMDGPU::VGPR65_VGPR66: OpKind = MCK_VReg_64; break;
   12378             :     case AMDGPU::VGPR66_VGPR67: OpKind = MCK_VReg_64; break;
   12379             :     case AMDGPU::VGPR67_VGPR68: OpKind = MCK_VReg_64; break;
   12380             :     case AMDGPU::VGPR68_VGPR69: OpKind = MCK_VReg_64; break;
   12381             :     case AMDGPU::VGPR69_VGPR70: OpKind = MCK_VReg_64; break;
   12382             :     case AMDGPU::VGPR70_VGPR71: OpKind = MCK_VReg_64; break;
   12383             :     case AMDGPU::VGPR71_VGPR72: OpKind = MCK_VReg_64; break;
   12384             :     case AMDGPU::VGPR72_VGPR73: OpKind = MCK_VReg_64; break;
   12385             :     case AMDGPU::VGPR73_VGPR74: OpKind = MCK_VReg_64; break;
   12386             :     case AMDGPU::VGPR74_VGPR75: OpKind = MCK_VReg_64; break;
   12387             :     case AMDGPU::VGPR75_VGPR76: OpKind = MCK_VReg_64; break;
   12388             :     case AMDGPU::VGPR76_VGPR77: OpKind = MCK_VReg_64; break;
   12389             :     case AMDGPU::VGPR77_VGPR78: OpKind = MCK_VReg_64; break;
   12390             :     case AMDGPU::VGPR78_VGPR79: OpKind = MCK_VReg_64; break;
   12391             :     case AMDGPU::VGPR79_VGPR80: OpKind = MCK_VReg_64; break;
   12392             :     case AMDGPU::VGPR80_VGPR81: OpKind = MCK_VReg_64; break;
   12393             :     case AMDGPU::VGPR81_VGPR82: OpKind = MCK_VReg_64; break;
   12394             :     case AMDGPU::VGPR82_VGPR83: OpKind = MCK_VReg_64; break;
   12395             :     case AMDGPU::VGPR83_VGPR84: OpKind = MCK_VReg_64; break;
   12396             :     case AMDGPU::VGPR84_VGPR85: OpKind = MCK_VReg_64; break;
   12397             :     case AMDGPU::VGPR85_VGPR86: OpKind = MCK_VReg_64; break;
   12398             :     case AMDGPU::VGPR86_VGPR87: OpKind = MCK_VReg_64; break;
   12399             :     case AMDGPU::VGPR87_VGPR88: OpKind = MCK_VReg_64; break;
   12400             :     case AMDGPU::VGPR88_VGPR89: OpKind = MCK_VReg_64; break;
   12401             :     case AMDGPU::VGPR89_VGPR90: OpKind = MCK_VReg_64; break;
   12402             :     case AMDGPU::VGPR90_VGPR91: OpKind = MCK_VReg_64; break;
   12403             :     case AMDGPU::VGPR91_VGPR92: OpKind = MCK_VReg_64; break;
   12404             :     case AMDGPU::VGPR92_VGPR93: OpKind = MCK_VReg_64; break;
   12405             :     case AMDGPU::VGPR93_VGPR94: OpKind = MCK_VReg_64; break;
   12406             :     case AMDGPU::VGPR94_VGPR95: OpKind = MCK_VReg_64; break;
   12407             :     case AMDGPU::VGPR95_VGPR96: OpKind = MCK_VReg_64; break;
   12408             :     case AMDGPU::VGPR96_VGPR97: OpKind = MCK_VReg_64; break;
   12409             :     case AMDGPU::VGPR97_VGPR98: OpKind = MCK_VReg_64; break;
   12410             :     case AMDGPU::VGPR98_VGPR99: OpKind = MCK_VReg_64; break;
   12411             :     case AMDGPU::VGPR99_VGPR100: OpKind = MCK_VReg_64; break;
   12412             :     case AMDGPU::VGPR100_VGPR101: OpKind = MCK_VReg_64; break;
   12413             :     case AMDGPU::VGPR101_VGPR102: OpKind = MCK_VReg_64; break;
   12414             :     case AMDGPU::VGPR102_VGPR103: OpKind = MCK_VReg_64; break;
   12415             :     case AMDGPU::VGPR103_VGPR104: OpKind = MCK_VReg_64; break;
   12416             :     case AMDGPU::VGPR104_VGPR105: OpKind = MCK_VReg_64; break;
   12417             :     case AMDGPU::VGPR105_VGPR106: OpKind = MCK_VReg_64; break;
   12418             :     case AMDGPU::VGPR106_VGPR107: OpKind = MCK_VReg_64; break;
   12419             :     case AMDGPU::VGPR107_VGPR108: OpKind = MCK_VReg_64; break;
   12420             :     case AMDGPU::VGPR108_VGPR109: OpKind = MCK_VReg_64; break;
   12421             :     case AMDGPU::VGPR109_VGPR110: OpKind = MCK_VReg_64; break;
   12422             :     case AMDGPU::VGPR110_VGPR111: OpKind = MCK_VReg_64; break;
   12423             :     case AMDGPU::VGPR111_VGPR112: OpKind = MCK_VReg_64; break;
   12424             :     case AMDGPU::VGPR112_VGPR113: OpKind = MCK_VReg_64; break;
   12425             :     case AMDGPU::VGPR113_VGPR114: OpKind = MCK_VReg_64; break;
   12426             :     case AMDGPU::VGPR114_VGPR115: OpKind = MCK_VReg_64; break;
   12427             :     case AMDGPU::VGPR115_VGPR116: OpKind = MCK_VReg_64; break;
   12428             :     case AMDGPU::VGPR116_VGPR117: OpKind = MCK_VReg_64; break;
   12429             :     case AMDGPU::VGPR117_VGPR118: OpKind = MCK_VReg_64; break;
   12430             :     case AMDGPU::VGPR118_VGPR119: OpKind = MCK_VReg_64; break;
   12431             :     case AMDGPU::VGPR119_VGPR120: OpKind = MCK_VReg_64; break;
   12432             :     case AMDGPU::VGPR120_VGPR121: OpKind = MCK_VReg_64; break;
   12433             :     case AMDGPU::VGPR121_VGPR122: OpKind = MCK_VReg_64; break;
   12434             :     case AMDGPU::VGPR122_VGPR123: OpKind = MCK_VReg_64; break;
   12435             :     case AMDGPU::VGPR123_VGPR124: OpKind = MCK_VReg_64; break;
   12436             :     case AMDGPU::VGPR124_VGPR125: OpKind = MCK_VReg_64; break;
   12437             :     case AMDGPU::VGPR125_VGPR126: OpKind = MCK_VReg_64; break;
   12438             :     case AMDGPU::VGPR126_VGPR127: OpKind = MCK_VReg_64; break;
   12439             :     case AMDGPU::VGPR127_VGPR128: OpKind = MCK_VReg_64; break;
   12440             :     case AMDGPU::VGPR128_VGPR129: OpKind = MCK_VReg_64; break;
   12441             :     case AMDGPU::VGPR129_VGPR130: OpKind = MCK_VReg_64; break;
   12442             :     case AMDGPU::VGPR130_VGPR131: OpKind = MCK_VReg_64; break;
   12443             :     case AMDGPU::VGPR131_VGPR132: OpKind = MCK_VReg_64; break;
   12444             :     case AMDGPU::VGPR132_VGPR133: OpKind = MCK_VReg_64; break;
   12445             :     case AMDGPU::VGPR133_VGPR134: OpKind = MCK_VReg_64; break;
   12446             :     case AMDGPU::VGPR134_VGPR135: OpKind = MCK_VReg_64; break;
   12447             :     case AMDGPU::VGPR135_VGPR136: OpKind = MCK_VReg_64; break;
   12448             :     case AMDGPU::VGPR136_VGPR137: OpKind = MCK_VReg_64; break;
   12449             :     case AMDGPU::VGPR137_VGPR138: OpKind = MCK_VReg_64; break;
   12450             :     case AMDGPU::VGPR138_VGPR139: OpKind = MCK_VReg_64; break;
   12451             :     case AMDGPU::VGPR139_VGPR140: OpKind = MCK_VReg_64; break;
   12452             :     case AMDGPU::VGPR140_VGPR141: OpKind = MCK_VReg_64; break;
   12453             :     case AMDGPU::VGPR141_VGPR142: OpKind = MCK_VReg_64; break;
   12454             :     case AMDGPU::VGPR142_VGPR143: OpKind = MCK_VReg_64; break;
   12455             :     case AMDGPU::VGPR143_VGPR144: OpKind = MCK_VReg_64; break;
   12456             :     case AMDGPU::VGPR144_VGPR145: OpKind = MCK_VReg_64; break;
   12457             :     case AMDGPU::VGPR145_VGPR146: OpKind = MCK_VReg_64; break;
   12458             :     case AMDGPU::VGPR146_VGPR147: OpKind = MCK_VReg_64; break;
   12459             :     case AMDGPU::VGPR147_VGPR148: OpKind = MCK_VReg_64; break;
   12460             :     case AMDGPU::VGPR148_VGPR149: OpKind = MCK_VReg_64; break;
   12461             :     case AMDGPU::VGPR149_VGPR150: OpKind = MCK_VReg_64; break;
   12462             :     case AMDGPU::VGPR150_VGPR151: OpKind = MCK_VReg_64; break;
   12463             :     case AMDGPU::VGPR151_VGPR152: OpKind = MCK_VReg_64; break;
   12464             :     case AMDGPU::VGPR152_VGPR153: OpKind = MCK_VReg_64; break;
   12465             :     case AMDGPU::VGPR153_VGPR154: OpKind = MCK_VReg_64; break;
   12466             :     case AMDGPU::VGPR154_VGPR155: OpKind = MCK_VReg_64; break;
   12467             :     case AMDGPU::VGPR155_VGPR156: OpKind = MCK_VReg_64; break;
   12468             :     case AMDGPU::VGPR156_VGPR157: OpKind = MCK_VReg_64; break;
   12469             :     case AMDGPU::VGPR157_VGPR158: OpKind = MCK_VReg_64; break;
   12470             :     case AMDGPU::VGPR158_VGPR159: OpKind = MCK_VReg_64; break;
   12471             :     case AMDGPU::VGPR159_VGPR160: OpKind = MCK_VReg_64; break;
   12472             :     case AMDGPU::VGPR160_VGPR161: OpKind = MCK_VReg_64; break;
   12473             :     case AMDGPU::VGPR161_VGPR162: OpKind = MCK_VReg_64; break;
   12474             :     case AMDGPU::VGPR162_VGPR163: OpKind = MCK_VReg_64; break;
   12475             :     case AMDGPU::VGPR163_VGPR164: OpKind = MCK_VReg_64; break;
   12476             :     case AMDGPU::VGPR164_VGPR165: OpKind = MCK_VReg_64; break;
   12477             :     case AMDGPU::VGPR165_VGPR166: OpKind = MCK_VReg_64; break;
   12478             :     case AMDGPU::VGPR166_VGPR167: OpKind = MCK_VReg_64; break;
   12479             :     case AMDGPU::VGPR167_VGPR168: OpKind = MCK_VReg_64; break;
   12480             :     case AMDGPU::VGPR168_VGPR169: OpKind = MCK_VReg_64; break;
   12481             :     case AMDGPU::VGPR169_VGPR170: OpKind = MCK_VReg_64; break;
   12482             :     case AMDGPU::VGPR170_VGPR171: OpKind = MCK_VReg_64; break;
   12483             :     case AMDGPU::VGPR171_VGPR172: OpKind = MCK_VReg_64; break;
   12484             :     case AMDGPU::VGPR172_VGPR173: OpKind = MCK_VReg_64; break;
   12485             :     case AMDGPU::VGPR173_VGPR174: OpKind = MCK_VReg_64; break;
   12486             :     case AMDGPU::VGPR174_VGPR175: OpKind = MCK_VReg_64; break;
   12487             :     case AMDGPU::VGPR175_VGPR176: OpKind = MCK_VReg_64; break;
   12488             :     case AMDGPU::VGPR176_VGPR177: OpKind = MCK_VReg_64; break;
   12489             :     case AMDGPU::VGPR177_VGPR178: OpKind = MCK_VReg_64; break;
   12490             :     case AMDGPU::VGPR178_VGPR179: OpKind = MCK_VReg_64; break;
   12491             :     case AMDGPU::VGPR179_VGPR180: OpKind = MCK_VReg_64; break;
   12492             :     case AMDGPU::VGPR180_VGPR181: OpKind = MCK_VReg_64; break;
   12493             :     case AMDGPU::VGPR181_VGPR182: OpKind = MCK_VReg_64; break;
   12494             :     case AMDGPU::VGPR182_VGPR183: OpKind = MCK_VReg_64; break;
   12495             :     case AMDGPU::VGPR183_VGPR184: OpKind = MCK_VReg_64; break;
   12496             :     case AMDGPU::VGPR184_VGPR185: OpKind = MCK_VReg_64; break;
   12497             :     case AMDGPU::VGPR185_VGPR186: OpKind = MCK_VReg_64; break;
   12498             :     case AMDGPU::VGPR186_VGPR187: OpKind = MCK_VReg_64; break;
   12499             :     case AMDGPU::VGPR187_VGPR188: OpKind = MCK_VReg_64; break;
   12500             :     case AMDGPU::VGPR188_VGPR189: OpKind = MCK_VReg_64; break;
   12501             :     case AMDGPU::VGPR189_VGPR190: OpKind = MCK_VReg_64; break;
   12502             :     case AMDGPU::VGPR190_VGPR191: OpKind = MCK_VReg_64; break;
   12503             :     case AMDGPU::VGPR191_VGPR192: OpKind = MCK_VReg_64; break;
   12504             :     case AMDGPU::VGPR192_VGPR193: OpKind = MCK_VReg_64; break;
   12505             :     case AMDGPU::VGPR193_VGPR194: OpKind = MCK_VReg_64; break;
   12506             :     case AMDGPU::VGPR194_VGPR195: OpKind = MCK_VReg_64; break;
   12507             :     case AMDGPU::VGPR195_VGPR196: OpKind = MCK_VReg_64; break;
   12508             :     case AMDGPU::VGPR196_VGPR197: OpKind = MCK_VReg_64; break;
   12509             :     case AMDGPU::VGPR197_VGPR198: OpKind = MCK_VReg_64; break;
   12510             :     case AMDGPU::VGPR198_VGPR199: OpKind = MCK_VReg_64; break;
   12511             :     case AMDGPU::VGPR199_VGPR200: OpKind = MCK_VReg_64; break;
   12512             :     case AMDGPU::VGPR200_VGPR201: OpKind = MCK_VReg_64; break;
   12513             :     case AMDGPU::VGPR201_VGPR202: OpKind = MCK_VReg_64; break;
   12514             :     case AMDGPU::VGPR202_VGPR203: OpKind = MCK_VReg_64; break;
   12515             :     case AMDGPU::VGPR203_VGPR204: OpKind = MCK_VReg_64; break;
   12516             :     case AMDGPU::VGPR204_VGPR205: OpKind = MCK_VReg_64; break;
   12517             :     case AMDGPU::VGPR205_VGPR206: OpKind = MCK_VReg_64; break;
   12518             :     case AMDGPU::VGPR206_VGPR207: OpKind = MCK_VReg_64; break;
   12519             :     case AMDGPU::VGPR207_VGPR208: OpKind = MCK_VReg_64; break;
   12520             :     case AMDGPU::VGPR208_VGPR209: OpKind = MCK_VReg_64; break;
   12521             :     case AMDGPU::VGPR209_VGPR210: OpKind = MCK_VReg_64; break;
   12522             :     case AMDGPU::VGPR210_VGPR211: OpKind = MCK_VReg_64; break;
   12523             :     case AMDGPU::VGPR211_VGPR212: OpKind = MCK_VReg_64; break;
   12524             :     case AMDGPU::VGPR212_VGPR213: OpKind = MCK_VReg_64; break;
   12525             :     case AMDGPU::VGPR213_VGPR214: OpKind = MCK_VReg_64; break;
   12526             :     case AMDGPU::VGPR214_VGPR215: OpKind = MCK_VReg_64; break;
   12527             :     case AMDGPU::VGPR215_VGPR216: OpKind = MCK_VReg_64; break;
   12528             :     case AMDGPU::VGPR216_VGPR217: OpKind = MCK_VReg_64; break;
   12529             :     case AMDGPU::VGPR217_VGPR218: OpKind = MCK_VReg_64; break;
   12530             :     case AMDGPU::VGPR218_VGPR219: OpKind = MCK_VReg_64; break;
   12531             :     case AMDGPU::VGPR219_VGPR220: OpKind = MCK_VReg_64; break;
   12532             :     case AMDGPU::VGPR220_VGPR221: OpKind = MCK_VReg_64; break;
   12533             :     case AMDGPU::VGPR221_VGPR222: OpKind = MCK_VReg_64; break;
   12534             :     case AMDGPU::VGPR222_VGPR223: OpKind = MCK_VReg_64; break;
   12535             :     case AMDGPU::VGPR223_VGPR224: OpKind = MCK_VReg_64; break;
   12536             :     case AMDGPU::VGPR224_VGPR225: OpKind = MCK_VReg_64; break;
   12537             :     case AMDGPU::VGPR225_VGPR226: OpKind = MCK_VReg_64; break;
   12538             :     case AMDGPU::VGPR226_VGPR227: OpKind = MCK_VReg_64; break;
   12539             :     case AMDGPU::VGPR227_VGPR228: OpKind = MCK_VReg_64; break;
   12540             :     case AMDGPU::VGPR228_VGPR229: OpKind = MCK_VReg_64; break;
   12541             :     case AMDGPU::VGPR229_VGPR230: OpKind = MCK_VReg_64; break;
   12542             :     case AMDGPU::VGPR230_VGPR231: OpKind = MCK_VReg_64; break;
   12543             :     case AMDGPU::VGPR231_VGPR232: OpKind = MCK_VReg_64; break;
   12544             :     case AMDGPU::VGPR232_VGPR233: OpKind = MCK_VReg_64; break;
   12545             :     case AMDGPU::VGPR233_VGPR234: OpKind = MCK_VReg_64; break;
   12546             :     case AMDGPU::VGPR234_VGPR235: OpKind = MCK_VReg_64; break;
   12547             :     case AMDGPU::VGPR235_VGPR236: OpKind = MCK_VReg_64; break;
   12548             :     case AMDGPU::VGPR236_VGPR237: OpKind = MCK_VReg_64; break;
   12549             :     case AMDGPU::VGPR237_VGPR238: OpKind = MCK_VReg_64; break;
   12550             :     case AMDGPU::VGPR238_VGPR239: OpKind = MCK_VReg_64; break;
   12551             :     case AMDGPU::VGPR239_VGPR240: OpKind = MCK_VReg_64; break;
   12552             :     case AMDGPU::VGPR240_VGPR241: OpKind = MCK_VReg_64; break;
   12553             :     case AMDGPU::VGPR241_VGPR242: OpKind = MCK_VReg_64; break;
   12554             :     case AMDGPU::VGPR242_VGPR243: OpKind = MCK_VReg_64; break;
   12555             :     case AMDGPU::VGPR243_VGPR244: OpKind = MCK_VReg_64; break;
   12556             :     case AMDGPU::VGPR244_VGPR245: OpKind = MCK_VReg_64; break;
   12557             :     case AMDGPU::VGPR245_VGPR246: OpKind = MCK_VReg_64; break;
   12558             :     case AMDGPU::VGPR246_VGPR247: OpKind = MCK_VReg_64; break;
   12559             :     case AMDGPU::VGPR247_VGPR248: OpKind = MCK_VReg_64; break;
   12560             :     case AMDGPU::VGPR248_VGPR249: OpKind = MCK_VReg_64; break;
   12561             :     case AMDGPU::VGPR249_VGPR250: OpKind = MCK_VReg_64; break;
   12562             :     case AMDGPU::VGPR250_VGPR251: OpKind = MCK_VReg_64; break;
   12563             :     case AMDGPU::VGPR251_VGPR252: OpKind = MCK_VReg_64; break;
   12564             :     case AMDGPU::VGPR252_VGPR253: OpKind = MCK_VReg_64; break;
   12565             :     case AMDGPU::VGPR253_VGPR254: OpKind = MCK_VReg_64; break;
   12566             :     case AMDGPU::VGPR254_VGPR255: OpKind = MCK_VReg_64; break;
   12567             :     case AMDGPU::VGPR0_VGPR1_VGPR2: OpKind = MCK_VReg_96; break;
   12568             :     case AMDGPU::VGPR1_VGPR2_VGPR3: OpKind = MCK_VReg_96; break;
   12569             :     case AMDGPU::VGPR2_VGPR3_VGPR4: OpKind = MCK_VReg_96; break;
   12570             :     case AMDGPU::VGPR3_VGPR4_VGPR5: OpKind = MCK_VReg_96; break;
   12571             :     case AMDGPU::VGPR4_VGPR5_VGPR6: OpKind = MCK_VReg_96; break;
   12572             :     case AMDGPU::VGPR5_VGPR6_VGPR7: OpKind = MCK_VReg_96; break;
   12573             :     case AMDGPU::VGPR6_VGPR7_VGPR8: OpKind = MCK_VReg_96; break;
   12574             :     case AMDGPU::VGPR7_VGPR8_VGPR9: OpKind = MCK_VReg_96; break;
   12575             :     case AMDGPU::VGPR8_VGPR9_VGPR10: OpKind = MCK_VReg_96; break;
   12576             :     case AMDGPU::VGPR9_VGPR10_VGPR11: OpKind = MCK_VReg_96; break;
   12577             :     case AMDGPU::VGPR10_VGPR11_VGPR12: OpKind = MCK_VReg_96; break;
   12578             :     case AMDGPU::VGPR11_VGPR12_VGPR13: OpKind = MCK_VReg_96; break;
   12579             :     case AMDGPU::VGPR12_VGPR13_VGPR14: OpKind = MCK_VReg_96; break;
   12580             :     case AMDGPU::VGPR13_VGPR14_VGPR15: OpKind = MCK_VReg_96; break;
   12581             :     case AMDGPU::VGPR14_VGPR15_VGPR16: OpKind = MCK_VReg_96; break;
   12582             :     case AMDGPU::VGPR15_VGPR16_VGPR17: OpKind = MCK_VReg_96; break;
   12583             :     case AMDGPU::VGPR16_VGPR17_VGPR18: OpKind = MCK_VReg_96; break;
   12584             :     case AMDGPU::VGPR17_VGPR18_VGPR19: OpKind = MCK_VReg_96; break;
   12585             :     case AMDGPU::VGPR18_VGPR19_VGPR20: OpKind = MCK_VReg_96; break;
   12586             :     case AMDGPU::VGPR19_VGPR20_VGPR21: OpKind = MCK_VReg_96; break;
   12587             :     case AMDGPU::VGPR20_VGPR21_VGPR22: OpKind = MCK_VReg_96; break;
   12588             :     case AMDGPU::VGPR21_VGPR22_VGPR23: OpKind = MCK_VReg_96; break;
   12589             :     case AMDGPU::VGPR22_VGPR23_VGPR24: OpKind = MCK_VReg_96; break;
   12590             :     case AMDGPU::VGPR23_VGPR24_VGPR25: OpKind = MCK_VReg_96; break;
   12591             :     case AMDGPU::VGPR24_VGPR25_VGPR26: OpKind = MCK_VReg_96; break;
   12592             :     case AMDGPU::VGPR25_VGPR26_VGPR27: OpKind = MCK_VReg_96; break;
   12593             :     case AMDGPU::VGPR26_VGPR27_VGPR28: OpKind = MCK_VReg_96; break;
   12594             :     case AMDGPU::VGPR27_VGPR28_VGPR29: OpKind = MCK_VReg_96; break;
   12595             :     case AMDGPU::VGPR28_VGPR29_VGPR30: OpKind = MCK_VReg_96; break;
   12596             :     case AMDGPU::VGPR29_VGPR30_VGPR31: OpKind = MCK_VReg_96; break;
   12597             :     case AMDGPU::VGPR30_VGPR31_VGPR32: OpKind = MCK_VReg_96; break;
   12598             :     case AMDGPU::VGPR31_VGPR32_VGPR33: OpKind = MCK_VReg_96; break;
   12599             :     case AMDGPU::VGPR32_VGPR33_VGPR34: OpKind = MCK_VReg_96; break;
   12600             :     case AMDGPU::VGPR33_VGPR34_VGPR35: OpKind = MCK_VReg_96; break;
   12601             :     case AMDGPU::VGPR34_VGPR35_VGPR36: OpKind = MCK_VReg_96; break;
   12602             :     case AMDGPU::VGPR35_VGPR36_VGPR37: OpKind = MCK_VReg_96; break;
   12603             :     case AMDGPU::VGPR36_VGPR37_VGPR38: OpKind = MCK_VReg_96; break;
   12604             :     case AMDGPU::VGPR37_VGPR38_VGPR39: OpKind = MCK_VReg_96; break;
   12605             :     case AMDGPU::VGPR38_VGPR39_VGPR40: OpKind = MCK_VReg_96; break;
   12606             :     case AMDGPU::VGPR39_VGPR40_VGPR41: OpKind = MCK_VReg_96; break;
   12607             :     case AMDGPU::VGPR40_VGPR41_VGPR42: OpKind = MCK_VReg_96; break;
   12608             :     case AMDGPU::VGPR41_VGPR42_VGPR43: OpKind = MCK_VReg_96; break;
   12609             :     case AMDGPU::VGPR42_VGPR43_VGPR44: OpKind = MCK_VReg_96; break;
   12610             :     case AMDGPU::VGPR43_VGPR44_VGPR45: OpKind = MCK_VReg_96; break;
   12611             :     case AMDGPU::VGPR44_VGPR45_VGPR46: OpKind = MCK_VReg_96; break;
   12612             :     case AMDGPU::VGPR45_VGPR46_VGPR47: OpKind = MCK_VReg_96; break;
   12613             :     case AMDGPU::VGPR46_VGPR47_VGPR48: OpKind = MCK_VReg_96; break;
   12614             :     case AMDGPU::VGPR47_VGPR48_VGPR49: OpKind = MCK_VReg_96; break;
   12615             :     case AMDGPU::VGPR48_VGPR49_VGPR50: OpKind = MCK_VReg_96; break;
   12616             :     case AMDGPU::VGPR49_VGPR50_VGPR51: OpKind = MCK_VReg_96; break;
   12617             :     case AMDGPU::VGPR50_VGPR51_VGPR52: OpKind = MCK_VReg_96; break;
   12618             :     case AMDGPU::VGPR51_VGPR52_VGPR53: OpKind = MCK_VReg_96; break;
   12619             :     case AMDGPU::VGPR52_VGPR53_VGPR54: OpKind = MCK_VReg_96; break;
   12620             :     case AMDGPU::VGPR53_VGPR54_VGPR55: OpKind = MCK_VReg_96; break;
   12621             :     case AMDGPU::VGPR54_VGPR55_VGPR56: OpKind = MCK_VReg_96; break;
   12622             :     case AMDGPU::VGPR55_VGPR56_VGPR57: OpKind = MCK_VReg_96; break;
   12623             :     case AMDGPU::VGPR56_VGPR57_VGPR58: OpKind = MCK_VReg_96; break;
   12624             :     case AMDGPU::VGPR57_VGPR58_VGPR59: OpKind = MCK_VReg_96; break;
   12625             :     case AMDGPU::VGPR58_VGPR59_VGPR60: OpKind = MCK_VReg_96; break;
   12626             :     case AMDGPU::VGPR59_VGPR60_VGPR61: OpKind = MCK_VReg_96; break;
   12627             :     case AMDGPU::VGPR60_VGPR61_VGPR62: OpKind = MCK_VReg_96; break;
   12628             :     case AMDGPU::VGPR61_VGPR62_VGPR63: OpKind = MCK_VReg_96; break;
   12629             :     case AMDGPU::VGPR62_VGPR63_VGPR64: OpKind = MCK_VReg_96; break;
   12630             :     case AMDGPU::VGPR63_VGPR64_VGPR65: OpKind = MCK_VReg_96; break;
   12631             :     case AMDGPU::VGPR64_VGPR65_VGPR66: OpKind = MCK_VReg_96; break;
   12632             :     case AMDGPU::VGPR65_VGPR66_VGPR67: OpKind = MCK_VReg_96; break;
   12633             :     case AMDGPU::VGPR66_VGPR67_VGPR68: OpKind = MCK_VReg_96; break;
   12634             :     case AMDGPU::VGPR67_VGPR68_VGPR69: OpKind = MCK_VReg_96; break;
   12635             :     case AMDGPU::VGPR68_VGPR69_VGPR70: OpKind = MCK_VReg_96; break;
   12636             :     case AMDGPU::VGPR69_VGPR70_VGPR71: OpKind = MCK_VReg_96; break;
   12637             :     case AMDGPU::VGPR70_VGPR71_VGPR72: OpKind = MCK_VReg_96; break;
   12638             :     case AMDGPU::VGPR71_VGPR72_VGPR73: OpKind = MCK_VReg_96; break;
   12639             :     case AMDGPU::VGPR72_VGPR73_VGPR74: OpKind = MCK_VReg_96; break;
   12640             :     case AMDGPU::VGPR73_VGPR74_VGPR75: OpKind = MCK_VReg_96; break;
   12641             :     case AMDGPU::VGPR74_VGPR75_VGPR76: OpKind = MCK_VReg_96; break;
   12642             :     case AMDGPU::VGPR75_VGPR76_VGPR77: OpKind = MCK_VReg_96; break;
   12643             :     case AMDGPU::VGPR76_VGPR77_VGPR78: OpKind = MCK_VReg_96; break;
   12644             :     case AMDGPU::VGPR77_VGPR78_VGPR79: OpKind = MCK_VReg_96; break;
   12645             :     case AMDGPU::VGPR78_VGPR79_VGPR80: OpKind = MCK_VReg_96; break;
   12646             :     case AMDGPU::VGPR79_VGPR80_VGPR81: OpKind = MCK_VReg_96; break;
   12647             :     case AMDGPU::VGPR80_VGPR81_VGPR82: OpKind = MCK_VReg_96; break;
   12648             :     case AMDGPU::VGPR81_VGPR82_VGPR83: OpKind = MCK_VReg_96; break;
   12649             :     case AMDGPU::VGPR82_VGPR83_VGPR84: OpKind = MCK_VReg_96; break;
   12650             :     case AMDGPU::VGPR83_VGPR84_VGPR85: OpKind = MCK_VReg_96; break;
   12651             :     case AMDGPU::VGPR84_VGPR85_VGPR86: OpKind = MCK_VReg_96; break;
   12652             :     case AMDGPU::VGPR85_VGPR86_VGPR87: OpKind = MCK_VReg_96; break;
   12653             :     case AMDGPU::VGPR86_VGPR87_VGPR88: OpKind = MCK_VReg_96; break;
   12654             :     case AMDGPU::VGPR87_VGPR88_VGPR89: OpKind = MCK_VReg_96; break;
   12655             :     case AMDGPU::VGPR88_VGPR89_VGPR90: OpKind = MCK_VReg_96; break;
   12656             :     case AMDGPU::VGPR89_VGPR90_VGPR91: OpKind = MCK_VReg_96; break;
   12657             :     case AMDGPU::VGPR90_VGPR91_VGPR92: OpKind = MCK_VReg_96; break;
   12658             :     case AMDGPU::VGPR91_VGPR92_VGPR93: OpKind = MCK_VReg_96; break;
   12659             :     case AMDGPU::VGPR92_VGPR93_VGPR94: OpKind = MCK_VReg_96; break;
   12660             :     case AMDGPU::VGPR93_VGPR94_VGPR95: OpKind = MCK_VReg_96; break;
   12661             :     case AMDGPU::VGPR94_VGPR95_VGPR96: OpKind = MCK_VReg_96; break;
   12662             :     case AMDGPU::VGPR95_VGPR96_VGPR97: OpKind = MCK_VReg_96; break;
   12663             :     case AMDGPU::VGPR96_VGPR97_VGPR98: OpKind = MCK_VReg_96; break;
   12664             :     case AMDGPU::VGPR97_VGPR98_VGPR99: OpKind = MCK_VReg_96; break;
   12665             :     case AMDGPU::VGPR98_VGPR99_VGPR100: OpKind = MCK_VReg_96; break;
   12666             :     case AMDGPU::VGPR99_VGPR100_VGPR101: OpKind = MCK_VReg_96; break;
   12667             :     case AMDGPU::VGPR100_VGPR101_VGPR102: OpKind = MCK_VReg_96; break;
   12668             :     case AMDGPU::VGPR101_VGPR102_VGPR103: OpKind = MCK_VReg_96; break;
   12669             :     case AMDGPU::VGPR102_VGPR103_VGPR104: OpKind = MCK_VReg_96; break;
   12670             :     case AMDGPU::VGPR103_VGPR104_VGPR105: OpKind = MCK_VReg_96; break;
   12671             :     case AMDGPU::VGPR104_VGPR105_VGPR106: OpKind = MCK_VReg_96; break;
   12672             :     case AMDGPU::VGPR105_VGPR106_VGPR107: OpKind = MCK_VReg_96; break;
   12673             :     case AMDGPU::VGPR106_VGPR107_VGPR108: OpKind = MCK_VReg_96; break;
   12674             :     case AMDGPU::VGPR107_VGPR108_VGPR109: OpKind = MCK_VReg_96; break;
   12675             :     case AMDGPU::VGPR108_VGPR109_VGPR110: OpKind = MCK_VReg_96; break;
   12676             :     case AMDGPU::VGPR109_VGPR110_VGPR111: OpKind = MCK_VReg_96; break;
   12677             :     case AMDGPU::VGPR110_VGPR111_VGPR112: OpKind = MCK_VReg_96; break;
   12678             :     case AMDGPU::VGPR111_VGPR112_VGPR113: OpKind = MCK_VReg_96; break;
   12679             :     case AMDGPU::VGPR112_VGPR113_VGPR114: OpKind = MCK_VReg_96; break;
   12680             :     case AMDGPU::VGPR113_VGPR114_VGPR115: OpKind = MCK_VReg_96; break;
   12681             :     case AMDGPU::VGPR114_VGPR115_VGPR116: OpKind = MCK_VReg_96; break;
   12682             :     case AMDGPU::VGPR115_VGPR116_VGPR117: OpKind = MCK_VReg_96; break;
   12683             :     case AMDGPU::VGPR116_VGPR117_VGPR118: OpKind = MCK_VReg_96; break;
   12684             :     case AMDGPU::VGPR117_VGPR118_VGPR119: OpKind = MCK_VReg_96; break;
   12685             :     case AMDGPU::VGPR118_VGPR119_VGPR120: OpKind = MCK_VReg_96; break;
   12686             :     case AMDGPU::VGPR119_VGPR120_VGPR121: OpKind = MCK_VReg_96; break;
   12687             :     case AMDGPU::VGPR120_VGPR121_VGPR122: OpKind = MCK_VReg_96; break;
   12688             :     case AMDGPU::VGPR121_VGPR122_VGPR123: OpKind = MCK_VReg_96; break;
   12689             :     case AMDGPU::VGPR122_VGPR123_VGPR124: OpKind = MCK_VReg_96; break;
   12690             :     case AMDGPU::VGPR123_VGPR124_VGPR125: OpKind = MCK_VReg_96; break;
   12691             :     case AMDGPU::VGPR124_VGPR125_VGPR126: OpKind = MCK_VReg_96; break;
   12692             :     case AMDGPU::VGPR125_VGPR126_VGPR127: OpKind = MCK_VReg_96; break;
   12693             :     case AMDGPU::VGPR126_VGPR127_VGPR128: OpKind = MCK_VReg_96; break;
   12694             :     case AMDGPU::VGPR127_VGPR128_VGPR129: OpKind = MCK_VReg_96; break;
   12695             :     case AMDGPU::VGPR128_VGPR129_VGPR130: OpKind = MCK_VReg_96; break;
   12696             :     case AMDGPU::VGPR129_VGPR130_VGPR131: OpKind = MCK_VReg_96; break;
   12697             :     case AMDGPU::VGPR130_VGPR131_VGPR132: OpKind = MCK_VReg_96; break;
   12698             :     case AMDGPU::VGPR131_VGPR132_VGPR133: OpKind = MCK_VReg_96; break;
   12699             :     case AMDGPU::VGPR132_VGPR133_VGPR134: OpKind = MCK_VReg_96; break;
   12700             :     case AMDGPU::VGPR133_VGPR134_VGPR135: OpKind = MCK_VReg_96; break;
   12701             :     case AMDGPU::VGPR134_VGPR135_VGPR136: OpKind = MCK_VReg_96; break;
   12702             :     case AMDGPU::VGPR135_VGPR136_VGPR137: OpKind = MCK_VReg_96; break;
   12703             :     case AMDGPU::VGPR136_VGPR137_VGPR138: OpKind = MCK_VReg_96; break;
   12704             :     case AMDGPU::VGPR137_VGPR138_VGPR139: OpKind = MCK_VReg_96; break;
   12705             :     case AMDGPU::VGPR138_VGPR139_VGPR140: OpKind = MCK_VReg_96; break;
   12706             :     case AMDGPU::VGPR139_VGPR140_VGPR141: OpKind = MCK_VReg_96; break;
   12707             :     case AMDGPU::VGPR140_VGPR141_VGPR142: OpKind = MCK_VReg_96; break;
   12708             :     case AMDGPU::VGPR141_VGPR142_VGPR143: OpKind = MCK_VReg_96; break;
   12709             :     case AMDGPU::VGPR142_VGPR143_VGPR144: OpKind = MCK_VReg_96; break;
   12710             :     case AMDGPU::VGPR143_VGPR144_VGPR145: OpKind = MCK_VReg_96; break;
   12711             :     case AMDGPU::VGPR144_VGPR145_VGPR146: OpKind = MCK_VReg_96; break;
   12712             :     case AMDGPU::VGPR145_VGPR146_VGPR147: OpKind = MCK_VReg_96; break;
   12713             :     case AMDGPU::VGPR146_VGPR147_VGPR148: OpKind = MCK_VReg_96; break;
   12714             :     case AMDGPU::VGPR147_VGPR148_VGPR149: OpKind = MCK_VReg_96; break;
   12715             :     case AMDGPU::VGPR148_VGPR149_VGPR150: OpKind = MCK_VReg_96; break;
   12716             :     case AMDGPU::VGPR149_VGPR150_VGPR151: OpKind = MCK_VReg_96; break;
   12717             :     case AMDGPU::VGPR150_VGPR151_VGPR152: OpKind = MCK_VReg_96; break;
   12718             :     case AMDGPU::VGPR151_VGPR152_VGPR153: OpKind = MCK_VReg_96; break;
   12719             :     case AMDGPU::VGPR152_VGPR153_VGPR154: OpKind = MCK_VReg_96; break;
   12720             :     case AMDGPU::VGPR153_VGPR154_VGPR155: OpKind = MCK_VReg_96; break;
   12721             :     case AMDGPU::VGPR154_VGPR155_VGPR156: OpKind = MCK_VReg_96; break;
   12722             :     case AMDGPU::VGPR155_VGPR156_VGPR157: OpKind = MCK_VReg_96; break;
   12723             :     case AMDGPU::VGPR156_VGPR157_VGPR158: OpKind = MCK_VReg_96; break;
   12724             :     case AMDGPU::VGPR157_VGPR158_VGPR159: OpKind = MCK_VReg_96; break;
   12725             :     case AMDGPU::VGPR158_VGPR159_VGPR160: OpKind = MCK_VReg_96; break;
   12726             :     case AMDGPU::VGPR159_VGPR160_VGPR161: OpKind = MCK_VReg_96; break;
   12727             :     case AMDGPU::VGPR160_VGPR161_VGPR162: OpKind = MCK_VReg_96; break;
   12728             :     case AMDGPU::VGPR161_VGPR162_VGPR163: OpKind = MCK_VReg_96; break;
   12729             :     case AMDGPU::VGPR162_VGPR163_VGPR164: OpKind = MCK_VReg_96; break;
   12730             :     case AMDGPU::VGPR163_VGPR164_VGPR165: OpKind = MCK_VReg_96; break;
   12731             :     case AMDGPU::VGPR164_VGPR165_VGPR166: OpKind = MCK_VReg_96; break;
   12732             :     case AMDGPU::VGPR165_VGPR166_VGPR167: OpKind = MCK_VReg_96; break;
   12733             :     case AMDGPU::VGPR166_VGPR167_VGPR168: OpKind = MCK_VReg_96; break;
   12734             :     case AMDGPU::VGPR167_VGPR168_VGPR169: OpKind = MCK_VReg_96; break;
   12735             :     case AMDGPU::VGPR168_VGPR169_VGPR170: OpKind = MCK_VReg_96; break;
   12736             :     case AMDGPU::VGPR169_VGPR170_VGPR171: OpKind = MCK_VReg_96; break;
   12737             :     case AMDGPU::VGPR170_VGPR171_VGPR172: OpKind = MCK_VReg_96; break;
   12738             :     case AMDGPU::VGPR171_VGPR172_VGPR173: OpKind = MCK_VReg_96; break;
   12739             :     case AMDGPU::VGPR172_VGPR173_VGPR174: OpKind = MCK_VReg_96; break;
   12740             :     case AMDGPU::VGPR173_VGPR174_VGPR175: OpKind = MCK_VReg_96; break;
   12741             :     case AMDGPU::VGPR174_VGPR175_VGPR176: OpKind = MCK_VReg_96; break;
   12742             :     case AMDGPU::VGPR175_VGPR176_VGPR177: OpKind = MCK_VReg_96; break;
   12743             :     case AMDGPU::VGPR176_VGPR177_VGPR178: OpKind = MCK_VReg_96; break;
   12744             :     case AMDGPU::VGPR177_VGPR178_VGPR179: OpKind = MCK_VReg_96; break;
   12745             :     case AMDGPU::VGPR178_VGPR179_VGPR180: OpKind = MCK_VReg_96; break;
   12746             :     case AMDGPU::VGPR179_VGPR180_VGPR181: OpKind = MCK_VReg_96; break;
   12747             :     case AMDGPU::VGPR180_VGPR181_VGPR182: OpKind = MCK_VReg_96; break;
   12748             :     case AMDGPU::VGPR181_VGPR182_VGPR183: OpKind = MCK_VReg_96; break;
   12749             :     case AMDGPU::VGPR182_VGPR183_VGPR184: OpKind = MCK_VReg_96; break;
   12750             :     case AMDGPU::VGPR183_VGPR184_VGPR185: OpKind = MCK_VReg_96; break;
   12751             :     case AMDGPU::VGPR184_VGPR185_VGPR186: OpKind = MCK_VReg_96; break;
   12752             :     case AMDGPU::VGPR185_VGPR186_VGPR187: OpKind = MCK_VReg_96; break;
   12753             :     case AMDGPU::VGPR186_VGPR187_VGPR188: OpKind = MCK_VReg_96; break;
   12754             :     case AMDGPU::VGPR187_VGPR188_VGPR189: OpKind = MCK_VReg_96; break;
   12755             :     case AMDGPU::VGPR188_VGPR189_VGPR190: OpKind = MCK_VReg_96; break;
   12756             :     case AMDGPU::VGPR189_VGPR190_VGPR191: OpKind = MCK_VReg_96; break;
   12757             :     case AMDGPU::VGPR190_VGPR191_VGPR192: OpKind = MCK_VReg_96; break;
   12758             :     case AMDGPU::VGPR191_VGPR192_VGPR193: OpKind = MCK_VReg_96; break;
   12759             :     case AMDGPU::VGPR192_VGPR193_VGPR194: OpKind = MCK_VReg_96; break;
   12760             :     case AMDGPU::VGPR193_VGPR194_VGPR195: OpKind = MCK_VReg_96; break;
   12761             :     case AMDGPU::VGPR194_VGPR195_VGPR196: OpKind = MCK_VReg_96; break;
   12762             :     case AMDGPU::VGPR195_VGPR196_VGPR197: OpKind = MCK_VReg_96; break;
   12763             :     case AMDGPU::VGPR196_VGPR197_VGPR198: OpKind = MCK_VReg_96; break;
   12764             :     case AMDGPU::VGPR197_VGPR198_VGPR199: OpKind = MCK_VReg_96; break;
   12765             :     case AMDGPU::VGPR198_VGPR199_VGPR200: OpKind = MCK_VReg_96; break;
   12766             :     case AMDGPU::VGPR199_VGPR200_VGPR201: OpKind = MCK_VReg_96; break;
   12767             :     case AMDGPU::VGPR200_VGPR201_VGPR202: OpKind = MCK_VReg_96; break;
   12768             :     case AMDGPU::VGPR201_VGPR202_VGPR203: OpKind = MCK_VReg_96; break;
   12769             :     case AMDGPU::VGPR202_VGPR203_VGPR204: OpKind = MCK_VReg_96; break;
   12770             :     case AMDGPU::VGPR203_VGPR204_VGPR205: OpKind = MCK_VReg_96; break;
   12771             :     case AMDGPU::VGPR204_VGPR205_VGPR206: OpKind = MCK_VReg_96; break;
   12772             :     case AMDGPU::VGPR205_VGPR206_VGPR207: OpKind = MCK_VReg_96; break;
   12773             :     case AMDGPU::VGPR206_VGPR207_VGPR208: OpKind = MCK_VReg_96; break;
   12774             :     case AMDGPU::VGPR207_VGPR208_VGPR209: OpKind = MCK_VReg_96; break;
   12775             :     case AMDGPU::VGPR208_VGPR209_VGPR210: OpKind = MCK_VReg_96; break;
   12776             :     case AMDGPU::VGPR209_VGPR210_VGPR211: OpKind = MCK_VReg_96; break;
   12777             :     case AMDGPU::VGPR210_VGPR211_VGPR212: OpKind = MCK_VReg_96; break;
   12778             :     case AMDGPU::VGPR211_VGPR212_VGPR213: OpKind = MCK_VReg_96; break;
   12779             :     case AMDGPU::VGPR212_VGPR213_VGPR214: OpKind = MCK_VReg_96; break;
   12780             :     case AMDGPU::VGPR213_VGPR214_VGPR215: OpKind = MCK_VReg_96; break;
   12781             :     case AMDGPU::VGPR214_VGPR215_VGPR216: OpKind = MCK_VReg_96; break;
   12782             :     case AMDGPU::VGPR215_VGPR216_VGPR217: OpKind = MCK_VReg_96; break;
   12783             :     case AMDGPU::VGPR216_VGPR217_VGPR218: OpKind = MCK_VReg_96; break;
   12784             :     case AMDGPU::VGPR217_VGPR218_VGPR219: OpKind = MCK_VReg_96; break;
   12785             :     case AMDGPU::VGPR218_VGPR219_VGPR220: OpKind = MCK_VReg_96; break;
   12786             :     case AMDGPU::VGPR219_VGPR220_VGPR221: OpKind = MCK_VReg_96; break;
   12787             :     case AMDGPU::VGPR220_VGPR221_VGPR222: OpKind = MCK_VReg_96; break;
   12788             :     case AMDGPU::VGPR221_VGPR222_VGPR223: OpKind = MCK_VReg_96; break;
   12789             :     case AMDGPU::VGPR222_VGPR223_VGPR224: OpKind = MCK_VReg_96; break;
   12790             :     case AMDGPU::VGPR223_VGPR224_VGPR225: OpKind = MCK_VReg_96; break;
   12791             :     case AMDGPU::VGPR224_VGPR225_VGPR226: OpKind = MCK_VReg_96; break;
   12792             :     case AMDGPU::VGPR225_VGPR226_VGPR227: OpKind = MCK_VReg_96; break;
   12793             :     case AMDGPU::VGPR226_VGPR227_VGPR228: OpKind = MCK_VReg_96; break;
   12794             :     case AMDGPU::VGPR227_VGPR228_VGPR229: OpKind = MCK_VReg_96; break;
   12795             :     case AMDGPU::VGPR228_VGPR229_VGPR230: OpKind = MCK_VReg_96; break;
   12796             :     case AMDGPU::VGPR229_VGPR230_VGPR231: OpKind = MCK_VReg_96; break;
   12797             :     case AMDGPU::VGPR230_VGPR231_VGPR232: OpKind = MCK_VReg_96; break;
   12798             :     case AMDGPU::VGPR231_VGPR232_VGPR233: OpKind = MCK_VReg_96; break;
   12799             :     case AMDGPU::VGPR232_VGPR233_VGPR234: OpKind = MCK_VReg_96; break;
   12800             :     case AMDGPU::VGPR233_VGPR234_VGPR235: OpKind = MCK_VReg_96; break;
   12801             :     case AMDGPU::VGPR234_VGPR235_VGPR236: OpKind = MCK_VReg_96; break;
   12802             :     case AMDGPU::VGPR235_VGPR236_VGPR237: OpKind = MCK_VReg_96; break;
   12803             :     case AMDGPU::VGPR236_VGPR237_VGPR238: OpKind = MCK_VReg_96; break;
   12804             :     case AMDGPU::VGPR237_VGPR238_VGPR239: OpKind = MCK_VReg_96; break;
   12805             :     case AMDGPU::VGPR238_VGPR239_VGPR240: OpKind = MCK_VReg_96; break;
   12806             :     case AMDGPU::VGPR239_VGPR240_VGPR241: OpKind = MCK_VReg_96; break;
   12807             :     case AMDGPU::VGPR240_VGPR241_VGPR242: OpKind = MCK_VReg_96; break;
   12808             :     case AMDGPU::VGPR241_VGPR242_VGPR243: OpKind = MCK_VReg_96; break;
   12809             :     case AMDGPU::VGPR242_VGPR243_VGPR244: OpKind = MCK_VReg_96; break;
   12810             :     case AMDGPU::VGPR243_VGPR244_VGPR245: OpKind = MCK_VReg_96; break;
   12811             :     case AMDGPU::VGPR244_VGPR245_VGPR246: OpKind = MCK_VReg_96; break;
   12812             :     case AMDGPU::VGPR245_VGPR246_VGPR247: OpKind = MCK_VReg_96; break;
   12813             :     case AMDGPU::VGPR246_VGPR247_VGPR248: OpKind = MCK_VReg_96; break;
   12814             :     case AMDGPU::VGPR247_VGPR248_VGPR249: OpKind = MCK_VReg_96; break;
   12815             :     case AMDGPU::VGPR248_VGPR249_VGPR250: OpKind = MCK_VReg_96; break;
   12816             :     case AMDGPU::VGPR249_VGPR250_VGPR251: OpKind = MCK_VReg_96; break;
   12817             :     case AMDGPU::VGPR250_VGPR251_VGPR252: OpKind = MCK_VReg_96; break;
   12818             :     case AMDGPU::VGPR251_VGPR252_VGPR253: OpKind = MCK_VReg_96; break;
   12819             :     case AMDGPU::VGPR252_VGPR253_VGPR254: OpKind = MCK_VReg_96; break;
   12820             :     case AMDGPU::VGPR253_VGPR254_VGPR255: OpKind = MCK_VReg_96; break;
   12821             :     }
   12822      406219 :     return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
   12823             :                                       getDiagKindFromRegisterClass(Kind);
   12824             :   }
   12825             : 
   12826             :   if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
   12827             :     return getDiagKindFromRegisterClass(Kind);
   12828             : 
   12829             :   return MCTargetAsmParser::Match_InvalidOperand;
   12830             : }
   12831             : 
   12832             : #ifndef NDEBUG
   12833             : const char *getMatchClassName(MatchClassKind Kind) {
   12834             :   switch (Kind) {
   12835             :   case InvalidMatchClass: return "InvalidMatchClass";
   12836             :   case OptionalMatchClass: return "OptionalMatchClass";
   12837             :   case MCK_addr64: return "MCK_addr64";
   12838             :   case MCK_done: return "MCK_done";
   12839             :   case MCK_gds: return "MCK_gds";
   12840             :   case MCK_glc: return "MCK_glc";
   12841             :   case MCK_idxen: return "MCK_idxen";
   12842             :   case MCK_lds: return "MCK_lds";
   12843             :   case MCK_off: return "MCK_off";
   12844             :   case MCK_offen: return "MCK_offen";
   12845             :   case MCK_M0_CLASS: return "MCK_M0_CLASS";
   12846             :   case MCK_Pseudo_SReg_128: return "MCK_Pseudo_SReg_128";
   12847             :   case MCK_SCC_CLASS: return "MCK_SCC_CLASS";
   12848             :   case MCK_TTMP_512: return "MCK_TTMP_512";
   12849             :   case MCK_VCC: return "MCK_VCC";
   12850             :   case MCK_Pseudo_SReg_32: return "MCK_Pseudo_SReg_32";
   12851             :   case MCK_TTMP_256: return "MCK_TTMP_256";
   12852             :   case MCK_TTMP_128: return "MCK_TTMP_128";
   12853             :   case MCK_TTMP_64: return "MCK_TTMP_64";
   12854             :   case MCK_TTMP_32: return "MCK_TTMP_32";
   12855             :   case MCK_SGPR_512: return "MCK_SGPR_512";
   12856             :   case MCK_SReg_512: return "MCK_SReg_512";
   12857             :   case MCK_SGPR_256: return "MCK_SGPR_256";
   12858             :   case MCK_SGPR_128: return "MCK_SGPR_128";
   12859             :   case MCK_SReg_256: return "MCK_SReg_256";
   12860             :   case MCK_SReg_128: return "MCK_SReg_128";
   12861             :   case MCK_SGPR_64: return "MCK_SGPR_64";
   12862             :   case MCK_SReg_64_XEXEC: return "MCK_SReg_64_XEXEC";
   12863             :   case MCK_SReg_64: return "MCK_SReg_64";
   12864             :   case MCK_SGPR_32: return "MCK_SGPR_32";
   12865             :   case MCK_SReg_32_XM0_XEXEC: return "MCK_SReg_32_XM0_XEXEC";
   12866             :   case MCK_Reg4: return "MCK_Reg4";
   12867             :   case MCK_SReg_32_XEXEC_HI: return "MCK_SReg_32_XEXEC_HI";
   12868             :   case MCK_SReg_32_XM0: return "MCK_SReg_32_XM0";
   12869             :   case MCK_SReg_32: return "MCK_SReg_32";
   12870             :   case MCK_VReg_512: return "MCK_VReg_512";
   12871             :   case MCK_VReg_256: return "MCK_VReg_256";
   12872             :   case MCK_VReg_128: return "MCK_VReg_128";
   12873             :   case MCK_VReg_96: return "MCK_VReg_96";
   12874             :   case MCK_VReg_64: return "MCK_VReg_64";
   12875             :   case MCK_VGPR_32: return "MCK_VGPR_32";
   12876             :   case MCK_VS_64: return "MCK_VS_64";
   12877             :   case MCK_VS_32: return "MCK_VS_32";
   12878             :   case MCK_AttrChan: return "MCK_AttrChan";
   12879             :   case MCK_Attr: return "MCK_Attr";
   12880             :   case MCK_ExpTgt: return "MCK_ExpTgt";
   12881             :   case MCK_RegOrImmWithFP16InputMods: return "MCK_RegOrImmWithFP16InputMods";
   12882             :   case MCK_SDWAWithFP16InputMods: return "MCK_SDWAWithFP16InputMods";
   12883             :   case MCK_RegOrImmWithFP32InputMods: return "MCK_RegOrImmWithFP32InputMods";
   12884             :   case MCK_SDWAWithFP32InputMods: return "MCK_SDWAWithFP32InputMods";
   12885             :   case MCK_RegOrImmWithFP64InputMods: return "MCK_RegOrImmWithFP64InputMods";
   12886             :   case MCK_VRegWithFPInputMods: return "MCK_VRegWithFPInputMods";
   12887             :   case MCK_GPRIdxMode: return "MCK_GPRIdxMode";
   12888             :   case MCK_Imm: return "MCK_Imm";
   12889             :   case MCK_SDWAWithInt16InputMods: return "MCK_SDWAWithInt16InputMods";
   12890             :   case MCK_RegOrImmWithInt32InputMods: return "MCK_RegOrImmWithInt32InputMods";
   12891             :   case MCK_SDWAWithInt32InputMods: return "MCK_SDWAWithInt32InputMods";
   12892             :   case MCK_RegOrImmWithInt64InputMods: return "MCK_RegOrImmWithInt64InputMods";
   12893             :   case MCK_OpSelMods: return "MCK_OpSelMods";
   12894             :   case MCK_VRegWithIntInputMods: return "MCK_VRegWithIntInputMods";
   12895             :   case MCK_InterpSlot: return "MCK_InterpSlot";
   12896             :   case MCK_KImmFP16: return "MCK_KImmFP16";
   12897             :   case MCK_KImmFP32: return "MCK_KImmFP32";
   12898             :   case MCK_PackedFP16InputMods: return "MCK_PackedFP16InputMods";
   12899             :   case MCK_PackedInt16InputMods: return "MCK_PackedInt16InputMods";
   12900             :   case MCK_SWaitCnt: return "MCK_SWaitCnt";
   12901             :   case MCK_SendMsg: return "MCK_SendMsg";
   12902             :   case MCK_SoppBrTarget: return "MCK_SoppBrTarget";
   12903             :   case MCK_Swizzle: return "MCK_Swizzle";
   12904             :   case MCK_VReg32OrOff: return "MCK_VReg32OrOff";
   12905             :   case MCK_SSrcB16: return "MCK_SSrcB16";
   12906             :   case MCK_SSrcF16: return "MCK_SSrcF16";
   12907             :   case MCK_SSrcB32: return "MCK_SSrcB32";
   12908             :   case MCK_SSrcF32: return "MCK_SSrcF32";
   12909             :   case MCK_SSrcB64: return "MCK_SSrcB64";
   12910             :   case MCK_SSrcF64: return "MCK_SSrcF64";
   12911             :   case MCK_SSrcV2B16: return "MCK_SSrcV2B16";
   12912             :   case MCK_SSrcV2F16: return "MCK_SSrcV2F16";
   12913             :   case MCK_SCSrcB16: return "MCK_SCSrcB16";
   12914             :   case MCK_SCSrcF16: return "MCK_SCSrcF16";
   12915             :   case MCK_SCSrcB32: return "MCK_SCSrcB32";
   12916             :   case MCK_SCSrcF32: return "MCK_SCSrcF32";
   12917             :   case MCK_SCSrcB64: return "MCK_SCSrcB64";
   12918             :   case MCK_SCSrcF64: return "MCK_SCSrcF64";
   12919             :   case MCK_SCSrcV2B16: return "MCK_SCSrcV2B16";
   12920             :   case MCK_SCSrcV2F16: return "MCK_SCSrcV2F16";
   12921             :   case MCK_VSrcB16: return "MCK_VSrcB16";
   12922             :   case MCK_VSrcF16: return "MCK_VSrcF16";
   12923             :   case MCK_VSrcB32: return "MCK_VSrcB32";
   12924             :   case MCK_VSrcF32: return "MCK_VSrcF32";
   12925             :   case MCK_VSrcB64: return "MCK_VSrcB64";
   12926             :   case MCK_VSrcF64: return "MCK_VSrcF64";
   12927             :   case MCK_VSrcV2B16: return "MCK_VSrcV2B16";
   12928             :   case MCK_VSrcV2F16: return "MCK_VSrcV2F16";
   12929             :   case MCK_VCSrcB16: return "MCK_VCSrcB16";
   12930             :   case MCK_VCSrcF16: return "MCK_VCSrcF16";
   12931             :   case MCK_VCSrcB32: return "MCK_VCSrcB32";
   12932             :   case MCK_VCSrcF32: return "MCK_VCSrcF32";
   12933             :   case MCK_VCSrcB64: return "MCK_VCSrcB64";
   12934             :   case MCK_VCSrcF64: return "MCK_VCSrcF64";
   12935             :   case MCK_VCSrcV2B16: return "MCK_VCSrcV2B16";
   12936             :   case MCK_VCSrcV2F16: return "MCK_VCSrcV2F16";
   12937             :   case MCK_ImmOffen: return "MCK_ImmOffen";
   12938             :   case MCK_ImmIdxen: return "MCK_ImmIdxen";
   12939             :   case MCK_ImmAddr64: return "MCK_ImmAddr64";
   12940             :   case MCK_ImmOffsetU12: return "MCK_ImmOffsetU12";
   12941             :   case MCK_ImmOffsetS13: return "MCK_ImmOffsetS13";
   12942             :   case MCK_ImmOffset: return "MCK_ImmOffset";
   12943             :   case MCK_ImmOffset0: return "MCK_ImmOffset0";
   12944             :   case MCK_ImmOffset1: return "MCK_ImmOffset1";
   12945             :   case MCK_ImmGDS: return "MCK_ImmGDS";
   12946             :   case MCK_ImmOModSI: return "MCK_ImmOModSI";
   12947             :   case MCK_ImmClampSI: return "MCK_ImmClampSI";
   12948             :   case MCK_ImmHigh: return "MCK_ImmHigh";
   12949             :   case MCK_ImmGLC: return "MCK_ImmGLC";
   12950             :   case MCK_ImmSLC: return "MCK_ImmSLC";
   12951             :   case MCK_ImmTFE: return "MCK_ImmTFE";
   12952             :   case MCK_ImmUNorm: return "MCK_ImmUNorm";
   12953             :   case MCK_ImmDA: return "MCK_ImmDA";
   12954             :   case MCK_ImmR128A16: return "MCK_ImmR128A16";
   12955             :   case MCK_ImmD16: return "MCK_ImmD16";
   12956             :   case MCK_ImmLWE: return "MCK_ImmLWE";
   12957             :   case MCK_ImmExpCompr: return "MCK_ImmExpCompr";
   12958             :   case MCK_ImmExpVM: return "MCK_ImmExpVM";
   12959             :   case MCK_ImmFORMAT: return "MCK_ImmFORMAT";
   12960             :   case MCK_ImmDMask: return "MCK_ImmDMask";
   12961             :   case MCK_ImmDPPCtrl: return "MCK_ImmDPPCtrl";
   12962             :   case MCK_ImmRowMask: return "MCK_ImmRowMask";
   12963             :   case MCK_ImmBankMask: return "MCK_ImmBankMask";
   12964             :   case MCK_ImmBoundCtrl: return "MCK_ImmBoundCtrl";
   12965             :   case MCK_ImmSDWADstSel: return "MCK_ImmSDWADstSel";
   12966             :   case MCK_ImmSDWASrc0Sel: return "MCK_ImmSDWASrc0Sel";
   12967             :   case MCK_ImmSDWASrc1Sel: return "MCK_ImmSDWASrc1Sel";
   12968             :   case MCK_ImmSDWADstUnused: return "MCK_ImmSDWADstUnused";
   12969             :   case MCK_ImmOpSel: return "MCK_ImmOpSel";
   12970             :   case MCK_ImmOpSelHi: return "MCK_ImmOpSelHi";
   12971             :   case MCK_ImmNegLo: return "MCK_ImmNegLo";
   12972             :   case MCK_ImmNegHi: return "MCK_ImmNegHi";
   12973             :   case MCK_ImmHwreg: return "MCK_ImmHwreg";
   12974             :   case MCK_ImmExpTgt: return "MCK_ImmExpTgt";
   12975             :   case MCK_ImmSMRDOffset8: return "MCK_ImmSMRDOffset8";
   12976             :   case MCK_ImmSMRDOffset20: return "MCK_ImmSMRDOffset20";
   12977             :   case MCK_ImmSMRDLiteralOffset: return "MCK_ImmSMRDLiteralOffset";
   12978             :   case MCK_S16Imm: return "MCK_S16Imm";
   12979             :   case MCK_U16Imm: return "MCK_U16Imm";
   12980             :   case NumMatchClassKinds: return "NumMatchClassKinds";
   12981             :   }
   12982             :   llvm_unreachable("unhandled MatchClassKind!");
   12983             : }
   12984             : 
   12985             : #endif // NDEBUG
   12986           0 : uint64_t AMDGPUAsmParser::
   12987             : ComputeAvailableFeatures(const FeatureBitset& FB) const {
   12988             :   uint64_t Features = 0;
   12989           0 :   if ((!FB[AMDGPU::FeatureGCN3Encoding]))
   12990             :     Features |= Feature_isSICI;
   12991           0 :   if ((FB[AMDGPU::FeatureGCN3Encoding]))
   12992           0 :     Features |= Feature_isVI;
   12993           0 :   if ((FB[AMDGPU::FeatureGFX9Insts]))
   12994           0 :     Features |= Feature_isGFX9;
   12995           0 :   if ((FB[AMDGPU::FeatureCIInsts]))
   12996           0 :     Features |= Feature_isCIVI;
   12997           0 :   if ((FB[AMDGPU::FeatureFlatAddressSpace]))
   12998           0 :     Features |= Feature_HasFlatAddressSpace;
   12999           0 :   if ((FB[AMDGPU::FeatureFlatGlobalInsts]))
   13000           0 :     Features |= Feature_HasFlatGlobalInsts;
   13001           0 :   if ((FB[AMDGPU::FeatureFlatScratchInsts]))
   13002           0 :     Features |= Feature_HasFlatScratchInsts;
   13003           0 :   if ((FB[AMDGPU::FeatureGFX9Insts]))
   13004           0 :     Features |= Feature_HasD16LoadStore;
   13005           0 :   if ((FB[AMDGPU::FeatureUnpackedD16VMem]))
   13006           0 :     Features |= Feature_HasUnpackedD16VMem;
   13007           0 :   if ((!FB[AMDGPU::FeatureUnpackedD16VMem]))
   13008           0 :     Features |= Feature_HasPackedD16VMem;
   13009           0 :   if ((FB[AMDGPU::FeatureD16PreservesUnusedBits]))
   13010           0 :     Features |= Feature_D16PreservesUnusedBits;
   13011           0 :   if ((FB[AMDGPU::FeatureGFX9Insts]))
   13012           0 :     Features |= Feature_HasDSAddTid;
   13013           0 :   if ((FB[AMDGPU::FeatureAddNoCarryInsts]))
   13014           0 :     Features |= Feature_HasAddNoCarryInsts;
   13015           0 :   if ((!FB[AMDGPU::FeatureAddNoCarryInsts]))
   13016           0 :     Features |= Feature_NotHasAddNoCarryInsts;
   13017           0 :   if ((FB[AMDGPU::Feature16BitInsts]))
   13018           0 :     Features |= Feature_Has16BitInsts;
   13019           0 :   if ((FB[AMDGPU::FeatureVOP3P]))
   13020           0 :     Features |= Feature_HasVOP3PInsts;
   13021           0 :   if ((!FB[AMDGPU::FeatureVOP3P]))
   13022           0 :     Features |= Feature_NotHasVOP3PInsts;
   13023           0 :   if ((FB[AMDGPU::FeatureSDWA]) && (FB[AMDGPU::FeatureVolcanicIslands]))
   13024           0 :     Features |= Feature_HasSDWA;
   13025           0 :   if ((FB[AMDGPU::FeatureSDWA]) && (FB[AMDGPU::FeatureGFX9]))
   13026           0 :     Features |= Feature_HasSDWA9;
   13027           0 :   if ((FB[AMDGPU::FeatureDPP]))
   13028           0 :     Features |= Feature_HasDPP;
   13029           0 :   if ((FB[AMDGPU::FeatureR128A16]))
   13030           0 :     Features |= Feature_HasR128A16;
   13031           0 :   if ((FB[AMDGPU::FeatureIntClamp]))
   13032           0 :     Features |= Feature_HasIntClamp;
   13033           0 :   if ((FB[AMDGPU::FeatureMadMixInsts]))
   13034           0 :     Features |= Feature_HasMadMixInsts;
   13035           0 :   if ((FB[AMDGPU::FeatureScalarAtomics]))
   13036           0 :     Features |= Feature_HasScalarAtomics;
   13037           0 :   if ((FB[AMDGPU::FeatureVGPRIndexMode]))
   13038           0 :     Features |= Feature_HasVGPRIndexMode;
   13039           0 :   if ((FB[AMDGPU::FeatureMovrel]))
   13040           0 :     Features |= Feature_HasMovrel;
   13041           0 :   if ((FB[AMDGPU::FeatureFmaMixInsts]))
   13042           0 :     Features |= Feature_HasFmaMixInsts;
   13043           0 :   if ((FB[AMDGPU::FeatureDLInsts]))
   13044           0 :     Features |= Feature_HasDLInsts;
   13045           0 :   if ((FB[AMDGPU::FeatureSeaIslands]))
   13046           0 :     Features |= Feature_isCIOnly;
   13047           0 :   if ((FB[AMDGPU::FeatureVolcanicIslands]))
   13048           0 :     Features |= Feature_isVIOnly;
   13049           0 :   if ((FB[AMDGPU::FeatureDisable]))
   13050           0 :     Features |= Feature_DisableInst;
   13051           0 :   if ((FB[AMDGPU::FeatureGCN]))
   13052           0 :     Features |= Feature_isGCN;
   13053           0 :   if ((FB[AMDGPU::FeatureSouthernIslands]))
   13054           0 :     Features |= Feature_isSI;
   13055           0 :   return Features;
   13056             : }
   13057             : 
   13058      160368 : static bool checkAsmTiedOperandConstraints(const AMDGPUAsmParser&AsmParser,
   13059             :                                unsigned Kind,
   13060             :                                const OperandVector &Operands,
   13061             :                                uint64_t &ErrorInfo) {
   13062             :   assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
   13063      160368 :   const uint8_t *Converter = ConversionTable[Kind];
   13064      476197 :   for (const uint8_t *p = Converter; *p; p+= 2) {
   13065      315829 :     switch (*p) {
   13066        4862 :     case CVT_Tied: {
   13067        4862 :       unsigned OpIdx = *(p+1);
   13068             :       assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
   13069             :                               std::begin(TiedAsmOperandTable)) &&
   13070             :              "Tied operand not found");
   13071        4862 :       unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
   13072        4862 :       unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
   13073        4862 :       if (OpndNum1 != OpndNum2) {
   13074           0 :         auto &SrcOp1 = Operands[OpndNum1];
   13075           0 :         auto &SrcOp2 = Operands[OpndNum2];
   13076           0 :         if (SrcOp1->isReg() && SrcOp2->isReg()) {
   13077           0 :           if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
   13078           0 :             ErrorInfo = OpndNum2;
   13079           0 :             return false;
   13080             :           }
   13081             :         }
   13082             :       }
   13083             :       break;
   13084             :     }
   13085             :     default:
   13086             :       break;
   13087             :     }
   13088             :   }
   13089             :   return true;
   13090             : }
   13091             : 
   13092             : static const char *const MnemonicTable =
   13093             :     "\021buffer_atomic_add\024buffer_atomic_add_x2\021buffer_atomic_and\024b"
   13094             :     "uffer_atomic_and_x2\025buffer_atomic_cmpswap\030buffer_atomic_cmpswap_x"
   13095             :     "2\021buffer_atomic_dec\024buffer_atomic_dec_x2\021buffer_atomic_inc\024"
   13096             :     "buffer_atomic_inc_x2\020buffer_atomic_or\023buffer_atomic_or_x2\022buff"
   13097             :     "er_atomic_smax\025buffer_atomic_smax_x2\022buffer_atomic_smin\025buffer"
   13098             :     "_atomic_smin_x2\021buffer_atomic_sub\024buffer_atomic_sub_x2\022buffer_"
   13099             :     "atomic_swap\025buffer_atomic_swap_x2\022buffer_atomic_umax\025buffer_at"
   13100             :     "omic_umax_x2\022buffer_atomic_umin\025buffer_atomic_umin_x2\021buffer_a"
   13101             :     "tomic_xor\024buffer_atomic_xor_x2\021buffer_load_dword\023buffer_load_d"
   13102             :     "wordx2\023buffer_load_dwordx3\023buffer_load_dwordx4\033buffer_load_for"
   13103             :     "mat_d16_hi_x\030buffer_load_format_d16_x\031buffer_load_format_d16_xy\032"
   13104             :     "buffer_load_format_d16_xyz\033buffer_load_format_d16_xyzw\024buffer_loa"
   13105             :     "d_format_x\025buffer_load_format_xy\026buffer_load_format_xyz\027buffer"
   13106             :     "_load_format_xyzw\021buffer_load_sbyte\025buffer_load_sbyte_d16\030buff"
   13107             :     "er_load_sbyte_d16_hi\025buffer_load_short_d16\030buffer_load_short_d16_"
   13108             :     "hi\022buffer_load_sshort\021buffer_load_ubyte\025buffer_load_ubyte_d16\030"
   13109             :     "buffer_load_ubyte_d16_hi\022buffer_load_ushort\021buffer_store_byte\030"
   13110             :     "buffer_store_byte_d16_hi\022buffer_store_dword\024buffer_store_dwordx2\024"
   13111             :     "buffer_store_dwordx3\024buffer_store_dwordx4\034buffer_store_format_d16"
   13112             :     "_hi_x\031buffer_store_format_d16_x\032buffer_store_format_d16_xy\033buf"
   13113             :     "fer_store_format_d16_xyz\034buffer_store_format_d16_xyzw\025buffer_stor"
   13114             :     "e_format_x\026buffer_store_format_xy\027buffer_store_format_xyz\030buff"
   13115             :     "er_store_format_xyzw\026buffer_store_lds_dword\022buffer_store_short\031"
   13116             :     "buffer_store_short_d16_hi\016buffer_wbinvl1\021buffer_wbinvl1_sc\022buf"
   13117             :     "fer_wbinvl1_vol\nds_add_f32\016ds_add_rtn_f32\016ds_add_rtn_u32\016ds_a"
   13118             :     "dd_rtn_u64\017ds_add_src2_f32\017ds_add_src2_u32\017ds_add_src2_u64\nds"
   13119             :     "_add_u32\nds_add_u64\nds_and_b32\nds_and_b64\016ds_and_rtn_b32\016ds_an"
   13120             :     "d_rtn_b64\017ds_and_src2_b32\017ds_and_src2_b64\tds_append\017ds_bpermu"
   13121             :     "te_b32\014ds_cmpst_b32\014ds_cmpst_b64\014ds_cmpst_f32\014ds_cmpst_f64\020"
   13122             :     "ds_cmpst_rtn_b32\020ds_cmpst_rtn_b64\020ds_cmpst_rtn_f32\020ds_cmpst_rt"
   13123             :     "n_f64\025ds_condxchg32_rtn_b64\nds_consume\016ds_dec_rtn_u32\016ds_dec_"
   13124             :     "rtn_u64\017ds_dec_src2_u32\017ds_dec_src2_u64\nds_dec_u32\nds_dec_u64\016"
   13125             :     "ds_gws_barrier\013ds_gws_init\016ds_gws_sema_br\015ds_gws_sema_p\027ds_"
   13126             :     "gws_sema_release_all\015ds_gws_sema_v\016ds_inc_rtn_u32\016ds_inc_rtn_u"
   13127             :     "64\017ds_inc_src2_u32\017ds_inc_src2_u64\nds_inc_u32\nds_inc_u64\nds_ma"
   13128             :     "x_f32\nds_max_f64\nds_max_i32\nds_max_i64\016ds_max_rtn_f32\016ds_max_r"
   13129             :     "tn_f64\016ds_max_rtn_i32\016ds_max_rtn_i64\016ds_max_rtn_u32\016ds_max_"
   13130             :     "rtn_u64\017ds_max_src2_f32\017ds_max_src2_f64\017ds_max_src2_i32\017ds_"
   13131             :     "max_src2_i64\017ds_max_src2_u32\017ds_max_src2_u64\nds_max_u32\nds_max_"
   13132             :     "u64\nds_min_f32\nds_min_f64\nds_min_i32\nds_min_i64\016ds_min_rtn_f32\016"
   13133             :     "ds_min_rtn_f64\016ds_min_rtn_i32\016ds_min_rtn_i64\016ds_min_rtn_u32\016"
   13134             :     "ds_min_rtn_u64\017ds_min_src2_f32\017ds_min_src2_f64\017ds_min_src2_i32"
   13135             :     "\017ds_min_src2_i64\017ds_min_src2_u32\017ds_min_src2_u64\nds_min_u32\n"
   13136             :     "ds_min_u64\014ds_mskor_b32\014ds_mskor_b64\020ds_mskor_rtn_b32\020ds_ms"
   13137             :     "kor_rtn_b64\006ds_nop\tds_or_b32\tds_or_b64\015ds_or_rtn_b32\015ds_or_r"
   13138             :     "tn_b64\016ds_or_src2_b32\016ds_or_src2_b64\020ds_ordered_count\016ds_pe"
   13139             :     "rmute_b32\014ds_read2_b32\014ds_read2_b64\020ds_read2st64_b32\020ds_rea"
   13140             :     "d2st64_b64\022ds_read_addtid_b32\014ds_read_b128\013ds_read_b32\013ds_r"
   13141             :     "ead_b64\013ds_read_b96\013ds_read_i16\nds_read_i8\016ds_read_i8_d16\021"
   13142             :     "ds_read_i8_d16_hi\013ds_read_u16\017ds_read_u16_d16\022ds_read_u16_d16_"
   13143             :     "hi\nds_read_u8\016ds_read_u8_d16\021ds_read_u8_d16_hi\017ds_rsub_rtn_u3"
   13144             :     "2\017ds_rsub_rtn_u64\020ds_rsub_src2_u32\020ds_rsub_src2_u64\013ds_rsub"
   13145             :     "_u32\013ds_rsub_u64\016ds_sub_rtn_u32\016ds_sub_rtn_u64\017ds_sub_src2_"
   13146             :     "u32\017ds_sub_src2_u64\nds_sub_u32\nds_sub_u64\016ds_swizzle_b32\017ds_"
   13147             :     "wrap_rtn_b32\015ds_write2_b32\015ds_write2_b64\021ds_write2st64_b32\021"
   13148             :     "ds_write2st64_b64\023ds_write_addtid_b32\015ds_write_b128\014ds_write_b"
   13149             :     "16\023ds_write_b16_d16_hi\014ds_write_b32\014ds_write_b64\013ds_write_b"
   13150             :     "8\022ds_write_b8_d16_hi\014ds_write_b96\021ds_write_src2_b32\021ds_writ"
   13151             :     "e_src2_b64\022ds_wrxchg2_rtn_b32\022ds_wrxchg2_rtn_b64\026ds_wrxchg2st6"
   13152             :     "4_rtn_b32\026ds_wrxchg2st64_rtn_b64\021ds_wrxchg_rtn_b32\021ds_wrxchg_r"
   13153             :     "tn_b64\nds_xor_b32\nds_xor_b64\016ds_xor_rtn_b32\016ds_xor_rtn_b64\017d"
   13154             :     "s_xor_src2_b32\017ds_xor_src2_b64\003exp\017flat_atomic_add\022flat_ato"
   13155             :     "mic_add_x2\017flat_atomic_and\022flat_atomic_and_x2\023flat_atomic_cmps"
   13156             :     "wap\026flat_atomic_cmpswap_x2\017flat_atomic_dec\022flat_atomic_dec_x2\024"
   13157             :     "flat_atomic_fcmpswap\027flat_atomic_fcmpswap_x2\020flat_atomic_fmax\023"
   13158             :     "flat_atomic_fmax_x2\020flat_atomic_fmin\023flat_atomic_fmin_x2\017flat_"
   13159             :     "atomic_inc\022flat_atomic_inc_x2\016flat_atomic_or\021flat_atomic_or_x2"
   13160             :     "\020flat_atomic_smax\023flat_atomic_smax_x2\020flat_atomic_smin\023flat"
   13161             :     "_atomic_smin_x2\017flat_atomic_sub\022flat_atomic_sub_x2\020flat_atomic"
   13162             :     "_swap\023flat_atomic_swap_x2\020flat_atomic_umax\023flat_atomic_umax_x2"
   13163             :     "\020flat_atomic_umin\023flat_atomic_umin_x2\017flat_atomic_xor\022flat_"
   13164             :     "atomic_xor_x2\017flat_load_dword\021flat_load_dwordx2\021flat_load_dwor"
   13165             :     "dx3\021flat_load_dwordx4\017flat_load_sbyte\023flat_load_sbyte_d16\026f"
   13166             :     "lat_load_sbyte_d16_hi\023flat_load_short_d16\026flat_load_short_d16_hi\020"
   13167             :     "flat_load_sshort\017flat_load_ubyte\023flat_load_ubyte_d16\026flat_load"
   13168             :     "_ubyte_d16_hi\020flat_load_ushort\017flat_store_byte\026flat_store_byte"
   13169             :     "_d16_hi\020flat_store_dword\022flat_store_dwordx2\022flat_store_dwordx3"
   13170             :     "\022flat_store_dwordx4\020flat_store_short\027flat_store_short_d16_hi\021"
   13171             :     "global_atomic_add\024global_atomic_add_x2\021global_atomic_and\024globa"
   13172             :     "l_atomic_and_x2\025global_atomic_cmpswap\030global_atomic_cmpswap_x2\021"
   13173             :     "global_atomic_dec\024global_atomic_dec_x2\021global_atomic_inc\024globa"
   13174             :     "l_atomic_inc_x2\020global_atomic_or\023global_atomic_or_x2\022global_at"
   13175             :     "omic_smax\025global_atomic_smax_x2\022global_atomic_smin\025global_atom"
   13176             :     "ic_smin_x2\021global_atomic_sub\024global_atomic_sub_x2\022global_atomi"
   13177             :     "c_swap\025global_atomic_swap_x2\022global_atomic_umax\025global_atomic_"
   13178             :     "umax_x2\022global_atomic_umin\025global_atomic_umin_x2\021global_atomic"
   13179             :     "_xor\024global_atomic_xor_x2\021global_load_dword\023global_load_dwordx"
   13180             :     "2\023global_load_dwordx3\023global_load_dwordx4\021global_load_sbyte\025"
   13181             :     "global_load_sbyte_d16\030global_load_sbyte_d16_hi\025global_load_short_"
   13182             :     "d16\030global_load_short_d16_hi\022global_load_sshort\021global_load_ub"
   13183             :     "yte\025global_load_ubyte_d16\030global_load_ubyte_d16_hi\022global_load"
   13184             :     "_ushort\021global_store_byte\030global_store_byte_d16_hi\022global_stor"
   13185             :     "e_dword\024global_store_dwordx2\024global_store_dwordx3\024global_store"
   13186             :     "_dwordx4\022global_store_short\031global_store_short_d16_hi\020image_at"
   13187             :     "omic_add\020image_atomic_and\024image_atomic_cmpswap\020image_atomic_de"
   13188             :     "c\020image_atomic_inc\017image_atomic_or\021image_atomic_smax\021image_"
   13189             :     "atomic_smin\020image_atomic_sub\021image_atomic_swap\021image_atomic_um"
   13190             :     "ax\021image_atomic_umin\020image_atomic_xor\015image_gather4\017image_g"
   13191             :     "ather4_b\022image_gather4_b_cl\024image_gather4_b_cl_o\021image_gather4"
   13192             :     "_b_o\017image_gather4_c\021image_gather4_c_b\024image_gather4_c_b_cl\026"
   13193             :     "image_gather4_c_b_cl_o\023image_gather4_c_b_o\022image_gather4_c_cl\024"
   13194             :     "image_gather4_c_cl_o\021image_gather4_c_l\023image_gather4_c_l_o\022ima"
   13195             :     "ge_gather4_c_lz\024image_gather4_c_lz_o\021image_gather4_c_o\020image_g"
   13196             :     "ather4_cl\022image_gather4_cl_o\017image_gather4_l\021image_gather4_l_o"
   13197             :     "\020image_gather4_lz\022image_gather4_lz_o\017image_gather4_o\015image_"
   13198             :     "get_lod\021image_get_resinfo\nimage_load\016image_load_mip\022image_loa"
   13199             :     "d_mip_pck\026image_load_mip_pck_sgn\016image_load_pck\022image_load_pck"
   13200             :     "_sgn\014image_sample\016image_sample_b\021image_sample_b_cl\023image_sa"
   13201             :     "mple_b_cl_o\020image_sample_b_o\016image_sample_c\020image_sample_c_b\023"
   13202             :     "image_sample_c_b_cl\025image_sample_c_b_cl_o\022image_sample_c_b_o\021i"
   13203             :     "mage_sample_c_cd\024image_sample_c_cd_cl\026image_sample_c_cd_cl_o\023i"
   13204             :     "mage_sample_c_cd_o\021image_sample_c_cl\023image_sample_c_cl_o\020image"
   13205             :     "_sample_c_d\023image_sample_c_d_cl\025image_sample_c_d_cl_o\022image_sa"
   13206             :     "mple_c_d_o\020image_sample_c_l\022image_sample_c_l_o\021image_sample_c_"
   13207             :     "lz\023image_sample_c_lz_o\020image_sample_c_o\017image_sample_cd\022ima"
   13208             :     "ge_sample_cd_cl\024image_sample_cd_cl_o\021image_sample_cd_o\017image_s"
   13209             :     "ample_cl\021image_sample_cl_o\016image_sample_d\021image_sample_d_cl\023"
   13210             :     "image_sample_d_cl_o\020image_sample_d_o\016image_sample_l\020image_samp"
   13211             :     "le_l_o\017image_sample_lz\021image_sample_lz_o\016image_sample_o\013ima"
   13212             :     "ge_store\017image_store_mip\023image_store_mip_pck\017image_store_pck\t"
   13213             :     "s_abs_i32\015s_absdiff_i32\ts_add_i32\ts_add_u32\ns_addc_u32\ns_addk_i3"
   13214             :     "2\ts_and_b32\ts_and_b64\022s_and_saveexec_b64\024s_andn1_saveexec_b64\022"
   13215             :     "s_andn1_wrexec_b64\013s_andn2_b32\013s_andn2_b64\024s_andn2_saveexec_b6"
   13216             :     "4\022s_andn2_wrexec_b64\ns_ashr_i32\ns_ashr_i64\013s_atc_probe\022s_atc"
   13217             :     "_probe_buffer\014s_atomic_add\017s_atomic_add_x2\014s_atomic_and\017s_a"
   13218             :     "tomic_and_x2\020s_atomic_cmpswap\023s_atomic_cmpswap_x2\014s_atomic_dec"
   13219             :     "\017s_atomic_dec_x2\014s_atomic_inc\017s_atomic_inc_x2\013s_atomic_or\016"
   13220             :     "s_atomic_or_x2\015s_atomic_smax\020s_atomic_smax_x2\015s_atomic_smin\020"
   13221             :     "s_atomic_smin_x2\014s_atomic_sub\017s_atomic_sub_x2\015s_atomic_swap\020"
   13222             :     "s_atomic_swap_x2\015s_atomic_umax\020s_atomic_umax_x2\015s_atomic_umin\020"
   13223             :     "s_atomic_umin_x2\014s_atomic_xor\017s_atomic_xor_x2\ts_barrier\017s_bcn"
   13224             :     "t0_i32_b32\017s_bcnt0_i32_b64\017s_bcnt1_i32_b32\017s_bcnt1_i32_b64\ts_"
   13225             :     "bfe_i32\ts_bfe_i64\ts_bfe_u32\ts_bfe_u64\ts_bfm_b32\ts_bfm_b64\015s_bit"
   13226             :     "cmp0_b32\015s_bitcmp0_b64\015s_bitcmp1_b32\015s_bitcmp1_b64\026s_bitrep"
   13227             :     "licate_b64_b32\015s_bitset0_b32\015s_bitset0_b64\015s_bitset1_b32\015s_"
   13228             :     "bitset1_b64\010s_branch\ns_brev_b32\ns_brev_b64\023s_buffer_atomic_add\026"
   13229             :     "s_buffer_atomic_add_x2\023s_buffer_atomic_and\026s_buffer_atomic_and_x2"
   13230             :     "\027s_buffer_atomic_cmpswap\032s_buffer_atomic_cmpswap_x2\023s_buffer_a"
   13231             :     "tomic_dec\026s_buffer_atomic_dec_x2\023s_buffer_atomic_inc\026s_buffer_"
   13232             :     "atomic_inc_x2\022s_buffer_atomic_or\025s_buffer_atomic_or_x2\024s_buffe"
   13233             :     "r_atomic_smax\027s_buffer_atomic_smax_x2\024s_buffer_atomic_smin\027s_b"
   13234             :     "uffer_atomic_smin_x2\023s_buffer_atomic_sub\026s_buffer_atomic_sub_x2\024"
   13235             :     "s_buffer_atomic_swap\027s_buffer_atomic_swap_x2\024s_buffer_atomic_umax"
   13236             :     "\027s_buffer_atomic_umax_x2\024s_buffer_atomic_umin\027s_buffer_atomic_"
   13237             :     "umin_x2\023s_buffer_atomic_xor\026s_buffer_atomic_xor_x2\023s_buffer_lo"
   13238             :     "ad_dword\026s_buffer_load_dwordx16\025s_buffer_load_dwordx2\025s_buffer"
   13239             :     "_load_dwordx4\025s_buffer_load_dwordx8\024s_buffer_store_dword\026s_buf"
   13240             :     "fer_store_dwordx2\026s_buffer_store_dwordx4\ns_call_b64\021s_cbranch_cd"
   13241             :     "bgsys\032s_cbranch_cdbgsys_and_user\031s_cbranch_cdbgsys_or_user\022s_c"
   13242             :     "branch_cdbguser\020s_cbranch_execnz\017s_cbranch_execz\020s_cbranch_g_f"
   13243             :     "ork\020s_cbranch_i_fork\016s_cbranch_join\016s_cbranch_scc0\016s_cbranc"
   13244             :     "h_scc1\017s_cbranch_vccnz\016s_cbranch_vccz\ns_cmov_b32\ns_cmov_b64\013"
   13245             :     "s_cmovk_i32\014s_cmp_eq_i32\014s_cmp_eq_u32\014s_cmp_eq_u64\014s_cmp_ge"
   13246             :     "_i32\014s_cmp_ge_u32\014s_cmp_gt_i32\014s_cmp_gt_u32\014s_cmp_le_i32\014"
   13247             :     "s_cmp_le_u32\014s_cmp_lg_i32\014s_cmp_lg_u32\014s_cmp_lg_u64\014s_cmp_l"
   13248             :     "t_i32\014s_cmp_lt_u32\015s_cmpk_eq_i32\015s_cmpk_eq_u32\015s_cmpk_ge_i3"
   13249             :     "2\015s_cmpk_ge_u32\015s_cmpk_gt_i32\015s_cmpk_gt_u32\015s_cmpk_le_i32\015"
   13250             :     "s_cmpk_le_u32\015s_cmpk_lg_i32\015s_cmpk_lg_u32\015s_cmpk_lt_i32\015s_c"
   13251             :     "mpk_lt_u32\015s_cselect_b32\015s_cselect_b64\020s_dcache_discard\023s_d"
   13252             :     "cache_discard_x2\014s_dcache_inv\020s_dcache_inv_vol\013s_dcache_wb\017"
   13253             :     "s_dcache_wb_vol\016s_decperflevel\010s_endpgm\030s_endpgm_ordered_ps_do"
   13254             :     "ne\016s_endpgm_saved\015s_ff0_i32_b32\015s_ff0_i32_b64\015s_ff1_i32_b32"
   13255             :     "\015s_ff1_i32_b64\013s_flbit_i32\017s_flbit_i32_b32\017s_flbit_i32_b64\017"
   13256             :     "s_flbit_i32_i64\013s_getpc_b64\014s_getreg_b32\014s_icache_inv\016s_inc"
   13257             :     "perflevel\014s_load_dword\017s_load_dwordx16\016s_load_dwordx2\016s_loa"
   13258             :     "d_dwordx4\016s_load_dwordx8\017s_lshl1_add_u32\017s_lshl2_add_u32\017s_"
   13259             :     "lshl3_add_u32\017s_lshl4_add_u32\ns_lshl_b32\ns_lshl_b64\ns_lshr_b32\ns"
   13260             :     "_lshr_b64\ts_max_i32\ts_max_u32\015s_memrealtime\ts_memtime\ts_min_i32\t"
   13261             :     "s_min_u32\ts_mov_b32\ts_mov_b64\015s_mov_fed_b32\017s_mov_regrd_b32\ns_"
   13262             :     "movk_i32\015s_movreld_b32\015s_movreld_b64\015s_movrels_b32\015s_movrel"
   13263             :     "s_b64\014s_mul_hi_i32\014s_mul_hi_u32\ts_mul_i32\ns_mulk_i32\ns_nand_b3"
   13264             :     "2\ns_nand_b64\023s_nand_saveexec_b64\005s_nop\ts_nor_b32\ts_nor_b64\022"
   13265             :     "s_nor_saveexec_b64\ts_not_b32\ts_not_b64\010s_or_b32\010s_or_b64\021s_o"
   13266             :     "r_saveexec_b64\023s_orn1_saveexec_b64\ns_orn2_b32\ns_orn2_b64\023s_orn2"
   13267             :     "_saveexec_b64\021s_pack_hh_b32_b16\021s_pack_lh_b32_b16\021s_pack_ll_b3"
   13268             :     "2_b16\016s_quadmask_b32\016s_quadmask_b64\ts_rfe_b64\021s_rfe_restore_b"
   13269             :     "64\024s_scratch_load_dword\026s_scratch_load_dwordx2\026s_scratch_load_"
   13270             :     "dwordx4\025s_scratch_store_dword\027s_scratch_store_dwordx2\027s_scratc"
   13271             :     "h_store_dwordx4\ts_sendmsg\015s_sendmsghalt\021s_set_gpr_idx_idx\022s_s"
   13272             :     "et_gpr_idx_mode\021s_set_gpr_idx_off\020s_set_gpr_idx_on\ts_sethalt\ts_"
   13273             :     "setkill\013s_setpc_b64\ts_setprio\014s_setreg_b32\022s_setreg_imm32_b32"
   13274             :     "\ns_setvskip\016s_sext_i32_i16\015s_sext_i32_i8\007s_sleep\015s_store_d"
   13275             :     "word\017s_store_dwordx2\017s_store_dwordx4\ts_sub_i32\ts_sub_u32\ns_sub"
   13276             :     "b_u32\014s_swappc_b64\006s_trap\014s_ttracedata\ts_waitcnt\010s_wakeup\t"
   13277             :     "s_wqm_b32\ts_wqm_b64\ns_xnor_b32\ns_xnor_b64\023s_xnor_saveexec_b64\ts_"
   13278             :     "xor_b32\ts_xor_b64\022s_xor_saveexec_b64\022scratch_load_dword\024scrat"
   13279             :     "ch_load_dwordx2\024scratch_load_dwordx3\024scratch_load_dwordx4\022scra"
   13280             :     "tch_load_sbyte\026scratch_load_sbyte_d16\031scratch_load_sbyte_d16_hi\026"
   13281             :     "scratch_load_short_d16\031scratch_load_short_d16_hi\023scratch_load_ssh"
   13282             :     "ort\022scratch_load_ubyte\026scratch_load_ubyte_d16\031scratch_load_uby"
   13283             :     "te_d16_hi\023scratch_load_ushort\022scratch_store_byte\031scratch_store"
   13284             :     "_byte_d16_hi\023scratch_store_dword\025scratch_store_dwordx2\025scratch"
   13285             :     "_store_dwordx3\025scratch_store_dwordx4\023scratch_store_short\032scrat"
   13286             :     "ch_store_short_d16_hi\031tbuffer_load_format_d16_x\032tbuffer_load_form"
   13287             :     "at_d16_xy\033tbuffer_load_format_d16_xyz\034tbuffer_load_format_d16_xyz"
   13288             :     "w\025tbuffer_load_format_x\026tbuffer_load_format_xy\027tbuffer_load_fo"
   13289             :     "rmat_xyz\030tbuffer_load_format_xyzw\032tbuffer_store_format_d16_x\033t"
   13290             :     "buffer_store_format_d16_xy\034tbuffer_store_format_d16_xyz\035tbuffer_s"
   13291             :     "tore_format_d16_xyzw\026tbuffer_store_format_x\027tbuffer_store_format_"
   13292             :     "xy\030tbuffer_store_format_xyz\031tbuffer_store_format_xyzw\nv_add3_u32"
   13293             :     "\014v_add_co_u32\tv_add_f16\tv_add_f32\tv_add_f64\tv_add_i16\tv_add_i32"
   13294             :     "\016v_add_lshl_u32\tv_add_u16\tv_add_u32\015v_addc_co_u32\nv_addc_u32\016"
   13295             :     "v_alignbit_b32\017v_alignbyte_b32\tv_and_b32\014v_and_or_b32\nv_ashr_i3"
   13296             :     "2\nv_ashr_i64\015v_ashrrev_i16\015v_ashrrev_i32\015v_ashrrev_i64\016v_b"
   13297             :     "cnt_u32_b32\tv_bfe_i32\tv_bfe_u32\tv_bfi_b32\tv_bfm_b32\013v_bfrev_b32\n"
   13298             :     "v_ceil_f16\nv_ceil_f32\nv_ceil_f64\tv_clrexcp\017v_cmp_class_f16\023v_c"
   13299             :     "mp_class_f16_e32\017v_cmp_class_f32\023v_cmp_class_f32_e32\017v_cmp_cla"
   13300             :     "ss_f64\023v_cmp_class_f64_e32\014v_cmp_eq_f16\020v_cmp_eq_f16_e32\014v_"
   13301             :     "cmp_eq_f32\020v_cmp_eq_f32_e32\014v_cmp_eq_f64\020v_cmp_eq_f64_e32\014v"
   13302             :     "_cmp_eq_i16\020v_cmp_eq_i16_e32\014v_cmp_eq_i32\020v_cmp_eq_i32_e32\014"
   13303             :     "v_cmp_eq_i64\020v_cmp_eq_i64_e32\014v_cmp_eq_u16\020v_cmp_eq_u16_e32\014"
   13304             :     "v_cmp_eq_u32\020v_cmp_eq_u32_e32\014v_cmp_eq_u64\020v_cmp_eq_u64_e32\013"
   13305             :     "v_cmp_f_f16\017v_cmp_f_f16_e32\013v_cmp_f_f32\017v_cmp_f_f32_e32\013v_c"
   13306             :     "mp_f_f64\017v_cmp_f_f64_e32\013v_cmp_f_i16\017v_cmp_f_i16_e32\013v_cmp_"
   13307             :     "f_i32\017v_cmp_f_i32_e32\013v_cmp_f_i64\017v_cmp_f_i64_e32\013v_cmp_f_u"
   13308             :     "16\017v_cmp_f_u16_e32\013v_cmp_f_u32\017v_cmp_f_u32_e32\013v_cmp_f_u64\017"
   13309             :     "v_cmp_f_u64_e32\014v_cmp_ge_f16\020v_cmp_ge_f16_e32\014v_cmp_ge_f32\020"
   13310             :     "v_cmp_ge_f32_e32\014v_cmp_ge_f64\020v_cmp_ge_f64_e32\014v_cmp_ge_i16\020"
   13311             :     "v_cmp_ge_i16_e32\014v_cmp_ge_i32\020v_cmp_ge_i32_e32\014v_cmp_ge_i64\020"
   13312             :     "v_cmp_ge_i64_e32\014v_cmp_ge_u16\020v_cmp_ge_u16_e32\014v_cmp_ge_u32\020"
   13313             :     "v_cmp_ge_u32_e32\014v_cmp_ge_u64\020v_cmp_ge_u64_e32\014v_cmp_gt_f16\020"
   13314             :     "v_cmp_gt_f16_e32\014v_cmp_gt_f32\020v_cmp_gt_f32_e32\014v_cmp_gt_f64\020"
   13315             :     "v_cmp_gt_f64_e32\014v_cmp_gt_i16\020v_cmp_gt_i16_e32\014v_cmp_gt_i32\020"
   13316             :     "v_cmp_gt_i32_e32\014v_cmp_gt_i64\020v_cmp_gt_i64_e32\014v_cmp_gt_u16\020"
   13317             :     "v_cmp_gt_u16_e32\014v_cmp_gt_u32\020v_cmp_gt_u32_e32\014v_cmp_gt_u64\020"
   13318             :     "v_cmp_gt_u64_e32\014v_cmp_le_f16\020v_cmp_le_f16_e32\014v_cmp_le_f32\020"
   13319             :     "v_cmp_le_f32_e32\014v_cmp_le_f64\020v_cmp_le_f64_e32\014v_cmp_le_i16\020"
   13320             :     "v_cmp_le_i16_e32\014v_cmp_le_i32\020v_cmp_le_i32_e32\014v_cmp_le_i64\020"
   13321             :     "v_cmp_le_i64_e32\014v_cmp_le_u16\020v_cmp_le_u16_e32\014v_cmp_le_u32\020"
   13322             :     "v_cmp_le_u32_e32\014v_cmp_le_u64\020v_cmp_le_u64_e32\014v_cmp_lg_f16\020"
   13323             :     "v_cmp_lg_f16_e32\014v_cmp_lg_f32\020v_cmp_lg_f32_e32\014v_cmp_lg_f64\020"
   13324             :     "v_cmp_lg_f64_e32\014v_cmp_lt_f16\020v_cmp_lt_f16_e32\014v_cmp_lt_f32\020"
   13325             :     "v_cmp_lt_f32_e32\014v_cmp_lt_f64\020v_cmp_lt_f64_e32\014v_cmp_lt_i16\020"
   13326             :     "v_cmp_lt_i16_e32\014v_cmp_lt_i32\020v_cmp_lt_i32_e32\014v_cmp_lt_i64\020"
   13327             :     "v_cmp_lt_i64_e32\014v_cmp_lt_u16\020v_cmp_lt_u16_e32\014v_cmp_lt_u32\020"
   13328             :     "v_cmp_lt_u32_e32\014v_cmp_lt_u64\020v_cmp_lt_u64_e32\014v_cmp_ne_i16\020"
   13329             :     "v_cmp_ne_i16_e32\014v_cmp_ne_i32\020v_cmp_ne_i32_e32\014v_cmp_ne_i64\020"
   13330             :     "v_cmp_ne_i64_e32\014v_cmp_ne_u16\020v_cmp_ne_u16_e32\014v_cmp_ne_u32\020"
   13331             :     "v_cmp_ne_u32_e32\014v_cmp_ne_u64\020v_cmp_ne_u64_e32\015v_cmp_neq_f16\021"
   13332             :     "v_cmp_neq_f16_e32\015v_cmp_neq_f32\021v_cmp_neq_f32_e32\015v_cmp_neq_f6"
   13333             :     "4\021v_cmp_neq_f64_e32\015v_cmp_nge_f16\021v_cmp_nge_f16_e32\015v_cmp_n"
   13334             :     "ge_f32\021v_cmp_nge_f32_e32\015v_cmp_nge_f64\021v_cmp_nge_f64_e32\015v_"
   13335             :     "cmp_ngt_f16\021v_cmp_ngt_f16_e32\015v_cmp_ngt_f32\021v_cmp_ngt_f32_e32\015"
   13336             :     "v_cmp_ngt_f64\021v_cmp_ngt_f64_e32\015v_cmp_nle_f16\021v_cmp_nle_f16_e3"
   13337             :     "2\015v_cmp_nle_f32\021v_cmp_nle_f32_e32\015v_cmp_nle_f64\021v_cmp_nle_f"
   13338             :     "64_e32\015v_cmp_nlg_f16\021v_cmp_nlg_f16_e32\015v_cmp_nlg_f32\021v_cmp_"
   13339             :     "nlg_f32_e32\015v_cmp_nlg_f64\021v_cmp_nlg_f64_e32\015v_cmp_nlt_f16\021v"
   13340             :     "_cmp_nlt_f16_e32\015v_cmp_nlt_f32\021v_cmp_nlt_f32_e32\015v_cmp_nlt_f64"
   13341             :     "\021v_cmp_nlt_f64_e32\013v_cmp_o_f16\017v_cmp_o_f16_e32\013v_cmp_o_f32\017"
   13342             :     "v_cmp_o_f32_e32\013v_cmp_o_f64\017v_cmp_o_f64_e32\013v_cmp_t_i16\017v_c"
   13343             :     "mp_t_i16_e32\013v_cmp_t_i32\017v_cmp_t_i32_e32\013v_cmp_t_i64\017v_cmp_"
   13344             :     "t_i64_e32\013v_cmp_t_u16\017v_cmp_t_u16_e32\013v_cmp_t_u32\017v_cmp_t_u"
   13345             :     "32_e32\013v_cmp_t_u64\017v_cmp_t_u64_e32\015v_cmp_tru_f16\021v_cmp_tru_"
   13346             :     "f16_e32\015v_cmp_tru_f32\021v_cmp_tru_f32_e32\015v_cmp_tru_f64\021v_cmp"
   13347             :     "_tru_f64_e32\013v_cmp_u_f16\017v_cmp_u_f16_e32\013v_cmp_u_f32\017v_cmp_"
   13348             :     "u_f32_e32\013v_cmp_u_f64\017v_cmp_u_f64_e32\015v_cmps_eq_f32\021v_cmps_"
   13349             :     "eq_f32_e32\015v_cmps_eq_f64\021v_cmps_eq_f64_e32\014v_cmps_f_f32\020v_c"
   13350             :     "mps_f_f32_e32\014v_cmps_f_f64\020v_cmps_f_f64_e32\015v_cmps_ge_f32\021v"
   13351             :     "_cmps_ge_f32_e32\015v_cmps_ge_f64\021v_cmps_ge_f64_e32\015v_cmps_gt_f32"
   13352             :     "\021v_cmps_gt_f32_e32\015v_cmps_gt_f64\021v_cmps_gt_f64_e32\015v_cmps_l"
   13353             :     "e_f32\021v_cmps_le_f32_e32\015v_cmps_le_f64\021v_cmps_le_f64_e32\015v_c"
   13354             :     "mps_lg_f32\021v_cmps_lg_f32_e32\015v_cmps_lg_f64\021v_cmps_lg_f64_e32\015"
   13355             :     "v_cmps_lt_f32\021v_cmps_lt_f32_e32\015v_cmps_lt_f64\021v_cmps_lt_f64_e3"
   13356             :     "2\016v_cmps_neq_f32\022v_cmps_neq_f32_e32\016v_cmps_neq_f64\022v_cmps_n"
   13357             :     "eq_f64_e32\016v_cmps_nge_f32\022v_cmps_nge_f32_e32\016v_cmps_nge_f64\022"
   13358             :     "v_cmps_nge_f64_e32\016v_cmps_ngt_f32\022v_cmps_ngt_f32_e32\016v_cmps_ng"
   13359             :     "t_f64\022v_cmps_ngt_f64_e32\016v_cmps_nle_f32\022v_cmps_nle_f32_e32\016"
   13360             :     "v_cmps_nle_f64\022v_cmps_nle_f64_e32\016v_cmps_nlg_f32\022v_cmps_nlg_f3"
   13361             :     "2_e32\016v_cmps_nlg_f64\022v_cmps_nlg_f64_e32\016v_cmps_nlt_f32\022v_cm"
   13362             :     "ps_nlt_f32_e32\016v_cmps_nlt_f64\022v_cmps_nlt_f64_e32\014v_cmps_o_f32\020"
   13363             :     "v_cmps_o_f32_e32\014v_cmps_o_f64\020v_cmps_o_f64_e32\016v_cmps_tru_f32\022"
   13364             :     "v_cmps_tru_f32_e32\016v_cmps_tru_f64\022v_cmps_tru_f64_e32\014v_cmps_u_"
   13365             :     "f32\020v_cmps_u_f32_e32\014v_cmps_u_f64\020v_cmps_u_f64_e32\016v_cmpsx_"
   13366             :     "eq_f32\022v_cmpsx_eq_f32_e32\016v_cmpsx_eq_f64\022v_cmpsx_eq_f64_e32\015"
   13367             :     "v_cmpsx_f_f32\021v_cmpsx_f_f32_e32\015v_cmpsx_f_f64\021v_cmpsx_f_f64_e3"
   13368             :     "2\016v_cmpsx_ge_f32\022v_cmpsx_ge_f32_e32\016v_cmpsx_ge_f64\022v_cmpsx_"
   13369             :     "ge_f64_e32\016v_cmpsx_gt_f32\022v_cmpsx_gt_f32_e32\016v_cmpsx_gt_f64\022"
   13370             :     "v_cmpsx_gt_f64_e32\016v_cmpsx_le_f32\022v_cmpsx_le_f32_e32\016v_cmpsx_l"
   13371             :     "e_f64\022v_cmpsx_le_f64_e32\016v_cmpsx_lg_f32\022v_cmpsx_lg_f32_e32\016"
   13372             :     "v_cmpsx_lg_f64\022v_cmpsx_lg_f64_e32\016v_cmpsx_lt_f32\022v_cmpsx_lt_f3"
   13373             :     "2_e32\016v_cmpsx_lt_f64\022v_cmpsx_lt_f64_e32\017v_cmpsx_neq_f32\023v_c"
   13374             :     "mpsx_neq_f32_e32\017v_cmpsx_neq_f64\023v_cmpsx_neq_f64_e32\017v_cmpsx_n"
   13375             :     "ge_f32\023v_cmpsx_nge_f32_e32\017v_cmpsx_nge_f64\023v_cmpsx_nge_f64_e32"
   13376             :     "\017v_cmpsx_ngt_f32\023v_cmpsx_ngt_f32_e32\017v_cmpsx_ngt_f64\023v_cmps"
   13377             :     "x_ngt_f64_e32\017v_cmpsx_nle_f32\023v_cmpsx_nle_f32_e32\017v_cmpsx_nle_"
   13378             :     "f64\023v_cmpsx_nle_f64_e32\017v_cmpsx_nlg_f32\023v_cmpsx_nlg_f32_e32\017"
   13379             :     "v_cmpsx_nlg_f64\023v_cmpsx_nlg_f64_e32\017v_cmpsx_nlt_f32\023v_cmpsx_nl"
   13380             :     "t_f32_e32\017v_cmpsx_nlt_f64\023v_cmpsx_nlt_f64_e32\015v_cmpsx_o_f32\021"
   13381             :     "v_cmpsx_o_f32_e32\015v_cmpsx_o_f64\021v_cmpsx_o_f64_e32\017v_cmpsx_tru_"
   13382             :     "f32\023v_cmpsx_tru_f32_e32\017v_cmpsx_tru_f64\023v_cmpsx_tru_f64_e32\015"
   13383             :     "v_cmpsx_u_f32\021v_cmpsx_u_f32_e32\015v_cmpsx_u_f64\021v_cmpsx_u_f64_e3"
   13384             :     "2\020v_cmpx_class_f16\024v_cmpx_class_f16_e32\020v_cmpx_class_f32\024v_"
   13385             :     "cmpx_class_f32_e32\020v_cmpx_class_f64\024v_cmpx_class_f64_e32\015v_cmp"
   13386             :     "x_eq_f16\021v_cmpx_eq_f16_e32\015v_cmpx_eq_f32\021v_cmpx_eq_f32_e32\015"
   13387             :     "v_cmpx_eq_f64\021v_cmpx_eq_f64_e32\015v_cmpx_eq_i16\021v_cmpx_eq_i16_e3"
   13388             :     "2\015v_cmpx_eq_i32\021v_cmpx_eq_i32_e32\015v_cmpx_eq_i64\021v_cmpx_eq_i"
   13389             :     "64_e32\015v_cmpx_eq_u16\021v_cmpx_eq_u16_e32\015v_cmpx_eq_u32\021v_cmpx"
   13390             :     "_eq_u32_e32\015v_cmpx_eq_u64\021v_cmpx_eq_u64_e32\014v_cmpx_f_f16\020v_"
   13391             :     "cmpx_f_f16_e32\014v_cmpx_f_f32\020v_cmpx_f_f32_e32\014v_cmpx_f_f64\020v"
   13392             :     "_cmpx_f_f64_e32\014v_cmpx_f_i16\020v_cmpx_f_i16_e32\014v_cmpx_f_i32\020"
   13393             :     "v_cmpx_f_i32_e32\014v_cmpx_f_i64\020v_cmpx_f_i64_e32\014v_cmpx_f_u16\020"
   13394             :     "v_cmpx_f_u16_e32\014v_cmpx_f_u32\020v_cmpx_f_u32_e32\014v_cmpx_f_u64\020"
   13395             :     "v_cmpx_f_u64_e32\015v_cmpx_ge_f16\021v_cmpx_ge_f16_e32\015v_cmpx_ge_f32"
   13396             :     "\021v_cmpx_ge_f32_e32\015v_cmpx_ge_f64\021v_cmpx_ge_f64_e32\015v_cmpx_g"
   13397             :     "e_i16\021v_cmpx_ge_i16_e32\015v_cmpx_ge_i32\021v_cmpx_ge_i32_e32\015v_c"
   13398             :     "mpx_ge_i64\021v_cmpx_ge_i64_e32\015v_cmpx_ge_u16\021v_cmpx_ge_u16_e32\015"
   13399             :     "v_cmpx_ge_u32\021v_cmpx_ge_u32_e32\015v_cmpx_ge_u64\021v_cmpx_ge_u64_e3"
   13400             :     "2\015v_cmpx_gt_f16\021v_cmpx_gt_f16_e32\015v_cmpx_gt_f32\021v_cmpx_gt_f"
   13401             :     "32_e32\015v_cmpx_gt_f64\021v_cmpx_gt_f64_e32\015v_cmpx_gt_i16\021v_cmpx"
   13402             :     "_gt_i16_e32\015v_cmpx_gt_i32\021v_cmpx_gt_i32_e32\015v_cmpx_gt_i64\021v"
   13403             :     "_cmpx_gt_i64_e32\015v_cmpx_gt_u16\021v_cmpx_gt_u16_e32\015v_cmpx_gt_u32"
   13404             :     "\021v_cmpx_gt_u32_e32\015v_cmpx_gt_u64\021v_cmpx_gt_u64_e32\015v_cmpx_l"
   13405             :     "e_f16\021v_cmpx_le_f16_e32\015v_cmpx_le_f32\021v_cmpx_le_f32_e32\015v_c"
   13406             :     "mpx_le_f64\021v_cmpx_le_f64_e32\015v_cmpx_le_i16\021v_cmpx_le_i16_e32\015"
   13407             :     "v_cmpx_le_i32\021v_cmpx_le_i32_e32\015v_cmpx_le_i64\021v_cmpx_le_i64_e3"
   13408             :     "2\015v_cmpx_le_u16\021v_cmpx_le_u16_e32\015v_cmpx_le_u32\021v_cmpx_le_u"
   13409             :     "32_e32\015v_cmpx_le_u64\021v_cmpx_le_u64_e32\015v_cmpx_lg_f16\021v_cmpx"
   13410             :     "_lg_f16_e32\015v_cmpx_lg_f32\021v_cmpx_lg_f32_e32\015v_cmpx_lg_f64\021v"
   13411             :     "_cmpx_lg_f64_e32\015v_cmpx_lt_f16\021v_cmpx_lt_f16_e32\015v_cmpx_lt_f32"
   13412             :     "\021v_cmpx_lt_f32_e32\015v_cmpx_lt_f64\021v_cmpx_lt_f64_e32\015v_cmpx_l"
   13413             :     "t_i16\021v_cmpx_lt_i16_e32\015v_cmpx_lt_i32\021v_cmpx_lt_i32_e32\015v_c"
   13414             :     "mpx_lt_i64\021v_cmpx_lt_i64_e32\015v_cmpx_lt_u16\021v_cmpx_lt_u16_e32\015"
   13415             :     "v_cmpx_lt_u32\021v_cmpx_lt_u32_e32\015v_cmpx_lt_u64\021v_cmpx_lt_u64_e3"
   13416             :     "2\015v_cmpx_ne_i16\021v_cmpx_ne_i16_e32\015v_cmpx_ne_i32\021v_cmpx_ne_i"
   13417             :     "32_e32\015v_cmpx_ne_i64\021v_cmpx_ne_i64_e32\015v_cmpx_ne_u16\021v_cmpx"
   13418             :     "_ne_u16_e32\015v_cmpx_ne_u32\021v_cmpx_ne_u32_e32\015v_cmpx_ne_u64\021v"
   13419             :     "_cmpx_ne_u64_e32\016v_cmpx_neq_f16\022v_cmpx_neq_f16_e32\016v_cmpx_neq_"
   13420             :     "f32\022v_cmpx_neq_f32_e32\016v_cmpx_neq_f64\022v_cmpx_neq_f64_e32\016v_"
   13421             :     "cmpx_nge_f16\022v_cmpx_nge_f16_e32\016v_cmpx_nge_f32\022v_cmpx_nge_f32_"
   13422             :     "e32\016v_cmpx_nge_f64\022v_cmpx_nge_f64_e32\016v_cmpx_ngt_f16\022v_cmpx"
   13423             :     "_ngt_f16_e32\016v_cmpx_ngt_f32\022v_cmpx_ngt_f32_e32\016v_cmpx_ngt_f64\022"
   13424             :     "v_cmpx_ngt_f64_e32\016v_cmpx_nle_f16\022v_cmpx_nle_f16_e32\016v_cmpx_nl"
   13425             :     "e_f32\022v_cmpx_nle_f32_e32\016v_cmpx_nle_f64\022v_cmpx_nle_f64_e32\016"
   13426             :     "v_cmpx_nlg_f16\022v_cmpx_nlg_f16_e32\016v_cmpx_nlg_f32\022v_cmpx_nlg_f3"
   13427             :     "2_e32\016v_cmpx_nlg_f64\022v_cmpx_nlg_f64_e32\016v_cmpx_nlt_f16\022v_cm"
   13428             :     "px_nlt_f16_e32\016v_cmpx_nlt_f32\022v_cmpx_nlt_f32_e32\016v_cmpx_nlt_f6"
   13429             :     "4\022v_cmpx_nlt_f64_e32\014v_cmpx_o_f16\020v_cmpx_o_f16_e32\014v_cmpx_o"
   13430             :     "_f32\020v_cmpx_o_f32_e32\014v_cmpx_o_f64\020v_cmpx_o_f64_e32\014v_cmpx_"
   13431             :     "t_i16\020v_cmpx_t_i16_e32\014v_cmpx_t_i32\020v_cmpx_t_i32_e32\014v_cmpx"
   13432             :     "_t_i64\020v_cmpx_t_i64_e32\014v_cmpx_t_u16\020v_cmpx_t_u16_e32\014v_cmp"
   13433             :     "x_t_u32\020v_cmpx_t_u32_e32\014v_cmpx_t_u64\020v_cmpx_t_u64_e32\016v_cm"
   13434             :     "px_tru_f16\022v_cmpx_tru_f16_e32\016v_cmpx_tru_f32\022v_cmpx_tru_f32_e3"
   13435             :     "2\016v_cmpx_tru_f64\022v_cmpx_tru_f64_e32\014v_cmpx_u_f16\020v_cmpx_u_f"
   13436             :     "16_e32\014v_cmpx_u_f32\020v_cmpx_u_f32_e32\014v_cmpx_u_f64\020v_cmpx_u_"
   13437             :     "f64_e32\015v_cndmask_b32\tv_cos_f16\tv_cos_f32\014v_cubeid_f32\014v_cub"
   13438             :     "ema_f32\014v_cubesc_f32\014v_cubetc_f32\015v_cvt_f16_f32\015v_cvt_f16_i"
   13439             :     "16\015v_cvt_f16_u16\015v_cvt_f32_f16\015v_cvt_f32_f64\015v_cvt_f32_i32\015"
   13440             :     "v_cvt_f32_u32\020v_cvt_f32_ubyte0\020v_cvt_f32_ubyte1\020v_cvt_f32_ubyt"
   13441             :     "e2\020v_cvt_f32_ubyte3\015v_cvt_f64_f32\015v_cvt_f64_i32\015v_cvt_f64_u"
   13442             :     "32\021v_cvt_flr_i32_f32\015v_cvt_i16_f16\015v_cvt_i32_f32\015v_cvt_i32_"
   13443             :     "f64\022v_cvt_norm_i16_f16\022v_cvt_norm_u16_f16\020v_cvt_off_f32_i4\020"
   13444             :     "v_cvt_pk_i16_i32\020v_cvt_pk_u16_u32\017v_cvt_pk_u8_f32\024v_cvt_pkaccu"
   13445             :     "m_u8_f32\024v_cvt_pknorm_i16_f16\024v_cvt_pknorm_i16_f32\024v_cvt_pknor"
   13446             :     "m_u16_f16\024v_cvt_pknorm_u16_f32\023v_cvt_pkrtz_f16_f32\021v_cvt_rpi_i"
   13447             :     "32_f32\015v_cvt_u16_f16\015v_cvt_u32_f32\015v_cvt_u32_f64\017v_div_fixu"
   13448             :     "p_f16\017v_div_fixup_f32\017v_div_fixup_f64\026v_div_fixup_legacy_f16\016"
   13449             :     "v_div_fmas_f32\016v_div_fmas_f64\017v_div_scale_f32\017v_div_scale_f64\016"
   13450             :     "v_dot2_f32_f16\016v_dot2_i32_i16\016v_dot2_u32_u16\015v_dot4_i32_i8\015"
   13451             :     "v_dot4_u32_u8\015v_dot8_i32_i4\015v_dot8_u32_u4\tv_exp_f16\tv_exp_f32\020"
   13452             :     "v_exp_legacy_f32\nv_ffbh_i32\nv_ffbh_u32\nv_ffbl_b32\013v_floor_f16\013"
   13453             :     "v_floor_f32\013v_floor_f64\tv_fma_f16\tv_fma_f32\tv_fma_f64\020v_fma_le"
   13454             :     "gacy_f16\015v_fma_mix_f32\017v_fma_mixhi_f16\017v_fma_mixlo_f16\nv_fmac"
   13455             :     "_f32\013v_fract_f16\013v_fract_f32\013v_fract_f64\023v_frexp_exp_i16_f1"
   13456             :     "6\023v_frexp_exp_i32_f32\023v_frexp_exp_i32_f64\020v_frexp_mant_f16\020"
   13457             :     "v_frexp_mant_f32\020v_frexp_mant_f64\020v_interp_mov_f32\017v_interp_p1"
   13458             :     "_f32\021v_interp_p1ll_f16\021v_interp_p1lv_f16\017v_interp_p2_f16\017v_"
   13459             :     "interp_p2_f32\026v_interp_p2_legacy_f16\013v_ldexp_f16\013v_ldexp_f32\013"
   13460             :     "v_ldexp_f64\tv_lerp_u8\017v_log_clamp_f32\tv_log_f16\tv_log_f32\020v_lo"
   13461             :     "g_legacy_f32\016v_lshl_add_u32\nv_lshl_b32\nv_lshl_b64\015v_lshl_or_b32"
   13462             :     "\015v_lshlrev_b16\015v_lshlrev_b32\015v_lshlrev_b64\nv_lshr_b32\nv_lshr"
   13463             :     "_b64\015v_lshrrev_b16\015v_lshrrev_b32\015v_lshrrev_b64\tv_mac_f16\tv_m"
   13464             :     "ac_f32\020v_mac_legacy_f32\tv_mad_f16\tv_mad_f32\tv_mad_i16\015v_mad_i3"
   13465             :     "2_i16\015v_mad_i32_i24\015v_mad_i64_i32\020v_mad_legacy_f16\020v_mad_le"
   13466             :     "gacy_f32\020v_mad_legacy_i16\020v_mad_legacy_u16\015v_mad_mix_f32\017v_"
   13467             :     "mad_mixhi_f16\017v_mad_mixlo_f16\tv_mad_u16\015v_mad_u32_u16\015v_mad_u"
   13468             :     "32_u24\015v_mad_u64_u32\013v_madak_f16\013v_madak_f32\013v_madmk_f16\013"
   13469             :     "v_madmk_f32\nv_max3_f16\nv_max3_f32\nv_max3_i16\nv_max3_i32\nv_max3_u16"
   13470             :     "\nv_max3_u32\tv_max_f16\tv_max_f32\tv_max_f64\tv_max_i16\tv_max_i32\020"
   13471             :     "v_max_legacy_f32\tv_max_u16\tv_max_u32\022v_mbcnt_hi_u32_b32\022v_mbcnt"
   13472             :     "_lo_u32_b32\nv_med3_f16\nv_med3_f32\nv_med3_i16\nv_med3_i32\nv_med3_u16"
   13473             :     "\nv_med3_u32\nv_min3_f16\nv_min3_f32\nv_min3_i16\nv_min3_i32\nv_min3_u1"
   13474             :     "6\nv_min3_u32\tv_min_f16\tv_min_f32\tv_min_f64\tv_min_i16\tv_min_i32\020"
   13475             :     "v_min_legacy_f32\tv_min_u16\tv_min_u32\tv_mov_b32\015v_mov_fed_b32\015v"
   13476             :     "_movreld_b32\015v_movrels_b32\016v_movrelsd_b32\021v_mqsad_pk_u16_u8\016"
   13477             :     "v_mqsad_u32_u8\tv_msad_u8\tv_mul_f16\tv_mul_f32\tv_mul_f64\014v_mul_hi_"
   13478             :     "i32\020v_mul_hi_i32_i24\014v_mul_hi_u32\020v_mul_hi_u32_u24\015v_mul_i3"
   13479             :     "2_i24\020v_mul_legacy_f32\014v_mul_lo_i32\014v_mul_lo_u16\014v_mul_lo_u"
   13480             :     "32\015v_mul_u32_u24\014v_mullit_f32\005v_nop\tv_not_b32\tv_or3_b32\010v"
   13481             :     "_or_b32\016v_pack_b32_f16\nv_perm_b32\014v_pk_add_f16\014v_pk_add_i16\014"
   13482             :     "v_pk_add_u16\020v_pk_ashrrev_i16\014v_pk_fma_f16\020v_pk_lshlrev_b16\020"
   13483             :     "v_pk_lshrrev_b16\014v_pk_mad_i16\014v_pk_mad_u16\014v_pk_max_f16\014v_p"
   13484             :     "k_max_i16\014v_pk_max_u16\014v_pk_min_f16\014v_pk_min_i16\014v_pk_min_u"
   13485             :     "16\014v_pk_mul_f16\017v_pk_mul_lo_u16\014v_pk_sub_i16\014v_pk_sub_u16\020"
   13486             :     "v_qsad_pk_u16_u8\017v_rcp_clamp_f32\017v_rcp_clamp_f64\tv_rcp_f16\tv_rc"
   13487             :     "p_f32\tv_rcp_f64\017v_rcp_iflag_f32\020v_rcp_legacy_f32\023v_readfirstl"
   13488             :     "ane_b32\016v_readlane_b32\013v_rndne_f16\013v_rndne_f32\013v_rndne_f64\017"
   13489             :     "v_rsq_clamp_f32\017v_rsq_clamp_f64\tv_rsq_f16\tv_rsq_f32\tv_rsq_f64\020"
   13490             :     "v_rsq_legacy_f32\013v_sad_hi_u8\tv_sad_u16\tv_sad_u32\010v_sad_u8\017v_"
   13491             :     "sat_pk_u8_i16\032v_screen_partition_4se_b32\tv_sin_f16\tv_sin_f32\nv_sq"
   13492             :     "rt_f16\nv_sqrt_f32\nv_sqrt_f64\014v_sub_co_u32\tv_sub_f16\tv_sub_f32\tv"
   13493             :     "_sub_i16\tv_sub_i32\tv_sub_u16\tv_sub_u32\015v_subb_co_u32\nv_subb_u32\020"
   13494             :     "v_subbrev_co_u32\015v_subbrev_u32\017v_subrev_co_u32\014v_subrev_f16\014"
   13495             :     "v_subrev_f32\014v_subrev_i32\014v_subrev_u16\014v_subrev_u32\nv_swap_b3"
   13496             :     "2\020v_trig_preop_f64\013v_trunc_f16\013v_trunc_f32\013v_trunc_f64\017v"
   13497             :     "_writelane_b32\tv_xad_u32\nv_xnor_b32\tv_xor_b32";
   13498             : 
   13499             : namespace {
   13500             :   struct MatchEntry {
   13501             :     uint16_t Mnemonic;
   13502             :     uint16_t Opcode;
   13503             :     uint16_t ConvertFn;
   13504             :     uint64_t RequiredFeatures;
   13505             :     uint8_t Classes[13];
   13506           0 :     StringRef getMnemonic() const {
   13507       24534 :       return StringRef(MnemonicTable + Mnemonic + 1,
   13508       24534 :                        MnemonicTable[Mnemonic]);
   13509             :     }
   13510             :   };
   13511             : 
   13512             :   // Predicate for searching for an opcode.
   13513             :   struct LessOpcode {
   13514           0 :     bool operator()(const MatchEntry &LHS, StringRef RHS) {
   13515           0 :       return LHS.getMnemonic() < RHS;
   13516             :     }
   13517           0 :     bool operator()(StringRef LHS, const MatchEntry &RHS) {
   13518           0 :       return LHS < RHS.getMnemonic();
   13519             :     }
   13520             :     bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
   13521             :       return LHS.getMnemonic() < RHS.getMnemonic();
   13522             :     }
   13523             :   };
   13524             : } // end anonymous namespace.
   13525             : 
   13526             : static const MatchEntry MatchTable0[] = {
   13527             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13528             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13529             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13530             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13531             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13532             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13533             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13534             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13535             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13536             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13537             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13538             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13539             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13540             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13541             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13542             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13543             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13544             :   { 0 /* buffer_atomic_add */, AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13545             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13546             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13547             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13548             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13549             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13550             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13551             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13552             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13553             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13554             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13555             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13556             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13557             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13558             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13559             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13560             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13561             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13562             :   { 18 /* buffer_atomic_add_x2 */, AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13563             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13564             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13565             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13566             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13567             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13568             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13569             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13570             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13571             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13572             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13573             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13574             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13575             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13576             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13577             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13578             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13579             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13580             :   { 39 /* buffer_atomic_and */, AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13581             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13582             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13583             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13584             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13585             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13586             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13587             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13588             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13589             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13590             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13591             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13592             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13593             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13594             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13595             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13596             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13597             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13598             :   { 57 /* buffer_atomic_and_x2 */, AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13599             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13600             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13601             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13602             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13603             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13604             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13605             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13606             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13607             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13608             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13609             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13610             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13611             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13612             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13613             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13614             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13615             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13616             :   { 78 /* buffer_atomic_cmpswap */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13617             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13618             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13619             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13620             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13621             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13622             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13623             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13624             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13625             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13626             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13627             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13628             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13629             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13630             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13631             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13632             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13633             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13634             :   { 100 /* buffer_atomic_cmpswap_x2 */, AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13635             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13636             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13637             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13638             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13639             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13640             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13641             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13642             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13643             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13644             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13645             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13646             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13647             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13648             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13649             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13650             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13651             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13652             :   { 125 /* buffer_atomic_dec */, AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13653             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13654             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13655             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13656             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13657             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13658             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13659             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13660             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13661             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13662             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13663             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13664             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13665             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13666             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13667             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13668             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13669             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13670             :   { 143 /* buffer_atomic_dec_x2 */, AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13671             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13672             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13673             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13674             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13675             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13676             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13677             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13678             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13679             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13680             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13681             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13682             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13683             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13684             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13685             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13686             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13687             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13688             :   { 164 /* buffer_atomic_inc */, AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13689             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13690             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13691             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13692             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13693             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13694             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13695             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13696             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13697             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13698             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13699             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13700             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13701             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13702             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13703             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13704             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13705             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13706             :   { 182 /* buffer_atomic_inc_x2 */, AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13707             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13708             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13709             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13710             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13711             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13712             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13713             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13714             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13715             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13716             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13717             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13718             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13719             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13720             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13721             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13722             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13723             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13724             :   { 203 /* buffer_atomic_or */, AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13725             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13726             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13727             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13728             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13729             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13730             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13731             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13732             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13733             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13734             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13735             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13736             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13737             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13738             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13739             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13740             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13741             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13742             :   { 220 /* buffer_atomic_or_x2 */, AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13743             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13744             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13745             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13746             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13747             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13748             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13749             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13750             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13751             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13752             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13753             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13754             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13755             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13756             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13757             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13758             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13759             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13760             :   { 240 /* buffer_atomic_smax */, AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13761             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13762             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13763             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13764             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13765             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13766             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13767             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13768             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13769             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13770             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13771             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13772             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13773             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13774             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13775             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13776             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13777             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13778             :   { 259 /* buffer_atomic_smax_x2 */, AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13779             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13780             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13781             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13782             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13783             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13784             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13785             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13786             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13787             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13788             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13789             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13790             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13791             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13792             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13793             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13794             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13795             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13796             :   { 281 /* buffer_atomic_smin */, AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13797             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13798             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13799             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13800             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13801             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13802             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13803             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13804             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13805             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13806             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13807             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13808             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13809             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13810             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13811             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13812             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13813             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13814             :   { 300 /* buffer_atomic_smin_x2 */, AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13815             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13816             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13817             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13818             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13819             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13820             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13821             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13822             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13823             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13824             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13825             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13826             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13827             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13828             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13829             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13830             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13831             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13832             :   { 322 /* buffer_atomic_sub */, AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13833             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13834             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13835             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13836             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13837             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13838             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13839             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13840             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13841             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13842             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13843             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13844             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13845             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13846             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13847             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13848             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13849             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13850             :   { 340 /* buffer_atomic_sub_x2 */, AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13851             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13852             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13853             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13854             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13855             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13856             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13857             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13858             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13859             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13860             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13861             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13862             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13863             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13864             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13865             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13866             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13867             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13868             :   { 361 /* buffer_atomic_swap */, AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13869             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13870             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13871             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13872             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13873             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13874             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13875             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13876             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13877             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13878             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13879             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13880             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13881             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13882             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13883             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13884             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13885             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13886             :   { 380 /* buffer_atomic_swap_x2 */, AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13887             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13888             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13889             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13890             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13891             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13892             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13893             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13894             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13895             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13896             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13897             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13898             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13899             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13900             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13901             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13902             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13903             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13904             :   { 402 /* buffer_atomic_umax */, AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13905             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13906             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13907             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13908             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13909             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13910             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13911             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13912             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13913             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13914             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13915             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13916             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13917             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13918             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13919             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13920             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13921             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13922             :   { 421 /* buffer_atomic_umax_x2 */, AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13923             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13924             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13925             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13926             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13927             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13928             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13929             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13930             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13931             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13932             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13933             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13934             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13935             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13936             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13937             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13938             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13939             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13940             :   { 443 /* buffer_atomic_umin */, AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13941             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13942             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13943             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13944             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13945             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13946             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13947             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13948             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13949             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13950             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13951             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13952             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13953             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13954             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13955             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13956             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13957             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13958             :   { 462 /* buffer_atomic_umin_x2 */, AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13959             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13960             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13961             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13962             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13963             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13964             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13965             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13966             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13967             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13968             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13969             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13970             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13971             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13972             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13973             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13974             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13975             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13976             :   { 484 /* buffer_atomic_xor */, AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13977             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13978             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, },
   13979             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13980             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13981             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmSLC }, },
   13982             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13983             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, },
   13984             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13985             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13986             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13987             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_si, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13988             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, },
   13989             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13990             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13991             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13992             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13993             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_si, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13994             :   { 502 /* buffer_atomic_xor_x2 */, AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi, ConvertCustom_cvtMubufAtomicReturn, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_glc, MCK_ImmSLC }, },
   13995             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   13996             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   13997             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   13998             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   13999             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_ADDR64_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14000             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14001             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14002             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14003             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14004             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14005             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14006             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14007             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14008             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14009             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14010             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14011             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14012             :   { 523 /* buffer_load_dword */, AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14013             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14014             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14015             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14016             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14017             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14018             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14019             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14020             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14021             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14022             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14023             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14024             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14025             :   { 541 /* buffer_load_dwordx2 */, AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14026             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14027             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14028             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14029             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14030             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14031             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14032             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14033             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14034             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14035             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14036             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14037             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14038             :   { 561 /* buffer_load_dwordx3 */, AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14039             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14040             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14041             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14042             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14043             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14044             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14045             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14046             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14047             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14048             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14049             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14050             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14051             :   { 581 /* buffer_load_dwordx4 */, AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14052             :   { 601 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14053             :   { 601 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14054             :   { 601 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14055             :   { 601 /* buffer_load_format_d16_hi_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14056             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14057             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14058             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14059             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14060             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14061             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14062             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14063             :   { 629 /* buffer_load_format_d16_x */, AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14064             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14065             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14066             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14067             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14068             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14069             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14070             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14071             :   { 654 /* buffer_load_format_d16_xy */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14072             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14073             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14074             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14075             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14076             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14077             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14078             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14079             :   { 680 /* buffer_load_format_d16_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14080             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14081             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14082             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14083             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14084             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14085             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14086             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14087             :   { 707 /* buffer_load_format_d16_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14088             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14089             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14090             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14091             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14092             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_ADDR64_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14093             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14094             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14095             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14096             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14097             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14098             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14099             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14100             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14101             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14102             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14103             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14104             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14105             :   { 735 /* buffer_load_format_x */, AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14106             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14107             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14108             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14109             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14110             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14111             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14112             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14113             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14114             :   { 756 /* buffer_load_format_xy */, AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14115             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14116             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14117             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14118             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14119             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14120             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14121             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14122             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14123             :   { 778 /* buffer_load_format_xyz */, AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14124             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14125             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14126             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14127             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14128             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14129             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14130             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14131             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14132             :   { 801 /* buffer_load_format_xyzw */, AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14133             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14134             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14135             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14136             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14137             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_ADDR64_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14138             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14139             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14140             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14141             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14142             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14143             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14144             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14145             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14146             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14147             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14148             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14149             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14150             :   { 825 /* buffer_load_sbyte */, AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14151             :   { 843 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14152             :   { 843 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14153             :   { 843 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14154             :   { 843 /* buffer_load_sbyte_d16 */, AMDGPU::BUFFER_LOAD_SBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14155             :   { 865 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14156             :   { 865 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14157             :   { 865 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14158             :   { 865 /* buffer_load_sbyte_d16_hi */, AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14159             :   { 890 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14160             :   { 890 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14161             :   { 890 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14162             :   { 890 /* buffer_load_short_d16 */, AMDGPU::BUFFER_LOAD_SHORT_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14163             :   { 912 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14164             :   { 912 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14165             :   { 912 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14166             :   { 912 /* buffer_load_short_d16_hi */, AMDGPU::BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14167             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14168             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14169             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14170             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14171             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_ADDR64_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14172             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14173             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14174             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14175             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14176             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14177             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14178             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14179             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14180             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14181             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14182             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14183             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14184             :   { 937 /* buffer_load_sshort */, AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14185             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14186             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14187             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14188             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14189             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_ADDR64_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14190             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14191             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14192             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14193             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14194             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14195             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14196             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14197             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14198             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14199             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14200             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14201             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14202             :   { 956 /* buffer_load_ubyte */, AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14203             :   { 974 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14204             :   { 974 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14205             :   { 974 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14206             :   { 974 /* buffer_load_ubyte_d16 */, AMDGPU::BUFFER_LOAD_UBYTE_D16_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14207             :   { 996 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14208             :   { 996 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14209             :   { 996 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14210             :   { 996 /* buffer_load_ubyte_d16_hi */, AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14211             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14212             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14213             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14214             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14215             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_ADDR64_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14216             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14217             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14218             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14219             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14220             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14221             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14222             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14223             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14224             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14225             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_si, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14226             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN_vi, ConvertCustom_cvtMubufLds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_lds }, },
   14227             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14228             :   { 1021 /* buffer_load_ushort */, AMDGPU::BUFFER_LOAD_USHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14229             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14230             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14231             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14232             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14233             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14234             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14235             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14236             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14237             :   { 1040 /* buffer_store_byte */, AMDGPU::BUFFER_STORE_BYTE_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14238             :   { 1058 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14239             :   { 1058 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14240             :   { 1058 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14241             :   { 1058 /* buffer_store_byte_d16_hi */, AMDGPU::BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14242             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14243             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14244             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14245             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14246             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14247             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14248             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14249             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14250             :   { 1083 /* buffer_store_dword */, AMDGPU::BUFFER_STORE_DWORD_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14251             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14252             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14253             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14254             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14255             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14256             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14257             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14258             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14259             :   { 1102 /* buffer_store_dwordx2 */, AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14260             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14261             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14262             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14263             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14264             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14265             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14266             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14267             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14268             :   { 1123 /* buffer_store_dwordx3 */, AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14269             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14270             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14271             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14272             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14273             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14274             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14275             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14276             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14277             :   { 1144 /* buffer_store_dwordx4 */, AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14278             :   { 1165 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14279             :   { 1165 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14280             :   { 1165 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14281             :   { 1165 /* buffer_store_format_d16_hi_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14282             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14283             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14284             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14285             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14286             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14287             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14288             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14289             :   { 1194 /* buffer_store_format_d16_x */, AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14290             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14291             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14292             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14293             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14294             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14295             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14296             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14297             :   { 1220 /* buffer_store_format_d16_xy */, AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14298             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14299             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14300             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14301             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14302             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14303             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14304             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14305             :   { 1247 /* buffer_store_format_d16_xyz */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14306             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14307             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14308             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14309             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14310             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14311             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14312             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMubuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14313             :   { 1275 /* buffer_store_format_d16_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14314             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14315             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14316             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14317             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14318             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14319             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14320             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14321             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14322             :   { 1304 /* buffer_store_format_x */, AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14323             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14324             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14325             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14326             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14327             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14328             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14329             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14330             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14331             :   { 1326 /* buffer_store_format_xy */, AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14332             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14333             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14334             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14335             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14336             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14337             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14338             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14339             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14340             :   { 1349 /* buffer_store_format_xyz */, AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14341             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14342             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14343             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14344             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14345             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14346             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14347             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14348             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14349             :   { 1373 /* buffer_store_format_xyzw */, AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14350             :   { 1398 /* buffer_store_lds_dword */, AMDGPU::BUFFER_STORE_LDS_DWORD_vi, ConvertCustom_cvtMubufLds, Feature_isVI|Feature_isVI, { MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_lds, MCK_ImmGLC, MCK_ImmSLC }, },
   14351             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14352             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14353             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_ADDR64_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14354             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14355             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14356             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14357             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14358             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_si, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14359             :   { 1421 /* buffer_store_short */, AMDGPU::BUFFER_STORE_SHORT_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14360             :   { 1440 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14361             :   { 1440 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_IDXEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14362             :   { 1440 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14363             :   { 1440 /* buffer_store_short_d16_hi */, AMDGPU::BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi, ConvertCustom_cvtMubuf, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   14364             :   { 1466 /* buffer_wbinvl1 */, AMDGPU::BUFFER_WBINVL1_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, {  }, },
   14365             :   { 1466 /* buffer_wbinvl1 */, AMDGPU::BUFFER_WBINVL1_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, {  }, },
   14366             :   { 1481 /* buffer_wbinvl1_sc */, AMDGPU::BUFFER_WBINVL1_SC_si, Convert_NoOperands, Feature_isSI|Feature_isSICI, {  }, },
   14367             :   { 1499 /* buffer_wbinvl1_vol */, AMDGPU::BUFFER_WBINVL1_VOL_ci, Convert_NoOperands, Feature_isCIVI|Feature_isCIOnly, {  }, },
   14368             :   { 1499 /* buffer_wbinvl1_vol */, AMDGPU::BUFFER_WBINVL1_VOL_vi, Convert_NoOperands, Feature_isCIVI|Feature_isVI, {  }, },
   14369             :   { 1518 /* ds_add_f32 */, AMDGPU::DS_ADD_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14370             :   { 1529 /* ds_add_rtn_f32 */, AMDGPU::DS_ADD_RTN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14371             :   { 1544 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14372             :   { 1544 /* ds_add_rtn_u32 */, AMDGPU::DS_ADD_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14373             :   { 1559 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14374             :   { 1559 /* ds_add_rtn_u64 */, AMDGPU::DS_ADD_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14375             :   { 1574 /* ds_add_src2_f32 */, AMDGPU::DS_ADD_SRC2_F32_vi, ConvertCustom_cvtDS, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14376             :   { 1590 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14377             :   { 1590 /* ds_add_src2_u32 */, AMDGPU::DS_ADD_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14378             :   { 1606 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14379             :   { 1606 /* ds_add_src2_u64 */, AMDGPU::DS_ADD_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14380             :   { 1622 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14381             :   { 1622 /* ds_add_u32 */, AMDGPU::DS_ADD_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14382             :   { 1633 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14383             :   { 1633 /* ds_add_u64 */, AMDGPU::DS_ADD_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14384             :   { 1644 /* ds_and_b32 */, AMDGPU::DS_AND_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14385             :   { 1644 /* ds_and_b32 */, AMDGPU::DS_AND_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14386             :   { 1655 /* ds_and_b64 */, AMDGPU::DS_AND_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14387             :   { 1655 /* ds_and_b64 */, AMDGPU::DS_AND_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14388             :   { 1666 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14389             :   { 1666 /* ds_and_rtn_b32 */, AMDGPU::DS_AND_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14390             :   { 1681 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14391             :   { 1681 /* ds_and_rtn_b64 */, AMDGPU::DS_AND_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14392             :   { 1696 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14393             :   { 1696 /* ds_and_src2_b32 */, AMDGPU::DS_AND_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14394             :   { 1712 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14395             :   { 1712 /* ds_and_src2_b64 */, AMDGPU::DS_AND_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14396             :   { 1728 /* ds_append */, AMDGPU::DS_APPEND_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14397             :   { 1728 /* ds_append */, AMDGPU::DS_APPEND_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14398             :   { 1738 /* ds_bpermute_b32 */, AMDGPU::DS_BPERMUTE_B32_vi, ConvertCustom_cvtDS, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
   14399             :   { 1754 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14400             :   { 1754 /* ds_cmpst_b32 */, AMDGPU::DS_CMPST_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14401             :   { 1767 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14402             :   { 1767 /* ds_cmpst_b64 */, AMDGPU::DS_CMPST_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14403             :   { 1780 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14404             :   { 1780 /* ds_cmpst_f32 */, AMDGPU::DS_CMPST_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14405             :   { 1793 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14406             :   { 1793 /* ds_cmpst_f64 */, AMDGPU::DS_CMPST_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14407             :   { 1806 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14408             :   { 1806 /* ds_cmpst_rtn_b32 */, AMDGPU::DS_CMPST_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14409             :   { 1823 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14410             :   { 1823 /* ds_cmpst_rtn_b64 */, AMDGPU::DS_CMPST_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14411             :   { 1840 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14412             :   { 1840 /* ds_cmpst_rtn_f32 */, AMDGPU::DS_CMPST_RTN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14413             :   { 1857 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14414             :   { 1857 /* ds_cmpst_rtn_f64 */, AMDGPU::DS_CMPST_RTN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14415             :   { 1874 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_si, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14416             :   { 1874 /* ds_condxchg32_rtn_b64 */, AMDGPU::DS_CONDXCHG32_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14417             :   { 1896 /* ds_consume */, AMDGPU::DS_CONSUME_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14418             :   { 1896 /* ds_consume */, AMDGPU::DS_CONSUME_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14419             :   { 1907 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14420             :   { 1907 /* ds_dec_rtn_u32 */, AMDGPU::DS_DEC_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14421             :   { 1922 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14422             :   { 1922 /* ds_dec_rtn_u64 */, AMDGPU::DS_DEC_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14423             :   { 1937 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14424             :   { 1937 /* ds_dec_src2_u32 */, AMDGPU::DS_DEC_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14425             :   { 1953 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14426             :   { 1953 /* ds_dec_src2_u64 */, AMDGPU::DS_DEC_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14427             :   { 1969 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14428             :   { 1969 /* ds_dec_u32 */, AMDGPU::DS_DEC_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14429             :   { 1980 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14430             :   { 1980 /* ds_dec_u64 */, AMDGPU::DS_DEC_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14431             :   { 1991 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_si, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14432             :   { 1991 /* ds_gws_barrier */, AMDGPU::DS_GWS_BARRIER_vi, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14433             :   { 2006 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_si, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14434             :   { 2006 /* ds_gws_init */, AMDGPU::DS_GWS_INIT_vi, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14435             :   { 2018 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_si, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14436             :   { 2018 /* ds_gws_sema_br */, AMDGPU::DS_GWS_SEMA_BR_vi, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14437             :   { 2033 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_si, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isSICI, { MCK_ImmOffset, MCK_gds }, },
   14438             :   { 2033 /* ds_gws_sema_p */, AMDGPU::DS_GWS_SEMA_P_vi, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isVI, { MCK_ImmOffset, MCK_gds }, },
   14439             :   { 2047 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_si, ConvertCustom_cvtDSGds, Feature_isCIVI|Feature_isSICI, { MCK_ImmOffset, MCK_gds }, },
   14440             :   { 2047 /* ds_gws_sema_release_all */, AMDGPU::DS_GWS_SEMA_RELEASE_ALL_vi, ConvertCustom_cvtDSGds, Feature_isCIVI|Feature_isVI, { MCK_ImmOffset, MCK_gds }, },
   14441             :   { 2071 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_si, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isSICI, { MCK_ImmOffset, MCK_gds }, },
   14442             :   { 2071 /* ds_gws_sema_v */, AMDGPU::DS_GWS_SEMA_V_vi, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isVI, { MCK_ImmOffset, MCK_gds }, },
   14443             :   { 2085 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14444             :   { 2085 /* ds_inc_rtn_u32 */, AMDGPU::DS_INC_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14445             :   { 2100 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14446             :   { 2100 /* ds_inc_rtn_u64 */, AMDGPU::DS_INC_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14447             :   { 2115 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14448             :   { 2115 /* ds_inc_src2_u32 */, AMDGPU::DS_INC_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14449             :   { 2131 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14450             :   { 2131 /* ds_inc_src2_u64 */, AMDGPU::DS_INC_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14451             :   { 2147 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14452             :   { 2147 /* ds_inc_u32 */, AMDGPU::DS_INC_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14453             :   { 2158 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14454             :   { 2158 /* ds_inc_u64 */, AMDGPU::DS_INC_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14455             :   { 2169 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14456             :   { 2169 /* ds_max_f32 */, AMDGPU::DS_MAX_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14457             :   { 2180 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14458             :   { 2180 /* ds_max_f64 */, AMDGPU::DS_MAX_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14459             :   { 2191 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14460             :   { 2191 /* ds_max_i32 */, AMDGPU::DS_MAX_I32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14461             :   { 2202 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14462             :   { 2202 /* ds_max_i64 */, AMDGPU::DS_MAX_I64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14463             :   { 2213 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14464             :   { 2213 /* ds_max_rtn_f32 */, AMDGPU::DS_MAX_RTN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14465             :   { 2228 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14466             :   { 2228 /* ds_max_rtn_f64 */, AMDGPU::DS_MAX_RTN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14467             :   { 2243 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14468             :   { 2243 /* ds_max_rtn_i32 */, AMDGPU::DS_MAX_RTN_I32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14469             :   { 2258 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14470             :   { 2258 /* ds_max_rtn_i64 */, AMDGPU::DS_MAX_RTN_I64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14471             :   { 2273 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14472             :   { 2273 /* ds_max_rtn_u32 */, AMDGPU::DS_MAX_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14473             :   { 2288 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14474             :   { 2288 /* ds_max_rtn_u64 */, AMDGPU::DS_MAX_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14475             :   { 2303 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14476             :   { 2303 /* ds_max_src2_f32 */, AMDGPU::DS_MAX_SRC2_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14477             :   { 2319 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14478             :   { 2319 /* ds_max_src2_f64 */, AMDGPU::DS_MAX_SRC2_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14479             :   { 2335 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14480             :   { 2335 /* ds_max_src2_i32 */, AMDGPU::DS_MAX_SRC2_I32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14481             :   { 2351 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14482             :   { 2351 /* ds_max_src2_i64 */, AMDGPU::DS_MAX_SRC2_I64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14483             :   { 2367 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14484             :   { 2367 /* ds_max_src2_u32 */, AMDGPU::DS_MAX_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14485             :   { 2383 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14486             :   { 2383 /* ds_max_src2_u64 */, AMDGPU::DS_MAX_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14487             :   { 2399 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14488             :   { 2399 /* ds_max_u32 */, AMDGPU::DS_MAX_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14489             :   { 2410 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14490             :   { 2410 /* ds_max_u64 */, AMDGPU::DS_MAX_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14491             :   { 2421 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14492             :   { 2421 /* ds_min_f32 */, AMDGPU::DS_MIN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14493             :   { 2432 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14494             :   { 2432 /* ds_min_f64 */, AMDGPU::DS_MIN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14495             :   { 2443 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14496             :   { 2443 /* ds_min_i32 */, AMDGPU::DS_MIN_I32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14497             :   { 2454 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14498             :   { 2454 /* ds_min_i64 */, AMDGPU::DS_MIN_I64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14499             :   { 2465 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14500             :   { 2465 /* ds_min_rtn_f32 */, AMDGPU::DS_MIN_RTN_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14501             :   { 2480 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14502             :   { 2480 /* ds_min_rtn_f64 */, AMDGPU::DS_MIN_RTN_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14503             :   { 2495 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14504             :   { 2495 /* ds_min_rtn_i32 */, AMDGPU::DS_MIN_RTN_I32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14505             :   { 2510 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14506             :   { 2510 /* ds_min_rtn_i64 */, AMDGPU::DS_MIN_RTN_I64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14507             :   { 2525 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14508             :   { 2525 /* ds_min_rtn_u32 */, AMDGPU::DS_MIN_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14509             :   { 2540 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14510             :   { 2540 /* ds_min_rtn_u64 */, AMDGPU::DS_MIN_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14511             :   { 2555 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14512             :   { 2555 /* ds_min_src2_f32 */, AMDGPU::DS_MIN_SRC2_F32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14513             :   { 2571 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14514             :   { 2571 /* ds_min_src2_f64 */, AMDGPU::DS_MIN_SRC2_F64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14515             :   { 2587 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14516             :   { 2587 /* ds_min_src2_i32 */, AMDGPU::DS_MIN_SRC2_I32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14517             :   { 2603 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14518             :   { 2603 /* ds_min_src2_i64 */, AMDGPU::DS_MIN_SRC2_I64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14519             :   { 2619 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14520             :   { 2619 /* ds_min_src2_u32 */, AMDGPU::DS_MIN_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14521             :   { 2635 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14522             :   { 2635 /* ds_min_src2_u64 */, AMDGPU::DS_MIN_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14523             :   { 2651 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14524             :   { 2651 /* ds_min_u32 */, AMDGPU::DS_MIN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14525             :   { 2662 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14526             :   { 2662 /* ds_min_u64 */, AMDGPU::DS_MIN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14527             :   { 2673 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14528             :   { 2673 /* ds_mskor_b32 */, AMDGPU::DS_MSKOR_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14529             :   { 2686 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14530             :   { 2686 /* ds_mskor_b64 */, AMDGPU::DS_MSKOR_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14531             :   { 2699 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14532             :   { 2699 /* ds_mskor_rtn_b32 */, AMDGPU::DS_MSKOR_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14533             :   { 2716 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14534             :   { 2716 /* ds_mskor_rtn_b64 */, AMDGPU::DS_MSKOR_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14535             :   { 2733 /* ds_nop */, AMDGPU::DS_NOP_si, Convert_NoOperands, Feature_isCIVI|Feature_isSICI, {  }, },
   14536             :   { 2733 /* ds_nop */, AMDGPU::DS_NOP_vi, Convert_NoOperands, Feature_isCIVI|Feature_isVI, {  }, },
   14537             :   { 2740 /* ds_or_b32 */, AMDGPU::DS_OR_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14538             :   { 2740 /* ds_or_b32 */, AMDGPU::DS_OR_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14539             :   { 2750 /* ds_or_b64 */, AMDGPU::DS_OR_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14540             :   { 2750 /* ds_or_b64 */, AMDGPU::DS_OR_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14541             :   { 2760 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14542             :   { 2760 /* ds_or_rtn_b32 */, AMDGPU::DS_OR_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14543             :   { 2774 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14544             :   { 2774 /* ds_or_rtn_b64 */, AMDGPU::DS_OR_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14545             :   { 2788 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14546             :   { 2788 /* ds_or_src2_b32 */, AMDGPU::DS_OR_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14547             :   { 2803 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14548             :   { 2803 /* ds_or_src2_b64 */, AMDGPU::DS_OR_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14549             :   { 2818 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_si, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14550             :   { 2818 /* ds_ordered_count */, AMDGPU::DS_ORDERED_COUNT_vi, ConvertCustom_cvtDSGds, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_gds }, },
   14551             :   { 2835 /* ds_permute_b32 */, AMDGPU::DS_PERMUTE_B32_vi, ConvertCustom_cvtDS, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset }, },
   14552             :   { 2850 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14553             :   { 2850 /* ds_read2_b32 */, AMDGPU::DS_READ2_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14554             :   { 2863 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14555             :   { 2863 /* ds_read2_b64 */, AMDGPU::DS_READ2_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14556             :   { 2876 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14557             :   { 2876 /* ds_read2st64_b32 */, AMDGPU::DS_READ2ST64_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14558             :   { 2893 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14559             :   { 2893 /* ds_read2st64_b64 */, AMDGPU::DS_READ2ST64_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14560             :   { 2910 /* ds_read_addtid_b32 */, AMDGPU::DS_READ_ADDTID_B32_vi, ConvertCustom_cvtDS, Feature_HasDSAddTid|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14561             :   { 2929 /* ds_read_b128 */, AMDGPU::DS_READ_B128_si, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14562             :   { 2929 /* ds_read_b128 */, AMDGPU::DS_READ_B128_vi, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14563             :   { 2942 /* ds_read_b32 */, AMDGPU::DS_READ_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14564             :   { 2942 /* ds_read_b32 */, AMDGPU::DS_READ_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14565             :   { 2954 /* ds_read_b64 */, AMDGPU::DS_READ_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14566             :   { 2954 /* ds_read_b64 */, AMDGPU::DS_READ_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14567             :   { 2966 /* ds_read_b96 */, AMDGPU::DS_READ_B96_si, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isSICI, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14568             :   { 2966 /* ds_read_b96 */, AMDGPU::DS_READ_B96_vi, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14569             :   { 2978 /* ds_read_i16 */, AMDGPU::DS_READ_I16_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14570             :   { 2978 /* ds_read_i16 */, AMDGPU::DS_READ_I16_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14571             :   { 2990 /* ds_read_i8 */, AMDGPU::DS_READ_I8_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14572             :   { 2990 /* ds_read_i8 */, AMDGPU::DS_READ_I8_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14573             :   { 3001 /* ds_read_i8_d16 */, AMDGPU::DS_READ_I8_D16_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14574             :   { 3016 /* ds_read_i8_d16_hi */, AMDGPU::DS_READ_I8_D16_HI_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14575             :   { 3034 /* ds_read_u16 */, AMDGPU::DS_READ_U16_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14576             :   { 3034 /* ds_read_u16 */, AMDGPU::DS_READ_U16_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14577             :   { 3046 /* ds_read_u16_d16 */, AMDGPU::DS_READ_U16_D16_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14578             :   { 3062 /* ds_read_u16_d16_hi */, AMDGPU::DS_READ_U16_D16_HI_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14579             :   { 3081 /* ds_read_u8 */, AMDGPU::DS_READ_U8_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14580             :   { 3081 /* ds_read_u8 */, AMDGPU::DS_READ_U8_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14581             :   { 3092 /* ds_read_u8_d16 */, AMDGPU::DS_READ_U8_D16_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14582             :   { 3107 /* ds_read_u8_d16_hi */, AMDGPU::DS_READ_U8_D16_HI_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14583             :   { 3125 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14584             :   { 3125 /* ds_rsub_rtn_u32 */, AMDGPU::DS_RSUB_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14585             :   { 3141 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14586             :   { 3141 /* ds_rsub_rtn_u64 */, AMDGPU::DS_RSUB_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14587             :   { 3157 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14588             :   { 3157 /* ds_rsub_src2_u32 */, AMDGPU::DS_RSUB_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14589             :   { 3174 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14590             :   { 3174 /* ds_rsub_src2_u64 */, AMDGPU::DS_RSUB_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14591             :   { 3191 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14592             :   { 3191 /* ds_rsub_u32 */, AMDGPU::DS_RSUB_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14593             :   { 3203 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14594             :   { 3203 /* ds_rsub_u64 */, AMDGPU::DS_RSUB_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14595             :   { 3215 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14596             :   { 3215 /* ds_sub_rtn_u32 */, AMDGPU::DS_SUB_RTN_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14597             :   { 3230 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14598             :   { 3230 /* ds_sub_rtn_u64 */, AMDGPU::DS_SUB_RTN_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14599             :   { 3245 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14600             :   { 3245 /* ds_sub_src2_u32 */, AMDGPU::DS_SUB_SRC2_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14601             :   { 3261 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14602             :   { 3261 /* ds_sub_src2_u64 */, AMDGPU::DS_SUB_SRC2_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14603             :   { 3277 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14604             :   { 3277 /* ds_sub_u32 */, AMDGPU::DS_SUB_U32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14605             :   { 3288 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14606             :   { 3288 /* ds_sub_u64 */, AMDGPU::DS_SUB_U64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14607             :   { 3299 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
   14608             :   { 3299 /* ds_swizzle_b32 */, AMDGPU::DS_SWIZZLE_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Swizzle, MCK_ImmGDS }, },
   14609             :   { 3314 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_si, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14610             :   { 3314 /* ds_wrap_rtn_b32 */, AMDGPU::DS_WRAP_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14611             :   { 3330 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14612             :   { 3330 /* ds_write2_b32 */, AMDGPU::DS_WRITE2_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14613             :   { 3344 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14614             :   { 3344 /* ds_write2_b64 */, AMDGPU::DS_WRITE2_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14615             :   { 3358 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14616             :   { 3358 /* ds_write2st64_b32 */, AMDGPU::DS_WRITE2ST64_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14617             :   { 3376 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14618             :   { 3376 /* ds_write2st64_b64 */, AMDGPU::DS_WRITE2ST64_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14619             :   { 3394 /* ds_write_addtid_b32 */, AMDGPU::DS_WRITE_ADDTID_B32_vi, ConvertCustom_cvtDS, Feature_HasDSAddTid|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14620             :   { 3414 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_si, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
   14621             :   { 3414 /* ds_write_b128 */, AMDGPU::DS_WRITE_B128_vi, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_ImmOffset, MCK_ImmGDS }, },
   14622             :   { 3428 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14623             :   { 3428 /* ds_write_b16 */, AMDGPU::DS_WRITE_B16_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14624             :   { 3441 /* ds_write_b16_d16_hi */, AMDGPU::DS_WRITE_B16_D16_HI_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14625             :   { 3461 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14626             :   { 3461 /* ds_write_b32 */, AMDGPU::DS_WRITE_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14627             :   { 3474 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14628             :   { 3474 /* ds_write_b64 */, AMDGPU::DS_WRITE_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14629             :   { 3487 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14630             :   { 3487 /* ds_write_b8 */, AMDGPU::DS_WRITE_B8_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14631             :   { 3499 /* ds_write_b8_d16_hi */, AMDGPU::DS_WRITE_B8_D16_HI_vi, ConvertCustom_cvtDS, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14632             :   { 3518 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_si, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
   14633             :   { 3518 /* ds_write_b96 */, AMDGPU::DS_WRITE_B96_vi, ConvertCustom_cvtDS, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_ImmOffset, MCK_ImmGDS }, },
   14634             :   { 3531 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14635             :   { 3531 /* ds_write_src2_b32 */, AMDGPU::DS_WRITE_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14636             :   { 3549 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14637             :   { 3549 /* ds_write_src2_b64 */, AMDGPU::DS_WRITE_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14638             :   { 3567 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14639             :   { 3567 /* ds_wrxchg2_rtn_b32 */, AMDGPU::DS_WRXCHG2_RTN_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14640             :   { 3586 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14641             :   { 3586 /* ds_wrxchg2_rtn_b64 */, AMDGPU::DS_WRXCHG2_RTN_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14642             :   { 3605 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14643             :   { 3605 /* ds_wrxchg2st64_rtn_b32 */, AMDGPU::DS_WRXCHG2ST64_RTN_B32_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14644             :   { 3628 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_si, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14645             :   { 3628 /* ds_wrxchg2st64_rtn_b64 */, AMDGPU::DS_WRXCHG2ST64_RTN_B64_vi, ConvertCustom_cvtDSOffset01, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffset0, MCK_ImmOffset1, MCK_ImmGDS }, },
   14646             :   { 3651 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14647             :   { 3651 /* ds_wrxchg_rtn_b32 */, AMDGPU::DS_WRXCHG_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14648             :   { 3669 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14649             :   { 3669 /* ds_wrxchg_rtn_b64 */, AMDGPU::DS_WRXCHG_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14650             :   { 3687 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14651             :   { 3687 /* ds_xor_b32 */, AMDGPU::DS_XOR_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14652             :   { 3698 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14653             :   { 3698 /* ds_xor_b64 */, AMDGPU::DS_XOR_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14654             :   { 3709 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14655             :   { 3709 /* ds_xor_rtn_b32 */, AMDGPU::DS_XOR_RTN_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14656             :   { 3724 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14657             :   { 3724 /* ds_xor_rtn_b64 */, AMDGPU::DS_XOR_RTN_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffset, MCK_ImmGDS }, },
   14658             :   { 3739 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14659             :   { 3739 /* ds_xor_src2_b32 */, AMDGPU::DS_XOR_SRC2_B32_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14660             :   { 3755 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_si, ConvertCustom_cvtDS, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14661             :   { 3755 /* ds_xor_src2_b64 */, AMDGPU::DS_XOR_SRC2_B64_vi, ConvertCustom_cvtDS, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_ImmOffset, MCK_ImmGDS }, },
   14662             :   { 3771 /* exp */, AMDGPU::EXP_si, ConvertCustom_cvtExp, Feature_isGCN|Feature_isSICI, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
   14663             :   { 3771 /* exp */, AMDGPU::EXP_vi, ConvertCustom_cvtExp, Feature_isGCN|Feature_isVI, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_ImmExpCompr, MCK_ImmExpVM }, },
   14664             :   { 3771 /* exp */, AMDGPU::EXP_DONE_si, ConvertCustom_cvtExp, Feature_isGCN|Feature_isSICI, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
   14665             :   { 3771 /* exp */, AMDGPU::EXP_DONE_vi, ConvertCustom_cvtExp, Feature_isGCN|Feature_isVI, { MCK_ImmExpTgt, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_VReg32OrOff, MCK_done, MCK_ImmExpCompr, MCK_ImmExpVM }, },
   14666             :   { 3775 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14667             :   { 3775 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14668             :   { 3775 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14669             :   { 3775 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14670             :   { 3791 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14671             :   { 3791 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14672             :   { 3791 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14673             :   { 3791 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14674             :   { 3810 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14675             :   { 3810 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14676             :   { 3810 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14677             :   { 3810 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14678             :   { 3826 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14679             :   { 3826 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14680             :   { 3826 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14681             :   { 3826 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14682             :   { 3845 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14683             :   { 3845 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14684             :   { 3845 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14685             :   { 3845 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14686             :   { 3865 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14687             :   { 3865 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14688             :   { 3865 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14689             :   { 3865 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14690             :   { 3888 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14691             :   { 3888 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14692             :   { 3888 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14693             :   { 3888 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14694             :   { 3904 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14695             :   { 3904 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14696             :   { 3904 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14697             :   { 3904 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14698             :   { 3923 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14699             :   { 3923 /* flat_atomic_fcmpswap */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14700             :   { 3944 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14701             :   { 3944 /* flat_atomic_fcmpswap_x2 */, AMDGPU::FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14702             :   { 3968 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14703             :   { 3968 /* flat_atomic_fmax */, AMDGPU::FLAT_ATOMIC_FMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14704             :   { 3985 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14705             :   { 3985 /* flat_atomic_fmax_x2 */, AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14706             :   { 4005 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14707             :   { 4005 /* flat_atomic_fmin */, AMDGPU::FLAT_ATOMIC_FMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14708             :   { 4022 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14709             :   { 4022 /* flat_atomic_fmin_x2 */, AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14710             :   { 4042 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14711             :   { 4042 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14712             :   { 4042 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14713             :   { 4042 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14714             :   { 4058 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14715             :   { 4058 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14716             :   { 4058 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14717             :   { 4058 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14718             :   { 4077 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14719             :   { 4077 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14720             :   { 4077 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14721             :   { 4077 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14722             :   { 4092 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14723             :   { 4092 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14724             :   { 4092 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14725             :   { 4092 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14726             :   { 4110 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14727             :   { 4110 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14728             :   { 4110 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14729             :   { 4110 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14730             :   { 4127 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14731             :   { 4127 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14732             :   { 4127 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14733             :   { 4127 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14734             :   { 4147 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14735             :   { 4147 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14736             :   { 4147 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14737             :   { 4147 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14738             :   { 4164 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14739             :   { 4164 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14740             :   { 4164 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14741             :   { 4164 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14742             :   { 4184 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14743             :   { 4184 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14744             :   { 4184 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14745             :   { 4184 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14746             :   { 4200 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14747             :   { 4200 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14748             :   { 4200 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14749             :   { 4200 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14750             :   { 4219 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14751             :   { 4219 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14752             :   { 4219 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14753             :   { 4219 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14754             :   { 4236 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14755             :   { 4236 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14756             :   { 4236 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14757             :   { 4236 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14758             :   { 4256 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14759             :   { 4256 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14760             :   { 4256 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14761             :   { 4256 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14762             :   { 4273 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14763             :   { 4273 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14764             :   { 4273 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14765             :   { 4273 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14766             :   { 4293 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14767             :   { 4293 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14768             :   { 4293 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14769             :   { 4293 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14770             :   { 4310 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14771             :   { 4310 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14772             :   { 4310 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14773             :   { 4310 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14774             :   { 4330 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14775             :   { 4330 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14776             :   { 4330 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14777             :   { 4330 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14778             :   { 4346 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14779             :   { 4346 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmSLC1_3, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmSLC }, },
   14780             :   { 4346 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14781             :   { 4346 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetU121_3__ImmSLC1_5, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_glc, MCK_ImmSLC }, },
   14782             :   { 4365 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14783             :   { 4365 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14784             :   { 4381 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14785             :   { 4381 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14786             :   { 4399 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_96, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14787             :   { 4399 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14788             :   { 4417 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_128, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14789             :   { 4417 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14790             :   { 4435 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14791             :   { 4435 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14792             :   { 4451 /* flat_load_sbyte_d16 */, AMDGPU::FLAT_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14793             :   { 4471 /* flat_load_sbyte_d16_hi */, AMDGPU::FLAT_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14794             :   { 4494 /* flat_load_short_d16 */, AMDGPU::FLAT_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14795             :   { 4514 /* flat_load_short_d16_hi */, AMDGPU::FLAT_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14796             :   { 4537 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14797             :   { 4537 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14798             :   { 4554 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14799             :   { 4554 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14800             :   { 4570 /* flat_load_ubyte_d16 */, AMDGPU::FLAT_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14801             :   { 4590 /* flat_load_ubyte_d16_hi */, AMDGPU::FLAT_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4__imm_95_0, Feature_HasD16LoadStore|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14802             :   { 4613 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14803             :   { 4613 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14804             :   { 4630 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14805             :   { 4630 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14806             :   { 4646 /* flat_store_byte_d16_hi */, AMDGPU::FLAT_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasD16LoadStore|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14807             :   { 4669 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14808             :   { 4669 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14809             :   { 4686 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14810             :   { 4686 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14811             :   { 4705 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_96, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14812             :   { 4705 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14813             :   { 4724 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14814             :   { 4724 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14815             :   { 4743 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_ci, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isCIOnly, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14816             :   { 4743 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasFlatAddressSpace|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14817             :   { 4760 /* flat_store_short_d16_hi */, AMDGPU::FLAT_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetU121_2__ImmGLC1_3__ImmSLC1_4, Feature_HasD16LoadStore|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmOffsetU12, MCK_ImmGLC, MCK_ImmSLC }, },
   14818             :   { 4784 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14819             :   { 4784 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14820             :   { 4784 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14821             :   { 4784 /* global_atomic_add */, AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14822             :   { 4802 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14823             :   { 4802 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14824             :   { 4802 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14825             :   { 4802 /* global_atomic_add_x2 */, AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14826             :   { 4823 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14827             :   { 4823 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14828             :   { 4823 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14829             :   { 4823 /* global_atomic_and */, AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14830             :   { 4841 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14831             :   { 4841 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14832             :   { 4841 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14833             :   { 4841 /* global_atomic_and_x2 */, AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14834             :   { 4862 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14835             :   { 4862 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14836             :   { 4862 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14837             :   { 4862 /* global_atomic_cmpswap */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14838             :   { 4884 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14839             :   { 4884 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14840             :   { 4884 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14841             :   { 4884 /* global_atomic_cmpswap_x2 */, AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14842             :   { 4909 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14843             :   { 4909 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14844             :   { 4909 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14845             :   { 4909 /* global_atomic_dec */, AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14846             :   { 4927 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14847             :   { 4927 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14848             :   { 4927 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14849             :   { 4927 /* global_atomic_dec_x2 */, AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14850             :   { 4948 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14851             :   { 4948 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14852             :   { 4948 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14853             :   { 4948 /* global_atomic_inc */, AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14854             :   { 4966 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14855             :   { 4966 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14856             :   { 4966 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14857             :   { 4966 /* global_atomic_inc_x2 */, AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14858             :   { 4987 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14859             :   { 4987 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14860             :   { 4987 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14861             :   { 4987 /* global_atomic_or */, AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14862             :   { 5004 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14863             :   { 5004 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14864             :   { 5004 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14865             :   { 5004 /* global_atomic_or_x2 */, AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14866             :   { 5024 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14867             :   { 5024 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14868             :   { 5024 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14869             :   { 5024 /* global_atomic_smax */, AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14870             :   { 5043 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14871             :   { 5043 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14872             :   { 5043 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14873             :   { 5043 /* global_atomic_smax_x2 */, AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14874             :   { 5065 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14875             :   { 5065 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14876             :   { 5065 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14877             :   { 5065 /* global_atomic_smin */, AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14878             :   { 5084 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14879             :   { 5084 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14880             :   { 5084 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14881             :   { 5084 /* global_atomic_smin_x2 */, AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14882             :   { 5106 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14883             :   { 5106 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14884             :   { 5106 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14885             :   { 5106 /* global_atomic_sub */, AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14886             :   { 5124 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14887             :   { 5124 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14888             :   { 5124 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14889             :   { 5124 /* global_atomic_sub_x2 */, AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14890             :   { 5145 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14891             :   { 5145 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14892             :   { 5145 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14893             :   { 5145 /* global_atomic_swap */, AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14894             :   { 5164 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14895             :   { 5164 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14896             :   { 5164 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14897             :   { 5164 /* global_atomic_swap_x2 */, AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14898             :   { 5186 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14899             :   { 5186 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14900             :   { 5186 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14901             :   { 5186 /* global_atomic_umax */, AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14902             :   { 5205 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14903             :   { 5205 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14904             :   { 5205 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14905             :   { 5205 /* global_atomic_umax_x2 */, AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14906             :   { 5227 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14907             :   { 5227 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14908             :   { 5227 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14909             :   { 5227 /* global_atomic_umin */, AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14910             :   { 5246 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14911             :   { 5246 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14912             :   { 5246 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14913             :   { 5246 /* global_atomic_umin_x2 */, AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14914             :   { 5268 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14915             :   { 5268 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14916             :   { 5268 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14917             :   { 5268 /* global_atomic_xor */, AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14918             :   { 5286 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14919             :   { 5286 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmSLC1_4, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmSLC }, },
   14920             :   { 5286 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14921             :   { 5286 /* global_atomic_xor_x2 */, AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__ImmOffsetS131_4__ImmSLC1_6, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_glc, MCK_ImmSLC }, },
   14922             :   { 5307 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14923             :   { 5307 /* global_load_dword */, AMDGPU::GLOBAL_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14924             :   { 5325 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14925             :   { 5325 /* global_load_dwordx2 */, AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14926             :   { 5345 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14927             :   { 5345 /* global_load_dwordx3 */, AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14928             :   { 5365 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14929             :   { 5365 /* global_load_dwordx4 */, AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14930             :   { 5385 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14931             :   { 5385 /* global_load_sbyte */, AMDGPU::GLOBAL_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14932             :   { 5403 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14933             :   { 5403 /* global_load_sbyte_d16 */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14934             :   { 5425 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14935             :   { 5425 /* global_load_sbyte_d16_hi */, AMDGPU::GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14936             :   { 5450 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14937             :   { 5450 /* global_load_short_d16 */, AMDGPU::GLOBAL_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14938             :   { 5472 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14939             :   { 5472 /* global_load_short_d16_hi */, AMDGPU::GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14940             :   { 5497 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14941             :   { 5497 /* global_load_sshort */, AMDGPU::GLOBAL_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14942             :   { 5516 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14943             :   { 5516 /* global_load_ubyte */, AMDGPU::GLOBAL_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14944             :   { 5534 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14945             :   { 5534 /* global_load_ubyte_d16 */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14946             :   { 5556 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14947             :   { 5556 /* global_load_ubyte_d16_hi */, AMDGPU::GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5__imm_95_0, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14948             :   { 5581 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14949             :   { 5581 /* global_load_ushort */, AMDGPU::GLOBAL_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14950             :   { 5600 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14951             :   { 5600 /* global_store_byte */, AMDGPU::GLOBAL_STORE_BYTE_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14952             :   { 5618 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14953             :   { 5618 /* global_store_byte_d16_hi */, AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14954             :   { 5643 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14955             :   { 5643 /* global_store_dword */, AMDGPU::GLOBAL_STORE_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14956             :   { 5662 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14957             :   { 5662 /* global_store_dwordx2 */, AMDGPU::GLOBAL_STORE_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14958             :   { 5683 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14959             :   { 5683 /* global_store_dwordx3 */, AMDGPU::GLOBAL_STORE_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14960             :   { 5704 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14961             :   { 5704 /* global_store_dwordx4 */, AMDGPU::GLOBAL_STORE_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14962             :   { 5725 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14963             :   { 5725 /* global_store_short */, AMDGPU::GLOBAL_STORE_SHORT_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14964             :   { 5744 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14965             :   { 5744 /* global_store_short_d16_hi */, AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatGlobalInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   14966             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14967             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14968             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14969             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14970             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14971             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14972             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14973             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14974             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14975             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14976             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14977             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14978             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14979             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14980             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14981             :   { 5770 /* image_atomic_add */, AMDGPU::IMAGE_ATOMIC_ADD_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14982             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14983             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14984             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14985             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14986             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14987             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14988             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14989             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14990             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14991             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14992             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14993             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14994             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14995             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14996             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14997             :   { 5787 /* image_atomic_and */, AMDGPU::IMAGE_ATOMIC_AND_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14998             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   14999             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15000             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15001             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15002             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15003             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15004             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15005             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15006             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15007             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15008             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15009             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15010             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15011             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15012             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15013             :   { 5804 /* image_atomic_cmpswap */, AMDGPU::IMAGE_ATOMIC_CMPSWAP_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15014             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15015             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15016             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15017             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15018             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15019             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15020             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15021             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15022             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15023             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15024             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15025             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15026             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15027             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15028             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15029             :   { 5825 /* image_atomic_dec */, AMDGPU::IMAGE_ATOMIC_DEC_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15030             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15031             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15032             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15033             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15034             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15035             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15036             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15037             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15038             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15039             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15040             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15041             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15042             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15043             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15044             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15045             :   { 5842 /* image_atomic_inc */, AMDGPU::IMAGE_ATOMIC_INC_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15046             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15047             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15048             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15049             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15050             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15051             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15052             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15053             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15054             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15055             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15056             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15057             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15058             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15059             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15060             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15061             :   { 5859 /* image_atomic_or */, AMDGPU::IMAGE_ATOMIC_OR_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15062             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15063             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15064             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15065             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15066             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15067             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15068             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15069             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15070             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15071             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15072             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15073             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15074             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15075             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15076             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15077             :   { 5875 /* image_atomic_smax */, AMDGPU::IMAGE_ATOMIC_SMAX_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15078             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15079             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15080             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15081             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15082             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15083             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15084             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15085             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15086             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15087             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15088             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15089             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15090             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15091             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15092             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15093             :   { 5893 /* image_atomic_smin */, AMDGPU::IMAGE_ATOMIC_SMIN_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15094             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15095             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15096             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15097             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15098             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15099             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15100             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15101             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15102             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15103             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15104             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15105             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15106             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15107             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15108             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15109             :   { 5911 /* image_atomic_sub */, AMDGPU::IMAGE_ATOMIC_SUB_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15110             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15111             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15112             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15113             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15114             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15115             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15116             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15117             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15118             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15119             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15120             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15121             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15122             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15123             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15124             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15125             :   { 5928 /* image_atomic_swap */, AMDGPU::IMAGE_ATOMIC_SWAP_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15126             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15127             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15128             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15129             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15130             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15131             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15132             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15133             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15134             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15135             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15136             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15137             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15138             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15139             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15140             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15141             :   { 5946 /* image_atomic_umax */, AMDGPU::IMAGE_ATOMIC_UMAX_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15142             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15143             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15144             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15145             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15146             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15147             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15148             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15149             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15150             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15151             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15152             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15153             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15154             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15155             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15156             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15157             :   { 5964 /* image_atomic_umin */, AMDGPU::IMAGE_ATOMIC_UMIN_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15158             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15159             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15160             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15161             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15162             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15163             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15164             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15165             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V2_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15166             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15167             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V4_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15168             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15169             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V3_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15170             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15171             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V2_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15172             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_si, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15173             :   { 5982 /* image_atomic_xor */, AMDGPU::IMAGE_ATOMIC_XOR_V1_V1_vi, ConvertCustom_cvtMIMGAtomic, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15174             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15175             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15176             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15177             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15178             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15179             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15180             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15181             :   { 5999 /* image_gather4 */, AMDGPU::IMAGE_GATHER4_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15182             :   { 6013 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15183             :   { 6013 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15184             :   { 6013 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15185             :   { 6013 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15186             :   { 6013 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15187             :   { 6013 /* image_gather4_b */, AMDGPU::IMAGE_GATHER4_B_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15188             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15189             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15190             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15191             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15192             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15193             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15194             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15195             :   { 6029 /* image_gather4_b_cl */, AMDGPU::IMAGE_GATHER4_B_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15196             :   { 6048 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15197             :   { 6048 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15198             :   { 6048 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15199             :   { 6048 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15200             :   { 6048 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15201             :   { 6048 /* image_gather4_b_cl_o */, AMDGPU::IMAGE_GATHER4_B_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15202             :   { 6069 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15203             :   { 6069 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15204             :   { 6069 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15205             :   { 6069 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15206             :   { 6069 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15207             :   { 6069 /* image_gather4_b_o */, AMDGPU::IMAGE_GATHER4_B_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15208             :   { 6087 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15209             :   { 6087 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15210             :   { 6087 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15211             :   { 6087 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15212             :   { 6087 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15213             :   { 6087 /* image_gather4_c */, AMDGPU::IMAGE_GATHER4_C_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15214             :   { 6103 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15215             :   { 6103 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15216             :   { 6103 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15217             :   { 6103 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15218             :   { 6103 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15219             :   { 6103 /* image_gather4_c_b */, AMDGPU::IMAGE_GATHER4_C_B_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15220             :   { 6121 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15221             :   { 6121 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15222             :   { 6121 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15223             :   { 6121 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15224             :   { 6121 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15225             :   { 6121 /* image_gather4_c_b_cl */, AMDGPU::IMAGE_GATHER4_C_B_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15226             :   { 6142 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15227             :   { 6142 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15228             :   { 6142 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15229             :   { 6142 /* image_gather4_c_b_cl_o */, AMDGPU::IMAGE_GATHER4_C_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15230             :   { 6165 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15231             :   { 6165 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15232             :   { 6165 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15233             :   { 6165 /* image_gather4_c_b_o */, AMDGPU::IMAGE_GATHER4_C_B_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15234             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15235             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15236             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15237             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15238             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15239             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15240             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15241             :   { 6185 /* image_gather4_c_cl */, AMDGPU::IMAGE_GATHER4_C_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15242             :   { 6204 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15243             :   { 6204 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15244             :   { 6204 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15245             :   { 6204 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15246             :   { 6204 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15247             :   { 6204 /* image_gather4_c_cl_o */, AMDGPU::IMAGE_GATHER4_C_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15248             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15249             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15250             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15251             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15252             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15253             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15254             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15255             :   { 6225 /* image_gather4_c_l */, AMDGPU::IMAGE_GATHER4_C_L_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15256             :   { 6243 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15257             :   { 6243 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15258             :   { 6243 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15259             :   { 6243 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15260             :   { 6243 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15261             :   { 6243 /* image_gather4_c_l_o */, AMDGPU::IMAGE_GATHER4_C_L_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15262             :   { 6263 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15263             :   { 6263 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15264             :   { 6263 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15265             :   { 6263 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15266             :   { 6263 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15267             :   { 6263 /* image_gather4_c_lz */, AMDGPU::IMAGE_GATHER4_C_LZ_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15268             :   { 6282 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15269             :   { 6282 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15270             :   { 6282 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15271             :   { 6282 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15272             :   { 6282 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15273             :   { 6282 /* image_gather4_c_lz_o */, AMDGPU::IMAGE_GATHER4_C_LZ_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15274             :   { 6303 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15275             :   { 6303 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15276             :   { 6303 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15277             :   { 6303 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15278             :   { 6303 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15279             :   { 6303 /* image_gather4_c_o */, AMDGPU::IMAGE_GATHER4_C_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15280             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15281             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15282             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15283             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15284             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15285             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15286             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15287             :   { 6321 /* image_gather4_cl */, AMDGPU::IMAGE_GATHER4_CL_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15288             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15289             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15290             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15291             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15292             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15293             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15294             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15295             :   { 6338 /* image_gather4_cl_o */, AMDGPU::IMAGE_GATHER4_CL_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15296             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15297             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15298             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15299             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15300             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15301             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15302             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15303             :   { 6357 /* image_gather4_l */, AMDGPU::IMAGE_GATHER4_L_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15304             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15305             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15306             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15307             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15308             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15309             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15310             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15311             :   { 6373 /* image_gather4_l_o */, AMDGPU::IMAGE_GATHER4_L_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15312             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15313             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15314             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15315             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15316             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15317             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15318             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15319             :   { 6391 /* image_gather4_lz */, AMDGPU::IMAGE_GATHER4_LZ_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15320             :   { 6408 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15321             :   { 6408 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15322             :   { 6408 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15323             :   { 6408 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15324             :   { 6408 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15325             :   { 6408 /* image_gather4_lz_o */, AMDGPU::IMAGE_GATHER4_LZ_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15326             :   { 6427 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15327             :   { 6427 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15328             :   { 6427 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15329             :   { 6427 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15330             :   { 6427 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15331             :   { 6427 /* image_gather4_o */, AMDGPU::IMAGE_GATHER4_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15332             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15333             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15334             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15335             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15336             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15337             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15338             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15339             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15340             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15341             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15342             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15343             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15344             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15345             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15346             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15347             :   { 6443 /* image_get_lod */, AMDGPU::IMAGE_GET_LOD_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15348             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15349             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15350             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15351             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15352             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15353             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15354             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15355             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15356             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15357             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15358             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15359             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15360             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15361             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15362             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15363             :   { 6457 /* image_get_resinfo */, AMDGPU::IMAGE_GET_RESINFO_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15364             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15365             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15366             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15367             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15368             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15369             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15370             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15371             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15372             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15373             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15374             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15375             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15376             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15377             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15378             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15379             :   { 6475 /* image_load */, AMDGPU::IMAGE_LOAD_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15380             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15381             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15382             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15383             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15384             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15385             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15386             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15387             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15388             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15389             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15390             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15391             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15392             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15393             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15394             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15395             :   { 6486 /* image_load_mip */, AMDGPU::IMAGE_LOAD_MIP_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15396             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15397             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15398             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15399             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15400             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15401             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15402             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15403             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15404             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15405             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15406             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15407             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15408             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15409             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15410             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15411             :   { 6501 /* image_load_mip_pck */, AMDGPU::IMAGE_LOAD_MIP_PCK_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15412             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15413             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15414             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15415             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15416             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15417             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15418             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15419             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15420             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15421             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15422             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15423             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15424             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15425             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15426             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15427             :   { 6520 /* image_load_mip_pck_sgn */, AMDGPU::IMAGE_LOAD_MIP_PCK_SGN_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15428             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15429             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15430             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15431             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15432             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15433             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15434             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15435             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15436             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15437             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15438             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15439             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15440             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15441             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15442             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15443             :   { 6543 /* image_load_pck */, AMDGPU::IMAGE_LOAD_PCK_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15444             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15445             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15446             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15447             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15448             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15449             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15450             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15451             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15452             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15453             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15454             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15455             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15456             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15457             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15458             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15459             :   { 6558 /* image_load_pck_sgn */, AMDGPU::IMAGE_LOAD_PCK_SGN_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   15460             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15461             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15462             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15463             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15464             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15465             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15466             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15467             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15468             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15469             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15470             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15471             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15472             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15473             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15474             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15475             :   { 6577 /* image_sample */, AMDGPU::IMAGE_SAMPLE_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15476             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15477             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15478             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15479             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15480             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15481             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15482             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15483             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15484             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15485             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15486             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15487             :   { 6590 /* image_sample_b */, AMDGPU::IMAGE_SAMPLE_B_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15488             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15489             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15490             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15491             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15492             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15493             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15494             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15495             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15496             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15497             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15498             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15499             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15500             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15501             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15502             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15503             :   { 6605 /* image_sample_b_cl */, AMDGPU::IMAGE_SAMPLE_B_CL_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15504             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15505             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15506             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15507             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15508             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15509             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15510             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15511             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15512             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15513             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15514             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15515             :   { 6623 /* image_sample_b_cl_o */, AMDGPU::IMAGE_SAMPLE_B_CL_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15516             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15517             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15518             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15519             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15520             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15521             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15522             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15523             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15524             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15525             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15526             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15527             :   { 6643 /* image_sample_b_o */, AMDGPU::IMAGE_SAMPLE_B_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15528             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15529             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15530             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15531             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15532             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15533             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15534             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15535             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15536             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15537             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15538             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15539             :   { 6660 /* image_sample_c */, AMDGPU::IMAGE_SAMPLE_C_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15540             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15541             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15542             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15543             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15544             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15545             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15546             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15547             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15548             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15549             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15550             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15551             :   { 6675 /* image_sample_c_b */, AMDGPU::IMAGE_SAMPLE_C_B_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15552             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15553             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15554             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15555             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15556             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15557             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15558             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15559             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15560             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15561             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15562             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15563             :   { 6692 /* image_sample_c_b_cl */, AMDGPU::IMAGE_SAMPLE_C_B_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15564             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15565             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15566             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15567             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15568             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15569             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15570             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15571             :   { 6712 /* image_sample_c_b_cl_o */, AMDGPU::IMAGE_SAMPLE_C_B_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15572             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15573             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15574             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15575             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15576             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15577             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15578             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15579             :   { 6734 /* image_sample_c_b_o */, AMDGPU::IMAGE_SAMPLE_C_B_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15580             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15581             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15582             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15583             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15584             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15585             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15586             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15587             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15588             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15589             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15590             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15591             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15592             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15593             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15594             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15595             :   { 6753 /* image_sample_c_cd */, AMDGPU::IMAGE_SAMPLE_C_CD_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15596             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15597             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15598             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15599             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15600             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15601             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15602             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15603             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15604             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15605             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15606             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15607             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15608             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15609             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15610             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15611             :   { 6771 /* image_sample_c_cd_cl */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15612             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15613             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15614             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15615             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15616             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15617             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15618             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15619             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15620             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15621             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15622             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15623             :   { 6792 /* image_sample_c_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CD_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15624             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15625             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15626             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15627             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15628             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15629             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15630             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15631             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15632             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15633             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15634             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15635             :   { 6815 /* image_sample_c_cd_o */, AMDGPU::IMAGE_SAMPLE_C_CD_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15636             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15637             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15638             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15639             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15640             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15641             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15642             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15643             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15644             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15645             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15646             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15647             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15648             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15649             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15650             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15651             :   { 6835 /* image_sample_c_cl */, AMDGPU::IMAGE_SAMPLE_C_CL_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15652             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15653             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15654             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15655             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15656             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15657             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15658             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15659             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15660             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15661             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15662             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15663             :   { 6853 /* image_sample_c_cl_o */, AMDGPU::IMAGE_SAMPLE_C_CL_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15664             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15665             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15666             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15667             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15668             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15669             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15670             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15671             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15672             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15673             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15674             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15675             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15676             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15677             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15678             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15679             :   { 6873 /* image_sample_c_d */, AMDGPU::IMAGE_SAMPLE_C_D_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15680             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15681             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15682             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15683             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15684             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15685             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15686             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15687             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15688             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15689             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15690             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15691             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15692             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15693             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15694             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15695             :   { 6890 /* image_sample_c_d_cl */, AMDGPU::IMAGE_SAMPLE_C_D_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15696             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15697             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15698             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15699             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15700             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15701             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15702             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15703             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15704             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15705             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15706             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15707             :   { 6910 /* image_sample_c_d_cl_o */, AMDGPU::IMAGE_SAMPLE_C_D_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15708             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15709             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15710             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15711             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15712             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15713             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15714             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15715             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15716             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15717             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15718             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15719             :   { 6932 /* image_sample_c_d_o */, AMDGPU::IMAGE_SAMPLE_C_D_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15720             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15721             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15722             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15723             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15724             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15725             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15726             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15727             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15728             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15729             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15730             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15731             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15732             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15733             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15734             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15735             :   { 6951 /* image_sample_c_l */, AMDGPU::IMAGE_SAMPLE_C_L_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15736             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15737             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15738             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15739             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15740             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15741             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15742             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15743             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15744             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15745             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15746             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15747             :   { 6968 /* image_sample_c_l_o */, AMDGPU::IMAGE_SAMPLE_C_L_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15748             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15749             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15750             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15751             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15752             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15753             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15754             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15755             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15756             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15757             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15758             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15759             :   { 6987 /* image_sample_c_lz */, AMDGPU::IMAGE_SAMPLE_C_LZ_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15760             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15761             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15762             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15763             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15764             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15765             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15766             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15767             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15768             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15769             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15770             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15771             :   { 7005 /* image_sample_c_lz_o */, AMDGPU::IMAGE_SAMPLE_C_LZ_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15772             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15773             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15774             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15775             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15776             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15777             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15778             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15779             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15780             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15781             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15782             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15783             :   { 7025 /* image_sample_c_o */, AMDGPU::IMAGE_SAMPLE_C_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15784             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15785             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15786             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15787             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15788             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15789             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15790             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15791             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15792             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15793             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15794             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15795             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15796             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15797             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15798             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15799             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15800             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15801             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15802             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15803             :   { 7042 /* image_sample_cd */, AMDGPU::IMAGE_SAMPLE_CD_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15804             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15805             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15806             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15807             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15808             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15809             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15810             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15811             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15812             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15813             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15814             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15815             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15816             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15817             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15818             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15819             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15820             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15821             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15822             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15823             :   { 7058 /* image_sample_cd_cl */, AMDGPU::IMAGE_SAMPLE_CD_CL_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15824             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15825             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15826             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15827             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15828             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15829             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15830             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15831             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15832             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15833             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15834             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15835             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15836             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15837             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15838             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15839             :   { 7077 /* image_sample_cd_cl_o */, AMDGPU::IMAGE_SAMPLE_CD_CL_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15840             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15841             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15842             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15843             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15844             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15845             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15846             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15847             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15848             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15849             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15850             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15851             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15852             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15853             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15854             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15855             :   { 7098 /* image_sample_cd_o */, AMDGPU::IMAGE_SAMPLE_CD_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15856             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15857             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15858             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15859             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15860             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15861             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15862             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15863             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15864             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15865             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15866             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15867             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15868             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15869             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15870             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15871             :   { 7116 /* image_sample_cl */, AMDGPU::IMAGE_SAMPLE_CL_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15872             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15873             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15874             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15875             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15876             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15877             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15878             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15879             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15880             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15881             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15882             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15883             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15884             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15885             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15886             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15887             :   { 7132 /* image_sample_cl_o */, AMDGPU::IMAGE_SAMPLE_CL_O_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15888             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15889             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15890             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15891             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15892             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15893             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15894             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15895             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15896             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15897             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15898             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15899             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15900             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15901             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15902             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15903             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15904             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15905             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15906             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15907             :   { 7150 /* image_sample_d */, AMDGPU::IMAGE_SAMPLE_D_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15908             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15909             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15910             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15911             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15912             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15913             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15914             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15915             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15916             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15917             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15918             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15919             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15920             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15921             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15922             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15923             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15924             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15925             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15926             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15927             :   { 7165 /* image_sample_d_cl */, AMDGPU::IMAGE_SAMPLE_D_CL_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15928             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15929             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15930             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15931             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15932             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15933             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15934             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15935             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15936             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15937             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15938             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15939             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15940             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15941             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15942             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15943             :   { 7183 /* image_sample_d_cl_o */, AMDGPU::IMAGE_SAMPLE_D_CL_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15944             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15945             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15946             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15947             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15948             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15949             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15950             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15951             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15952             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15953             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15954             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15955             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15956             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V16, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_512, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15957             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15958             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15959             :   { 7203 /* image_sample_d_o */, AMDGPU::IMAGE_SAMPLE_D_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15960             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15961             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15962             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15963             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15964             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15965             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15966             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15967             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15968             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15969             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15970             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15971             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15972             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15973             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15974             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15975             :   { 7220 /* image_sample_l */, AMDGPU::IMAGE_SAMPLE_L_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15976             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15977             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15978             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15979             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15980             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15981             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15982             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15983             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15984             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15985             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15986             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15987             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15988             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V8, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_256, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15989             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15990             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15991             :   { 7235 /* image_sample_l_o */, AMDGPU::IMAGE_SAMPLE_L_O_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15992             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15993             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15994             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15995             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15996             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15997             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15998             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   15999             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16000             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16001             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16002             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16003             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16004             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16005             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16006             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16007             :   { 7252 /* image_sample_lz */, AMDGPU::IMAGE_SAMPLE_LZ_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16008             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16009             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16010             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16011             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16012             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16013             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16014             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16015             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16016             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16017             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16018             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16019             :   { 7268 /* image_sample_lz_o */, AMDGPU::IMAGE_SAMPLE_LZ_O_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16020             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16021             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16022             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16023             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16024             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16025             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16026             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16027             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16028             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16029             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16030             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16031             :   { 7286 /* image_sample_o */, AMDGPU::IMAGE_SAMPLE_O_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_SReg_128, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16032             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16033             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16034             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16035             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16036             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16037             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16038             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16039             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16040             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16041             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16042             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16043             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16044             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16045             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16046             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16047             :   { 7301 /* image_store */, AMDGPU::IMAGE_STORE_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16048             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16049             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16050             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16051             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16052             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16053             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16054             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16055             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16056             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16057             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16058             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16059             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16060             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16061             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16062             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16063             :   { 7313 /* image_store_mip */, AMDGPU::IMAGE_STORE_MIP_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA, MCK_ImmD16 }, },
   16064             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16065             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16066             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16067             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16068             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16069             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16070             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16071             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16072             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16073             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16074             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16075             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16076             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16077             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16078             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16079             :   { 7329 /* image_store_mip_pck */, AMDGPU::IMAGE_STORE_MIP_PCK_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16080             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16081             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16082             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16083             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V4_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16084             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16085             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16086             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16087             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V3_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16088             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16089             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16090             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16091             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V2_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16092             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V4, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_128, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16093             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V3, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_96, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16094             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V2, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16095             :   { 7349 /* image_store_pck */, AMDGPU::IMAGE_STORE_PCK_V1_V1, ConvertCustom_cvtMIMG, Feature_isGCN, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_256, MCK_ImmDMask, MCK_ImmUNorm, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmR128A16, MCK_ImmTFE, MCK_ImmLWE, MCK_ImmDA }, },
   16096             :   { 7365 /* s_abs_i32 */, AMDGPU::S_ABS_I32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16097             :   { 7365 /* s_abs_i32 */, AMDGPU::S_ABS_I32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16098             :   { 7375 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16099             :   { 7375 /* s_absdiff_i32 */, AMDGPU::S_ABSDIFF_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16100             :   { 7389 /* s_add_i32 */, AMDGPU::S_ADD_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16101             :   { 7389 /* s_add_i32 */, AMDGPU::S_ADD_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16102             :   { 7399 /* s_add_u32 */, AMDGPU::S_ADD_U32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16103             :   { 7399 /* s_add_u32 */, AMDGPU::S_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16104             :   { 7409 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16105             :   { 7409 /* s_addc_u32 */, AMDGPU::S_ADDC_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16106             :   { 7420 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_si, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16107             :   { 7420 /* s_addk_i32 */, AMDGPU::S_ADDK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16108             :   { 7431 /* s_and_b32 */, AMDGPU::S_AND_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16109             :   { 7431 /* s_and_b32 */, AMDGPU::S_AND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16110             :   { 7441 /* s_and_b64 */, AMDGPU::S_AND_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16111             :   { 7441 /* s_and_b64 */, AMDGPU::S_AND_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16112             :   { 7451 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16113             :   { 7451 /* s_and_saveexec_b64 */, AMDGPU::S_AND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16114             :   { 7470 /* s_andn1_saveexec_b64 */, AMDGPU::S_ANDN1_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16115             :   { 7491 /* s_andn1_wrexec_b64 */, AMDGPU::S_ANDN1_WREXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16116             :   { 7510 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16117             :   { 7510 /* s_andn2_b32 */, AMDGPU::S_ANDN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16118             :   { 7522 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16119             :   { 7522 /* s_andn2_b64 */, AMDGPU::S_ANDN2_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16120             :   { 7534 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16121             :   { 7534 /* s_andn2_saveexec_b64 */, AMDGPU::S_ANDN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16122             :   { 7555 /* s_andn2_wrexec_b64 */, AMDGPU::S_ANDN2_WREXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16123             :   { 7574 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16124             :   { 7574 /* s_ashr_i32 */, AMDGPU::S_ASHR_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16125             :   { 7585 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_si, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16126             :   { 7585 /* s_ashr_i64 */, AMDGPU::S_ASHR_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16127             :   { 7596 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_Imm, MCK_SReg_64, MCK_SReg_32 }, },
   16128             :   { 7596 /* s_atc_probe */, AMDGPU::S_ATC_PROBE_IMM_vi, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, Feature_isVI|Feature_isVI, { MCK_Imm, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16129             :   { 7608 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_SGPR_vi, Convert__Imm1_0__Reg1_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_Imm, MCK_SReg_128, MCK_SReg_32 }, },
   16130             :   { 7608 /* s_atc_probe_buffer */, AMDGPU::S_ATC_PROBE_BUFFER_IMM_vi, Convert__Imm1_0__Reg1_1__ImmSMRDOffset201_2, Feature_isVI|Feature_isVI, { MCK_Imm, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16131             :   { 7627 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16132             :   { 7627 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16133             :   { 7627 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16134             :   { 7627 /* s_atomic_add */, AMDGPU::S_ATOMIC_ADD_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16135             :   { 7640 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16136             :   { 7640 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16137             :   { 7640 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16138             :   { 7640 /* s_atomic_add_x2 */, AMDGPU::S_ATOMIC_ADD_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16139             :   { 7656 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16140             :   { 7656 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16141             :   { 7656 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16142             :   { 7656 /* s_atomic_and */, AMDGPU::S_ATOMIC_AND_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16143             :   { 7669 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16144             :   { 7669 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16145             :   { 7669 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16146             :   { 7669 /* s_atomic_and_x2 */, AMDGPU::S_ATOMIC_AND_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16147             :   { 7685 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16148             :   { 7685 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16149             :   { 7685 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16150             :   { 7685 /* s_atomic_cmpswap */, AMDGPU::S_ATOMIC_CMPSWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16151             :   { 7702 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32 }, },
   16152             :   { 7702 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16153             :   { 7702 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16154             :   { 7702 /* s_atomic_cmpswap_x2 */, AMDGPU::S_ATOMIC_CMPSWAP_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16155             :   { 7722 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16156             :   { 7722 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16157             :   { 7722 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16158             :   { 7722 /* s_atomic_dec */, AMDGPU::S_ATOMIC_DEC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16159             :   { 7735 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16160             :   { 7735 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16161             :   { 7735 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16162             :   { 7735 /* s_atomic_dec_x2 */, AMDGPU::S_ATOMIC_DEC_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16163             :   { 7751 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16164             :   { 7751 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16165             :   { 7751 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16166             :   { 7751 /* s_atomic_inc */, AMDGPU::S_ATOMIC_INC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16167             :   { 7764 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16168             :   { 7764 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16169             :   { 7764 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16170             :   { 7764 /* s_atomic_inc_x2 */, AMDGPU::S_ATOMIC_INC_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16171             :   { 7780 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16172             :   { 7780 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16173             :   { 7780 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16174             :   { 7780 /* s_atomic_or */, AMDGPU::S_ATOMIC_OR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16175             :   { 7792 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16176             :   { 7792 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16177             :   { 7792 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16178             :   { 7792 /* s_atomic_or_x2 */, AMDGPU::S_ATOMIC_OR_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16179             :   { 7807 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16180             :   { 7807 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16181             :   { 7807 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16182             :   { 7807 /* s_atomic_smax */, AMDGPU::S_ATOMIC_SMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16183             :   { 7821 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16184             :   { 7821 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16185             :   { 7821 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16186             :   { 7821 /* s_atomic_smax_x2 */, AMDGPU::S_ATOMIC_SMAX_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16187             :   { 7838 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16188             :   { 7838 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16189             :   { 7838 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16190             :   { 7838 /* s_atomic_smin */, AMDGPU::S_ATOMIC_SMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16191             :   { 7852 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16192             :   { 7852 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16193             :   { 7852 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16194             :   { 7852 /* s_atomic_smin_x2 */, AMDGPU::S_ATOMIC_SMIN_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16195             :   { 7869 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16196             :   { 7869 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16197             :   { 7869 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16198             :   { 7869 /* s_atomic_sub */, AMDGPU::S_ATOMIC_SUB_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16199             :   { 7882 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16200             :   { 7882 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16201             :   { 7882 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16202             :   { 7882 /* s_atomic_sub_x2 */, AMDGPU::S_ATOMIC_SUB_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16203             :   { 7898 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16204             :   { 7898 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16205             :   { 7898 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16206             :   { 7898 /* s_atomic_swap */, AMDGPU::S_ATOMIC_SWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16207             :   { 7912 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16208             :   { 7912 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16209             :   { 7912 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16210             :   { 7912 /* s_atomic_swap_x2 */, AMDGPU::S_ATOMIC_SWAP_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16211             :   { 7929 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16212             :   { 7929 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16213             :   { 7929 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16214             :   { 7929 /* s_atomic_umax */, AMDGPU::S_ATOMIC_UMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16215             :   { 7943 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16216             :   { 7943 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16217             :   { 7943 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16218             :   { 7943 /* s_atomic_umax_x2 */, AMDGPU::S_ATOMIC_UMAX_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16219             :   { 7960 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16220             :   { 7960 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16221             :   { 7960 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16222             :   { 7960 /* s_atomic_umin */, AMDGPU::S_ATOMIC_UMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16223             :   { 7974 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16224             :   { 7974 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16225             :   { 7974 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16226             :   { 7974 /* s_atomic_umin_x2 */, AMDGPU::S_ATOMIC_UMIN_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16227             :   { 7991 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16228             :   { 7991 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16229             :   { 7991 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16230             :   { 7991 /* s_atomic_xor */, AMDGPU::S_ATOMIC_XOR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16231             :   { 8004 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32 }, },
   16232             :   { 8004 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16233             :   { 8004 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_glc }, },
   16234             :   { 8004 /* s_atomic_xor_x2 */, AMDGPU::S_ATOMIC_XOR_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_glc }, },
   16235             :   { 8020 /* s_barrier */, AMDGPU::S_BARRIER, Convert_NoOperands, Feature_isGCN, {  }, },
   16236             :   { 8030 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16237             :   { 8030 /* s_bcnt0_i32_b32 */, AMDGPU::S_BCNT0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16238             :   { 8046 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16239             :   { 8046 /* s_bcnt0_i32_b64 */, AMDGPU::S_BCNT0_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16240             :   { 8062 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16241             :   { 8062 /* s_bcnt1_i32_b32 */, AMDGPU::S_BCNT1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16242             :   { 8078 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16243             :   { 8078 /* s_bcnt1_i32_b64 */, AMDGPU::S_BCNT1_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16244             :   { 8094 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16245             :   { 8094 /* s_bfe_i32 */, AMDGPU::S_BFE_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16246             :   { 8104 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_si, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16247             :   { 8104 /* s_bfe_i64 */, AMDGPU::S_BFE_I64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16248             :   { 8114 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16249             :   { 8114 /* s_bfe_u32 */, AMDGPU::S_BFE_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16250             :   { 8124 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_si, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16251             :   { 8124 /* s_bfe_u64 */, AMDGPU::S_BFE_U64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16252             :   { 8134 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16253             :   { 8134 /* s_bfm_b32 */, AMDGPU::S_BFM_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16254             :   { 8144 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
   16255             :   { 8144 /* s_bfm_b64 */, AMDGPU::S_BFM_B64_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB32, MCK_SSrcB32 }, },
   16256             :   { 8154 /* s_bitcmp0_b32 */, AMDGPU::S_BITCMP0_B32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16257             :   { 8168 /* s_bitcmp0_b64 */, AMDGPU::S_BITCMP0_B64, Convert__SSrcB641_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB64, MCK_SSrcB32 }, },
   16258             :   { 8182 /* s_bitcmp1_b32 */, AMDGPU::S_BITCMP1_B32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16259             :   { 8196 /* s_bitcmp1_b64 */, AMDGPU::S_BITCMP1_B64, Convert__SSrcB641_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB64, MCK_SSrcB32 }, },
   16260             :   { 8210 /* s_bitreplicate_b64_b32 */, AMDGPU::S_BITREPLICATE_B64_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_SSrcB32 }, },
   16261             :   { 8233 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16262             :   { 8233 /* s_bitset0_b32 */, AMDGPU::S_BITSET0_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16263             :   { 8247 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB32 }, },
   16264             :   { 8247 /* s_bitset0_b64 */, AMDGPU::S_BITSET0_B64_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB32 }, },
   16265             :   { 8261 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16266             :   { 8261 /* s_bitset1_b32 */, AMDGPU::S_BITSET1_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16267             :   { 8275 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB32 }, },
   16268             :   { 8275 /* s_bitset1_b64 */, AMDGPU::S_BITSET1_B64_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB32 }, },
   16269             :   { 8289 /* s_branch */, AMDGPU::S_BRANCH, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16270             :   { 8298 /* s_brev_b32 */, AMDGPU::S_BREV_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16271             :   { 8298 /* s_brev_b32 */, AMDGPU::S_BREV_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16272             :   { 8309 /* s_brev_b64 */, AMDGPU::S_BREV_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16273             :   { 8309 /* s_brev_b64 */, AMDGPU::S_BREV_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16274             :   { 8320 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16275             :   { 8320 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16276             :   { 8320 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16277             :   { 8320 /* s_buffer_atomic_add */, AMDGPU::S_BUFFER_ATOMIC_ADD_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16278             :   { 8340 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16279             :   { 8340 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16280             :   { 8340 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16281             :   { 8340 /* s_buffer_atomic_add_x2 */, AMDGPU::S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16282             :   { 8363 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16283             :   { 8363 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16284             :   { 8363 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16285             :   { 8363 /* s_buffer_atomic_and */, AMDGPU::S_BUFFER_ATOMIC_AND_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16286             :   { 8383 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16287             :   { 8383 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16288             :   { 8383 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16289             :   { 8383 /* s_buffer_atomic_and_x2 */, AMDGPU::S_BUFFER_ATOMIC_AND_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16290             :   { 8406 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16291             :   { 8406 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16292             :   { 8406 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16293             :   { 8406 /* s_buffer_atomic_cmpswap */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16294             :   { 8430 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32 }, },
   16295             :   { 8430 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16296             :   { 8430 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16297             :   { 8430 /* s_buffer_atomic_cmpswap_x2 */, AMDGPU::S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16298             :   { 8457 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16299             :   { 8457 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16300             :   { 8457 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16301             :   { 8457 /* s_buffer_atomic_dec */, AMDGPU::S_BUFFER_ATOMIC_DEC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16302             :   { 8477 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16303             :   { 8477 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16304             :   { 8477 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16305             :   { 8477 /* s_buffer_atomic_dec_x2 */, AMDGPU::S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16306             :   { 8500 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16307             :   { 8500 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16308             :   { 8500 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16309             :   { 8500 /* s_buffer_atomic_inc */, AMDGPU::S_BUFFER_ATOMIC_INC_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16310             :   { 8520 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16311             :   { 8520 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16312             :   { 8520 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16313             :   { 8520 /* s_buffer_atomic_inc_x2 */, AMDGPU::S_BUFFER_ATOMIC_INC_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16314             :   { 8543 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16315             :   { 8543 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16316             :   { 8543 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16317             :   { 8543 /* s_buffer_atomic_or */, AMDGPU::S_BUFFER_ATOMIC_OR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16318             :   { 8562 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16319             :   { 8562 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16320             :   { 8562 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16321             :   { 8562 /* s_buffer_atomic_or_x2 */, AMDGPU::S_BUFFER_ATOMIC_OR_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16322             :   { 8584 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16323             :   { 8584 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16324             :   { 8584 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16325             :   { 8584 /* s_buffer_atomic_smax */, AMDGPU::S_BUFFER_ATOMIC_SMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16326             :   { 8605 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16327             :   { 8605 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16328             :   { 8605 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16329             :   { 8605 /* s_buffer_atomic_smax_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16330             :   { 8629 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16331             :   { 8629 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16332             :   { 8629 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16333             :   { 8629 /* s_buffer_atomic_smin */, AMDGPU::S_BUFFER_ATOMIC_SMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16334             :   { 8650 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16335             :   { 8650 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16336             :   { 8650 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16337             :   { 8650 /* s_buffer_atomic_smin_x2 */, AMDGPU::S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16338             :   { 8674 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16339             :   { 8674 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16340             :   { 8674 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16341             :   { 8674 /* s_buffer_atomic_sub */, AMDGPU::S_BUFFER_ATOMIC_SUB_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16342             :   { 8694 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16343             :   { 8694 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16344             :   { 8694 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16345             :   { 8694 /* s_buffer_atomic_sub_x2 */, AMDGPU::S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16346             :   { 8717 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16347             :   { 8717 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16348             :   { 8717 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16349             :   { 8717 /* s_buffer_atomic_swap */, AMDGPU::S_BUFFER_ATOMIC_SWAP_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16350             :   { 8738 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16351             :   { 8738 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16352             :   { 8738 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16353             :   { 8738 /* s_buffer_atomic_swap_x2 */, AMDGPU::S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16354             :   { 8762 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16355             :   { 8762 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16356             :   { 8762 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16357             :   { 8762 /* s_buffer_atomic_umax */, AMDGPU::S_BUFFER_ATOMIC_UMAX_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16358             :   { 8783 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16359             :   { 8783 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16360             :   { 8783 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16361             :   { 8783 /* s_buffer_atomic_umax_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16362             :   { 8807 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16363             :   { 8807 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16364             :   { 8807 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16365             :   { 8807 /* s_buffer_atomic_umin */, AMDGPU::S_BUFFER_ATOMIC_UMIN_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16366             :   { 8828 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16367             :   { 8828 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16368             :   { 8828 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16369             :   { 8828 /* s_buffer_atomic_umin_x2 */, AMDGPU::S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16370             :   { 8852 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16371             :   { 8852 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16372             :   { 8852 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16373             :   { 8852 /* s_buffer_atomic_xor */, AMDGPU::S_BUFFER_ATOMIC_XOR_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16374             :   { 8872 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32 }, },
   16375             :   { 8872 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20 }, },
   16376             :   { 8872 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_glc }, },
   16377             :   { 8872 /* s_buffer_atomic_xor_x2 */, AMDGPU::S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmSMRDOffset201_2, Feature_HasScalarAtomics|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_glc }, },
   16378             :   { 8895 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16379             :   { 8895 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16380             :   { 8895 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16381             :   { 8895 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16382             :   { 8895 /* s_buffer_load_dword */, AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16383             :   { 8915 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16384             :   { 8915 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16385             :   { 8915 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16386             :   { 8915 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16387             :   { 8915 /* s_buffer_load_dwordx16 */, AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_512, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16388             :   { 8938 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16389             :   { 8938 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16390             :   { 8938 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16391             :   { 8938 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16392             :   { 8938 /* s_buffer_load_dwordx2 */, AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16393             :   { 8960 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16394             :   { 8960 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16395             :   { 8960 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16396             :   { 8960 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16397             :   { 8960 /* s_buffer_load_dwordx4 */, AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16398             :   { 8982 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16399             :   { 8982 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16400             :   { 8982 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16401             :   { 8982 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16402             :   { 8982 /* s_buffer_load_dwordx8 */, AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_256, MCK_SReg_128, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16403             :   { 9004 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16404             :   { 9004 /* s_buffer_store_dword */, AMDGPU::S_BUFFER_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16405             :   { 9025 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16406             :   { 9025 /* s_buffer_store_dwordx2 */, AMDGPU::S_BUFFER_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16407             :   { 9048 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_SReg_32, MCK_ImmGLC }, },
   16408             :   { 9048 /* s_buffer_store_dwordx4 */, AMDGPU::S_BUFFER_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_128, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16409             :   { 9071 /* s_call_b64 */, AMDGPU::S_CALL_B64_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_S16Imm }, },
   16410             :   { 9082 /* s_cbranch_cdbgsys */, AMDGPU::S_CBRANCH_CDBGSYS, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16411             :   { 9100 /* s_cbranch_cdbgsys_and_user */, AMDGPU::S_CBRANCH_CDBGSYS_AND_USER, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16412             :   { 9127 /* s_cbranch_cdbgsys_or_user */, AMDGPU::S_CBRANCH_CDBGSYS_OR_USER, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16413             :   { 9153 /* s_cbranch_cdbguser */, AMDGPU::S_CBRANCH_CDBGUSER, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16414             :   { 9172 /* s_cbranch_execnz */, AMDGPU::S_CBRANCH_EXECNZ, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16415             :   { 9189 /* s_cbranch_execz */, AMDGPU::S_CBRANCH_EXECZ, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16416             :   { 9205 /* s_cbranch_g_fork */, AMDGPU::S_CBRANCH_G_FORK_si, Convert__SCSrcB641_0__SCSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SCSrcB64, MCK_SCSrcB64 }, },
   16417             :   { 9205 /* s_cbranch_g_fork */, AMDGPU::S_CBRANCH_G_FORK_vi, Convert__SCSrcB641_0__SCSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SCSrcB64, MCK_SCSrcB64 }, },
   16418             :   { 9222 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_S16Imm }, },
   16419             :   { 9222 /* s_cbranch_i_fork */, AMDGPU::S_CBRANCH_I_FORK_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_S16Imm }, },
   16420             :   { 9239 /* s_cbranch_join */, AMDGPU::S_CBRANCH_JOIN_si, Convert__Reg1_0, Feature_isGCN|Feature_isSICI, { MCK_SReg_32 }, },
   16421             :   { 9239 /* s_cbranch_join */, AMDGPU::S_CBRANCH_JOIN_vi, Convert__Reg1_0, Feature_isGCN|Feature_isVI, { MCK_SReg_32 }, },
   16422             :   { 9254 /* s_cbranch_scc0 */, AMDGPU::S_CBRANCH_SCC0, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16423             :   { 9269 /* s_cbranch_scc1 */, AMDGPU::S_CBRANCH_SCC1, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16424             :   { 9284 /* s_cbranch_vccnz */, AMDGPU::S_CBRANCH_VCCNZ, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16425             :   { 9300 /* s_cbranch_vccz */, AMDGPU::S_CBRANCH_VCCZ, Convert__SoppBrTarget1_0, Feature_isGCN, { MCK_SoppBrTarget }, },
   16426             :   { 9315 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16427             :   { 9315 /* s_cmov_b32 */, AMDGPU::S_CMOV_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16428             :   { 9326 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16429             :   { 9326 /* s_cmov_b64 */, AMDGPU::S_CMOV_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16430             :   { 9337 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16431             :   { 9337 /* s_cmovk_i32 */, AMDGPU::S_CMOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16432             :   { 9349 /* s_cmp_eq_i32 */, AMDGPU::S_CMP_EQ_I32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16433             :   { 9362 /* s_cmp_eq_u32 */, AMDGPU::S_CMP_EQ_U32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16434             :   { 9375 /* s_cmp_eq_u64 */, AMDGPU::S_CMP_EQ_U64, Convert__SSrcB641_0__SSrcB641_1, Feature_isVI, { MCK_SSrcB64, MCK_SSrcB64 }, },
   16435             :   { 9388 /* s_cmp_ge_i32 */, AMDGPU::S_CMP_GE_I32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16436             :   { 9401 /* s_cmp_ge_u32 */, AMDGPU::S_CMP_GE_U32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16437             :   { 9414 /* s_cmp_gt_i32 */, AMDGPU::S_CMP_GT_I32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16438             :   { 9427 /* s_cmp_gt_u32 */, AMDGPU::S_CMP_GT_U32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16439             :   { 9440 /* s_cmp_le_i32 */, AMDGPU::S_CMP_LE_I32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16440             :   { 9453 /* s_cmp_le_u32 */, AMDGPU::S_CMP_LE_U32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16441             :   { 9466 /* s_cmp_lg_i32 */, AMDGPU::S_CMP_LG_I32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16442             :   { 9479 /* s_cmp_lg_u32 */, AMDGPU::S_CMP_LG_U32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16443             :   { 9492 /* s_cmp_lg_u64 */, AMDGPU::S_CMP_LG_U64, Convert__SSrcB641_0__SSrcB641_1, Feature_isVI, { MCK_SSrcB64, MCK_SSrcB64 }, },
   16444             :   { 9505 /* s_cmp_lt_i32 */, AMDGPU::S_CMP_LT_I32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16445             :   { 9518 /* s_cmp_lt_u32 */, AMDGPU::S_CMP_LT_U32, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16446             :   { 9531 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16447             :   { 9531 /* s_cmpk_eq_i32 */, AMDGPU::S_CMPK_EQ_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16448             :   { 9545 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_si, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_U16Imm }, },
   16449             :   { 9545 /* s_cmpk_eq_u32 */, AMDGPU::S_CMPK_EQ_U32_vi, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_U16Imm }, },
   16450             :   { 9559 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16451             :   { 9559 /* s_cmpk_ge_i32 */, AMDGPU::S_CMPK_GE_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16452             :   { 9573 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_si, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_U16Imm }, },
   16453             :   { 9573 /* s_cmpk_ge_u32 */, AMDGPU::S_CMPK_GE_U32_vi, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_U16Imm }, },
   16454             :   { 9587 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16455             :   { 9587 /* s_cmpk_gt_i32 */, AMDGPU::S_CMPK_GT_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16456             :   { 9601 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_si, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_U16Imm }, },
   16457             :   { 9601 /* s_cmpk_gt_u32 */, AMDGPU::S_CMPK_GT_U32_vi, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_U16Imm }, },
   16458             :   { 9615 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16459             :   { 9615 /* s_cmpk_le_i32 */, AMDGPU::S_CMPK_LE_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16460             :   { 9629 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_si, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_U16Imm }, },
   16461             :   { 9629 /* s_cmpk_le_u32 */, AMDGPU::S_CMPK_LE_U32_vi, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_U16Imm }, },
   16462             :   { 9643 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16463             :   { 9643 /* s_cmpk_lg_i32 */, AMDGPU::S_CMPK_LG_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16464             :   { 9657 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_si, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_U16Imm }, },
   16465             :   { 9657 /* s_cmpk_lg_u32 */, AMDGPU::S_CMPK_LG_U32_vi, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_U16Imm }, },
   16466             :   { 9671 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16467             :   { 9671 /* s_cmpk_lt_i32 */, AMDGPU::S_CMPK_LT_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16468             :   { 9685 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_si, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_U16Imm }, },
   16469             :   { 9685 /* s_cmpk_lt_u32 */, AMDGPU::S_CMPK_LT_U32_vi, Convert__Reg1_0__U16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_U16Imm }, },
   16470             :   { 9699 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16471             :   { 9699 /* s_cselect_b32 */, AMDGPU::S_CSELECT_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16472             :   { 9713 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16473             :   { 9713 /* s_cselect_b64 */, AMDGPU::S_CSELECT_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16474             :   { 9727 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_SGPR_vi, Convert__Reg1_0__Reg1_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_SReg_32 }, },
   16475             :   { 9727 /* s_dcache_discard */, AMDGPU::S_DCACHE_DISCARD_IMM_vi, Convert__Reg1_0__ImmSMRDOffset201_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16476             :   { 9744 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_SGPR_vi, Convert__Reg1_0__Reg1_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_SReg_32 }, },
   16477             :   { 9744 /* s_dcache_discard_x2 */, AMDGPU::S_DCACHE_DISCARD_X2_IMM_vi, Convert__Reg1_0__ImmSMRDOffset201_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_ImmSMRDOffset20 }, },
   16478             :   { 9764 /* s_dcache_inv */, AMDGPU::S_DCACHE_INV_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, {  }, },
   16479             :   { 9764 /* s_dcache_inv */, AMDGPU::S_DCACHE_INV_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, {  }, },
   16480             :   { 9777 /* s_dcache_inv_vol */, AMDGPU::S_DCACHE_INV_VOL_ci, Convert_NoOperands, Feature_isCIVI|Feature_isCIOnly, {  }, },
   16481             :   { 9777 /* s_dcache_inv_vol */, AMDGPU::S_DCACHE_INV_VOL_vi, Convert_NoOperands, Feature_isCIVI|Feature_isVI, {  }, },
   16482             :   { 9794 /* s_dcache_wb */, AMDGPU::S_DCACHE_WB_vi, Convert_NoOperands, Feature_isVI|Feature_isVI, {  }, },
   16483             :   { 9806 /* s_dcache_wb_vol */, AMDGPU::S_DCACHE_WB_VOL_vi, Convert_NoOperands, Feature_isVI|Feature_isVI, {  }, },
   16484             :   { 9822 /* s_decperflevel */, AMDGPU::S_DECPERFLEVEL, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16485             :   { 9837 /* s_endpgm */, AMDGPU::S_ENDPGM, Convert_NoOperands, Feature_isGCN, {  }, },
   16486             :   { 9846 /* s_endpgm_ordered_ps_done */, AMDGPU::S_ENDPGM_ORDERED_PS_DONE, Convert_NoOperands, Feature_isGFX9, {  }, },
   16487             :   { 9871 /* s_endpgm_saved */, AMDGPU::S_ENDPGM_SAVED, Convert_NoOperands, Feature_isVI, {  }, },
   16488             :   { 9886 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16489             :   { 9886 /* s_ff0_i32_b32 */, AMDGPU::S_FF0_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16490             :   { 9900 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16491             :   { 9900 /* s_ff0_i32_b64 */, AMDGPU::S_FF0_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16492             :   { 9914 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16493             :   { 9914 /* s_ff1_i32_b32 */, AMDGPU::S_FF1_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16494             :   { 9928 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16495             :   { 9928 /* s_ff1_i32_b64 */, AMDGPU::S_FF1_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16496             :   { 9942 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16497             :   { 9942 /* s_flbit_i32 */, AMDGPU::S_FLBIT_I32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16498             :   { 9954 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16499             :   { 9954 /* s_flbit_i32_b32 */, AMDGPU::S_FLBIT_I32_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16500             :   { 9970 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16501             :   { 9970 /* s_flbit_i32_b64 */, AMDGPU::S_FLBIT_I32_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16502             :   { 9986 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16503             :   { 9986 /* s_flbit_i32_i64 */, AMDGPU::S_FLBIT_I32_I64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB64 }, },
   16504             :   { 10002 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_si, Convert__Reg1_0, Feature_isGCN|Feature_isSICI, { MCK_SReg_64 }, },
   16505             :   { 10002 /* s_getpc_b64 */, AMDGPU::S_GETPC_B64_vi, Convert__Reg1_0, Feature_isGCN|Feature_isVI, { MCK_SReg_64 }, },
   16506             :   { 10014 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_si, Convert__Reg1_0__ImmHwreg1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_ImmHwreg }, },
   16507             :   { 10014 /* s_getreg_b32 */, AMDGPU::S_GETREG_B32_vi, Convert__Reg1_0__ImmHwreg1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_ImmHwreg }, },
   16508             :   { 10027 /* s_icache_inv */, AMDGPU::S_ICACHE_INV, Convert_NoOperands, Feature_isGCN, {  }, },
   16509             :   { 10040 /* s_incperflevel */, AMDGPU::S_INCPERFLEVEL, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16510             :   { 10055 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16511             :   { 10055 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16512             :   { 10055 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16513             :   { 10055 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16514             :   { 10055 /* s_load_dword */, AMDGPU::S_LOAD_DWORD_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16515             :   { 10068 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16516             :   { 10068 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16517             :   { 10068 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16518             :   { 10068 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16519             :   { 10068 /* s_load_dwordx16 */, AMDGPU::S_LOAD_DWORDX16_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_512, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16520             :   { 10084 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16521             :   { 10084 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16522             :   { 10084 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16523             :   { 10084 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16524             :   { 10084 /* s_load_dwordx2 */, AMDGPU::S_LOAD_DWORDX2_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16525             :   { 10099 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16526             :   { 10099 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16527             :   { 10099 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16528             :   { 10099 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16529             :   { 10099 /* s_load_dwordx4 */, AMDGPU::S_LOAD_DWORDX4_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16530             :   { 10114 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_si, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16531             :   { 10114 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16532             :   { 10114 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_si, Convert__Reg1_0__Reg1_1__ImmSMRDOffset81_2__ImmGLC1_3, Feature_isGCN|Feature_isSICI, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset8, MCK_ImmGLC }, },
   16533             :   { 10114 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16534             :   { 10114 /* s_load_dwordx8 */, AMDGPU::S_LOAD_DWORDX8_IMM_ci, Convert__Reg1_0__Reg1_1__ImmSMRDLiteralOffset1_2__ImmGLC1_3, Feature_isGCN|Feature_isCIOnly, { MCK_SReg_256, MCK_SReg_64, MCK_ImmSMRDLiteralOffset, MCK_ImmGLC }, },
   16535             :   { 10129 /* s_lshl1_add_u32 */, AMDGPU::S_LSHL1_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16536             :   { 10145 /* s_lshl2_add_u32 */, AMDGPU::S_LSHL2_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16537             :   { 10161 /* s_lshl3_add_u32 */, AMDGPU::S_LSHL3_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16538             :   { 10177 /* s_lshl4_add_u32 */, AMDGPU::S_LSHL4_ADD_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16539             :   { 10193 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16540             :   { 10193 /* s_lshl_b32 */, AMDGPU::S_LSHL_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16541             :   { 10204 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16542             :   { 10204 /* s_lshl_b64 */, AMDGPU::S_LSHL_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16543             :   { 10215 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16544             :   { 10215 /* s_lshr_b32 */, AMDGPU::S_LSHR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16545             :   { 10226 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16546             :   { 10226 /* s_lshr_b64 */, AMDGPU::S_LSHR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB32 }, },
   16547             :   { 10237 /* s_max_i32 */, AMDGPU::S_MAX_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16548             :   { 10237 /* s_max_i32 */, AMDGPU::S_MAX_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16549             :   { 10247 /* s_max_u32 */, AMDGPU::S_MAX_U32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16550             :   { 10247 /* s_max_u32 */, AMDGPU::S_MAX_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16551             :   { 10257 /* s_memrealtime */, AMDGPU::S_MEMREALTIME_vi, Convert__Reg1_0, Feature_isVI|Feature_isVI, { MCK_SReg_64_XEXEC }, },
   16552             :   { 10271 /* s_memtime */, AMDGPU::S_MEMTIME_si, Convert__Reg1_0, Feature_isGCN|Feature_isSICI, { MCK_SReg_64_XEXEC }, },
   16553             :   { 10271 /* s_memtime */, AMDGPU::S_MEMTIME_vi, Convert__Reg1_0, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC }, },
   16554             :   { 10281 /* s_min_i32 */, AMDGPU::S_MIN_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16555             :   { 10281 /* s_min_i32 */, AMDGPU::S_MIN_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16556             :   { 10291 /* s_min_u32 */, AMDGPU::S_MIN_U32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16557             :   { 10291 /* s_min_u32 */, AMDGPU::S_MIN_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16558             :   { 10301 /* s_mov_b32 */, AMDGPU::S_MOV_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16559             :   { 10301 /* s_mov_b32 */, AMDGPU::S_MOV_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16560             :   { 10311 /* s_mov_b64 */, AMDGPU::S_MOV_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16561             :   { 10311 /* s_mov_b64 */, AMDGPU::S_MOV_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16562             :   { 10321 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16563             :   { 10321 /* s_mov_fed_b32 */, AMDGPU::S_MOV_FED_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16564             :   { 10335 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16565             :   { 10335 /* s_mov_regrd_b32 */, AMDGPU::S_MOV_REGRD_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16566             :   { 10351 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_si, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16567             :   { 10351 /* s_movk_i32 */, AMDGPU::S_MOVK_I32_vi, Convert__Reg1_0__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16568             :   { 10362 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16569             :   { 10362 /* s_movreld_b32 */, AMDGPU::S_MOVRELD_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16570             :   { 10376 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16571             :   { 10376 /* s_movreld_b64 */, AMDGPU::S_MOVRELD_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16572             :   { 10390 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16573             :   { 10390 /* s_movrels_b32 */, AMDGPU::S_MOVRELS_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16574             :   { 10404 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16575             :   { 10404 /* s_movrels_b64 */, AMDGPU::S_MOVRELS_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16576             :   { 10418 /* s_mul_hi_i32 */, AMDGPU::S_MUL_HI_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16577             :   { 10431 /* s_mul_hi_u32 */, AMDGPU::S_MUL_HI_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16578             :   { 10444 /* s_mul_i32 */, AMDGPU::S_MUL_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16579             :   { 10444 /* s_mul_i32 */, AMDGPU::S_MUL_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16580             :   { 10454 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_si, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_S16Imm }, },
   16581             :   { 10454 /* s_mulk_i32 */, AMDGPU::S_MULK_I32_vi, Convert__Reg1_0__Tie0_1_1__S16Imm1_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_S16Imm }, },
   16582             :   { 10465 /* s_nand_b32 */, AMDGPU::S_NAND_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16583             :   { 10465 /* s_nand_b32 */, AMDGPU::S_NAND_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16584             :   { 10476 /* s_nand_b64 */, AMDGPU::S_NAND_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16585             :   { 10476 /* s_nand_b64 */, AMDGPU::S_NAND_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16586             :   { 10487 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16587             :   { 10487 /* s_nand_saveexec_b64 */, AMDGPU::S_NAND_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16588             :   { 10507 /* s_nop */, AMDGPU::S_NOP, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16589             :   { 10513 /* s_nor_b32 */, AMDGPU::S_NOR_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16590             :   { 10513 /* s_nor_b32 */, AMDGPU::S_NOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16591             :   { 10523 /* s_nor_b64 */, AMDGPU::S_NOR_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16592             :   { 10523 /* s_nor_b64 */, AMDGPU::S_NOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16593             :   { 10533 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16594             :   { 10533 /* s_nor_saveexec_b64 */, AMDGPU::S_NOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16595             :   { 10552 /* s_not_b32 */, AMDGPU::S_NOT_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16596             :   { 10552 /* s_not_b32 */, AMDGPU::S_NOT_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16597             :   { 10562 /* s_not_b64 */, AMDGPU::S_NOT_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16598             :   { 10562 /* s_not_b64 */, AMDGPU::S_NOT_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16599             :   { 10572 /* s_or_b32 */, AMDGPU::S_OR_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16600             :   { 10572 /* s_or_b32 */, AMDGPU::S_OR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16601             :   { 10581 /* s_or_b64 */, AMDGPU::S_OR_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16602             :   { 10581 /* s_or_b64 */, AMDGPU::S_OR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16603             :   { 10590 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16604             :   { 10590 /* s_or_saveexec_b64 */, AMDGPU::S_OR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16605             :   { 10608 /* s_orn1_saveexec_b64 */, AMDGPU::S_ORN1_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGFX9|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16606             :   { 10628 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16607             :   { 10628 /* s_orn2_b32 */, AMDGPU::S_ORN2_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16608             :   { 10639 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16609             :   { 10639 /* s_orn2_b64 */, AMDGPU::S_ORN2_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16610             :   { 10650 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16611             :   { 10650 /* s_orn2_saveexec_b64 */, AMDGPU::S_ORN2_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16612             :   { 10670 /* s_pack_hh_b32_b16 */, AMDGPU::S_PACK_HH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16613             :   { 10688 /* s_pack_lh_b32_b16 */, AMDGPU::S_PACK_LH_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16614             :   { 10706 /* s_pack_ll_b32_b16 */, AMDGPU::S_PACK_LL_B32_B16_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGFX9|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16615             :   { 10724 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16616             :   { 10724 /* s_quadmask_b32 */, AMDGPU::S_QUADMASK_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16617             :   { 10739 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16618             :   { 10739 /* s_quadmask_b64 */, AMDGPU::S_QUADMASK_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16619             :   { 10754 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_si, Convert__Reg1_0, Feature_isGCN|Feature_isSICI, { MCK_SReg_64 }, },
   16620             :   { 10754 /* s_rfe_b64 */, AMDGPU::S_RFE_B64_vi, Convert__Reg1_0, Feature_isGCN|Feature_isVI, { MCK_SReg_64 }, },
   16621             :   { 10764 /* s_rfe_restore_b64 */, AMDGPU::S_RFE_RESTORE_B64_vi, Convert__SSrcB641_0__SSrcB321_1, Feature_isVI|Feature_isVI, { MCK_SSrcB64, MCK_SSrcB32 }, },
   16622             :   { 10782 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16623             :   { 10782 /* s_scratch_load_dword */, AMDGPU::S_SCRATCH_LOAD_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16624             :   { 10803 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16625             :   { 10803 /* s_scratch_load_dwordx2 */, AMDGPU::S_SCRATCH_LOAD_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16626             :   { 10826 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16627             :   { 10826 /* s_scratch_load_dwordx4 */, AMDGPU::S_SCRATCH_LOAD_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16628             :   { 10849 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16629             :   { 10849 /* s_scratch_store_dword */, AMDGPU::S_SCRATCH_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16630             :   { 10871 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16631             :   { 10871 /* s_scratch_store_dwordx2 */, AMDGPU::S_SCRATCH_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16632             :   { 10895 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16633             :   { 10895 /* s_scratch_store_dwordx4 */, AMDGPU::S_SCRATCH_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16634             :   { 10919 /* s_sendmsg */, AMDGPU::S_SENDMSG, Convert__SendMsg1_0, Feature_isGCN, { MCK_SendMsg }, },
   16635             :   { 10929 /* s_sendmsghalt */, AMDGPU::S_SENDMSGHALT, Convert__SendMsg1_0, Feature_isGCN, { MCK_SendMsg }, },
   16636             :   { 10943 /* s_set_gpr_idx_idx */, AMDGPU::S_SET_GPR_IDX_IDX_vi, Convert__SSrcB321_0, Feature_HasVGPRIndexMode|Feature_isVI, { MCK_SSrcB32 }, },
   16637             :   { 10961 /* s_set_gpr_idx_mode */, AMDGPU::S_SET_GPR_IDX_MODE, Convert__GPRIdxMode1_0, Feature_HasVGPRIndexMode, { MCK_GPRIdxMode }, },
   16638             :   { 10980 /* s_set_gpr_idx_off */, AMDGPU::S_SET_GPR_IDX_OFF, Convert_NoOperands, Feature_HasVGPRIndexMode, {  }, },
   16639             :   { 10998 /* s_set_gpr_idx_on */, AMDGPU::S_SET_GPR_IDX_ON, Convert__SSrcB321_0__GPRIdxMode1_1, Feature_HasVGPRIndexMode, { MCK_SSrcB32, MCK_GPRIdxMode }, },
   16640             :   { 11015 /* s_sethalt */, AMDGPU::S_SETHALT, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16641             :   { 11025 /* s_setkill */, AMDGPU::S_SETKILL, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16642             :   { 11035 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_si, Convert__Reg1_0, Feature_isGCN|Feature_isSICI, { MCK_SReg_64 }, },
   16643             :   { 11035 /* s_setpc_b64 */, AMDGPU::S_SETPC_B64_vi, Convert__Reg1_0, Feature_isGCN|Feature_isVI, { MCK_SReg_64 }, },
   16644             :   { 11047 /* s_setprio */, AMDGPU::S_SETPRIO, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16645             :   { 11057 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_si, Convert__Reg1_1__ImmHwreg1_0, Feature_isGCN|Feature_isSICI, { MCK_ImmHwreg, MCK_SReg_32 }, },
   16646             :   { 11057 /* s_setreg_b32 */, AMDGPU::S_SETREG_B32_vi, Convert__Reg1_1__ImmHwreg1_0, Feature_isGCN|Feature_isVI, { MCK_ImmHwreg, MCK_SReg_32 }, },
   16647             :   { 11070 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_si, Convert__Imm1_1__ImmHwreg1_0, Feature_isGCN|Feature_isSICI, { MCK_ImmHwreg, MCK_Imm }, },
   16648             :   { 11070 /* s_setreg_imm32_b32 */, AMDGPU::S_SETREG_IMM32_B32_vi, Convert__Imm1_1__ImmHwreg1_0, Feature_isGCN|Feature_isVI, { MCK_ImmHwreg, MCK_Imm }, },
   16649             :   { 11089 /* s_setvskip */, AMDGPU::S_SETVSKIP, Convert__SSrcB321_0__SSrcB321_1, Feature_isGCN, { MCK_SSrcB32, MCK_SSrcB32 }, },
   16650             :   { 11100 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16651             :   { 11100 /* s_sext_i32_i16 */, AMDGPU::S_SEXT_I32_I16_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16652             :   { 11115 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16653             :   { 11115 /* s_sext_i32_i8 */, AMDGPU::S_SEXT_I32_I8_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16654             :   { 11129 /* s_sleep */, AMDGPU::S_SLEEP, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16655             :   { 11137 /* s_store_dword */, AMDGPU::S_STORE_DWORD_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16656             :   { 11137 /* s_store_dword */, AMDGPU::S_STORE_DWORD_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_32_XM0_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16657             :   { 11151 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16658             :   { 11151 /* s_store_dwordx2 */, AMDGPU::S_STORE_DWORDX2_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_64_XEXEC, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16659             :   { 11167 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_SGPR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_SReg_32, MCK_ImmGLC }, },
   16660             :   { 11167 /* s_store_dwordx4 */, AMDGPU::S_STORE_DWORDX4_IMM_vi, Convert__Reg1_0__Reg1_1__ImmSMRDOffset201_2__ImmGLC1_3, Feature_isGCN|Feature_isVI, { MCK_SReg_128, MCK_SReg_64, MCK_ImmSMRDOffset20, MCK_ImmGLC }, },
   16661             :   { 11183 /* s_sub_i32 */, AMDGPU::S_SUB_I32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16662             :   { 11183 /* s_sub_i32 */, AMDGPU::S_SUB_I32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16663             :   { 11193 /* s_sub_u32 */, AMDGPU::S_SUB_U32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16664             :   { 11193 /* s_sub_u32 */, AMDGPU::S_SUB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16665             :   { 11203 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16666             :   { 11203 /* s_subb_u32 */, AMDGPU::S_SUBB_U32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16667             :   { 11214 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16668             :   { 11214 /* s_swappc_b64 */, AMDGPU::S_SWAPPC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16669             :   { 11227 /* s_trap */, AMDGPU::S_TRAP, Convert__Imm1_0, Feature_isGCN, { MCK_Imm }, },
   16670             :   { 11234 /* s_ttracedata */, AMDGPU::S_TTRACEDATA, Convert_NoOperands, Feature_isGCN, {  }, },
   16671             :   { 11247 /* s_waitcnt */, AMDGPU::S_WAITCNT, Convert__SWaitCnt1_0, Feature_isGCN, { MCK_SWaitCnt }, },
   16672             :   { 11257 /* s_wakeup */, AMDGPU::S_WAKEUP, Convert_NoOperands, Feature_isVI, {  }, },
   16673             :   { 11266 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_si, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16674             :   { 11266 /* s_wqm_b32 */, AMDGPU::S_WQM_B32_vi, Convert__Reg1_0__SSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32 }, },
   16675             :   { 11276 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16676             :   { 11276 /* s_wqm_b64 */, AMDGPU::S_WQM_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16677             :   { 11286 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16678             :   { 11286 /* s_xnor_b32 */, AMDGPU::S_XNOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16679             :   { 11297 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16680             :   { 11297 /* s_xnor_b64 */, AMDGPU::S_XNOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16681             :   { 11308 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16682             :   { 11308 /* s_xnor_saveexec_b64 */, AMDGPU::S_XNOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16683             :   { 11328 /* s_xor_b32 */, AMDGPU::S_XOR_B32_si, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16684             :   { 11328 /* s_xor_b32 */, AMDGPU::S_XOR_B32_vi, Convert__Reg1_0__SSrcB321_1__SSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_SSrcB32, MCK_SSrcB32 }, },
   16685             :   { 11338 /* s_xor_b64 */, AMDGPU::S_XOR_B64_si, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16686             :   { 11338 /* s_xor_b64 */, AMDGPU::S_XOR_B64_vi, Convert__Reg1_0__SSrcB641_1__SSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64, MCK_SSrcB64 }, },
   16687             :   { 11348 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_si, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16688             :   { 11348 /* s_xor_saveexec_b64 */, AMDGPU::S_XOR_SAVEEXEC_B64_vi, Convert__Reg1_0__SSrcB641_1, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_SSrcB64 }, },
   16689             :   { 11367 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16690             :   { 11367 /* scratch_load_dword */, AMDGPU::SCRATCH_LOAD_DWORD_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16691             :   { 11386 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16692             :   { 11386 /* scratch_load_dwordx2 */, AMDGPU::SCRATCH_LOAD_DWORDX2_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16693             :   { 11407 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VReg_96, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16694             :   { 11407 /* scratch_load_dwordx3 */, AMDGPU::SCRATCH_LOAD_DWORDX3_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VReg_96, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16695             :   { 11428 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16696             :   { 11428 /* scratch_load_dwordx4 */, AMDGPU::SCRATCH_LOAD_DWORDX4_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16697             :   { 11449 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16698             :   { 11449 /* scratch_load_sbyte */, AMDGPU::SCRATCH_LOAD_SBYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16699             :   { 11468 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16700             :   { 11468 /* scratch_load_sbyte_d16 */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16701             :   { 11491 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16702             :   { 11491 /* scratch_load_sbyte_d16_hi */, AMDGPU::SCRATCH_LOAD_SBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16703             :   { 11517 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16704             :   { 11517 /* scratch_load_short_d16 */, AMDGPU::SCRATCH_LOAD_SHORT_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16705             :   { 11540 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16706             :   { 11540 /* scratch_load_short_d16_hi */, AMDGPU::SCRATCH_LOAD_SHORT_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16707             :   { 11566 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16708             :   { 11566 /* scratch_load_sshort */, AMDGPU::SCRATCH_LOAD_SSHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16709             :   { 11586 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16710             :   { 11586 /* scratch_load_ubyte */, AMDGPU::SCRATCH_LOAD_UBYTE_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16711             :   { 11605 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16712             :   { 11605 /* scratch_load_ubyte_d16 */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16713             :   { 11628 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16714             :   { 11628 /* scratch_load_ubyte_d16_hi */, AMDGPU::SCRATCH_LOAD_UBYTE_D16_HI_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16715             :   { 11654 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_SADDR_vi, Convert__Reg1_0__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16716             :   { 11654 /* scratch_load_ushort */, AMDGPU::SCRATCH_LOAD_USHORT_vi, Convert__Reg1_0__Reg1_1__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16717             :   { 11674 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16718             :   { 11674 /* scratch_store_byte */, AMDGPU::SCRATCH_STORE_BYTE_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16719             :   { 11693 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16720             :   { 11693 /* scratch_store_byte_d16_hi */, AMDGPU::SCRATCH_STORE_BYTE_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16721             :   { 11719 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16722             :   { 11719 /* scratch_store_dword */, AMDGPU::SCRATCH_STORE_DWORD_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16723             :   { 11739 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VReg_64, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16724             :   { 11739 /* scratch_store_dwordx2 */, AMDGPU::SCRATCH_STORE_DWORDX2_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16725             :   { 11761 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VReg_96, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16726             :   { 11761 /* scratch_store_dwordx3 */, AMDGPU::SCRATCH_STORE_DWORDX3_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_96, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16727             :   { 11783 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VReg_128, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16728             :   { 11783 /* scratch_store_dwordx4 */, AMDGPU::SCRATCH_STORE_DWORDX4_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VReg_128, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16729             :   { 11805 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16730             :   { 11805 /* scratch_store_short */, AMDGPU::SCRATCH_STORE_SHORT_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16731             :   { 11825 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR_vi, Convert__Reg1_1__Reg1_2__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_off, MCK_VGPR_32, MCK_SReg_32_XEXEC_HI, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16732             :   { 11825 /* scratch_store_short_d16_hi */, AMDGPU::SCRATCH_STORE_SHORT_D16_HI_vi, Convert__Reg1_1__Reg1_0__ImmOffsetS131_3__ImmGLC1_4__ImmSLC1_5, Feature_HasFlatScratchInsts|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_off, MCK_ImmOffsetS13, MCK_ImmGLC, MCK_ImmSLC }, },
   16733             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16734             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16735             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16736             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16737             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16738             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16739             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16740             :   { 11852 /* tbuffer_load_format_d16_x */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16741             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16742             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16743             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16744             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16745             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16746             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16747             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16748             :   { 11878 /* tbuffer_load_format_d16_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16749             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16750             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16751             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16752             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16753             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16754             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16755             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16756             :   { 11905 /* tbuffer_load_format_d16_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16757             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16758             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16759             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16760             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16761             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16762             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16763             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16764             :   { 11933 /* tbuffer_load_format_d16_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16765             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16766             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16767             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16768             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16769             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16770             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16771             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16772             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16773             :   { 11962 /* tbuffer_load_format_x */, AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16774             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16775             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16776             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16777             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16778             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16779             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16780             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16781             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16782             :   { 11984 /* tbuffer_load_format_xy */, AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16783             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16784             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16785             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16786             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16787             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16788             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16789             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16790             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16791             :   { 12007 /* tbuffer_load_format_xyz */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16792             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16793             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16794             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16795             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16796             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16797             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16798             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16799             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16800             :   { 12031 /* tbuffer_load_format_xyzw */, AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16801             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16802             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16803             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16804             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16805             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16806             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16807             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16808             :   { 12056 /* tbuffer_store_format_d16_x */, AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16809             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16810             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16811             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16812             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16813             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16814             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16815             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16816             :   { 12083 /* tbuffer_store_format_d16_xy */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16817             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16818             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16819             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16820             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16821             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16822             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16823             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_96, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16824             :   { 12111 /* tbuffer_store_format_d16_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16825             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16826             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16827             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16828             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16829             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16830             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16831             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80, ConvertCustom_cvtMtbuf, Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16832             :   { 12140 /* tbuffer_store_format_d16_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_HasPackedD16VMem|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16833             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16834             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16835             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16836             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16837             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16838             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16839             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16840             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16841             :   { 12170 /* tbuffer_store_format_x */, AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16842             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16843             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16844             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16845             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16846             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16847             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16848             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16849             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16850             :   { 12193 /* tbuffer_store_format_xy */, AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16851             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16852             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16853             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16854             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16855             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16856             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16857             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16858             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16859             :   { 12217 /* tbuffer_store_format_xyz */, AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16860             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16861             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_off, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16862             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_ADDR64_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_addr64, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16863             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16864             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16865             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16866             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VGPR_32, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16867             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_si, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isSICI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16868             :   { 12242 /* tbuffer_store_format_xyzw */, AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi, ConvertCustom_cvtMtbuf, Feature_isGCN|Feature_isVI, { MCK_VReg_128, MCK_VReg_64, MCK_SReg_128, MCK_ImmFORMAT, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmTFE }, },
   16869             :   { 12279 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16870             :   { 12292 /* v_add_f16 */, AMDGPU::V_ADD_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   16871             :   { 12302 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   16872             :   { 12302 /* v_add_f32 */, AMDGPU::V_ADD_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   16873             :   { 12332 /* v_add_i32 */, AMDGPU::V_ADD_I32_e32_si, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16874             :   { 12357 /* v_add_u16 */, AMDGPU::V_ADD_U16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   16875             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_HasAddNoCarryInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16876             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16877             :   { 12377 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e32_gfx9, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   16878             :   { 12391 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_si, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   16879             :   { 12391 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e32_vi, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   16880             :   { 12433 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16881             :   { 12433 /* v_and_b32 */, AMDGPU::V_AND_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16882             :   { 12456 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16883             :   { 12478 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   16884             :   { 12492 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16885             :   { 12492 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16886             :   { 12520 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16887             :   { 12565 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   16888             :   { 12575 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   16889             :   { 12575 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   16890             :   { 12587 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   16891             :   { 12598 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   16892             :   { 12598 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   16893             :   { 12609 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_ci, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_VSrcF64 }, },
   16894             :   { 12609 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   16895             :   { 12620 /* v_clrexcp */, AMDGPU::V_CLREXCP_e32_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, {  }, },
   16896             :   { 12620 /* v_clrexcp */, AMDGPU::V_CLREXCP_e32_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, {  }, },
   16897             :   { 12630 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16898             :   { 12646 /* v_cmp_class_f16_e32 */, AMDGPU::V_CMP_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16899             :   { 12666 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16900             :   { 12666 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16901             :   { 12682 /* v_cmp_class_f32_e32 */, AMDGPU::V_CMP_CLASS_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16902             :   { 12682 /* v_cmp_class_f32_e32 */, AMDGPU::V_CMP_CLASS_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16903             :   { 12702 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   16904             :   { 12702 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   16905             :   { 12718 /* v_cmp_class_f64_e32 */, AMDGPU::V_CMP_CLASS_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   16906             :   { 12718 /* v_cmp_class_f64_e32 */, AMDGPU::V_CMP_CLASS_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   16907             :   { 12738 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16908             :   { 12751 /* v_cmp_eq_f16_e32 */, AMDGPU::V_CMP_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16909             :   { 12768 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16910             :   { 12768 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16911             :   { 12781 /* v_cmp_eq_f32_e32 */, AMDGPU::V_CMP_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16912             :   { 12781 /* v_cmp_eq_f32_e32 */, AMDGPU::V_CMP_EQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16913             :   { 12798 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16914             :   { 12798 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16915             :   { 12811 /* v_cmp_eq_f64_e32 */, AMDGPU::V_CMP_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16916             :   { 12811 /* v_cmp_eq_f64_e32 */, AMDGPU::V_CMP_EQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16917             :   { 12828 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16918             :   { 12841 /* v_cmp_eq_i16_e32 */, AMDGPU::V_CMP_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16919             :   { 12858 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16920             :   { 12858 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16921             :   { 12871 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16922             :   { 12871 /* v_cmp_eq_i32_e32 */, AMDGPU::V_CMP_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16923             :   { 12888 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16924             :   { 12888 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16925             :   { 12901 /* v_cmp_eq_i64_e32 */, AMDGPU::V_CMP_EQ_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16926             :   { 12901 /* v_cmp_eq_i64_e32 */, AMDGPU::V_CMP_EQ_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16927             :   { 12918 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16928             :   { 12931 /* v_cmp_eq_u16_e32 */, AMDGPU::V_CMP_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16929             :   { 12948 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16930             :   { 12948 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16931             :   { 12961 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16932             :   { 12961 /* v_cmp_eq_u32_e32 */, AMDGPU::V_CMP_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16933             :   { 12978 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16934             :   { 12978 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16935             :   { 12991 /* v_cmp_eq_u64_e32 */, AMDGPU::V_CMP_EQ_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16936             :   { 12991 /* v_cmp_eq_u64_e32 */, AMDGPU::V_CMP_EQ_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16937             :   { 13008 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16938             :   { 13020 /* v_cmp_f_f16_e32 */, AMDGPU::V_CMP_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16939             :   { 13036 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16940             :   { 13036 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16941             :   { 13048 /* v_cmp_f_f32_e32 */, AMDGPU::V_CMP_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16942             :   { 13048 /* v_cmp_f_f32_e32 */, AMDGPU::V_CMP_F_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16943             :   { 13064 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16944             :   { 13064 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16945             :   { 13076 /* v_cmp_f_f64_e32 */, AMDGPU::V_CMP_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16946             :   { 13076 /* v_cmp_f_f64_e32 */, AMDGPU::V_CMP_F_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16947             :   { 13092 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16948             :   { 13104 /* v_cmp_f_i16_e32 */, AMDGPU::V_CMP_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16949             :   { 13120 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16950             :   { 13120 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16951             :   { 13132 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16952             :   { 13132 /* v_cmp_f_i32_e32 */, AMDGPU::V_CMP_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16953             :   { 13148 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16954             :   { 13148 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16955             :   { 13160 /* v_cmp_f_i64_e32 */, AMDGPU::V_CMP_F_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16956             :   { 13160 /* v_cmp_f_i64_e32 */, AMDGPU::V_CMP_F_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16957             :   { 13176 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16958             :   { 13188 /* v_cmp_f_u16_e32 */, AMDGPU::V_CMP_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16959             :   { 13204 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16960             :   { 13204 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16961             :   { 13216 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16962             :   { 13216 /* v_cmp_f_u32_e32 */, AMDGPU::V_CMP_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16963             :   { 13232 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16964             :   { 13232 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16965             :   { 13244 /* v_cmp_f_u64_e32 */, AMDGPU::V_CMP_F_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16966             :   { 13244 /* v_cmp_f_u64_e32 */, AMDGPU::V_CMP_F_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16967             :   { 13260 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16968             :   { 13273 /* v_cmp_ge_f16_e32 */, AMDGPU::V_CMP_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16969             :   { 13290 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16970             :   { 13290 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16971             :   { 13303 /* v_cmp_ge_f32_e32 */, AMDGPU::V_CMP_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16972             :   { 13303 /* v_cmp_ge_f32_e32 */, AMDGPU::V_CMP_GE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   16973             :   { 13320 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16974             :   { 13320 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16975             :   { 13333 /* v_cmp_ge_f64_e32 */, AMDGPU::V_CMP_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16976             :   { 13333 /* v_cmp_ge_f64_e32 */, AMDGPU::V_CMP_GE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   16977             :   { 13350 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16978             :   { 13363 /* v_cmp_ge_i16_e32 */, AMDGPU::V_CMP_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16979             :   { 13380 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16980             :   { 13380 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16981             :   { 13393 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16982             :   { 13393 /* v_cmp_ge_i32_e32 */, AMDGPU::V_CMP_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16983             :   { 13410 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16984             :   { 13410 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16985             :   { 13423 /* v_cmp_ge_i64_e32 */, AMDGPU::V_CMP_GE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16986             :   { 13423 /* v_cmp_ge_i64_e32 */, AMDGPU::V_CMP_GE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16987             :   { 13440 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16988             :   { 13453 /* v_cmp_ge_u16_e32 */, AMDGPU::V_CMP_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   16989             :   { 13470 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16990             :   { 13470 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16991             :   { 13483 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16992             :   { 13483 /* v_cmp_ge_u32_e32 */, AMDGPU::V_CMP_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   16993             :   { 13500 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16994             :   { 13500 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16995             :   { 13513 /* v_cmp_ge_u64_e32 */, AMDGPU::V_CMP_GE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16996             :   { 13513 /* v_cmp_ge_u64_e32 */, AMDGPU::V_CMP_GE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   16997             :   { 13530 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16998             :   { 13543 /* v_cmp_gt_f16_e32 */, AMDGPU::V_CMP_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   16999             :   { 13560 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17000             :   { 13560 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17001             :   { 13573 /* v_cmp_gt_f32_e32 */, AMDGPU::V_CMP_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17002             :   { 13573 /* v_cmp_gt_f32_e32 */, AMDGPU::V_CMP_GT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17003             :   { 13590 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17004             :   { 13590 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17005             :   { 13603 /* v_cmp_gt_f64_e32 */, AMDGPU::V_CMP_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17006             :   { 13603 /* v_cmp_gt_f64_e32 */, AMDGPU::V_CMP_GT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17007             :   { 13620 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17008             :   { 13633 /* v_cmp_gt_i16_e32 */, AMDGPU::V_CMP_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17009             :   { 13650 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17010             :   { 13650 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17011             :   { 13663 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17012             :   { 13663 /* v_cmp_gt_i32_e32 */, AMDGPU::V_CMP_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17013             :   { 13680 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17014             :   { 13680 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17015             :   { 13693 /* v_cmp_gt_i64_e32 */, AMDGPU::V_CMP_GT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17016             :   { 13693 /* v_cmp_gt_i64_e32 */, AMDGPU::V_CMP_GT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17017             :   { 13710 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17018             :   { 13723 /* v_cmp_gt_u16_e32 */, AMDGPU::V_CMP_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17019             :   { 13740 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17020             :   { 13740 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17021             :   { 13753 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17022             :   { 13753 /* v_cmp_gt_u32_e32 */, AMDGPU::V_CMP_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17023             :   { 13770 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17024             :   { 13770 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17025             :   { 13783 /* v_cmp_gt_u64_e32 */, AMDGPU::V_CMP_GT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17026             :   { 13783 /* v_cmp_gt_u64_e32 */, AMDGPU::V_CMP_GT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17027             :   { 13800 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17028             :   { 13813 /* v_cmp_le_f16_e32 */, AMDGPU::V_CMP_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17029             :   { 13830 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17030             :   { 13830 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17031             :   { 13843 /* v_cmp_le_f32_e32 */, AMDGPU::V_CMP_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17032             :   { 13843 /* v_cmp_le_f32_e32 */, AMDGPU::V_CMP_LE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17033             :   { 13860 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17034             :   { 13860 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17035             :   { 13873 /* v_cmp_le_f64_e32 */, AMDGPU::V_CMP_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17036             :   { 13873 /* v_cmp_le_f64_e32 */, AMDGPU::V_CMP_LE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17037             :   { 13890 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17038             :   { 13903 /* v_cmp_le_i16_e32 */, AMDGPU::V_CMP_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17039             :   { 13920 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17040             :   { 13920 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17041             :   { 13933 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17042             :   { 13933 /* v_cmp_le_i32_e32 */, AMDGPU::V_CMP_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17043             :   { 13950 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17044             :   { 13950 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17045             :   { 13963 /* v_cmp_le_i64_e32 */, AMDGPU::V_CMP_LE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17046             :   { 13963 /* v_cmp_le_i64_e32 */, AMDGPU::V_CMP_LE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17047             :   { 13980 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17048             :   { 13993 /* v_cmp_le_u16_e32 */, AMDGPU::V_CMP_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17049             :   { 14010 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17050             :   { 14010 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17051             :   { 14023 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17052             :   { 14023 /* v_cmp_le_u32_e32 */, AMDGPU::V_CMP_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17053             :   { 14040 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17054             :   { 14040 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17055             :   { 14053 /* v_cmp_le_u64_e32 */, AMDGPU::V_CMP_LE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17056             :   { 14053 /* v_cmp_le_u64_e32 */, AMDGPU::V_CMP_LE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17057             :   { 14070 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17058             :   { 14083 /* v_cmp_lg_f16_e32 */, AMDGPU::V_CMP_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17059             :   { 14100 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17060             :   { 14100 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17061             :   { 14113 /* v_cmp_lg_f32_e32 */, AMDGPU::V_CMP_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17062             :   { 14113 /* v_cmp_lg_f32_e32 */, AMDGPU::V_CMP_LG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17063             :   { 14130 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17064             :   { 14130 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17065             :   { 14143 /* v_cmp_lg_f64_e32 */, AMDGPU::V_CMP_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17066             :   { 14143 /* v_cmp_lg_f64_e32 */, AMDGPU::V_CMP_LG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17067             :   { 14160 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17068             :   { 14173 /* v_cmp_lt_f16_e32 */, AMDGPU::V_CMP_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17069             :   { 14190 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17070             :   { 14190 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17071             :   { 14203 /* v_cmp_lt_f32_e32 */, AMDGPU::V_CMP_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17072             :   { 14203 /* v_cmp_lt_f32_e32 */, AMDGPU::V_CMP_LT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17073             :   { 14220 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17074             :   { 14220 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17075             :   { 14233 /* v_cmp_lt_f64_e32 */, AMDGPU::V_CMP_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17076             :   { 14233 /* v_cmp_lt_f64_e32 */, AMDGPU::V_CMP_LT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17077             :   { 14250 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17078             :   { 14263 /* v_cmp_lt_i16_e32 */, AMDGPU::V_CMP_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17079             :   { 14280 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17080             :   { 14280 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17081             :   { 14293 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17082             :   { 14293 /* v_cmp_lt_i32_e32 */, AMDGPU::V_CMP_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17083             :   { 14310 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17084             :   { 14310 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17085             :   { 14323 /* v_cmp_lt_i64_e32 */, AMDGPU::V_CMP_LT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17086             :   { 14323 /* v_cmp_lt_i64_e32 */, AMDGPU::V_CMP_LT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17087             :   { 14340 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17088             :   { 14353 /* v_cmp_lt_u16_e32 */, AMDGPU::V_CMP_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17089             :   { 14370 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17090             :   { 14370 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17091             :   { 14383 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17092             :   { 14383 /* v_cmp_lt_u32_e32 */, AMDGPU::V_CMP_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17093             :   { 14400 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17094             :   { 14400 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17095             :   { 14413 /* v_cmp_lt_u64_e32 */, AMDGPU::V_CMP_LT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17096             :   { 14413 /* v_cmp_lt_u64_e32 */, AMDGPU::V_CMP_LT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17097             :   { 14430 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17098             :   { 14443 /* v_cmp_ne_i16_e32 */, AMDGPU::V_CMP_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17099             :   { 14460 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17100             :   { 14460 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17101             :   { 14473 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17102             :   { 14473 /* v_cmp_ne_i32_e32 */, AMDGPU::V_CMP_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17103             :   { 14490 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17104             :   { 14490 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17105             :   { 14503 /* v_cmp_ne_i64_e32 */, AMDGPU::V_CMP_NE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17106             :   { 14503 /* v_cmp_ne_i64_e32 */, AMDGPU::V_CMP_NE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17107             :   { 14520 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17108             :   { 14533 /* v_cmp_ne_u16_e32 */, AMDGPU::V_CMP_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17109             :   { 14550 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17110             :   { 14550 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17111             :   { 14563 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17112             :   { 14563 /* v_cmp_ne_u32_e32 */, AMDGPU::V_CMP_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17113             :   { 14580 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17114             :   { 14580 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17115             :   { 14593 /* v_cmp_ne_u64_e32 */, AMDGPU::V_CMP_NE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17116             :   { 14593 /* v_cmp_ne_u64_e32 */, AMDGPU::V_CMP_NE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17117             :   { 14610 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17118             :   { 14624 /* v_cmp_neq_f16_e32 */, AMDGPU::V_CMP_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17119             :   { 14642 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17120             :   { 14642 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17121             :   { 14656 /* v_cmp_neq_f32_e32 */, AMDGPU::V_CMP_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17122             :   { 14656 /* v_cmp_neq_f32_e32 */, AMDGPU::V_CMP_NEQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17123             :   { 14674 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17124             :   { 14674 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17125             :   { 14688 /* v_cmp_neq_f64_e32 */, AMDGPU::V_CMP_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17126             :   { 14688 /* v_cmp_neq_f64_e32 */, AMDGPU::V_CMP_NEQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17127             :   { 14706 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17128             :   { 14720 /* v_cmp_nge_f16_e32 */, AMDGPU::V_CMP_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17129             :   { 14738 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17130             :   { 14738 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17131             :   { 14752 /* v_cmp_nge_f32_e32 */, AMDGPU::V_CMP_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17132             :   { 14752 /* v_cmp_nge_f32_e32 */, AMDGPU::V_CMP_NGE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17133             :   { 14770 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17134             :   { 14770 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17135             :   { 14784 /* v_cmp_nge_f64_e32 */, AMDGPU::V_CMP_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17136             :   { 14784 /* v_cmp_nge_f64_e32 */, AMDGPU::V_CMP_NGE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17137             :   { 14802 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17138             :   { 14816 /* v_cmp_ngt_f16_e32 */, AMDGPU::V_CMP_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17139             :   { 14834 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17140             :   { 14834 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17141             :   { 14848 /* v_cmp_ngt_f32_e32 */, AMDGPU::V_CMP_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17142             :   { 14848 /* v_cmp_ngt_f32_e32 */, AMDGPU::V_CMP_NGT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17143             :   { 14866 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17144             :   { 14866 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17145             :   { 14880 /* v_cmp_ngt_f64_e32 */, AMDGPU::V_CMP_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17146             :   { 14880 /* v_cmp_ngt_f64_e32 */, AMDGPU::V_CMP_NGT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17147             :   { 14898 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17148             :   { 14912 /* v_cmp_nle_f16_e32 */, AMDGPU::V_CMP_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17149             :   { 14930 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17150             :   { 14930 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17151             :   { 14944 /* v_cmp_nle_f32_e32 */, AMDGPU::V_CMP_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17152             :   { 14944 /* v_cmp_nle_f32_e32 */, AMDGPU::V_CMP_NLE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17153             :   { 14962 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17154             :   { 14962 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17155             :   { 14976 /* v_cmp_nle_f64_e32 */, AMDGPU::V_CMP_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17156             :   { 14976 /* v_cmp_nle_f64_e32 */, AMDGPU::V_CMP_NLE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17157             :   { 14994 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17158             :   { 15008 /* v_cmp_nlg_f16_e32 */, AMDGPU::V_CMP_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17159             :   { 15026 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17160             :   { 15026 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17161             :   { 15040 /* v_cmp_nlg_f32_e32 */, AMDGPU::V_CMP_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17162             :   { 15040 /* v_cmp_nlg_f32_e32 */, AMDGPU::V_CMP_NLG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17163             :   { 15058 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17164             :   { 15058 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17165             :   { 15072 /* v_cmp_nlg_f64_e32 */, AMDGPU::V_CMP_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17166             :   { 15072 /* v_cmp_nlg_f64_e32 */, AMDGPU::V_CMP_NLG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17167             :   { 15090 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17168             :   { 15104 /* v_cmp_nlt_f16_e32 */, AMDGPU::V_CMP_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17169             :   { 15122 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17170             :   { 15122 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17171             :   { 15136 /* v_cmp_nlt_f32_e32 */, AMDGPU::V_CMP_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17172             :   { 15136 /* v_cmp_nlt_f32_e32 */, AMDGPU::V_CMP_NLT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17173             :   { 15154 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17174             :   { 15154 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17175             :   { 15168 /* v_cmp_nlt_f64_e32 */, AMDGPU::V_CMP_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17176             :   { 15168 /* v_cmp_nlt_f64_e32 */, AMDGPU::V_CMP_NLT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17177             :   { 15186 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17178             :   { 15198 /* v_cmp_o_f16_e32 */, AMDGPU::V_CMP_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17179             :   { 15214 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17180             :   { 15214 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17181             :   { 15226 /* v_cmp_o_f32_e32 */, AMDGPU::V_CMP_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17182             :   { 15226 /* v_cmp_o_f32_e32 */, AMDGPU::V_CMP_O_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17183             :   { 15242 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17184             :   { 15242 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17185             :   { 15254 /* v_cmp_o_f64_e32 */, AMDGPU::V_CMP_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17186             :   { 15254 /* v_cmp_o_f64_e32 */, AMDGPU::V_CMP_O_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17187             :   { 15270 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17188             :   { 15282 /* v_cmp_t_i16_e32 */, AMDGPU::V_CMP_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17189             :   { 15298 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17190             :   { 15298 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17191             :   { 15310 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17192             :   { 15310 /* v_cmp_t_i32_e32 */, AMDGPU::V_CMP_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17193             :   { 15326 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17194             :   { 15326 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17195             :   { 15338 /* v_cmp_t_i64_e32 */, AMDGPU::V_CMP_T_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17196             :   { 15338 /* v_cmp_t_i64_e32 */, AMDGPU::V_CMP_T_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17197             :   { 15354 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17198             :   { 15366 /* v_cmp_t_u16_e32 */, AMDGPU::V_CMP_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17199             :   { 15382 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17200             :   { 15382 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17201             :   { 15394 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17202             :   { 15394 /* v_cmp_t_u32_e32 */, AMDGPU::V_CMP_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17203             :   { 15410 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17204             :   { 15410 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17205             :   { 15422 /* v_cmp_t_u64_e32 */, AMDGPU::V_CMP_T_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17206             :   { 15422 /* v_cmp_t_u64_e32 */, AMDGPU::V_CMP_T_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17207             :   { 15438 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17208             :   { 15452 /* v_cmp_tru_f16_e32 */, AMDGPU::V_CMP_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17209             :   { 15470 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17210             :   { 15470 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17211             :   { 15484 /* v_cmp_tru_f32_e32 */, AMDGPU::V_CMP_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17212             :   { 15484 /* v_cmp_tru_f32_e32 */, AMDGPU::V_CMP_TRU_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17213             :   { 15502 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17214             :   { 15502 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17215             :   { 15516 /* v_cmp_tru_f64_e32 */, AMDGPU::V_CMP_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17216             :   { 15516 /* v_cmp_tru_f64_e32 */, AMDGPU::V_CMP_TRU_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17217             :   { 15534 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17218             :   { 15546 /* v_cmp_u_f16_e32 */, AMDGPU::V_CMP_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17219             :   { 15562 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17220             :   { 15562 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17221             :   { 15574 /* v_cmp_u_f32_e32 */, AMDGPU::V_CMP_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17222             :   { 15574 /* v_cmp_u_f32_e32 */, AMDGPU::V_CMP_U_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17223             :   { 15590 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17224             :   { 15590 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17225             :   { 15602 /* v_cmp_u_f64_e32 */, AMDGPU::V_CMP_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17226             :   { 15602 /* v_cmp_u_f64_e32 */, AMDGPU::V_CMP_U_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17227             :   { 15618 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17228             :   { 15632 /* v_cmps_eq_f32_e32 */, AMDGPU::V_CMPS_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17229             :   { 15650 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17230             :   { 15664 /* v_cmps_eq_f64_e32 */, AMDGPU::V_CMPS_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17231             :   { 15682 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17232             :   { 15695 /* v_cmps_f_f32_e32 */, AMDGPU::V_CMPS_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17233             :   { 15712 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17234             :   { 15725 /* v_cmps_f_f64_e32 */, AMDGPU::V_CMPS_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17235             :   { 15742 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17236             :   { 15756 /* v_cmps_ge_f32_e32 */, AMDGPU::V_CMPS_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17237             :   { 15774 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17238             :   { 15788 /* v_cmps_ge_f64_e32 */, AMDGPU::V_CMPS_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17239             :   { 15806 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17240             :   { 15820 /* v_cmps_gt_f32_e32 */, AMDGPU::V_CMPS_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17241             :   { 15838 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17242             :   { 15852 /* v_cmps_gt_f64_e32 */, AMDGPU::V_CMPS_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17243             :   { 15870 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17244             :   { 15884 /* v_cmps_le_f32_e32 */, AMDGPU::V_CMPS_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17245             :   { 15902 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17246             :   { 15916 /* v_cmps_le_f64_e32 */, AMDGPU::V_CMPS_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17247             :   { 15934 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17248             :   { 15948 /* v_cmps_lg_f32_e32 */, AMDGPU::V_CMPS_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17249             :   { 15966 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17250             :   { 15980 /* v_cmps_lg_f64_e32 */, AMDGPU::V_CMPS_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17251             :   { 15998 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17252             :   { 16012 /* v_cmps_lt_f32_e32 */, AMDGPU::V_CMPS_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17253             :   { 16030 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17254             :   { 16044 /* v_cmps_lt_f64_e32 */, AMDGPU::V_CMPS_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17255             :   { 16062 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17256             :   { 16077 /* v_cmps_neq_f32_e32 */, AMDGPU::V_CMPS_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17257             :   { 16096 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17258             :   { 16111 /* v_cmps_neq_f64_e32 */, AMDGPU::V_CMPS_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17259             :   { 16130 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17260             :   { 16145 /* v_cmps_nge_f32_e32 */, AMDGPU::V_CMPS_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17261             :   { 16164 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17262             :   { 16179 /* v_cmps_nge_f64_e32 */, AMDGPU::V_CMPS_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17263             :   { 16198 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17264             :   { 16213 /* v_cmps_ngt_f32_e32 */, AMDGPU::V_CMPS_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17265             :   { 16232 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17266             :   { 16247 /* v_cmps_ngt_f64_e32 */, AMDGPU::V_CMPS_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17267             :   { 16266 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17268             :   { 16281 /* v_cmps_nle_f32_e32 */, AMDGPU::V_CMPS_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17269             :   { 16300 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17270             :   { 16315 /* v_cmps_nle_f64_e32 */, AMDGPU::V_CMPS_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17271             :   { 16334 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17272             :   { 16349 /* v_cmps_nlg_f32_e32 */, AMDGPU::V_CMPS_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17273             :   { 16368 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17274             :   { 16383 /* v_cmps_nlg_f64_e32 */, AMDGPU::V_CMPS_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17275             :   { 16402 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17276             :   { 16417 /* v_cmps_nlt_f32_e32 */, AMDGPU::V_CMPS_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17277             :   { 16436 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17278             :   { 16451 /* v_cmps_nlt_f64_e32 */, AMDGPU::V_CMPS_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17279             :   { 16470 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17280             :   { 16483 /* v_cmps_o_f32_e32 */, AMDGPU::V_CMPS_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17281             :   { 16500 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17282             :   { 16513 /* v_cmps_o_f64_e32 */, AMDGPU::V_CMPS_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17283             :   { 16530 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17284             :   { 16545 /* v_cmps_tru_f32_e32 */, AMDGPU::V_CMPS_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17285             :   { 16564 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17286             :   { 16579 /* v_cmps_tru_f64_e32 */, AMDGPU::V_CMPS_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17287             :   { 16598 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17288             :   { 16611 /* v_cmps_u_f32_e32 */, AMDGPU::V_CMPS_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17289             :   { 16628 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17290             :   { 16641 /* v_cmps_u_f64_e32 */, AMDGPU::V_CMPS_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17291             :   { 16658 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17292             :   { 16673 /* v_cmpsx_eq_f32_e32 */, AMDGPU::V_CMPSX_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17293             :   { 16692 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17294             :   { 16707 /* v_cmpsx_eq_f64_e32 */, AMDGPU::V_CMPSX_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17295             :   { 16726 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17296             :   { 16740 /* v_cmpsx_f_f32_e32 */, AMDGPU::V_CMPSX_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17297             :   { 16758 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17298             :   { 16772 /* v_cmpsx_f_f64_e32 */, AMDGPU::V_CMPSX_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17299             :   { 16790 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17300             :   { 16805 /* v_cmpsx_ge_f32_e32 */, AMDGPU::V_CMPSX_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17301             :   { 16824 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17302             :   { 16839 /* v_cmpsx_ge_f64_e32 */, AMDGPU::V_CMPSX_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17303             :   { 16858 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17304             :   { 16873 /* v_cmpsx_gt_f32_e32 */, AMDGPU::V_CMPSX_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17305             :   { 16892 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17306             :   { 16907 /* v_cmpsx_gt_f64_e32 */, AMDGPU::V_CMPSX_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17307             :   { 16926 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17308             :   { 16941 /* v_cmpsx_le_f32_e32 */, AMDGPU::V_CMPSX_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17309             :   { 16960 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17310             :   { 16975 /* v_cmpsx_le_f64_e32 */, AMDGPU::V_CMPSX_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17311             :   { 16994 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17312             :   { 17009 /* v_cmpsx_lg_f32_e32 */, AMDGPU::V_CMPSX_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17313             :   { 17028 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17314             :   { 17043 /* v_cmpsx_lg_f64_e32 */, AMDGPU::V_CMPSX_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17315             :   { 17062 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17316             :   { 17077 /* v_cmpsx_lt_f32_e32 */, AMDGPU::V_CMPSX_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17317             :   { 17096 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17318             :   { 17111 /* v_cmpsx_lt_f64_e32 */, AMDGPU::V_CMPSX_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17319             :   { 17130 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17320             :   { 17146 /* v_cmpsx_neq_f32_e32 */, AMDGPU::V_CMPSX_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17321             :   { 17166 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17322             :   { 17182 /* v_cmpsx_neq_f64_e32 */, AMDGPU::V_CMPSX_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17323             :   { 17202 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17324             :   { 17218 /* v_cmpsx_nge_f32_e32 */, AMDGPU::V_CMPSX_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17325             :   { 17238 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17326             :   { 17254 /* v_cmpsx_nge_f64_e32 */, AMDGPU::V_CMPSX_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17327             :   { 17274 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17328             :   { 17290 /* v_cmpsx_ngt_f32_e32 */, AMDGPU::V_CMPSX_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17329             :   { 17310 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17330             :   { 17326 /* v_cmpsx_ngt_f64_e32 */, AMDGPU::V_CMPSX_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17331             :   { 17346 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17332             :   { 17362 /* v_cmpsx_nle_f32_e32 */, AMDGPU::V_CMPSX_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17333             :   { 17382 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17334             :   { 17398 /* v_cmpsx_nle_f64_e32 */, AMDGPU::V_CMPSX_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17335             :   { 17418 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17336             :   { 17434 /* v_cmpsx_nlg_f32_e32 */, AMDGPU::V_CMPSX_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17337             :   { 17454 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17338             :   { 17470 /* v_cmpsx_nlg_f64_e32 */, AMDGPU::V_CMPSX_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17339             :   { 17490 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17340             :   { 17506 /* v_cmpsx_nlt_f32_e32 */, AMDGPU::V_CMPSX_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17341             :   { 17526 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17342             :   { 17542 /* v_cmpsx_nlt_f64_e32 */, AMDGPU::V_CMPSX_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17343             :   { 17562 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17344             :   { 17576 /* v_cmpsx_o_f32_e32 */, AMDGPU::V_CMPSX_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17345             :   { 17594 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17346             :   { 17608 /* v_cmpsx_o_f64_e32 */, AMDGPU::V_CMPSX_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17347             :   { 17626 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17348             :   { 17642 /* v_cmpsx_tru_f32_e32 */, AMDGPU::V_CMPSX_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17349             :   { 17662 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17350             :   { 17678 /* v_cmpsx_tru_f64_e32 */, AMDGPU::V_CMPSX_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17351             :   { 17698 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17352             :   { 17712 /* v_cmpsx_u_f32_e32 */, AMDGPU::V_CMPSX_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17353             :   { 17730 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17354             :   { 17744 /* v_cmpsx_u_f64_e32 */, AMDGPU::V_CMPSX_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17355             :   { 17762 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17356             :   { 17779 /* v_cmpx_class_f16_e32 */, AMDGPU::V_CMPX_CLASS_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17357             :   { 17800 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17358             :   { 17800 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17359             :   { 17817 /* v_cmpx_class_f32_e32 */, AMDGPU::V_CMPX_CLASS_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17360             :   { 17817 /* v_cmpx_class_f32_e32 */, AMDGPU::V_CMPX_CLASS_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17361             :   { 17838 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   17362             :   { 17838 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   17363             :   { 17855 /* v_cmpx_class_f64_e32 */, AMDGPU::V_CMPX_CLASS_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   17364             :   { 17855 /* v_cmpx_class_f64_e32 */, AMDGPU::V_CMPX_CLASS_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VGPR_32 }, },
   17365             :   { 17876 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17366             :   { 17890 /* v_cmpx_eq_f16_e32 */, AMDGPU::V_CMPX_EQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17367             :   { 17908 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17368             :   { 17908 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17369             :   { 17922 /* v_cmpx_eq_f32_e32 */, AMDGPU::V_CMPX_EQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17370             :   { 17922 /* v_cmpx_eq_f32_e32 */, AMDGPU::V_CMPX_EQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17371             :   { 17940 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17372             :   { 17940 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17373             :   { 17954 /* v_cmpx_eq_f64_e32 */, AMDGPU::V_CMPX_EQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17374             :   { 17954 /* v_cmpx_eq_f64_e32 */, AMDGPU::V_CMPX_EQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17375             :   { 17972 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17376             :   { 17986 /* v_cmpx_eq_i16_e32 */, AMDGPU::V_CMPX_EQ_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17377             :   { 18004 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17378             :   { 18004 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17379             :   { 18018 /* v_cmpx_eq_i32_e32 */, AMDGPU::V_CMPX_EQ_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17380             :   { 18018 /* v_cmpx_eq_i32_e32 */, AMDGPU::V_CMPX_EQ_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17381             :   { 18036 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17382             :   { 18036 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17383             :   { 18050 /* v_cmpx_eq_i64_e32 */, AMDGPU::V_CMPX_EQ_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17384             :   { 18050 /* v_cmpx_eq_i64_e32 */, AMDGPU::V_CMPX_EQ_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17385             :   { 18068 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17386             :   { 18082 /* v_cmpx_eq_u16_e32 */, AMDGPU::V_CMPX_EQ_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17387             :   { 18100 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17388             :   { 18100 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17389             :   { 18114 /* v_cmpx_eq_u32_e32 */, AMDGPU::V_CMPX_EQ_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17390             :   { 18114 /* v_cmpx_eq_u32_e32 */, AMDGPU::V_CMPX_EQ_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17391             :   { 18132 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17392             :   { 18132 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17393             :   { 18146 /* v_cmpx_eq_u64_e32 */, AMDGPU::V_CMPX_EQ_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17394             :   { 18146 /* v_cmpx_eq_u64_e32 */, AMDGPU::V_CMPX_EQ_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17395             :   { 18164 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17396             :   { 18177 /* v_cmpx_f_f16_e32 */, AMDGPU::V_CMPX_F_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17397             :   { 18194 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17398             :   { 18194 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17399             :   { 18207 /* v_cmpx_f_f32_e32 */, AMDGPU::V_CMPX_F_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17400             :   { 18207 /* v_cmpx_f_f32_e32 */, AMDGPU::V_CMPX_F_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17401             :   { 18224 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17402             :   { 18224 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17403             :   { 18237 /* v_cmpx_f_f64_e32 */, AMDGPU::V_CMPX_F_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17404             :   { 18237 /* v_cmpx_f_f64_e32 */, AMDGPU::V_CMPX_F_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17405             :   { 18254 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17406             :   { 18267 /* v_cmpx_f_i16_e32 */, AMDGPU::V_CMPX_F_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17407             :   { 18284 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17408             :   { 18284 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17409             :   { 18297 /* v_cmpx_f_i32_e32 */, AMDGPU::V_CMPX_F_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17410             :   { 18297 /* v_cmpx_f_i32_e32 */, AMDGPU::V_CMPX_F_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17411             :   { 18314 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17412             :   { 18314 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17413             :   { 18327 /* v_cmpx_f_i64_e32 */, AMDGPU::V_CMPX_F_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17414             :   { 18327 /* v_cmpx_f_i64_e32 */, AMDGPU::V_CMPX_F_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17415             :   { 18344 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17416             :   { 18357 /* v_cmpx_f_u16_e32 */, AMDGPU::V_CMPX_F_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17417             :   { 18374 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17418             :   { 18374 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17419             :   { 18387 /* v_cmpx_f_u32_e32 */, AMDGPU::V_CMPX_F_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17420             :   { 18387 /* v_cmpx_f_u32_e32 */, AMDGPU::V_CMPX_F_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17421             :   { 18404 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17422             :   { 18404 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17423             :   { 18417 /* v_cmpx_f_u64_e32 */, AMDGPU::V_CMPX_F_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17424             :   { 18417 /* v_cmpx_f_u64_e32 */, AMDGPU::V_CMPX_F_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17425             :   { 18434 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17426             :   { 18448 /* v_cmpx_ge_f16_e32 */, AMDGPU::V_CMPX_GE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17427             :   { 18466 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17428             :   { 18466 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17429             :   { 18480 /* v_cmpx_ge_f32_e32 */, AMDGPU::V_CMPX_GE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17430             :   { 18480 /* v_cmpx_ge_f32_e32 */, AMDGPU::V_CMPX_GE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17431             :   { 18498 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17432             :   { 18498 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17433             :   { 18512 /* v_cmpx_ge_f64_e32 */, AMDGPU::V_CMPX_GE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17434             :   { 18512 /* v_cmpx_ge_f64_e32 */, AMDGPU::V_CMPX_GE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17435             :   { 18530 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17436             :   { 18544 /* v_cmpx_ge_i16_e32 */, AMDGPU::V_CMPX_GE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17437             :   { 18562 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17438             :   { 18562 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17439             :   { 18576 /* v_cmpx_ge_i32_e32 */, AMDGPU::V_CMPX_GE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17440             :   { 18576 /* v_cmpx_ge_i32_e32 */, AMDGPU::V_CMPX_GE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17441             :   { 18594 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17442             :   { 18594 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17443             :   { 18608 /* v_cmpx_ge_i64_e32 */, AMDGPU::V_CMPX_GE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17444             :   { 18608 /* v_cmpx_ge_i64_e32 */, AMDGPU::V_CMPX_GE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17445             :   { 18626 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17446             :   { 18640 /* v_cmpx_ge_u16_e32 */, AMDGPU::V_CMPX_GE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17447             :   { 18658 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17448             :   { 18658 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17449             :   { 18672 /* v_cmpx_ge_u32_e32 */, AMDGPU::V_CMPX_GE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17450             :   { 18672 /* v_cmpx_ge_u32_e32 */, AMDGPU::V_CMPX_GE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17451             :   { 18690 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17452             :   { 18690 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17453             :   { 18704 /* v_cmpx_ge_u64_e32 */, AMDGPU::V_CMPX_GE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17454             :   { 18704 /* v_cmpx_ge_u64_e32 */, AMDGPU::V_CMPX_GE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17455             :   { 18722 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17456             :   { 18736 /* v_cmpx_gt_f16_e32 */, AMDGPU::V_CMPX_GT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17457             :   { 18754 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17458             :   { 18754 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17459             :   { 18768 /* v_cmpx_gt_f32_e32 */, AMDGPU::V_CMPX_GT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17460             :   { 18768 /* v_cmpx_gt_f32_e32 */, AMDGPU::V_CMPX_GT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17461             :   { 18786 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17462             :   { 18786 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17463             :   { 18800 /* v_cmpx_gt_f64_e32 */, AMDGPU::V_CMPX_GT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17464             :   { 18800 /* v_cmpx_gt_f64_e32 */, AMDGPU::V_CMPX_GT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17465             :   { 18818 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17466             :   { 18832 /* v_cmpx_gt_i16_e32 */, AMDGPU::V_CMPX_GT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17467             :   { 18850 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17468             :   { 18850 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17469             :   { 18864 /* v_cmpx_gt_i32_e32 */, AMDGPU::V_CMPX_GT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17470             :   { 18864 /* v_cmpx_gt_i32_e32 */, AMDGPU::V_CMPX_GT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17471             :   { 18882 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17472             :   { 18882 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17473             :   { 18896 /* v_cmpx_gt_i64_e32 */, AMDGPU::V_CMPX_GT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17474             :   { 18896 /* v_cmpx_gt_i64_e32 */, AMDGPU::V_CMPX_GT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17475             :   { 18914 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17476             :   { 18928 /* v_cmpx_gt_u16_e32 */, AMDGPU::V_CMPX_GT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17477             :   { 18946 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17478             :   { 18946 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17479             :   { 18960 /* v_cmpx_gt_u32_e32 */, AMDGPU::V_CMPX_GT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17480             :   { 18960 /* v_cmpx_gt_u32_e32 */, AMDGPU::V_CMPX_GT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17481             :   { 18978 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17482             :   { 18978 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17483             :   { 18992 /* v_cmpx_gt_u64_e32 */, AMDGPU::V_CMPX_GT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17484             :   { 18992 /* v_cmpx_gt_u64_e32 */, AMDGPU::V_CMPX_GT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17485             :   { 19010 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17486             :   { 19024 /* v_cmpx_le_f16_e32 */, AMDGPU::V_CMPX_LE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17487             :   { 19042 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17488             :   { 19042 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17489             :   { 19056 /* v_cmpx_le_f32_e32 */, AMDGPU::V_CMPX_LE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17490             :   { 19056 /* v_cmpx_le_f32_e32 */, AMDGPU::V_CMPX_LE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17491             :   { 19074 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17492             :   { 19074 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17493             :   { 19088 /* v_cmpx_le_f64_e32 */, AMDGPU::V_CMPX_LE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17494             :   { 19088 /* v_cmpx_le_f64_e32 */, AMDGPU::V_CMPX_LE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17495             :   { 19106 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17496             :   { 19120 /* v_cmpx_le_i16_e32 */, AMDGPU::V_CMPX_LE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17497             :   { 19138 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17498             :   { 19138 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17499             :   { 19152 /* v_cmpx_le_i32_e32 */, AMDGPU::V_CMPX_LE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17500             :   { 19152 /* v_cmpx_le_i32_e32 */, AMDGPU::V_CMPX_LE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17501             :   { 19170 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17502             :   { 19170 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17503             :   { 19184 /* v_cmpx_le_i64_e32 */, AMDGPU::V_CMPX_LE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17504             :   { 19184 /* v_cmpx_le_i64_e32 */, AMDGPU::V_CMPX_LE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17505             :   { 19202 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17506             :   { 19216 /* v_cmpx_le_u16_e32 */, AMDGPU::V_CMPX_LE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17507             :   { 19234 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17508             :   { 19234 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17509             :   { 19248 /* v_cmpx_le_u32_e32 */, AMDGPU::V_CMPX_LE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17510             :   { 19248 /* v_cmpx_le_u32_e32 */, AMDGPU::V_CMPX_LE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17511             :   { 19266 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17512             :   { 19266 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17513             :   { 19280 /* v_cmpx_le_u64_e32 */, AMDGPU::V_CMPX_LE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17514             :   { 19280 /* v_cmpx_le_u64_e32 */, AMDGPU::V_CMPX_LE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17515             :   { 19298 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17516             :   { 19312 /* v_cmpx_lg_f16_e32 */, AMDGPU::V_CMPX_LG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17517             :   { 19330 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17518             :   { 19330 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17519             :   { 19344 /* v_cmpx_lg_f32_e32 */, AMDGPU::V_CMPX_LG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17520             :   { 19344 /* v_cmpx_lg_f32_e32 */, AMDGPU::V_CMPX_LG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17521             :   { 19362 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17522             :   { 19362 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17523             :   { 19376 /* v_cmpx_lg_f64_e32 */, AMDGPU::V_CMPX_LG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17524             :   { 19376 /* v_cmpx_lg_f64_e32 */, AMDGPU::V_CMPX_LG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17525             :   { 19394 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17526             :   { 19408 /* v_cmpx_lt_f16_e32 */, AMDGPU::V_CMPX_LT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17527             :   { 19426 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17528             :   { 19426 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17529             :   { 19440 /* v_cmpx_lt_f32_e32 */, AMDGPU::V_CMPX_LT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17530             :   { 19440 /* v_cmpx_lt_f32_e32 */, AMDGPU::V_CMPX_LT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17531             :   { 19458 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17532             :   { 19458 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17533             :   { 19472 /* v_cmpx_lt_f64_e32 */, AMDGPU::V_CMPX_LT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17534             :   { 19472 /* v_cmpx_lt_f64_e32 */, AMDGPU::V_CMPX_LT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17535             :   { 19490 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17536             :   { 19504 /* v_cmpx_lt_i16_e32 */, AMDGPU::V_CMPX_LT_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17537             :   { 19522 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17538             :   { 19522 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17539             :   { 19536 /* v_cmpx_lt_i32_e32 */, AMDGPU::V_CMPX_LT_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17540             :   { 19536 /* v_cmpx_lt_i32_e32 */, AMDGPU::V_CMPX_LT_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17541             :   { 19554 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17542             :   { 19554 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17543             :   { 19568 /* v_cmpx_lt_i64_e32 */, AMDGPU::V_CMPX_LT_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17544             :   { 19568 /* v_cmpx_lt_i64_e32 */, AMDGPU::V_CMPX_LT_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17545             :   { 19586 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17546             :   { 19600 /* v_cmpx_lt_u16_e32 */, AMDGPU::V_CMPX_LT_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17547             :   { 19618 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17548             :   { 19618 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17549             :   { 19632 /* v_cmpx_lt_u32_e32 */, AMDGPU::V_CMPX_LT_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17550             :   { 19632 /* v_cmpx_lt_u32_e32 */, AMDGPU::V_CMPX_LT_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17551             :   { 19650 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17552             :   { 19650 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17553             :   { 19664 /* v_cmpx_lt_u64_e32 */, AMDGPU::V_CMPX_LT_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17554             :   { 19664 /* v_cmpx_lt_u64_e32 */, AMDGPU::V_CMPX_LT_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17555             :   { 19682 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17556             :   { 19696 /* v_cmpx_ne_i16_e32 */, AMDGPU::V_CMPX_NE_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17557             :   { 19714 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17558             :   { 19714 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17559             :   { 19728 /* v_cmpx_ne_i32_e32 */, AMDGPU::V_CMPX_NE_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17560             :   { 19728 /* v_cmpx_ne_i32_e32 */, AMDGPU::V_CMPX_NE_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17561             :   { 19746 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17562             :   { 19746 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17563             :   { 19760 /* v_cmpx_ne_i64_e32 */, AMDGPU::V_CMPX_NE_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17564             :   { 19760 /* v_cmpx_ne_i64_e32 */, AMDGPU::V_CMPX_NE_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17565             :   { 19778 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17566             :   { 19792 /* v_cmpx_ne_u16_e32 */, AMDGPU::V_CMPX_NE_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17567             :   { 19810 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17568             :   { 19810 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17569             :   { 19824 /* v_cmpx_ne_u32_e32 */, AMDGPU::V_CMPX_NE_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17570             :   { 19824 /* v_cmpx_ne_u32_e32 */, AMDGPU::V_CMPX_NE_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17571             :   { 19842 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17572             :   { 19842 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17573             :   { 19856 /* v_cmpx_ne_u64_e32 */, AMDGPU::V_CMPX_NE_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17574             :   { 19856 /* v_cmpx_ne_u64_e32 */, AMDGPU::V_CMPX_NE_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17575             :   { 19874 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17576             :   { 19889 /* v_cmpx_neq_f16_e32 */, AMDGPU::V_CMPX_NEQ_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17577             :   { 19908 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17578             :   { 19908 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17579             :   { 19923 /* v_cmpx_neq_f32_e32 */, AMDGPU::V_CMPX_NEQ_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17580             :   { 19923 /* v_cmpx_neq_f32_e32 */, AMDGPU::V_CMPX_NEQ_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17581             :   { 19942 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17582             :   { 19942 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17583             :   { 19957 /* v_cmpx_neq_f64_e32 */, AMDGPU::V_CMPX_NEQ_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17584             :   { 19957 /* v_cmpx_neq_f64_e32 */, AMDGPU::V_CMPX_NEQ_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17585             :   { 19976 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17586             :   { 19991 /* v_cmpx_nge_f16_e32 */, AMDGPU::V_CMPX_NGE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17587             :   { 20010 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17588             :   { 20010 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17589             :   { 20025 /* v_cmpx_nge_f32_e32 */, AMDGPU::V_CMPX_NGE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17590             :   { 20025 /* v_cmpx_nge_f32_e32 */, AMDGPU::V_CMPX_NGE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17591             :   { 20044 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17592             :   { 20044 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17593             :   { 20059 /* v_cmpx_nge_f64_e32 */, AMDGPU::V_CMPX_NGE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17594             :   { 20059 /* v_cmpx_nge_f64_e32 */, AMDGPU::V_CMPX_NGE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17595             :   { 20078 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17596             :   { 20093 /* v_cmpx_ngt_f16_e32 */, AMDGPU::V_CMPX_NGT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17597             :   { 20112 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17598             :   { 20112 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17599             :   { 20127 /* v_cmpx_ngt_f32_e32 */, AMDGPU::V_CMPX_NGT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17600             :   { 20127 /* v_cmpx_ngt_f32_e32 */, AMDGPU::V_CMPX_NGT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17601             :   { 20146 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17602             :   { 20146 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17603             :   { 20161 /* v_cmpx_ngt_f64_e32 */, AMDGPU::V_CMPX_NGT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17604             :   { 20161 /* v_cmpx_ngt_f64_e32 */, AMDGPU::V_CMPX_NGT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17605             :   { 20180 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17606             :   { 20195 /* v_cmpx_nle_f16_e32 */, AMDGPU::V_CMPX_NLE_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17607             :   { 20214 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17608             :   { 20214 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17609             :   { 20229 /* v_cmpx_nle_f32_e32 */, AMDGPU::V_CMPX_NLE_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17610             :   { 20229 /* v_cmpx_nle_f32_e32 */, AMDGPU::V_CMPX_NLE_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17611             :   { 20248 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17612             :   { 20248 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17613             :   { 20263 /* v_cmpx_nle_f64_e32 */, AMDGPU::V_CMPX_NLE_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17614             :   { 20263 /* v_cmpx_nle_f64_e32 */, AMDGPU::V_CMPX_NLE_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17615             :   { 20282 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17616             :   { 20297 /* v_cmpx_nlg_f16_e32 */, AMDGPU::V_CMPX_NLG_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17617             :   { 20316 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17618             :   { 20316 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17619             :   { 20331 /* v_cmpx_nlg_f32_e32 */, AMDGPU::V_CMPX_NLG_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17620             :   { 20331 /* v_cmpx_nlg_f32_e32 */, AMDGPU::V_CMPX_NLG_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17621             :   { 20350 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17622             :   { 20350 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17623             :   { 20365 /* v_cmpx_nlg_f64_e32 */, AMDGPU::V_CMPX_NLG_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17624             :   { 20365 /* v_cmpx_nlg_f64_e32 */, AMDGPU::V_CMPX_NLG_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17625             :   { 20384 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17626             :   { 20399 /* v_cmpx_nlt_f16_e32 */, AMDGPU::V_CMPX_NLT_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17627             :   { 20418 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17628             :   { 20418 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17629             :   { 20433 /* v_cmpx_nlt_f32_e32 */, AMDGPU::V_CMPX_NLT_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17630             :   { 20433 /* v_cmpx_nlt_f32_e32 */, AMDGPU::V_CMPX_NLT_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17631             :   { 20452 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17632             :   { 20452 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17633             :   { 20467 /* v_cmpx_nlt_f64_e32 */, AMDGPU::V_CMPX_NLT_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17634             :   { 20467 /* v_cmpx_nlt_f64_e32 */, AMDGPU::V_CMPX_NLT_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17635             :   { 20486 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17636             :   { 20499 /* v_cmpx_o_f16_e32 */, AMDGPU::V_CMPX_O_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17637             :   { 20516 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17638             :   { 20516 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17639             :   { 20529 /* v_cmpx_o_f32_e32 */, AMDGPU::V_CMPX_O_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17640             :   { 20529 /* v_cmpx_o_f32_e32 */, AMDGPU::V_CMPX_O_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17641             :   { 20546 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17642             :   { 20546 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17643             :   { 20559 /* v_cmpx_o_f64_e32 */, AMDGPU::V_CMPX_O_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17644             :   { 20559 /* v_cmpx_o_f64_e32 */, AMDGPU::V_CMPX_O_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17645             :   { 20576 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17646             :   { 20589 /* v_cmpx_t_i16_e32 */, AMDGPU::V_CMPX_T_I16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17647             :   { 20606 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17648             :   { 20606 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17649             :   { 20619 /* v_cmpx_t_i32_e32 */, AMDGPU::V_CMPX_T_I32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17650             :   { 20619 /* v_cmpx_t_i32_e32 */, AMDGPU::V_CMPX_T_I32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17651             :   { 20636 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17652             :   { 20636 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17653             :   { 20649 /* v_cmpx_t_i64_e32 */, AMDGPU::V_CMPX_T_I64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17654             :   { 20649 /* v_cmpx_t_i64_e32 */, AMDGPU::V_CMPX_T_I64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17655             :   { 20666 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17656             :   { 20679 /* v_cmpx_t_u16_e32 */, AMDGPU::V_CMPX_T_U16_e32_vi, Convert__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcB16, MCK_VGPR_32 }, },
   17657             :   { 20696 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17658             :   { 20696 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17659             :   { 20709 /* v_cmpx_t_u32_e32 */, AMDGPU::V_CMPX_T_U32_e32_si, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17660             :   { 20709 /* v_cmpx_t_u32_e32 */, AMDGPU::V_CMPX_T_U32_e32_vi, Convert__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17661             :   { 20726 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17662             :   { 20726 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17663             :   { 20739 /* v_cmpx_t_u64_e32 */, AMDGPU::V_CMPX_T_U64_e32_si, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17664             :   { 20739 /* v_cmpx_t_u64_e32 */, AMDGPU::V_CMPX_T_U64_e32_vi, Convert__VSrcB641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcB64, MCK_VReg_64 }, },
   17665             :   { 20756 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17666             :   { 20771 /* v_cmpx_tru_f16_e32 */, AMDGPU::V_CMPX_TRU_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17667             :   { 20790 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17668             :   { 20790 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17669             :   { 20805 /* v_cmpx_tru_f32_e32 */, AMDGPU::V_CMPX_TRU_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17670             :   { 20805 /* v_cmpx_tru_f32_e32 */, AMDGPU::V_CMPX_TRU_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17671             :   { 20824 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17672             :   { 20824 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17673             :   { 20839 /* v_cmpx_tru_f64_e32 */, AMDGPU::V_CMPX_TRU_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17674             :   { 20839 /* v_cmpx_tru_f64_e32 */, AMDGPU::V_CMPX_TRU_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17675             :   { 20858 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17676             :   { 20871 /* v_cmpx_u_f16_e32 */, AMDGPU::V_CMPX_U_F16_e32_vi, Convert__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VCC, MCK_VSrcF16, MCK_VGPR_32 }, },
   17677             :   { 20888 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17678             :   { 20888 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17679             :   { 20901 /* v_cmpx_u_f32_e32 */, AMDGPU::V_CMPX_U_F32_e32_si, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17680             :   { 20901 /* v_cmpx_u_f32_e32 */, AMDGPU::V_CMPX_U_F32_e32_vi, Convert__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF32, MCK_VGPR_32 }, },
   17681             :   { 20918 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17682             :   { 20918 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isVI|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17683             :   { 20931 /* v_cmpx_u_f64_e32 */, AMDGPU::V_CMPX_U_F64_e32_si, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17684             :   { 20931 /* v_cmpx_u_f64_e32 */, AMDGPU::V_CMPX_U_F64_e32_vi, Convert__VSrcF641_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VCC, MCK_VSrcF64, MCK_VReg_64 }, },
   17685             :   { 20948 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_si, Convert__Reg1_0__VCSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17686             :   { 20948 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e32_vi, Convert__Reg1_0__VCSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17687             :   { 20962 /* v_cos_f16 */, AMDGPU::V_COS_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17688             :   { 20972 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17689             :   { 20972 /* v_cos_f32 */, AMDGPU::V_COS_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17690             :   { 21034 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17691             :   { 21034 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17692             :   { 21048 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e32_vi, Convert__Reg1_0__VSrcB161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16 }, },
   17693             :   { 21062 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e32_vi, Convert__Reg1_0__VSrcB161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16 }, },
   17694             :   { 21076 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_si, Convert__Reg1_0__VSrcF161_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17695             :   { 21076 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17696             :   { 21090 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17697             :   { 21090 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17698             :   { 21104 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17699             :   { 21104 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17700             :   { 21118 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17701             :   { 21118 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17702             :   { 21132 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17703             :   { 21132 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17704             :   { 21149 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17705             :   { 21149 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17706             :   { 21166 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17707             :   { 21166 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17708             :   { 21183 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17709             :   { 21183 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17710             :   { 21200 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF32 }, },
   17711             :   { 21200 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcF32 }, },
   17712             :   { 21214 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcB32 }, },
   17713             :   { 21214 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcB32 }, },
   17714             :   { 21228 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcB32 }, },
   17715             :   { 21228 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcB32 }, },
   17716             :   { 21242 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17717             :   { 21242 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17718             :   { 21260 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17719             :   { 21274 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17720             :   { 21274 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17721             :   { 21288 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17722             :   { 21288 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17723             :   { 21302 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17724             :   { 21321 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17725             :   { 21340 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17726             :   { 21340 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17727             :   { 21357 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17728             :   { 21374 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17729             :   { 21407 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17730             :   { 21449 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17731             :   { 21491 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17732             :   { 21512 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17733             :   { 21532 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17734             :   { 21532 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17735             :   { 21550 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17736             :   { 21564 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17737             :   { 21564 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17738             :   { 21578 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17739             :   { 21578 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17740             :   { 21826 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17741             :   { 21836 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17742             :   { 21836 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17743             :   { 21846 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e32_ci, Convert__Reg1_0__VSrcF321_1, Feature_isCIVI|Feature_isCIOnly, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17744             :   { 21846 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17745             :   { 21863 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17746             :   { 21863 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17747             :   { 21874 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17748             :   { 21874 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17749             :   { 21885 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17750             :   { 21885 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17751             :   { 21896 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17752             :   { 21908 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17753             :   { 21908 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17754             :   { 21920 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_ci, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_VSrcF64 }, },
   17755             :   { 21920 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17756             :   { 22025 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1, Feature_HasDLInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17757             :   { 22036 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17758             :   { 22048 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17759             :   { 22048 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17760             :   { 22060 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17761             :   { 22060 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17762             :   { 22072 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17763             :   { 22092 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17764             :   { 22092 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17765             :   { 22112 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17766             :   { 22112 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF64 }, },
   17767             :   { 22132 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17768             :   { 22149 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17769             :   { 22149 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17770             :   { 22166 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17771             :   { 22166 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17772             :   { 22183 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_si, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
   17773             :   { 22183 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_vi, Convert__Reg1_0__InterpSlot1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan }, },
   17774             :   { 22200 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_si, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
   17775             :   { 22200 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_16bank_vi, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
   17776             :   { 22200 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_si, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
   17777             :   { 22200 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_vi, Convert__Reg1_0__Reg1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
   17778             :   { 22268 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_si, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
   17779             :   { 22268 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Attr1_2__AttrChan1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32, MCK_Attr, MCK_AttrChan }, },
   17780             :   { 22307 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   17781             :   { 22319 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17782             :   { 22353 /* v_log_clamp_f32 */, AMDGPU::V_LOG_CLAMP_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17783             :   { 22369 /* v_log_f16 */, AMDGPU::V_LOG_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17784             :   { 22379 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17785             :   { 22379 /* v_log_f32 */, AMDGPU::V_LOG_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17786             :   { 22389 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e32_ci, Convert__Reg1_0__VSrcF321_1, Feature_isCIVI|Feature_isCIOnly, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17787             :   { 22389 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17788             :   { 22421 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17789             :   { 22457 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17790             :   { 22471 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17791             :   { 22471 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17792             :   { 22499 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17793             :   { 22521 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17794             :   { 22535 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17795             :   { 22535 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17796             :   { 22563 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2__Tie0_1_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   17797             :   { 22573 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17798             :   { 22573 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2__Tie0_1_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17799             :   { 22583 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17800             :   { 22838 /* v_madak_f16 */, AMDGPU::V_MADAK_F16_vi, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP161_3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP16 }, },
   17801             :   { 22850 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_si, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, },
   17802             :   { 22850 /* v_madak_f32 */, AMDGPU::V_MADAK_F32_vi, Convert__Reg1_0__VCSrcF321_1__Reg1_2__KImmFP321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VGPR_32, MCK_KImmFP32 }, },
   17803             :   { 22862 /* v_madmk_f16 */, AMDGPU::V_MADMK_F16_vi, Convert__Reg1_0__VCSrcF321_1__KImmFP161_2__Reg1_3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP16, MCK_VGPR_32 }, },
   17804             :   { 22874 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_si, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, },
   17805             :   { 22874 /* v_madmk_f32 */, AMDGPU::V_MADMK_F32_vi, Convert__Reg1_0__VCSrcF321_1__KImmFP321_2__Reg1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_KImmFP32, MCK_VGPR_32 }, },
   17806             :   { 22952 /* v_max_f16 */, AMDGPU::V_MAX_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   17807             :   { 22962 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17808             :   { 22962 /* v_max_f32 */, AMDGPU::V_MAX_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17809             :   { 22982 /* v_max_i16 */, AMDGPU::V_MAX_I16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17810             :   { 22992 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17811             :   { 22992 /* v_max_i32 */, AMDGPU::V_MAX_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17812             :   { 23002 /* v_max_legacy_f32 */, AMDGPU::V_MAX_LEGACY_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17813             :   { 23019 /* v_max_u16 */, AMDGPU::V_MAX_U16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17814             :   { 23029 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17815             :   { 23029 /* v_max_u32 */, AMDGPU::V_MAX_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17816             :   { 23039 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17817             :   { 23058 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17818             :   { 23209 /* v_min_f16 */, AMDGPU::V_MIN_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   17819             :   { 23219 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17820             :   { 23219 /* v_min_f32 */, AMDGPU::V_MIN_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17821             :   { 23239 /* v_min_i16 */, AMDGPU::V_MIN_I16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17822             :   { 23249 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17823             :   { 23249 /* v_min_i32 */, AMDGPU::V_MIN_I32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17824             :   { 23259 /* v_min_legacy_f32 */, AMDGPU::V_MIN_LEGACY_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17825             :   { 23276 /* v_min_u16 */, AMDGPU::V_MIN_U16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17826             :   { 23286 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17827             :   { 23286 /* v_min_u32 */, AMDGPU::V_MIN_U32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17828             :   { 23296 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17829             :   { 23296 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17830             :   { 23306 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17831             :   { 23306 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17832             :   { 23320 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_HasMovrel|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17833             :   { 23320 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_HasMovrel|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17834             :   { 23334 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e32_si, Convert__Reg1_0__Reg1_1, Feature_HasMovrel|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32 }, },
   17835             :   { 23334 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e32_vi, Convert__Reg1_0__Reg1_1, Feature_HasMovrel|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32 }, },
   17836             :   { 23348 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_HasMovrel|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17837             :   { 23348 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_HasMovrel|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17838             :   { 23406 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   17839             :   { 23416 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17840             :   { 23416 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17841             :   { 23449 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17842             :   { 23449 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17843             :   { 23479 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17844             :   { 23479 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17845             :   { 23496 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17846             :   { 23496 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17847             :   { 23510 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17848             :   { 23510 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17849             :   { 23540 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17850             :   { 23566 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17851             :   { 23566 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17852             :   { 23593 /* v_nop */, AMDGPU::V_NOP_e32_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, {  }, },
   17853             :   { 23593 /* v_nop */, AMDGPU::V_NOP_e32_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, {  }, },
   17854             :   { 23599 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_si, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17855             :   { 23599 /* v_not_b32 */, AMDGPU::V_NOT_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17856             :   { 23619 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17857             :   { 23619 /* v_or_b32 */, AMDGPU::V_OR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17858             :   { 23933 /* v_rcp_clamp_f32 */, AMDGPU::V_RCP_CLAMP_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17859             :   { 23949 /* v_rcp_clamp_f64 */, AMDGPU::V_RCP_CLAMP_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17860             :   { 23965 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17861             :   { 23975 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17862             :   { 23975 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17863             :   { 23985 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17864             :   { 23985 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17865             :   { 23995 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17866             :   { 23995 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17867             :   { 24011 /* v_rcp_legacy_f32 */, AMDGPU::V_RCP_LEGACY_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17868             :   { 24028 /* v_readfirstlane_b32 */, AMDGPU::V_READFIRSTLANE_B32, Convert__Reg1_0__Reg1_1, Feature_isGCN, { MCK_SReg_32, MCK_VGPR_32 }, },
   17869             :   { 24048 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_si, Convert__Reg1_0__Reg1_1__SCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_32, MCK_VGPR_32, MCK_SCSrcB32 }, },
   17870             :   { 24048 /* v_readlane_b32 */, AMDGPU::V_READLANE_B32_vi, Convert__Reg1_0__Reg1_1__SCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_32, MCK_VGPR_32, MCK_SCSrcB32 }, },
   17871             :   { 24063 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17872             :   { 24075 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17873             :   { 24075 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17874             :   { 24087 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_ci, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_VSrcF64 }, },
   17875             :   { 24087 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17876             :   { 24099 /* v_rsq_clamp_f32 */, AMDGPU::V_RSQ_CLAMP_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17877             :   { 24115 /* v_rsq_clamp_f64 */, AMDGPU::V_RSQ_CLAMP_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17878             :   { 24131 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17879             :   { 24141 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17880             :   { 24141 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17881             :   { 24151 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17882             :   { 24151 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17883             :   { 24161 /* v_rsq_legacy_f32 */, AMDGPU::V_RSQ_LEGACY_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17884             :   { 24219 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17885             :   { 24235 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_e32_vi, Convert__Reg1_0__VSrcB321_1, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_VSrcB32 }, },
   17886             :   { 24262 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17887             :   { 24272 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17888             :   { 24272 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17889             :   { 24282 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17890             :   { 24293 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17891             :   { 24293 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17892             :   { 24304 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_si, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17893             :   { 24304 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17894             :   { 24315 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17895             :   { 24328 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   17896             :   { 24338 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17897             :   { 24338 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17898             :   { 24358 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e32_si, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17899             :   { 24368 /* v_sub_u16 */, AMDGPU::V_SUB_U16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17900             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_HasAddNoCarryInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17901             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17902             :   { 24388 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e32_gfx9, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17903             :   { 24402 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_si, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17904             :   { 24402 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e32_vi, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17905             :   { 24413 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17906             :   { 24430 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_si, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17907             :   { 24430 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e32_vi, Convert__Reg1_0__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VCSrcB32, MCK_VGPR_32, MCK_VCC }, },
   17908             :   { 24444 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17909             :   { 24460 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e32_vi, Convert__Reg1_0__VSrcF161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16, MCK_VGPR_32 }, },
   17910             :   { 24473 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_si, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17911             :   { 24473 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e32_vi, Convert__Reg1_0__VSrcF321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32, MCK_VGPR_32 }, },
   17912             :   { 24486 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e32_si, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17913             :   { 24499 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_e32_vi, Convert__Reg1_0__VSrcB161_1__Reg1_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB16, MCK_VGPR_32 }, },
   17914             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e32_gfx9, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_HasAddNoCarryInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17915             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e32_vi, Convert__Reg1_0__VSrcB321_2__Reg1_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VSrcB32, MCK_VGPR_32 }, },
   17916             :   { 24525 /* v_swap_b32 */, AMDGPU::V_SWAP_B32_vi, Convert__Reg1_0__Reg1_1__Tie1_2_2__Tie0_1_1, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32 }, },
   17917             :   { 24553 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e32_vi, Convert__Reg1_0__VSrcF161_1, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF16 }, },
   17918             :   { 24565 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_si, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17919             :   { 24565 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e32_vi, Convert__Reg1_0__VSrcF321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcF32 }, },
   17920             :   { 24577 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_ci, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_VSrcF64 }, },
   17921             :   { 24577 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e32_vi, Convert__Reg1_0__VSrcF641_1, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VSrcF64 }, },
   17922             :   { 24589 /* v_writelane_b32 */, AMDGPU::V_WRITELANE_B32_si, Convert__Reg1_0__SSrcB321_1__SCSrcB321_2__Tie0_1_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SSrcB32, MCK_SCSrcB32 }, },
   17923             :   { 24589 /* v_writelane_b32 */, AMDGPU::V_WRITELANE_B32_vi, Convert__Reg1_0__SCSrcB321_1__SCSrcB321_2__Tie0_1_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_SCSrcB32, MCK_SCSrcB32 }, },
   17924             :   { 24615 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_HasDLInsts|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17925             :   { 24626 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_si, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17926             :   { 24626 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e32_vi, Convert__Reg1_0__VSrcB321_1__Reg1_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32, MCK_VGPR_32 }, },
   17927             : };
   17928             : 
   17929             : static const MatchEntry MatchTable1[] = {
   17930             :   { 12268 /* v_add3_u32 */, AMDGPU::V_ADD3_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17931             :   { 12279 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_e64_gfx9, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17932             :   { 12292 /* v_add_f16 */, AMDGPU::V_ADD_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17933             :   { 12302 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17934             :   { 12302 /* v_add_f32 */, AMDGPU::V_ADD_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17935             :   { 12312 /* v_add_f64 */, AMDGPU::V_ADD_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17936             :   { 12312 /* v_add_f64 */, AMDGPU::V_ADD_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17937             :   { 12322 /* v_add_i16 */, AMDGPU::V_ADD_I16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   17938             :   { 12332 /* v_add_i32 */, AMDGPU::V_ADD_I32_gfx9_gfx9, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17939             :   { 12332 /* v_add_i32 */, AMDGPU::V_ADD_I32_e64_si, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17940             :   { 12342 /* v_add_lshl_u32 */, AMDGPU::V_ADD_LSHL_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17941             :   { 12357 /* v_add_u16 */, AMDGPU::V_ADD_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   17942             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_gfx9, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_HasAddNoCarryInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17943             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_e64_vi, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17944             :   { 12377 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_e64_gfx9, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   17945             :   { 12391 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_si, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   17946             :   { 12391 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_e64_vi, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   17947             :   { 12402 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17948             :   { 12402 /* v_alignbit_b32 */, AMDGPU::V_ALIGNBIT_B32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17949             :   { 12417 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17950             :   { 12417 /* v_alignbyte_b32 */, AMDGPU::V_ALIGNBYTE_B32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17951             :   { 12433 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17952             :   { 12433 /* v_and_b32 */, AMDGPU::V_AND_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17953             :   { 12443 /* v_and_or_b32 */, AMDGPU::V_AND_OR_B32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17954             :   { 12456 /* v_ashr_i32 */, AMDGPU::V_ASHR_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17955             :   { 12467 /* v_ashr_i64 */, AMDGPU::V_ASHR_I64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB321_2, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrcB64, MCK_VCSrcB32 }, },
   17956             :   { 12478 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   17957             :   { 12492 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17958             :   { 12492 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17959             :   { 12506 /* v_ashrrev_i64 */, AMDGPU::V_ASHRREV_I64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB641_2, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VCSrcB32, MCK_VCSrcB64 }, },
   17960             :   { 12520 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17961             :   { 12520 /* v_bcnt_u32_b32 */, AMDGPU::V_BCNT_U32_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17962             :   { 12535 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17963             :   { 12535 /* v_bfe_i32 */, AMDGPU::V_BFE_I32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17964             :   { 12545 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17965             :   { 12545 /* v_bfe_u32 */, AMDGPU::V_BFE_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17966             :   { 12555 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17967             :   { 12555 /* v_bfi_b32 */, AMDGPU::V_BFI_B32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17968             :   { 12565 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17969             :   { 12565 /* v_bfm_b32 */, AMDGPU::V_BFM_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17970             :   { 12575 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   17971             :   { 12575 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   17972             :   { 12587 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17973             :   { 12598 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17974             :   { 12598 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17975             :   { 12609 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17976             :   { 12609 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   17977             :   { 12620 /* v_clrexcp */, AMDGPU::V_CLREXCP_e64_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, {  }, },
   17978             :   { 12620 /* v_clrexcp */, AMDGPU::V_CLREXCP_e64_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, {  }, },
   17979             :   { 12630 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_VCSrcB32 }, },
   17980             :   { 12666 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_VCSrcB32 }, },
   17981             :   { 12666 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_VCSrcB32 }, },
   17982             :   { 12702 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_VCSrcB32 }, },
   17983             :   { 12702 /* v_cmp_class_f64 */, AMDGPU::V_CMP_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_VCSrcB32 }, },
   17984             :   { 12738 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   17985             :   { 12768 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   17986             :   { 12768 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   17987             :   { 12798 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   17988             :   { 12798 /* v_cmp_eq_f64 */, AMDGPU::V_CMP_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   17989             :   { 12828 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   17990             :   { 12858 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17991             :   { 12858 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17992             :   { 12888 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   17993             :   { 12888 /* v_cmp_eq_i64 */, AMDGPU::V_CMP_EQ_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   17994             :   { 12918 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   17995             :   { 12948 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17996             :   { 12948 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   17997             :   { 12978 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   17998             :   { 12978 /* v_cmp_eq_u64 */, AMDGPU::V_CMP_EQ_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   17999             :   { 13008 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18000             :   { 13036 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18001             :   { 13036 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18002             :   { 13064 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18003             :   { 13064 /* v_cmp_f_f64 */, AMDGPU::V_CMP_F_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18004             :   { 13092 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18005             :   { 13120 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18006             :   { 13120 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18007             :   { 13148 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18008             :   { 13148 /* v_cmp_f_i64 */, AMDGPU::V_CMP_F_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18009             :   { 13176 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18010             :   { 13204 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18011             :   { 13204 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18012             :   { 13232 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18013             :   { 13232 /* v_cmp_f_u64 */, AMDGPU::V_CMP_F_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18014             :   { 13260 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18015             :   { 13290 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18016             :   { 13290 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18017             :   { 13320 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18018             :   { 13320 /* v_cmp_ge_f64 */, AMDGPU::V_CMP_GE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18019             :   { 13350 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18020             :   { 13380 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18021             :   { 13380 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18022             :   { 13410 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18023             :   { 13410 /* v_cmp_ge_i64 */, AMDGPU::V_CMP_GE_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18024             :   { 13440 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18025             :   { 13470 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18026             :   { 13470 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18027             :   { 13500 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18028             :   { 13500 /* v_cmp_ge_u64 */, AMDGPU::V_CMP_GE_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18029             :   { 13530 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18030             :   { 13560 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18031             :   { 13560 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18032             :   { 13590 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18033             :   { 13590 /* v_cmp_gt_f64 */, AMDGPU::V_CMP_GT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18034             :   { 13620 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18035             :   { 13650 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18036             :   { 13650 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18037             :   { 13680 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18038             :   { 13680 /* v_cmp_gt_i64 */, AMDGPU::V_CMP_GT_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18039             :   { 13710 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18040             :   { 13740 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18041             :   { 13740 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18042             :   { 13770 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18043             :   { 13770 /* v_cmp_gt_u64 */, AMDGPU::V_CMP_GT_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18044             :   { 13800 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18045             :   { 13830 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18046             :   { 13830 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18047             :   { 13860 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18048             :   { 13860 /* v_cmp_le_f64 */, AMDGPU::V_CMP_LE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18049             :   { 13890 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18050             :   { 13920 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18051             :   { 13920 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18052             :   { 13950 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18053             :   { 13950 /* v_cmp_le_i64 */, AMDGPU::V_CMP_LE_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18054             :   { 13980 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18055             :   { 14010 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18056             :   { 14010 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18057             :   { 14040 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18058             :   { 14040 /* v_cmp_le_u64 */, AMDGPU::V_CMP_LE_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18059             :   { 14070 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18060             :   { 14100 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18061             :   { 14100 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18062             :   { 14130 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18063             :   { 14130 /* v_cmp_lg_f64 */, AMDGPU::V_CMP_LG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18064             :   { 14160 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18065             :   { 14190 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18066             :   { 14190 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18067             :   { 14220 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18068             :   { 14220 /* v_cmp_lt_f64 */, AMDGPU::V_CMP_LT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18069             :   { 14250 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18070             :   { 14280 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18071             :   { 14280 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18072             :   { 14310 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18073             :   { 14310 /* v_cmp_lt_i64 */, AMDGPU::V_CMP_LT_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18074             :   { 14340 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18075             :   { 14370 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18076             :   { 14370 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18077             :   { 14400 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18078             :   { 14400 /* v_cmp_lt_u64 */, AMDGPU::V_CMP_LT_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18079             :   { 14430 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18080             :   { 14460 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18081             :   { 14460 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18082             :   { 14490 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18083             :   { 14490 /* v_cmp_ne_i64 */, AMDGPU::V_CMP_NE_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18084             :   { 14520 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18085             :   { 14550 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18086             :   { 14550 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18087             :   { 14580 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18088             :   { 14580 /* v_cmp_ne_u64 */, AMDGPU::V_CMP_NE_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18089             :   { 14610 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18090             :   { 14642 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18091             :   { 14642 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18092             :   { 14674 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18093             :   { 14674 /* v_cmp_neq_f64 */, AMDGPU::V_CMP_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18094             :   { 14706 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18095             :   { 14738 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18096             :   { 14738 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18097             :   { 14770 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18098             :   { 14770 /* v_cmp_nge_f64 */, AMDGPU::V_CMP_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18099             :   { 14802 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18100             :   { 14834 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18101             :   { 14834 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18102             :   { 14866 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18103             :   { 14866 /* v_cmp_ngt_f64 */, AMDGPU::V_CMP_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18104             :   { 14898 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18105             :   { 14930 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18106             :   { 14930 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18107             :   { 14962 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18108             :   { 14962 /* v_cmp_nle_f64 */, AMDGPU::V_CMP_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18109             :   { 14994 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18110             :   { 15026 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18111             :   { 15026 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18112             :   { 15058 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18113             :   { 15058 /* v_cmp_nlg_f64 */, AMDGPU::V_CMP_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18114             :   { 15090 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18115             :   { 15122 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18116             :   { 15122 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18117             :   { 15154 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18118             :   { 15154 /* v_cmp_nlt_f64 */, AMDGPU::V_CMP_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18119             :   { 15186 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18120             :   { 15214 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18121             :   { 15214 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18122             :   { 15242 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18123             :   { 15242 /* v_cmp_o_f64 */, AMDGPU::V_CMP_O_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18124             :   { 15270 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18125             :   { 15298 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18126             :   { 15298 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18127             :   { 15326 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18128             :   { 15326 /* v_cmp_t_i64 */, AMDGPU::V_CMP_T_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18129             :   { 15354 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18130             :   { 15382 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18131             :   { 15382 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18132             :   { 15410 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18133             :   { 15410 /* v_cmp_t_u64 */, AMDGPU::V_CMP_T_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18134             :   { 15438 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18135             :   { 15470 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18136             :   { 15470 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18137             :   { 15502 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18138             :   { 15502 /* v_cmp_tru_f64 */, AMDGPU::V_CMP_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18139             :   { 15534 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18140             :   { 15562 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18141             :   { 15562 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18142             :   { 15590 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18143             :   { 15590 /* v_cmp_u_f64 */, AMDGPU::V_CMP_U_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18144             :   { 15618 /* v_cmps_eq_f32 */, AMDGPU::V_CMPS_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18145             :   { 15650 /* v_cmps_eq_f64 */, AMDGPU::V_CMPS_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18146             :   { 15682 /* v_cmps_f_f32 */, AMDGPU::V_CMPS_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18147             :   { 15712 /* v_cmps_f_f64 */, AMDGPU::V_CMPS_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18148             :   { 15742 /* v_cmps_ge_f32 */, AMDGPU::V_CMPS_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18149             :   { 15774 /* v_cmps_ge_f64 */, AMDGPU::V_CMPS_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18150             :   { 15806 /* v_cmps_gt_f32 */, AMDGPU::V_CMPS_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18151             :   { 15838 /* v_cmps_gt_f64 */, AMDGPU::V_CMPS_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18152             :   { 15870 /* v_cmps_le_f32 */, AMDGPU::V_CMPS_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18153             :   { 15902 /* v_cmps_le_f64 */, AMDGPU::V_CMPS_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18154             :   { 15934 /* v_cmps_lg_f32 */, AMDGPU::V_CMPS_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18155             :   { 15966 /* v_cmps_lg_f64 */, AMDGPU::V_CMPS_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18156             :   { 15998 /* v_cmps_lt_f32 */, AMDGPU::V_CMPS_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18157             :   { 16030 /* v_cmps_lt_f64 */, AMDGPU::V_CMPS_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18158             :   { 16062 /* v_cmps_neq_f32 */, AMDGPU::V_CMPS_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18159             :   { 16096 /* v_cmps_neq_f64 */, AMDGPU::V_CMPS_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18160             :   { 16130 /* v_cmps_nge_f32 */, AMDGPU::V_CMPS_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18161             :   { 16164 /* v_cmps_nge_f64 */, AMDGPU::V_CMPS_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18162             :   { 16198 /* v_cmps_ngt_f32 */, AMDGPU::V_CMPS_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18163             :   { 16232 /* v_cmps_ngt_f64 */, AMDGPU::V_CMPS_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18164             :   { 16266 /* v_cmps_nle_f32 */, AMDGPU::V_CMPS_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18165             :   { 16300 /* v_cmps_nle_f64 */, AMDGPU::V_CMPS_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18166             :   { 16334 /* v_cmps_nlg_f32 */, AMDGPU::V_CMPS_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18167             :   { 16368 /* v_cmps_nlg_f64 */, AMDGPU::V_CMPS_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18168             :   { 16402 /* v_cmps_nlt_f32 */, AMDGPU::V_CMPS_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18169             :   { 16436 /* v_cmps_nlt_f64 */, AMDGPU::V_CMPS_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18170             :   { 16470 /* v_cmps_o_f32 */, AMDGPU::V_CMPS_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18171             :   { 16500 /* v_cmps_o_f64 */, AMDGPU::V_CMPS_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18172             :   { 16530 /* v_cmps_tru_f32 */, AMDGPU::V_CMPS_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18173             :   { 16564 /* v_cmps_tru_f64 */, AMDGPU::V_CMPS_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18174             :   { 16598 /* v_cmps_u_f32 */, AMDGPU::V_CMPS_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18175             :   { 16628 /* v_cmps_u_f64 */, AMDGPU::V_CMPS_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18176             :   { 16658 /* v_cmpsx_eq_f32 */, AMDGPU::V_CMPSX_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18177             :   { 16692 /* v_cmpsx_eq_f64 */, AMDGPU::V_CMPSX_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18178             :   { 16726 /* v_cmpsx_f_f32 */, AMDGPU::V_CMPSX_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18179             :   { 16758 /* v_cmpsx_f_f64 */, AMDGPU::V_CMPSX_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18180             :   { 16790 /* v_cmpsx_ge_f32 */, AMDGPU::V_CMPSX_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18181             :   { 16824 /* v_cmpsx_ge_f64 */, AMDGPU::V_CMPSX_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18182             :   { 16858 /* v_cmpsx_gt_f32 */, AMDGPU::V_CMPSX_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18183             :   { 16892 /* v_cmpsx_gt_f64 */, AMDGPU::V_CMPSX_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18184             :   { 16926 /* v_cmpsx_le_f32 */, AMDGPU::V_CMPSX_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18185             :   { 16960 /* v_cmpsx_le_f64 */, AMDGPU::V_CMPSX_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18186             :   { 16994 /* v_cmpsx_lg_f32 */, AMDGPU::V_CMPSX_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18187             :   { 17028 /* v_cmpsx_lg_f64 */, AMDGPU::V_CMPSX_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18188             :   { 17062 /* v_cmpsx_lt_f32 */, AMDGPU::V_CMPSX_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18189             :   { 17096 /* v_cmpsx_lt_f64 */, AMDGPU::V_CMPSX_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18190             :   { 17130 /* v_cmpsx_neq_f32 */, AMDGPU::V_CMPSX_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18191             :   { 17166 /* v_cmpsx_neq_f64 */, AMDGPU::V_CMPSX_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18192             :   { 17202 /* v_cmpsx_nge_f32 */, AMDGPU::V_CMPSX_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18193             :   { 17238 /* v_cmpsx_nge_f64 */, AMDGPU::V_CMPSX_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18194             :   { 17274 /* v_cmpsx_ngt_f32 */, AMDGPU::V_CMPSX_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18195             :   { 17310 /* v_cmpsx_ngt_f64 */, AMDGPU::V_CMPSX_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18196             :   { 17346 /* v_cmpsx_nle_f32 */, AMDGPU::V_CMPSX_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18197             :   { 17382 /* v_cmpsx_nle_f64 */, AMDGPU::V_CMPSX_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18198             :   { 17418 /* v_cmpsx_nlg_f32 */, AMDGPU::V_CMPSX_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18199             :   { 17454 /* v_cmpsx_nlg_f64 */, AMDGPU::V_CMPSX_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18200             :   { 17490 /* v_cmpsx_nlt_f32 */, AMDGPU::V_CMPSX_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18201             :   { 17526 /* v_cmpsx_nlt_f64 */, AMDGPU::V_CMPSX_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18202             :   { 17562 /* v_cmpsx_o_f32 */, AMDGPU::V_CMPSX_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18203             :   { 17594 /* v_cmpsx_o_f64 */, AMDGPU::V_CMPSX_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18204             :   { 17626 /* v_cmpsx_tru_f32 */, AMDGPU::V_CMPSX_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18205             :   { 17662 /* v_cmpsx_tru_f64 */, AMDGPU::V_CMPSX_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18206             :   { 17698 /* v_cmpsx_u_f32 */, AMDGPU::V_CMPSX_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18207             :   { 17730 /* v_cmpsx_u_f64 */, AMDGPU::V_CMPSX_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18208             :   { 17762 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_VCSrcB32 }, },
   18209             :   { 17800 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_VCSrcB32 }, },
   18210             :   { 17800 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_VCSrcB32 }, },
   18211             :   { 17838 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_VCSrcB32 }, },
   18212             :   { 17838 /* v_cmpx_class_f64 */, AMDGPU::V_CMPX_CLASS_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_VCSrcB32 }, },
   18213             :   { 17876 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18214             :   { 17908 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18215             :   { 17908 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18216             :   { 17940 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18217             :   { 17940 /* v_cmpx_eq_f64 */, AMDGPU::V_CMPX_EQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18218             :   { 17972 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18219             :   { 18004 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18220             :   { 18004 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18221             :   { 18036 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18222             :   { 18036 /* v_cmpx_eq_i64 */, AMDGPU::V_CMPX_EQ_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18223             :   { 18068 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18224             :   { 18100 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18225             :   { 18100 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18226             :   { 18132 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18227             :   { 18132 /* v_cmpx_eq_u64 */, AMDGPU::V_CMPX_EQ_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18228             :   { 18164 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18229             :   { 18194 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18230             :   { 18194 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18231             :   { 18224 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18232             :   { 18224 /* v_cmpx_f_f64 */, AMDGPU::V_CMPX_F_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18233             :   { 18254 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18234             :   { 18284 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18235             :   { 18284 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18236             :   { 18314 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18237             :   { 18314 /* v_cmpx_f_i64 */, AMDGPU::V_CMPX_F_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18238             :   { 18344 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18239             :   { 18374 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18240             :   { 18374 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18241             :   { 18404 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18242             :   { 18404 /* v_cmpx_f_u64 */, AMDGPU::V_CMPX_F_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18243             :   { 18434 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18244             :   { 18466 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18245             :   { 18466 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18246             :   { 18498 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18247             :   { 18498 /* v_cmpx_ge_f64 */, AMDGPU::V_CMPX_GE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18248             :   { 18530 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18249             :   { 18562 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18250             :   { 18562 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18251             :   { 18594 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18252             :   { 18594 /* v_cmpx_ge_i64 */, AMDGPU::V_CMPX_GE_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18253             :   { 18626 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18254             :   { 18658 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18255             :   { 18658 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18256             :   { 18690 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18257             :   { 18690 /* v_cmpx_ge_u64 */, AMDGPU::V_CMPX_GE_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18258             :   { 18722 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18259             :   { 18754 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18260             :   { 18754 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18261             :   { 18786 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18262             :   { 18786 /* v_cmpx_gt_f64 */, AMDGPU::V_CMPX_GT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18263             :   { 18818 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18264             :   { 18850 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18265             :   { 18850 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18266             :   { 18882 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18267             :   { 18882 /* v_cmpx_gt_i64 */, AMDGPU::V_CMPX_GT_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18268             :   { 18914 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18269             :   { 18946 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18270             :   { 18946 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18271             :   { 18978 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18272             :   { 18978 /* v_cmpx_gt_u64 */, AMDGPU::V_CMPX_GT_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18273             :   { 19010 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18274             :   { 19042 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18275             :   { 19042 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18276             :   { 19074 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18277             :   { 19074 /* v_cmpx_le_f64 */, AMDGPU::V_CMPX_LE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18278             :   { 19106 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18279             :   { 19138 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18280             :   { 19138 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18281             :   { 19170 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18282             :   { 19170 /* v_cmpx_le_i64 */, AMDGPU::V_CMPX_LE_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18283             :   { 19202 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18284             :   { 19234 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18285             :   { 19234 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18286             :   { 19266 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18287             :   { 19266 /* v_cmpx_le_u64 */, AMDGPU::V_CMPX_LE_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18288             :   { 19298 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18289             :   { 19330 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18290             :   { 19330 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18291             :   { 19362 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18292             :   { 19362 /* v_cmpx_lg_f64 */, AMDGPU::V_CMPX_LG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18293             :   { 19394 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18294             :   { 19426 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18295             :   { 19426 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18296             :   { 19458 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18297             :   { 19458 /* v_cmpx_lt_f64 */, AMDGPU::V_CMPX_LT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18298             :   { 19490 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18299             :   { 19522 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18300             :   { 19522 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18301             :   { 19554 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18302             :   { 19554 /* v_cmpx_lt_i64 */, AMDGPU::V_CMPX_LT_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18303             :   { 19586 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18304             :   { 19618 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18305             :   { 19618 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18306             :   { 19650 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18307             :   { 19650 /* v_cmpx_lt_u64 */, AMDGPU::V_CMPX_LT_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18308             :   { 19682 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18309             :   { 19714 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18310             :   { 19714 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18311             :   { 19746 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18312             :   { 19746 /* v_cmpx_ne_i64 */, AMDGPU::V_CMPX_NE_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18313             :   { 19778 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18314             :   { 19810 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18315             :   { 19810 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18316             :   { 19842 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18317             :   { 19842 /* v_cmpx_ne_u64 */, AMDGPU::V_CMPX_NE_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18318             :   { 19874 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18319             :   { 19908 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18320             :   { 19908 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18321             :   { 19942 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18322             :   { 19942 /* v_cmpx_neq_f64 */, AMDGPU::V_CMPX_NEQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18323             :   { 19976 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18324             :   { 20010 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18325             :   { 20010 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18326             :   { 20044 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18327             :   { 20044 /* v_cmpx_nge_f64 */, AMDGPU::V_CMPX_NGE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18328             :   { 20078 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18329             :   { 20112 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18330             :   { 20112 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18331             :   { 20146 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18332             :   { 20146 /* v_cmpx_ngt_f64 */, AMDGPU::V_CMPX_NGT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18333             :   { 20180 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18334             :   { 20214 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18335             :   { 20214 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18336             :   { 20248 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18337             :   { 20248 /* v_cmpx_nle_f64 */, AMDGPU::V_CMPX_NLE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18338             :   { 20282 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18339             :   { 20316 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18340             :   { 20316 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18341             :   { 20350 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18342             :   { 20350 /* v_cmpx_nlg_f64 */, AMDGPU::V_CMPX_NLG_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18343             :   { 20384 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18344             :   { 20418 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18345             :   { 20418 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18346             :   { 20452 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18347             :   { 20452 /* v_cmpx_nlt_f64 */, AMDGPU::V_CMPX_NLT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18348             :   { 20486 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18349             :   { 20516 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18350             :   { 20516 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18351             :   { 20546 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18352             :   { 20546 /* v_cmpx_o_f64 */, AMDGPU::V_CMPX_O_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18353             :   { 20576 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18354             :   { 20606 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18355             :   { 20606 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18356             :   { 20636 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18357             :   { 20636 /* v_cmpx_t_i64 */, AMDGPU::V_CMPX_T_I64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18358             :   { 20666 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18359             :   { 20696 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18360             :   { 20696 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18361             :   { 20726 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18362             :   { 20726 /* v_cmpx_t_u64 */, AMDGPU::V_CMPX_T_U64_e64_vi, Convert__Reg1_0__VCSrcB641_1__VCSrcB641_2, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_VCSrcB64, MCK_VCSrcB64 }, },
   18363             :   { 20756 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18364             :   { 20790 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18365             :   { 20790 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18366             :   { 20824 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18367             :   { 20824 /* v_cmpx_tru_f64 */, AMDGPU::V_CMPX_TRU_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18368             :   { 20858 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18369             :   { 20888 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18370             :   { 20888 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18371             :   { 20918 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18372             :   { 20918 /* v_cmpx_u_f64 */, AMDGPU::V_CMPX_U_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_SReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18373             :   { 20948 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18374             :   { 20948 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__Reg1_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18375             :   { 20962 /* v_cos_f16 */, AMDGPU::V_COS_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18376             :   { 20972 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18377             :   { 20972 /* v_cos_f32 */, AMDGPU::V_COS_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18378             :   { 20982 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18379             :   { 20982 /* v_cubeid_f32 */, AMDGPU::V_CUBEID_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18380             :   { 20995 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18381             :   { 20995 /* v_cubema_f32 */, AMDGPU::V_CUBEMA_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18382             :   { 21008 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18383             :   { 21008 /* v_cubesc_f32 */, AMDGPU::V_CUBESC_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18384             :   { 21021 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18385             :   { 21021 /* v_cubetc_f32 */, AMDGPU::V_CUBETC_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18386             :   { 21034 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18387             :   { 21034 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18388             :   { 21048 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18389             :   { 21062 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18390             :   { 21076 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18391             :   { 21076 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18392             :   { 21090 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18393             :   { 21090 /* v_cvt_f32_f64 */, AMDGPU::V_CVT_F32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18394             :   { 21104 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18395             :   { 21104 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18396             :   { 21118 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18397             :   { 21118 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18398             :   { 21132 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18399             :   { 21132 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18400             :   { 21149 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18401             :   { 21149 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18402             :   { 21166 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18403             :   { 21166 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18404             :   { 21183 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18405             :   { 21183 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18406             :   { 21200 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18407             :   { 21200 /* v_cvt_f64_f32 */, AMDGPU::V_CVT_F64_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18408             :   { 21214 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18409             :   { 21214 /* v_cvt_f64_i32 */, AMDGPU::V_CVT_F64_I32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18410             :   { 21228 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18411             :   { 21228 /* v_cvt_f64_u32 */, AMDGPU::V_CVT_F64_U32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18412             :   { 21242 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18413             :   { 21242 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18414             :   { 21260 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18415             :   { 21274 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18416             :   { 21274 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18417             :   { 21288 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18418             :   { 21288 /* v_cvt_i32_f64 */, AMDGPU::V_CVT_I32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18419             :   { 21302 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18420             :   { 21321 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18421             :   { 21340 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18422             :   { 21340 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18423             :   { 21357 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18424             :   { 21357 /* v_cvt_pk_i16_i32 */, AMDGPU::V_CVT_PK_I16_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18425             :   { 21374 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18426             :   { 21374 /* v_cvt_pk_u16_u32 */, AMDGPU::V_CVT_PK_U16_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18427             :   { 21391 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
   18428             :   { 21391 /* v_cvt_pk_u8_f32 */, AMDGPU::V_CVT_PK_U8_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
   18429             :   { 21407 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
   18430             :   { 21407 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
   18431             :   { 21407 /* v_cvt_pkaccum_u8_f32 */, AMDGPU::V_CVT_PKACCUM_U8_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI }, },
   18432             :   { 21428 /* v_cvt_pknorm_i16_f16 */, AMDGPU::V_CVT_PKNORM_I16_F16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18433             :   { 21449 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
   18434             :   { 21449 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18435             :   { 21449 /* v_cvt_pknorm_i16_f32 */, AMDGPU::V_CVT_PKNORM_I16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18436             :   { 21470 /* v_cvt_pknorm_u16_f16 */, AMDGPU::V_CVT_PKNORM_U16_F16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18437             :   { 21491 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
   18438             :   { 21491 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18439             :   { 21491 /* v_cvt_pknorm_u16_f32 */, AMDGPU::V_CVT_PKNORM_U16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18440             :   { 21512 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
   18441             :   { 21512 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18442             :   { 21512 /* v_cvt_pkrtz_f16_f32 */, AMDGPU::V_CVT_PKRTZ_F16_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18443             :   { 21532 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18444             :   { 21532 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18445             :   { 21550 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18446             :   { 21564 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18447             :   { 21564 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18448             :   { 21578 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18449             :   { 21578 /* v_cvt_u32_f64 */, AMDGPU::V_CVT_U32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18450             :   { 21592 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18451             :   { 21592 /* v_div_fixup_f16 */, AMDGPU::V_DIV_FIXUP_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18452             :   { 21608 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18453             :   { 21608 /* v_div_fixup_f32 */, AMDGPU::V_DIV_FIXUP_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18454             :   { 21624 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18455             :   { 21624 /* v_div_fixup_f64 */, AMDGPU::V_DIV_FIXUP_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18456             :   { 21640 /* v_div_fixup_legacy_f16 */, AMDGPU::V_DIV_FIXUP_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18457             :   { 21663 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18458             :   { 21663 /* v_div_fmas_f32 */, AMDGPU::V_DIV_FMAS_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18459             :   { 21678 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18460             :   { 21678 /* v_div_fmas_f64 */, AMDGPU::V_DIV_FMAS_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18461             :   { 21693 /* v_div_scale_f32 */, AMDGPU::V_DIV_SCALE_F32_si, Convert__Reg1_0__Reg1_1__VCSrcF321_2__VCSrcF321_3__VCSrcF321_4, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcF32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
   18462             :   { 21693 /* v_div_scale_f32 */, AMDGPU::V_DIV_SCALE_F32_vi, Convert__Reg1_0__Reg1_1__VCSrcF321_2__VCSrcF321_3__VCSrcF321_4, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcF32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
   18463             :   { 21709 /* v_div_scale_f64 */, AMDGPU::V_DIV_SCALE_F64_si, Convert__Reg1_0__Reg1_1__VCSrcF641_2__VCSrcF641_3__VCSrcF641_4, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_SReg_64, MCK_VCSrcF64, MCK_VCSrcF64, MCK_VCSrcF64 }, },
   18464             :   { 21709 /* v_div_scale_f64 */, AMDGPU::V_DIV_SCALE_F64_vi, Convert__Reg1_0__Reg1_1__VCSrcF641_2__VCSrcF641_3__VCSrcF641_4, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_SReg_64, MCK_VCSrcF64, MCK_VCSrcF64, MCK_VCSrcF64 }, },
   18465             :   { 21725 /* v_dot2_f32_f16 */, AMDGPU::V_DOT2_F32_F16_vi, ConvertCustom_cvtVOP3P, Feature_HasDLInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2F16, MCK_VCSrcV2F16, MCK_VCSrcF32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18466             :   { 21740 /* v_dot2_i32_i16 */, AMDGPU::V_DOT2_I32_I16_vi, ConvertCustom_cvtVOP3P, Feature_HasDLInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18467             :   { 21755 /* v_dot2_u32_u16 */, AMDGPU::V_DOT2_U32_U16_vi, ConvertCustom_cvtVOP3P, Feature_HasDLInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18468             :   { 21770 /* v_dot4_i32_i8 */, AMDGPU::V_DOT4_I32_I8_vi, ConvertCustom_cvtVOP3P, Feature_HasDLInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18469             :   { 21784 /* v_dot4_u32_u8 */, AMDGPU::V_DOT4_U32_U8_vi, ConvertCustom_cvtVOP3P, Feature_HasDLInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18470             :   { 21798 /* v_dot8_i32_i4 */, AMDGPU::V_DOT8_I32_I4_vi, ConvertCustom_cvtVOP3P, Feature_HasDLInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18471             :   { 21812 /* v_dot8_u32_u4 */, AMDGPU::V_DOT8_U32_U4_vi, ConvertCustom_cvtVOP3P, Feature_HasDLInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18472             :   { 21826 /* v_exp_f16 */, AMDGPU::V_EXP_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18473             :   { 21836 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18474             :   { 21836 /* v_exp_f32 */, AMDGPU::V_EXP_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18475             :   { 21846 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18476             :   { 21846 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18477             :   { 21863 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18478             :   { 21863 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18479             :   { 21874 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18480             :   { 21874 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18481             :   { 21885 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18482             :   { 21885 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18483             :   { 21896 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18484             :   { 21908 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18485             :   { 21908 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18486             :   { 21920 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18487             :   { 21920 /* v_floor_f64 */, AMDGPU::V_FLOOR_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18488             :   { 21932 /* v_fma_f16 */, AMDGPU::V_FMA_F16_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVIOnly, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18489             :   { 21932 /* v_fma_f16 */, AMDGPU::V_FMA_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18490             :   { 21942 /* v_fma_f32 */, AMDGPU::V_FMA_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18491             :   { 21942 /* v_fma_f32 */, AMDGPU::V_FMA_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18492             :   { 21952 /* v_fma_f64 */, AMDGPU::V_FMA_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18493             :   { 21952 /* v_fma_f64 */, AMDGPU::V_FMA_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18494             :   { 21962 /* v_fma_legacy_f16 */, AMDGPU::V_FMA_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18495             :   { 21979 /* v_fma_mix_f32 */, AMDGPU::V_FMA_MIX_F32_vi, ConvertCustom_cvtVOP3P, Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
   18496             :   { 21993 /* v_fma_mixhi_f16 */, AMDGPU::V_FMA_MIXHI_F16_vi, ConvertCustom_cvtVOP3P, Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
   18497             :   { 22009 /* v_fma_mixlo_f16 */, AMDGPU::V_FMA_MIXLO_F16_vi, ConvertCustom_cvtVOP3P, Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
   18498             :   { 22025 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_HasDLInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18499             :   { 22036 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18500             :   { 22048 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18501             :   { 22048 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18502             :   { 22060 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18503             :   { 22060 /* v_fract_f64 */, AMDGPU::V_FRACT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18504             :   { 22072 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI }, },
   18505             :   { 22092 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18506             :   { 22092 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI }, },
   18507             :   { 22112 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18508             :   { 22112 /* v_frexp_exp_i32_f64 */, AMDGPU::V_FREXP_EXP_I32_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI }, },
   18509             :   { 22132 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18510             :   { 22149 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18511             :   { 22149 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18512             :   { 22166 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18513             :   { 22166 /* v_frexp_mant_f64 */, AMDGPU::V_FREXP_MANT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18514             :   { 22183 /* v_interp_mov_f32 */, AMDGPU::V_INTERP_MOV_F32_e64_vi, ConvertCustom_cvtVOP3Interp, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_InterpSlot, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18515             :   { 22200 /* v_interp_p1_f32 */, AMDGPU::V_INTERP_P1_F32_e64_vi, ConvertCustom_cvtVOP3Interp, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18516             :   { 22216 /* v_interp_p1ll_f16 */, AMDGPU::V_INTERP_P1LL_F16_vi, ConvertCustom_cvtVOP3Interp, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18517             :   { 22234 /* v_interp_p1lv_f16 */, AMDGPU::V_INTERP_P1LV_F16_vi, ConvertCustom_cvtVOP3Interp, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP16InputMods, MCK_ImmHigh, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18518             :   { 22252 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_gfx9_gfx9, ConvertCustom_cvtVOP3Interp, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
   18519             :   { 22252 /* v_interp_p2_f16 */, AMDGPU::V_INTERP_P2_F16_vi, ConvertCustom_cvtVOP3Interp, Feature_Has16BitInsts|Feature_isVIOnly, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
   18520             :   { 22268 /* v_interp_p2_f32 */, AMDGPU::V_INTERP_P2_F32_e64_vi, ConvertCustom_cvtVOP3Interp, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18521             :   { 22284 /* v_interp_p2_legacy_f16 */, AMDGPU::V_INTERP_P2_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3Interp, Feature_Has16BitInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_Attr, MCK_AttrChan, MCK_RegOrImmWithFP32InputMods, MCK_ImmHigh, MCK_ImmClampSI }, },
   18522             :   { 22307 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18523             :   { 22319 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, Convert__Reg1_0__imm_95_0__VCSrcF321_1__imm_95_0__VCSrcF321_2__imm_95_0__imm_95_0, Feature_isVI, { MCK_VGPR_32, MCK_VCSrcF32, MCK_VCSrcF32 }, },
   18524             :   { 22319 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18525             :   { 22319 /* v_ldexp_f32 */, AMDGPU::V_LDEXP_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18526             :   { 22331 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18527             :   { 22331 /* v_ldexp_f64 */, AMDGPU::V_LDEXP_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18528             :   { 22343 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18529             :   { 22343 /* v_lerp_u8 */, AMDGPU::V_LERP_U8_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18530             :   { 22353 /* v_log_clamp_f32 */, AMDGPU::V_LOG_CLAMP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18531             :   { 22369 /* v_log_f16 */, AMDGPU::V_LOG_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18532             :   { 22379 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18533             :   { 22379 /* v_log_f32 */, AMDGPU::V_LOG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18534             :   { 22389 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18535             :   { 22389 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18536             :   { 22406 /* v_lshl_add_u32 */, AMDGPU::V_LSHL_ADD_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18537             :   { 22421 /* v_lshl_b32 */, AMDGPU::V_LSHL_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18538             :   { 22432 /* v_lshl_b64 */, AMDGPU::V_LSHL_B64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB321_2, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrcB64, MCK_VCSrcB32 }, },
   18539             :   { 22443 /* v_lshl_or_b32 */, AMDGPU::V_LSHL_OR_B32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18540             :   { 22457 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18541             :   { 22471 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18542             :   { 22471 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18543             :   { 22485 /* v_lshlrev_b64 */, AMDGPU::V_LSHLREV_B64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB641_2, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VCSrcB32, MCK_VCSrcB64 }, },
   18544             :   { 22499 /* v_lshr_b32 */, AMDGPU::V_LSHR_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18545             :   { 22510 /* v_lshr_b64 */, AMDGPU::V_LSHR_B64_si, Convert__Reg1_0__VCSrcB641_1__VCSrcB321_2, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_VCSrcB64, MCK_VCSrcB32 }, },
   18546             :   { 22521 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18547             :   { 22535 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18548             :   { 22535 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18549             :   { 22549 /* v_lshrrev_b64 */, AMDGPU::V_LSHRREV_B64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB641_2, Feature_isVI|Feature_isVI, { MCK_VReg_64, MCK_VCSrcB32, MCK_VCSrcB64 }, },
   18550             :   { 22563 /* v_mac_f16 */, AMDGPU::V_MAC_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18551             :   { 22573 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18552             :   { 22573 /* v_mac_f32 */, AMDGPU::V_MAC_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18553             :   { 22583 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18554             :   { 22600 /* v_mad_f16 */, AMDGPU::V_MAD_F16_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVIOnly, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18555             :   { 22600 /* v_mad_f16 */, AMDGPU::V_MAD_F16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18556             :   { 22610 /* v_mad_f32 */, AMDGPU::V_MAD_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18557             :   { 22610 /* v_mad_f32 */, AMDGPU::V_MAD_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18558             :   { 22620 /* v_mad_i16 */, AMDGPU::V_MAD_I16_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmClampSI }, },
   18559             :   { 22620 /* v_mad_i16 */, AMDGPU::V_MAD_I16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18560             :   { 22630 /* v_mad_i32_i16 */, AMDGPU::V_MAD_I32_I16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18561             :   { 22644 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18562             :   { 22644 /* v_mad_i32_i24 */, AMDGPU::V_MAD_I32_I24_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18563             :   { 22658 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18564             :   { 22658 /* v_mad_i64_i32 */, AMDGPU::V_MAD_I64_I32_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18565             :   { 22672 /* v_mad_legacy_f16 */, AMDGPU::V_MAD_LEGACY_F16_gfx9, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18566             :   { 22689 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18567             :   { 22689 /* v_mad_legacy_f32 */, AMDGPU::V_MAD_LEGACY_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18568             :   { 22706 /* v_mad_legacy_i16 */, AMDGPU::V_MAD_LEGACY_I16_gfx9, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmClampSI }, },
   18569             :   { 22723 /* v_mad_legacy_u16 */, AMDGPU::V_MAD_LEGACY_U16_gfx9, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmClampSI }, },
   18570             :   { 22740 /* v_mad_mix_f32 */, AMDGPU::V_MAD_MIX_F32_vi, ConvertCustom_cvtVOP3P, Feature_HasMadMixInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
   18571             :   { 22754 /* v_mad_mixhi_f16 */, AMDGPU::V_MAD_MIXHI_F16_vi, ConvertCustom_cvtVOP3P, Feature_HasMadMixInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
   18572             :   { 22770 /* v_mad_mixlo_f16 */, AMDGPU::V_MAD_MIXLO_F16_vi, ConvertCustom_cvtVOP3P, Feature_HasMadMixInsts|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmClampSI }, },
   18573             :   { 22786 /* v_mad_u16 */, AMDGPU::V_MAD_U16_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmClampSI }, },
   18574             :   { 22786 /* v_mad_u16 */, AMDGPU::V_MAD_U16_gfx9_gfx9, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18575             :   { 22796 /* v_mad_u32_u16 */, AMDGPU::V_MAD_U32_U16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB32, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18576             :   { 22810 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18577             :   { 22810 /* v_mad_u32_u24 */, AMDGPU::V_MAD_U32_U24_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18578             :   { 22824 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18579             :   { 22824 /* v_mad_u64_u32 */, AMDGPU::V_MAD_U64_U32_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18580             :   { 22886 /* v_max3_f16 */, AMDGPU::V_MAX3_F16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18581             :   { 22897 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18582             :   { 22897 /* v_max3_f32 */, AMDGPU::V_MAX3_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18583             :   { 22908 /* v_max3_i16 */, AMDGPU::V_MAX3_I16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18584             :   { 22919 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18585             :   { 22919 /* v_max3_i32 */, AMDGPU::V_MAX3_I32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18586             :   { 22930 /* v_max3_u16 */, AMDGPU::V_MAX3_U16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18587             :   { 22941 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18588             :   { 22941 /* v_max3_u32 */, AMDGPU::V_MAX3_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18589             :   { 22952 /* v_max_f16 */, AMDGPU::V_MAX_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18590             :   { 22962 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18591             :   { 22962 /* v_max_f32 */, AMDGPU::V_MAX_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18592             :   { 22972 /* v_max_f64 */, AMDGPU::V_MAX_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18593             :   { 22972 /* v_max_f64 */, AMDGPU::V_MAX_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18594             :   { 22982 /* v_max_i16 */, AMDGPU::V_MAX_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18595             :   { 22992 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18596             :   { 22992 /* v_max_i32 */, AMDGPU::V_MAX_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18597             :   { 23002 /* v_max_legacy_f32 */, AMDGPU::V_MAX_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18598             :   { 23019 /* v_max_u16 */, AMDGPU::V_MAX_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18599             :   { 23029 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18600             :   { 23029 /* v_max_u32 */, AMDGPU::V_MAX_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18601             :   { 23039 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18602             :   { 23039 /* v_mbcnt_hi_u32_b32 */, AMDGPU::V_MBCNT_HI_U32_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18603             :   { 23058 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18604             :   { 23058 /* v_mbcnt_lo_u32_b32 */, AMDGPU::V_MBCNT_LO_U32_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18605             :   { 23077 /* v_med3_f16 */, AMDGPU::V_MED3_F16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18606             :   { 23088 /* v_med3_f32 */, AMDGPU::V_MED3_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18607             :   { 23088 /* v_med3_f32 */, AMDGPU::V_MED3_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18608             :   { 23099 /* v_med3_i16 */, AMDGPU::V_MED3_I16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18609             :   { 23110 /* v_med3_i32 */, AMDGPU::V_MED3_I32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18610             :   { 23110 /* v_med3_i32 */, AMDGPU::V_MED3_I32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18611             :   { 23121 /* v_med3_u16 */, AMDGPU::V_MED3_U16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18612             :   { 23132 /* v_med3_u32 */, AMDGPU::V_MED3_U32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18613             :   { 23132 /* v_med3_u32 */, AMDGPU::V_MED3_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18614             :   { 23143 /* v_min3_f16 */, AMDGPU::V_MIN3_F16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18615             :   { 23154 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18616             :   { 23154 /* v_min3_f32 */, AMDGPU::V_MIN3_F32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18617             :   { 23165 /* v_min3_i16 */, AMDGPU::V_MIN3_I16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18618             :   { 23176 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18619             :   { 23176 /* v_min3_i32 */, AMDGPU::V_MIN3_I32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18620             :   { 23187 /* v_min3_u16 */, AMDGPU::V_MIN3_U16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18621             :   { 23198 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18622             :   { 23198 /* v_min3_u32 */, AMDGPU::V_MIN3_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18623             :   { 23209 /* v_min_f16 */, AMDGPU::V_MIN_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18624             :   { 23219 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18625             :   { 23219 /* v_min_f32 */, AMDGPU::V_MIN_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18626             :   { 23229 /* v_min_f64 */, AMDGPU::V_MIN_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18627             :   { 23229 /* v_min_f64 */, AMDGPU::V_MIN_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18628             :   { 23239 /* v_min_i16 */, AMDGPU::V_MIN_I16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18629             :   { 23249 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18630             :   { 23249 /* v_min_i32 */, AMDGPU::V_MIN_I32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18631             :   { 23259 /* v_min_legacy_f32 */, AMDGPU::V_MIN_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18632             :   { 23276 /* v_min_u16 */, AMDGPU::V_MIN_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18633             :   { 23286 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18634             :   { 23286 /* v_min_u32 */, AMDGPU::V_MIN_U32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18635             :   { 23296 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18636             :   { 23296 /* v_mov_b32 */, AMDGPU::V_MOV_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18637             :   { 23306 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18638             :   { 23306 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18639             :   { 23320 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_si, Convert__Reg1_0__VSrcB321_1, Feature_HasMovrel|Feature_isSICI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   18640             :   { 23320 /* v_movreld_b32 */, AMDGPU::V_MOVRELD_B32_e64_vi, Convert__Reg1_0__VSrcB321_1, Feature_HasMovrel|Feature_isVI, { MCK_VGPR_32, MCK_VSrcB32 }, },
   18641             :   { 23334 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e64_si, Convert__Reg1_0__Reg1_1, Feature_HasMovrel|Feature_isSICI, { MCK_VGPR_32, MCK_VGPR_32 }, },
   18642             :   { 23334 /* v_movrels_b32 */, AMDGPU::V_MOVRELS_B32_e64_vi, Convert__Reg1_0__Reg1_1, Feature_HasMovrel|Feature_isVI, { MCK_VGPR_32, MCK_VGPR_32 }, },
   18643             :   { 23348 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_HasMovrel|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18644             :   { 23348 /* v_movrelsd_b32 */, AMDGPU::V_MOVRELSD_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_HasMovrel|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18645             :   { 23363 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_VCSrcB64, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18646             :   { 23363 /* v_mqsad_pk_u16_u8 */, AMDGPU::V_MQSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_VCSrcB64, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18647             :   { 23381 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_128, MCK_VCSrcB64, MCK_VCSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
   18648             :   { 23381 /* v_mqsad_u32_u8 */, AMDGPU::V_MQSAD_U32_U8_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_128, MCK_VCSrcB64, MCK_VCSrcB32, MCK_VReg_128, MCK_ImmClampSI }, },
   18649             :   { 23396 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18650             :   { 23396 /* v_msad_u8 */, AMDGPU::V_MSAD_U8_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18651             :   { 23406 /* v_mul_f16 */, AMDGPU::V_MUL_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18652             :   { 23416 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18653             :   { 23416 /* v_mul_f32 */, AMDGPU::V_MUL_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18654             :   { 23426 /* v_mul_f64 */, AMDGPU::V_MUL_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18655             :   { 23426 /* v_mul_f64 */, AMDGPU::V_MUL_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18656             :   { 23436 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18657             :   { 23436 /* v_mul_hi_i32 */, AMDGPU::V_MUL_HI_I32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18658             :   { 23449 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18659             :   { 23449 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18660             :   { 23466 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18661             :   { 23466 /* v_mul_hi_u32 */, AMDGPU::V_MUL_HI_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18662             :   { 23479 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18663             :   { 23479 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18664             :   { 23496 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18665             :   { 23496 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18666             :   { 23510 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18667             :   { 23510 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18668             :   { 23527 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18669             :   { 23527 /* v_mul_lo_i32 */, AMDGPU::V_MUL_LO_I32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18670             :   { 23540 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18671             :   { 23553 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18672             :   { 23553 /* v_mul_lo_u32 */, AMDGPU::V_MUL_LO_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18673             :   { 23566 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18674             :   { 23566 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18675             :   { 23580 /* v_mullit_f32 */, AMDGPU::V_MULLIT_F32_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18676             :   { 23593 /* v_nop */, AMDGPU::V_NOP_e64_si, Convert_NoOperands, Feature_isGCN|Feature_isSICI, {  }, },
   18677             :   { 23593 /* v_nop */, AMDGPU::V_NOP_e64_vi, Convert_NoOperands, Feature_isGCN|Feature_isVI, {  }, },
   18678             :   { 23599 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_si, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18679             :   { 23599 /* v_not_b32 */, AMDGPU::V_NOT_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18680             :   { 23609 /* v_or3_b32 */, AMDGPU::V_OR3_B32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18681             :   { 23619 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18682             :   { 23619 /* v_or_b32 */, AMDGPU::V_OR_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18683             :   { 23628 /* v_pack_b32_f16 */, AMDGPU::V_PACK_B32_F16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18684             :   { 23643 /* v_perm_b32 */, AMDGPU::V_PERM_B32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isVI|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18685             :   { 23654 /* v_pk_add_f16 */, AMDGPU::V_PK_ADD_F16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2F16, MCK_VCSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18686             :   { 23667 /* v_pk_add_i16 */, AMDGPU::V_PK_ADD_I16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18687             :   { 23680 /* v_pk_add_u16 */, AMDGPU::V_PK_ADD_U16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18688             :   { 23693 /* v_pk_ashrrev_i16 */, AMDGPU::V_PK_ASHRREV_I16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18689             :   { 23710 /* v_pk_fma_f16 */, AMDGPU::V_PK_FMA_F16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2F16, MCK_VCSrcV2F16, MCK_VCSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18690             :   { 23723 /* v_pk_lshlrev_b16 */, AMDGPU::V_PK_LSHLREV_B16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18691             :   { 23740 /* v_pk_lshrrev_b16 */, AMDGPU::V_PK_LSHRREV_B16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18692             :   { 23757 /* v_pk_mad_i16 */, AMDGPU::V_PK_MAD_I16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18693             :   { 23770 /* v_pk_mad_u16 */, AMDGPU::V_PK_MAD_U16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18694             :   { 23783 /* v_pk_max_f16 */, AMDGPU::V_PK_MAX_F16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2F16, MCK_VCSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18695             :   { 23796 /* v_pk_max_i16 */, AMDGPU::V_PK_MAX_I16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18696             :   { 23809 /* v_pk_max_u16 */, AMDGPU::V_PK_MAX_U16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18697             :   { 23822 /* v_pk_min_f16 */, AMDGPU::V_PK_MIN_F16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2F16, MCK_VCSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18698             :   { 23835 /* v_pk_min_i16 */, AMDGPU::V_PK_MIN_I16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18699             :   { 23848 /* v_pk_min_u16 */, AMDGPU::V_PK_MIN_U16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18700             :   { 23861 /* v_pk_mul_f16 */, AMDGPU::V_PK_MUL_F16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2F16, MCK_VCSrcV2F16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18701             :   { 23874 /* v_pk_mul_lo_u16 */, AMDGPU::V_PK_MUL_LO_U16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18702             :   { 23890 /* v_pk_sub_i16 */, AMDGPU::V_PK_SUB_I16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18703             :   { 23903 /* v_pk_sub_u16 */, AMDGPU::V_PK_SUB_U16_vi, ConvertCustom_cvtVOP3P, Feature_isGCN|Feature_HasVOP3PInsts, { MCK_VGPR_32, MCK_VCSrcV2B16, MCK_VCSrcV2B16, MCK_ImmOpSel, MCK_ImmOpSelHi, MCK_ImmNegLo, MCK_ImmNegHi, MCK_ImmClampSI }, },
   18704             :   { 23916 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_VCSrcB64, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18705             :   { 23916 /* v_qsad_pk_u16_u8 */, AMDGPU::V_QSAD_PK_U16_U8_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_VCSrcB64, MCK_VCSrcB32, MCK_VCSrcB64, MCK_ImmClampSI }, },
   18706             :   { 23933 /* v_rcp_clamp_f32 */, AMDGPU::V_RCP_CLAMP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18707             :   { 23949 /* v_rcp_clamp_f64 */, AMDGPU::V_RCP_CLAMP_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18708             :   { 23965 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18709             :   { 23975 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18710             :   { 23975 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18711             :   { 23985 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18712             :   { 23985 /* v_rcp_f64 */, AMDGPU::V_RCP_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18713             :   { 23995 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18714             :   { 23995 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18715             :   { 24011 /* v_rcp_legacy_f32 */, AMDGPU::V_RCP_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18716             :   { 24063 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18717             :   { 24075 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18718             :   { 24075 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18719             :   { 24087 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18720             :   { 24087 /* v_rndne_f64 */, AMDGPU::V_RNDNE_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18721             :   { 24099 /* v_rsq_clamp_f32 */, AMDGPU::V_RSQ_CLAMP_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18722             :   { 24115 /* v_rsq_clamp_f64 */, AMDGPU::V_RSQ_CLAMP_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18723             :   { 24131 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18724             :   { 24141 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18725             :   { 24141 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18726             :   { 24151 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18727             :   { 24151 /* v_rsq_f64 */, AMDGPU::V_RSQ_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18728             :   { 24161 /* v_rsq_legacy_f32 */, AMDGPU::V_RSQ_LEGACY_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isSICI|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18729             :   { 24178 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18730             :   { 24178 /* v_sad_hi_u8 */, AMDGPU::V_SAD_HI_U8_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18731             :   { 24190 /* v_sad_u16 */, AMDGPU::V_SAD_U16_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18732             :   { 24190 /* v_sad_u16 */, AMDGPU::V_SAD_U16_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18733             :   { 24200 /* v_sad_u32 */, AMDGPU::V_SAD_U32_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18734             :   { 24200 /* v_sad_u32 */, AMDGPU::V_SAD_U32_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18735             :   { 24210 /* v_sad_u8 */, AMDGPU::V_SAD_U8_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18736             :   { 24210 /* v_sad_u8 */, AMDGPU::V_SAD_U8_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_ImmClampSI }, },
   18737             :   { 24219 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18738             :   { 24235 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB32 }, },
   18739             :   { 24262 /* v_sin_f16 */, AMDGPU::V_SIN_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18740             :   { 24272 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18741             :   { 24272 /* v_sin_f32 */, AMDGPU::V_SIN_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18742             :   { 24282 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18743             :   { 24293 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18744             :   { 24293 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18745             :   { 24304 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18746             :   { 24304 /* v_sqrt_f64 */, AMDGPU::V_SQRT_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18747             :   { 24315 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_e64_gfx9, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18748             :   { 24328 /* v_sub_f16 */, AMDGPU::V_SUB_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18749             :   { 24338 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18750             :   { 24338 /* v_sub_f32 */, AMDGPU::V_SUB_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18751             :   { 24348 /* v_sub_i16 */, AMDGPU::V_SUB_I16_vi, ConvertCustom_cvtVOP3OpSel, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16, MCK_ImmOpSel, MCK_ImmClampSI }, },
   18752             :   { 24358 /* v_sub_i32 */, AMDGPU::V_SUB_I32_gfx9_gfx9, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGFX9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18753             :   { 24358 /* v_sub_i32 */, AMDGPU::V_SUB_I32_e64_si, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18754             :   { 24368 /* v_sub_u16 */, AMDGPU::V_SUB_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18755             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_gfx9, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_HasAddNoCarryInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18756             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_e64_vi, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18757             :   { 24388 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_e64_gfx9, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18758             :   { 24402 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_si, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18759             :   { 24402 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_e64_vi, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18760             :   { 24413 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_e64_gfx9, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18761             :   { 24430 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_si, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18762             :   { 24430 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_e64_vi, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3__Reg1_4, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32, MCK_SReg_64_XEXEC }, },
   18763             :   { 24444 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_e64_gfx9, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isGFX9, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18764             :   { 24460 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18765             :   { 24473 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18766             :   { 24473 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18767             :   { 24486 /* v_subrev_i32 */, AMDGPU::V_SUBREV_I32_e64_si, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18768             :   { 24499 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_e64_vi, Convert__Reg1_0__VCSrcB161_1__VCSrcB161_2, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB16, MCK_VCSrcB16 }, },
   18769             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_gfx9, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_HasAddNoCarryInsts|Feature_isGFX9, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18770             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_e64_vi, Convert__Reg1_0__Reg1_1__VCSrcB321_2__VCSrcB321_3, Feature_isGCN|Feature_isVIOnly, { MCK_VGPR_32, MCK_SReg_64, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18771             :   { 24536 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18772             :   { 24536 /* v_trig_preop_f64 */, AMDGPU::V_TRIG_PREOP_F64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_RegOrImmWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18773             :   { 24553 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_e64_vi, ConvertCustom_cvtVOP3, Feature_Has16BitInsts|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18774             :   { 24565 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_si, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18775             :   { 24565 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_e64_vi, ConvertCustom_cvtVOP3, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_RegOrImmWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18776             :   { 24577 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_ci, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isCIOnly, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18777             :   { 24577 /* v_trunc_f64 */, AMDGPU::V_TRUNC_F64_e64_vi, ConvertCustom_cvtVOP3, Feature_isCIVI|Feature_isVI, { MCK_VReg_64, MCK_RegOrImmWithFP64InputMods, MCK_ImmClampSI, MCK_ImmOModSI }, },
   18778             :   { 24605 /* v_xad_u32 */, AMDGPU::V_XAD_U32_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2__VCSrcB321_3, Feature_isGFX9|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18779             :   { 24615 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_HasDLInsts|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18780             :   { 24626 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_si, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isSICI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18781             :   { 24626 /* v_xor_b32 */, AMDGPU::V_XOR_B32_e64_vi, Convert__Reg1_0__VCSrcB321_1__VCSrcB321_2, Feature_isGCN|Feature_isVI, { MCK_VGPR_32, MCK_VCSrcB32, MCK_VCSrcB32 }, },
   18782             : };
   18783             : 
   18784             : static const MatchEntry MatchTable2[] = {
   18785             :   { 12292 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18786             :   { 12302 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18787             :   { 12357 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18788             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18789             :   { 12391 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18790             :   { 12433 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18791             :   { 12478 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18792             :   { 12492 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18793             :   { 12575 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18794             :   { 12587 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18795             :   { 12598 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18796             :   { 12630 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18797             :   { 12666 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18798             :   { 12738 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18799             :   { 12768 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18800             :   { 12828 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18801             :   { 12858 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18802             :   { 12918 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18803             :   { 12948 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18804             :   { 13008 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18805             :   { 13036 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18806             :   { 13092 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18807             :   { 13120 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18808             :   { 13176 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18809             :   { 13204 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18810             :   { 13260 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18811             :   { 13290 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18812             :   { 13350 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18813             :   { 13380 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18814             :   { 13440 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18815             :   { 13470 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18816             :   { 13530 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18817             :   { 13560 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18818             :   { 13620 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18819             :   { 13650 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18820             :   { 13710 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18821             :   { 13740 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18822             :   { 13800 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18823             :   { 13830 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18824             :   { 13890 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18825             :   { 13920 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18826             :   { 13980 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18827             :   { 14010 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18828             :   { 14070 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18829             :   { 14100 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18830             :   { 14160 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18831             :   { 14190 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18832             :   { 14250 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18833             :   { 14280 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18834             :   { 14340 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18835             :   { 14370 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18836             :   { 14430 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18837             :   { 14460 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18838             :   { 14520 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18839             :   { 14550 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18840             :   { 14610 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18841             :   { 14642 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18842             :   { 14706 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18843             :   { 14738 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18844             :   { 14802 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18845             :   { 14834 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18846             :   { 14898 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18847             :   { 14930 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18848             :   { 14994 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18849             :   { 15026 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18850             :   { 15090 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18851             :   { 15122 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18852             :   { 15186 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18853             :   { 15214 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18854             :   { 15270 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18855             :   { 15298 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18856             :   { 15354 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18857             :   { 15382 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18858             :   { 15438 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18859             :   { 15470 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18860             :   { 15534 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18861             :   { 15562 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18862             :   { 17762 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18863             :   { 17800 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18864             :   { 17876 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18865             :   { 17908 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18866             :   { 17972 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18867             :   { 18004 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18868             :   { 18068 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18869             :   { 18100 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18870             :   { 18164 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18871             :   { 18194 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18872             :   { 18254 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18873             :   { 18284 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18874             :   { 18344 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18875             :   { 18374 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18876             :   { 18434 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18877             :   { 18466 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18878             :   { 18530 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18879             :   { 18562 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18880             :   { 18626 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18881             :   { 18658 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18882             :   { 18722 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18883             :   { 18754 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18884             :   { 18818 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18885             :   { 18850 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18886             :   { 18914 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18887             :   { 18946 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18888             :   { 19010 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18889             :   { 19042 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18890             :   { 19106 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18891             :   { 19138 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18892             :   { 19202 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18893             :   { 19234 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18894             :   { 19298 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18895             :   { 19330 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18896             :   { 19394 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18897             :   { 19426 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18898             :   { 19490 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18899             :   { 19522 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18900             :   { 19586 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18901             :   { 19618 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18902             :   { 19682 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18903             :   { 19714 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18904             :   { 19778 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18905             :   { 19810 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18906             :   { 19874 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18907             :   { 19908 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18908             :   { 19976 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18909             :   { 20010 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18910             :   { 20078 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18911             :   { 20112 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18912             :   { 20180 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18913             :   { 20214 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18914             :   { 20282 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18915             :   { 20316 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18916             :   { 20384 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18917             :   { 20418 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18918             :   { 20486 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18919             :   { 20516 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18920             :   { 20576 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18921             :   { 20606 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18922             :   { 20666 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18923             :   { 20696 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18924             :   { 20756 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18925             :   { 20790 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18926             :   { 20858 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18927             :   { 20888 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_vi, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA|Feature_HasSDWA, { MCK_VCC, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18928             :   { 20948 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18929             :   { 20962 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18930             :   { 20972 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18931             :   { 21034 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18932             :   { 21048 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18933             :   { 21062 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18934             :   { 21076 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18935             :   { 21104 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18936             :   { 21118 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18937             :   { 21132 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18938             :   { 21149 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18939             :   { 21166 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18940             :   { 21183 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18941             :   { 21242 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18942             :   { 21260 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18943             :   { 21274 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18944             :   { 21302 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_isGFX9|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18945             :   { 21321 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_isGFX9|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18946             :   { 21340 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18947             :   { 21532 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18948             :   { 21550 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18949             :   { 21564 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18950             :   { 21826 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18951             :   { 21836 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18952             :   { 21846 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_isCIVI|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18953             :   { 21863 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18954             :   { 21874 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18955             :   { 21885 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18956             :   { 21896 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18957             :   { 21908 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18958             :   { 22025 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_HasDLInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18959             :   { 22036 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18960             :   { 22048 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18961             :   { 22072 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18962             :   { 22092 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18963             :   { 22132 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18964             :   { 22149 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18965             :   { 22307 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18966             :   { 22369 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18967             :   { 22379 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18968             :   { 22389 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_isCIVI|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18969             :   { 22457 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18970             :   { 22471 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18971             :   { 22521 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18972             :   { 22535 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18973             :   { 22563 /* v_mac_f16 */, AMDGPU::V_MAC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18974             :   { 22573 /* v_mac_f32 */, AMDGPU::V_MAC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18975             :   { 22952 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18976             :   { 22962 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18977             :   { 22982 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18978             :   { 22992 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18979             :   { 23019 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18980             :   { 23029 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18981             :   { 23209 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18982             :   { 23219 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18983             :   { 23239 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18984             :   { 23249 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18985             :   { 23276 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18986             :   { 23286 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18987             :   { 23296 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18988             :   { 23306 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18989             :   { 23406 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18990             :   { 23416 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18991             :   { 23449 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18992             :   { 23479 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18993             :   { 23496 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18994             :   { 23510 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18995             :   { 23540 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18996             :   { 23566 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   18997             :   { 23593 /* v_nop */, AMDGPU::V_NOP_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, {  }, },
   18998             :   { 23599 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   18999             :   { 23619 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19000             :   { 23965 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19001             :   { 23975 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19002             :   { 23995 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19003             :   { 24063 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19004             :   { 24075 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19005             :   { 24131 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19006             :   { 24141 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19007             :   { 24219 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_isGFX9|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19008             :   { 24262 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19009             :   { 24272 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19010             :   { 24282 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19011             :   { 24293 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19012             :   { 24328 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19013             :   { 24338 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19014             :   { 24368 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19015             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19016             :   { 24402 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19017             :   { 24430 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19018             :   { 24460 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19019             :   { 24473 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19020             :   { 24499 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19021             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_vi, ConvertCustom_cvtSdwaVOP2b, Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19022             :   { 24553 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_Has16BitInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19023             :   { 24565 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_vi, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19024             :   { 24615 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_HasDLInsts|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19025             :   { 24626 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_vi, ConvertCustom_cvtSdwaVOP2, Feature_isGCN|Feature_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19026             : };
   19027             : 
   19028             : static const MatchEntry MatchTable3[] = {
   19029             :   { 12279 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19030             :   { 12292 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19031             :   { 12302 /* v_add_f32 */, AMDGPU::V_ADD_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19032             :   { 12357 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19033             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19034             :   { 12377 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19035             :   { 12433 /* v_and_b32 */, AMDGPU::V_AND_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19036             :   { 12478 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19037             :   { 12492 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19038             :   { 12575 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19039             :   { 12587 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19040             :   { 12598 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19041             :   { 12630 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19042             :   { 12666 /* v_cmp_class_f32 */, AMDGPU::V_CMP_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19043             :   { 12738 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19044             :   { 12768 /* v_cmp_eq_f32 */, AMDGPU::V_CMP_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19045             :   { 12828 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19046             :   { 12858 /* v_cmp_eq_i32 */, AMDGPU::V_CMP_EQ_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19047             :   { 12918 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19048             :   { 12948 /* v_cmp_eq_u32 */, AMDGPU::V_CMP_EQ_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19049             :   { 13008 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19050             :   { 13036 /* v_cmp_f_f32 */, AMDGPU::V_CMP_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19051             :   { 13092 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19052             :   { 13120 /* v_cmp_f_i32 */, AMDGPU::V_CMP_F_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19053             :   { 13176 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19054             :   { 13204 /* v_cmp_f_u32 */, AMDGPU::V_CMP_F_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19055             :   { 13260 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19056             :   { 13290 /* v_cmp_ge_f32 */, AMDGPU::V_CMP_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19057             :   { 13350 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19058             :   { 13380 /* v_cmp_ge_i32 */, AMDGPU::V_CMP_GE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19059             :   { 13440 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19060             :   { 13470 /* v_cmp_ge_u32 */, AMDGPU::V_CMP_GE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19061             :   { 13530 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19062             :   { 13560 /* v_cmp_gt_f32 */, AMDGPU::V_CMP_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19063             :   { 13620 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19064             :   { 13650 /* v_cmp_gt_i32 */, AMDGPU::V_CMP_GT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19065             :   { 13710 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19066             :   { 13740 /* v_cmp_gt_u32 */, AMDGPU::V_CMP_GT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19067             :   { 13800 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19068             :   { 13830 /* v_cmp_le_f32 */, AMDGPU::V_CMP_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19069             :   { 13890 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19070             :   { 13920 /* v_cmp_le_i32 */, AMDGPU::V_CMP_LE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19071             :   { 13980 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19072             :   { 14010 /* v_cmp_le_u32 */, AMDGPU::V_CMP_LE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19073             :   { 14070 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19074             :   { 14100 /* v_cmp_lg_f32 */, AMDGPU::V_CMP_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19075             :   { 14160 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19076             :   { 14190 /* v_cmp_lt_f32 */, AMDGPU::V_CMP_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19077             :   { 14250 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19078             :   { 14280 /* v_cmp_lt_i32 */, AMDGPU::V_CMP_LT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19079             :   { 14340 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19080             :   { 14370 /* v_cmp_lt_u32 */, AMDGPU::V_CMP_LT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19081             :   { 14430 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19082             :   { 14460 /* v_cmp_ne_i32 */, AMDGPU::V_CMP_NE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19083             :   { 14520 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19084             :   { 14550 /* v_cmp_ne_u32 */, AMDGPU::V_CMP_NE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19085             :   { 14610 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19086             :   { 14642 /* v_cmp_neq_f32 */, AMDGPU::V_CMP_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19087             :   { 14706 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19088             :   { 14738 /* v_cmp_nge_f32 */, AMDGPU::V_CMP_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19089             :   { 14802 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19090             :   { 14834 /* v_cmp_ngt_f32 */, AMDGPU::V_CMP_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19091             :   { 14898 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19092             :   { 14930 /* v_cmp_nle_f32 */, AMDGPU::V_CMP_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19093             :   { 14994 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19094             :   { 15026 /* v_cmp_nlg_f32 */, AMDGPU::V_CMP_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19095             :   { 15090 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19096             :   { 15122 /* v_cmp_nlt_f32 */, AMDGPU::V_CMP_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19097             :   { 15186 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19098             :   { 15214 /* v_cmp_o_f32 */, AMDGPU::V_CMP_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19099             :   { 15270 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19100             :   { 15298 /* v_cmp_t_i32 */, AMDGPU::V_CMP_T_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19101             :   { 15354 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19102             :   { 15382 /* v_cmp_t_u32 */, AMDGPU::V_CMP_T_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19103             :   { 15438 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19104             :   { 15470 /* v_cmp_tru_f32 */, AMDGPU::V_CMP_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19105             :   { 15534 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19106             :   { 15562 /* v_cmp_u_f32 */, AMDGPU::V_CMP_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19107             :   { 17762 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19108             :   { 17800 /* v_cmpx_class_f32 */, AMDGPU::V_CMPX_CLASS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19109             :   { 17876 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19110             :   { 17908 /* v_cmpx_eq_f32 */, AMDGPU::V_CMPX_EQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19111             :   { 17972 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19112             :   { 18004 /* v_cmpx_eq_i32 */, AMDGPU::V_CMPX_EQ_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19113             :   { 18068 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19114             :   { 18100 /* v_cmpx_eq_u32 */, AMDGPU::V_CMPX_EQ_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19115             :   { 18164 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19116             :   { 18194 /* v_cmpx_f_f32 */, AMDGPU::V_CMPX_F_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19117             :   { 18254 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19118             :   { 18284 /* v_cmpx_f_i32 */, AMDGPU::V_CMPX_F_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19119             :   { 18344 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19120             :   { 18374 /* v_cmpx_f_u32 */, AMDGPU::V_CMPX_F_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19121             :   { 18434 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19122             :   { 18466 /* v_cmpx_ge_f32 */, AMDGPU::V_CMPX_GE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19123             :   { 18530 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19124             :   { 18562 /* v_cmpx_ge_i32 */, AMDGPU::V_CMPX_GE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19125             :   { 18626 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19126             :   { 18658 /* v_cmpx_ge_u32 */, AMDGPU::V_CMPX_GE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19127             :   { 18722 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19128             :   { 18754 /* v_cmpx_gt_f32 */, AMDGPU::V_CMPX_GT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19129             :   { 18818 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19130             :   { 18850 /* v_cmpx_gt_i32 */, AMDGPU::V_CMPX_GT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19131             :   { 18914 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19132             :   { 18946 /* v_cmpx_gt_u32 */, AMDGPU::V_CMPX_GT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19133             :   { 19010 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19134             :   { 19042 /* v_cmpx_le_f32 */, AMDGPU::V_CMPX_LE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19135             :   { 19106 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19136             :   { 19138 /* v_cmpx_le_i32 */, AMDGPU::V_CMPX_LE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19137             :   { 19202 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19138             :   { 19234 /* v_cmpx_le_u32 */, AMDGPU::V_CMPX_LE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19139             :   { 19298 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19140             :   { 19330 /* v_cmpx_lg_f32 */, AMDGPU::V_CMPX_LG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19141             :   { 19394 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19142             :   { 19426 /* v_cmpx_lt_f32 */, AMDGPU::V_CMPX_LT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19143             :   { 19490 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19144             :   { 19522 /* v_cmpx_lt_i32 */, AMDGPU::V_CMPX_LT_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19145             :   { 19586 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19146             :   { 19618 /* v_cmpx_lt_u32 */, AMDGPU::V_CMPX_LT_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19147             :   { 19682 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19148             :   { 19714 /* v_cmpx_ne_i32 */, AMDGPU::V_CMPX_NE_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19149             :   { 19778 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19150             :   { 19810 /* v_cmpx_ne_u32 */, AMDGPU::V_CMPX_NE_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19151             :   { 19874 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19152             :   { 19908 /* v_cmpx_neq_f32 */, AMDGPU::V_CMPX_NEQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19153             :   { 19976 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19154             :   { 20010 /* v_cmpx_nge_f32 */, AMDGPU::V_CMPX_NGE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19155             :   { 20078 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19156             :   { 20112 /* v_cmpx_ngt_f32 */, AMDGPU::V_CMPX_NGT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19157             :   { 20180 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19158             :   { 20214 /* v_cmpx_nle_f32 */, AMDGPU::V_CMPX_NLE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19159             :   { 20282 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19160             :   { 20316 /* v_cmpx_nlg_f32 */, AMDGPU::V_CMPX_NLG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19161             :   { 20384 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19162             :   { 20418 /* v_cmpx_nlt_f32 */, AMDGPU::V_CMPX_NLT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19163             :   { 20486 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19164             :   { 20516 /* v_cmpx_o_f32 */, AMDGPU::V_CMPX_O_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19165             :   { 20576 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19166             :   { 20606 /* v_cmpx_t_i32 */, AMDGPU::V_CMPX_T_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19167             :   { 20666 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19168             :   { 20696 /* v_cmpx_t_u32 */, AMDGPU::V_CMPX_T_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19169             :   { 20756 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19170             :   { 20790 /* v_cmpx_tru_f32 */, AMDGPU::V_CMPX_TRU_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19171             :   { 20858 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19172             :   { 20888 /* v_cmpx_u_f32 */, AMDGPU::V_CMPX_U_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOPC, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_SReg_64, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19173             :   { 20948 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19174             :   { 20962 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19175             :   { 20972 /* v_cos_f32 */, AMDGPU::V_COS_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19176             :   { 21034 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19177             :   { 21048 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19178             :   { 21062 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19179             :   { 21076 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19180             :   { 21104 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19181             :   { 21118 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19182             :   { 21132 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19183             :   { 21149 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19184             :   { 21166 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19185             :   { 21183 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19186             :   { 21242 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19187             :   { 21260 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19188             :   { 21274 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19189             :   { 21302 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19190             :   { 21321 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19191             :   { 21340 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19192             :   { 21532 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19193             :   { 21550 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19194             :   { 21564 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19195             :   { 21826 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19196             :   { 21836 /* v_exp_f32 */, AMDGPU::V_EXP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19197             :   { 21846 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19198             :   { 21863 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19199             :   { 21874 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19200             :   { 21885 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19201             :   { 21896 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19202             :   { 21908 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19203             :   { 22036 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19204             :   { 22048 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19205             :   { 22072 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19206             :   { 22092 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19207             :   { 22132 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19208             :   { 22149 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19209             :   { 22307 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19210             :   { 22369 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19211             :   { 22379 /* v_log_f32 */, AMDGPU::V_LOG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19212             :   { 22389 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19213             :   { 22457 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19214             :   { 22471 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19215             :   { 22521 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19216             :   { 22535 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19217             :   { 22952 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19218             :   { 22962 /* v_max_f32 */, AMDGPU::V_MAX_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19219             :   { 22982 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19220             :   { 22992 /* v_max_i32 */, AMDGPU::V_MAX_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19221             :   { 23019 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19222             :   { 23029 /* v_max_u32 */, AMDGPU::V_MAX_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19223             :   { 23209 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19224             :   { 23219 /* v_min_f32 */, AMDGPU::V_MIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19225             :   { 23239 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19226             :   { 23249 /* v_min_i32 */, AMDGPU::V_MIN_I32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19227             :   { 23276 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19228             :   { 23286 /* v_min_u32 */, AMDGPU::V_MIN_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19229             :   { 23296 /* v_mov_b32 */, AMDGPU::V_MOV_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19230             :   { 23306 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19231             :   { 23406 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19232             :   { 23416 /* v_mul_f32 */, AMDGPU::V_MUL_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19233             :   { 23449 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19234             :   { 23479 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19235             :   { 23496 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19236             :   { 23510 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19237             :   { 23540 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19238             :   { 23566 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19239             :   { 23593 /* v_nop */, AMDGPU::V_NOP_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, {  }, },
   19240             :   { 23599 /* v_not_b32 */, AMDGPU::V_NOT_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19241             :   { 23619 /* v_or_b32 */, AMDGPU::V_OR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19242             :   { 23965 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19243             :   { 23975 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19244             :   { 23995 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19245             :   { 24063 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19246             :   { 24075 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19247             :   { 24131 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19248             :   { 24141 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19249             :   { 24219 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19250             :   { 24235 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19251             :   { 24262 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19252             :   { 24272 /* v_sin_f32 */, AMDGPU::V_SIN_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19253             :   { 24282 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19254             :   { 24293 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19255             :   { 24315 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19256             :   { 24328 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19257             :   { 24338 /* v_sub_f32 */, AMDGPU::V_SUB_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19258             :   { 24368 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19259             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19260             :   { 24388 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19261             :   { 24413 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_VCC, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19262             :   { 24444 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2b, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19263             :   { 24460 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19264             :   { 24473 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19265             :   { 24499 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19266             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19267             :   { 24553 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19268             :   { 24565 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP1, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithFP32InputMods, MCK_ImmClampSI, MCK_ImmOModSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
   19269             :   { 24615 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasDLInsts|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19270             :   { 24626 /* v_xor_b32 */, AMDGPU::V_XOR_B32_sdwa_gfx9, ConvertCustom_cvtSdwaVOP2, Feature_HasSDWA9|Feature_HasSDWA9, { MCK_VGPR_32, MCK_SDWAWithInt32InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
   19271             : };
   19272             : 
   19273             : static const MatchEntry MatchTable4[] = {
   19274             :   { 12279 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19275             :   { 12292 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19276             :   { 12302 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19277             :   { 12357 /* v_add_u16 */, AMDGPU::V_ADD_U16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19278             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19279             :   { 12367 /* v_add_u32 */, AMDGPU::V_ADD_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19280             :   { 12377 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19281             :   { 12391 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19282             :   { 12433 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19283             :   { 12478 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19284             :   { 12492 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19285             :   { 12575 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19286             :   { 12587 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19287             :   { 12598 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19288             :   { 20948 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19289             :   { 20962 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19290             :   { 20972 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19291             :   { 21034 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19292             :   { 21048 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19293             :   { 21062 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19294             :   { 21076 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19295             :   { 21104 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19296             :   { 21118 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19297             :   { 21132 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19298             :   { 21149 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19299             :   { 21166 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19300             :   { 21183 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19301             :   { 21242 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19302             :   { 21260 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19303             :   { 21274 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19304             :   { 21302 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19305             :   { 21321 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19306             :   { 21340 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19307             :   { 21532 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19308             :   { 21550 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19309             :   { 21564 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19310             :   { 21826 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19311             :   { 21836 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19312             :   { 21846 /* v_exp_legacy_f32 */, AMDGPU::V_EXP_LEGACY_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19313             :   { 21863 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19314             :   { 21874 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19315             :   { 21885 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19316             :   { 21896 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19317             :   { 21908 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19318             :   { 22025 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDLInsts|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19319             :   { 22036 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19320             :   { 22048 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19321             :   { 22072 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19322             :   { 22092 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19323             :   { 22132 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19324             :   { 22149 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19325             :   { 22307 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19326             :   { 22369 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19327             :   { 22379 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19328             :   { 22389 /* v_log_legacy_f32 */, AMDGPU::V_LOG_LEGACY_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19329             :   { 22457 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19330             :   { 22471 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19331             :   { 22521 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19332             :   { 22535 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19333             :   { 22563 /* v_mac_f16 */, AMDGPU::V_MAC_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19334             :   { 22573 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19335             :   { 22952 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19336             :   { 22962 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19337             :   { 22982 /* v_max_i16 */, AMDGPU::V_MAX_I16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19338             :   { 22992 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19339             :   { 23019 /* v_max_u16 */, AMDGPU::V_MAX_U16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19340             :   { 23029 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19341             :   { 23209 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19342             :   { 23219 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19343             :   { 23239 /* v_min_i16 */, AMDGPU::V_MIN_I16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19344             :   { 23249 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19345             :   { 23276 /* v_min_u16 */, AMDGPU::V_MIN_U16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19346             :   { 23286 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19347             :   { 23296 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19348             :   { 23306 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19349             :   { 23406 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19350             :   { 23416 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19351             :   { 23449 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19352             :   { 23479 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19353             :   { 23496 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19354             :   { 23510 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19355             :   { 23540 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19356             :   { 23566 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19357             :   { 23593 /* v_nop */, AMDGPU::V_NOP_dpp, Convert__ImmDPPCtrl1_0__ImmRowMask1_1__ImmBankMask1_2__ImmBoundCtrl1_3, Feature_HasDPP|Feature_HasDPP, { MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19358             :   { 23599 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19359             :   { 23619 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19360             :   { 23965 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19361             :   { 23975 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19362             :   { 23995 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19363             :   { 24063 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19364             :   { 24075 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19365             :   { 24131 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19366             :   { 24141 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19367             :   { 24219 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19368             :   { 24235 /* v_screen_partition_4se_b32 */, AMDGPU::V_SCREEN_PARTITION_4SE_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19369             :   { 24262 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19370             :   { 24272 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19371             :   { 24282 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19372             :   { 24293 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19373             :   { 24315 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19374             :   { 24328 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19375             :   { 24338 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19376             :   { 24368 /* v_sub_u16 */, AMDGPU::V_SUB_U16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19377             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19378             :   { 24378 /* v_sub_u32 */, AMDGPU::V_SUB_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19379             :   { 24388 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19380             :   { 24402 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19381             :   { 24413 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19382             :   { 24430 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19383             :   { 24444 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19384             :   { 24460 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19385             :   { 24473 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19386             :   { 24499 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19387             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19388             :   { 24512 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19389             :   { 24553 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19390             :   { 24565 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp, ConvertCustom_cvtDPP, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19391             :   { 24615 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDLInsts|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19392             :   { 24626 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, Feature_HasDPP|Feature_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
   19393             : };
   19394             : 
   19395             : #include "llvm/Support/Debug.h"
   19396             : #include "llvm/Support/Format.h"
   19397             : 
   19398      216633 : unsigned AMDGPUAsmParser::
   19399             : MatchInstructionImpl(const OperandVector &Operands,
   19400             :                      MCInst &Inst,
   19401             :                      uint64_t &ErrorInfo,
   19402             :                      bool matchingInlineAsm, unsigned VariantID) {
   19403             :   // Eliminate obvious mismatches.
   19404      216633 :   if (Operands.size() > 14) {
   19405           0 :     ErrorInfo = 14;
   19406           0 :     return Match_InvalidOperand;
   19407             :   }
   19408             : 
   19409             :   // Get the current feature set.
   19410      216633 :   uint64_t AvailableFeatures = getAvailableFeatures();
   19411             : 
   19412             :   // Get the instruction mnemonic, which is the first token.
   19413      216633 :   StringRef Mnemonic = ((AMDGPUOperand&)*Operands[0]).getToken();
   19414             : 
   19415             :   // Process all MnemonicAliases to remap the mnemonic.
   19416      216633 :   applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
   19417             : 
   19418             :   // Some state to try to produce better error messages.
   19419             :   bool HadMatchOtherThanFeatures = false;
   19420             :   bool HadMatchOtherThanPredicate = false;
   19421             :   unsigned RetCode = Match_InvalidOperand;
   19422             :   uint64_t MissingFeatures = ~0ULL;
   19423             :   // Set ErrorInfo to the operand that mismatches if it is
   19424             :   // wrong for all instances of the instruction.
   19425      216633 :   ErrorInfo = ~0ULL;
   19426      216633 :   SmallBitVector OptionalOperandsMask(13);
   19427             :   // Find the appropriate table for this asm variant.
   19428             :   const MatchEntry *Start, *End;
   19429      216633 :   switch (VariantID) {
   19430           0 :   default: llvm_unreachable("invalid variant!");
   19431             :   case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
   19432       67097 :   case 1: Start = std::begin(MatchTable1); End = std::end(MatchTable1); break;
   19433       27994 :   case 2: Start = std::begin(MatchTable2); End = std::end(MatchTable2); break;
   19434       22316 :   case 3: Start = std::begin(MatchTable3); End = std::end(MatchTable3); break;
   19435       12633 :   case 4: Start = std::begin(MatchTable4); End = std::end(MatchTable4); break;
   19436             :   }
   19437             :   // Search the table.
   19438             :   auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
   19439             : 
   19440             :   DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
   19441             :   std::distance(MnemonicRange.first, MnemonicRange.second) << 
   19442             :   " encodings with mnemonic '" << Mnemonic << "'\n");
   19443             : 
   19444             :   // Return a more specific error code if no mnemonics match.
   19445      216633 :   if (MnemonicRange.first == MnemonicRange.second)
   19446             :     return Match_MnemonicFail;
   19447             : 
   19448      137670 :   for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
   19449      327606 :        it != ie; ++it) {
   19450      298038 :     bool HasRequiredFeatures =
   19451      298038 :       (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures;
   19452             :     DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
   19453             :                                           << MII.getName(it->Opcode) << "\n");
   19454             :     // equal_range guarantees that instruction mnemonic matches.
   19455             :     assert(Mnemonic == it->getMnemonic());
   19456             :     bool OperandsValid = true;
   19457      298038 :     OptionalOperandsMask.reset(0, 13);
   19458     1229954 :     for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 13; ++FormalIdx) {
   19459     1229830 :       auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
   19460             :       DEBUG_WITH_TYPE("asm-matcher",
   19461             :                       dbgs() << "  Matching formal operand class " << getMatchClassName(Formal)
   19462             :                              << " against actual operand at index " << ActualIdx);
   19463     1229830 :       if (ActualIdx < Operands.size())
   19464             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
   19465             :                         Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
   19466             :       else
   19467             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
   19468     1229830 :       if (ActualIdx >= Operands.size()) {
   19469             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
   19470      231929 :         OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
   19471         759 :         if (!OperandsValid) ErrorInfo = ActualIdx;
   19472      231929 :         OptionalOperandsMask.set(FormalIdx, 13);
   19473      231929 :         break;
   19474             :       }
   19475             :       MCParsedAsmOperand &Actual = *Operands[ActualIdx];
   19476      997901 :       unsigned Diag = validateOperandClass(Actual, Formal);
   19477      997901 :       if (Diag == Match_Success) {
   19478             :         DEBUG_WITH_TYPE("asm-matcher",
   19479             :                         dbgs() << "match success using generic matcher\n");
   19480      877740 :         ++ActualIdx;
   19481      877740 :         continue;
   19482             :       }
   19483             :       // If the generic handler indicates an invalid operand
   19484             :       // failure, check for a special case.
   19485             :       if (Diag != Match_Success) {
   19486      120161 :         unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
   19487      120161 :         if (TargetDiag == Match_Success) {
   19488             :           DEBUG_WITH_TYPE("asm-matcher",
   19489             :                           dbgs() << "match success using target matcher\n");
   19490        3664 :           ++ActualIdx;
   19491        3664 :           continue;
   19492             :         }
   19493             :         // If the target matcher returned a specific error code use
   19494             :         // that, else use the one from the generic matcher.
   19495      116497 :         if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
   19496             :           Diag = TargetDiag;
   19497             :       }
   19498             :       // If current formal operand wasn't matched and it is optional
   19499             :       // then try to match next formal operand
   19500      116497 :       if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
   19501       50512 :         OptionalOperandsMask.set(FormalIdx);
   19502             :         DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
   19503       50512 :         continue;
   19504             :       }
   19505             :       // If this operand is broken for all of the instances of this
   19506             :       // mnemonic, keep track of it so we can report loc info.
   19507             :       // If we already had a match that only failed due to a
   19508             :       // target predicate, that diagnostic is preferred.
   19509       65985 :       if (!HadMatchOtherThanPredicate &&
   19510       41189 :           (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
   19511       62282 :         if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
   19512             :           RetCode = Diag;
   19513       62282 :         ErrorInfo = ActualIdx;
   19514             :       }
   19515             :       // Otherwise, just reject this instance of the mnemonic.
   19516             :       OperandsValid = false;
   19517             :       break;
   19518             :     }
   19519             : 
   19520      298038 :     if (!OperandsValid) {
   19521             :       DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
   19522             :                                                "operand mismatches, ignoring "
   19523             :                                                "this opcode\n");
   19524             :       continue;
   19525             :     }
   19526      231294 :     if (!HasRequiredFeatures) {
   19527             :       HadMatchOtherThanFeatures = true;
   19528       70902 :       uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
   19529             :       DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: "
   19530             :                                             << format_hex(NewMissingFeatures, 18)
   19531             :                                             << "\n");
   19532       70902 :       if (countPopulation(NewMissingFeatures) <=
   19533             :           countPopulation(MissingFeatures))
   19534             :         MissingFeatures = NewMissingFeatures;
   19535       70902 :       continue;
   19536             :     }
   19537             : 
   19538             :     Inst.clear();
   19539             : 
   19540      160392 :     Inst.setOpcode(it->Opcode);
   19541             :     // We have a potential match but have not rendered the operands.
   19542             :     // Check the target predicate to handle any context sensitive
   19543             :     // constraints.
   19544             :     // For example, Ties that are referenced multiple times must be
   19545             :     // checked here to ensure the input is the same for each match
   19546             :     // constraints. If we leave it any later the ties will have been
   19547             :     // canonicalized
   19548             :     unsigned MatchResult;
   19549      160392 :     if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
   19550             :       Inst.clear();
   19551             :       DEBUG_WITH_TYPE(
   19552             :           "asm-matcher",
   19553             :           dbgs() << "Early target match predicate failed with diag code "
   19554             :                  << MatchResult << "\n");
   19555             :       RetCode = MatchResult;
   19556             :       HadMatchOtherThanPredicate = true;
   19557             :       continue;
   19558             :     }
   19559             : 
   19560      160392 :     if (matchingInlineAsm) {
   19561           0 :       convertToMapAndConstraints(it->ConvertFn, Operands);
   19562           0 :       if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
   19563             :         return Match_InvalidTiedOperand;
   19564             : 
   19565           0 :       return Match_Success;
   19566             :     }
   19567             : 
   19568             :     // We have selected a definite instruction, convert the parsed
   19569             :     // operands into the appropriate MCInst.
   19570      160392 :     convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
   19571             :                     OptionalOperandsMask);
   19572             : 
   19573             :     // We have a potential match. Check the target predicate to
   19574             :     // handle any context sensitive constraints.
   19575      160392 :     if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
   19576             :       DEBUG_WITH_TYPE("asm-matcher",
   19577             :                       dbgs() << "Target match predicate failed with diag code "
   19578             :                              << MatchResult << "\n");
   19579             :       Inst.clear();
   19580             :       RetCode = MatchResult;
   19581             :       HadMatchOtherThanPredicate = true;
   19582          24 :       continue;
   19583             :     }
   19584             : 
   19585      160368 :     if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
   19586           0 :       return Match_InvalidTiedOperand;
   19587             : 
   19588             :     DEBUG_WITH_TYPE(
   19589             :         "asm-matcher",
   19590             :         dbgs() << "Opcode result: complete match, selecting this opcode\n");
   19591             :     return Match_Success;
   19592             :   }
   19593             : 
   19594             :   // Okay, we had no match.  Try to return a useful error code.
   19595       29568 :   if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
   19596             :     return RetCode;
   19597             : 
   19598             :   // Missing feature matches return which features were missing
   19599       11480 :   ErrorInfo = MissingFeatures;
   19600       11480 :   return Match_MissingFeature;
   19601             : }
   19602             : 
   19603             : namespace {
   19604             :   struct OperandMatchEntry {
   19605             :     uint64_t RequiredFeatures;
   19606             :     uint16_t Mnemonic;
   19607             :     uint8_t Class;
   19608             :     uint16_t OperandMask;
   19609             : 
   19610           0 :     StringRef getMnemonic() const {
   19611           0 :       return StringRef(MnemonicTable + Mnemonic + 1,
   19612           0 :                        MnemonicTable[Mnemonic]);
   19613             :     }
   19614             :   };
   19615             : 
   19616             :   // Predicate for searching for an opcode.
   19617             :   struct LessOpcodeOperand {
   19618           0 :     bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
   19619           0 :       return LHS.getMnemonic()  < RHS;
   19620             :     }
   19621           0 :     bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
   19622           0 :       return LHS < RHS.getMnemonic();
   19623             :     }
   19624             :     bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
   19625             :       return LHS.getMnemonic() < RHS.getMnemonic();
   19626             :     }
   19627             :   };
   19628             : } // end anonymous namespace.
   19629             : 
   19630             : static const OperandMatchEntry OperandMatchTable[18557] = {
   19631             :   /* Operand List Mask, Mnemonic, Operand Class, Features */
   19632             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 16 /* 4 */ },
   19633             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 32 /* 5 */ },
   19634             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 16 /* 4 */ },
   19635             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 32 /* 5 */ },
   19636             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 16 /* 4 */ },
   19637             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   19638             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 16 /* 4 */ },
   19639             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   19640             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19641             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   19642             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19643             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   19644             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19645             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   19646             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19647             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   19648             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19649             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   19650             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19651             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 128 /* 7 */ },
   19652             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 64 /* 6 */ },
   19653             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 128 /* 7 */ },
   19654             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 64 /* 6 */ },
   19655             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 128 /* 7 */ },
   19656             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19657             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 128 /* 7 */ },
   19658             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19659             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 128 /* 7 */ },
   19660             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19661             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 128 /* 7 */ },
   19662             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 32 /* 5 */ },
   19663             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 128 /* 7 */ },
   19664             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 64 /* 6 */ },
   19665             :   { Feature_isGCN|Feature_isSICI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 256 /* 8 */ },
   19666             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmOffset, 64 /* 6 */ },
   19667             :   { Feature_isGCN|Feature_isVI, 0 /* buffer_atomic_add */, MCK_ImmSLC, 256 /* 8 */ },
   19668             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19669             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19670             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19671             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19672             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19673             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19674             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19675             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19676             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19677             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19678             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19679             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19680             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19681             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19682             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19683             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19684             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19685             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19686             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19687             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19688             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19689             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19690             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19691             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19692             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19693             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19694             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19695             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19696             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19697             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19698             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19699             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19700             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19701             :   { Feature_isGCN|Feature_isSICI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19702             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19703             :   { Feature_isGCN|Feature_isVI, 18 /* buffer_atomic_add_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19704             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 16 /* 4 */ },
   19705             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 32 /* 5 */ },
   19706             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 16 /* 4 */ },
   19707             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 32 /* 5 */ },
   19708             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 16 /* 4 */ },
   19709             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   19710             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 16 /* 4 */ },
   19711             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   19712             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19713             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   19714             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19715             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   19716             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19717             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   19718             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19719             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   19720             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19721             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   19722             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19723             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 128 /* 7 */ },
   19724             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 64 /* 6 */ },
   19725             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 128 /* 7 */ },
   19726             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 64 /* 6 */ },
   19727             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 128 /* 7 */ },
   19728             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19729             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 128 /* 7 */ },
   19730             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19731             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 128 /* 7 */ },
   19732             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19733             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 128 /* 7 */ },
   19734             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 32 /* 5 */ },
   19735             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 128 /* 7 */ },
   19736             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 64 /* 6 */ },
   19737             :   { Feature_isGCN|Feature_isSICI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 256 /* 8 */ },
   19738             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmOffset, 64 /* 6 */ },
   19739             :   { Feature_isGCN|Feature_isVI, 39 /* buffer_atomic_and */, MCK_ImmSLC, 256 /* 8 */ },
   19740             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19741             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19742             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19743             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19744             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19745             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19746             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19747             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19748             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19749             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19750             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19751             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19752             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19753             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19754             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19755             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19756             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19757             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19758             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19759             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19760             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19761             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19762             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19763             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19764             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19765             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19766             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19767             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19768             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19769             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19770             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19771             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19772             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19773             :   { Feature_isGCN|Feature_isSICI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19774             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19775             :   { Feature_isGCN|Feature_isVI, 57 /* buffer_atomic_and_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19776             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 16 /* 4 */ },
   19777             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 32 /* 5 */ },
   19778             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 16 /* 4 */ },
   19779             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 32 /* 5 */ },
   19780             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 16 /* 4 */ },
   19781             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   19782             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 16 /* 4 */ },
   19783             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   19784             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19785             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   19786             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19787             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   19788             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19789             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   19790             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19791             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   19792             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19793             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   19794             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19795             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 128 /* 7 */ },
   19796             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 64 /* 6 */ },
   19797             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 128 /* 7 */ },
   19798             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 64 /* 6 */ },
   19799             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 128 /* 7 */ },
   19800             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19801             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 128 /* 7 */ },
   19802             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19803             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 128 /* 7 */ },
   19804             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19805             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 128 /* 7 */ },
   19806             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 32 /* 5 */ },
   19807             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 128 /* 7 */ },
   19808             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 64 /* 6 */ },
   19809             :   { Feature_isGCN|Feature_isSICI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 256 /* 8 */ },
   19810             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmOffset, 64 /* 6 */ },
   19811             :   { Feature_isGCN|Feature_isVI, 78 /* buffer_atomic_cmpswap */, MCK_ImmSLC, 256 /* 8 */ },
   19812             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19813             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19814             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19815             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19816             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19817             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19818             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19819             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19820             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19821             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19822             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19823             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19824             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19825             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19826             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19827             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19828             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19829             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19830             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19831             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19832             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19833             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19834             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19835             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19836             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19837             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19838             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19839             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19840             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19841             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19842             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19843             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19844             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19845             :   { Feature_isGCN|Feature_isSICI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19846             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19847             :   { Feature_isGCN|Feature_isVI, 100 /* buffer_atomic_cmpswap_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19848             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 16 /* 4 */ },
   19849             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 32 /* 5 */ },
   19850             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 16 /* 4 */ },
   19851             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 32 /* 5 */ },
   19852             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 16 /* 4 */ },
   19853             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   19854             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 16 /* 4 */ },
   19855             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   19856             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19857             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   19858             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19859             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   19860             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19861             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   19862             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19863             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   19864             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19865             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   19866             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19867             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 128 /* 7 */ },
   19868             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 64 /* 6 */ },
   19869             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 128 /* 7 */ },
   19870             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 64 /* 6 */ },
   19871             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 128 /* 7 */ },
   19872             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19873             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 128 /* 7 */ },
   19874             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19875             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 128 /* 7 */ },
   19876             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19877             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 128 /* 7 */ },
   19878             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 32 /* 5 */ },
   19879             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 128 /* 7 */ },
   19880             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 64 /* 6 */ },
   19881             :   { Feature_isGCN|Feature_isSICI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 256 /* 8 */ },
   19882             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmOffset, 64 /* 6 */ },
   19883             :   { Feature_isGCN|Feature_isVI, 125 /* buffer_atomic_dec */, MCK_ImmSLC, 256 /* 8 */ },
   19884             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19885             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19886             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19887             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19888             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19889             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19890             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19891             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19892             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19893             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19894             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19895             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19896             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19897             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19898             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19899             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19900             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19901             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19902             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19903             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19904             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19905             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19906             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19907             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19908             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19909             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19910             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19911             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19912             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19913             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19914             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19915             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19916             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19917             :   { Feature_isGCN|Feature_isSICI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19918             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19919             :   { Feature_isGCN|Feature_isVI, 143 /* buffer_atomic_dec_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19920             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 16 /* 4 */ },
   19921             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 32 /* 5 */ },
   19922             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 16 /* 4 */ },
   19923             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 32 /* 5 */ },
   19924             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 16 /* 4 */ },
   19925             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   19926             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 16 /* 4 */ },
   19927             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   19928             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19929             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   19930             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19931             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   19932             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19933             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   19934             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19935             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   19936             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19937             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   19938             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19939             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 128 /* 7 */ },
   19940             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 64 /* 6 */ },
   19941             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 128 /* 7 */ },
   19942             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 64 /* 6 */ },
   19943             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 128 /* 7 */ },
   19944             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19945             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 128 /* 7 */ },
   19946             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19947             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 128 /* 7 */ },
   19948             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19949             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 128 /* 7 */ },
   19950             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 32 /* 5 */ },
   19951             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 128 /* 7 */ },
   19952             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 64 /* 6 */ },
   19953             :   { Feature_isGCN|Feature_isSICI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 256 /* 8 */ },
   19954             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmOffset, 64 /* 6 */ },
   19955             :   { Feature_isGCN|Feature_isVI, 164 /* buffer_atomic_inc */, MCK_ImmSLC, 256 /* 8 */ },
   19956             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19957             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19958             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19959             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   19960             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19961             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19962             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   19963             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19964             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19965             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19966             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19967             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19968             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19969             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19970             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19971             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19972             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19973             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   19974             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19975             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19976             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19977             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19978             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19979             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19980             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19981             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19982             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19983             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19984             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19985             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19986             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   19987             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   19988             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19989             :   { Feature_isGCN|Feature_isSICI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19990             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   19991             :   { Feature_isGCN|Feature_isVI, 182 /* buffer_atomic_inc_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   19992             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 16 /* 4 */ },
   19993             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 32 /* 5 */ },
   19994             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 16 /* 4 */ },
   19995             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 32 /* 5 */ },
   19996             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 16 /* 4 */ },
   19997             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   19998             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 16 /* 4 */ },
   19999             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   20000             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20001             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   20002             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20003             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   20004             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20005             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   20006             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20007             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   20008             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20009             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   20010             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20011             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 128 /* 7 */ },
   20012             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 64 /* 6 */ },
   20013             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 128 /* 7 */ },
   20014             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 64 /* 6 */ },
   20015             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 128 /* 7 */ },
   20016             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20017             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 128 /* 7 */ },
   20018             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20019             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 128 /* 7 */ },
   20020             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20021             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 128 /* 7 */ },
   20022             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 32 /* 5 */ },
   20023             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 128 /* 7 */ },
   20024             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 64 /* 6 */ },
   20025             :   { Feature_isGCN|Feature_isSICI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 256 /* 8 */ },
   20026             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmOffset, 64 /* 6 */ },
   20027             :   { Feature_isGCN|Feature_isVI, 203 /* buffer_atomic_or */, MCK_ImmSLC, 256 /* 8 */ },
   20028             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20029             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20030             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20031             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20032             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20033             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20034             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20035             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20036             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20037             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20038             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20039             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20040             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20041             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20042             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20043             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20044             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20045             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20046             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20047             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20048             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20049             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20050             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20051             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20052             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20053             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20054             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20055             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20056             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20057             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20058             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20059             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20060             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20061             :   { Feature_isGCN|Feature_isSICI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20062             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20063             :   { Feature_isGCN|Feature_isVI, 220 /* buffer_atomic_or_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20064             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 16 /* 4 */ },
   20065             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 32 /* 5 */ },
   20066             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 16 /* 4 */ },
   20067             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 32 /* 5 */ },
   20068             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 16 /* 4 */ },
   20069             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   20070             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 16 /* 4 */ },
   20071             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   20072             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20073             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   20074             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20075             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   20076             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20077             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   20078             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20079             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   20080             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20081             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   20082             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20083             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 128 /* 7 */ },
   20084             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 64 /* 6 */ },
   20085             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 128 /* 7 */ },
   20086             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 64 /* 6 */ },
   20087             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 128 /* 7 */ },
   20088             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20089             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 128 /* 7 */ },
   20090             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20091             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 128 /* 7 */ },
   20092             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20093             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 128 /* 7 */ },
   20094             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 32 /* 5 */ },
   20095             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 128 /* 7 */ },
   20096             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 64 /* 6 */ },
   20097             :   { Feature_isGCN|Feature_isSICI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 256 /* 8 */ },
   20098             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmOffset, 64 /* 6 */ },
   20099             :   { Feature_isGCN|Feature_isVI, 240 /* buffer_atomic_smax */, MCK_ImmSLC, 256 /* 8 */ },
   20100             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20101             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20102             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20103             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20104             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20105             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20106             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20107             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20108             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20109             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20110             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20111             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20112             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20113             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20114             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20115             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20116             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20117             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20118             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20119             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20120             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20121             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20122             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20123             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20124             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20125             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20126             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20127             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20128             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20129             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20130             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20131             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20132             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20133             :   { Feature_isGCN|Feature_isSICI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20134             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20135             :   { Feature_isGCN|Feature_isVI, 259 /* buffer_atomic_smax_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20136             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 16 /* 4 */ },
   20137             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 32 /* 5 */ },
   20138             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 16 /* 4 */ },
   20139             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 32 /* 5 */ },
   20140             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 16 /* 4 */ },
   20141             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   20142             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 16 /* 4 */ },
   20143             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   20144             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20145             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   20146             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20147             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   20148             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20149             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   20150             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20151             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   20152             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20153             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   20154             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20155             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 128 /* 7 */ },
   20156             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 64 /* 6 */ },
   20157             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 128 /* 7 */ },
   20158             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 64 /* 6 */ },
   20159             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 128 /* 7 */ },
   20160             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20161             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 128 /* 7 */ },
   20162             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20163             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 128 /* 7 */ },
   20164             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20165             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 128 /* 7 */ },
   20166             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 32 /* 5 */ },
   20167             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 128 /* 7 */ },
   20168             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 64 /* 6 */ },
   20169             :   { Feature_isGCN|Feature_isSICI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 256 /* 8 */ },
   20170             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmOffset, 64 /* 6 */ },
   20171             :   { Feature_isGCN|Feature_isVI, 281 /* buffer_atomic_smin */, MCK_ImmSLC, 256 /* 8 */ },
   20172             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20173             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20174             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20175             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20176             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20177             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20178             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20179             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20180             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20181             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20182             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20183             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20184             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20185             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20186             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20187             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20188             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20189             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20190             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20191             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20192             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20193             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20194             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20195             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20196             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20197             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20198             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20199             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20200             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20201             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20202             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20203             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20204             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20205             :   { Feature_isGCN|Feature_isSICI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20206             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20207             :   { Feature_isGCN|Feature_isVI, 300 /* buffer_atomic_smin_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20208             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 16 /* 4 */ },
   20209             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 32 /* 5 */ },
   20210             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 16 /* 4 */ },
   20211             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 32 /* 5 */ },
   20212             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 16 /* 4 */ },
   20213             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   20214             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 16 /* 4 */ },
   20215             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   20216             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20217             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   20218             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20219             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   20220             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20221             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   20222             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20223             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   20224             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20225             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   20226             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20227             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 128 /* 7 */ },
   20228             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 64 /* 6 */ },
   20229             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 128 /* 7 */ },
   20230             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 64 /* 6 */ },
   20231             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 128 /* 7 */ },
   20232             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20233             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 128 /* 7 */ },
   20234             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20235             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 128 /* 7 */ },
   20236             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20237             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 128 /* 7 */ },
   20238             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 32 /* 5 */ },
   20239             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 128 /* 7 */ },
   20240             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 64 /* 6 */ },
   20241             :   { Feature_isGCN|Feature_isSICI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 256 /* 8 */ },
   20242             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmOffset, 64 /* 6 */ },
   20243             :   { Feature_isGCN|Feature_isVI, 322 /* buffer_atomic_sub */, MCK_ImmSLC, 256 /* 8 */ },
   20244             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20245             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20246             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20247             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20248             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20249             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20250             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20251             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20252             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20253             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20254             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20255             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20256             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20257             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20258             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20259             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20260             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20261             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20262             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20263             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20264             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20265             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20266             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20267             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20268             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20269             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20270             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20271             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20272             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20273             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20274             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20275             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20276             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20277             :   { Feature_isGCN|Feature_isSICI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20278             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20279             :   { Feature_isGCN|Feature_isVI, 340 /* buffer_atomic_sub_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20280             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 16 /* 4 */ },
   20281             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 32 /* 5 */ },
   20282             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 16 /* 4 */ },
   20283             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 32 /* 5 */ },
   20284             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 16 /* 4 */ },
   20285             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   20286             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 16 /* 4 */ },
   20287             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   20288             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20289             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   20290             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20291             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   20292             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20293             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   20294             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20295             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   20296             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20297             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   20298             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20299             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 128 /* 7 */ },
   20300             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 64 /* 6 */ },
   20301             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 128 /* 7 */ },
   20302             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 64 /* 6 */ },
   20303             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 128 /* 7 */ },
   20304             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20305             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 128 /* 7 */ },
   20306             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20307             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 128 /* 7 */ },
   20308             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20309             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 128 /* 7 */ },
   20310             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 32 /* 5 */ },
   20311             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 128 /* 7 */ },
   20312             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 64 /* 6 */ },
   20313             :   { Feature_isGCN|Feature_isSICI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 256 /* 8 */ },
   20314             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmOffset, 64 /* 6 */ },
   20315             :   { Feature_isGCN|Feature_isVI, 361 /* buffer_atomic_swap */, MCK_ImmSLC, 256 /* 8 */ },
   20316             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20317             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20318             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20319             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20320             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20321             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20322             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20323             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20324             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20325             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20326             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20327             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20328             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20329             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20330             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20331             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20332             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20333             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20334             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20335             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20336             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20337             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20338             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20339             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20340             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20341             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20342             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20343             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20344             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20345             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20346             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20347             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20348             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20349             :   { Feature_isGCN|Feature_isSICI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20350             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20351             :   { Feature_isGCN|Feature_isVI, 380 /* buffer_atomic_swap_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20352             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 16 /* 4 */ },
   20353             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 32 /* 5 */ },
   20354             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 16 /* 4 */ },
   20355             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 32 /* 5 */ },
   20356             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 16 /* 4 */ },
   20357             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   20358             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 16 /* 4 */ },
   20359             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   20360             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20361             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   20362             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20363             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   20364             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20365             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   20366             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20367             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   20368             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20369             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   20370             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20371             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 128 /* 7 */ },
   20372             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 64 /* 6 */ },
   20373             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 128 /* 7 */ },
   20374             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 64 /* 6 */ },
   20375             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 128 /* 7 */ },
   20376             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20377             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 128 /* 7 */ },
   20378             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20379             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 128 /* 7 */ },
   20380             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20381             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 128 /* 7 */ },
   20382             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 32 /* 5 */ },
   20383             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 128 /* 7 */ },
   20384             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 64 /* 6 */ },
   20385             :   { Feature_isGCN|Feature_isSICI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 256 /* 8 */ },
   20386             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmOffset, 64 /* 6 */ },
   20387             :   { Feature_isGCN|Feature_isVI, 402 /* buffer_atomic_umax */, MCK_ImmSLC, 256 /* 8 */ },
   20388             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20389             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20390             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20391             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20392             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20393             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20394             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20395             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20396             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20397             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20398             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20399             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20400             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20401             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20402             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20403             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20404             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20405             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20406             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20407             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20408             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20409             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20410             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20411             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20412             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20413             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20414             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20415             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20416             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20417             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20418             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20419             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20420             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20421             :   { Feature_isGCN|Feature_isSICI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20422             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20423             :   { Feature_isGCN|Feature_isVI, 421 /* buffer_atomic_umax_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20424             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 16 /* 4 */ },
   20425             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 32 /* 5 */ },
   20426             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 16 /* 4 */ },
   20427             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 32 /* 5 */ },
   20428             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 16 /* 4 */ },
   20429             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   20430             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 16 /* 4 */ },
   20431             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   20432             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20433             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   20434             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20435             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   20436             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20437             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   20438             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20439             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   20440             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20441             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   20442             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20443             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 128 /* 7 */ },
   20444             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 64 /* 6 */ },
   20445             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 128 /* 7 */ },
   20446             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 64 /* 6 */ },
   20447             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 128 /* 7 */ },
   20448             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20449             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 128 /* 7 */ },
   20450             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20451             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 128 /* 7 */ },
   20452             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20453             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 128 /* 7 */ },
   20454             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 32 /* 5 */ },
   20455             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 128 /* 7 */ },
   20456             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 64 /* 6 */ },
   20457             :   { Feature_isGCN|Feature_isSICI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 256 /* 8 */ },
   20458             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmOffset, 64 /* 6 */ },
   20459             :   { Feature_isGCN|Feature_isVI, 443 /* buffer_atomic_umin */, MCK_ImmSLC, 256 /* 8 */ },
   20460             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20461             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20462             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20463             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20464             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20465             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20466             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20467             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20468             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20469             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20470             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20471             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20472             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20473             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20474             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20475             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20476             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20477             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20478             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20479             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20480             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20481             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20482             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20483             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20484             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20485             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20486             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20487             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20488             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20489             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20490             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20491             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20492             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20493             :   { Feature_isGCN|Feature_isSICI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20494             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20495             :   { Feature_isGCN|Feature_isVI, 462 /* buffer_atomic_umin_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20496             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 16 /* 4 */ },
   20497             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 32 /* 5 */ },
   20498             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 16 /* 4 */ },
   20499             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 32 /* 5 */ },
   20500             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 16 /* 4 */ },
   20501             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   20502             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 16 /* 4 */ },
   20503             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   20504             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20505             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   20506             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20507             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   20508             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20509             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   20510             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20511             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   20512             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20513             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   20514             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20515             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 128 /* 7 */ },
   20516             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 64 /* 6 */ },
   20517             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 128 /* 7 */ },
   20518             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 64 /* 6 */ },
   20519             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 128 /* 7 */ },
   20520             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20521             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 128 /* 7 */ },
   20522             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20523             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 128 /* 7 */ },
   20524             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20525             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 128 /* 7 */ },
   20526             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 32 /* 5 */ },
   20527             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 128 /* 7 */ },
   20528             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 64 /* 6 */ },
   20529             :   { Feature_isGCN|Feature_isSICI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 256 /* 8 */ },
   20530             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmOffset, 64 /* 6 */ },
   20531             :   { Feature_isGCN|Feature_isVI, 484 /* buffer_atomic_xor */, MCK_ImmSLC, 256 /* 8 */ },
   20532             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20533             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20534             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20535             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   20536             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20537             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20538             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 16 /* 4 */ },
   20539             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20540             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20541             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20542             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20543             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20544             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20545             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20546             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20547             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20548             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20549             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   20550             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20551             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20552             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20553             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20554             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20555             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20556             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20557             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20558             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20559             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20560             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20561             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20562             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 32 /* 5 */ },
   20563             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 128 /* 7 */ },
   20564             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20565             :   { Feature_isGCN|Feature_isSICI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20566             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmOffset, 64 /* 6 */ },
   20567             :   { Feature_isGCN|Feature_isVI, 502 /* buffer_atomic_xor_x2 */, MCK_ImmSLC, 256 /* 8 */ },
   20568             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 16 /* 4 */ },
   20569             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 32 /* 5 */ },
   20570             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 64 /* 6 */ },
   20571             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 16 /* 4 */ },
   20572             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 32 /* 5 */ },
   20573             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 64 /* 6 */ },
   20574             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 16 /* 4 */ },
   20575             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 32 /* 5 */ },
   20576             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 64 /* 6 */ },
   20577             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmTFE, 128 /* 7 */ },
   20578             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 16 /* 4 */ },
   20579             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 32 /* 5 */ },
   20580             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 64 /* 6 */ },
   20581             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmTFE, 128 /* 7 */ },
   20582             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20583             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20584             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20585             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20586             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20587             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20588             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmTFE, 256 /* 8 */ },
   20589             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20590             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20591             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20592             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20593             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20594             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20595             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20596             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20597             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20598             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmTFE, 256 /* 8 */ },
   20599             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20600             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20601             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20602             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmTFE, 256 /* 8 */ },
   20603             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20604             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20605             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20606             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20607             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20608             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20609             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20610             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20611             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20612             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmTFE, 256 /* 8 */ },
   20613             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 32 /* 5 */ },
   20614             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 64 /* 6 */ },
   20615             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 128 /* 7 */ },
   20616             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmTFE, 256 /* 8 */ },
   20617             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 64 /* 6 */ },
   20618             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 128 /* 7 */ },
   20619             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 256 /* 8 */ },
   20620             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 64 /* 6 */ },
   20621             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 128 /* 7 */ },
   20622             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 256 /* 8 */ },
   20623             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmOffset, 64 /* 6 */ },
   20624             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmGLC, 128 /* 7 */ },
   20625             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmSLC, 256 /* 8 */ },
   20626             :   { Feature_isGCN|Feature_isSICI, 523 /* buffer_load_dword */, MCK_ImmTFE, 512 /* 9 */ },
   20627             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmOffset, 64 /* 6 */ },
   20628             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmGLC, 128 /* 7 */ },
   20629             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmSLC, 256 /* 8 */ },
   20630             :   { Feature_isGCN|Feature_isVI, 523 /* buffer_load_dword */, MCK_ImmTFE, 512 /* 9 */ },
   20631             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 16 /* 4 */ },
   20632             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 32 /* 5 */ },
   20633             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 64 /* 6 */ },
   20634             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 16 /* 4 */ },
   20635             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 32 /* 5 */ },
   20636             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 64 /* 6 */ },
   20637             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 128 /* 7 */ },
   20638             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 16 /* 4 */ },
   20639             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 32 /* 5 */ },
   20640             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 64 /* 6 */ },
   20641             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 128 /* 7 */ },
   20642             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   20643             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   20644             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   20645             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   20646             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   20647             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   20648             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   20649             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   20650             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   20651             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   20652             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   20653             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   20654             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   20655             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   20656             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   20657             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   20658             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   20659             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   20660             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   20661             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   20662             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   20663             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   20664             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   20665             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   20666             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   20667             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   20668             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 64 /* 6 */ },
   20669             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 128 /* 7 */ },
   20670             :   { Feature_isVI|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 256 /* 8 */ },
   20671             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 64 /* 6 */ },
   20672             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 128 /* 7 */ },
   20673             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 256 /* 8 */ },
   20674             :   { Feature_isGCN|Feature_isSICI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 512 /* 9 */ },
   20675             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmOffset, 64 /* 6 */ },
   20676             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmGLC, 128 /* 7 */ },
   20677             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmSLC, 256 /* 8 */ },
   20678             :   { Feature_isGCN|Feature_isVI, 541 /* buffer_load_dwordx2 */, MCK_ImmTFE, 512 /* 9 */ },
   20679             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 16 /* 4 */ },
   20680             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 32 /* 5 */ },
   20681             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 64 /* 6 */ },
   20682             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 16 /* 4 */ },
   20683             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 32 /* 5 */ },
   20684             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 64 /* 6 */ },
   20685             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 128 /* 7 */ },
   20686             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 16 /* 4 */ },
   20687             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 32 /* 5 */ },
   20688             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 64 /* 6 */ },
   20689             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 128 /* 7 */ },
   20690             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   20691             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   20692             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   20693             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   20694             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   20695             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   20696             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   20697             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   20698             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   20699             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   20700             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   20701             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   20702             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   20703             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   20704             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   20705             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   20706             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   20707             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   20708             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   20709             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   20710             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   20711             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   20712             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   20713             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   20714             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   20715             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   20716             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 64 /* 6 */ },
   20717             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 128 /* 7 */ },
   20718             :   { Feature_isVI|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 256 /* 8 */ },
   20719             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 64 /* 6 */ },
   20720             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 128 /* 7 */ },
   20721             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 256 /* 8 */ },
   20722             :   { Feature_isGCN|Feature_isSICI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 512 /* 9 */ },
   20723             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmOffset, 64 /* 6 */ },
   20724             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmGLC, 128 /* 7 */ },
   20725             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmSLC, 256 /* 8 */ },
   20726             :   { Feature_isGCN|Feature_isVI, 561 /* buffer_load_dwordx3 */, MCK_ImmTFE, 512 /* 9 */ },
   20727             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 16 /* 4 */ },
   20728             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 32 /* 5 */ },
   20729             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 64 /* 6 */ },
   20730             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 16 /* 4 */ },
   20731             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 32 /* 5 */ },
   20732             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 64 /* 6 */ },
   20733             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 128 /* 7 */ },
   20734             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 16 /* 4 */ },
   20735             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 32 /* 5 */ },
   20736             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 64 /* 6 */ },
   20737             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 128 /* 7 */ },
   20738             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   20739             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   20740             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   20741             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   20742             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   20743             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   20744             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   20745             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   20746             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   20747             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   20748             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   20749             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   20750             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   20751             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   20752             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   20753             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   20754             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   20755             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   20756             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   20757             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   20758             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   20759             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   20760             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   20761             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   20762             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   20763             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   20764             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 64 /* 6 */ },
   20765             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 128 /* 7 */ },
   20766             :   { Feature_isVI|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 256 /* 8 */ },
   20767             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 64 /* 6 */ },
   20768             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 128 /* 7 */ },
   20769             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 256 /* 8 */ },
   20770             :   { Feature_isGCN|Feature_isSICI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 512 /* 9 */ },
   20771             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmOffset, 64 /* 6 */ },
   20772             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmGLC, 128 /* 7 */ },
   20773             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmSLC, 256 /* 8 */ },
   20774             :   { Feature_isGCN|Feature_isVI, 581 /* buffer_load_dwordx4 */, MCK_ImmTFE, 512 /* 9 */ },
   20775             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmOffset, 16 /* 4 */ },
   20776             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmGLC, 32 /* 5 */ },
   20777             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmSLC, 64 /* 6 */ },
   20778             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmTFE, 128 /* 7 */ },
   20779             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmOffset, 32 /* 5 */ },
   20780             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmGLC, 64 /* 6 */ },
   20781             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmSLC, 128 /* 7 */ },
   20782             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmTFE, 256 /* 8 */ },
   20783             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmOffset, 32 /* 5 */ },
   20784             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmGLC, 64 /* 6 */ },
   20785             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmSLC, 128 /* 7 */ },
   20786             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmTFE, 256 /* 8 */ },
   20787             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmOffset, 64 /* 6 */ },
   20788             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmGLC, 128 /* 7 */ },
   20789             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmSLC, 256 /* 8 */ },
   20790             :   { Feature_HasD16LoadStore|Feature_isVI, 601 /* buffer_load_format_d16_hi_x */, MCK_ImmTFE, 512 /* 9 */ },
   20791             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 16 /* 4 */ },
   20792             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 32 /* 5 */ },
   20793             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 64 /* 6 */ },
   20794             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 128 /* 7 */ },
   20795             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 16 /* 4 */ },
   20796             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 32 /* 5 */ },
   20797             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 64 /* 6 */ },
   20798             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 128 /* 7 */ },
   20799             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   20800             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   20801             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   20802             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   20803             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   20804             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   20805             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   20806             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   20807             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   20808             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   20809             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   20810             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   20811             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   20812             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   20813             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   20814             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   20815             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   20816             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   20817             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   20818             :   { Feature_HasPackedD16VMem|Feature_isVI, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   20819             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   20820             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   20821             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   20822             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 629 /* buffer_load_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   20823             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 16 /* 4 */ },
   20824             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 32 /* 5 */ },
   20825             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 64 /* 6 */ },
   20826             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 128 /* 7 */ },
   20827             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 16 /* 4 */ },
   20828             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 32 /* 5 */ },
   20829             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 64 /* 6 */ },
   20830             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 128 /* 7 */ },
   20831             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   20832             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   20833             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   20834             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   20835             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   20836             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   20837             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   20838             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   20839             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   20840             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   20841             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   20842             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   20843             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   20844             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   20845             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   20846             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   20847             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   20848             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   20849             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   20850             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   20851             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   20852             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   20853             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   20854             :   { Feature_HasPackedD16VMem|Feature_isVI, 654 /* buffer_load_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   20855             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   20856             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   20857             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   20858             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   20859             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   20860             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   20861             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   20862             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   20863             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   20864             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   20865             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   20866             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   20867             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   20868             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   20869             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   20870             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   20871             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   20872             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   20873             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   20874             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   20875             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   20876             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   20877             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   20878             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   20879             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   20880             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   20881             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   20882             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   20883             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   20884             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   20885             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   20886             :   { Feature_HasPackedD16VMem|Feature_isVI, 680 /* buffer_load_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   20887             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   20888             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   20889             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   20890             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   20891             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   20892             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   20893             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   20894             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   20895             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   20896             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   20897             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   20898             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   20899             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   20900             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   20901             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   20902             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   20903             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   20904             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   20905             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   20906             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   20907             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   20908             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   20909             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   20910             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   20911             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   20912             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   20913             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   20914             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   20915             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   20916             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   20917             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   20918             :   { Feature_HasPackedD16VMem|Feature_isVI, 707 /* buffer_load_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   20919             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 16 /* 4 */ },
   20920             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 32 /* 5 */ },
   20921             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 64 /* 6 */ },
   20922             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 16 /* 4 */ },
   20923             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 32 /* 5 */ },
   20924             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 64 /* 6 */ },
   20925             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 16 /* 4 */ },
   20926             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 32 /* 5 */ },
   20927             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 64 /* 6 */ },
   20928             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 128 /* 7 */ },
   20929             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 16 /* 4 */ },
   20930             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 32 /* 5 */ },
   20931             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 64 /* 6 */ },
   20932             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 128 /* 7 */ },
   20933             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20934             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20935             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20936             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20937             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20938             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20939             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   20940             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20941             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20942             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20943             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20944             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20945             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20946             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20947             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20948             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20949             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   20950             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20951             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20952             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20953             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   20954             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20955             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20956             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20957             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20958             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20959             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20960             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20961             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20962             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20963             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   20964             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   20965             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   20966             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   20967             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   20968             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   20969             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   20970             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   20971             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   20972             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   20973             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   20974             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   20975             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   20976             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   20977             :   { Feature_isGCN|Feature_isSICI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   20978             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   20979             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   20980             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   20981             :   { Feature_isGCN|Feature_isVI, 735 /* buffer_load_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   20982             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 16 /* 4 */ },
   20983             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 32 /* 5 */ },
   20984             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 64 /* 6 */ },
   20985             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 128 /* 7 */ },
   20986             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 16 /* 4 */ },
   20987             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 32 /* 5 */ },
   20988             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 64 /* 6 */ },
   20989             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 128 /* 7 */ },
   20990             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   20991             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   20992             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   20993             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   20994             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   20995             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   20996             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   20997             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   20998             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   20999             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21000             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21001             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21002             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21003             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21004             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21005             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21006             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21007             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21008             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21009             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21010             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   21011             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   21012             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   21013             :   { Feature_isGCN|Feature_isSICI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   21014             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   21015             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   21016             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   21017             :   { Feature_isGCN|Feature_isVI, 756 /* buffer_load_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   21018             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   21019             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   21020             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   21021             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   21022             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   21023             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   21024             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   21025             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   21026             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21027             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21028             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21029             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21030             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21031             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21032             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21033             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21034             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21035             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21036             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21037             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21038             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21039             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21040             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21041             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21042             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21043             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21044             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21045             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21046             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   21047             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   21048             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   21049             :   { Feature_isGCN|Feature_isSICI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   21050             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   21051             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   21052             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   21053             :   { Feature_isGCN|Feature_isVI, 778 /* buffer_load_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   21054             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   21055             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   21056             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   21057             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   21058             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   21059             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   21060             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   21061             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   21062             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21063             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21064             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21065             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21066             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21067             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21068             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21069             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21070             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21071             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21072             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21073             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21074             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21075             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21076             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21077             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21078             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21079             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21080             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21081             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21082             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   21083             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   21084             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   21085             :   { Feature_isGCN|Feature_isSICI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   21086             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   21087             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   21088             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   21089             :   { Feature_isGCN|Feature_isVI, 801 /* buffer_load_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   21090             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 16 /* 4 */ },
   21091             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 32 /* 5 */ },
   21092             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 64 /* 6 */ },
   21093             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 16 /* 4 */ },
   21094             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 32 /* 5 */ },
   21095             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 64 /* 6 */ },
   21096             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 16 /* 4 */ },
   21097             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 32 /* 5 */ },
   21098             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 64 /* 6 */ },
   21099             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 128 /* 7 */ },
   21100             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 16 /* 4 */ },
   21101             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 32 /* 5 */ },
   21102             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 64 /* 6 */ },
   21103             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 128 /* 7 */ },
   21104             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21105             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21106             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21107             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21108             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21109             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21110             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 256 /* 8 */ },
   21111             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21112             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21113             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21114             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21115             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21116             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21117             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21118             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21119             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21120             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 256 /* 8 */ },
   21121             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21122             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21123             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21124             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 256 /* 8 */ },
   21125             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21126             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21127             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21128             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21129             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21130             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21131             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21132             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21133             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21134             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 256 /* 8 */ },
   21135             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 32 /* 5 */ },
   21136             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 64 /* 6 */ },
   21137             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 128 /* 7 */ },
   21138             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 256 /* 8 */ },
   21139             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 64 /* 6 */ },
   21140             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 128 /* 7 */ },
   21141             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 256 /* 8 */ },
   21142             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 64 /* 6 */ },
   21143             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 128 /* 7 */ },
   21144             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 256 /* 8 */ },
   21145             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 64 /* 6 */ },
   21146             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 128 /* 7 */ },
   21147             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 256 /* 8 */ },
   21148             :   { Feature_isGCN|Feature_isSICI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 512 /* 9 */ },
   21149             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmOffset, 64 /* 6 */ },
   21150             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmGLC, 128 /* 7 */ },
   21151             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmSLC, 256 /* 8 */ },
   21152             :   { Feature_isGCN|Feature_isVI, 825 /* buffer_load_sbyte */, MCK_ImmTFE, 512 /* 9 */ },
   21153             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmOffset, 16 /* 4 */ },
   21154             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmGLC, 32 /* 5 */ },
   21155             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmSLC, 64 /* 6 */ },
   21156             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmTFE, 128 /* 7 */ },
   21157             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmOffset, 32 /* 5 */ },
   21158             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmGLC, 64 /* 6 */ },
   21159             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmSLC, 128 /* 7 */ },
   21160             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmTFE, 256 /* 8 */ },
   21161             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmOffset, 32 /* 5 */ },
   21162             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmGLC, 64 /* 6 */ },
   21163             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmSLC, 128 /* 7 */ },
   21164             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmTFE, 256 /* 8 */ },
   21165             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmOffset, 64 /* 6 */ },
   21166             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmGLC, 128 /* 7 */ },
   21167             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmSLC, 256 /* 8 */ },
   21168             :   { Feature_HasD16LoadStore|Feature_isVI, 843 /* buffer_load_sbyte_d16 */, MCK_ImmTFE, 512 /* 9 */ },
   21169             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmOffset, 16 /* 4 */ },
   21170             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmGLC, 32 /* 5 */ },
   21171             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmSLC, 64 /* 6 */ },
   21172             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmTFE, 128 /* 7 */ },
   21173             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21174             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21175             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21176             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21177             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21178             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21179             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21180             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21181             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmOffset, 64 /* 6 */ },
   21182             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmGLC, 128 /* 7 */ },
   21183             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmSLC, 256 /* 8 */ },
   21184             :   { Feature_HasD16LoadStore|Feature_isVI, 865 /* buffer_load_sbyte_d16_hi */, MCK_ImmTFE, 512 /* 9 */ },
   21185             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmOffset, 16 /* 4 */ },
   21186             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmGLC, 32 /* 5 */ },
   21187             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmSLC, 64 /* 6 */ },
   21188             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmTFE, 128 /* 7 */ },
   21189             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmOffset, 32 /* 5 */ },
   21190             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmGLC, 64 /* 6 */ },
   21191             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmSLC, 128 /* 7 */ },
   21192             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmTFE, 256 /* 8 */ },
   21193             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmOffset, 32 /* 5 */ },
   21194             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmGLC, 64 /* 6 */ },
   21195             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmSLC, 128 /* 7 */ },
   21196             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmTFE, 256 /* 8 */ },
   21197             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmOffset, 64 /* 6 */ },
   21198             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmGLC, 128 /* 7 */ },
   21199             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmSLC, 256 /* 8 */ },
   21200             :   { Feature_HasD16LoadStore|Feature_isVI, 890 /* buffer_load_short_d16 */, MCK_ImmTFE, 512 /* 9 */ },
   21201             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmOffset, 16 /* 4 */ },
   21202             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmGLC, 32 /* 5 */ },
   21203             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmSLC, 64 /* 6 */ },
   21204             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmTFE, 128 /* 7 */ },
   21205             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21206             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21207             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21208             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21209             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21210             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21211             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21212             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21213             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmOffset, 64 /* 6 */ },
   21214             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmGLC, 128 /* 7 */ },
   21215             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmSLC, 256 /* 8 */ },
   21216             :   { Feature_HasD16LoadStore|Feature_isVI, 912 /* buffer_load_short_d16_hi */, MCK_ImmTFE, 512 /* 9 */ },
   21217             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 16 /* 4 */ },
   21218             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 32 /* 5 */ },
   21219             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 64 /* 6 */ },
   21220             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 16 /* 4 */ },
   21221             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 32 /* 5 */ },
   21222             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 64 /* 6 */ },
   21223             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 16 /* 4 */ },
   21224             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 32 /* 5 */ },
   21225             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 64 /* 6 */ },
   21226             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 128 /* 7 */ },
   21227             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 16 /* 4 */ },
   21228             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 32 /* 5 */ },
   21229             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 64 /* 6 */ },
   21230             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 128 /* 7 */ },
   21231             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21232             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21233             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21234             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21235             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21236             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21237             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 256 /* 8 */ },
   21238             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21239             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21240             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21241             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21242             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21243             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21244             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21245             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21246             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21247             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 256 /* 8 */ },
   21248             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21249             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21250             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21251             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 256 /* 8 */ },
   21252             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21253             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21254             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21255             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21256             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21257             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21258             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21259             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21260             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21261             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 256 /* 8 */ },
   21262             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 32 /* 5 */ },
   21263             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 64 /* 6 */ },
   21264             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 128 /* 7 */ },
   21265             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 256 /* 8 */ },
   21266             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 64 /* 6 */ },
   21267             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 128 /* 7 */ },
   21268             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 256 /* 8 */ },
   21269             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 64 /* 6 */ },
   21270             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 128 /* 7 */ },
   21271             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 256 /* 8 */ },
   21272             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 64 /* 6 */ },
   21273             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 128 /* 7 */ },
   21274             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 256 /* 8 */ },
   21275             :   { Feature_isGCN|Feature_isSICI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 512 /* 9 */ },
   21276             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmOffset, 64 /* 6 */ },
   21277             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmGLC, 128 /* 7 */ },
   21278             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmSLC, 256 /* 8 */ },
   21279             :   { Feature_isGCN|Feature_isVI, 937 /* buffer_load_sshort */, MCK_ImmTFE, 512 /* 9 */ },
   21280             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 16 /* 4 */ },
   21281             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 32 /* 5 */ },
   21282             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 64 /* 6 */ },
   21283             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 16 /* 4 */ },
   21284             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 32 /* 5 */ },
   21285             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 64 /* 6 */ },
   21286             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 16 /* 4 */ },
   21287             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 32 /* 5 */ },
   21288             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 64 /* 6 */ },
   21289             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 128 /* 7 */ },
   21290             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 16 /* 4 */ },
   21291             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 32 /* 5 */ },
   21292             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 64 /* 6 */ },
   21293             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 128 /* 7 */ },
   21294             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21295             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21296             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21297             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21298             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21299             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21300             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 256 /* 8 */ },
   21301             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21302             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21303             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21304             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21305             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21306             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21307             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21308             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21309             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21310             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 256 /* 8 */ },
   21311             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21312             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21313             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21314             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 256 /* 8 */ },
   21315             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21316             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21317             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21318             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21319             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21320             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21321             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21322             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21323             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21324             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 256 /* 8 */ },
   21325             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 32 /* 5 */ },
   21326             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 64 /* 6 */ },
   21327             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 128 /* 7 */ },
   21328             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 256 /* 8 */ },
   21329             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 64 /* 6 */ },
   21330             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 128 /* 7 */ },
   21331             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 256 /* 8 */ },
   21332             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 64 /* 6 */ },
   21333             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 128 /* 7 */ },
   21334             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 256 /* 8 */ },
   21335             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 64 /* 6 */ },
   21336             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 128 /* 7 */ },
   21337             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 256 /* 8 */ },
   21338             :   { Feature_isGCN|Feature_isSICI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 512 /* 9 */ },
   21339             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmOffset, 64 /* 6 */ },
   21340             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmGLC, 128 /* 7 */ },
   21341             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmSLC, 256 /* 8 */ },
   21342             :   { Feature_isGCN|Feature_isVI, 956 /* buffer_load_ubyte */, MCK_ImmTFE, 512 /* 9 */ },
   21343             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmOffset, 16 /* 4 */ },
   21344             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmGLC, 32 /* 5 */ },
   21345             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmSLC, 64 /* 6 */ },
   21346             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmTFE, 128 /* 7 */ },
   21347             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmOffset, 32 /* 5 */ },
   21348             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmGLC, 64 /* 6 */ },
   21349             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmSLC, 128 /* 7 */ },
   21350             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmTFE, 256 /* 8 */ },
   21351             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmOffset, 32 /* 5 */ },
   21352             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmGLC, 64 /* 6 */ },
   21353             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmSLC, 128 /* 7 */ },
   21354             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmTFE, 256 /* 8 */ },
   21355             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmOffset, 64 /* 6 */ },
   21356             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmGLC, 128 /* 7 */ },
   21357             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmSLC, 256 /* 8 */ },
   21358             :   { Feature_HasD16LoadStore|Feature_isVI, 974 /* buffer_load_ubyte_d16 */, MCK_ImmTFE, 512 /* 9 */ },
   21359             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmOffset, 16 /* 4 */ },
   21360             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmGLC, 32 /* 5 */ },
   21361             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmSLC, 64 /* 6 */ },
   21362             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmTFE, 128 /* 7 */ },
   21363             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21364             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21365             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21366             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21367             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21368             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21369             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21370             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21371             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmOffset, 64 /* 6 */ },
   21372             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmGLC, 128 /* 7 */ },
   21373             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmSLC, 256 /* 8 */ },
   21374             :   { Feature_HasD16LoadStore|Feature_isVI, 996 /* buffer_load_ubyte_d16_hi */, MCK_ImmTFE, 512 /* 9 */ },
   21375             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 16 /* 4 */ },
   21376             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 32 /* 5 */ },
   21377             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 64 /* 6 */ },
   21378             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 16 /* 4 */ },
   21379             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 32 /* 5 */ },
   21380             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 64 /* 6 */ },
   21381             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 16 /* 4 */ },
   21382             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 32 /* 5 */ },
   21383             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 64 /* 6 */ },
   21384             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 128 /* 7 */ },
   21385             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 16 /* 4 */ },
   21386             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 32 /* 5 */ },
   21387             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 64 /* 6 */ },
   21388             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 128 /* 7 */ },
   21389             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21390             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21391             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21392             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21393             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21394             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21395             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 256 /* 8 */ },
   21396             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21397             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21398             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21399             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21400             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21401             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21402             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21403             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21404             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21405             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 256 /* 8 */ },
   21406             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21407             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21408             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21409             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 256 /* 8 */ },
   21410             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21411             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21412             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21413             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21414             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21415             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21416             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21417             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21418             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21419             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 256 /* 8 */ },
   21420             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 32 /* 5 */ },
   21421             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 64 /* 6 */ },
   21422             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 128 /* 7 */ },
   21423             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 256 /* 8 */ },
   21424             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 64 /* 6 */ },
   21425             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 128 /* 7 */ },
   21426             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 256 /* 8 */ },
   21427             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 64 /* 6 */ },
   21428             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 128 /* 7 */ },
   21429             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 256 /* 8 */ },
   21430             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 64 /* 6 */ },
   21431             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 128 /* 7 */ },
   21432             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 256 /* 8 */ },
   21433             :   { Feature_isGCN|Feature_isSICI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 512 /* 9 */ },
   21434             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmOffset, 64 /* 6 */ },
   21435             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmGLC, 128 /* 7 */ },
   21436             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmSLC, 256 /* 8 */ },
   21437             :   { Feature_isGCN|Feature_isVI, 1021 /* buffer_load_ushort */, MCK_ImmTFE, 512 /* 9 */ },
   21438             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 16 /* 4 */ },
   21439             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 32 /* 5 */ },
   21440             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 64 /* 6 */ },
   21441             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 128 /* 7 */ },
   21442             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 16 /* 4 */ },
   21443             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 32 /* 5 */ },
   21444             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 64 /* 6 */ },
   21445             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 128 /* 7 */ },
   21446             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 32 /* 5 */ },
   21447             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 64 /* 6 */ },
   21448             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 128 /* 7 */ },
   21449             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 256 /* 8 */ },
   21450             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 32 /* 5 */ },
   21451             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 64 /* 6 */ },
   21452             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 128 /* 7 */ },
   21453             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 256 /* 8 */ },
   21454             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 32 /* 5 */ },
   21455             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 64 /* 6 */ },
   21456             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 128 /* 7 */ },
   21457             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 256 /* 8 */ },
   21458             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 32 /* 5 */ },
   21459             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 64 /* 6 */ },
   21460             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 128 /* 7 */ },
   21461             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 256 /* 8 */ },
   21462             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 32 /* 5 */ },
   21463             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 64 /* 6 */ },
   21464             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 128 /* 7 */ },
   21465             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 256 /* 8 */ },
   21466             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 64 /* 6 */ },
   21467             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 128 /* 7 */ },
   21468             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 256 /* 8 */ },
   21469             :   { Feature_isGCN|Feature_isSICI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 512 /* 9 */ },
   21470             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmOffset, 64 /* 6 */ },
   21471             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmGLC, 128 /* 7 */ },
   21472             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmSLC, 256 /* 8 */ },
   21473             :   { Feature_isGCN|Feature_isVI, 1040 /* buffer_store_byte */, MCK_ImmTFE, 512 /* 9 */ },
   21474             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmOffset, 16 /* 4 */ },
   21475             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmGLC, 32 /* 5 */ },
   21476             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmSLC, 64 /* 6 */ },
   21477             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmTFE, 128 /* 7 */ },
   21478             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21479             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21480             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21481             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21482             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21483             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21484             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21485             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21486             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmOffset, 64 /* 6 */ },
   21487             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmGLC, 128 /* 7 */ },
   21488             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmSLC, 256 /* 8 */ },
   21489             :   { Feature_HasD16LoadStore|Feature_isVI, 1058 /* buffer_store_byte_d16_hi */, MCK_ImmTFE, 512 /* 9 */ },
   21490             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 16 /* 4 */ },
   21491             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 32 /* 5 */ },
   21492             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 64 /* 6 */ },
   21493             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 128 /* 7 */ },
   21494             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 16 /* 4 */ },
   21495             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 32 /* 5 */ },
   21496             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 64 /* 6 */ },
   21497             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 128 /* 7 */ },
   21498             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 32 /* 5 */ },
   21499             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 64 /* 6 */ },
   21500             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 128 /* 7 */ },
   21501             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 256 /* 8 */ },
   21502             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 32 /* 5 */ },
   21503             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 64 /* 6 */ },
   21504             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 128 /* 7 */ },
   21505             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 256 /* 8 */ },
   21506             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 32 /* 5 */ },
   21507             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 64 /* 6 */ },
   21508             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 128 /* 7 */ },
   21509             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 256 /* 8 */ },
   21510             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 32 /* 5 */ },
   21511             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 64 /* 6 */ },
   21512             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 128 /* 7 */ },
   21513             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 256 /* 8 */ },
   21514             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 32 /* 5 */ },
   21515             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 64 /* 6 */ },
   21516             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 128 /* 7 */ },
   21517             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 256 /* 8 */ },
   21518             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 64 /* 6 */ },
   21519             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 128 /* 7 */ },
   21520             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 256 /* 8 */ },
   21521             :   { Feature_isGCN|Feature_isSICI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 512 /* 9 */ },
   21522             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmOffset, 64 /* 6 */ },
   21523             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmGLC, 128 /* 7 */ },
   21524             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmSLC, 256 /* 8 */ },
   21525             :   { Feature_isGCN|Feature_isVI, 1083 /* buffer_store_dword */, MCK_ImmTFE, 512 /* 9 */ },
   21526             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 16 /* 4 */ },
   21527             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 32 /* 5 */ },
   21528             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 64 /* 6 */ },
   21529             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 128 /* 7 */ },
   21530             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 16 /* 4 */ },
   21531             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 32 /* 5 */ },
   21532             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 64 /* 6 */ },
   21533             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 128 /* 7 */ },
   21534             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   21535             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   21536             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   21537             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   21538             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   21539             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   21540             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   21541             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   21542             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   21543             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   21544             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   21545             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   21546             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   21547             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   21548             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   21549             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   21550             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 32 /* 5 */ },
   21551             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 64 /* 6 */ },
   21552             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 128 /* 7 */ },
   21553             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 256 /* 8 */ },
   21554             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 64 /* 6 */ },
   21555             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 128 /* 7 */ },
   21556             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 256 /* 8 */ },
   21557             :   { Feature_isGCN|Feature_isSICI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 512 /* 9 */ },
   21558             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmOffset, 64 /* 6 */ },
   21559             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmGLC, 128 /* 7 */ },
   21560             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmSLC, 256 /* 8 */ },
   21561             :   { Feature_isGCN|Feature_isVI, 1102 /* buffer_store_dwordx2 */, MCK_ImmTFE, 512 /* 9 */ },
   21562             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 16 /* 4 */ },
   21563             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 32 /* 5 */ },
   21564             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 64 /* 6 */ },
   21565             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 128 /* 7 */ },
   21566             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 16 /* 4 */ },
   21567             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 32 /* 5 */ },
   21568             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 64 /* 6 */ },
   21569             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 128 /* 7 */ },
   21570             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   21571             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   21572             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   21573             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   21574             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   21575             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   21576             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   21577             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   21578             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   21579             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   21580             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   21581             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   21582             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   21583             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   21584             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   21585             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   21586             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 32 /* 5 */ },
   21587             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 64 /* 6 */ },
   21588             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 128 /* 7 */ },
   21589             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 256 /* 8 */ },
   21590             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 64 /* 6 */ },
   21591             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 128 /* 7 */ },
   21592             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 256 /* 8 */ },
   21593             :   { Feature_isGCN|Feature_isSICI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 512 /* 9 */ },
   21594             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmOffset, 64 /* 6 */ },
   21595             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmGLC, 128 /* 7 */ },
   21596             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmSLC, 256 /* 8 */ },
   21597             :   { Feature_isGCN|Feature_isVI, 1123 /* buffer_store_dwordx3 */, MCK_ImmTFE, 512 /* 9 */ },
   21598             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 16 /* 4 */ },
   21599             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 32 /* 5 */ },
   21600             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 64 /* 6 */ },
   21601             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 128 /* 7 */ },
   21602             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 16 /* 4 */ },
   21603             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 32 /* 5 */ },
   21604             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 64 /* 6 */ },
   21605             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 128 /* 7 */ },
   21606             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   21607             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   21608             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   21609             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   21610             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   21611             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   21612             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   21613             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   21614             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   21615             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   21616             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   21617             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   21618             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   21619             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   21620             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   21621             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   21622             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 32 /* 5 */ },
   21623             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 64 /* 6 */ },
   21624             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 128 /* 7 */ },
   21625             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 256 /* 8 */ },
   21626             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 64 /* 6 */ },
   21627             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 128 /* 7 */ },
   21628             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 256 /* 8 */ },
   21629             :   { Feature_isGCN|Feature_isSICI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 512 /* 9 */ },
   21630             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmOffset, 64 /* 6 */ },
   21631             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmGLC, 128 /* 7 */ },
   21632             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmSLC, 256 /* 8 */ },
   21633             :   { Feature_isGCN|Feature_isVI, 1144 /* buffer_store_dwordx4 */, MCK_ImmTFE, 512 /* 9 */ },
   21634             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmOffset, 16 /* 4 */ },
   21635             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmGLC, 32 /* 5 */ },
   21636             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmSLC, 64 /* 6 */ },
   21637             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmTFE, 128 /* 7 */ },
   21638             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmOffset, 32 /* 5 */ },
   21639             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmGLC, 64 /* 6 */ },
   21640             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmSLC, 128 /* 7 */ },
   21641             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmTFE, 256 /* 8 */ },
   21642             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmOffset, 32 /* 5 */ },
   21643             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmGLC, 64 /* 6 */ },
   21644             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmSLC, 128 /* 7 */ },
   21645             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmTFE, 256 /* 8 */ },
   21646             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmOffset, 64 /* 6 */ },
   21647             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmGLC, 128 /* 7 */ },
   21648             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmSLC, 256 /* 8 */ },
   21649             :   { Feature_HasD16LoadStore|Feature_isVI, 1165 /* buffer_store_format_d16_hi_x */, MCK_ImmTFE, 512 /* 9 */ },
   21650             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 16 /* 4 */ },
   21651             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 32 /* 5 */ },
   21652             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 64 /* 6 */ },
   21653             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 128 /* 7 */ },
   21654             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 16 /* 4 */ },
   21655             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 32 /* 5 */ },
   21656             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 64 /* 6 */ },
   21657             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 128 /* 7 */ },
   21658             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   21659             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   21660             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   21661             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   21662             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   21663             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   21664             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   21665             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   21666             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   21667             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   21668             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   21669             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   21670             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   21671             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   21672             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   21673             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   21674             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   21675             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   21676             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   21677             :   { Feature_HasPackedD16VMem|Feature_isVI, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   21678             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   21679             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   21680             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   21681             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1194 /* buffer_store_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   21682             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 16 /* 4 */ },
   21683             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 32 /* 5 */ },
   21684             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 64 /* 6 */ },
   21685             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 128 /* 7 */ },
   21686             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 16 /* 4 */ },
   21687             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 32 /* 5 */ },
   21688             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 64 /* 6 */ },
   21689             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 128 /* 7 */ },
   21690             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21691             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21692             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21693             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21694             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21695             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21696             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21697             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21698             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21699             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21700             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21701             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21702             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21703             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21704             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21705             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21706             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   21707             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   21708             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   21709             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   21710             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   21711             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   21712             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   21713             :   { Feature_HasPackedD16VMem|Feature_isVI, 1220 /* buffer_store_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   21714             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   21715             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   21716             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   21717             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   21718             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   21719             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   21720             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   21721             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   21722             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21723             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21724             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21725             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21726             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21727             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21728             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21729             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21730             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21731             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21732             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21733             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21734             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21735             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21736             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21737             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21738             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   21739             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   21740             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   21741             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   21742             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   21743             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   21744             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   21745             :   { Feature_HasPackedD16VMem|Feature_isVI, 1247 /* buffer_store_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   21746             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   21747             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   21748             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   21749             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   21750             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   21751             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   21752             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   21753             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   21754             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21755             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21756             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21757             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21758             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21759             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21760             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21761             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21762             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21763             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21764             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21765             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21766             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21767             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21768             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21769             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21770             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   21771             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   21772             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   21773             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   21774             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   21775             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   21776             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   21777             :   { Feature_HasPackedD16VMem|Feature_isVI, 1275 /* buffer_store_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   21778             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 16 /* 4 */ },
   21779             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 32 /* 5 */ },
   21780             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 64 /* 6 */ },
   21781             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 128 /* 7 */ },
   21782             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 16 /* 4 */ },
   21783             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 32 /* 5 */ },
   21784             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 64 /* 6 */ },
   21785             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 128 /* 7 */ },
   21786             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   21787             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   21788             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   21789             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   21790             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   21791             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   21792             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   21793             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   21794             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   21795             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   21796             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   21797             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   21798             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   21799             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   21800             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   21801             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   21802             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   21803             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   21804             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   21805             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   21806             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   21807             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   21808             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   21809             :   { Feature_isGCN|Feature_isSICI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   21810             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   21811             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   21812             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   21813             :   { Feature_isGCN|Feature_isVI, 1304 /* buffer_store_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   21814             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 16 /* 4 */ },
   21815             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 32 /* 5 */ },
   21816             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 64 /* 6 */ },
   21817             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 128 /* 7 */ },
   21818             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 16 /* 4 */ },
   21819             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 32 /* 5 */ },
   21820             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 64 /* 6 */ },
   21821             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 128 /* 7 */ },
   21822             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21823             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21824             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21825             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21826             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21827             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21828             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21829             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21830             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21831             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21832             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21833             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21834             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21835             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21836             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21837             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21838             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   21839             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   21840             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   21841             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   21842             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   21843             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   21844             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   21845             :   { Feature_isGCN|Feature_isSICI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   21846             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   21847             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   21848             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   21849             :   { Feature_isGCN|Feature_isVI, 1326 /* buffer_store_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   21850             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   21851             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   21852             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   21853             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   21854             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 16 /* 4 */ },
   21855             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 32 /* 5 */ },
   21856             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 64 /* 6 */ },
   21857             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 128 /* 7 */ },
   21858             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21859             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21860             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21861             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21862             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21863             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21864             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21865             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21866             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21867             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21868             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21869             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21870             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21871             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21872             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21873             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21874             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   21875             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   21876             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   21877             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   21878             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   21879             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   21880             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   21881             :   { Feature_isGCN|Feature_isSICI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   21882             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   21883             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   21884             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   21885             :   { Feature_isGCN|Feature_isVI, 1349 /* buffer_store_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   21886             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   21887             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   21888             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   21889             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   21890             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 16 /* 4 */ },
   21891             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 32 /* 5 */ },
   21892             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 64 /* 6 */ },
   21893             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 128 /* 7 */ },
   21894             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21895             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21896             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21897             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21898             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21899             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21900             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21901             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21902             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21903             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21904             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21905             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21906             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21907             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21908             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21909             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21910             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   21911             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   21912             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   21913             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   21914             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   21915             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   21916             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   21917             :   { Feature_isGCN|Feature_isSICI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   21918             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   21919             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   21920             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   21921             :   { Feature_isGCN|Feature_isVI, 1373 /* buffer_store_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   21922             :   { Feature_isVI|Feature_isVI, 1398 /* buffer_store_lds_dword */, MCK_ImmOffset, 4 /* 2 */ },
   21923             :   { Feature_isVI|Feature_isVI, 1398 /* buffer_store_lds_dword */, MCK_ImmGLC, 16 /* 4 */ },
   21924             :   { Feature_isVI|Feature_isVI, 1398 /* buffer_store_lds_dword */, MCK_ImmSLC, 32 /* 5 */ },
   21925             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmOffset, 16 /* 4 */ },
   21926             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmGLC, 32 /* 5 */ },
   21927             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmSLC, 64 /* 6 */ },
   21928             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmTFE, 128 /* 7 */ },
   21929             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmOffset, 16 /* 4 */ },
   21930             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmGLC, 32 /* 5 */ },
   21931             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmSLC, 64 /* 6 */ },
   21932             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmTFE, 128 /* 7 */ },
   21933             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmOffset, 32 /* 5 */ },
   21934             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmGLC, 64 /* 6 */ },
   21935             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmSLC, 128 /* 7 */ },
   21936             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmTFE, 256 /* 8 */ },
   21937             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmOffset, 32 /* 5 */ },
   21938             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmGLC, 64 /* 6 */ },
   21939             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmSLC, 128 /* 7 */ },
   21940             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmTFE, 256 /* 8 */ },
   21941             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmOffset, 32 /* 5 */ },
   21942             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmGLC, 64 /* 6 */ },
   21943             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmSLC, 128 /* 7 */ },
   21944             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmTFE, 256 /* 8 */ },
   21945             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmOffset, 32 /* 5 */ },
   21946             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmGLC, 64 /* 6 */ },
   21947             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmSLC, 128 /* 7 */ },
   21948             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmTFE, 256 /* 8 */ },
   21949             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmOffset, 32 /* 5 */ },
   21950             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmGLC, 64 /* 6 */ },
   21951             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmSLC, 128 /* 7 */ },
   21952             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmTFE, 256 /* 8 */ },
   21953             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmOffset, 64 /* 6 */ },
   21954             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmGLC, 128 /* 7 */ },
   21955             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmSLC, 256 /* 8 */ },
   21956             :   { Feature_isGCN|Feature_isSICI, 1421 /* buffer_store_short */, MCK_ImmTFE, 512 /* 9 */ },
   21957             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmOffset, 64 /* 6 */ },
   21958             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmGLC, 128 /* 7 */ },
   21959             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmSLC, 256 /* 8 */ },
   21960             :   { Feature_isGCN|Feature_isVI, 1421 /* buffer_store_short */, MCK_ImmTFE, 512 /* 9 */ },
   21961             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmOffset, 16 /* 4 */ },
   21962             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmGLC, 32 /* 5 */ },
   21963             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmSLC, 64 /* 6 */ },
   21964             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmTFE, 128 /* 7 */ },
   21965             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21966             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21967             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21968             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21969             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmOffset, 32 /* 5 */ },
   21970             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmGLC, 64 /* 6 */ },
   21971             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmSLC, 128 /* 7 */ },
   21972             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmTFE, 256 /* 8 */ },
   21973             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmOffset, 64 /* 6 */ },
   21974             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmGLC, 128 /* 7 */ },
   21975             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmSLC, 256 /* 8 */ },
   21976             :   { Feature_HasD16LoadStore|Feature_isVI, 1440 /* buffer_store_short_d16_hi */, MCK_ImmTFE, 512 /* 9 */ },
   21977             :   { Feature_isGCN|Feature_isVI, 1518 /* ds_add_f32 */, MCK_ImmOffset, 4 /* 2 */ },
   21978             :   { Feature_isGCN|Feature_isVI, 1518 /* ds_add_f32 */, MCK_ImmGDS, 8 /* 3 */ },
   21979             :   { Feature_isGCN|Feature_isVI, 1529 /* ds_add_rtn_f32 */, MCK_ImmOffset, 8 /* 3 */ },
   21980             :   { Feature_isGCN|Feature_isVI, 1529 /* ds_add_rtn_f32 */, MCK_ImmGDS, 16 /* 4 */ },
   21981             :   { Feature_isGCN|Feature_isSICI, 1544 /* ds_add_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   21982             :   { Feature_isGCN|Feature_isSICI, 1544 /* ds_add_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   21983             :   { Feature_isGCN|Feature_isVI, 1544 /* ds_add_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   21984             :   { Feature_isGCN|Feature_isVI, 1544 /* ds_add_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   21985             :   { Feature_isGCN|Feature_isSICI, 1559 /* ds_add_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   21986             :   { Feature_isGCN|Feature_isSICI, 1559 /* ds_add_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   21987             :   { Feature_isGCN|Feature_isVI, 1559 /* ds_add_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   21988             :   { Feature_isGCN|Feature_isVI, 1559 /* ds_add_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   21989             :   { Feature_isVI|Feature_isVI, 1574 /* ds_add_src2_f32 */, MCK_ImmOffset, 2 /* 1 */ },
   21990             :   { Feature_isVI|Feature_isVI, 1574 /* ds_add_src2_f32 */, MCK_ImmGDS, 4 /* 2 */ },
   21991             :   { Feature_isGCN|Feature_isSICI, 1590 /* ds_add_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   21992             :   { Feature_isGCN|Feature_isSICI, 1590 /* ds_add_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   21993             :   { Feature_isGCN|Feature_isVI, 1590 /* ds_add_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   21994             :   { Feature_isGCN|Feature_isVI, 1590 /* ds_add_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   21995             :   { Feature_isGCN|Feature_isSICI, 1606 /* ds_add_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   21996             :   { Feature_isGCN|Feature_isSICI, 1606 /* ds_add_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   21997             :   { Feature_isGCN|Feature_isVI, 1606 /* ds_add_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   21998             :   { Feature_isGCN|Feature_isVI, 1606 /* ds_add_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   21999             :   { Feature_isGCN|Feature_isSICI, 1622 /* ds_add_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22000             :   { Feature_isGCN|Feature_isSICI, 1622 /* ds_add_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22001             :   { Feature_isGCN|Feature_isVI, 1622 /* ds_add_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22002             :   { Feature_isGCN|Feature_isVI, 1622 /* ds_add_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22003             :   { Feature_isGCN|Feature_isSICI, 1633 /* ds_add_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22004             :   { Feature_isGCN|Feature_isSICI, 1633 /* ds_add_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22005             :   { Feature_isGCN|Feature_isVI, 1633 /* ds_add_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22006             :   { Feature_isGCN|Feature_isVI, 1633 /* ds_add_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22007             :   { Feature_isGCN|Feature_isSICI, 1644 /* ds_and_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22008             :   { Feature_isGCN|Feature_isSICI, 1644 /* ds_and_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22009             :   { Feature_isGCN|Feature_isVI, 1644 /* ds_and_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22010             :   { Feature_isGCN|Feature_isVI, 1644 /* ds_and_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22011             :   { Feature_isGCN|Feature_isSICI, 1655 /* ds_and_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22012             :   { Feature_isGCN|Feature_isSICI, 1655 /* ds_and_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22013             :   { Feature_isGCN|Feature_isVI, 1655 /* ds_and_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22014             :   { Feature_isGCN|Feature_isVI, 1655 /* ds_and_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22015             :   { Feature_isGCN|Feature_isSICI, 1666 /* ds_and_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22016             :   { Feature_isGCN|Feature_isSICI, 1666 /* ds_and_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22017             :   { Feature_isGCN|Feature_isVI, 1666 /* ds_and_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22018             :   { Feature_isGCN|Feature_isVI, 1666 /* ds_and_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22019             :   { Feature_isGCN|Feature_isSICI, 1681 /* ds_and_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22020             :   { Feature_isGCN|Feature_isSICI, 1681 /* ds_and_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22021             :   { Feature_isGCN|Feature_isVI, 1681 /* ds_and_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22022             :   { Feature_isGCN|Feature_isVI, 1681 /* ds_and_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22023             :   { Feature_isGCN|Feature_isSICI, 1696 /* ds_and_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22024             :   { Feature_isGCN|Feature_isSICI, 1696 /* ds_and_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22025             :   { Feature_isGCN|Feature_isVI, 1696 /* ds_and_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22026             :   { Feature_isGCN|Feature_isVI, 1696 /* ds_and_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22027             :   { Feature_isGCN|Feature_isSICI, 1712 /* ds_and_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22028             :   { Feature_isGCN|Feature_isSICI, 1712 /* ds_and_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22029             :   { Feature_isGCN|Feature_isVI, 1712 /* ds_and_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22030             :   { Feature_isGCN|Feature_isVI, 1712 /* ds_and_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22031             :   { Feature_isGCN|Feature_isSICI, 1728 /* ds_append */, MCK_ImmOffset, 2 /* 1 */ },
   22032             :   { Feature_isGCN|Feature_isSICI, 1728 /* ds_append */, MCK_ImmGDS, 4 /* 2 */ },
   22033             :   { Feature_isGCN|Feature_isVI, 1728 /* ds_append */, MCK_ImmOffset, 2 /* 1 */ },
   22034             :   { Feature_isGCN|Feature_isVI, 1728 /* ds_append */, MCK_ImmGDS, 4 /* 2 */ },
   22035             :   { Feature_isVI|Feature_isVI, 1738 /* ds_bpermute_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22036             :   { Feature_isGCN|Feature_isSICI, 1754 /* ds_cmpst_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22037             :   { Feature_isGCN|Feature_isSICI, 1754 /* ds_cmpst_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22038             :   { Feature_isGCN|Feature_isVI, 1754 /* ds_cmpst_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22039             :   { Feature_isGCN|Feature_isVI, 1754 /* ds_cmpst_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22040             :   { Feature_isGCN|Feature_isSICI, 1767 /* ds_cmpst_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22041             :   { Feature_isGCN|Feature_isSICI, 1767 /* ds_cmpst_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22042             :   { Feature_isGCN|Feature_isVI, 1767 /* ds_cmpst_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22043             :   { Feature_isGCN|Feature_isVI, 1767 /* ds_cmpst_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22044             :   { Feature_isGCN|Feature_isSICI, 1780 /* ds_cmpst_f32 */, MCK_ImmOffset, 8 /* 3 */ },
   22045             :   { Feature_isGCN|Feature_isSICI, 1780 /* ds_cmpst_f32 */, MCK_ImmGDS, 16 /* 4 */ },
   22046             :   { Feature_isGCN|Feature_isVI, 1780 /* ds_cmpst_f32 */, MCK_ImmOffset, 8 /* 3 */ },
   22047             :   { Feature_isGCN|Feature_isVI, 1780 /* ds_cmpst_f32 */, MCK_ImmGDS, 16 /* 4 */ },
   22048             :   { Feature_isGCN|Feature_isSICI, 1793 /* ds_cmpst_f64 */, MCK_ImmOffset, 8 /* 3 */ },
   22049             :   { Feature_isGCN|Feature_isSICI, 1793 /* ds_cmpst_f64 */, MCK_ImmGDS, 16 /* 4 */ },
   22050             :   { Feature_isGCN|Feature_isVI, 1793 /* ds_cmpst_f64 */, MCK_ImmOffset, 8 /* 3 */ },
   22051             :   { Feature_isGCN|Feature_isVI, 1793 /* ds_cmpst_f64 */, MCK_ImmGDS, 16 /* 4 */ },
   22052             :   { Feature_isGCN|Feature_isSICI, 1806 /* ds_cmpst_rtn_b32 */, MCK_ImmOffset, 16 /* 4 */ },
   22053             :   { Feature_isGCN|Feature_isSICI, 1806 /* ds_cmpst_rtn_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22054             :   { Feature_isGCN|Feature_isVI, 1806 /* ds_cmpst_rtn_b32 */, MCK_ImmOffset, 16 /* 4 */ },
   22055             :   { Feature_isGCN|Feature_isVI, 1806 /* ds_cmpst_rtn_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22056             :   { Feature_isGCN|Feature_isSICI, 1823 /* ds_cmpst_rtn_b64 */, MCK_ImmOffset, 16 /* 4 */ },
   22057             :   { Feature_isGCN|Feature_isSICI, 1823 /* ds_cmpst_rtn_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22058             :   { Feature_isGCN|Feature_isVI, 1823 /* ds_cmpst_rtn_b64 */, MCK_ImmOffset, 16 /* 4 */ },
   22059             :   { Feature_isGCN|Feature_isVI, 1823 /* ds_cmpst_rtn_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22060             :   { Feature_isGCN|Feature_isSICI, 1840 /* ds_cmpst_rtn_f32 */, MCK_ImmOffset, 16 /* 4 */ },
   22061             :   { Feature_isGCN|Feature_isSICI, 1840 /* ds_cmpst_rtn_f32 */, MCK_ImmGDS, 32 /* 5 */ },
   22062             :   { Feature_isGCN|Feature_isVI, 1840 /* ds_cmpst_rtn_f32 */, MCK_ImmOffset, 16 /* 4 */ },
   22063             :   { Feature_isGCN|Feature_isVI, 1840 /* ds_cmpst_rtn_f32 */, MCK_ImmGDS, 32 /* 5 */ },
   22064             :   { Feature_isGCN|Feature_isSICI, 1857 /* ds_cmpst_rtn_f64 */, MCK_ImmOffset, 16 /* 4 */ },
   22065             :   { Feature_isGCN|Feature_isSICI, 1857 /* ds_cmpst_rtn_f64 */, MCK_ImmGDS, 32 /* 5 */ },
   22066             :   { Feature_isGCN|Feature_isVI, 1857 /* ds_cmpst_rtn_f64 */, MCK_ImmOffset, 16 /* 4 */ },
   22067             :   { Feature_isGCN|Feature_isVI, 1857 /* ds_cmpst_rtn_f64 */, MCK_ImmGDS, 32 /* 5 */ },
   22068             :   { Feature_isCIVI|Feature_isSICI, 1874 /* ds_condxchg32_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22069             :   { Feature_isCIVI|Feature_isSICI, 1874 /* ds_condxchg32_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22070             :   { Feature_isCIVI|Feature_isVI, 1874 /* ds_condxchg32_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22071             :   { Feature_isCIVI|Feature_isVI, 1874 /* ds_condxchg32_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22072             :   { Feature_isGCN|Feature_isSICI, 1896 /* ds_consume */, MCK_ImmOffset, 2 /* 1 */ },
   22073             :   { Feature_isGCN|Feature_isSICI, 1896 /* ds_consume */, MCK_ImmGDS, 4 /* 2 */ },
   22074             :   { Feature_isGCN|Feature_isVI, 1896 /* ds_consume */, MCK_ImmOffset, 2 /* 1 */ },
   22075             :   { Feature_isGCN|Feature_isVI, 1896 /* ds_consume */, MCK_ImmGDS, 4 /* 2 */ },
   22076             :   { Feature_isGCN|Feature_isSICI, 1907 /* ds_dec_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22077             :   { Feature_isGCN|Feature_isSICI, 1907 /* ds_dec_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22078             :   { Feature_isGCN|Feature_isVI, 1907 /* ds_dec_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22079             :   { Feature_isGCN|Feature_isVI, 1907 /* ds_dec_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22080             :   { Feature_isGCN|Feature_isSICI, 1922 /* ds_dec_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22081             :   { Feature_isGCN|Feature_isSICI, 1922 /* ds_dec_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22082             :   { Feature_isGCN|Feature_isVI, 1922 /* ds_dec_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22083             :   { Feature_isGCN|Feature_isVI, 1922 /* ds_dec_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22084             :   { Feature_isGCN|Feature_isSICI, 1937 /* ds_dec_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22085             :   { Feature_isGCN|Feature_isSICI, 1937 /* ds_dec_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22086             :   { Feature_isGCN|Feature_isVI, 1937 /* ds_dec_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22087             :   { Feature_isGCN|Feature_isVI, 1937 /* ds_dec_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22088             :   { Feature_isGCN|Feature_isSICI, 1953 /* ds_dec_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22089             :   { Feature_isGCN|Feature_isSICI, 1953 /* ds_dec_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22090             :   { Feature_isGCN|Feature_isVI, 1953 /* ds_dec_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22091             :   { Feature_isGCN|Feature_isVI, 1953 /* ds_dec_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22092             :   { Feature_isGCN|Feature_isSICI, 1969 /* ds_dec_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22093             :   { Feature_isGCN|Feature_isSICI, 1969 /* ds_dec_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22094             :   { Feature_isGCN|Feature_isVI, 1969 /* ds_dec_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22095             :   { Feature_isGCN|Feature_isVI, 1969 /* ds_dec_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22096             :   { Feature_isGCN|Feature_isSICI, 1980 /* ds_dec_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22097             :   { Feature_isGCN|Feature_isSICI, 1980 /* ds_dec_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22098             :   { Feature_isGCN|Feature_isVI, 1980 /* ds_dec_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22099             :   { Feature_isGCN|Feature_isVI, 1980 /* ds_dec_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22100             :   { Feature_isGCN|Feature_isSICI, 1991 /* ds_gws_barrier */, MCK_ImmOffset, 2 /* 1 */ },
   22101             :   { Feature_isGCN|Feature_isVI, 1991 /* ds_gws_barrier */, MCK_ImmOffset, 2 /* 1 */ },
   22102             :   { Feature_isGCN|Feature_isSICI, 2006 /* ds_gws_init */, MCK_ImmOffset, 2 /* 1 */ },
   22103             :   { Feature_isGCN|Feature_isVI, 2006 /* ds_gws_init */, MCK_ImmOffset, 2 /* 1 */ },
   22104             :   { Feature_isGCN|Feature_isSICI, 2018 /* ds_gws_sema_br */, MCK_ImmOffset, 2 /* 1 */ },
   22105             :   { Feature_isGCN|Feature_isVI, 2018 /* ds_gws_sema_br */, MCK_ImmOffset, 2 /* 1 */ },
   22106             :   { Feature_isGCN|Feature_isSICI, 2033 /* ds_gws_sema_p */, MCK_ImmOffset, 1 /* 0 */ },
   22107             :   { Feature_isGCN|Feature_isVI, 2033 /* ds_gws_sema_p */, MCK_ImmOffset, 1 /* 0 */ },
   22108             :   { Feature_isCIVI|Feature_isSICI, 2047 /* ds_gws_sema_release_all */, MCK_ImmOffset, 1 /* 0 */ },
   22109             :   { Feature_isCIVI|Feature_isVI, 2047 /* ds_gws_sema_release_all */, MCK_ImmOffset, 1 /* 0 */ },
   22110             :   { Feature_isGCN|Feature_isSICI, 2071 /* ds_gws_sema_v */, MCK_ImmOffset, 1 /* 0 */ },
   22111             :   { Feature_isGCN|Feature_isVI, 2071 /* ds_gws_sema_v */, MCK_ImmOffset, 1 /* 0 */ },
   22112             :   { Feature_isGCN|Feature_isSICI, 2085 /* ds_inc_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22113             :   { Feature_isGCN|Feature_isSICI, 2085 /* ds_inc_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22114             :   { Feature_isGCN|Feature_isVI, 2085 /* ds_inc_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22115             :   { Feature_isGCN|Feature_isVI, 2085 /* ds_inc_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22116             :   { Feature_isGCN|Feature_isSICI, 2100 /* ds_inc_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22117             :   { Feature_isGCN|Feature_isSICI, 2100 /* ds_inc_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22118             :   { Feature_isGCN|Feature_isVI, 2100 /* ds_inc_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22119             :   { Feature_isGCN|Feature_isVI, 2100 /* ds_inc_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22120             :   { Feature_isGCN|Feature_isSICI, 2115 /* ds_inc_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22121             :   { Feature_isGCN|Feature_isSICI, 2115 /* ds_inc_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22122             :   { Feature_isGCN|Feature_isVI, 2115 /* ds_inc_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22123             :   { Feature_isGCN|Feature_isVI, 2115 /* ds_inc_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22124             :   { Feature_isGCN|Feature_isSICI, 2131 /* ds_inc_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22125             :   { Feature_isGCN|Feature_isSICI, 2131 /* ds_inc_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22126             :   { Feature_isGCN|Feature_isVI, 2131 /* ds_inc_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22127             :   { Feature_isGCN|Feature_isVI, 2131 /* ds_inc_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22128             :   { Feature_isGCN|Feature_isSICI, 2147 /* ds_inc_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22129             :   { Feature_isGCN|Feature_isSICI, 2147 /* ds_inc_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22130             :   { Feature_isGCN|Feature_isVI, 2147 /* ds_inc_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22131             :   { Feature_isGCN|Feature_isVI, 2147 /* ds_inc_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22132             :   { Feature_isGCN|Feature_isSICI, 2158 /* ds_inc_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22133             :   { Feature_isGCN|Feature_isSICI, 2158 /* ds_inc_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22134             :   { Feature_isGCN|Feature_isVI, 2158 /* ds_inc_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22135             :   { Feature_isGCN|Feature_isVI, 2158 /* ds_inc_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22136             :   { Feature_isGCN|Feature_isSICI, 2169 /* ds_max_f32 */, MCK_ImmOffset, 4 /* 2 */ },
   22137             :   { Feature_isGCN|Feature_isSICI, 2169 /* ds_max_f32 */, MCK_ImmGDS, 8 /* 3 */ },
   22138             :   { Feature_isGCN|Feature_isVI, 2169 /* ds_max_f32 */, MCK_ImmOffset, 4 /* 2 */ },
   22139             :   { Feature_isGCN|Feature_isVI, 2169 /* ds_max_f32 */, MCK_ImmGDS, 8 /* 3 */ },
   22140             :   { Feature_isGCN|Feature_isSICI, 2180 /* ds_max_f64 */, MCK_ImmOffset, 4 /* 2 */ },
   22141             :   { Feature_isGCN|Feature_isSICI, 2180 /* ds_max_f64 */, MCK_ImmGDS, 8 /* 3 */ },
   22142             :   { Feature_isGCN|Feature_isVI, 2180 /* ds_max_f64 */, MCK_ImmOffset, 4 /* 2 */ },
   22143             :   { Feature_isGCN|Feature_isVI, 2180 /* ds_max_f64 */, MCK_ImmGDS, 8 /* 3 */ },
   22144             :   { Feature_isGCN|Feature_isSICI, 2191 /* ds_max_i32 */, MCK_ImmOffset, 4 /* 2 */ },
   22145             :   { Feature_isGCN|Feature_isSICI, 2191 /* ds_max_i32 */, MCK_ImmGDS, 8 /* 3 */ },
   22146             :   { Feature_isGCN|Feature_isVI, 2191 /* ds_max_i32 */, MCK_ImmOffset, 4 /* 2 */ },
   22147             :   { Feature_isGCN|Feature_isVI, 2191 /* ds_max_i32 */, MCK_ImmGDS, 8 /* 3 */ },
   22148             :   { Feature_isGCN|Feature_isSICI, 2202 /* ds_max_i64 */, MCK_ImmOffset, 4 /* 2 */ },
   22149             :   { Feature_isGCN|Feature_isSICI, 2202 /* ds_max_i64 */, MCK_ImmGDS, 8 /* 3 */ },
   22150             :   { Feature_isGCN|Feature_isVI, 2202 /* ds_max_i64 */, MCK_ImmOffset, 4 /* 2 */ },
   22151             :   { Feature_isGCN|Feature_isVI, 2202 /* ds_max_i64 */, MCK_ImmGDS, 8 /* 3 */ },
   22152             :   { Feature_isGCN|Feature_isSICI, 2213 /* ds_max_rtn_f32 */, MCK_ImmOffset, 8 /* 3 */ },
   22153             :   { Feature_isGCN|Feature_isSICI, 2213 /* ds_max_rtn_f32 */, MCK_ImmGDS, 16 /* 4 */ },
   22154             :   { Feature_isGCN|Feature_isVI, 2213 /* ds_max_rtn_f32 */, MCK_ImmOffset, 8 /* 3 */ },
   22155             :   { Feature_isGCN|Feature_isVI, 2213 /* ds_max_rtn_f32 */, MCK_ImmGDS, 16 /* 4 */ },
   22156             :   { Feature_isGCN|Feature_isSICI, 2228 /* ds_max_rtn_f64 */, MCK_ImmOffset, 8 /* 3 */ },
   22157             :   { Feature_isGCN|Feature_isSICI, 2228 /* ds_max_rtn_f64 */, MCK_ImmGDS, 16 /* 4 */ },
   22158             :   { Feature_isGCN|Feature_isVI, 2228 /* ds_max_rtn_f64 */, MCK_ImmOffset, 8 /* 3 */ },
   22159             :   { Feature_isGCN|Feature_isVI, 2228 /* ds_max_rtn_f64 */, MCK_ImmGDS, 16 /* 4 */ },
   22160             :   { Feature_isGCN|Feature_isSICI, 2243 /* ds_max_rtn_i32 */, MCK_ImmOffset, 8 /* 3 */ },
   22161             :   { Feature_isGCN|Feature_isSICI, 2243 /* ds_max_rtn_i32 */, MCK_ImmGDS, 16 /* 4 */ },
   22162             :   { Feature_isGCN|Feature_isVI, 2243 /* ds_max_rtn_i32 */, MCK_ImmOffset, 8 /* 3 */ },
   22163             :   { Feature_isGCN|Feature_isVI, 2243 /* ds_max_rtn_i32 */, MCK_ImmGDS, 16 /* 4 */ },
   22164             :   { Feature_isGCN|Feature_isSICI, 2258 /* ds_max_rtn_i64 */, MCK_ImmOffset, 8 /* 3 */ },
   22165             :   { Feature_isGCN|Feature_isSICI, 2258 /* ds_max_rtn_i64 */, MCK_ImmGDS, 16 /* 4 */ },
   22166             :   { Feature_isGCN|Feature_isVI, 2258 /* ds_max_rtn_i64 */, MCK_ImmOffset, 8 /* 3 */ },
   22167             :   { Feature_isGCN|Feature_isVI, 2258 /* ds_max_rtn_i64 */, MCK_ImmGDS, 16 /* 4 */ },
   22168             :   { Feature_isGCN|Feature_isSICI, 2273 /* ds_max_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22169             :   { Feature_isGCN|Feature_isSICI, 2273 /* ds_max_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22170             :   { Feature_isGCN|Feature_isVI, 2273 /* ds_max_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22171             :   { Feature_isGCN|Feature_isVI, 2273 /* ds_max_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22172             :   { Feature_isGCN|Feature_isSICI, 2288 /* ds_max_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22173             :   { Feature_isGCN|Feature_isSICI, 2288 /* ds_max_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22174             :   { Feature_isGCN|Feature_isVI, 2288 /* ds_max_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22175             :   { Feature_isGCN|Feature_isVI, 2288 /* ds_max_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22176             :   { Feature_isGCN|Feature_isSICI, 2303 /* ds_max_src2_f32 */, MCK_ImmOffset, 2 /* 1 */ },
   22177             :   { Feature_isGCN|Feature_isSICI, 2303 /* ds_max_src2_f32 */, MCK_ImmGDS, 4 /* 2 */ },
   22178             :   { Feature_isGCN|Feature_isVI, 2303 /* ds_max_src2_f32 */, MCK_ImmOffset, 2 /* 1 */ },
   22179             :   { Feature_isGCN|Feature_isVI, 2303 /* ds_max_src2_f32 */, MCK_ImmGDS, 4 /* 2 */ },
   22180             :   { Feature_isGCN|Feature_isSICI, 2319 /* ds_max_src2_f64 */, MCK_ImmOffset, 2 /* 1 */ },
   22181             :   { Feature_isGCN|Feature_isSICI, 2319 /* ds_max_src2_f64 */, MCK_ImmGDS, 4 /* 2 */ },
   22182             :   { Feature_isGCN|Feature_isVI, 2319 /* ds_max_src2_f64 */, MCK_ImmOffset, 2 /* 1 */ },
   22183             :   { Feature_isGCN|Feature_isVI, 2319 /* ds_max_src2_f64 */, MCK_ImmGDS, 4 /* 2 */ },
   22184             :   { Feature_isGCN|Feature_isSICI, 2335 /* ds_max_src2_i32 */, MCK_ImmOffset, 2 /* 1 */ },
   22185             :   { Feature_isGCN|Feature_isSICI, 2335 /* ds_max_src2_i32 */, MCK_ImmGDS, 4 /* 2 */ },
   22186             :   { Feature_isGCN|Feature_isVI, 2335 /* ds_max_src2_i32 */, MCK_ImmOffset, 2 /* 1 */ },
   22187             :   { Feature_isGCN|Feature_isVI, 2335 /* ds_max_src2_i32 */, MCK_ImmGDS, 4 /* 2 */ },
   22188             :   { Feature_isGCN|Feature_isSICI, 2351 /* ds_max_src2_i64 */, MCK_ImmOffset, 2 /* 1 */ },
   22189             :   { Feature_isGCN|Feature_isSICI, 2351 /* ds_max_src2_i64 */, MCK_ImmGDS, 4 /* 2 */ },
   22190             :   { Feature_isGCN|Feature_isVI, 2351 /* ds_max_src2_i64 */, MCK_ImmOffset, 2 /* 1 */ },
   22191             :   { Feature_isGCN|Feature_isVI, 2351 /* ds_max_src2_i64 */, MCK_ImmGDS, 4 /* 2 */ },
   22192             :   { Feature_isGCN|Feature_isSICI, 2367 /* ds_max_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22193             :   { Feature_isGCN|Feature_isSICI, 2367 /* ds_max_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22194             :   { Feature_isGCN|Feature_isVI, 2367 /* ds_max_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22195             :   { Feature_isGCN|Feature_isVI, 2367 /* ds_max_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22196             :   { Feature_isGCN|Feature_isSICI, 2383 /* ds_max_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22197             :   { Feature_isGCN|Feature_isSICI, 2383 /* ds_max_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22198             :   { Feature_isGCN|Feature_isVI, 2383 /* ds_max_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22199             :   { Feature_isGCN|Feature_isVI, 2383 /* ds_max_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22200             :   { Feature_isGCN|Feature_isSICI, 2399 /* ds_max_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22201             :   { Feature_isGCN|Feature_isSICI, 2399 /* ds_max_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22202             :   { Feature_isGCN|Feature_isVI, 2399 /* ds_max_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22203             :   { Feature_isGCN|Feature_isVI, 2399 /* ds_max_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22204             :   { Feature_isGCN|Feature_isSICI, 2410 /* ds_max_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22205             :   { Feature_isGCN|Feature_isSICI, 2410 /* ds_max_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22206             :   { Feature_isGCN|Feature_isVI, 2410 /* ds_max_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22207             :   { Feature_isGCN|Feature_isVI, 2410 /* ds_max_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22208             :   { Feature_isGCN|Feature_isSICI, 2421 /* ds_min_f32 */, MCK_ImmOffset, 4 /* 2 */ },
   22209             :   { Feature_isGCN|Feature_isSICI, 2421 /* ds_min_f32 */, MCK_ImmGDS, 8 /* 3 */ },
   22210             :   { Feature_isGCN|Feature_isVI, 2421 /* ds_min_f32 */, MCK_ImmOffset, 4 /* 2 */ },
   22211             :   { Feature_isGCN|Feature_isVI, 2421 /* ds_min_f32 */, MCK_ImmGDS, 8 /* 3 */ },
   22212             :   { Feature_isGCN|Feature_isSICI, 2432 /* ds_min_f64 */, MCK_ImmOffset, 4 /* 2 */ },
   22213             :   { Feature_isGCN|Feature_isSICI, 2432 /* ds_min_f64 */, MCK_ImmGDS, 8 /* 3 */ },
   22214             :   { Feature_isGCN|Feature_isVI, 2432 /* ds_min_f64 */, MCK_ImmOffset, 4 /* 2 */ },
   22215             :   { Feature_isGCN|Feature_isVI, 2432 /* ds_min_f64 */, MCK_ImmGDS, 8 /* 3 */ },
   22216             :   { Feature_isGCN|Feature_isSICI, 2443 /* ds_min_i32 */, MCK_ImmOffset, 4 /* 2 */ },
   22217             :   { Feature_isGCN|Feature_isSICI, 2443 /* ds_min_i32 */, MCK_ImmGDS, 8 /* 3 */ },
   22218             :   { Feature_isGCN|Feature_isVI, 2443 /* ds_min_i32 */, MCK_ImmOffset, 4 /* 2 */ },
   22219             :   { Feature_isGCN|Feature_isVI, 2443 /* ds_min_i32 */, MCK_ImmGDS, 8 /* 3 */ },
   22220             :   { Feature_isGCN|Feature_isSICI, 2454 /* ds_min_i64 */, MCK_ImmOffset, 4 /* 2 */ },
   22221             :   { Feature_isGCN|Feature_isSICI, 2454 /* ds_min_i64 */, MCK_ImmGDS, 8 /* 3 */ },
   22222             :   { Feature_isGCN|Feature_isVI, 2454 /* ds_min_i64 */, MCK_ImmOffset, 4 /* 2 */ },
   22223             :   { Feature_isGCN|Feature_isVI, 2454 /* ds_min_i64 */, MCK_ImmGDS, 8 /* 3 */ },
   22224             :   { Feature_isGCN|Feature_isSICI, 2465 /* ds_min_rtn_f32 */, MCK_ImmOffset, 8 /* 3 */ },
   22225             :   { Feature_isGCN|Feature_isSICI, 2465 /* ds_min_rtn_f32 */, MCK_ImmGDS, 16 /* 4 */ },
   22226             :   { Feature_isGCN|Feature_isVI, 2465 /* ds_min_rtn_f32 */, MCK_ImmOffset, 8 /* 3 */ },
   22227             :   { Feature_isGCN|Feature_isVI, 2465 /* ds_min_rtn_f32 */, MCK_ImmGDS, 16 /* 4 */ },
   22228             :   { Feature_isGCN|Feature_isSICI, 2480 /* ds_min_rtn_f64 */, MCK_ImmOffset, 8 /* 3 */ },
   22229             :   { Feature_isGCN|Feature_isSICI, 2480 /* ds_min_rtn_f64 */, MCK_ImmGDS, 16 /* 4 */ },
   22230             :   { Feature_isGCN|Feature_isVI, 2480 /* ds_min_rtn_f64 */, MCK_ImmOffset, 8 /* 3 */ },
   22231             :   { Feature_isGCN|Feature_isVI, 2480 /* ds_min_rtn_f64 */, MCK_ImmGDS, 16 /* 4 */ },
   22232             :   { Feature_isGCN|Feature_isSICI, 2495 /* ds_min_rtn_i32 */, MCK_ImmOffset, 8 /* 3 */ },
   22233             :   { Feature_isGCN|Feature_isSICI, 2495 /* ds_min_rtn_i32 */, MCK_ImmGDS, 16 /* 4 */ },
   22234             :   { Feature_isGCN|Feature_isVI, 2495 /* ds_min_rtn_i32 */, MCK_ImmOffset, 8 /* 3 */ },
   22235             :   { Feature_isGCN|Feature_isVI, 2495 /* ds_min_rtn_i32 */, MCK_ImmGDS, 16 /* 4 */ },
   22236             :   { Feature_isGCN|Feature_isSICI, 2510 /* ds_min_rtn_i64 */, MCK_ImmOffset, 8 /* 3 */ },
   22237             :   { Feature_isGCN|Feature_isSICI, 2510 /* ds_min_rtn_i64 */, MCK_ImmGDS, 16 /* 4 */ },
   22238             :   { Feature_isGCN|Feature_isVI, 2510 /* ds_min_rtn_i64 */, MCK_ImmOffset, 8 /* 3 */ },
   22239             :   { Feature_isGCN|Feature_isVI, 2510 /* ds_min_rtn_i64 */, MCK_ImmGDS, 16 /* 4 */ },
   22240             :   { Feature_isGCN|Feature_isSICI, 2525 /* ds_min_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22241             :   { Feature_isGCN|Feature_isSICI, 2525 /* ds_min_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22242             :   { Feature_isGCN|Feature_isVI, 2525 /* ds_min_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22243             :   { Feature_isGCN|Feature_isVI, 2525 /* ds_min_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22244             :   { Feature_isGCN|Feature_isSICI, 2540 /* ds_min_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22245             :   { Feature_isGCN|Feature_isSICI, 2540 /* ds_min_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22246             :   { Feature_isGCN|Feature_isVI, 2540 /* ds_min_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22247             :   { Feature_isGCN|Feature_isVI, 2540 /* ds_min_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22248             :   { Feature_isGCN|Feature_isSICI, 2555 /* ds_min_src2_f32 */, MCK_ImmOffset, 2 /* 1 */ },
   22249             :   { Feature_isGCN|Feature_isSICI, 2555 /* ds_min_src2_f32 */, MCK_ImmGDS, 4 /* 2 */ },
   22250             :   { Feature_isGCN|Feature_isVI, 2555 /* ds_min_src2_f32 */, MCK_ImmOffset, 2 /* 1 */ },
   22251             :   { Feature_isGCN|Feature_isVI, 2555 /* ds_min_src2_f32 */, MCK_ImmGDS, 4 /* 2 */ },
   22252             :   { Feature_isGCN|Feature_isSICI, 2571 /* ds_min_src2_f64 */, MCK_ImmOffset, 2 /* 1 */ },
   22253             :   { Feature_isGCN|Feature_isSICI, 2571 /* ds_min_src2_f64 */, MCK_ImmGDS, 4 /* 2 */ },
   22254             :   { Feature_isGCN|Feature_isVI, 2571 /* ds_min_src2_f64 */, MCK_ImmOffset, 2 /* 1 */ },
   22255             :   { Feature_isGCN|Feature_isVI, 2571 /* ds_min_src2_f64 */, MCK_ImmGDS, 4 /* 2 */ },
   22256             :   { Feature_isGCN|Feature_isSICI, 2587 /* ds_min_src2_i32 */, MCK_ImmOffset, 2 /* 1 */ },
   22257             :   { Feature_isGCN|Feature_isSICI, 2587 /* ds_min_src2_i32 */, MCK_ImmGDS, 4 /* 2 */ },
   22258             :   { Feature_isGCN|Feature_isVI, 2587 /* ds_min_src2_i32 */, MCK_ImmOffset, 2 /* 1 */ },
   22259             :   { Feature_isGCN|Feature_isVI, 2587 /* ds_min_src2_i32 */, MCK_ImmGDS, 4 /* 2 */ },
   22260             :   { Feature_isGCN|Feature_isSICI, 2603 /* ds_min_src2_i64 */, MCK_ImmOffset, 2 /* 1 */ },
   22261             :   { Feature_isGCN|Feature_isSICI, 2603 /* ds_min_src2_i64 */, MCK_ImmGDS, 4 /* 2 */ },
   22262             :   { Feature_isGCN|Feature_isVI, 2603 /* ds_min_src2_i64 */, MCK_ImmOffset, 2 /* 1 */ },
   22263             :   { Feature_isGCN|Feature_isVI, 2603 /* ds_min_src2_i64 */, MCK_ImmGDS, 4 /* 2 */ },
   22264             :   { Feature_isGCN|Feature_isSICI, 2619 /* ds_min_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22265             :   { Feature_isGCN|Feature_isSICI, 2619 /* ds_min_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22266             :   { Feature_isGCN|Feature_isVI, 2619 /* ds_min_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22267             :   { Feature_isGCN|Feature_isVI, 2619 /* ds_min_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22268             :   { Feature_isGCN|Feature_isSICI, 2635 /* ds_min_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22269             :   { Feature_isGCN|Feature_isSICI, 2635 /* ds_min_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22270             :   { Feature_isGCN|Feature_isVI, 2635 /* ds_min_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22271             :   { Feature_isGCN|Feature_isVI, 2635 /* ds_min_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22272             :   { Feature_isGCN|Feature_isSICI, 2651 /* ds_min_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22273             :   { Feature_isGCN|Feature_isSICI, 2651 /* ds_min_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22274             :   { Feature_isGCN|Feature_isVI, 2651 /* ds_min_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22275             :   { Feature_isGCN|Feature_isVI, 2651 /* ds_min_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22276             :   { Feature_isGCN|Feature_isSICI, 2662 /* ds_min_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22277             :   { Feature_isGCN|Feature_isSICI, 2662 /* ds_min_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22278             :   { Feature_isGCN|Feature_isVI, 2662 /* ds_min_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22279             :   { Feature_isGCN|Feature_isVI, 2662 /* ds_min_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22280             :   { Feature_isGCN|Feature_isSICI, 2673 /* ds_mskor_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22281             :   { Feature_isGCN|Feature_isSICI, 2673 /* ds_mskor_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22282             :   { Feature_isGCN|Feature_isVI, 2673 /* ds_mskor_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22283             :   { Feature_isGCN|Feature_isVI, 2673 /* ds_mskor_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22284             :   { Feature_isGCN|Feature_isSICI, 2686 /* ds_mskor_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22285             :   { Feature_isGCN|Feature_isSICI, 2686 /* ds_mskor_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22286             :   { Feature_isGCN|Feature_isVI, 2686 /* ds_mskor_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22287             :   { Feature_isGCN|Feature_isVI, 2686 /* ds_mskor_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22288             :   { Feature_isGCN|Feature_isSICI, 2699 /* ds_mskor_rtn_b32 */, MCK_ImmOffset, 16 /* 4 */ },
   22289             :   { Feature_isGCN|Feature_isSICI, 2699 /* ds_mskor_rtn_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22290             :   { Feature_isGCN|Feature_isVI, 2699 /* ds_mskor_rtn_b32 */, MCK_ImmOffset, 16 /* 4 */ },
   22291             :   { Feature_isGCN|Feature_isVI, 2699 /* ds_mskor_rtn_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22292             :   { Feature_isGCN|Feature_isSICI, 2716 /* ds_mskor_rtn_b64 */, MCK_ImmOffset, 16 /* 4 */ },
   22293             :   { Feature_isGCN|Feature_isSICI, 2716 /* ds_mskor_rtn_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22294             :   { Feature_isGCN|Feature_isVI, 2716 /* ds_mskor_rtn_b64 */, MCK_ImmOffset, 16 /* 4 */ },
   22295             :   { Feature_isGCN|Feature_isVI, 2716 /* ds_mskor_rtn_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22296             :   { Feature_isGCN|Feature_isSICI, 2740 /* ds_or_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22297             :   { Feature_isGCN|Feature_isSICI, 2740 /* ds_or_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22298             :   { Feature_isGCN|Feature_isVI, 2740 /* ds_or_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22299             :   { Feature_isGCN|Feature_isVI, 2740 /* ds_or_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22300             :   { Feature_isGCN|Feature_isSICI, 2750 /* ds_or_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22301             :   { Feature_isGCN|Feature_isSICI, 2750 /* ds_or_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22302             :   { Feature_isGCN|Feature_isVI, 2750 /* ds_or_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22303             :   { Feature_isGCN|Feature_isVI, 2750 /* ds_or_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22304             :   { Feature_isGCN|Feature_isSICI, 2760 /* ds_or_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22305             :   { Feature_isGCN|Feature_isSICI, 2760 /* ds_or_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22306             :   { Feature_isGCN|Feature_isVI, 2760 /* ds_or_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22307             :   { Feature_isGCN|Feature_isVI, 2760 /* ds_or_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22308             :   { Feature_isGCN|Feature_isSICI, 2774 /* ds_or_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22309             :   { Feature_isGCN|Feature_isSICI, 2774 /* ds_or_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22310             :   { Feature_isGCN|Feature_isVI, 2774 /* ds_or_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22311             :   { Feature_isGCN|Feature_isVI, 2774 /* ds_or_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22312             :   { Feature_isGCN|Feature_isSICI, 2788 /* ds_or_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22313             :   { Feature_isGCN|Feature_isSICI, 2788 /* ds_or_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22314             :   { Feature_isGCN|Feature_isVI, 2788 /* ds_or_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22315             :   { Feature_isGCN|Feature_isVI, 2788 /* ds_or_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22316             :   { Feature_isGCN|Feature_isSICI, 2803 /* ds_or_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22317             :   { Feature_isGCN|Feature_isSICI, 2803 /* ds_or_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22318             :   { Feature_isGCN|Feature_isVI, 2803 /* ds_or_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22319             :   { Feature_isGCN|Feature_isVI, 2803 /* ds_or_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22320             :   { Feature_isGCN|Feature_isSICI, 2818 /* ds_ordered_count */, MCK_ImmOffset, 4 /* 2 */ },
   22321             :   { Feature_isGCN|Feature_isVI, 2818 /* ds_ordered_count */, MCK_ImmOffset, 4 /* 2 */ },
   22322             :   { Feature_isVI|Feature_isVI, 2835 /* ds_permute_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22323             :   { Feature_isGCN|Feature_isSICI, 2850 /* ds_read2_b32 */, MCK_ImmOffset0, 4 /* 2 */ },
   22324             :   { Feature_isGCN|Feature_isSICI, 2850 /* ds_read2_b32 */, MCK_ImmOffset1, 8 /* 3 */ },
   22325             :   { Feature_isGCN|Feature_isSICI, 2850 /* ds_read2_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22326             :   { Feature_isGCN|Feature_isVI, 2850 /* ds_read2_b32 */, MCK_ImmOffset0, 4 /* 2 */ },
   22327             :   { Feature_isGCN|Feature_isVI, 2850 /* ds_read2_b32 */, MCK_ImmOffset1, 8 /* 3 */ },
   22328             :   { Feature_isGCN|Feature_isVI, 2850 /* ds_read2_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22329             :   { Feature_isGCN|Feature_isSICI, 2863 /* ds_read2_b64 */, MCK_ImmOffset0, 4 /* 2 */ },
   22330             :   { Feature_isGCN|Feature_isSICI, 2863 /* ds_read2_b64 */, MCK_ImmOffset1, 8 /* 3 */ },
   22331             :   { Feature_isGCN|Feature_isSICI, 2863 /* ds_read2_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22332             :   { Feature_isGCN|Feature_isVI, 2863 /* ds_read2_b64 */, MCK_ImmOffset0, 4 /* 2 */ },
   22333             :   { Feature_isGCN|Feature_isVI, 2863 /* ds_read2_b64 */, MCK_ImmOffset1, 8 /* 3 */ },
   22334             :   { Feature_isGCN|Feature_isVI, 2863 /* ds_read2_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22335             :   { Feature_isGCN|Feature_isSICI, 2876 /* ds_read2st64_b32 */, MCK_ImmOffset0, 4 /* 2 */ },
   22336             :   { Feature_isGCN|Feature_isSICI, 2876 /* ds_read2st64_b32 */, MCK_ImmOffset1, 8 /* 3 */ },
   22337             :   { Feature_isGCN|Feature_isSICI, 2876 /* ds_read2st64_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22338             :   { Feature_isGCN|Feature_isVI, 2876 /* ds_read2st64_b32 */, MCK_ImmOffset0, 4 /* 2 */ },
   22339             :   { Feature_isGCN|Feature_isVI, 2876 /* ds_read2st64_b32 */, MCK_ImmOffset1, 8 /* 3 */ },
   22340             :   { Feature_isGCN|Feature_isVI, 2876 /* ds_read2st64_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22341             :   { Feature_isGCN|Feature_isSICI, 2893 /* ds_read2st64_b64 */, MCK_ImmOffset0, 4 /* 2 */ },
   22342             :   { Feature_isGCN|Feature_isSICI, 2893 /* ds_read2st64_b64 */, MCK_ImmOffset1, 8 /* 3 */ },
   22343             :   { Feature_isGCN|Feature_isSICI, 2893 /* ds_read2st64_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22344             :   { Feature_isGCN|Feature_isVI, 2893 /* ds_read2st64_b64 */, MCK_ImmOffset0, 4 /* 2 */ },
   22345             :   { Feature_isGCN|Feature_isVI, 2893 /* ds_read2st64_b64 */, MCK_ImmOffset1, 8 /* 3 */ },
   22346             :   { Feature_isGCN|Feature_isVI, 2893 /* ds_read2st64_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22347             :   { Feature_HasDSAddTid|Feature_isVI, 2910 /* ds_read_addtid_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22348             :   { Feature_HasDSAddTid|Feature_isVI, 2910 /* ds_read_addtid_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22349             :   { Feature_isCIVI|Feature_isSICI, 2929 /* ds_read_b128 */, MCK_ImmOffset, 4 /* 2 */ },
   22350             :   { Feature_isCIVI|Feature_isSICI, 2929 /* ds_read_b128 */, MCK_ImmGDS, 8 /* 3 */ },
   22351             :   { Feature_isCIVI|Feature_isVI, 2929 /* ds_read_b128 */, MCK_ImmOffset, 4 /* 2 */ },
   22352             :   { Feature_isCIVI|Feature_isVI, 2929 /* ds_read_b128 */, MCK_ImmGDS, 8 /* 3 */ },
   22353             :   { Feature_isGCN|Feature_isSICI, 2942 /* ds_read_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22354             :   { Feature_isGCN|Feature_isSICI, 2942 /* ds_read_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22355             :   { Feature_isGCN|Feature_isVI, 2942 /* ds_read_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22356             :   { Feature_isGCN|Feature_isVI, 2942 /* ds_read_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22357             :   { Feature_isGCN|Feature_isSICI, 2954 /* ds_read_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22358             :   { Feature_isGCN|Feature_isSICI, 2954 /* ds_read_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22359             :   { Feature_isGCN|Feature_isVI, 2954 /* ds_read_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22360             :   { Feature_isGCN|Feature_isVI, 2954 /* ds_read_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22361             :   { Feature_isCIVI|Feature_isSICI, 2966 /* ds_read_b96 */, MCK_ImmOffset, 4 /* 2 */ },
   22362             :   { Feature_isCIVI|Feature_isSICI, 2966 /* ds_read_b96 */, MCK_ImmGDS, 8 /* 3 */ },
   22363             :   { Feature_isCIVI|Feature_isVI, 2966 /* ds_read_b96 */, MCK_ImmOffset, 4 /* 2 */ },
   22364             :   { Feature_isCIVI|Feature_isVI, 2966 /* ds_read_b96 */, MCK_ImmGDS, 8 /* 3 */ },
   22365             :   { Feature_isGCN|Feature_isSICI, 2978 /* ds_read_i16 */, MCK_ImmOffset, 4 /* 2 */ },
   22366             :   { Feature_isGCN|Feature_isSICI, 2978 /* ds_read_i16 */, MCK_ImmGDS, 8 /* 3 */ },
   22367             :   { Feature_isGCN|Feature_isVI, 2978 /* ds_read_i16 */, MCK_ImmOffset, 4 /* 2 */ },
   22368             :   { Feature_isGCN|Feature_isVI, 2978 /* ds_read_i16 */, MCK_ImmGDS, 8 /* 3 */ },
   22369             :   { Feature_isGCN|Feature_isSICI, 2990 /* ds_read_i8 */, MCK_ImmOffset, 4 /* 2 */ },
   22370             :   { Feature_isGCN|Feature_isSICI, 2990 /* ds_read_i8 */, MCK_ImmGDS, 8 /* 3 */ },
   22371             :   { Feature_isGCN|Feature_isVI, 2990 /* ds_read_i8 */, MCK_ImmOffset, 4 /* 2 */ },
   22372             :   { Feature_isGCN|Feature_isVI, 2990 /* ds_read_i8 */, MCK_ImmGDS, 8 /* 3 */ },
   22373             :   { Feature_HasD16LoadStore|Feature_isVI, 3001 /* ds_read_i8_d16 */, MCK_ImmOffset, 4 /* 2 */ },
   22374             :   { Feature_HasD16LoadStore|Feature_isVI, 3001 /* ds_read_i8_d16 */, MCK_ImmGDS, 8 /* 3 */ },
   22375             :   { Feature_HasD16LoadStore|Feature_isVI, 3016 /* ds_read_i8_d16_hi */, MCK_ImmOffset, 4 /* 2 */ },
   22376             :   { Feature_HasD16LoadStore|Feature_isVI, 3016 /* ds_read_i8_d16_hi */, MCK_ImmGDS, 8 /* 3 */ },
   22377             :   { Feature_isGCN|Feature_isSICI, 3034 /* ds_read_u16 */, MCK_ImmOffset, 4 /* 2 */ },
   22378             :   { Feature_isGCN|Feature_isSICI, 3034 /* ds_read_u16 */, MCK_ImmGDS, 8 /* 3 */ },
   22379             :   { Feature_isGCN|Feature_isVI, 3034 /* ds_read_u16 */, MCK_ImmOffset, 4 /* 2 */ },
   22380             :   { Feature_isGCN|Feature_isVI, 3034 /* ds_read_u16 */, MCK_ImmGDS, 8 /* 3 */ },
   22381             :   { Feature_HasD16LoadStore|Feature_isVI, 3046 /* ds_read_u16_d16 */, MCK_ImmOffset, 4 /* 2 */ },
   22382             :   { Feature_HasD16LoadStore|Feature_isVI, 3046 /* ds_read_u16_d16 */, MCK_ImmGDS, 8 /* 3 */ },
   22383             :   { Feature_HasD16LoadStore|Feature_isVI, 3062 /* ds_read_u16_d16_hi */, MCK_ImmOffset, 4 /* 2 */ },
   22384             :   { Feature_HasD16LoadStore|Feature_isVI, 3062 /* ds_read_u16_d16_hi */, MCK_ImmGDS, 8 /* 3 */ },
   22385             :   { Feature_isGCN|Feature_isSICI, 3081 /* ds_read_u8 */, MCK_ImmOffset, 4 /* 2 */ },
   22386             :   { Feature_isGCN|Feature_isSICI, 3081 /* ds_read_u8 */, MCK_ImmGDS, 8 /* 3 */ },
   22387             :   { Feature_isGCN|Feature_isVI, 3081 /* ds_read_u8 */, MCK_ImmOffset, 4 /* 2 */ },
   22388             :   { Feature_isGCN|Feature_isVI, 3081 /* ds_read_u8 */, MCK_ImmGDS, 8 /* 3 */ },
   22389             :   { Feature_HasD16LoadStore|Feature_isVI, 3092 /* ds_read_u8_d16 */, MCK_ImmOffset, 4 /* 2 */ },
   22390             :   { Feature_HasD16LoadStore|Feature_isVI, 3092 /* ds_read_u8_d16 */, MCK_ImmGDS, 8 /* 3 */ },
   22391             :   { Feature_HasD16LoadStore|Feature_isVI, 3107 /* ds_read_u8_d16_hi */, MCK_ImmOffset, 4 /* 2 */ },
   22392             :   { Feature_HasD16LoadStore|Feature_isVI, 3107 /* ds_read_u8_d16_hi */, MCK_ImmGDS, 8 /* 3 */ },
   22393             :   { Feature_isGCN|Feature_isSICI, 3125 /* ds_rsub_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22394             :   { Feature_isGCN|Feature_isSICI, 3125 /* ds_rsub_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22395             :   { Feature_isGCN|Feature_isVI, 3125 /* ds_rsub_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22396             :   { Feature_isGCN|Feature_isVI, 3125 /* ds_rsub_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22397             :   { Feature_isGCN|Feature_isSICI, 3141 /* ds_rsub_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22398             :   { Feature_isGCN|Feature_isSICI, 3141 /* ds_rsub_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22399             :   { Feature_isGCN|Feature_isVI, 3141 /* ds_rsub_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22400             :   { Feature_isGCN|Feature_isVI, 3141 /* ds_rsub_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22401             :   { Feature_isGCN|Feature_isSICI, 3157 /* ds_rsub_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22402             :   { Feature_isGCN|Feature_isSICI, 3157 /* ds_rsub_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22403             :   { Feature_isGCN|Feature_isVI, 3157 /* ds_rsub_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22404             :   { Feature_isGCN|Feature_isVI, 3157 /* ds_rsub_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22405             :   { Feature_isGCN|Feature_isSICI, 3174 /* ds_rsub_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22406             :   { Feature_isGCN|Feature_isSICI, 3174 /* ds_rsub_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22407             :   { Feature_isGCN|Feature_isVI, 3174 /* ds_rsub_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22408             :   { Feature_isGCN|Feature_isVI, 3174 /* ds_rsub_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22409             :   { Feature_isGCN|Feature_isSICI, 3191 /* ds_rsub_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22410             :   { Feature_isGCN|Feature_isSICI, 3191 /* ds_rsub_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22411             :   { Feature_isGCN|Feature_isVI, 3191 /* ds_rsub_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22412             :   { Feature_isGCN|Feature_isVI, 3191 /* ds_rsub_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22413             :   { Feature_isGCN|Feature_isSICI, 3203 /* ds_rsub_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22414             :   { Feature_isGCN|Feature_isSICI, 3203 /* ds_rsub_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22415             :   { Feature_isGCN|Feature_isVI, 3203 /* ds_rsub_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22416             :   { Feature_isGCN|Feature_isVI, 3203 /* ds_rsub_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22417             :   { Feature_isGCN|Feature_isSICI, 3215 /* ds_sub_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22418             :   { Feature_isGCN|Feature_isSICI, 3215 /* ds_sub_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22419             :   { Feature_isGCN|Feature_isVI, 3215 /* ds_sub_rtn_u32 */, MCK_ImmOffset, 8 /* 3 */ },
   22420             :   { Feature_isGCN|Feature_isVI, 3215 /* ds_sub_rtn_u32 */, MCK_ImmGDS, 16 /* 4 */ },
   22421             :   { Feature_isGCN|Feature_isSICI, 3230 /* ds_sub_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22422             :   { Feature_isGCN|Feature_isSICI, 3230 /* ds_sub_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22423             :   { Feature_isGCN|Feature_isVI, 3230 /* ds_sub_rtn_u64 */, MCK_ImmOffset, 8 /* 3 */ },
   22424             :   { Feature_isGCN|Feature_isVI, 3230 /* ds_sub_rtn_u64 */, MCK_ImmGDS, 16 /* 4 */ },
   22425             :   { Feature_isGCN|Feature_isSICI, 3245 /* ds_sub_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22426             :   { Feature_isGCN|Feature_isSICI, 3245 /* ds_sub_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22427             :   { Feature_isGCN|Feature_isVI, 3245 /* ds_sub_src2_u32 */, MCK_ImmOffset, 2 /* 1 */ },
   22428             :   { Feature_isGCN|Feature_isVI, 3245 /* ds_sub_src2_u32 */, MCK_ImmGDS, 4 /* 2 */ },
   22429             :   { Feature_isGCN|Feature_isSICI, 3261 /* ds_sub_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22430             :   { Feature_isGCN|Feature_isSICI, 3261 /* ds_sub_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22431             :   { Feature_isGCN|Feature_isVI, 3261 /* ds_sub_src2_u64 */, MCK_ImmOffset, 2 /* 1 */ },
   22432             :   { Feature_isGCN|Feature_isVI, 3261 /* ds_sub_src2_u64 */, MCK_ImmGDS, 4 /* 2 */ },
   22433             :   { Feature_isGCN|Feature_isSICI, 3277 /* ds_sub_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22434             :   { Feature_isGCN|Feature_isSICI, 3277 /* ds_sub_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22435             :   { Feature_isGCN|Feature_isVI, 3277 /* ds_sub_u32 */, MCK_ImmOffset, 4 /* 2 */ },
   22436             :   { Feature_isGCN|Feature_isVI, 3277 /* ds_sub_u32 */, MCK_ImmGDS, 8 /* 3 */ },
   22437             :   { Feature_isGCN|Feature_isSICI, 3288 /* ds_sub_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22438             :   { Feature_isGCN|Feature_isSICI, 3288 /* ds_sub_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22439             :   { Feature_isGCN|Feature_isVI, 3288 /* ds_sub_u64 */, MCK_ImmOffset, 4 /* 2 */ },
   22440             :   { Feature_isGCN|Feature_isVI, 3288 /* ds_sub_u64 */, MCK_ImmGDS, 8 /* 3 */ },
   22441             :   { Feature_isGCN|Feature_isSICI, 3299 /* ds_swizzle_b32 */, MCK_Swizzle, 4 /* 2 */ },
   22442             :   { Feature_isGCN|Feature_isSICI, 3299 /* ds_swizzle_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22443             :   { Feature_isGCN|Feature_isVI, 3299 /* ds_swizzle_b32 */, MCK_Swizzle, 4 /* 2 */ },
   22444             :   { Feature_isGCN|Feature_isVI, 3299 /* ds_swizzle_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22445             :   { Feature_isCIVI|Feature_isSICI, 3314 /* ds_wrap_rtn_b32 */, MCK_ImmOffset, 16 /* 4 */ },
   22446             :   { Feature_isCIVI|Feature_isSICI, 3314 /* ds_wrap_rtn_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22447             :   { Feature_isCIVI|Feature_isVI, 3314 /* ds_wrap_rtn_b32 */, MCK_ImmOffset, 16 /* 4 */ },
   22448             :   { Feature_isCIVI|Feature_isVI, 3314 /* ds_wrap_rtn_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22449             :   { Feature_isGCN|Feature_isSICI, 3330 /* ds_write2_b32 */, MCK_ImmOffset0, 8 /* 3 */ },
   22450             :   { Feature_isGCN|Feature_isSICI, 3330 /* ds_write2_b32 */, MCK_ImmOffset1, 16 /* 4 */ },
   22451             :   { Feature_isGCN|Feature_isSICI, 3330 /* ds_write2_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22452             :   { Feature_isGCN|Feature_isVI, 3330 /* ds_write2_b32 */, MCK_ImmOffset0, 8 /* 3 */ },
   22453             :   { Feature_isGCN|Feature_isVI, 3330 /* ds_write2_b32 */, MCK_ImmOffset1, 16 /* 4 */ },
   22454             :   { Feature_isGCN|Feature_isVI, 3330 /* ds_write2_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22455             :   { Feature_isGCN|Feature_isSICI, 3344 /* ds_write2_b64 */, MCK_ImmOffset0, 8 /* 3 */ },
   22456             :   { Feature_isGCN|Feature_isSICI, 3344 /* ds_write2_b64 */, MCK_ImmOffset1, 16 /* 4 */ },
   22457             :   { Feature_isGCN|Feature_isSICI, 3344 /* ds_write2_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22458             :   { Feature_isGCN|Feature_isVI, 3344 /* ds_write2_b64 */, MCK_ImmOffset0, 8 /* 3 */ },
   22459             :   { Feature_isGCN|Feature_isVI, 3344 /* ds_write2_b64 */, MCK_ImmOffset1, 16 /* 4 */ },
   22460             :   { Feature_isGCN|Feature_isVI, 3344 /* ds_write2_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22461             :   { Feature_isGCN|Feature_isSICI, 3358 /* ds_write2st64_b32 */, MCK_ImmOffset0, 8 /* 3 */ },
   22462             :   { Feature_isGCN|Feature_isSICI, 3358 /* ds_write2st64_b32 */, MCK_ImmOffset1, 16 /* 4 */ },
   22463             :   { Feature_isGCN|Feature_isSICI, 3358 /* ds_write2st64_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22464             :   { Feature_isGCN|Feature_isVI, 3358 /* ds_write2st64_b32 */, MCK_ImmOffset0, 8 /* 3 */ },
   22465             :   { Feature_isGCN|Feature_isVI, 3358 /* ds_write2st64_b32 */, MCK_ImmOffset1, 16 /* 4 */ },
   22466             :   { Feature_isGCN|Feature_isVI, 3358 /* ds_write2st64_b32 */, MCK_ImmGDS, 32 /* 5 */ },
   22467             :   { Feature_isGCN|Feature_isSICI, 3376 /* ds_write2st64_b64 */, MCK_ImmOffset0, 8 /* 3 */ },
   22468             :   { Feature_isGCN|Feature_isSICI, 3376 /* ds_write2st64_b64 */, MCK_ImmOffset1, 16 /* 4 */ },
   22469             :   { Feature_isGCN|Feature_isSICI, 3376 /* ds_write2st64_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22470             :   { Feature_isGCN|Feature_isVI, 3376 /* ds_write2st64_b64 */, MCK_ImmOffset0, 8 /* 3 */ },
   22471             :   { Feature_isGCN|Feature_isVI, 3376 /* ds_write2st64_b64 */, MCK_ImmOffset1, 16 /* 4 */ },
   22472             :   { Feature_isGCN|Feature_isVI, 3376 /* ds_write2st64_b64 */, MCK_ImmGDS, 32 /* 5 */ },
   22473             :   { Feature_HasDSAddTid|Feature_isVI, 3394 /* ds_write_addtid_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22474             :   { Feature_HasDSAddTid|Feature_isVI, 3394 /* ds_write_addtid_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22475             :   { Feature_isCIVI|Feature_isSICI, 3414 /* ds_write_b128 */, MCK_ImmOffset, 4 /* 2 */ },
   22476             :   { Feature_isCIVI|Feature_isSICI, 3414 /* ds_write_b128 */, MCK_ImmGDS, 8 /* 3 */ },
   22477             :   { Feature_isCIVI|Feature_isVI, 3414 /* ds_write_b128 */, MCK_ImmOffset, 4 /* 2 */ },
   22478             :   { Feature_isCIVI|Feature_isVI, 3414 /* ds_write_b128 */, MCK_ImmGDS, 8 /* 3 */ },
   22479             :   { Feature_isGCN|Feature_isSICI, 3428 /* ds_write_b16 */, MCK_ImmOffset, 4 /* 2 */ },
   22480             :   { Feature_isGCN|Feature_isSICI, 3428 /* ds_write_b16 */, MCK_ImmGDS, 8 /* 3 */ },
   22481             :   { Feature_isGCN|Feature_isVI, 3428 /* ds_write_b16 */, MCK_ImmOffset, 4 /* 2 */ },
   22482             :   { Feature_isGCN|Feature_isVI, 3428 /* ds_write_b16 */, MCK_ImmGDS, 8 /* 3 */ },
   22483             :   { Feature_HasD16LoadStore|Feature_isVI, 3441 /* ds_write_b16_d16_hi */, MCK_ImmOffset, 4 /* 2 */ },
   22484             :   { Feature_HasD16LoadStore|Feature_isVI, 3441 /* ds_write_b16_d16_hi */, MCK_ImmGDS, 8 /* 3 */ },
   22485             :   { Feature_isGCN|Feature_isSICI, 3461 /* ds_write_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22486             :   { Feature_isGCN|Feature_isSICI, 3461 /* ds_write_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22487             :   { Feature_isGCN|Feature_isVI, 3461 /* ds_write_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22488             :   { Feature_isGCN|Feature_isVI, 3461 /* ds_write_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22489             :   { Feature_isGCN|Feature_isSICI, 3474 /* ds_write_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22490             :   { Feature_isGCN|Feature_isSICI, 3474 /* ds_write_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22491             :   { Feature_isGCN|Feature_isVI, 3474 /* ds_write_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22492             :   { Feature_isGCN|Feature_isVI, 3474 /* ds_write_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22493             :   { Feature_isGCN|Feature_isSICI, 3487 /* ds_write_b8 */, MCK_ImmOffset, 4 /* 2 */ },
   22494             :   { Feature_isGCN|Feature_isSICI, 3487 /* ds_write_b8 */, MCK_ImmGDS, 8 /* 3 */ },
   22495             :   { Feature_isGCN|Feature_isVI, 3487 /* ds_write_b8 */, MCK_ImmOffset, 4 /* 2 */ },
   22496             :   { Feature_isGCN|Feature_isVI, 3487 /* ds_write_b8 */, MCK_ImmGDS, 8 /* 3 */ },
   22497             :   { Feature_HasD16LoadStore|Feature_isVI, 3499 /* ds_write_b8_d16_hi */, MCK_ImmOffset, 4 /* 2 */ },
   22498             :   { Feature_HasD16LoadStore|Feature_isVI, 3499 /* ds_write_b8_d16_hi */, MCK_ImmGDS, 8 /* 3 */ },
   22499             :   { Feature_isCIVI|Feature_isSICI, 3518 /* ds_write_b96 */, MCK_ImmOffset, 4 /* 2 */ },
   22500             :   { Feature_isCIVI|Feature_isSICI, 3518 /* ds_write_b96 */, MCK_ImmGDS, 8 /* 3 */ },
   22501             :   { Feature_isCIVI|Feature_isVI, 3518 /* ds_write_b96 */, MCK_ImmOffset, 4 /* 2 */ },
   22502             :   { Feature_isCIVI|Feature_isVI, 3518 /* ds_write_b96 */, MCK_ImmGDS, 8 /* 3 */ },
   22503             :   { Feature_isGCN|Feature_isSICI, 3531 /* ds_write_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22504             :   { Feature_isGCN|Feature_isSICI, 3531 /* ds_write_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22505             :   { Feature_isGCN|Feature_isVI, 3531 /* ds_write_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22506             :   { Feature_isGCN|Feature_isVI, 3531 /* ds_write_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22507             :   { Feature_isGCN|Feature_isSICI, 3549 /* ds_write_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22508             :   { Feature_isGCN|Feature_isSICI, 3549 /* ds_write_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22509             :   { Feature_isGCN|Feature_isVI, 3549 /* ds_write_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22510             :   { Feature_isGCN|Feature_isVI, 3549 /* ds_write_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22511             :   { Feature_isGCN|Feature_isSICI, 3567 /* ds_wrxchg2_rtn_b32 */, MCK_ImmOffset0, 16 /* 4 */ },
   22512             :   { Feature_isGCN|Feature_isSICI, 3567 /* ds_wrxchg2_rtn_b32 */, MCK_ImmOffset1, 32 /* 5 */ },
   22513             :   { Feature_isGCN|Feature_isSICI, 3567 /* ds_wrxchg2_rtn_b32 */, MCK_ImmGDS, 64 /* 6 */ },
   22514             :   { Feature_isGCN|Feature_isVI, 3567 /* ds_wrxchg2_rtn_b32 */, MCK_ImmOffset0, 16 /* 4 */ },
   22515             :   { Feature_isGCN|Feature_isVI, 3567 /* ds_wrxchg2_rtn_b32 */, MCK_ImmOffset1, 32 /* 5 */ },
   22516             :   { Feature_isGCN|Feature_isVI, 3567 /* ds_wrxchg2_rtn_b32 */, MCK_ImmGDS, 64 /* 6 */ },
   22517             :   { Feature_isGCN|Feature_isSICI, 3586 /* ds_wrxchg2_rtn_b64 */, MCK_ImmOffset0, 16 /* 4 */ },
   22518             :   { Feature_isGCN|Feature_isSICI, 3586 /* ds_wrxchg2_rtn_b64 */, MCK_ImmOffset1, 32 /* 5 */ },
   22519             :   { Feature_isGCN|Feature_isSICI, 3586 /* ds_wrxchg2_rtn_b64 */, MCK_ImmGDS, 64 /* 6 */ },
   22520             :   { Feature_isGCN|Feature_isVI, 3586 /* ds_wrxchg2_rtn_b64 */, MCK_ImmOffset0, 16 /* 4 */ },
   22521             :   { Feature_isGCN|Feature_isVI, 3586 /* ds_wrxchg2_rtn_b64 */, MCK_ImmOffset1, 32 /* 5 */ },
   22522             :   { Feature_isGCN|Feature_isVI, 3586 /* ds_wrxchg2_rtn_b64 */, MCK_ImmGDS, 64 /* 6 */ },
   22523             :   { Feature_isGCN|Feature_isSICI, 3605 /* ds_wrxchg2st64_rtn_b32 */, MCK_ImmOffset0, 16 /* 4 */ },
   22524             :   { Feature_isGCN|Feature_isSICI, 3605 /* ds_wrxchg2st64_rtn_b32 */, MCK_ImmOffset1, 32 /* 5 */ },
   22525             :   { Feature_isGCN|Feature_isSICI, 3605 /* ds_wrxchg2st64_rtn_b32 */, MCK_ImmGDS, 64 /* 6 */ },
   22526             :   { Feature_isGCN|Feature_isVI, 3605 /* ds_wrxchg2st64_rtn_b32 */, MCK_ImmOffset0, 16 /* 4 */ },
   22527             :   { Feature_isGCN|Feature_isVI, 3605 /* ds_wrxchg2st64_rtn_b32 */, MCK_ImmOffset1, 32 /* 5 */ },
   22528             :   { Feature_isGCN|Feature_isVI, 3605 /* ds_wrxchg2st64_rtn_b32 */, MCK_ImmGDS, 64 /* 6 */ },
   22529             :   { Feature_isGCN|Feature_isSICI, 3628 /* ds_wrxchg2st64_rtn_b64 */, MCK_ImmOffset0, 16 /* 4 */ },
   22530             :   { Feature_isGCN|Feature_isSICI, 3628 /* ds_wrxchg2st64_rtn_b64 */, MCK_ImmOffset1, 32 /* 5 */ },
   22531             :   { Feature_isGCN|Feature_isSICI, 3628 /* ds_wrxchg2st64_rtn_b64 */, MCK_ImmGDS, 64 /* 6 */ },
   22532             :   { Feature_isGCN|Feature_isVI, 3628 /* ds_wrxchg2st64_rtn_b64 */, MCK_ImmOffset0, 16 /* 4 */ },
   22533             :   { Feature_isGCN|Feature_isVI, 3628 /* ds_wrxchg2st64_rtn_b64 */, MCK_ImmOffset1, 32 /* 5 */ },
   22534             :   { Feature_isGCN|Feature_isVI, 3628 /* ds_wrxchg2st64_rtn_b64 */, MCK_ImmGDS, 64 /* 6 */ },
   22535             :   { Feature_isGCN|Feature_isSICI, 3651 /* ds_wrxchg_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22536             :   { Feature_isGCN|Feature_isSICI, 3651 /* ds_wrxchg_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22537             :   { Feature_isGCN|Feature_isVI, 3651 /* ds_wrxchg_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22538             :   { Feature_isGCN|Feature_isVI, 3651 /* ds_wrxchg_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22539             :   { Feature_isGCN|Feature_isSICI, 3669 /* ds_wrxchg_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22540             :   { Feature_isGCN|Feature_isSICI, 3669 /* ds_wrxchg_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22541             :   { Feature_isGCN|Feature_isVI, 3669 /* ds_wrxchg_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22542             :   { Feature_isGCN|Feature_isVI, 3669 /* ds_wrxchg_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22543             :   { Feature_isGCN|Feature_isSICI, 3687 /* ds_xor_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22544             :   { Feature_isGCN|Feature_isSICI, 3687 /* ds_xor_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22545             :   { Feature_isGCN|Feature_isVI, 3687 /* ds_xor_b32 */, MCK_ImmOffset, 4 /* 2 */ },
   22546             :   { Feature_isGCN|Feature_isVI, 3687 /* ds_xor_b32 */, MCK_ImmGDS, 8 /* 3 */ },
   22547             :   { Feature_isGCN|Feature_isSICI, 3698 /* ds_xor_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22548             :   { Feature_isGCN|Feature_isSICI, 3698 /* ds_xor_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22549             :   { Feature_isGCN|Feature_isVI, 3698 /* ds_xor_b64 */, MCK_ImmOffset, 4 /* 2 */ },
   22550             :   { Feature_isGCN|Feature_isVI, 3698 /* ds_xor_b64 */, MCK_ImmGDS, 8 /* 3 */ },
   22551             :   { Feature_isGCN|Feature_isSICI, 3709 /* ds_xor_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22552             :   { Feature_isGCN|Feature_isSICI, 3709 /* ds_xor_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22553             :   { Feature_isGCN|Feature_isVI, 3709 /* ds_xor_rtn_b32 */, MCK_ImmOffset, 8 /* 3 */ },
   22554             :   { Feature_isGCN|Feature_isVI, 3709 /* ds_xor_rtn_b32 */, MCK_ImmGDS, 16 /* 4 */ },
   22555             :   { Feature_isGCN|Feature_isSICI, 3724 /* ds_xor_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22556             :   { Feature_isGCN|Feature_isSICI, 3724 /* ds_xor_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22557             :   { Feature_isGCN|Feature_isVI, 3724 /* ds_xor_rtn_b64 */, MCK_ImmOffset, 8 /* 3 */ },
   22558             :   { Feature_isGCN|Feature_isVI, 3724 /* ds_xor_rtn_b64 */, MCK_ImmGDS, 16 /* 4 */ },
   22559             :   { Feature_isGCN|Feature_isSICI, 3739 /* ds_xor_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22560             :   { Feature_isGCN|Feature_isSICI, 3739 /* ds_xor_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22561             :   { Feature_isGCN|Feature_isVI, 3739 /* ds_xor_src2_b32 */, MCK_ImmOffset, 2 /* 1 */ },
   22562             :   { Feature_isGCN|Feature_isVI, 3739 /* ds_xor_src2_b32 */, MCK_ImmGDS, 4 /* 2 */ },
   22563             :   { Feature_isGCN|Feature_isSICI, 3755 /* ds_xor_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22564             :   { Feature_isGCN|Feature_isSICI, 3755 /* ds_xor_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22565             :   { Feature_isGCN|Feature_isVI, 3755 /* ds_xor_src2_b64 */, MCK_ImmOffset, 2 /* 1 */ },
   22566             :   { Feature_isGCN|Feature_isVI, 3755 /* ds_xor_src2_b64 */, MCK_ImmGDS, 4 /* 2 */ },
   22567             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_VReg32OrOff, 30 /* 1, 2, 3, 4 */ },
   22568             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_ImmExpCompr, 32 /* 5 */ },
   22569             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_ImmExpVM, 64 /* 6 */ },
   22570             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_ImmExpTgt, 1 /* 0 */ },
   22571             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_VReg32OrOff, 30 /* 1, 2, 3, 4 */ },
   22572             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_ImmExpCompr, 32 /* 5 */ },
   22573             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_ImmExpVM, 64 /* 6 */ },
   22574             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_ImmExpTgt, 1 /* 0 */ },
   22575             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_VReg32OrOff, 30 /* 1, 2, 3, 4 */ },
   22576             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_ImmExpCompr, 64 /* 6 */ },
   22577             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_ImmExpVM, 128 /* 7 */ },
   22578             :   { Feature_isGCN|Feature_isSICI, 3771 /* exp */, MCK_ImmExpTgt, 1 /* 0 */ },
   22579             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_VReg32OrOff, 30 /* 1, 2, 3, 4 */ },
   22580             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_ImmExpCompr, 64 /* 6 */ },
   22581             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_ImmExpVM, 128 /* 7 */ },
   22582             :   { Feature_isGCN|Feature_isVI, 3771 /* exp */, MCK_ImmExpTgt, 1 /* 0 */ },
   22583             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3775 /* flat_atomic_add */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22584             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3775 /* flat_atomic_add */, MCK_ImmSLC, 8 /* 3 */ },
   22585             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3775 /* flat_atomic_add */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22586             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3775 /* flat_atomic_add */, MCK_ImmSLC, 8 /* 3 */ },
   22587             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3775 /* flat_atomic_add */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22588             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3775 /* flat_atomic_add */, MCK_ImmSLC, 32 /* 5 */ },
   22589             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3775 /* flat_atomic_add */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22590             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3775 /* flat_atomic_add */, MCK_ImmSLC, 32 /* 5 */ },
   22591             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3791 /* flat_atomic_add_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22592             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3791 /* flat_atomic_add_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22593             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3791 /* flat_atomic_add_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22594             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3791 /* flat_atomic_add_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22595             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3791 /* flat_atomic_add_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22596             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3791 /* flat_atomic_add_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22597             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3791 /* flat_atomic_add_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22598             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3791 /* flat_atomic_add_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22599             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3810 /* flat_atomic_and */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22600             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3810 /* flat_atomic_and */, MCK_ImmSLC, 8 /* 3 */ },
   22601             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3810 /* flat_atomic_and */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22602             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3810 /* flat_atomic_and */, MCK_ImmSLC, 8 /* 3 */ },
   22603             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3810 /* flat_atomic_and */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22604             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3810 /* flat_atomic_and */, MCK_ImmSLC, 32 /* 5 */ },
   22605             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3810 /* flat_atomic_and */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22606             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3810 /* flat_atomic_and */, MCK_ImmSLC, 32 /* 5 */ },
   22607             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3826 /* flat_atomic_and_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22608             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3826 /* flat_atomic_and_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22609             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3826 /* flat_atomic_and_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22610             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3826 /* flat_atomic_and_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22611             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3826 /* flat_atomic_and_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22612             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3826 /* flat_atomic_and_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22613             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3826 /* flat_atomic_and_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22614             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3826 /* flat_atomic_and_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22615             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3845 /* flat_atomic_cmpswap */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22616             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3845 /* flat_atomic_cmpswap */, MCK_ImmSLC, 8 /* 3 */ },
   22617             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3845 /* flat_atomic_cmpswap */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22618             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3845 /* flat_atomic_cmpswap */, MCK_ImmSLC, 8 /* 3 */ },
   22619             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3845 /* flat_atomic_cmpswap */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22620             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3845 /* flat_atomic_cmpswap */, MCK_ImmSLC, 32 /* 5 */ },
   22621             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3845 /* flat_atomic_cmpswap */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22622             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3845 /* flat_atomic_cmpswap */, MCK_ImmSLC, 32 /* 5 */ },
   22623             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22624             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22625             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22626             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22627             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22628             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22629             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22630             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3865 /* flat_atomic_cmpswap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22631             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3888 /* flat_atomic_dec */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22632             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3888 /* flat_atomic_dec */, MCK_ImmSLC, 8 /* 3 */ },
   22633             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3888 /* flat_atomic_dec */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22634             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3888 /* flat_atomic_dec */, MCK_ImmSLC, 8 /* 3 */ },
   22635             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3888 /* flat_atomic_dec */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22636             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3888 /* flat_atomic_dec */, MCK_ImmSLC, 32 /* 5 */ },
   22637             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3888 /* flat_atomic_dec */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22638             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3888 /* flat_atomic_dec */, MCK_ImmSLC, 32 /* 5 */ },
   22639             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3904 /* flat_atomic_dec_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22640             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3904 /* flat_atomic_dec_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22641             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3904 /* flat_atomic_dec_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22642             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3904 /* flat_atomic_dec_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22643             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3904 /* flat_atomic_dec_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22644             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 3904 /* flat_atomic_dec_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22645             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3904 /* flat_atomic_dec_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22646             :   { Feature_HasFlatAddressSpace|Feature_isVI, 3904 /* flat_atomic_dec_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22647             :   { Feature_isCIOnly, 3923 /* flat_atomic_fcmpswap */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22648             :   { Feature_isCIOnly, 3923 /* flat_atomic_fcmpswap */, MCK_ImmSLC, 8 /* 3 */ },
   22649             :   { Feature_isCIOnly, 3923 /* flat_atomic_fcmpswap */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22650             :   { Feature_isCIOnly, 3923 /* flat_atomic_fcmpswap */, MCK_ImmSLC, 32 /* 5 */ },
   22651             :   { Feature_isCIOnly, 3944 /* flat_atomic_fcmpswap_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22652             :   { Feature_isCIOnly, 3944 /* flat_atomic_fcmpswap_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22653             :   { Feature_isCIOnly, 3944 /* flat_atomic_fcmpswap_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22654             :   { Feature_isCIOnly, 3944 /* flat_atomic_fcmpswap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22655             :   { Feature_isCIOnly, 3968 /* flat_atomic_fmax */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22656             :   { Feature_isCIOnly, 3968 /* flat_atomic_fmax */, MCK_ImmSLC, 8 /* 3 */ },
   22657             :   { Feature_isCIOnly, 3968 /* flat_atomic_fmax */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22658             :   { Feature_isCIOnly, 3968 /* flat_atomic_fmax */, MCK_ImmSLC, 32 /* 5 */ },
   22659             :   { Feature_isCIOnly, 3985 /* flat_atomic_fmax_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22660             :   { Feature_isCIOnly, 3985 /* flat_atomic_fmax_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22661             :   { Feature_isCIOnly, 3985 /* flat_atomic_fmax_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22662             :   { Feature_isCIOnly, 3985 /* flat_atomic_fmax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22663             :   { Feature_isCIOnly, 4005 /* flat_atomic_fmin */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22664             :   { Feature_isCIOnly, 4005 /* flat_atomic_fmin */, MCK_ImmSLC, 8 /* 3 */ },
   22665             :   { Feature_isCIOnly, 4005 /* flat_atomic_fmin */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22666             :   { Feature_isCIOnly, 4005 /* flat_atomic_fmin */, MCK_ImmSLC, 32 /* 5 */ },
   22667             :   { Feature_isCIOnly, 4022 /* flat_atomic_fmin_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22668             :   { Feature_isCIOnly, 4022 /* flat_atomic_fmin_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22669             :   { Feature_isCIOnly, 4022 /* flat_atomic_fmin_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22670             :   { Feature_isCIOnly, 4022 /* flat_atomic_fmin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22671             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4042 /* flat_atomic_inc */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22672             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4042 /* flat_atomic_inc */, MCK_ImmSLC, 8 /* 3 */ },
   22673             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4042 /* flat_atomic_inc */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22674             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4042 /* flat_atomic_inc */, MCK_ImmSLC, 8 /* 3 */ },
   22675             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4042 /* flat_atomic_inc */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22676             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4042 /* flat_atomic_inc */, MCK_ImmSLC, 32 /* 5 */ },
   22677             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4042 /* flat_atomic_inc */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22678             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4042 /* flat_atomic_inc */, MCK_ImmSLC, 32 /* 5 */ },
   22679             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4058 /* flat_atomic_inc_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22680             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4058 /* flat_atomic_inc_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22681             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4058 /* flat_atomic_inc_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22682             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4058 /* flat_atomic_inc_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22683             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4058 /* flat_atomic_inc_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22684             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4058 /* flat_atomic_inc_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22685             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4058 /* flat_atomic_inc_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22686             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4058 /* flat_atomic_inc_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22687             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4077 /* flat_atomic_or */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22688             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4077 /* flat_atomic_or */, MCK_ImmSLC, 8 /* 3 */ },
   22689             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4077 /* flat_atomic_or */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22690             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4077 /* flat_atomic_or */, MCK_ImmSLC, 8 /* 3 */ },
   22691             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4077 /* flat_atomic_or */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22692             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4077 /* flat_atomic_or */, MCK_ImmSLC, 32 /* 5 */ },
   22693             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4077 /* flat_atomic_or */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22694             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4077 /* flat_atomic_or */, MCK_ImmSLC, 32 /* 5 */ },
   22695             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4092 /* flat_atomic_or_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22696             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4092 /* flat_atomic_or_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22697             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4092 /* flat_atomic_or_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22698             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4092 /* flat_atomic_or_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22699             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4092 /* flat_atomic_or_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22700             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4092 /* flat_atomic_or_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22701             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4092 /* flat_atomic_or_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22702             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4092 /* flat_atomic_or_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22703             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4110 /* flat_atomic_smax */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22704             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4110 /* flat_atomic_smax */, MCK_ImmSLC, 8 /* 3 */ },
   22705             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4110 /* flat_atomic_smax */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22706             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4110 /* flat_atomic_smax */, MCK_ImmSLC, 8 /* 3 */ },
   22707             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4110 /* flat_atomic_smax */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22708             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4110 /* flat_atomic_smax */, MCK_ImmSLC, 32 /* 5 */ },
   22709             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4110 /* flat_atomic_smax */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22710             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4110 /* flat_atomic_smax */, MCK_ImmSLC, 32 /* 5 */ },
   22711             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4127 /* flat_atomic_smax_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22712             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4127 /* flat_atomic_smax_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22713             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4127 /* flat_atomic_smax_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22714             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4127 /* flat_atomic_smax_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22715             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4127 /* flat_atomic_smax_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22716             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4127 /* flat_atomic_smax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22717             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4127 /* flat_atomic_smax_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22718             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4127 /* flat_atomic_smax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22719             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4147 /* flat_atomic_smin */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22720             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4147 /* flat_atomic_smin */, MCK_ImmSLC, 8 /* 3 */ },
   22721             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4147 /* flat_atomic_smin */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22722             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4147 /* flat_atomic_smin */, MCK_ImmSLC, 8 /* 3 */ },
   22723             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4147 /* flat_atomic_smin */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22724             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4147 /* flat_atomic_smin */, MCK_ImmSLC, 32 /* 5 */ },
   22725             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4147 /* flat_atomic_smin */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22726             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4147 /* flat_atomic_smin */, MCK_ImmSLC, 32 /* 5 */ },
   22727             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4164 /* flat_atomic_smin_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22728             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4164 /* flat_atomic_smin_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22729             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4164 /* flat_atomic_smin_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22730             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4164 /* flat_atomic_smin_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22731             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4164 /* flat_atomic_smin_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22732             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4164 /* flat_atomic_smin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22733             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4164 /* flat_atomic_smin_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22734             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4164 /* flat_atomic_smin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22735             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4184 /* flat_atomic_sub */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22736             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4184 /* flat_atomic_sub */, MCK_ImmSLC, 8 /* 3 */ },
   22737             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4184 /* flat_atomic_sub */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22738             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4184 /* flat_atomic_sub */, MCK_ImmSLC, 8 /* 3 */ },
   22739             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4184 /* flat_atomic_sub */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22740             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4184 /* flat_atomic_sub */, MCK_ImmSLC, 32 /* 5 */ },
   22741             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4184 /* flat_atomic_sub */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22742             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4184 /* flat_atomic_sub */, MCK_ImmSLC, 32 /* 5 */ },
   22743             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4200 /* flat_atomic_sub_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22744             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4200 /* flat_atomic_sub_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22745             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4200 /* flat_atomic_sub_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22746             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4200 /* flat_atomic_sub_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22747             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4200 /* flat_atomic_sub_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22748             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4200 /* flat_atomic_sub_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22749             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4200 /* flat_atomic_sub_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22750             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4200 /* flat_atomic_sub_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22751             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4219 /* flat_atomic_swap */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22752             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4219 /* flat_atomic_swap */, MCK_ImmSLC, 8 /* 3 */ },
   22753             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4219 /* flat_atomic_swap */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22754             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4219 /* flat_atomic_swap */, MCK_ImmSLC, 8 /* 3 */ },
   22755             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4219 /* flat_atomic_swap */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22756             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4219 /* flat_atomic_swap */, MCK_ImmSLC, 32 /* 5 */ },
   22757             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4219 /* flat_atomic_swap */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22758             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4219 /* flat_atomic_swap */, MCK_ImmSLC, 32 /* 5 */ },
   22759             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4236 /* flat_atomic_swap_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22760             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4236 /* flat_atomic_swap_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22761             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4236 /* flat_atomic_swap_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22762             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4236 /* flat_atomic_swap_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22763             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4236 /* flat_atomic_swap_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22764             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4236 /* flat_atomic_swap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22765             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4236 /* flat_atomic_swap_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22766             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4236 /* flat_atomic_swap_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22767             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4256 /* flat_atomic_umax */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22768             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4256 /* flat_atomic_umax */, MCK_ImmSLC, 8 /* 3 */ },
   22769             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4256 /* flat_atomic_umax */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22770             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4256 /* flat_atomic_umax */, MCK_ImmSLC, 8 /* 3 */ },
   22771             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4256 /* flat_atomic_umax */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22772             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4256 /* flat_atomic_umax */, MCK_ImmSLC, 32 /* 5 */ },
   22773             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4256 /* flat_atomic_umax */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22774             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4256 /* flat_atomic_umax */, MCK_ImmSLC, 32 /* 5 */ },
   22775             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4273 /* flat_atomic_umax_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22776             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4273 /* flat_atomic_umax_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22777             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4273 /* flat_atomic_umax_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22778             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4273 /* flat_atomic_umax_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22779             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4273 /* flat_atomic_umax_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22780             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4273 /* flat_atomic_umax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22781             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4273 /* flat_atomic_umax_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22782             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4273 /* flat_atomic_umax_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22783             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4293 /* flat_atomic_umin */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22784             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4293 /* flat_atomic_umin */, MCK_ImmSLC, 8 /* 3 */ },
   22785             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4293 /* flat_atomic_umin */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22786             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4293 /* flat_atomic_umin */, MCK_ImmSLC, 8 /* 3 */ },
   22787             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4293 /* flat_atomic_umin */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22788             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4293 /* flat_atomic_umin */, MCK_ImmSLC, 32 /* 5 */ },
   22789             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4293 /* flat_atomic_umin */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22790             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4293 /* flat_atomic_umin */, MCK_ImmSLC, 32 /* 5 */ },
   22791             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4310 /* flat_atomic_umin_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22792             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4310 /* flat_atomic_umin_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22793             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4310 /* flat_atomic_umin_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22794             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4310 /* flat_atomic_umin_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22795             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4310 /* flat_atomic_umin_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22796             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4310 /* flat_atomic_umin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22797             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4310 /* flat_atomic_umin_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22798             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4310 /* flat_atomic_umin_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22799             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4330 /* flat_atomic_xor */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22800             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4330 /* flat_atomic_xor */, MCK_ImmSLC, 8 /* 3 */ },
   22801             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4330 /* flat_atomic_xor */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22802             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4330 /* flat_atomic_xor */, MCK_ImmSLC, 8 /* 3 */ },
   22803             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4330 /* flat_atomic_xor */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22804             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4330 /* flat_atomic_xor */, MCK_ImmSLC, 32 /* 5 */ },
   22805             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4330 /* flat_atomic_xor */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22806             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4330 /* flat_atomic_xor */, MCK_ImmSLC, 32 /* 5 */ },
   22807             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4346 /* flat_atomic_xor_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22808             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4346 /* flat_atomic_xor_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22809             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4346 /* flat_atomic_xor_x2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22810             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4346 /* flat_atomic_xor_x2 */, MCK_ImmSLC, 8 /* 3 */ },
   22811             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4346 /* flat_atomic_xor_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22812             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4346 /* flat_atomic_xor_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22813             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4346 /* flat_atomic_xor_x2 */, MCK_ImmOffsetU12, 8 /* 3 */ },
   22814             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4346 /* flat_atomic_xor_x2 */, MCK_ImmSLC, 32 /* 5 */ },
   22815             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4365 /* flat_load_dword */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22816             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4365 /* flat_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   22817             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4365 /* flat_load_dword */, MCK_ImmSLC, 16 /* 4 */ },
   22818             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4365 /* flat_load_dword */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22819             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4365 /* flat_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   22820             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4365 /* flat_load_dword */, MCK_ImmSLC, 16 /* 4 */ },
   22821             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4381 /* flat_load_dwordx2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22822             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4381 /* flat_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   22823             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4381 /* flat_load_dwordx2 */, MCK_ImmSLC, 16 /* 4 */ },
   22824             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4381 /* flat_load_dwordx2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22825             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4381 /* flat_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   22826             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4381 /* flat_load_dwordx2 */, MCK_ImmSLC, 16 /* 4 */ },
   22827             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4399 /* flat_load_dwordx3 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22828             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4399 /* flat_load_dwordx3 */, MCK_ImmGLC, 8 /* 3 */ },
   22829             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4399 /* flat_load_dwordx3 */, MCK_ImmSLC, 16 /* 4 */ },
   22830             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4399 /* flat_load_dwordx3 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22831             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4399 /* flat_load_dwordx3 */, MCK_ImmGLC, 8 /* 3 */ },
   22832             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4399 /* flat_load_dwordx3 */, MCK_ImmSLC, 16 /* 4 */ },
   22833             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4417 /* flat_load_dwordx4 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22834             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4417 /* flat_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   22835             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4417 /* flat_load_dwordx4 */, MCK_ImmSLC, 16 /* 4 */ },
   22836             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4417 /* flat_load_dwordx4 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22837             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4417 /* flat_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   22838             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4417 /* flat_load_dwordx4 */, MCK_ImmSLC, 16 /* 4 */ },
   22839             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4435 /* flat_load_sbyte */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22840             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4435 /* flat_load_sbyte */, MCK_ImmGLC, 8 /* 3 */ },
   22841             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4435 /* flat_load_sbyte */, MCK_ImmSLC, 16 /* 4 */ },
   22842             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4435 /* flat_load_sbyte */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22843             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4435 /* flat_load_sbyte */, MCK_ImmGLC, 8 /* 3 */ },
   22844             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4435 /* flat_load_sbyte */, MCK_ImmSLC, 16 /* 4 */ },
   22845             :   { Feature_HasD16LoadStore|Feature_isVI, 4451 /* flat_load_sbyte_d16 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22846             :   { Feature_HasD16LoadStore|Feature_isVI, 4451 /* flat_load_sbyte_d16 */, MCK_ImmGLC, 8 /* 3 */ },
   22847             :   { Feature_HasD16LoadStore|Feature_isVI, 4451 /* flat_load_sbyte_d16 */, MCK_ImmSLC, 16 /* 4 */ },
   22848             :   { Feature_HasD16LoadStore|Feature_isVI, 4471 /* flat_load_sbyte_d16_hi */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22849             :   { Feature_HasD16LoadStore|Feature_isVI, 4471 /* flat_load_sbyte_d16_hi */, MCK_ImmGLC, 8 /* 3 */ },
   22850             :   { Feature_HasD16LoadStore|Feature_isVI, 4471 /* flat_load_sbyte_d16_hi */, MCK_ImmSLC, 16 /* 4 */ },
   22851             :   { Feature_HasD16LoadStore|Feature_isVI, 4494 /* flat_load_short_d16 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22852             :   { Feature_HasD16LoadStore|Feature_isVI, 4494 /* flat_load_short_d16 */, MCK_ImmGLC, 8 /* 3 */ },
   22853             :   { Feature_HasD16LoadStore|Feature_isVI, 4494 /* flat_load_short_d16 */, MCK_ImmSLC, 16 /* 4 */ },
   22854             :   { Feature_HasD16LoadStore|Feature_isVI, 4514 /* flat_load_short_d16_hi */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22855             :   { Feature_HasD16LoadStore|Feature_isVI, 4514 /* flat_load_short_d16_hi */, MCK_ImmGLC, 8 /* 3 */ },
   22856             :   { Feature_HasD16LoadStore|Feature_isVI, 4514 /* flat_load_short_d16_hi */, MCK_ImmSLC, 16 /* 4 */ },
   22857             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4537 /* flat_load_sshort */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22858             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4537 /* flat_load_sshort */, MCK_ImmGLC, 8 /* 3 */ },
   22859             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4537 /* flat_load_sshort */, MCK_ImmSLC, 16 /* 4 */ },
   22860             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4537 /* flat_load_sshort */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22861             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4537 /* flat_load_sshort */, MCK_ImmGLC, 8 /* 3 */ },
   22862             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4537 /* flat_load_sshort */, MCK_ImmSLC, 16 /* 4 */ },
   22863             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4554 /* flat_load_ubyte */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22864             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4554 /* flat_load_ubyte */, MCK_ImmGLC, 8 /* 3 */ },
   22865             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4554 /* flat_load_ubyte */, MCK_ImmSLC, 16 /* 4 */ },
   22866             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4554 /* flat_load_ubyte */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22867             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4554 /* flat_load_ubyte */, MCK_ImmGLC, 8 /* 3 */ },
   22868             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4554 /* flat_load_ubyte */, MCK_ImmSLC, 16 /* 4 */ },
   22869             :   { Feature_HasD16LoadStore|Feature_isVI, 4570 /* flat_load_ubyte_d16 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22870             :   { Feature_HasD16LoadStore|Feature_isVI, 4570 /* flat_load_ubyte_d16 */, MCK_ImmGLC, 8 /* 3 */ },
   22871             :   { Feature_HasD16LoadStore|Feature_isVI, 4570 /* flat_load_ubyte_d16 */, MCK_ImmSLC, 16 /* 4 */ },
   22872             :   { Feature_HasD16LoadStore|Feature_isVI, 4590 /* flat_load_ubyte_d16_hi */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22873             :   { Feature_HasD16LoadStore|Feature_isVI, 4590 /* flat_load_ubyte_d16_hi */, MCK_ImmGLC, 8 /* 3 */ },
   22874             :   { Feature_HasD16LoadStore|Feature_isVI, 4590 /* flat_load_ubyte_d16_hi */, MCK_ImmSLC, 16 /* 4 */ },
   22875             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4613 /* flat_load_ushort */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22876             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4613 /* flat_load_ushort */, MCK_ImmGLC, 8 /* 3 */ },
   22877             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4613 /* flat_load_ushort */, MCK_ImmSLC, 16 /* 4 */ },
   22878             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4613 /* flat_load_ushort */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22879             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4613 /* flat_load_ushort */, MCK_ImmGLC, 8 /* 3 */ },
   22880             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4613 /* flat_load_ushort */, MCK_ImmSLC, 16 /* 4 */ },
   22881             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4630 /* flat_store_byte */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22882             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4630 /* flat_store_byte */, MCK_ImmGLC, 8 /* 3 */ },
   22883             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4630 /* flat_store_byte */, MCK_ImmSLC, 16 /* 4 */ },
   22884             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4630 /* flat_store_byte */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22885             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4630 /* flat_store_byte */, MCK_ImmGLC, 8 /* 3 */ },
   22886             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4630 /* flat_store_byte */, MCK_ImmSLC, 16 /* 4 */ },
   22887             :   { Feature_HasD16LoadStore|Feature_isVI, 4646 /* flat_store_byte_d16_hi */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22888             :   { Feature_HasD16LoadStore|Feature_isVI, 4646 /* flat_store_byte_d16_hi */, MCK_ImmGLC, 8 /* 3 */ },
   22889             :   { Feature_HasD16LoadStore|Feature_isVI, 4646 /* flat_store_byte_d16_hi */, MCK_ImmSLC, 16 /* 4 */ },
   22890             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4669 /* flat_store_dword */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22891             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4669 /* flat_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   22892             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4669 /* flat_store_dword */, MCK_ImmSLC, 16 /* 4 */ },
   22893             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4669 /* flat_store_dword */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22894             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4669 /* flat_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   22895             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4669 /* flat_store_dword */, MCK_ImmSLC, 16 /* 4 */ },
   22896             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4686 /* flat_store_dwordx2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22897             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4686 /* flat_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   22898             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4686 /* flat_store_dwordx2 */, MCK_ImmSLC, 16 /* 4 */ },
   22899             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4686 /* flat_store_dwordx2 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22900             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4686 /* flat_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   22901             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4686 /* flat_store_dwordx2 */, MCK_ImmSLC, 16 /* 4 */ },
   22902             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4705 /* flat_store_dwordx3 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22903             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4705 /* flat_store_dwordx3 */, MCK_ImmGLC, 8 /* 3 */ },
   22904             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4705 /* flat_store_dwordx3 */, MCK_ImmSLC, 16 /* 4 */ },
   22905             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4705 /* flat_store_dwordx3 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22906             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4705 /* flat_store_dwordx3 */, MCK_ImmGLC, 8 /* 3 */ },
   22907             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4705 /* flat_store_dwordx3 */, MCK_ImmSLC, 16 /* 4 */ },
   22908             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4724 /* flat_store_dwordx4 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22909             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4724 /* flat_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   22910             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4724 /* flat_store_dwordx4 */, MCK_ImmSLC, 16 /* 4 */ },
   22911             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4724 /* flat_store_dwordx4 */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22912             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4724 /* flat_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   22913             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4724 /* flat_store_dwordx4 */, MCK_ImmSLC, 16 /* 4 */ },
   22914             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4743 /* flat_store_short */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22915             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4743 /* flat_store_short */, MCK_ImmGLC, 8 /* 3 */ },
   22916             :   { Feature_HasFlatAddressSpace|Feature_isCIOnly, 4743 /* flat_store_short */, MCK_ImmSLC, 16 /* 4 */ },
   22917             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4743 /* flat_store_short */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22918             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4743 /* flat_store_short */, MCK_ImmGLC, 8 /* 3 */ },
   22919             :   { Feature_HasFlatAddressSpace|Feature_isVI, 4743 /* flat_store_short */, MCK_ImmSLC, 16 /* 4 */ },
   22920             :   { Feature_HasD16LoadStore|Feature_isVI, 4760 /* flat_store_short_d16_hi */, MCK_ImmOffsetU12, 4 /* 2 */ },
   22921             :   { Feature_HasD16LoadStore|Feature_isVI, 4760 /* flat_store_short_d16_hi */, MCK_ImmGLC, 8 /* 3 */ },
   22922             :   { Feature_HasD16LoadStore|Feature_isVI, 4760 /* flat_store_short_d16_hi */, MCK_ImmSLC, 16 /* 4 */ },
   22923             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22924             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmSLC, 16 /* 4 */ },
   22925             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22926             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmSLC, 16 /* 4 */ },
   22927             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22928             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   22929             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22930             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4784 /* global_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   22931             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22932             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22933             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22934             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22935             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22936             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22937             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22938             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4802 /* global_atomic_add_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22939             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22940             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmSLC, 16 /* 4 */ },
   22941             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22942             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmSLC, 16 /* 4 */ },
   22943             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22944             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   22945             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22946             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4823 /* global_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   22947             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22948             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22949             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22950             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22951             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22952             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22953             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22954             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4841 /* global_atomic_and_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22955             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22956             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmSLC, 16 /* 4 */ },
   22957             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22958             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmSLC, 16 /* 4 */ },
   22959             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22960             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   22961             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22962             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4862 /* global_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   22963             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22964             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22965             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22966             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22967             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22968             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22969             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22970             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4884 /* global_atomic_cmpswap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22971             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22972             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmSLC, 16 /* 4 */ },
   22973             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22974             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmSLC, 16 /* 4 */ },
   22975             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22976             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   22977             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22978             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4909 /* global_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   22979             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22980             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22981             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22982             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22983             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22984             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22985             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22986             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4927 /* global_atomic_dec_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   22987             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22988             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmSLC, 16 /* 4 */ },
   22989             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22990             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmSLC, 16 /* 4 */ },
   22991             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22992             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   22993             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmOffsetS13, 16 /* 4 */ },
   22994             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4948 /* global_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   22995             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22996             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22997             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   22998             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   22999             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23000             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23001             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23002             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4966 /* global_atomic_inc_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23003             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23004             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmSLC, 16 /* 4 */ },
   23005             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23006             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmSLC, 16 /* 4 */ },
   23007             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23008             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23009             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23010             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 4987 /* global_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23011             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23012             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23013             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23014             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23015             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23016             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23017             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23018             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5004 /* global_atomic_or_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23019             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23020             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmSLC, 16 /* 4 */ },
   23021             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23022             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmSLC, 16 /* 4 */ },
   23023             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23024             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   23025             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23026             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5024 /* global_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   23027             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23028             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23029             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23030             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23031             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23032             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23033             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23034             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5043 /* global_atomic_smax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23035             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23036             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmSLC, 16 /* 4 */ },
   23037             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23038             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmSLC, 16 /* 4 */ },
   23039             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23040             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   23041             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23042             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5065 /* global_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   23043             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23044             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23045             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23046             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23047             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23048             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23049             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23050             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5084 /* global_atomic_smin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23051             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23052             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmSLC, 16 /* 4 */ },
   23053             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23054             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmSLC, 16 /* 4 */ },
   23055             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23056             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   23057             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23058             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5106 /* global_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   23059             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23060             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23061             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23062             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23063             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23064             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23065             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23066             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5124 /* global_atomic_sub_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23067             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23068             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmSLC, 16 /* 4 */ },
   23069             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23070             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmSLC, 16 /* 4 */ },
   23071             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23072             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   23073             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23074             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5145 /* global_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   23075             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23076             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23077             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23078             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23079             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23080             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23081             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23082             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5164 /* global_atomic_swap_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23083             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23084             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmSLC, 16 /* 4 */ },
   23085             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23086             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmSLC, 16 /* 4 */ },
   23087             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23088             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   23089             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23090             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5186 /* global_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   23091             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23092             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23093             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23094             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23095             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23096             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23097             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23098             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5205 /* global_atomic_umax_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23099             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23100             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmSLC, 16 /* 4 */ },
   23101             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23102             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmSLC, 16 /* 4 */ },
   23103             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23104             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   23105             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23106             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5227 /* global_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   23107             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23108             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23109             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23110             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23111             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23112             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23113             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23114             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5246 /* global_atomic_umin_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23115             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23116             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmSLC, 16 /* 4 */ },
   23117             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23118             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmSLC, 16 /* 4 */ },
   23119             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23120             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   23121             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23122             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5268 /* global_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   23123             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23124             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23125             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23126             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmSLC, 16 /* 4 */ },
   23127             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23128             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23129             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmOffsetS13, 16 /* 4 */ },
   23130             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5286 /* global_atomic_xor_x2 */, MCK_ImmSLC, 64 /* 6 */ },
   23131             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5307 /* global_load_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23132             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5307 /* global_load_dword */, MCK_ImmGLC, 16 /* 4 */ },
   23133             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5307 /* global_load_dword */, MCK_ImmSLC, 32 /* 5 */ },
   23134             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5307 /* global_load_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23135             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5307 /* global_load_dword */, MCK_ImmGLC, 16 /* 4 */ },
   23136             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5307 /* global_load_dword */, MCK_ImmSLC, 32 /* 5 */ },
   23137             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5325 /* global_load_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23138             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5325 /* global_load_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   23139             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5325 /* global_load_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   23140             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5325 /* global_load_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23141             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5325 /* global_load_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   23142             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5325 /* global_load_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   23143             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5345 /* global_load_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23144             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5345 /* global_load_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   23145             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5345 /* global_load_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   23146             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5345 /* global_load_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23147             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5345 /* global_load_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   23148             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5345 /* global_load_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   23149             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5365 /* global_load_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23150             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5365 /* global_load_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   23151             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5365 /* global_load_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   23152             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5365 /* global_load_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23153             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5365 /* global_load_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   23154             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5365 /* global_load_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   23155             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5385 /* global_load_sbyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23156             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5385 /* global_load_sbyte */, MCK_ImmGLC, 16 /* 4 */ },
   23157             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5385 /* global_load_sbyte */, MCK_ImmSLC, 32 /* 5 */ },
   23158             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5385 /* global_load_sbyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23159             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5385 /* global_load_sbyte */, MCK_ImmGLC, 16 /* 4 */ },
   23160             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5385 /* global_load_sbyte */, MCK_ImmSLC, 32 /* 5 */ },
   23161             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5403 /* global_load_sbyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23162             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5403 /* global_load_sbyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   23163             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5403 /* global_load_sbyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   23164             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5403 /* global_load_sbyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23165             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5403 /* global_load_sbyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   23166             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5403 /* global_load_sbyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   23167             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5425 /* global_load_sbyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23168             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5425 /* global_load_sbyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23169             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5425 /* global_load_sbyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23170             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5425 /* global_load_sbyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23171             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5425 /* global_load_sbyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23172             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5425 /* global_load_sbyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23173             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5450 /* global_load_short_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23174             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5450 /* global_load_short_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   23175             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5450 /* global_load_short_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   23176             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5450 /* global_load_short_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23177             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5450 /* global_load_short_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   23178             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5450 /* global_load_short_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   23179             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5472 /* global_load_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23180             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5472 /* global_load_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23181             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5472 /* global_load_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23182             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5472 /* global_load_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23183             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5472 /* global_load_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23184             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5472 /* global_load_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23185             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5497 /* global_load_sshort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23186             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5497 /* global_load_sshort */, MCK_ImmGLC, 16 /* 4 */ },
   23187             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5497 /* global_load_sshort */, MCK_ImmSLC, 32 /* 5 */ },
   23188             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5497 /* global_load_sshort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23189             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5497 /* global_load_sshort */, MCK_ImmGLC, 16 /* 4 */ },
   23190             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5497 /* global_load_sshort */, MCK_ImmSLC, 32 /* 5 */ },
   23191             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5516 /* global_load_ubyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23192             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5516 /* global_load_ubyte */, MCK_ImmGLC, 16 /* 4 */ },
   23193             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5516 /* global_load_ubyte */, MCK_ImmSLC, 32 /* 5 */ },
   23194             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5516 /* global_load_ubyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23195             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5516 /* global_load_ubyte */, MCK_ImmGLC, 16 /* 4 */ },
   23196             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5516 /* global_load_ubyte */, MCK_ImmSLC, 32 /* 5 */ },
   23197             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5534 /* global_load_ubyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23198             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5534 /* global_load_ubyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   23199             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5534 /* global_load_ubyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   23200             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5534 /* global_load_ubyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23201             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5534 /* global_load_ubyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   23202             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5534 /* global_load_ubyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   23203             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5556 /* global_load_ubyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23204             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5556 /* global_load_ubyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23205             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5556 /* global_load_ubyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23206             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5556 /* global_load_ubyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23207             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5556 /* global_load_ubyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23208             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5556 /* global_load_ubyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23209             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5581 /* global_load_ushort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23210             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5581 /* global_load_ushort */, MCK_ImmGLC, 16 /* 4 */ },
   23211             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5581 /* global_load_ushort */, MCK_ImmSLC, 32 /* 5 */ },
   23212             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5581 /* global_load_ushort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23213             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5581 /* global_load_ushort */, MCK_ImmGLC, 16 /* 4 */ },
   23214             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5581 /* global_load_ushort */, MCK_ImmSLC, 32 /* 5 */ },
   23215             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5600 /* global_store_byte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23216             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5600 /* global_store_byte */, MCK_ImmGLC, 16 /* 4 */ },
   23217             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5600 /* global_store_byte */, MCK_ImmSLC, 32 /* 5 */ },
   23218             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5600 /* global_store_byte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23219             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5600 /* global_store_byte */, MCK_ImmGLC, 16 /* 4 */ },
   23220             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5600 /* global_store_byte */, MCK_ImmSLC, 32 /* 5 */ },
   23221             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5618 /* global_store_byte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23222             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5618 /* global_store_byte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23223             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5618 /* global_store_byte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23224             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5618 /* global_store_byte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23225             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5618 /* global_store_byte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23226             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5618 /* global_store_byte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23227             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5643 /* global_store_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23228             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5643 /* global_store_dword */, MCK_ImmGLC, 16 /* 4 */ },
   23229             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5643 /* global_store_dword */, MCK_ImmSLC, 32 /* 5 */ },
   23230             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5643 /* global_store_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23231             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5643 /* global_store_dword */, MCK_ImmGLC, 16 /* 4 */ },
   23232             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5643 /* global_store_dword */, MCK_ImmSLC, 32 /* 5 */ },
   23233             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5662 /* global_store_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23234             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5662 /* global_store_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   23235             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5662 /* global_store_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   23236             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5662 /* global_store_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23237             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5662 /* global_store_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   23238             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5662 /* global_store_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   23239             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5683 /* global_store_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23240             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5683 /* global_store_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   23241             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5683 /* global_store_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   23242             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5683 /* global_store_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23243             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5683 /* global_store_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   23244             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5683 /* global_store_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   23245             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5704 /* global_store_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23246             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5704 /* global_store_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   23247             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5704 /* global_store_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   23248             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5704 /* global_store_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23249             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5704 /* global_store_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   23250             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5704 /* global_store_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   23251             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5725 /* global_store_short */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23252             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5725 /* global_store_short */, MCK_ImmGLC, 16 /* 4 */ },
   23253             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5725 /* global_store_short */, MCK_ImmSLC, 32 /* 5 */ },
   23254             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5725 /* global_store_short */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23255             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5725 /* global_store_short */, MCK_ImmGLC, 16 /* 4 */ },
   23256             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5725 /* global_store_short */, MCK_ImmSLC, 32 /* 5 */ },
   23257             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5744 /* global_store_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23258             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5744 /* global_store_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23259             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5744 /* global_store_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23260             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5744 /* global_store_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   23261             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5744 /* global_store_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   23262             :   { Feature_HasFlatGlobalInsts|Feature_isVI, 5744 /* global_store_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   23263             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23264             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23265             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23266             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23267             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23268             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23269             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23270             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23271             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23272             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23273             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23274             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23275             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23276             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23277             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23278             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23279             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23280             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23281             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23282             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23283             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23284             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23285             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23286             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23287             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23288             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23289             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23290             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23291             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23292             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23293             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23294             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23295             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23296             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23297             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23298             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23299             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23300             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23301             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23302             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23303             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23304             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23305             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23306             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23307             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23308             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23309             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23310             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23311             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23312             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23313             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23314             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23315             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23316             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23317             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23318             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23319             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23320             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23321             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23322             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23323             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23324             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23325             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23326             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23327             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23328             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23329             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23330             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23331             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23332             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23333             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23334             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23335             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23336             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23337             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23338             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23339             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23340             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23341             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23342             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23343             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23344             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23345             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23346             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23347             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23348             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23349             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23350             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23351             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23352             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23353             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23354             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23355             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23356             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23357             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23358             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23359             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23360             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23361             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23362             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23363             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23364             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23365             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23366             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23367             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23368             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23369             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23370             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23371             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23372             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23373             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23374             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23375             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23376             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23377             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23378             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23379             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23380             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23381             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23382             :   { Feature_isGCN|Feature_isSICI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23383             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmGLC, 32 /* 5 */ },
   23384             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmSLC, 64 /* 6 */ },
   23385             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmTFE, 256 /* 8 */ },
   23386             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmUNorm, 16 /* 4 */ },
   23387             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDA, 1024 /* 10 */ },
   23388             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmR128A16, 128 /* 7 */ },
   23389             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmLWE, 512 /* 9 */ },
   23390             :   { Feature_isGCN|Feature_isVI, 5770 /* image_atomic_add */, MCK_ImmDMask, 8 /* 3 */ },
   23391             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23392             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23393             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23394             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23395             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23396             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23397             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23398             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23399             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23400             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23401             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23402             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23403             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23404             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23405             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23406             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23407             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23408             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23409             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23410             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23411             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23412             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23413             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23414             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23415             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23416             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23417             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23418             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23419             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23420             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23421             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23422             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23423             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23424             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23425             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23426             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23427             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23428             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23429             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23430             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23431             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23432             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23433             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23434             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23435             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23436             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23437             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23438             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23439             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23440             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23441             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23442             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23443             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23444             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23445             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23446             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23447             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23448             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23449             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23450             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23451             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23452             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23453             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23454             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23455             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23456             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23457             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23458             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23459             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23460             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23461             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23462             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23463             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23464             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23465             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23466             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23467             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23468             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23469             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23470             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23471             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23472             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23473             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23474             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23475             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23476             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23477             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23478             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23479             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23480             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23481             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23482             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23483             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23484             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23485             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23486             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23487             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23488             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23489             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23490             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23491             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23492             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23493             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23494             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23495             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23496             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23497             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23498             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23499             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23500             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23501             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23502             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23503             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23504             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23505             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23506             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23507             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23508             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23509             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23510             :   { Feature_isGCN|Feature_isSICI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23511             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmGLC, 32 /* 5 */ },
   23512             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmSLC, 64 /* 6 */ },
   23513             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmTFE, 256 /* 8 */ },
   23514             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmUNorm, 16 /* 4 */ },
   23515             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDA, 1024 /* 10 */ },
   23516             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmR128A16, 128 /* 7 */ },
   23517             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmLWE, 512 /* 9 */ },
   23518             :   { Feature_isGCN|Feature_isVI, 5787 /* image_atomic_and */, MCK_ImmDMask, 8 /* 3 */ },
   23519             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23520             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23521             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23522             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23523             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23524             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23525             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23526             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23527             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23528             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23529             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23530             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23531             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23532             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23533             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23534             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23535             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23536             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23537             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23538             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23539             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23540             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23541             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23542             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23543             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23544             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23545             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23546             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23547             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23548             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23549             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23550             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23551             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23552             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23553             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23554             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23555             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23556             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23557             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23558             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23559             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23560             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23561             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23562             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23563             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23564             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23565             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23566             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23567             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23568             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23569             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23570             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23571             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23572             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23573             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23574             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23575             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23576             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23577             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23578             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23579             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23580             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23581             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23582             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23583             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23584             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23585             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23586             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23587             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23588             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23589             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23590             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23591             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23592             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23593             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23594             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23595             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23596             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23597             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23598             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23599             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23600             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23601             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23602             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23603             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23604             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23605             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23606             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23607             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23608             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23609             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23610             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23611             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23612             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23613             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23614             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23615             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23616             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23617             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23618             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23619             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23620             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23621             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23622             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23623             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23624             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23625             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23626             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23627             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23628             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23629             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23630             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23631             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23632             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23633             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23634             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23635             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23636             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23637             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23638             :   { Feature_isGCN|Feature_isSICI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23639             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmGLC, 32 /* 5 */ },
   23640             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmSLC, 64 /* 6 */ },
   23641             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmTFE, 256 /* 8 */ },
   23642             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmUNorm, 16 /* 4 */ },
   23643             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDA, 1024 /* 10 */ },
   23644             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmR128A16, 128 /* 7 */ },
   23645             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmLWE, 512 /* 9 */ },
   23646             :   { Feature_isGCN|Feature_isVI, 5804 /* image_atomic_cmpswap */, MCK_ImmDMask, 8 /* 3 */ },
   23647             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23648             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23649             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23650             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23651             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23652             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23653             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23654             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23655             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23656             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23657             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23658             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23659             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23660             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23661             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23662             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23663             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23664             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23665             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23666             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23667             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23668             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23669             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23670             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23671             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23672             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23673             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23674             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23675             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23676             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23677             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23678             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23679             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23680             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23681             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23682             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23683             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23684             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23685             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23686             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23687             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23688             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23689             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23690             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23691             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23692             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23693             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23694             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23695             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23696             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23697             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23698             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23699             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23700             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23701             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23702             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23703             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23704             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23705             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23706             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23707             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23708             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23709             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23710             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23711             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23712             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23713             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23714             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23715             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23716             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23717             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23718             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23719             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23720             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23721             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23722             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23723             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23724             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23725             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23726             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23727             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23728             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23729             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23730             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23731             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23732             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23733             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23734             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23735             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23736             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23737             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23738             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23739             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23740             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23741             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23742             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23743             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23744             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23745             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23746             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23747             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23748             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23749             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23750             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23751             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23752             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23753             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23754             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23755             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23756             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23757             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23758             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23759             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23760             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23761             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23762             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23763             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23764             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23765             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23766             :   { Feature_isGCN|Feature_isSICI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23767             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmGLC, 32 /* 5 */ },
   23768             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmSLC, 64 /* 6 */ },
   23769             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmTFE, 256 /* 8 */ },
   23770             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmUNorm, 16 /* 4 */ },
   23771             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDA, 1024 /* 10 */ },
   23772             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmR128A16, 128 /* 7 */ },
   23773             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmLWE, 512 /* 9 */ },
   23774             :   { Feature_isGCN|Feature_isVI, 5825 /* image_atomic_dec */, MCK_ImmDMask, 8 /* 3 */ },
   23775             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23776             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23777             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23778             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23779             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23780             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23781             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23782             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23783             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23784             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23785             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23786             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23787             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23788             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23789             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23790             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23791             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23792             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23793             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23794             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23795             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23796             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23797             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23798             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23799             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23800             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23801             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23802             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23803             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23804             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23805             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23806             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23807             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23808             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23809             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23810             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23811             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23812             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23813             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23814             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23815             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23816             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23817             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23818             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23819             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23820             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23821             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23822             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23823             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23824             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23825             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23826             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23827             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23828             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23829             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23830             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23831             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23832             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23833             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23834             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23835             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23836             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23837             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23838             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23839             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23840             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23841             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23842             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23843             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23844             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23845             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23846             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23847             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23848             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23849             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23850             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23851             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23852             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23853             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23854             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23855             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23856             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23857             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23858             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23859             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23860             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23861             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23862             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23863             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23864             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23865             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23866             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23867             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23868             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23869             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23870             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23871             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23872             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23873             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23874             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23875             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23876             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23877             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23878             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23879             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23880             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23881             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23882             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23883             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23884             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23885             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23886             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23887             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23888             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23889             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23890             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23891             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23892             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23893             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23894             :   { Feature_isGCN|Feature_isSICI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23895             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmGLC, 32 /* 5 */ },
   23896             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmSLC, 64 /* 6 */ },
   23897             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmTFE, 256 /* 8 */ },
   23898             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmUNorm, 16 /* 4 */ },
   23899             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDA, 1024 /* 10 */ },
   23900             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmR128A16, 128 /* 7 */ },
   23901             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmLWE, 512 /* 9 */ },
   23902             :   { Feature_isGCN|Feature_isVI, 5842 /* image_atomic_inc */, MCK_ImmDMask, 8 /* 3 */ },
   23903             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23904             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23905             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23906             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23907             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23908             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23909             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23910             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23911             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23912             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23913             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23914             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23915             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23916             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23917             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23918             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23919             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23920             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23921             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23922             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23923             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23924             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23925             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23926             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23927             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23928             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23929             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23930             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23931             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23932             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23933             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23934             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23935             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23936             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23937             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23938             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23939             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23940             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23941             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23942             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23943             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23944             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23945             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23946             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23947             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23948             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23949             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23950             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23951             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23952             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23953             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23954             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23955             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23956             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23957             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23958             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23959             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23960             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23961             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23962             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23963             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23964             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23965             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23966             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23967             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23968             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23969             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23970             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23971             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23972             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23973             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23974             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23975             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23976             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23977             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23978             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23979             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23980             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23981             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23982             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23983             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23984             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23985             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23986             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23987             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23988             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23989             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23990             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23991             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   23992             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   23993             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   23994             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   23995             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   23996             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   23997             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   23998             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   23999             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   24000             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   24001             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   24002             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   24003             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   24004             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   24005             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   24006             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   24007             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   24008             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   24009             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   24010             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   24011             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   24012             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   24013             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   24014             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   24015             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   24016             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   24017             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   24018             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   24019             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   24020             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   24021             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   24022             :   { Feature_isGCN|Feature_isSICI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   24023             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmGLC, 32 /* 5 */ },
   24024             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmSLC, 64 /* 6 */ },
   24025             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmTFE, 256 /* 8 */ },
   24026             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmUNorm, 16 /* 4 */ },
   24027             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDA, 1024 /* 10 */ },
   24028             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmR128A16, 128 /* 7 */ },
   24029             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmLWE, 512 /* 9 */ },
   24030             :   { Feature_isGCN|Feature_isVI, 5859 /* image_atomic_or */, MCK_ImmDMask, 8 /* 3 */ },
   24031             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24032             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24033             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24034             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24035             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24036             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24037             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24038             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24039             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24040             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24041             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24042             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24043             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24044             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24045             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24046             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24047             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24048             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24049             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24050             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24051             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24052             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24053             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24054             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24055             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24056             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24057             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24058             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24059             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24060             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24061             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24062             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24063             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24064             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24065             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24066             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24067             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24068             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24069             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24070             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24071             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24072             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24073             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24074             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24075             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24076             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24077             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24078             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24079             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24080             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24081             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24082             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24083             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24084             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24085             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24086             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24087             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24088             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24089             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24090             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24091             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24092             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24093             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24094             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24095             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24096             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24097             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24098             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24099             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24100             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24101             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24102             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24103             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24104             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24105             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24106             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24107             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24108             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24109             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24110             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24111             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24112             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24113             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24114             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24115             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24116             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24117             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24118             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24119             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24120             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24121             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24122             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24123             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24124             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24125             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24126             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24127             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24128             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24129             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24130             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24131             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24132             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24133             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24134             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24135             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24136             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24137             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24138             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24139             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24140             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24141             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24142             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24143             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24144             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24145             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24146             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24147             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24148             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24149             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24150             :   { Feature_isGCN|Feature_isSICI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24151             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmGLC, 32 /* 5 */ },
   24152             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmSLC, 64 /* 6 */ },
   24153             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmTFE, 256 /* 8 */ },
   24154             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmUNorm, 16 /* 4 */ },
   24155             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDA, 1024 /* 10 */ },
   24156             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmR128A16, 128 /* 7 */ },
   24157             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmLWE, 512 /* 9 */ },
   24158             :   { Feature_isGCN|Feature_isVI, 5875 /* image_atomic_smax */, MCK_ImmDMask, 8 /* 3 */ },
   24159             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24160             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24161             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24162             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24163             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24164             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24165             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24166             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24167             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24168             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24169             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24170             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24171             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24172             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24173             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24174             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24175             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24176             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24177             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24178             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24179             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24180             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24181             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24182             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24183             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24184             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24185             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24186             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24187             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24188             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24189             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24190             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24191             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24192             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24193             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24194             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24195             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24196             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24197             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24198             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24199             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24200             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24201             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24202             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24203             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24204             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24205             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24206             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24207             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24208             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24209             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24210             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24211             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24212             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24213             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24214             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24215             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24216             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24217             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24218             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24219             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24220             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24221             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24222             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24223             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24224             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24225             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24226             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24227             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24228             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24229             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24230             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24231             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24232             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24233             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24234             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24235             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24236             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24237             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24238             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24239             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24240             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24241             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24242             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24243             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24244             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24245             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24246             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24247             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24248             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24249             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24250             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24251             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24252             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24253             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24254             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24255             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24256             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24257             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24258             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24259             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24260             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24261             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24262             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24263             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24264             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24265             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24266             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24267             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24268             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24269             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24270             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24271             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24272             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24273             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24274             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24275             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24276             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24277             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24278             :   { Feature_isGCN|Feature_isSICI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24279             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmGLC, 32 /* 5 */ },
   24280             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmSLC, 64 /* 6 */ },
   24281             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmTFE, 256 /* 8 */ },
   24282             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmUNorm, 16 /* 4 */ },
   24283             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDA, 1024 /* 10 */ },
   24284             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmR128A16, 128 /* 7 */ },
   24285             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmLWE, 512 /* 9 */ },
   24286             :   { Feature_isGCN|Feature_isVI, 5893 /* image_atomic_smin */, MCK_ImmDMask, 8 /* 3 */ },
   24287             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24288             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24289             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24290             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24291             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24292             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24293             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24294             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24295             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24296             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24297             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24298             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24299             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24300             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24301             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24302             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24303             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24304             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24305             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24306             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24307             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24308             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24309             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24310             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24311             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24312             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24313             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24314             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24315             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24316             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24317             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24318             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24319             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24320             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24321             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24322             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24323             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24324             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24325             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24326             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24327             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24328             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24329             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24330             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24331             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24332             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24333             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24334             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24335             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24336             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24337             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24338             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24339             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24340             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24341             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24342             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24343             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24344             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24345             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24346             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24347             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24348             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24349             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24350             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24351             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24352             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24353             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24354             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24355             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24356             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24357             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24358             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24359             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24360             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24361             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24362             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24363             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24364             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24365             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24366             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24367             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24368             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24369             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24370             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24371             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24372             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24373             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24374             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24375             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24376             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24377             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24378             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24379             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24380             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24381             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24382             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24383             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24384             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24385             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24386             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24387             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24388             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24389             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24390             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24391             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24392             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24393             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24394             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24395             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24396             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24397             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24398             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24399             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24400             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24401             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24402             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24403             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24404             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24405             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24406             :   { Feature_isGCN|Feature_isSICI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24407             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmGLC, 32 /* 5 */ },
   24408             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmSLC, 64 /* 6 */ },
   24409             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmTFE, 256 /* 8 */ },
   24410             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmUNorm, 16 /* 4 */ },
   24411             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDA, 1024 /* 10 */ },
   24412             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmR128A16, 128 /* 7 */ },
   24413             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmLWE, 512 /* 9 */ },
   24414             :   { Feature_isGCN|Feature_isVI, 5911 /* image_atomic_sub */, MCK_ImmDMask, 8 /* 3 */ },
   24415             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24416             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24417             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24418             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24419             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24420             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24421             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24422             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24423             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24424             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24425             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24426             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24427             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24428             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24429             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24430             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24431             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24432             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24433             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24434             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24435             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24436             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24437             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24438             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24439             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24440             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24441             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24442             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24443             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24444             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24445             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24446             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24447             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24448             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24449             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24450             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24451             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24452             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24453             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24454             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24455             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24456             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24457             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24458             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24459             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24460             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24461             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24462             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24463             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24464             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24465             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24466             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24467             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24468             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24469             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24470             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24471             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24472             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24473             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24474             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24475             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24476             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24477             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24478             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24479             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24480             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24481             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24482             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24483             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24484             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24485             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24486             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24487             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24488             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24489             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24490             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24491             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24492             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24493             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24494             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24495             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24496             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24497             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24498             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24499             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24500             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24501             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24502             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24503             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24504             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24505             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24506             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24507             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24508             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24509             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24510             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24511             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24512             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24513             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24514             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24515             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24516             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24517             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24518             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24519             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24520             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24521             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24522             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24523             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24524             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24525             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24526             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24527             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24528             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24529             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24530             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24531             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24532             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24533             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24534             :   { Feature_isGCN|Feature_isSICI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24535             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmGLC, 32 /* 5 */ },
   24536             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmSLC, 64 /* 6 */ },
   24537             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmTFE, 256 /* 8 */ },
   24538             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmUNorm, 16 /* 4 */ },
   24539             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDA, 1024 /* 10 */ },
   24540             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmR128A16, 128 /* 7 */ },
   24541             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmLWE, 512 /* 9 */ },
   24542             :   { Feature_isGCN|Feature_isVI, 5928 /* image_atomic_swap */, MCK_ImmDMask, 8 /* 3 */ },
   24543             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24544             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24545             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24546             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24547             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24548             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24549             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24550             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24551             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24552             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24553             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24554             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24555             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24556             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24557             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24558             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24559             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24560             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24561             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24562             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24563             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24564             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24565             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24566             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24567             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24568             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24569             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24570             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24571             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24572             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24573             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24574             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24575             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24576             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24577             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24578             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24579             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24580             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24581             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24582             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24583             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24584             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24585             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24586             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24587             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24588             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24589             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24590             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24591             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24592             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24593             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24594             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24595             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24596             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24597             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24598             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24599             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24600             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24601             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24602             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24603             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24604             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24605             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24606             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24607             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24608             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24609             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24610             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24611             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24612             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24613             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24614             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24615             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24616             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24617             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24618             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24619             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24620             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24621             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24622             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24623             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24624             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24625             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24626             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24627             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24628             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24629             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24630             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24631             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24632             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24633             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24634             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24635             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24636             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24637             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24638             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24639             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24640             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24641             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24642             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24643             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24644             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24645             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24646             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24647             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24648             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24649             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24650             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24651             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24652             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24653             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24654             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24655             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24656             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24657             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24658             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24659             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24660             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24661             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24662             :   { Feature_isGCN|Feature_isSICI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24663             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmGLC, 32 /* 5 */ },
   24664             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmSLC, 64 /* 6 */ },
   24665             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmTFE, 256 /* 8 */ },
   24666             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmUNorm, 16 /* 4 */ },
   24667             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDA, 1024 /* 10 */ },
   24668             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmR128A16, 128 /* 7 */ },
   24669             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmLWE, 512 /* 9 */ },
   24670             :   { Feature_isGCN|Feature_isVI, 5946 /* image_atomic_umax */, MCK_ImmDMask, 8 /* 3 */ },
   24671             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24672             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24673             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24674             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24675             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24676             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24677             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24678             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24679             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24680             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24681             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24682             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24683             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24684             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24685             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24686             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24687             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24688             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24689             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24690             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24691             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24692             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24693             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24694             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24695             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24696             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24697             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24698             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24699             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24700             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24701             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24702             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24703             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24704             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24705             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24706             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24707             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24708             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24709             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24710             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24711             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24712             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24713             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24714             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24715             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24716             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24717             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24718             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24719             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24720             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24721             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24722             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24723             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24724             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24725             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24726             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24727             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24728             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24729             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24730             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24731             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24732             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24733             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24734             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24735             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24736             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24737             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24738             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24739             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24740             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24741             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24742             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24743             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24744             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24745             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24746             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24747             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24748             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24749             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24750             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24751             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24752             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24753             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24754             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24755             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24756             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24757             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24758             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24759             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24760             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24761             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24762             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24763             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24764             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24765             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24766             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24767             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24768             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24769             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24770             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24771             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24772             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24773             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24774             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24775             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24776             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24777             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24778             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24779             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24780             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24781             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24782             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24783             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24784             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24785             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24786             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24787             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24788             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24789             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24790             :   { Feature_isGCN|Feature_isSICI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24791             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmGLC, 32 /* 5 */ },
   24792             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmSLC, 64 /* 6 */ },
   24793             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmTFE, 256 /* 8 */ },
   24794             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmUNorm, 16 /* 4 */ },
   24795             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDA, 1024 /* 10 */ },
   24796             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmR128A16, 128 /* 7 */ },
   24797             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmLWE, 512 /* 9 */ },
   24798             :   { Feature_isGCN|Feature_isVI, 5964 /* image_atomic_umin */, MCK_ImmDMask, 8 /* 3 */ },
   24799             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24800             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24801             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24802             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24803             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24804             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24805             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24806             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24807             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24808             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24809             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24810             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24811             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24812             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24813             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24814             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24815             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24816             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24817             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24818             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24819             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24820             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24821             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24822             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24823             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24824             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24825             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24826             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24827             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24828             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24829             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24830             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24831             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24832             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24833             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24834             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24835             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24836             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24837             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24838             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24839             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24840             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24841             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24842             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24843             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24844             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24845             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24846             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24847             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24848             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24849             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24850             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24851             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24852             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24853             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24854             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24855             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24856             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24857             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24858             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24859             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24860             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24861             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24862             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24863             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24864             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24865             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24866             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24867             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24868             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24869             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24870             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24871             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24872             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24873             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24874             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24875             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24876             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24877             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24878             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24879             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24880             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24881             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24882             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24883             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24884             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24885             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24886             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24887             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24888             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24889             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24890             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24891             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24892             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24893             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24894             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24895             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24896             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24897             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24898             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24899             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24900             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24901             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24902             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24903             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24904             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24905             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24906             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24907             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24908             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24909             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24910             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24911             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24912             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24913             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24914             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24915             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24916             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24917             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24918             :   { Feature_isGCN|Feature_isSICI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24919             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmGLC, 32 /* 5 */ },
   24920             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmSLC, 64 /* 6 */ },
   24921             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmTFE, 256 /* 8 */ },
   24922             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmUNorm, 16 /* 4 */ },
   24923             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDA, 1024 /* 10 */ },
   24924             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmR128A16, 128 /* 7 */ },
   24925             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmLWE, 512 /* 9 */ },
   24926             :   { Feature_isGCN|Feature_isVI, 5982 /* image_atomic_xor */, MCK_ImmDMask, 8 /* 3 */ },
   24927             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24928             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24929             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24930             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24931             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24932             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24933             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24934             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24935             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24936             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24937             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24938             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24939             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24940             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24941             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24942             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24943             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24944             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24945             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24946             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24947             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24948             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24949             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24950             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24951             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24952             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24953             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24954             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24955             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24956             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24957             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24958             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24959             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24960             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24961             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24962             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24963             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24964             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24965             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24966             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24967             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24968             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24969             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24970             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24971             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24972             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24973             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24974             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24975             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24976             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24977             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24978             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24979             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24980             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24981             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24982             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24983             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24984             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24985             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24986             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24987             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24988             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24989             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24990             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmGLC, 64 /* 6 */ },
   24991             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmSLC, 128 /* 7 */ },
   24992             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmTFE, 512 /* 9 */ },
   24993             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmUNorm, 32 /* 5 */ },
   24994             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDA, 2048 /* 11 */ },
   24995             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmR128A16, 256 /* 8 */ },
   24996             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmD16, 4096 /* 12 */ },
   24997             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmLWE, 1024 /* 10 */ },
   24998             :   { Feature_isGCN, 5999 /* image_gather4 */, MCK_ImmDMask, 16 /* 4 */ },
   24999             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmGLC, 64 /* 6 */ },
   25000             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmSLC, 128 /* 7 */ },
   25001             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmTFE, 512 /* 9 */ },
   25002             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25003             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDA, 2048 /* 11 */ },
   25004             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25005             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmD16, 4096 /* 12 */ },
   25006             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25007             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDMask, 16 /* 4 */ },
   25008             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmGLC, 64 /* 6 */ },
   25009             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmSLC, 128 /* 7 */ },
   25010             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmTFE, 512 /* 9 */ },
   25011             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25012             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDA, 2048 /* 11 */ },
   25013             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25014             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmD16, 4096 /* 12 */ },
   25015             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25016             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDMask, 16 /* 4 */ },
   25017             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmGLC, 64 /* 6 */ },
   25018             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmSLC, 128 /* 7 */ },
   25019             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmTFE, 512 /* 9 */ },
   25020             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25021             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDA, 2048 /* 11 */ },
   25022             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25023             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmD16, 4096 /* 12 */ },
   25024             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25025             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDMask, 16 /* 4 */ },
   25026             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmGLC, 64 /* 6 */ },
   25027             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmSLC, 128 /* 7 */ },
   25028             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmTFE, 512 /* 9 */ },
   25029             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25030             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDA, 2048 /* 11 */ },
   25031             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25032             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmD16, 4096 /* 12 */ },
   25033             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25034             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDMask, 16 /* 4 */ },
   25035             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmGLC, 64 /* 6 */ },
   25036             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmSLC, 128 /* 7 */ },
   25037             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmTFE, 512 /* 9 */ },
   25038             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25039             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDA, 2048 /* 11 */ },
   25040             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25041             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmD16, 4096 /* 12 */ },
   25042             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25043             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDMask, 16 /* 4 */ },
   25044             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmGLC, 64 /* 6 */ },
   25045             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmSLC, 128 /* 7 */ },
   25046             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmTFE, 512 /* 9 */ },
   25047             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25048             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDA, 2048 /* 11 */ },
   25049             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25050             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmD16, 4096 /* 12 */ },
   25051             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25052             :   { Feature_isGCN, 6013 /* image_gather4_b */, MCK_ImmDMask, 16 /* 4 */ },
   25053             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25054             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25055             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25056             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25057             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25058             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25059             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25060             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25061             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25062             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25063             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25064             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25065             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25066             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25067             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25068             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25069             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25070             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25071             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25072             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25073             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25074             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25075             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25076             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25077             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25078             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25079             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25080             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25081             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25082             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25083             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25084             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25085             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25086             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25087             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25088             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25089             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25090             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25091             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25092             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25093             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25094             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25095             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25096             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25097             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25098             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25099             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25100             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25101             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25102             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25103             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25104             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25105             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25106             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25107             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25108             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25109             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25110             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25111             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25112             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25113             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25114             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25115             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25116             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25117             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25118             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25119             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25120             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25121             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25122             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25123             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25124             :   { Feature_isGCN, 6029 /* image_gather4_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25125             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25126             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25127             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25128             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25129             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25130             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25131             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25132             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25133             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25134             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25135             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25136             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25137             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25138             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25139             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25140             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25141             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25142             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25143             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25144             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25145             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25146             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25147             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25148             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25149             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25150             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25151             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25152             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25153             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25154             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25155             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25156             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25157             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25158             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25159             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25160             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25161             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25162             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25163             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25164             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25165             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25166             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25167             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25168             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25169             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25170             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25171             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25172             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25173             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25174             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25175             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25176             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25177             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25178             :   { Feature_isGCN, 6048 /* image_gather4_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25179             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25180             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25181             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25182             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25183             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25184             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25185             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25186             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25187             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25188             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25189             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25190             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25191             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25192             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25193             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25194             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25195             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25196             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25197             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25198             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25199             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25200             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25201             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25202             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25203             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25204             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25205             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25206             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25207             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25208             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25209             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25210             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25211             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25212             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25213             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25214             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25215             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25216             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25217             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25218             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25219             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25220             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25221             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25222             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25223             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25224             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25225             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25226             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25227             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25228             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25229             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25230             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25231             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25232             :   { Feature_isGCN, 6069 /* image_gather4_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25233             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmGLC, 64 /* 6 */ },
   25234             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmSLC, 128 /* 7 */ },
   25235             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmTFE, 512 /* 9 */ },
   25236             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmUNorm, 32 /* 5 */ },
   25237             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDA, 2048 /* 11 */ },
   25238             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmR128A16, 256 /* 8 */ },
   25239             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmD16, 4096 /* 12 */ },
   25240             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmLWE, 1024 /* 10 */ },
   25241             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDMask, 16 /* 4 */ },
   25242             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmGLC, 64 /* 6 */ },
   25243             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmSLC, 128 /* 7 */ },
   25244             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmTFE, 512 /* 9 */ },
   25245             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmUNorm, 32 /* 5 */ },
   25246             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDA, 2048 /* 11 */ },
   25247             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmR128A16, 256 /* 8 */ },
   25248             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmD16, 4096 /* 12 */ },
   25249             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmLWE, 1024 /* 10 */ },
   25250             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDMask, 16 /* 4 */ },
   25251             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmGLC, 64 /* 6 */ },
   25252             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmSLC, 128 /* 7 */ },
   25253             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmTFE, 512 /* 9 */ },
   25254             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmUNorm, 32 /* 5 */ },
   25255             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDA, 2048 /* 11 */ },
   25256             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmR128A16, 256 /* 8 */ },
   25257             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmD16, 4096 /* 12 */ },
   25258             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmLWE, 1024 /* 10 */ },
   25259             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDMask, 16 /* 4 */ },
   25260             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmGLC, 64 /* 6 */ },
   25261             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmSLC, 128 /* 7 */ },
   25262             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmTFE, 512 /* 9 */ },
   25263             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmUNorm, 32 /* 5 */ },
   25264             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDA, 2048 /* 11 */ },
   25265             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmR128A16, 256 /* 8 */ },
   25266             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmD16, 4096 /* 12 */ },
   25267             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmLWE, 1024 /* 10 */ },
   25268             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDMask, 16 /* 4 */ },
   25269             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmGLC, 64 /* 6 */ },
   25270             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmSLC, 128 /* 7 */ },
   25271             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmTFE, 512 /* 9 */ },
   25272             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmUNorm, 32 /* 5 */ },
   25273             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDA, 2048 /* 11 */ },
   25274             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmR128A16, 256 /* 8 */ },
   25275             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmD16, 4096 /* 12 */ },
   25276             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmLWE, 1024 /* 10 */ },
   25277             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDMask, 16 /* 4 */ },
   25278             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmGLC, 64 /* 6 */ },
   25279             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmSLC, 128 /* 7 */ },
   25280             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmTFE, 512 /* 9 */ },
   25281             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmUNorm, 32 /* 5 */ },
   25282             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDA, 2048 /* 11 */ },
   25283             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmR128A16, 256 /* 8 */ },
   25284             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmD16, 4096 /* 12 */ },
   25285             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmLWE, 1024 /* 10 */ },
   25286             :   { Feature_isGCN, 6087 /* image_gather4_c */, MCK_ImmDMask, 16 /* 4 */ },
   25287             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   25288             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   25289             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   25290             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25291             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   25292             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25293             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   25294             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25295             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   25296             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   25297             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   25298             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   25299             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25300             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   25301             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25302             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   25303             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25304             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   25305             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   25306             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   25307             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   25308             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25309             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   25310             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25311             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   25312             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25313             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   25314             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   25315             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   25316             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   25317             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25318             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   25319             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25320             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   25321             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25322             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   25323             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   25324             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   25325             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   25326             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25327             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   25328             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25329             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   25330             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25331             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   25332             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   25333             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   25334             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   25335             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   25336             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   25337             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   25338             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   25339             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   25340             :   { Feature_isGCN, 6103 /* image_gather4_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   25341             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25342             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25343             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25344             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25345             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25346             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25347             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25348             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25349             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25350             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25351             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25352             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25353             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25354             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25355             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25356             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25357             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25358             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25359             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25360             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25361             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25362             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25363             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25364             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25365             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25366             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25367             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25368             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25369             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25370             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25371             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25372             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25373             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25374             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25375             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25376             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25377             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25378             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25379             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25380             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25381             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25382             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25383             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25384             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25385             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25386             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25387             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25388             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25389             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25390             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25391             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25392             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25393             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25394             :   { Feature_isGCN, 6121 /* image_gather4_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25395             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25396             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25397             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25398             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25399             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25400             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25401             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25402             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25403             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25404             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25405             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25406             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25407             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25408             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25409             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25410             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25411             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25412             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25413             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25414             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25415             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25416             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25417             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25418             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25419             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25420             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25421             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25422             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25423             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25424             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25425             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25426             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25427             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25428             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25429             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25430             :   { Feature_isGCN, 6142 /* image_gather4_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25431             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25432             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25433             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25434             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25435             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25436             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25437             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25438             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25439             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25440             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25441             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25442             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25443             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25444             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25445             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25446             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25447             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25448             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25449             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25450             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25451             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25452             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25453             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25454             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25455             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25456             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25457             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25458             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   25459             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   25460             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   25461             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25462             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   25463             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25464             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   25465             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25466             :   { Feature_isGCN, 6165 /* image_gather4_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   25467             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25468             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25469             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25470             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25471             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25472             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25473             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25474             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25475             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25476             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25477             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25478             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25479             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25480             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25481             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25482             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25483             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25484             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25485             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25486             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25487             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25488             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25489             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25490             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25491             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25492             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25493             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25494             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25495             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25496             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25497             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25498             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25499             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25500             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25501             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25502             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25503             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25504             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25505             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25506             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25507             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25508             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25509             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25510             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25511             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25512             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25513             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25514             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25515             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25516             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25517             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25518             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25519             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25520             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25521             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25522             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25523             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25524             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25525             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25526             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25527             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25528             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25529             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25530             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25531             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25532             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25533             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25534             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25535             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25536             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25537             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25538             :   { Feature_isGCN, 6185 /* image_gather4_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25539             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25540             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25541             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25542             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25543             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25544             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25545             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25546             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25547             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25548             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25549             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25550             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25551             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25552             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25553             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25554             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25555             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25556             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25557             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25558             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25559             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25560             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25561             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25562             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25563             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25564             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25565             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25566             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25567             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25568             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25569             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25570             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25571             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25572             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25573             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25574             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25575             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25576             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25577             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25578             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25579             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25580             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25581             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25582             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25583             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25584             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25585             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25586             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25587             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25588             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25589             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25590             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25591             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25592             :   { Feature_isGCN, 6204 /* image_gather4_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25593             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25594             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25595             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25596             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25597             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25598             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25599             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25600             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25601             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25602             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25603             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25604             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25605             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25606             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25607             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25608             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25609             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25610             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25611             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25612             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25613             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25614             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25615             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25616             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25617             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25618             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25619             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25620             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25621             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25622             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25623             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25624             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25625             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25626             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25627             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25628             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25629             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25630             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25631             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25632             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25633             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25634             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25635             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25636             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25637             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25638             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25639             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25640             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25641             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25642             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25643             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25644             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25645             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25646             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25647             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25648             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25649             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25650             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25651             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25652             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25653             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25654             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25655             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25656             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   25657             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   25658             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   25659             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   25660             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   25661             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   25662             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   25663             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   25664             :   { Feature_isGCN, 6225 /* image_gather4_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   25665             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   25666             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   25667             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   25668             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25669             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   25670             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25671             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   25672             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25673             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   25674             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   25675             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   25676             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   25677             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25678             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   25679             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25680             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   25681             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25682             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   25683             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   25684             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   25685             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   25686             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25687             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   25688             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25689             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   25690             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25691             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   25692             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   25693             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   25694             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   25695             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25696             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   25697             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25698             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   25699             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25700             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   25701             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   25702             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   25703             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   25704             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25705             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   25706             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25707             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   25708             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25709             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   25710             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   25711             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   25712             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   25713             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25714             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   25715             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25716             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   25717             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25718             :   { Feature_isGCN, 6243 /* image_gather4_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   25719             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   25720             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   25721             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   25722             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   25723             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   25724             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   25725             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   25726             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   25727             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   25728             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   25729             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   25730             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   25731             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   25732             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   25733             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   25734             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   25735             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   25736             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   25737             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   25738             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   25739             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   25740             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   25741             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   25742             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   25743             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   25744             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   25745             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   25746             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   25747             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   25748             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   25749             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   25750             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   25751             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   25752             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   25753             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   25754             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   25755             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   25756             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   25757             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   25758             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   25759             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   25760             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   25761             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   25762             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   25763             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   25764             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   25765             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   25766             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   25767             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   25768             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   25769             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   25770             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   25771             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   25772             :   { Feature_isGCN, 6263 /* image_gather4_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   25773             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   25774             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   25775             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   25776             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25777             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   25778             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25779             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   25780             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25781             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   25782             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   25783             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   25784             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   25785             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25786             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   25787             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25788             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   25789             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25790             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   25791             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   25792             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   25793             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   25794             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25795             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   25796             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25797             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   25798             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25799             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   25800             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   25801             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   25802             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   25803             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25804             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   25805             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25806             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   25807             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25808             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   25809             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   25810             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   25811             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   25812             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25813             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   25814             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25815             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   25816             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25817             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   25818             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   25819             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   25820             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   25821             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25822             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   25823             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25824             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   25825             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25826             :   { Feature_isGCN, 6282 /* image_gather4_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   25827             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   25828             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   25829             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   25830             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25831             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   25832             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25833             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   25834             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25835             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   25836             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   25837             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   25838             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   25839             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25840             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   25841             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25842             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   25843             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25844             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   25845             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   25846             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   25847             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   25848             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25849             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   25850             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25851             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   25852             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25853             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   25854             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   25855             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   25856             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   25857             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25858             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   25859             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25860             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   25861             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25862             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   25863             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   25864             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   25865             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   25866             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25867             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   25868             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25869             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   25870             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25871             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   25872             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   25873             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   25874             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   25875             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25876             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   25877             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25878             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   25879             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25880             :   { Feature_isGCN, 6303 /* image_gather4_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   25881             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25882             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25883             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25884             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25885             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25886             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25887             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25888             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25889             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25890             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25891             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25892             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25893             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25894             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25895             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25896             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25897             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25898             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25899             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25900             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25901             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25902             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25903             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25904             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25905             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25906             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25907             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25908             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25909             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25910             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25911             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25912             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25913             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25914             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25915             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25916             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25917             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25918             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25919             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25920             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25921             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25922             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25923             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25924             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25925             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25926             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25927             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25928             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25929             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25930             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25931             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25932             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25933             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25934             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25935             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25936             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25937             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25938             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25939             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25940             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25941             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25942             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25943             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25944             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmGLC, 64 /* 6 */ },
   25945             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmSLC, 128 /* 7 */ },
   25946             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmTFE, 512 /* 9 */ },
   25947             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   25948             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDA, 2048 /* 11 */ },
   25949             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   25950             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmD16, 4096 /* 12 */ },
   25951             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   25952             :   { Feature_isGCN, 6321 /* image_gather4_cl */, MCK_ImmDMask, 16 /* 4 */ },
   25953             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25954             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25955             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25956             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25957             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25958             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25959             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25960             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25961             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25962             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25963             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25964             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25965             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25966             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25967             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25968             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25969             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25970             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25971             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25972             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25973             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25974             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25975             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25976             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25977             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25978             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25979             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25980             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25981             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25982             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25983             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25984             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25985             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25986             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25987             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25988             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25989             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25990             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   25991             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   25992             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   25993             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   25994             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   25995             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   25996             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   25997             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   25998             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   25999             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   26000             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   26001             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26002             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   26003             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26004             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   26005             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26006             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   26007             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   26008             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   26009             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   26010             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26011             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   26012             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26013             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   26014             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26015             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   26016             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   26017             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   26018             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   26019             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26020             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   26021             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26022             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   26023             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26024             :   { Feature_isGCN, 6338 /* image_gather4_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   26025             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26026             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26027             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26028             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26029             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26030             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26031             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26032             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26033             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26034             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26035             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26036             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26037             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26038             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26039             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26040             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26041             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26042             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26043             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26044             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26045             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26046             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26047             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26048             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26049             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26050             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26051             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26052             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26053             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26054             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26055             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26056             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26057             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26058             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26059             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26060             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26061             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26062             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26063             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26064             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26065             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26066             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26067             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26068             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26069             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26070             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26071             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26072             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26073             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26074             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26075             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26076             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26077             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26078             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26079             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26080             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26081             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26082             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26083             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26084             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26085             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26086             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26087             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26088             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmGLC, 64 /* 6 */ },
   26089             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmSLC, 128 /* 7 */ },
   26090             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmTFE, 512 /* 9 */ },
   26091             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmUNorm, 32 /* 5 */ },
   26092             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDA, 2048 /* 11 */ },
   26093             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmR128A16, 256 /* 8 */ },
   26094             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmD16, 4096 /* 12 */ },
   26095             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmLWE, 1024 /* 10 */ },
   26096             :   { Feature_isGCN, 6357 /* image_gather4_l */, MCK_ImmDMask, 16 /* 4 */ },
   26097             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26098             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26099             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26100             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26101             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26102             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26103             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26104             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26105             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26106             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26107             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26108             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26109             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26110             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26111             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26112             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26113             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26114             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26115             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26116             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26117             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26118             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26119             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26120             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26121             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26122             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26123             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26124             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26125             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26126             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26127             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26128             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26129             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26130             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26131             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26132             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26133             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26134             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26135             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26136             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26137             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26138             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26139             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26140             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26141             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26142             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26143             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26144             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26145             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26146             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26147             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26148             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26149             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26150             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26151             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26152             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26153             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26154             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26155             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26156             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26157             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26158             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26159             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26160             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   26161             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   26162             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   26163             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26164             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   26165             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26166             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   26167             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26168             :   { Feature_isGCN, 6373 /* image_gather4_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   26169             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26170             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26171             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26172             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26173             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26174             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26175             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26176             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26177             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26178             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26179             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26180             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26181             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26182             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26183             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26184             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26185             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26186             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26187             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26188             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26189             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26190             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26191             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26192             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26193             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26194             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26195             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26196             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26197             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26198             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26199             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26200             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26201             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26202             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26203             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26204             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26205             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26206             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26207             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26208             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26209             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26210             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26211             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26212             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26213             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26214             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26215             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26216             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26217             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26218             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26219             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26220             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26221             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26222             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26223             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26224             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26225             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26226             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26227             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26228             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26229             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26230             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26231             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26232             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmGLC, 64 /* 6 */ },
   26233             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmSLC, 128 /* 7 */ },
   26234             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmTFE, 512 /* 9 */ },
   26235             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   26236             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDA, 2048 /* 11 */ },
   26237             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   26238             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmD16, 4096 /* 12 */ },
   26239             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   26240             :   { Feature_isGCN, 6391 /* image_gather4_lz */, MCK_ImmDMask, 16 /* 4 */ },
   26241             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   26242             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   26243             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   26244             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26245             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   26246             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26247             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   26248             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26249             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   26250             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   26251             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   26252             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   26253             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26254             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   26255             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26256             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   26257             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26258             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   26259             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   26260             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   26261             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   26262             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26263             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   26264             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26265             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   26266             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26267             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   26268             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   26269             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   26270             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   26271             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26272             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   26273             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26274             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   26275             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26276             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   26277             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   26278             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   26279             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   26280             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26281             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   26282             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26283             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   26284             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26285             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   26286             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   26287             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   26288             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   26289             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26290             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   26291             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26292             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   26293             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26294             :   { Feature_isGCN, 6408 /* image_gather4_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   26295             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmGLC, 64 /* 6 */ },
   26296             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmSLC, 128 /* 7 */ },
   26297             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmTFE, 512 /* 9 */ },
   26298             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26299             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDA, 2048 /* 11 */ },
   26300             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26301             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmD16, 4096 /* 12 */ },
   26302             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26303             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDMask, 16 /* 4 */ },
   26304             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmGLC, 64 /* 6 */ },
   26305             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmSLC, 128 /* 7 */ },
   26306             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmTFE, 512 /* 9 */ },
   26307             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26308             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDA, 2048 /* 11 */ },
   26309             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26310             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmD16, 4096 /* 12 */ },
   26311             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26312             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDMask, 16 /* 4 */ },
   26313             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmGLC, 64 /* 6 */ },
   26314             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmSLC, 128 /* 7 */ },
   26315             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmTFE, 512 /* 9 */ },
   26316             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26317             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDA, 2048 /* 11 */ },
   26318             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26319             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmD16, 4096 /* 12 */ },
   26320             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26321             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDMask, 16 /* 4 */ },
   26322             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmGLC, 64 /* 6 */ },
   26323             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmSLC, 128 /* 7 */ },
   26324             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmTFE, 512 /* 9 */ },
   26325             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26326             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDA, 2048 /* 11 */ },
   26327             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26328             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmD16, 4096 /* 12 */ },
   26329             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26330             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDMask, 16 /* 4 */ },
   26331             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmGLC, 64 /* 6 */ },
   26332             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmSLC, 128 /* 7 */ },
   26333             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmTFE, 512 /* 9 */ },
   26334             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26335             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDA, 2048 /* 11 */ },
   26336             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26337             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmD16, 4096 /* 12 */ },
   26338             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26339             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDMask, 16 /* 4 */ },
   26340             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmGLC, 64 /* 6 */ },
   26341             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmSLC, 128 /* 7 */ },
   26342             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmTFE, 512 /* 9 */ },
   26343             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmUNorm, 32 /* 5 */ },
   26344             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDA, 2048 /* 11 */ },
   26345             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmR128A16, 256 /* 8 */ },
   26346             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmD16, 4096 /* 12 */ },
   26347             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmLWE, 1024 /* 10 */ },
   26348             :   { Feature_isGCN, 6427 /* image_gather4_o */, MCK_ImmDMask, 16 /* 4 */ },
   26349             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26350             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26351             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26352             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26353             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26354             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26355             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26356             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26357             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26358             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26359             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26360             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26361             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26362             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26363             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26364             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26365             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26366             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26367             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26368             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26369             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26370             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26371             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26372             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26373             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26374             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26375             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26376             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26377             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26378             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26379             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26380             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26381             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26382             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26383             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26384             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26385             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26386             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26387             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26388             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26389             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26390             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26391             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26392             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26393             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26394             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26395             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26396             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26397             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26398             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26399             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26400             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26401             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26402             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26403             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26404             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26405             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26406             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26407             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26408             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26409             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26410             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26411             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26412             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26413             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26414             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26415             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26416             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26417             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26418             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26419             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26420             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26421             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26422             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26423             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26424             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26425             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26426             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26427             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26428             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26429             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26430             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26431             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26432             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26433             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26434             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26435             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26436             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26437             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26438             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26439             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26440             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26441             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26442             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26443             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26444             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26445             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26446             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26447             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26448             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26449             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26450             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26451             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26452             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26453             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26454             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26455             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26456             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26457             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26458             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26459             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26460             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26461             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26462             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26463             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26464             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26465             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26466             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26467             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26468             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26469             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmGLC, 64 /* 6 */ },
   26470             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmSLC, 128 /* 7 */ },
   26471             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmTFE, 512 /* 9 */ },
   26472             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmUNorm, 32 /* 5 */ },
   26473             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDA, 2048 /* 11 */ },
   26474             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmR128A16, 256 /* 8 */ },
   26475             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmLWE, 1024 /* 10 */ },
   26476             :   { Feature_isGCN, 6443 /* image_get_lod */, MCK_ImmDMask, 16 /* 4 */ },
   26477             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26478             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26479             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26480             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26481             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26482             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26483             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26484             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26485             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26486             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26487             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26488             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26489             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26490             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26491             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26492             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26493             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26494             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26495             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26496             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26497             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26498             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26499             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26500             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26501             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26502             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26503             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26504             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26505             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26506             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26507             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26508             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26509             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26510             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26511             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26512             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26513             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26514             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26515             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26516             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26517             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26518             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26519             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26520             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26521             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26522             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26523             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26524             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26525             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26526             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26527             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26528             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26529             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26530             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26531             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26532             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26533             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26534             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26535             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26536             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26537             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26538             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26539             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26540             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26541             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26542             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26543             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26544             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26545             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26546             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26547             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26548             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26549             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26550             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26551             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26552             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26553             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26554             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26555             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26556             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26557             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26558             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26559             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26560             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26561             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26562             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26563             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26564             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26565             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26566             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26567             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26568             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26569             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26570             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26571             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26572             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26573             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26574             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26575             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26576             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26577             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26578             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26579             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26580             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26581             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26582             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26583             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26584             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26585             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26586             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26587             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26588             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26589             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26590             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26591             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26592             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26593             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26594             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26595             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26596             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26597             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmGLC, 32 /* 5 */ },
   26598             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmSLC, 64 /* 6 */ },
   26599             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmTFE, 256 /* 8 */ },
   26600             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmUNorm, 16 /* 4 */ },
   26601             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDA, 1024 /* 10 */ },
   26602             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmR128A16, 128 /* 7 */ },
   26603             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmLWE, 512 /* 9 */ },
   26604             :   { Feature_isGCN, 6457 /* image_get_resinfo */, MCK_ImmDMask, 8 /* 3 */ },
   26605             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26606             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26607             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26608             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26609             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26610             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26611             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26612             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26613             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26614             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26615             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26616             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26617             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26618             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26619             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26620             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26621             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26622             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26623             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26624             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26625             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26626             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26627             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26628             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26629             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26630             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26631             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26632             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26633             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26634             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26635             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26636             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26637             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26638             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26639             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26640             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26641             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26642             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26643             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26644             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26645             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26646             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26647             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26648             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26649             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26650             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26651             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26652             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26653             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26654             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26655             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26656             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26657             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26658             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26659             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26660             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26661             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26662             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26663             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26664             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26665             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26666             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26667             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26668             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26669             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26670             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26671             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26672             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26673             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26674             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26675             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26676             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26677             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26678             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26679             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26680             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26681             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26682             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26683             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26684             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26685             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26686             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26687             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26688             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26689             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26690             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26691             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26692             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26693             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26694             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26695             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26696             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26697             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26698             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26699             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26700             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26701             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26702             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26703             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26704             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26705             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26706             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26707             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26708             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26709             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26710             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26711             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26712             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26713             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26714             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26715             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26716             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26717             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26718             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26719             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26720             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26721             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26722             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26723             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26724             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26725             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26726             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26727             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26728             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26729             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26730             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26731             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26732             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26733             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26734             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26735             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26736             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26737             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26738             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26739             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26740             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmGLC, 32 /* 5 */ },
   26741             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmSLC, 64 /* 6 */ },
   26742             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmTFE, 256 /* 8 */ },
   26743             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmUNorm, 16 /* 4 */ },
   26744             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDA, 1024 /* 10 */ },
   26745             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmR128A16, 128 /* 7 */ },
   26746             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmD16, 2048 /* 11 */ },
   26747             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmLWE, 512 /* 9 */ },
   26748             :   { Feature_isGCN, 6475 /* image_load */, MCK_ImmDMask, 8 /* 3 */ },
   26749             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26750             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26751             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26752             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26753             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26754             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26755             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26756             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26757             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26758             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26759             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26760             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26761             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26762             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26763             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26764             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26765             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26766             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26767             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26768             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26769             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26770             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26771             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26772             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26773             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26774             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26775             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26776             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26777             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26778             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26779             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26780             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26781             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26782             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26783             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26784             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26785             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26786             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26787             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26788             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26789             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26790             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26791             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26792             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26793             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26794             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26795             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26796             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26797             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26798             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26799             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26800             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26801             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26802             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26803             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26804             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26805             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26806             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26807             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26808             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26809             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26810             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26811             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26812             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26813             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26814             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26815             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26816             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26817             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26818             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26819             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26820             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26821             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26822             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26823             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26824             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26825             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26826             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26827             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26828             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26829             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26830             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26831             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26832             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26833             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26834             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26835             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26836             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26837             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26838             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26839             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26840             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26841             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26842             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26843             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26844             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26845             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26846             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26847             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26848             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26849             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26850             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26851             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26852             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26853             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26854             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26855             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26856             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26857             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26858             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26859             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26860             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26861             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26862             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26863             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26864             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26865             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26866             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26867             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26868             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26869             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26870             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26871             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26872             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26873             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26874             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26875             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26876             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26877             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26878             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26879             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26880             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26881             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26882             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26883             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26884             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmGLC, 32 /* 5 */ },
   26885             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmSLC, 64 /* 6 */ },
   26886             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmTFE, 256 /* 8 */ },
   26887             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   26888             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDA, 1024 /* 10 */ },
   26889             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   26890             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmD16, 2048 /* 11 */ },
   26891             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmLWE, 512 /* 9 */ },
   26892             :   { Feature_isGCN, 6486 /* image_load_mip */, MCK_ImmDMask, 8 /* 3 */ },
   26893             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26894             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26895             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26896             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26897             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26898             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26899             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26900             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26901             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26902             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26903             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26904             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26905             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26906             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26907             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26908             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26909             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26910             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26911             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26912             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26913             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26914             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26915             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26916             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26917             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26918             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26919             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26920             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26921             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26922             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26923             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26924             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26925             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26926             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26927             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26928             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26929             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26930             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26931             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26932             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26933             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26934             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26935             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26936             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26937             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26938             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26939             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26940             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26941             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26942             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26943             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26944             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26945             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26946             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26947             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26948             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26949             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26950             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26951             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26952             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26953             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26954             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26955             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26956             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26957             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26958             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26959             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26960             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26961             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26962             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26963             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26964             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26965             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26966             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26967             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26968             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26969             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26970             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26971             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26972             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26973             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26974             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26975             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26976             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26977             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26978             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26979             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26980             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26981             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26982             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26983             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26984             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26985             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26986             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26987             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26988             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26989             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26990             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26991             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   26992             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   26993             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   26994             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   26995             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   26996             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   26997             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   26998             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   26999             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27000             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27001             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27002             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27003             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27004             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27005             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27006             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27007             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27008             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27009             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27010             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27011             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27012             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27013             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27014             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27015             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27016             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27017             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27018             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27019             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27020             :   { Feature_isGCN, 6501 /* image_load_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27021             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27022             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27023             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27024             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27025             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27026             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27027             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27028             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27029             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27030             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27031             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27032             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27033             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27034             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27035             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27036             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27037             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27038             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27039             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27040             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27041             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27042             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27043             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27044             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27045             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27046             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27047             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27048             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27049             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27050             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27051             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27052             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27053             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27054             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27055             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27056             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27057             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27058             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27059             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27060             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27061             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27062             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27063             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27064             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27065             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27066             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27067             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27068             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27069             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27070             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27071             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27072             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27073             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27074             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27075             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27076             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27077             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27078             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27079             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27080             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27081             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27082             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27083             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27084             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27085             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27086             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27087             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27088             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27089             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27090             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27091             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27092             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27093             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27094             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27095             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27096             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27097             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27098             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27099             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27100             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27101             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27102             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27103             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27104             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27105             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27106             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27107             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27108             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27109             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27110             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27111             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27112             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27113             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27114             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27115             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27116             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27117             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27118             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27119             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27120             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27121             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27122             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27123             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27124             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27125             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27126             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27127             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27128             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27129             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27130             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27131             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27132             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27133             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27134             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27135             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27136             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27137             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27138             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27139             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27140             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27141             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27142             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27143             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27144             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27145             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27146             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27147             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27148             :   { Feature_isGCN, 6520 /* image_load_mip_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27149             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27150             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27151             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27152             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27153             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27154             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27155             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27156             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27157             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27158             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27159             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27160             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27161             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27162             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27163             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27164             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27165             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27166             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27167             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27168             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27169             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27170             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27171             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27172             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27173             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27174             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27175             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27176             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27177             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27178             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27179             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27180             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27181             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27182             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27183             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27184             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27185             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27186             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27187             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27188             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27189             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27190             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27191             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27192             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27193             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27194             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27195             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27196             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27197             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27198             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27199             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27200             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27201             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27202             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27203             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27204             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27205             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27206             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27207             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27208             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27209             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27210             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27211             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27212             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27213             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27214             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27215             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27216             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27217             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27218             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27219             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27220             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27221             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27222             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27223             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27224             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27225             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27226             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27227             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27228             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27229             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27230             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27231             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27232             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27233             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27234             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27235             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27236             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27237             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27238             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27239             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27240             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27241             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27242             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27243             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27244             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27245             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27246             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27247             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27248             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27249             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27250             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27251             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27252             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27253             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27254             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27255             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27256             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27257             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27258             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27259             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27260             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27261             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27262             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27263             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27264             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27265             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27266             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27267             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27268             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27269             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmGLC, 32 /* 5 */ },
   27270             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmSLC, 64 /* 6 */ },
   27271             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmTFE, 256 /* 8 */ },
   27272             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   27273             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDA, 1024 /* 10 */ },
   27274             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   27275             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmLWE, 512 /* 9 */ },
   27276             :   { Feature_isGCN, 6543 /* image_load_pck */, MCK_ImmDMask, 8 /* 3 */ },
   27277             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27278             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27279             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27280             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27281             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27282             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27283             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27284             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27285             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27286             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27287             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27288             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27289             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27290             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27291             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27292             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27293             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27294             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27295             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27296             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27297             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27298             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27299             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27300             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27301             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27302             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27303             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27304             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27305             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27306             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27307             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27308             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27309             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27310             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27311             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27312             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27313             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27314             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27315             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27316             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27317             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27318             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27319             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27320             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27321             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27322             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27323             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27324             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27325             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27326             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27327             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27328             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27329             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27330             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27331             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27332             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27333             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27334             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27335             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27336             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27337             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27338             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27339             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27340             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27341             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27342             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27343             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27344             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27345             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27346             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27347             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27348             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27349             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27350             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27351             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27352             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27353             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27354             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27355             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27356             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27357             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27358             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27359             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27360             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27361             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27362             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27363             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27364             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27365             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27366             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27367             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27368             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27369             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27370             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27371             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27372             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27373             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27374             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27375             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27376             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27377             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27378             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27379             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27380             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27381             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27382             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27383             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27384             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27385             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27386             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27387             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27388             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27389             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27390             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27391             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27392             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27393             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27394             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27395             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27396             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27397             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmGLC, 32 /* 5 */ },
   27398             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmSLC, 64 /* 6 */ },
   27399             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmTFE, 256 /* 8 */ },
   27400             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmUNorm, 16 /* 4 */ },
   27401             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDA, 1024 /* 10 */ },
   27402             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmR128A16, 128 /* 7 */ },
   27403             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmLWE, 512 /* 9 */ },
   27404             :   { Feature_isGCN, 6558 /* image_load_pck_sgn */, MCK_ImmDMask, 8 /* 3 */ },
   27405             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27406             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27407             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27408             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27409             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27410             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27411             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27412             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27413             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27414             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27415             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27416             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27417             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27418             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27419             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27420             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27421             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27422             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27423             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27424             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27425             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27426             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27427             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27428             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27429             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27430             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27431             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27432             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27433             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27434             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27435             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27436             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27437             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27438             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27439             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27440             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27441             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27442             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27443             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27444             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27445             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27446             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27447             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27448             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27449             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27450             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27451             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27452             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27453             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27454             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27455             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27456             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27457             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27458             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27459             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27460             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27461             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27462             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27463             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27464             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27465             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27466             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27467             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27468             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27469             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27470             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27471             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27472             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27473             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27474             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27475             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27476             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27477             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27478             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27479             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27480             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27481             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27482             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27483             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27484             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27485             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27486             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27487             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27488             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27489             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27490             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27491             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27492             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27493             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27494             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27495             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27496             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27497             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27498             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27499             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27500             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27501             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27502             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27503             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27504             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27505             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27506             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27507             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27508             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27509             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27510             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27511             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27512             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27513             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27514             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27515             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27516             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27517             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27518             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27519             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27520             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27521             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27522             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27523             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27524             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27525             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27526             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27527             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27528             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27529             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27530             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27531             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27532             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27533             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27534             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27535             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27536             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27537             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27538             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27539             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27540             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmGLC, 64 /* 6 */ },
   27541             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmSLC, 128 /* 7 */ },
   27542             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmTFE, 512 /* 9 */ },
   27543             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmUNorm, 32 /* 5 */ },
   27544             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDA, 2048 /* 11 */ },
   27545             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmR128A16, 256 /* 8 */ },
   27546             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmD16, 4096 /* 12 */ },
   27547             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmLWE, 1024 /* 10 */ },
   27548             :   { Feature_isGCN, 6577 /* image_sample */, MCK_ImmDMask, 16 /* 4 */ },
   27549             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27550             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27551             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27552             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27553             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27554             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27555             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27556             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27557             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27558             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27559             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27560             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27561             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27562             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27563             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27564             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27565             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27566             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27567             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27568             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27569             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27570             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27571             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27572             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27573             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27574             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27575             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27576             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27577             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27578             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27579             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27580             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27581             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27582             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27583             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27584             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27585             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27586             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27587             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27588             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27589             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27590             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27591             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27592             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27593             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27594             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27595             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27596             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27597             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27598             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27599             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27600             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27601             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27602             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27603             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27604             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27605             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27606             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27607             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27608             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27609             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27610             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27611             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27612             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27613             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27614             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27615             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27616             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27617             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27618             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27619             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27620             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27621             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27622             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27623             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27624             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27625             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27626             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27627             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27628             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27629             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27630             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27631             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27632             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27633             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27634             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27635             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27636             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27637             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27638             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27639             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27640             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27641             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27642             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27643             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27644             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27645             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27646             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27647             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27648             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmGLC, 64 /* 6 */ },
   27649             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmSLC, 128 /* 7 */ },
   27650             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmTFE, 512 /* 9 */ },
   27651             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmUNorm, 32 /* 5 */ },
   27652             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDA, 2048 /* 11 */ },
   27653             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmR128A16, 256 /* 8 */ },
   27654             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmD16, 4096 /* 12 */ },
   27655             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmLWE, 1024 /* 10 */ },
   27656             :   { Feature_isGCN, 6590 /* image_sample_b */, MCK_ImmDMask, 16 /* 4 */ },
   27657             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27658             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27659             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27660             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27661             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27662             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27663             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27664             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27665             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27666             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27667             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27668             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27669             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27670             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27671             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27672             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27673             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27674             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27675             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27676             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27677             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27678             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27679             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27680             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27681             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27682             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27683             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27684             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27685             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27686             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27687             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27688             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27689             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27690             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27691             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27692             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27693             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27694             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27695             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27696             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27697             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27698             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27699             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27700             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27701             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27702             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27703             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27704             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27705             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27706             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27707             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27708             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27709             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27710             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27711             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27712             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27713             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27714             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27715             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27716             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27717             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27718             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27719             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27720             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27721             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27722             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27723             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27724             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27725             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27726             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27727             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27728             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27729             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27730             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27731             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27732             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27733             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27734             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27735             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27736             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27737             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27738             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27739             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27740             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27741             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27742             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27743             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27744             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27745             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27746             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27747             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27748             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27749             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27750             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27751             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27752             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27753             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27754             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27755             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27756             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27757             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27758             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27759             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27760             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27761             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27762             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27763             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27764             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27765             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27766             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27767             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27768             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27769             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27770             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27771             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27772             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27773             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27774             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27775             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27776             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27777             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27778             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27779             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27780             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27781             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27782             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27783             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27784             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27785             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27786             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27787             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27788             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27789             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27790             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27791             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27792             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   27793             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   27794             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   27795             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   27796             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   27797             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   27798             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   27799             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   27800             :   { Feature_isGCN, 6605 /* image_sample_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   27801             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27802             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27803             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27804             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27805             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27806             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27807             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27808             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27809             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27810             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27811             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27812             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27813             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27814             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27815             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27816             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27817             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27818             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27819             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27820             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27821             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27822             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27823             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27824             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27825             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27826             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27827             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27828             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27829             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27830             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27831             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27832             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27833             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27834             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27835             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27836             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27837             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27838             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27839             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27840             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27841             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27842             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27843             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27844             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27845             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27846             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27847             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27848             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27849             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27850             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27851             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27852             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27853             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27854             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27855             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27856             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27857             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27858             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27859             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27860             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27861             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27862             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27863             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27864             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27865             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27866             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27867             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27868             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27869             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27870             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27871             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27872             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27873             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27874             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27875             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27876             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27877             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27878             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27879             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27880             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27881             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27882             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27883             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27884             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27885             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27886             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27887             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27888             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27889             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27890             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27891             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27892             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27893             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27894             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27895             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27896             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27897             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27898             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27899             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27900             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   27901             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   27902             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   27903             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27904             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   27905             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27906             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   27907             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27908             :   { Feature_isGCN, 6623 /* image_sample_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   27909             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27910             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27911             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27912             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27913             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27914             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27915             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27916             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27917             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27918             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27919             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27920             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27921             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27922             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27923             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27924             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27925             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27926             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27927             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27928             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27929             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27930             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27931             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27932             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27933             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27934             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27935             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27936             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27937             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27938             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27939             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27940             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27941             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27942             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27943             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27944             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27945             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27946             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27947             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27948             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27949             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27950             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27951             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27952             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27953             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27954             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27955             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27956             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27957             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27958             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27959             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27960             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27961             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27962             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27963             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27964             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27965             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27966             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27967             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27968             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27969             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27970             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27971             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27972             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27973             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27974             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27975             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27976             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27977             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27978             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27979             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27980             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27981             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27982             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27983             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27984             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27985             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27986             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27987             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27988             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27989             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27990             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   27991             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   27992             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   27993             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   27994             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   27995             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   27996             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   27997             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   27998             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   27999             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28000             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28001             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28002             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28003             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28004             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28005             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28006             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28007             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28008             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28009             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28010             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28011             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28012             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28013             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28014             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28015             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28016             :   { Feature_isGCN, 6643 /* image_sample_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28017             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28018             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28019             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28020             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28021             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28022             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28023             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28024             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28025             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28026             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28027             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28028             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28029             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28030             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28031             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28032             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28033             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28034             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28035             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28036             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28037             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28038             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28039             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28040             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28041             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28042             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28043             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28044             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28045             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28046             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28047             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28048             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28049             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28050             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28051             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28052             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28053             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28054             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28055             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28056             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28057             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28058             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28059             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28060             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28061             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28062             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28063             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28064             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28065             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28066             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28067             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28068             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28069             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28070             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28071             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28072             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28073             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28074             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28075             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28076             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28077             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28078             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28079             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28080             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28081             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28082             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28083             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28084             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28085             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28086             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28087             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28088             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28089             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28090             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28091             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28092             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28093             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28094             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28095             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28096             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28097             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28098             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28099             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28100             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28101             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28102             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28103             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28104             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28105             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28106             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28107             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28108             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28109             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28110             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28111             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28112             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28113             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28114             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28115             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28116             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmGLC, 64 /* 6 */ },
   28117             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmSLC, 128 /* 7 */ },
   28118             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmTFE, 512 /* 9 */ },
   28119             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmUNorm, 32 /* 5 */ },
   28120             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDA, 2048 /* 11 */ },
   28121             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmR128A16, 256 /* 8 */ },
   28122             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmD16, 4096 /* 12 */ },
   28123             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmLWE, 1024 /* 10 */ },
   28124             :   { Feature_isGCN, 6660 /* image_sample_c */, MCK_ImmDMask, 16 /* 4 */ },
   28125             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28126             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28127             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28128             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28129             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28130             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28131             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28132             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28133             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28134             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28135             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28136             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28137             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28138             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28139             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28140             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28141             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28142             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28143             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28144             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28145             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28146             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28147             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28148             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28149             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28150             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28151             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28152             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28153             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28154             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28155             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28156             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28157             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28158             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28159             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28160             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28161             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28162             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28163             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28164             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28165             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28166             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28167             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28168             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28169             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28170             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28171             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28172             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28173             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28174             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28175             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28176             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28177             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28178             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28179             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28180             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28181             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28182             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28183             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28184             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28185             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28186             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28187             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28188             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28189             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28190             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28191             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28192             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28193             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28194             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28195             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28196             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28197             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28198             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28199             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28200             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28201             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28202             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28203             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28204             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28205             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28206             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28207             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28208             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28209             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28210             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28211             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28212             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28213             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28214             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28215             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28216             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28217             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28218             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28219             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28220             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28221             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28222             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28223             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28224             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmGLC, 64 /* 6 */ },
   28225             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmSLC, 128 /* 7 */ },
   28226             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmTFE, 512 /* 9 */ },
   28227             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmUNorm, 32 /* 5 */ },
   28228             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDA, 2048 /* 11 */ },
   28229             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmR128A16, 256 /* 8 */ },
   28230             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmD16, 4096 /* 12 */ },
   28231             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmLWE, 1024 /* 10 */ },
   28232             :   { Feature_isGCN, 6675 /* image_sample_c_b */, MCK_ImmDMask, 16 /* 4 */ },
   28233             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28234             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28235             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28236             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28237             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28238             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28239             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28240             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28241             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28242             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28243             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28244             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28245             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28246             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28247             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28248             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28249             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28250             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28251             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28252             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28253             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28254             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28255             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28256             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28257             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28258             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28259             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28260             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28261             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28262             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28263             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28264             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28265             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28266             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28267             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28268             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28269             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28270             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28271             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28272             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28273             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28274             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28275             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28276             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28277             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28278             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28279             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28280             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28281             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28282             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28283             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28284             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28285             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28286             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28287             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28288             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28289             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28290             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28291             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28292             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28293             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28294             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28295             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28296             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28297             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28298             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28299             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28300             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28301             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28302             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28303             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28304             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28305             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28306             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28307             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28308             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28309             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28310             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28311             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28312             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28313             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28314             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28315             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28316             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28317             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28318             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28319             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28320             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28321             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28322             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28323             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28324             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28325             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28326             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28327             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28328             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28329             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28330             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28331             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28332             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28333             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28334             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28335             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28336             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28337             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28338             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28339             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28340             :   { Feature_isGCN, 6692 /* image_sample_c_b_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28341             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28342             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28343             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28344             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28345             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28346             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28347             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28348             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28349             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28350             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28351             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28352             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28353             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28354             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28355             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28356             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28357             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28358             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28359             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28360             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28361             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28362             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28363             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28364             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28365             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28366             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28367             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28368             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28369             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28370             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28371             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28372             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28373             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28374             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28375             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28376             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28377             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28378             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28379             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28380             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28381             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28382             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28383             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28384             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28385             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28386             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28387             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28388             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28389             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28390             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28391             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28392             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28393             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28394             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28395             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28396             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28397             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28398             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28399             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28400             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28401             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28402             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28403             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28404             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28405             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28406             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28407             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28408             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28409             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28410             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28411             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28412             :   { Feature_isGCN, 6712 /* image_sample_c_b_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28413             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28414             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28415             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28416             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28417             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28418             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28419             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28420             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28421             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28422             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28423             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28424             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28425             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28426             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28427             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28428             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28429             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28430             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28431             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28432             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28433             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28434             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28435             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28436             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28437             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28438             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28439             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28440             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28441             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28442             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28443             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28444             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28445             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28446             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28447             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28448             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28449             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28450             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28451             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28452             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28453             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28454             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28455             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28456             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28457             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28458             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28459             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28460             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28461             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28462             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28463             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28464             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28465             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28466             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28467             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28468             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28469             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28470             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28471             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28472             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28473             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28474             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28475             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28476             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmGLC, 64 /* 6 */ },
   28477             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmSLC, 128 /* 7 */ },
   28478             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmTFE, 512 /* 9 */ },
   28479             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28480             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDA, 2048 /* 11 */ },
   28481             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28482             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmD16, 4096 /* 12 */ },
   28483             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28484             :   { Feature_isGCN, 6734 /* image_sample_c_b_o */, MCK_ImmDMask, 16 /* 4 */ },
   28485             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28486             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28487             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28488             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28489             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28490             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28491             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28492             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28493             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28494             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28495             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28496             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28497             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28498             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28499             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28500             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28501             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28502             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28503             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28504             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28505             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28506             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28507             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28508             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28509             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28510             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28511             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28512             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28513             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28514             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28515             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28516             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28517             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28518             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28519             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28520             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28521             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28522             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28523             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28524             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28525             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28526             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28527             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28528             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28529             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28530             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28531             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28532             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28533             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28534             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28535             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28536             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28537             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28538             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28539             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28540             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28541             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28542             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28543             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28544             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28545             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28546             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28547             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28548             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28549             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28550             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28551             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28552             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28553             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28554             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28555             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28556             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28557             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28558             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28559             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28560             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28561             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28562             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28563             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28564             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28565             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28566             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28567             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28568             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28569             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28570             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28571             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28572             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28573             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28574             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28575             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28576             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28577             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28578             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28579             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28580             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28581             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28582             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28583             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28584             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28585             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28586             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28587             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28588             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28589             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28590             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28591             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28592             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28593             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28594             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28595             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28596             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28597             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28598             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28599             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28600             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28601             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28602             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28603             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28604             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28605             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28606             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28607             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28608             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28609             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28610             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28611             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28612             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28613             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28614             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28615             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28616             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28617             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28618             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28619             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28620             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmGLC, 64 /* 6 */ },
   28621             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmSLC, 128 /* 7 */ },
   28622             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmTFE, 512 /* 9 */ },
   28623             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   28624             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDA, 2048 /* 11 */ },
   28625             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   28626             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmD16, 4096 /* 12 */ },
   28627             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   28628             :   { Feature_isGCN, 6753 /* image_sample_c_cd */, MCK_ImmDMask, 16 /* 4 */ },
   28629             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28630             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28631             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28632             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28633             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28634             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28635             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28636             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28637             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28638             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28639             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28640             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28641             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28642             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28643             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28644             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28645             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28646             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28647             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28648             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28649             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28650             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28651             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28652             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28653             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28654             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28655             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28656             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28657             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28658             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28659             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28660             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28661             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28662             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28663             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28664             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28665             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28666             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28667             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28668             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28669             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28670             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28671             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28672             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28673             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28674             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28675             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28676             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28677             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28678             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28679             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28680             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28681             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28682             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28683             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28684             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28685             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28686             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28687             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28688             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28689             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28690             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28691             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28692             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28693             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28694             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28695             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28696             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28697             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28698             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28699             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28700             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28701             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28702             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28703             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28704             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28705             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28706             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28707             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28708             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28709             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28710             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28711             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28712             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28713             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28714             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28715             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28716             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28717             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28718             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28719             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28720             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28721             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28722             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28723             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28724             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28725             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28726             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28727             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28728             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28729             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28730             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28731             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28732             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28733             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28734             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28735             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28736             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28737             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28738             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28739             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28740             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28741             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28742             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28743             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28744             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28745             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28746             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28747             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28748             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28749             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28750             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28751             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28752             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28753             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28754             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28755             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28756             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28757             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28758             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28759             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28760             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28761             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28762             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28763             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28764             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28765             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28766             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28767             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28768             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28769             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28770             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28771             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28772             :   { Feature_isGCN, 6771 /* image_sample_c_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28773             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28774             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28775             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28776             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28777             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28778             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28779             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28780             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28781             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28782             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28783             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28784             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28785             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28786             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28787             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28788             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28789             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28790             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28791             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28792             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28793             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28794             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28795             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28796             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28797             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28798             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28799             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28800             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28801             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28802             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28803             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28804             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28805             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28806             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28807             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28808             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28809             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28810             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28811             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28812             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28813             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28814             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28815             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28816             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28817             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28818             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28819             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28820             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28821             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28822             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28823             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28824             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28825             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28826             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28827             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28828             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28829             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28830             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28831             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28832             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28833             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28834             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28835             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28836             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28837             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28838             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28839             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28840             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28841             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28842             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28843             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28844             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28845             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28846             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28847             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28848             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28849             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28850             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28851             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28852             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28853             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28854             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28855             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28856             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28857             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28858             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28859             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28860             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28861             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28862             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28863             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28864             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28865             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28866             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28867             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28868             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28869             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28870             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28871             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28872             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   28873             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   28874             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   28875             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28876             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   28877             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28878             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   28879             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28880             :   { Feature_isGCN, 6792 /* image_sample_c_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   28881             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28882             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28883             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28884             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28885             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28886             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28887             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28888             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28889             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28890             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28891             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28892             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28893             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28894             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28895             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28896             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28897             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28898             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28899             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28900             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28901             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28902             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28903             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28904             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28905             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28906             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28907             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28908             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28909             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28910             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28911             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28912             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28913             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28914             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28915             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28916             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28917             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28918             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28919             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28920             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28921             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28922             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28923             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28924             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28925             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28926             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28927             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28928             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28929             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28930             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28931             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28932             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28933             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28934             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28935             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28936             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28937             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28938             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28939             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28940             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28941             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28942             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28943             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28944             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28945             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28946             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28947             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28948             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28949             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28950             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28951             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28952             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28953             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28954             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28955             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28956             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28957             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28958             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28959             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28960             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28961             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28962             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28963             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28964             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28965             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28966             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28967             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28968             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28969             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28970             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28971             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28972             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28973             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28974             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28975             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28976             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28977             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28978             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28979             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28980             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   28981             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   28982             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   28983             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   28984             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   28985             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   28986             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   28987             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   28988             :   { Feature_isGCN, 6815 /* image_sample_c_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   28989             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28990             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   28991             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   28992             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   28993             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   28994             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   28995             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   28996             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   28997             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   28998             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   28999             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29000             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29001             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29002             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29003             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29004             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29005             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29006             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29007             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29008             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29009             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29010             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29011             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29012             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29013             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29014             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29015             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29016             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29017             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29018             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29019             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29020             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29021             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29022             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29023             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29024             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29025             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29026             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29027             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29028             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29029             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29030             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29031             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29032             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29033             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29034             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29035             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29036             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29037             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29038             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29039             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29040             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29041             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29042             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29043             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29044             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29045             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29046             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29047             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29048             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29049             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29050             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29051             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29052             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29053             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29054             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29055             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29056             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29057             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29058             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29059             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29060             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29061             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29062             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29063             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29064             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29065             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29066             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29067             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29068             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29069             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29070             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29071             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29072             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29073             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29074             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29075             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29076             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29077             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29078             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29079             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29080             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29081             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29082             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29083             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29084             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29085             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29086             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29087             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29088             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29089             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29090             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29091             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29092             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29093             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29094             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29095             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29096             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29097             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29098             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29099             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29100             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29101             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29102             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29103             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29104             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29105             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29106             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29107             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29108             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29109             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29110             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29111             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29112             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29113             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29114             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29115             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29116             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29117             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29118             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29119             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29120             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29121             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29122             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29123             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29124             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29125             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29126             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29127             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29128             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29129             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29130             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29131             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29132             :   { Feature_isGCN, 6835 /* image_sample_c_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29133             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29134             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29135             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29136             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29137             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29138             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29139             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29140             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29141             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29142             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29143             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29144             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29145             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29146             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29147             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29148             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29149             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29150             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29151             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29152             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29153             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29154             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29155             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29156             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29157             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29158             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29159             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29160             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29161             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29162             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29163             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29164             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29165             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29166             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29167             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29168             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29169             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29170             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29171             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29172             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29173             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29174             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29175             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29176             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29177             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29178             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29179             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29180             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29181             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29182             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29183             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29184             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29185             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29186             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29187             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29188             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29189             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29190             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29191             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29192             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29193             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29194             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29195             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29196             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29197             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29198             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29199             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29200             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29201             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29202             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29203             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29204             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29205             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29206             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29207             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29208             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29209             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29210             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29211             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29212             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29213             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29214             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29215             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29216             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29217             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29218             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29219             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29220             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29221             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29222             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29223             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29224             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29225             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29226             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29227             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29228             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29229             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29230             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29231             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29232             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29233             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29234             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29235             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29236             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29237             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29238             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29239             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29240             :   { Feature_isGCN, 6853 /* image_sample_c_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29241             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29242             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29243             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29244             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29245             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29246             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29247             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29248             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29249             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29250             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29251             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29252             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29253             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29254             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29255             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29256             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29257             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29258             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29259             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29260             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29261             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29262             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29263             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29264             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29265             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29266             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29267             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29268             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29269             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29270             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29271             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29272             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29273             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29274             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29275             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29276             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29277             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29278             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29279             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29280             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29281             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29282             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29283             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29284             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29285             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29286             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29287             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29288             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29289             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29290             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29291             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29292             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29293             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29294             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29295             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29296             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29297             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29298             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29299             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29300             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29301             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29302             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29303             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29304             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29305             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29306             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29307             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29308             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29309             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29310             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29311             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29312             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29313             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29314             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29315             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29316             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29317             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29318             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29319             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29320             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29321             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29322             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29323             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29324             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29325             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29326             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29327             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29328             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29329             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29330             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29331             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29332             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29333             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29334             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29335             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29336             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29337             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29338             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29339             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29340             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29341             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29342             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29343             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29344             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29345             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29346             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29347             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29348             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29349             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29350             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29351             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29352             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29353             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29354             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29355             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29356             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29357             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29358             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29359             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29360             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29361             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29362             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29363             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29364             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29365             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29366             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29367             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29368             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29369             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29370             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29371             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29372             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29373             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29374             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29375             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29376             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmGLC, 64 /* 6 */ },
   29377             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmSLC, 128 /* 7 */ },
   29378             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmTFE, 512 /* 9 */ },
   29379             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmUNorm, 32 /* 5 */ },
   29380             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDA, 2048 /* 11 */ },
   29381             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmR128A16, 256 /* 8 */ },
   29382             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmD16, 4096 /* 12 */ },
   29383             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmLWE, 1024 /* 10 */ },
   29384             :   { Feature_isGCN, 6873 /* image_sample_c_d */, MCK_ImmDMask, 16 /* 4 */ },
   29385             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29386             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29387             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29388             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29389             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29390             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29391             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29392             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29393             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29394             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29395             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29396             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29397             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29398             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29399             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29400             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29401             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29402             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29403             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29404             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29405             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29406             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29407             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29408             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29409             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29410             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29411             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29412             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29413             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29414             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29415             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29416             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29417             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29418             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29419             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29420             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29421             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29422             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29423             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29424             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29425             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29426             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29427             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29428             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29429             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29430             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29431             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29432             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29433             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29434             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29435             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29436             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29437             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29438             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29439             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29440             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29441             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29442             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29443             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29444             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29445             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29446             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29447             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29448             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29449             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29450             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29451             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29452             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29453             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29454             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29455             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29456             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29457             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29458             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29459             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29460             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29461             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29462             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29463             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29464             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29465             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29466             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29467             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29468             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29469             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29470             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29471             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29472             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29473             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29474             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29475             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29476             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29477             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29478             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29479             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29480             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29481             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29482             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29483             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29484             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29485             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29486             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29487             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29488             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29489             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29490             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29491             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29492             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29493             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29494             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29495             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29496             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29497             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29498             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29499             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29500             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29501             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29502             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29503             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29504             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29505             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29506             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29507             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29508             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29509             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29510             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29511             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29512             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29513             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29514             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29515             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29516             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29517             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29518             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29519             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29520             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   29521             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   29522             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   29523             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   29524             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   29525             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   29526             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   29527             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   29528             :   { Feature_isGCN, 6890 /* image_sample_c_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   29529             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29530             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29531             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29532             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29533             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29534             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29535             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29536             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29537             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29538             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29539             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29540             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29541             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29542             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29543             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29544             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29545             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29546             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29547             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29548             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29549             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29550             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29551             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29552             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29553             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29554             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29555             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29556             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29557             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29558             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29559             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29560             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29561             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29562             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29563             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29564             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29565             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29566             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29567             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29568             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29569             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29570             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29571             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29572             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29573             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29574             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29575             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29576             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29577             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29578             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29579             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29580             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29581             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29582             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29583             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29584             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29585             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29586             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29587             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29588             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29589             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29590             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29591             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29592             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29593             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29594             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29595             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29596             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29597             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29598             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29599             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29600             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29601             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29602             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29603             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29604             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29605             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29606             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29607             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29608             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29609             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29610             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29611             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29612             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29613             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29614             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29615             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29616             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29617             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29618             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29619             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29620             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29621             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29622             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29623             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29624             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29625             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29626             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29627             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29628             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   29629             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   29630             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   29631             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29632             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   29633             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29634             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   29635             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29636             :   { Feature_isGCN, 6910 /* image_sample_c_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   29637             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29638             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29639             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29640             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29641             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29642             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29643             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29644             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29645             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29646             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29647             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29648             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29649             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29650             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29651             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29652             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29653             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29654             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29655             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29656             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29657             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29658             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29659             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29660             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29661             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29662             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29663             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29664             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29665             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29666             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29667             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29668             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29669             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29670             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29671             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29672             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29673             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29674             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29675             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29676             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29677             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29678             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29679             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29680             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29681             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29682             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29683             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29684             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29685             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29686             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29687             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29688             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29689             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29690             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29691             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29692             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29693             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29694             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29695             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29696             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29697             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29698             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29699             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29700             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29701             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29702             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29703             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29704             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29705             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29706             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29707             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29708             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29709             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29710             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29711             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29712             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29713             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29714             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29715             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29716             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29717             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29718             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29719             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29720             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29721             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29722             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29723             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29724             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29725             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29726             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29727             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29728             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29729             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29730             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29731             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29732             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29733             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29734             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29735             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29736             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   29737             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   29738             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   29739             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29740             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   29741             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29742             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   29743             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29744             :   { Feature_isGCN, 6932 /* image_sample_c_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   29745             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29746             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29747             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29748             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29749             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29750             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29751             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29752             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29753             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29754             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29755             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29756             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29757             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29758             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29759             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29760             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29761             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29762             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29763             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29764             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29765             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29766             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29767             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29768             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29769             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29770             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29771             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29772             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29773             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29774             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29775             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29776             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29777             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29778             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29779             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29780             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29781             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29782             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29783             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29784             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29785             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29786             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29787             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29788             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29789             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29790             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29791             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29792             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29793             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29794             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29795             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29796             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29797             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29798             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29799             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29800             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29801             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29802             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29803             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29804             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29805             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29806             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29807             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29808             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29809             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29810             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29811             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29812             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29813             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29814             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29815             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29816             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29817             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29818             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29819             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29820             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29821             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29822             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29823             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29824             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29825             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29826             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29827             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29828             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29829             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29830             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29831             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29832             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29833             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29834             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29835             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29836             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29837             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29838             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29839             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29840             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29841             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29842             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29843             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29844             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29845             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29846             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29847             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29848             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29849             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29850             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29851             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29852             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29853             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29854             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29855             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29856             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29857             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29858             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29859             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29860             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29861             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29862             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29863             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29864             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29865             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29866             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29867             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29868             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29869             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29870             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29871             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29872             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29873             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29874             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29875             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29876             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29877             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29878             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29879             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29880             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmGLC, 64 /* 6 */ },
   29881             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmSLC, 128 /* 7 */ },
   29882             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmTFE, 512 /* 9 */ },
   29883             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmUNorm, 32 /* 5 */ },
   29884             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDA, 2048 /* 11 */ },
   29885             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmR128A16, 256 /* 8 */ },
   29886             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmD16, 4096 /* 12 */ },
   29887             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmLWE, 1024 /* 10 */ },
   29888             :   { Feature_isGCN, 6951 /* image_sample_c_l */, MCK_ImmDMask, 16 /* 4 */ },
   29889             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29890             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29891             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29892             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29893             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29894             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29895             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29896             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29897             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29898             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29899             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29900             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29901             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29902             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29903             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29904             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29905             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29906             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29907             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29908             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29909             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29910             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29911             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29912             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29913             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29914             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29915             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29916             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29917             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29918             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29919             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29920             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29921             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29922             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29923             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29924             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29925             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29926             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29927             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29928             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29929             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29930             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29931             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29932             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29933             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29934             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29935             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29936             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29937             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29938             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29939             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29940             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29941             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29942             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29943             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29944             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29945             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29946             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29947             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29948             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29949             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29950             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29951             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29952             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29953             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29954             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29955             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29956             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29957             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29958             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29959             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29960             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29961             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29962             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29963             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29964             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29965             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29966             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29967             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29968             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29969             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29970             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29971             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29972             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29973             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29974             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29975             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29976             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29977             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29978             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29979             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29980             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29981             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29982             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29983             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29984             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29985             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29986             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29987             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29988             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   29989             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   29990             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   29991             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   29992             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   29993             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   29994             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   29995             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   29996             :   { Feature_isGCN, 6968 /* image_sample_c_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   29997             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   29998             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   29999             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30000             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30001             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30002             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30003             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30004             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30005             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30006             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30007             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30008             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30009             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30010             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30011             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30012             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30013             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30014             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30015             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30016             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30017             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30018             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30019             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30020             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30021             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30022             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30023             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30024             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30025             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30026             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30027             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30028             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30029             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30030             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30031             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30032             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30033             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30034             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30035             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30036             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30037             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30038             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30039             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30040             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30041             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30042             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30043             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30044             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30045             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30046             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30047             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30048             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30049             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30050             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30051             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30052             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30053             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30054             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30055             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30056             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30057             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30058             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30059             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30060             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30061             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30062             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30063             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30064             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30065             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30066             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30067             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30068             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30069             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30070             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30071             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30072             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30073             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30074             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30075             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30076             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30077             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30078             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30079             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30080             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30081             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30082             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30083             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30084             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30085             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30086             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30087             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30088             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30089             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30090             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30091             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30092             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30093             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30094             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30095             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30096             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmGLC, 64 /* 6 */ },
   30097             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmSLC, 128 /* 7 */ },
   30098             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmTFE, 512 /* 9 */ },
   30099             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   30100             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDA, 2048 /* 11 */ },
   30101             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   30102             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmD16, 4096 /* 12 */ },
   30103             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   30104             :   { Feature_isGCN, 6987 /* image_sample_c_lz */, MCK_ImmDMask, 16 /* 4 */ },
   30105             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30106             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30107             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30108             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30109             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30110             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30111             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30112             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30113             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30114             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30115             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30116             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30117             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30118             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30119             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30120             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30121             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30122             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30123             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30124             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30125             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30126             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30127             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30128             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30129             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30130             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30131             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30132             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30133             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30134             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30135             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30136             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30137             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30138             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30139             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30140             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30141             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30142             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30143             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30144             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30145             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30146             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30147             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30148             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30149             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30150             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30151             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30152             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30153             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30154             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30155             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30156             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30157             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30158             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30159             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30160             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30161             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30162             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30163             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30164             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30165             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30166             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30167             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30168             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30169             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30170             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30171             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30172             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30173             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30174             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30175             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30176             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30177             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30178             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30179             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30180             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30181             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30182             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30183             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30184             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30185             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30186             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30187             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30188             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30189             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30190             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30191             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30192             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30193             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30194             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30195             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30196             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30197             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30198             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30199             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30200             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30201             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30202             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30203             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30204             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   30205             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   30206             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   30207             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30208             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   30209             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30210             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   30211             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30212             :   { Feature_isGCN, 7005 /* image_sample_c_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   30213             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30214             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30215             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30216             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30217             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30218             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30219             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30220             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30221             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30222             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30223             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30224             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30225             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30226             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30227             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30228             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30229             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30230             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30231             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30232             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30233             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30234             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30235             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30236             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30237             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30238             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30239             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30240             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30241             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30242             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30243             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30244             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30245             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30246             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30247             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30248             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30249             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30250             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30251             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30252             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30253             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30254             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30255             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30256             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30257             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30258             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30259             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30260             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30261             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30262             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30263             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30264             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30265             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30266             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30267             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30268             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30269             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30270             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30271             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30272             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30273             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30274             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30275             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30276             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30277             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30278             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30279             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30280             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30281             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30282             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30283             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30284             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30285             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30286             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30287             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30288             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30289             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30290             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30291             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30292             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30293             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30294             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30295             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30296             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30297             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30298             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30299             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30300             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30301             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30302             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30303             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30304             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30305             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30306             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30307             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30308             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30309             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30310             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30311             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30312             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmGLC, 64 /* 6 */ },
   30313             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmSLC, 128 /* 7 */ },
   30314             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmTFE, 512 /* 9 */ },
   30315             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30316             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDA, 2048 /* 11 */ },
   30317             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30318             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmD16, 4096 /* 12 */ },
   30319             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30320             :   { Feature_isGCN, 7025 /* image_sample_c_o */, MCK_ImmDMask, 16 /* 4 */ },
   30321             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30322             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30323             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30324             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30325             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30326             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30327             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30328             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30329             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30330             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30331             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30332             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30333             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30334             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30335             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30336             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30337             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30338             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30339             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30340             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30341             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30342             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30343             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30344             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30345             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30346             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30347             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30348             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30349             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30350             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30351             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30352             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30353             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30354             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30355             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30356             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30357             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30358             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30359             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30360             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30361             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30362             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30363             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30364             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30365             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30366             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30367             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30368             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30369             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30370             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30371             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30372             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30373             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30374             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30375             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30376             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30377             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30378             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30379             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30380             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30381             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30382             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30383             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30384             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30385             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30386             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30387             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30388             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30389             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30390             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30391             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30392             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30393             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30394             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30395             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30396             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30397             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30398             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30399             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30400             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30401             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30402             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30403             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30404             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30405             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30406             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30407             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30408             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30409             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30410             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30411             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30412             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30413             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30414             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30415             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30416             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30417             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30418             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30419             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30420             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30421             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30422             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30423             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30424             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30425             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30426             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30427             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30428             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30429             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30430             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30431             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30432             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30433             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30434             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30435             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30436             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30437             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30438             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30439             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30440             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30441             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30442             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30443             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30444             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30445             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30446             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30447             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30448             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30449             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30450             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30451             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30452             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30453             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30454             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30455             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30456             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30457             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30458             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30459             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30460             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30461             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30462             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30463             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30464             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30465             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30466             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30467             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30468             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30469             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30470             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30471             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30472             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30473             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30474             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30475             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30476             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30477             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30478             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30479             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30480             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30481             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30482             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30483             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30484             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30485             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30486             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30487             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30488             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30489             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30490             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30491             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30492             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmGLC, 64 /* 6 */ },
   30493             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmSLC, 128 /* 7 */ },
   30494             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmTFE, 512 /* 9 */ },
   30495             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmUNorm, 32 /* 5 */ },
   30496             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDA, 2048 /* 11 */ },
   30497             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmR128A16, 256 /* 8 */ },
   30498             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmD16, 4096 /* 12 */ },
   30499             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmLWE, 1024 /* 10 */ },
   30500             :   { Feature_isGCN, 7042 /* image_sample_cd */, MCK_ImmDMask, 16 /* 4 */ },
   30501             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30502             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30503             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30504             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30505             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30506             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30507             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30508             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30509             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30510             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30511             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30512             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30513             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30514             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30515             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30516             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30517             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30518             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30519             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30520             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30521             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30522             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30523             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30524             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30525             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30526             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30527             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30528             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30529             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30530             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30531             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30532             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30533             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30534             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30535             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30536             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30537             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30538             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30539             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30540             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30541             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30542             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30543             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30544             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30545             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30546             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30547             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30548             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30549             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30550             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30551             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30552             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30553             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30554             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30555             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30556             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30557             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30558             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30559             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30560             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30561             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30562             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30563             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30564             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30565             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30566             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30567             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30568             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30569             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30570             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30571             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30572             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30573             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30574             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30575             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30576             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30577             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30578             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30579             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30580             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30581             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30582             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30583             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30584             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30585             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30586             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30587             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30588             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30589             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30590             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30591             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30592             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30593             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30594             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30595             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30596             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30597             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30598             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30599             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30600             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30601             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30602             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30603             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30604             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30605             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30606             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30607             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30608             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30609             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30610             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30611             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30612             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30613             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30614             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30615             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30616             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30617             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30618             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30619             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30620             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30621             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30622             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30623             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30624             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30625             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30626             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30627             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30628             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30629             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30630             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30631             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30632             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30633             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30634             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30635             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30636             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30637             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30638             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30639             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30640             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30641             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30642             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30643             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30644             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30645             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30646             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30647             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30648             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30649             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30650             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30651             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30652             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30653             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30654             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30655             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30656             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30657             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30658             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30659             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30660             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30661             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30662             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30663             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30664             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30665             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30666             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30667             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30668             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30669             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30670             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30671             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30672             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30673             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30674             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30675             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30676             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30677             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30678             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30679             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30680             :   { Feature_isGCN, 7058 /* image_sample_cd_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30681             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30682             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30683             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30684             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30685             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30686             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30687             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30688             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30689             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30690             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30691             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30692             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30693             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30694             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30695             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30696             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30697             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30698             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30699             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30700             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30701             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30702             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30703             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30704             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30705             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30706             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30707             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30708             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30709             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30710             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30711             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30712             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30713             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30714             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30715             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30716             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30717             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30718             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30719             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30720             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30721             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30722             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30723             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30724             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30725             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30726             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30727             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30728             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30729             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30730             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30731             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30732             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30733             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30734             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30735             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30736             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30737             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30738             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30739             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30740             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30741             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30742             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30743             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30744             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30745             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30746             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30747             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30748             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30749             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30750             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30751             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30752             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30753             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30754             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30755             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30756             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30757             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30758             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30759             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30760             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30761             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30762             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30763             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30764             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30765             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30766             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30767             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30768             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30769             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30770             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30771             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30772             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30773             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30774             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30775             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30776             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30777             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30778             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30779             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30780             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30781             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30782             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30783             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30784             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30785             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30786             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30787             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30788             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30789             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30790             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30791             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30792             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30793             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30794             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30795             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30796             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30797             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30798             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30799             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30800             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30801             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30802             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30803             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30804             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30805             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30806             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30807             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30808             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30809             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30810             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30811             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30812             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30813             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30814             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30815             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30816             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   30817             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   30818             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   30819             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30820             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   30821             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30822             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   30823             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30824             :   { Feature_isGCN, 7077 /* image_sample_cd_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   30825             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30826             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30827             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30828             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30829             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30830             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30831             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30832             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30833             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30834             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30835             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30836             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30837             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30838             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30839             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30840             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30841             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30842             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30843             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30844             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30845             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30846             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30847             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30848             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30849             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30850             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30851             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30852             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30853             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30854             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30855             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30856             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30857             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30858             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30859             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30860             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30861             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30862             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30863             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30864             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30865             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30866             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30867             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30868             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30869             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30870             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30871             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30872             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30873             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30874             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30875             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30876             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30877             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30878             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30879             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30880             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30881             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30882             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30883             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30884             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30885             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30886             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30887             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30888             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30889             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30890             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30891             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30892             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30893             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30894             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30895             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30896             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30897             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30898             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30899             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30900             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30901             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30902             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30903             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30904             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30905             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30906             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30907             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30908             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30909             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30910             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30911             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30912             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30913             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30914             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30915             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30916             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30917             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30918             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30919             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30920             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30921             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30922             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30923             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30924             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30925             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30926             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30927             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30928             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30929             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30930             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30931             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30932             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30933             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30934             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30935             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30936             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30937             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30938             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30939             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30940             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30941             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30942             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30943             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30944             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30945             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30946             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30947             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30948             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30949             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30950             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30951             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30952             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30953             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30954             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30955             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30956             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30957             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30958             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30959             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30960             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmGLC, 64 /* 6 */ },
   30961             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmSLC, 128 /* 7 */ },
   30962             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmTFE, 512 /* 9 */ },
   30963             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmUNorm, 32 /* 5 */ },
   30964             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDA, 2048 /* 11 */ },
   30965             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmR128A16, 256 /* 8 */ },
   30966             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmD16, 4096 /* 12 */ },
   30967             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmLWE, 1024 /* 10 */ },
   30968             :   { Feature_isGCN, 7098 /* image_sample_cd_o */, MCK_ImmDMask, 16 /* 4 */ },
   30969             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30970             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30971             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30972             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30973             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30974             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30975             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30976             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30977             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30978             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30979             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30980             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30981             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30982             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30983             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30984             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30985             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30986             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30987             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30988             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30989             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30990             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   30991             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   30992             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   30993             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   30994             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   30995             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   30996             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   30997             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   30998             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   30999             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31000             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31001             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31002             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31003             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31004             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31005             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31006             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31007             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31008             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31009             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31010             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31011             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31012             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31013             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31014             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31015             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31016             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31017             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31018             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31019             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31020             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31021             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31022             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31023             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31024             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31025             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31026             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31027             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31028             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31029             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31030             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31031             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31032             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31033             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31034             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31035             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31036             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31037             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31038             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31039             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31040             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31041             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31042             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31043             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31044             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31045             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31046             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31047             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31048             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31049             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31050             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31051             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31052             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31053             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31054             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31055             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31056             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31057             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31058             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31059             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31060             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31061             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31062             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31063             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31064             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31065             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31066             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31067             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31068             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31069             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31070             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31071             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31072             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31073             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31074             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31075             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31076             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31077             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31078             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31079             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31080             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31081             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31082             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31083             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31084             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31085             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31086             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31087             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31088             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31089             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31090             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31091             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31092             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31093             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31094             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31095             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31096             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31097             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31098             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31099             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31100             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31101             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31102             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31103             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31104             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31105             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31106             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31107             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31108             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31109             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31110             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31111             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31112             :   { Feature_isGCN, 7116 /* image_sample_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31113             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31114             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31115             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31116             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31117             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31118             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31119             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31120             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31121             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31122             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31123             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31124             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31125             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31126             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31127             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31128             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31129             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31130             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31131             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31132             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31133             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31134             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31135             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31136             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31137             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31138             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31139             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31140             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31141             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31142             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31143             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31144             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31145             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31146             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31147             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31148             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31149             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31150             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31151             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31152             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31153             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31154             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31155             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31156             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31157             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31158             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31159             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31160             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31161             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31162             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31163             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31164             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31165             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31166             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31167             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31168             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31169             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31170             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31171             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31172             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31173             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31174             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31175             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31176             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31177             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31178             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31179             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31180             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31181             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31182             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31183             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31184             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31185             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31186             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31187             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31188             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31189             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31190             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31191             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31192             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31193             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31194             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31195             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31196             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31197             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31198             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31199             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31200             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31201             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31202             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31203             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31204             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31205             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31206             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31207             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31208             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31209             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31210             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31211             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31212             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31213             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31214             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31215             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31216             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31217             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31218             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31219             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31220             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31221             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31222             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31223             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31224             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31225             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31226             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31227             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31228             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31229             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31230             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31231             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31232             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31233             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31234             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31235             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31236             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31237             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31238             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31239             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31240             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31241             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31242             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31243             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31244             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31245             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31246             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31247             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31248             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31249             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31250             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31251             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31252             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31253             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31254             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31255             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31256             :   { Feature_isGCN, 7132 /* image_sample_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31257             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31258             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31259             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31260             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31261             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31262             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31263             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31264             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31265             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31266             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31267             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31268             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31269             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31270             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31271             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31272             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31273             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31274             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31275             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31276             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31277             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31278             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31279             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31280             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31281             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31282             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31283             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31284             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31285             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31286             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31287             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31288             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31289             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31290             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31291             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31292             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31293             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31294             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31295             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31296             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31297             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31298             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31299             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31300             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31301             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31302             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31303             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31304             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31305             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31306             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31307             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31308             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31309             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31310             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31311             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31312             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31313             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31314             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31315             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31316             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31317             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31318             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31319             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31320             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31321             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31322             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31323             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31324             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31325             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31326             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31327             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31328             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31329             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31330             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31331             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31332             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31333             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31334             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31335             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31336             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31337             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31338             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31339             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31340             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31341             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31342             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31343             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31344             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31345             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31346             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31347             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31348             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31349             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31350             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31351             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31352             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31353             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31354             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31355             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31356             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31357             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31358             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31359             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31360             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31361             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31362             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31363             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31364             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31365             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31366             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31367             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31368             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31369             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31370             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31371             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31372             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31373             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31374             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31375             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31376             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31377             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31378             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31379             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31380             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31381             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31382             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31383             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31384             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31385             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31386             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31387             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31388             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31389             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31390             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31391             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31392             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31393             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31394             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31395             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31396             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31397             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31398             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31399             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31400             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31401             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31402             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31403             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31404             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31405             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31406             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31407             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31408             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31409             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31410             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31411             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31412             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31413             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31414             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31415             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31416             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31417             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31418             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31419             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31420             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31421             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31422             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31423             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31424             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31425             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31426             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31427             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31428             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmGLC, 64 /* 6 */ },
   31429             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmSLC, 128 /* 7 */ },
   31430             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmTFE, 512 /* 9 */ },
   31431             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmUNorm, 32 /* 5 */ },
   31432             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDA, 2048 /* 11 */ },
   31433             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmR128A16, 256 /* 8 */ },
   31434             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmD16, 4096 /* 12 */ },
   31435             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmLWE, 1024 /* 10 */ },
   31436             :   { Feature_isGCN, 7150 /* image_sample_d */, MCK_ImmDMask, 16 /* 4 */ },
   31437             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31438             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31439             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31440             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31441             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31442             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31443             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31444             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31445             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31446             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31447             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31448             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31449             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31450             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31451             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31452             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31453             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31454             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31455             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31456             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31457             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31458             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31459             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31460             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31461             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31462             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31463             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31464             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31465             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31466             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31467             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31468             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31469             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31470             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31471             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31472             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31473             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31474             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31475             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31476             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31477             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31478             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31479             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31480             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31481             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31482             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31483             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31484             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31485             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31486             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31487             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31488             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31489             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31490             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31491             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31492             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31493             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31494             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31495             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31496             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31497             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31498             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31499             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31500             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31501             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31502             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31503             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31504             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31505             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31506             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31507             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31508             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31509             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31510             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31511             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31512             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31513             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31514             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31515             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31516             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31517             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31518             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31519             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31520             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31521             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31522             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31523             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31524             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31525             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31526             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31527             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31528             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31529             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31530             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31531             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31532             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31533             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31534             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31535             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31536             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31537             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31538             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31539             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31540             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31541             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31542             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31543             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31544             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31545             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31546             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31547             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31548             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31549             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31550             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31551             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31552             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31553             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31554             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31555             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31556             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31557             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31558             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31559             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31560             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31561             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31562             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31563             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31564             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31565             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31566             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31567             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31568             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31569             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31570             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31571             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31572             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31573             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31574             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31575             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31576             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31577             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31578             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31579             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31580             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31581             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31582             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31583             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31584             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31585             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31586             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31587             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31588             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31589             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31590             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31591             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31592             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31593             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31594             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31595             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31596             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31597             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31598             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31599             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31600             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31601             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31602             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31603             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31604             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31605             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31606             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31607             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31608             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmGLC, 64 /* 6 */ },
   31609             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmSLC, 128 /* 7 */ },
   31610             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmTFE, 512 /* 9 */ },
   31611             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmUNorm, 32 /* 5 */ },
   31612             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDA, 2048 /* 11 */ },
   31613             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmR128A16, 256 /* 8 */ },
   31614             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmD16, 4096 /* 12 */ },
   31615             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmLWE, 1024 /* 10 */ },
   31616             :   { Feature_isGCN, 7165 /* image_sample_d_cl */, MCK_ImmDMask, 16 /* 4 */ },
   31617             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31618             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31619             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31620             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31621             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31622             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31623             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31624             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31625             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31626             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31627             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31628             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31629             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31630             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31631             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31632             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31633             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31634             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31635             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31636             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31637             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31638             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31639             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31640             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31641             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31642             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31643             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31644             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31645             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31646             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31647             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31648             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31649             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31650             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31651             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31652             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31653             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31654             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31655             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31656             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31657             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31658             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31659             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31660             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31661             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31662             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31663             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31664             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31665             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31666             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31667             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31668             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31669             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31670             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31671             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31672             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31673             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31674             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31675             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31676             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31677             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31678             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31679             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31680             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31681             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31682             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31683             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31684             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31685             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31686             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31687             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31688             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31689             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31690             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31691             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31692             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31693             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31694             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31695             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31696             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31697             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31698             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31699             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31700             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31701             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31702             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31703             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31704             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31705             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31706             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31707             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31708             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31709             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31710             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31711             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31712             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31713             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31714             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31715             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31716             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31717             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31718             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31719             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31720             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31721             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31722             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31723             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31724             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31725             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31726             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31727             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31728             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31729             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31730             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31731             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31732             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31733             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31734             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31735             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31736             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31737             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31738             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31739             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31740             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31741             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31742             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31743             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31744             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31745             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31746             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31747             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31748             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31749             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31750             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31751             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31752             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmGLC, 64 /* 6 */ },
   31753             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmSLC, 128 /* 7 */ },
   31754             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmTFE, 512 /* 9 */ },
   31755             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31756             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDA, 2048 /* 11 */ },
   31757             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31758             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmD16, 4096 /* 12 */ },
   31759             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31760             :   { Feature_isGCN, 7183 /* image_sample_d_cl_o */, MCK_ImmDMask, 16 /* 4 */ },
   31761             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31762             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31763             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31764             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31765             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31766             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31767             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31768             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31769             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31770             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31771             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31772             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31773             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31774             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31775             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31776             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31777             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31778             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31779             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31780             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31781             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31782             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31783             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31784             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31785             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31786             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31787             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31788             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31789             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31790             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31791             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31792             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31793             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31794             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31795             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31796             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31797             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31798             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31799             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31800             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31801             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31802             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31803             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31804             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31805             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31806             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31807             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31808             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31809             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31810             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31811             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31812             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31813             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31814             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31815             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31816             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31817             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31818             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31819             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31820             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31821             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31822             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31823             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31824             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31825             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31826             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31827             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31828             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31829             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31830             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31831             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31832             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31833             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31834             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31835             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31836             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31837             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31838             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31839             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31840             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31841             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31842             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31843             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31844             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31845             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31846             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31847             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31848             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31849             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31850             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31851             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31852             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31853             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31854             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31855             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31856             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31857             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31858             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31859             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31860             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31861             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31862             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31863             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31864             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31865             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31866             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31867             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31868             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31869             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31870             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31871             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31872             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31873             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31874             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31875             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31876             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31877             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31878             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31879             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31880             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31881             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31882             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31883             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31884             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31885             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31886             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31887             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31888             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31889             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31890             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31891             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31892             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31893             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31894             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31895             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31896             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmGLC, 64 /* 6 */ },
   31897             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmSLC, 128 /* 7 */ },
   31898             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmTFE, 512 /* 9 */ },
   31899             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmUNorm, 32 /* 5 */ },
   31900             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDA, 2048 /* 11 */ },
   31901             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmR128A16, 256 /* 8 */ },
   31902             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmD16, 4096 /* 12 */ },
   31903             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmLWE, 1024 /* 10 */ },
   31904             :   { Feature_isGCN, 7203 /* image_sample_d_o */, MCK_ImmDMask, 16 /* 4 */ },
   31905             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31906             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31907             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31908             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31909             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31910             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31911             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31912             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31913             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31914             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31915             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31916             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31917             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31918             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31919             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31920             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31921             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31922             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31923             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31924             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31925             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31926             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31927             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31928             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31929             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31930             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31931             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31932             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31933             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31934             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31935             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31936             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31937             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31938             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31939             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31940             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31941             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31942             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31943             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31944             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31945             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31946             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31947             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31948             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31949             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31950             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31951             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31952             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31953             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31954             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31955             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31956             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31957             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31958             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31959             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31960             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31961             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31962             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31963             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31964             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31965             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31966             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31967             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31968             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31969             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31970             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31971             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31972             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31973             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31974             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31975             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31976             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31977             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31978             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31979             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31980             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31981             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31982             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31983             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31984             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31985             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31986             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31987             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31988             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31989             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31990             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   31991             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   31992             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   31993             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   31994             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   31995             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   31996             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   31997             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   31998             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   31999             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   32000             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   32001             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   32002             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   32003             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   32004             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   32005             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   32006             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   32007             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   32008             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   32009             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   32010             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   32011             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   32012             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   32013             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   32014             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   32015             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   32016             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   32017             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   32018             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   32019             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   32020             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   32021             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   32022             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   32023             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   32024             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   32025             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   32026             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   32027             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   32028             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   32029             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   32030             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   32031             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   32032             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   32033             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   32034             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   32035             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   32036             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   32037             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   32038             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   32039             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   32040             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmGLC, 64 /* 6 */ },
   32041             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmSLC, 128 /* 7 */ },
   32042             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmTFE, 512 /* 9 */ },
   32043             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmUNorm, 32 /* 5 */ },
   32044             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDA, 2048 /* 11 */ },
   32045             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmR128A16, 256 /* 8 */ },
   32046             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmD16, 4096 /* 12 */ },
   32047             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmLWE, 1024 /* 10 */ },
   32048             :   { Feature_isGCN, 7220 /* image_sample_l */, MCK_ImmDMask, 16 /* 4 */ },
   32049             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32050             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32051             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32052             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32053             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32054             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32055             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32056             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32057             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32058             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32059             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32060             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32061             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32062             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32063             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32064             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32065             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32066             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32067             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32068             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32069             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32070             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32071             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32072             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32073             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32074             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32075             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32076             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32077             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32078             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32079             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32080             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32081             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32082             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32083             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32084             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32085             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32086             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32087             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32088             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32089             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32090             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32091             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32092             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32093             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32094             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32095             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32096             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32097             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32098             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32099             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32100             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32101             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32102             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32103             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32104             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32105             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32106             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32107             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32108             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32109             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32110             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32111             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32112             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32113             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32114             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32115             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32116             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32117             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32118             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32119             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32120             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32121             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32122             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32123             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32124             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32125             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32126             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32127             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32128             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32129             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32130             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32131             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32132             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32133             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32134             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32135             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32136             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32137             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32138             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32139             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32140             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32141             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32142             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32143             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32144             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32145             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32146             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32147             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32148             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32149             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32150             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32151             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32152             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32153             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32154             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32155             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32156             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32157             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32158             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32159             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32160             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32161             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32162             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32163             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32164             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32165             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32166             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32167             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32168             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32169             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32170             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32171             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32172             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32173             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32174             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32175             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32176             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32177             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32178             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32179             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32180             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32181             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32182             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32183             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32184             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmGLC, 64 /* 6 */ },
   32185             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmSLC, 128 /* 7 */ },
   32186             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmTFE, 512 /* 9 */ },
   32187             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32188             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDA, 2048 /* 11 */ },
   32189             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32190             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmD16, 4096 /* 12 */ },
   32191             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32192             :   { Feature_isGCN, 7235 /* image_sample_l_o */, MCK_ImmDMask, 16 /* 4 */ },
   32193             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32194             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32195             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32196             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32197             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32198             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32199             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32200             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32201             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32202             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32203             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32204             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32205             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32206             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32207             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32208             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32209             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32210             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32211             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32212             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32213             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32214             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32215             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32216             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32217             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32218             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32219             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32220             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32221             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32222             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32223             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32224             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32225             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32226             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32227             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32228             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32229             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32230             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32231             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32232             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32233             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32234             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32235             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32236             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32237             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32238             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32239             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32240             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32241             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32242             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32243             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32244             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32245             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32246             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32247             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32248             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32249             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32250             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32251             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32252             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32253             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32254             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32255             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32256             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32257             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32258             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32259             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32260             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32261             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32262             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32263             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32264             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32265             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32266             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32267             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32268             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32269             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32270             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32271             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32272             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32273             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32274             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32275             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32276             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32277             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32278             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32279             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32280             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32281             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32282             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32283             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32284             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32285             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32286             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32287             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32288             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32289             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32290             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32291             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32292             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32293             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32294             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32295             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32296             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32297             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32298             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32299             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32300             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32301             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32302             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32303             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32304             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32305             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32306             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32307             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32308             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32309             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32310             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32311             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32312             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32313             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32314             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32315             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32316             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32317             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32318             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32319             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32320             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32321             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32322             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32323             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32324             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32325             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32326             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32327             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32328             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmGLC, 64 /* 6 */ },
   32329             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmSLC, 128 /* 7 */ },
   32330             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmTFE, 512 /* 9 */ },
   32331             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmUNorm, 32 /* 5 */ },
   32332             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDA, 2048 /* 11 */ },
   32333             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmR128A16, 256 /* 8 */ },
   32334             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmD16, 4096 /* 12 */ },
   32335             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmLWE, 1024 /* 10 */ },
   32336             :   { Feature_isGCN, 7252 /* image_sample_lz */, MCK_ImmDMask, 16 /* 4 */ },
   32337             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32338             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32339             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32340             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32341             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32342             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32343             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32344             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32345             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32346             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32347             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32348             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32349             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32350             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32351             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32352             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32353             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32354             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32355             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32356             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32357             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32358             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32359             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32360             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32361             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32362             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32363             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32364             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32365             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32366             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32367             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32368             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32369             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32370             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32371             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32372             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32373             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32374             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32375             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32376             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32377             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32378             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32379             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32380             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32381             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32382             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32383             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32384             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32385             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32386             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32387             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32388             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32389             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32390             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32391             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32392             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32393             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32394             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32395             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32396             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32397             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32398             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32399             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32400             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32401             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32402             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32403             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32404             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32405             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32406             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32407             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32408             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32409             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32410             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32411             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32412             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32413             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32414             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32415             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32416             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32417             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32418             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32419             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32420             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32421             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32422             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32423             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32424             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32425             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32426             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32427             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32428             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32429             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32430             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32431             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32432             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32433             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32434             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32435             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32436             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmGLC, 64 /* 6 */ },
   32437             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmSLC, 128 /* 7 */ },
   32438             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmTFE, 512 /* 9 */ },
   32439             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32440             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDA, 2048 /* 11 */ },
   32441             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32442             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmD16, 4096 /* 12 */ },
   32443             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32444             :   { Feature_isGCN, 7268 /* image_sample_lz_o */, MCK_ImmDMask, 16 /* 4 */ },
   32445             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32446             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32447             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32448             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32449             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32450             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32451             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32452             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32453             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32454             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32455             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32456             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32457             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32458             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32459             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32460             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32461             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32462             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32463             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32464             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32465             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32466             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32467             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32468             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32469             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32470             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32471             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32472             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32473             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32474             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32475             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32476             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32477             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32478             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32479             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32480             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32481             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32482             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32483             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32484             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32485             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32486             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32487             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32488             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32489             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32490             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32491             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32492             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32493             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32494             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32495             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32496             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32497             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32498             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32499             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32500             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32501             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32502             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32503             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32504             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32505             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32506             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32507             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32508             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32509             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32510             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32511             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32512             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32513             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32514             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32515             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32516             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32517             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32518             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32519             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32520             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32521             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32522             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32523             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32524             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32525             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32526             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32527             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32528             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32529             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32530             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32531             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32532             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32533             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32534             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32535             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32536             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32537             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32538             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32539             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32540             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32541             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32542             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32543             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32544             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmGLC, 64 /* 6 */ },
   32545             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmSLC, 128 /* 7 */ },
   32546             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmTFE, 512 /* 9 */ },
   32547             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmUNorm, 32 /* 5 */ },
   32548             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDA, 2048 /* 11 */ },
   32549             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmR128A16, 256 /* 8 */ },
   32550             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmD16, 4096 /* 12 */ },
   32551             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmLWE, 1024 /* 10 */ },
   32552             :   { Feature_isGCN, 7286 /* image_sample_o */, MCK_ImmDMask, 16 /* 4 */ },
   32553             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32554             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32555             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32556             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32557             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32558             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32559             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32560             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32561             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32562             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32563             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32564             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32565             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32566             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32567             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32568             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32569             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32570             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32571             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32572             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32573             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32574             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32575             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32576             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32577             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32578             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32579             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32580             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32581             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32582             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32583             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32584             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32585             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32586             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32587             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32588             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32589             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32590             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32591             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32592             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32593             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32594             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32595             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32596             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32597             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32598             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32599             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32600             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32601             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32602             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32603             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32604             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32605             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32606             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32607             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32608             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32609             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32610             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32611             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32612             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32613             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32614             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32615             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32616             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32617             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32618             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32619             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32620             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32621             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32622             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32623             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32624             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32625             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32626             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32627             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32628             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32629             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32630             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32631             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32632             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32633             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32634             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32635             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32636             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32637             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32638             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32639             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32640             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32641             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32642             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32643             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32644             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32645             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32646             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32647             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32648             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32649             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32650             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32651             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32652             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32653             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32654             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32655             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32656             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32657             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32658             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32659             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32660             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32661             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32662             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32663             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32664             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32665             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32666             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32667             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32668             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32669             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32670             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32671             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32672             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32673             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32674             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32675             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32676             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32677             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32678             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32679             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32680             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32681             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32682             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32683             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32684             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32685             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32686             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32687             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32688             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmGLC, 32 /* 5 */ },
   32689             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmSLC, 64 /* 6 */ },
   32690             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmTFE, 256 /* 8 */ },
   32691             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmUNorm, 16 /* 4 */ },
   32692             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDA, 1024 /* 10 */ },
   32693             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmR128A16, 128 /* 7 */ },
   32694             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmD16, 2048 /* 11 */ },
   32695             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmLWE, 512 /* 9 */ },
   32696             :   { Feature_isGCN, 7301 /* image_store */, MCK_ImmDMask, 8 /* 3 */ },
   32697             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32698             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32699             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32700             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32701             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32702             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32703             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32704             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32705             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32706             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32707             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32708             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32709             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32710             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32711             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32712             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32713             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32714             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32715             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32716             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32717             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32718             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32719             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32720             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32721             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32722             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32723             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32724             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32725             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32726             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32727             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32728             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32729             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32730             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32731             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32732             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32733             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32734             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32735             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32736             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32737             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32738             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32739             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32740             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32741             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32742             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32743             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32744             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32745             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32746             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32747             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32748             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32749             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32750             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32751             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32752             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32753             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32754             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32755             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32756             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32757             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32758             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32759             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32760             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32761             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32762             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32763             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32764             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32765             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32766             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32767             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32768             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32769             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32770             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32771             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32772             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32773             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32774             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32775             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32776             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32777             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32778             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32779             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32780             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32781             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32782             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32783             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32784             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32785             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32786             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32787             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32788             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32789             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32790             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32791             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32792             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32793             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32794             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32795             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32796             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32797             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32798             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32799             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32800             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32801             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32802             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32803             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32804             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32805             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32806             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32807             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32808             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32809             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32810             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32811             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32812             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32813             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32814             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32815             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32816             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32817             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32818             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32819             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32820             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32821             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32822             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32823             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32824             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32825             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32826             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32827             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32828             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32829             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32830             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32831             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32832             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmGLC, 32 /* 5 */ },
   32833             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmSLC, 64 /* 6 */ },
   32834             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmTFE, 256 /* 8 */ },
   32835             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmUNorm, 16 /* 4 */ },
   32836             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDA, 1024 /* 10 */ },
   32837             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmR128A16, 128 /* 7 */ },
   32838             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmD16, 2048 /* 11 */ },
   32839             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmLWE, 512 /* 9 */ },
   32840             :   { Feature_isGCN, 7313 /* image_store_mip */, MCK_ImmDMask, 8 /* 3 */ },
   32841             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32842             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32843             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32844             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32845             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32846             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32847             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32848             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32849             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32850             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32851             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32852             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32853             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32854             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32855             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32856             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32857             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32858             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32859             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32860             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32861             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32862             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32863             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32864             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32865             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32866             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32867             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32868             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32869             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32870             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32871             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32872             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32873             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32874             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32875             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32876             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32877             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32878             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32879             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32880             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32881             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32882             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32883             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32884             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32885             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32886             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32887             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32888             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32889             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32890             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32891             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32892             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32893             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32894             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32895             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32896             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32897             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32898             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32899             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32900             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32901             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32902             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32903             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32904             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32905             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32906             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32907             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32908             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32909             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32910             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32911             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32912             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32913             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32914             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32915             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32916             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32917             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32918             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32919             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32920             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32921             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32922             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32923             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32924             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32925             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32926             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32927             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32928             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32929             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32930             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32931             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32932             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32933             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32934             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32935             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32936             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32937             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32938             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32939             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32940             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32941             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32942             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32943             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32944             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32945             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32946             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32947             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32948             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32949             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32950             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32951             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32952             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32953             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32954             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32955             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32956             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32957             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32958             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32959             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32960             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32961             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32962             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32963             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32964             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32965             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32966             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32967             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32968             :   { Feature_isGCN, 7329 /* image_store_mip_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32969             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32970             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32971             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32972             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32973             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32974             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32975             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32976             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32977             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32978             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32979             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32980             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32981             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32982             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32983             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32984             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32985             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32986             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32987             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32988             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32989             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32990             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32991             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   32992             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   32993             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   32994             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   32995             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   32996             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   32997             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   32998             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   32999             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33000             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33001             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33002             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33003             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33004             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33005             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33006             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33007             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33008             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33009             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33010             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33011             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33012             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33013             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33014             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33015             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33016             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33017             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33018             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33019             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33020             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33021             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33022             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33023             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33024             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33025             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33026             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33027             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33028             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33029             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33030             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33031             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33032             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33033             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33034             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33035             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33036             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33037             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33038             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33039             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33040             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33041             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33042             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33043             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33044             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33045             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33046             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33047             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33048             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33049             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33050             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33051             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33052             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33053             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33054             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33055             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33056             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33057             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33058             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33059             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33060             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33061             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33062             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33063             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33064             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33065             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33066             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33067             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33068             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33069             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33070             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33071             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33072             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33073             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33074             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33075             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33076             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33077             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33078             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33079             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33080             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33081             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33082             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33083             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33084             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33085             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33086             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33087             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33088             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33089             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmGLC, 32 /* 5 */ },
   33090             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmSLC, 64 /* 6 */ },
   33091             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmTFE, 256 /* 8 */ },
   33092             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmUNorm, 16 /* 4 */ },
   33093             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDA, 1024 /* 10 */ },
   33094             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmR128A16, 128 /* 7 */ },
   33095             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmLWE, 512 /* 9 */ },
   33096             :   { Feature_isGCN, 7349 /* image_store_pck */, MCK_ImmDMask, 8 /* 3 */ },
   33097             :   { Feature_isVI|Feature_isVI, 7596 /* s_atc_probe */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33098             :   { Feature_isVI|Feature_isVI, 7608 /* s_atc_probe_buffer */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33099             :   { Feature_HasScalarAtomics|Feature_isVI, 7627 /* s_atomic_add */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33100             :   { Feature_HasScalarAtomics|Feature_isVI, 7627 /* s_atomic_add */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33101             :   { Feature_HasScalarAtomics|Feature_isVI, 7640 /* s_atomic_add_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33102             :   { Feature_HasScalarAtomics|Feature_isVI, 7640 /* s_atomic_add_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33103             :   { Feature_HasScalarAtomics|Feature_isVI, 7656 /* s_atomic_and */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33104             :   { Feature_HasScalarAtomics|Feature_isVI, 7656 /* s_atomic_and */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33105             :   { Feature_HasScalarAtomics|Feature_isVI, 7669 /* s_atomic_and_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33106             :   { Feature_HasScalarAtomics|Feature_isVI, 7669 /* s_atomic_and_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33107             :   { Feature_HasScalarAtomics|Feature_isVI, 7685 /* s_atomic_cmpswap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33108             :   { Feature_HasScalarAtomics|Feature_isVI, 7685 /* s_atomic_cmpswap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33109             :   { Feature_HasScalarAtomics|Feature_isVI, 7702 /* s_atomic_cmpswap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33110             :   { Feature_HasScalarAtomics|Feature_isVI, 7702 /* s_atomic_cmpswap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33111             :   { Feature_HasScalarAtomics|Feature_isVI, 7722 /* s_atomic_dec */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33112             :   { Feature_HasScalarAtomics|Feature_isVI, 7722 /* s_atomic_dec */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33113             :   { Feature_HasScalarAtomics|Feature_isVI, 7735 /* s_atomic_dec_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33114             :   { Feature_HasScalarAtomics|Feature_isVI, 7735 /* s_atomic_dec_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33115             :   { Feature_HasScalarAtomics|Feature_isVI, 7751 /* s_atomic_inc */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33116             :   { Feature_HasScalarAtomics|Feature_isVI, 7751 /* s_atomic_inc */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33117             :   { Feature_HasScalarAtomics|Feature_isVI, 7764 /* s_atomic_inc_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33118             :   { Feature_HasScalarAtomics|Feature_isVI, 7764 /* s_atomic_inc_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33119             :   { Feature_HasScalarAtomics|Feature_isVI, 7780 /* s_atomic_or */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33120             :   { Feature_HasScalarAtomics|Feature_isVI, 7780 /* s_atomic_or */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33121             :   { Feature_HasScalarAtomics|Feature_isVI, 7792 /* s_atomic_or_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33122             :   { Feature_HasScalarAtomics|Feature_isVI, 7792 /* s_atomic_or_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33123             :   { Feature_HasScalarAtomics|Feature_isVI, 7807 /* s_atomic_smax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33124             :   { Feature_HasScalarAtomics|Feature_isVI, 7807 /* s_atomic_smax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33125             :   { Feature_HasScalarAtomics|Feature_isVI, 7821 /* s_atomic_smax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33126             :   { Feature_HasScalarAtomics|Feature_isVI, 7821 /* s_atomic_smax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33127             :   { Feature_HasScalarAtomics|Feature_isVI, 7838 /* s_atomic_smin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33128             :   { Feature_HasScalarAtomics|Feature_isVI, 7838 /* s_atomic_smin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33129             :   { Feature_HasScalarAtomics|Feature_isVI, 7852 /* s_atomic_smin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33130             :   { Feature_HasScalarAtomics|Feature_isVI, 7852 /* s_atomic_smin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33131             :   { Feature_HasScalarAtomics|Feature_isVI, 7869 /* s_atomic_sub */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33132             :   { Feature_HasScalarAtomics|Feature_isVI, 7869 /* s_atomic_sub */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33133             :   { Feature_HasScalarAtomics|Feature_isVI, 7882 /* s_atomic_sub_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33134             :   { Feature_HasScalarAtomics|Feature_isVI, 7882 /* s_atomic_sub_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33135             :   { Feature_HasScalarAtomics|Feature_isVI, 7898 /* s_atomic_swap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33136             :   { Feature_HasScalarAtomics|Feature_isVI, 7898 /* s_atomic_swap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33137             :   { Feature_HasScalarAtomics|Feature_isVI, 7912 /* s_atomic_swap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33138             :   { Feature_HasScalarAtomics|Feature_isVI, 7912 /* s_atomic_swap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33139             :   { Feature_HasScalarAtomics|Feature_isVI, 7929 /* s_atomic_umax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33140             :   { Feature_HasScalarAtomics|Feature_isVI, 7929 /* s_atomic_umax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33141             :   { Feature_HasScalarAtomics|Feature_isVI, 7943 /* s_atomic_umax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33142             :   { Feature_HasScalarAtomics|Feature_isVI, 7943 /* s_atomic_umax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33143             :   { Feature_HasScalarAtomics|Feature_isVI, 7960 /* s_atomic_umin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33144             :   { Feature_HasScalarAtomics|Feature_isVI, 7960 /* s_atomic_umin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33145             :   { Feature_HasScalarAtomics|Feature_isVI, 7974 /* s_atomic_umin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33146             :   { Feature_HasScalarAtomics|Feature_isVI, 7974 /* s_atomic_umin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33147             :   { Feature_HasScalarAtomics|Feature_isVI, 7991 /* s_atomic_xor */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33148             :   { Feature_HasScalarAtomics|Feature_isVI, 7991 /* s_atomic_xor */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33149             :   { Feature_HasScalarAtomics|Feature_isVI, 8004 /* s_atomic_xor_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33150             :   { Feature_HasScalarAtomics|Feature_isVI, 8004 /* s_atomic_xor_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33151             :   { Feature_isGCN, 8289 /* s_branch */, MCK_SoppBrTarget, 1 /* 0 */ },
   33152             :   { Feature_HasScalarAtomics|Feature_isVI, 8320 /* s_buffer_atomic_add */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33153             :   { Feature_HasScalarAtomics|Feature_isVI, 8320 /* s_buffer_atomic_add */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33154             :   { Feature_HasScalarAtomics|Feature_isVI, 8340 /* s_buffer_atomic_add_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33155             :   { Feature_HasScalarAtomics|Feature_isVI, 8340 /* s_buffer_atomic_add_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33156             :   { Feature_HasScalarAtomics|Feature_isVI, 8363 /* s_buffer_atomic_and */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33157             :   { Feature_HasScalarAtomics|Feature_isVI, 8363 /* s_buffer_atomic_and */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33158             :   { Feature_HasScalarAtomics|Feature_isVI, 8383 /* s_buffer_atomic_and_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33159             :   { Feature_HasScalarAtomics|Feature_isVI, 8383 /* s_buffer_atomic_and_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33160             :   { Feature_HasScalarAtomics|Feature_isVI, 8406 /* s_buffer_atomic_cmpswap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33161             :   { Feature_HasScalarAtomics|Feature_isVI, 8406 /* s_buffer_atomic_cmpswap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33162             :   { Feature_HasScalarAtomics|Feature_isVI, 8430 /* s_buffer_atomic_cmpswap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33163             :   { Feature_HasScalarAtomics|Feature_isVI, 8430 /* s_buffer_atomic_cmpswap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33164             :   { Feature_HasScalarAtomics|Feature_isVI, 8457 /* s_buffer_atomic_dec */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33165             :   { Feature_HasScalarAtomics|Feature_isVI, 8457 /* s_buffer_atomic_dec */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33166             :   { Feature_HasScalarAtomics|Feature_isVI, 8477 /* s_buffer_atomic_dec_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33167             :   { Feature_HasScalarAtomics|Feature_isVI, 8477 /* s_buffer_atomic_dec_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33168             :   { Feature_HasScalarAtomics|Feature_isVI, 8500 /* s_buffer_atomic_inc */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33169             :   { Feature_HasScalarAtomics|Feature_isVI, 8500 /* s_buffer_atomic_inc */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33170             :   { Feature_HasScalarAtomics|Feature_isVI, 8520 /* s_buffer_atomic_inc_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33171             :   { Feature_HasScalarAtomics|Feature_isVI, 8520 /* s_buffer_atomic_inc_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33172             :   { Feature_HasScalarAtomics|Feature_isVI, 8543 /* s_buffer_atomic_or */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33173             :   { Feature_HasScalarAtomics|Feature_isVI, 8543 /* s_buffer_atomic_or */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33174             :   { Feature_HasScalarAtomics|Feature_isVI, 8562 /* s_buffer_atomic_or_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33175             :   { Feature_HasScalarAtomics|Feature_isVI, 8562 /* s_buffer_atomic_or_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33176             :   { Feature_HasScalarAtomics|Feature_isVI, 8584 /* s_buffer_atomic_smax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33177             :   { Feature_HasScalarAtomics|Feature_isVI, 8584 /* s_buffer_atomic_smax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33178             :   { Feature_HasScalarAtomics|Feature_isVI, 8605 /* s_buffer_atomic_smax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33179             :   { Feature_HasScalarAtomics|Feature_isVI, 8605 /* s_buffer_atomic_smax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33180             :   { Feature_HasScalarAtomics|Feature_isVI, 8629 /* s_buffer_atomic_smin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33181             :   { Feature_HasScalarAtomics|Feature_isVI, 8629 /* s_buffer_atomic_smin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33182             :   { Feature_HasScalarAtomics|Feature_isVI, 8650 /* s_buffer_atomic_smin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33183             :   { Feature_HasScalarAtomics|Feature_isVI, 8650 /* s_buffer_atomic_smin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33184             :   { Feature_HasScalarAtomics|Feature_isVI, 8674 /* s_buffer_atomic_sub */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33185             :   { Feature_HasScalarAtomics|Feature_isVI, 8674 /* s_buffer_atomic_sub */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33186             :   { Feature_HasScalarAtomics|Feature_isVI, 8694 /* s_buffer_atomic_sub_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33187             :   { Feature_HasScalarAtomics|Feature_isVI, 8694 /* s_buffer_atomic_sub_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33188             :   { Feature_HasScalarAtomics|Feature_isVI, 8717 /* s_buffer_atomic_swap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33189             :   { Feature_HasScalarAtomics|Feature_isVI, 8717 /* s_buffer_atomic_swap */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33190             :   { Feature_HasScalarAtomics|Feature_isVI, 8738 /* s_buffer_atomic_swap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33191             :   { Feature_HasScalarAtomics|Feature_isVI, 8738 /* s_buffer_atomic_swap_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33192             :   { Feature_HasScalarAtomics|Feature_isVI, 8762 /* s_buffer_atomic_umax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33193             :   { Feature_HasScalarAtomics|Feature_isVI, 8762 /* s_buffer_atomic_umax */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33194             :   { Feature_HasScalarAtomics|Feature_isVI, 8783 /* s_buffer_atomic_umax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33195             :   { Feature_HasScalarAtomics|Feature_isVI, 8783 /* s_buffer_atomic_umax_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33196             :   { Feature_HasScalarAtomics|Feature_isVI, 8807 /* s_buffer_atomic_umin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33197             :   { Feature_HasScalarAtomics|Feature_isVI, 8807 /* s_buffer_atomic_umin */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33198             :   { Feature_HasScalarAtomics|Feature_isVI, 8828 /* s_buffer_atomic_umin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33199             :   { Feature_HasScalarAtomics|Feature_isVI, 8828 /* s_buffer_atomic_umin_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33200             :   { Feature_HasScalarAtomics|Feature_isVI, 8852 /* s_buffer_atomic_xor */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33201             :   { Feature_HasScalarAtomics|Feature_isVI, 8852 /* s_buffer_atomic_xor */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33202             :   { Feature_HasScalarAtomics|Feature_isVI, 8872 /* s_buffer_atomic_xor_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33203             :   { Feature_HasScalarAtomics|Feature_isVI, 8872 /* s_buffer_atomic_xor_x2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33204             :   { Feature_isGCN|Feature_isSICI, 8895 /* s_buffer_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33205             :   { Feature_isGCN|Feature_isVI, 8895 /* s_buffer_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33206             :   { Feature_isGCN|Feature_isSICI, 8895 /* s_buffer_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33207             :   { Feature_isGCN|Feature_isSICI, 8895 /* s_buffer_load_dword */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33208             :   { Feature_isGCN|Feature_isVI, 8895 /* s_buffer_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33209             :   { Feature_isGCN|Feature_isVI, 8895 /* s_buffer_load_dword */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33210             :   { Feature_isGCN|Feature_isCIOnly, 8895 /* s_buffer_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33211             :   { Feature_isGCN|Feature_isCIOnly, 8895 /* s_buffer_load_dword */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33212             :   { Feature_isGCN|Feature_isSICI, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33213             :   { Feature_isGCN|Feature_isVI, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33214             :   { Feature_isGCN|Feature_isSICI, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33215             :   { Feature_isGCN|Feature_isSICI, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33216             :   { Feature_isGCN|Feature_isVI, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33217             :   { Feature_isGCN|Feature_isVI, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33218             :   { Feature_isGCN|Feature_isCIOnly, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33219             :   { Feature_isGCN|Feature_isCIOnly, 8915 /* s_buffer_load_dwordx16 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33220             :   { Feature_isGCN|Feature_isSICI, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33221             :   { Feature_isGCN|Feature_isVI, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33222             :   { Feature_isGCN|Feature_isSICI, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33223             :   { Feature_isGCN|Feature_isSICI, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33224             :   { Feature_isGCN|Feature_isVI, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33225             :   { Feature_isGCN|Feature_isVI, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33226             :   { Feature_isGCN|Feature_isCIOnly, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33227             :   { Feature_isGCN|Feature_isCIOnly, 8938 /* s_buffer_load_dwordx2 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33228             :   { Feature_isGCN|Feature_isSICI, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33229             :   { Feature_isGCN|Feature_isVI, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33230             :   { Feature_isGCN|Feature_isSICI, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33231             :   { Feature_isGCN|Feature_isSICI, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33232             :   { Feature_isGCN|Feature_isVI, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33233             :   { Feature_isGCN|Feature_isVI, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33234             :   { Feature_isGCN|Feature_isCIOnly, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33235             :   { Feature_isGCN|Feature_isCIOnly, 8960 /* s_buffer_load_dwordx4 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33236             :   { Feature_isGCN|Feature_isSICI, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33237             :   { Feature_isGCN|Feature_isVI, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33238             :   { Feature_isGCN|Feature_isSICI, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33239             :   { Feature_isGCN|Feature_isSICI, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33240             :   { Feature_isGCN|Feature_isVI, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33241             :   { Feature_isGCN|Feature_isVI, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33242             :   { Feature_isGCN|Feature_isCIOnly, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33243             :   { Feature_isGCN|Feature_isCIOnly, 8982 /* s_buffer_load_dwordx8 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33244             :   { Feature_isGCN|Feature_isVI, 9004 /* s_buffer_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33245             :   { Feature_isGCN|Feature_isVI, 9004 /* s_buffer_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33246             :   { Feature_isGCN|Feature_isVI, 9004 /* s_buffer_store_dword */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33247             :   { Feature_isGCN|Feature_isVI, 9025 /* s_buffer_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33248             :   { Feature_isGCN|Feature_isVI, 9025 /* s_buffer_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33249             :   { Feature_isGCN|Feature_isVI, 9025 /* s_buffer_store_dwordx2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33250             :   { Feature_isGCN|Feature_isVI, 9048 /* s_buffer_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33251             :   { Feature_isGCN|Feature_isVI, 9048 /* s_buffer_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33252             :   { Feature_isGCN|Feature_isVI, 9048 /* s_buffer_store_dwordx4 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33253             :   { Feature_isGCN, 9082 /* s_cbranch_cdbgsys */, MCK_SoppBrTarget, 1 /* 0 */ },
   33254             :   { Feature_isGCN, 9100 /* s_cbranch_cdbgsys_and_user */, MCK_SoppBrTarget, 1 /* 0 */ },
   33255             :   { Feature_isGCN, 9127 /* s_cbranch_cdbgsys_or_user */, MCK_SoppBrTarget, 1 /* 0 */ },
   33256             :   { Feature_isGCN, 9153 /* s_cbranch_cdbguser */, MCK_SoppBrTarget, 1 /* 0 */ },
   33257             :   { Feature_isGCN, 9172 /* s_cbranch_execnz */, MCK_SoppBrTarget, 1 /* 0 */ },
   33258             :   { Feature_isGCN, 9189 /* s_cbranch_execz */, MCK_SoppBrTarget, 1 /* 0 */ },
   33259             :   { Feature_isGCN, 9254 /* s_cbranch_scc0 */, MCK_SoppBrTarget, 1 /* 0 */ },
   33260             :   { Feature_isGCN, 9269 /* s_cbranch_scc1 */, MCK_SoppBrTarget, 1 /* 0 */ },
   33261             :   { Feature_isGCN, 9284 /* s_cbranch_vccnz */, MCK_SoppBrTarget, 1 /* 0 */ },
   33262             :   { Feature_isGCN, 9300 /* s_cbranch_vccz */, MCK_SoppBrTarget, 1 /* 0 */ },
   33263             :   { Feature_isGFX9|Feature_isVI, 9727 /* s_dcache_discard */, MCK_ImmSMRDOffset20, 2 /* 1 */ },
   33264             :   { Feature_isGFX9|Feature_isVI, 9744 /* s_dcache_discard_x2 */, MCK_ImmSMRDOffset20, 2 /* 1 */ },
   33265             :   { Feature_isGCN|Feature_isSICI, 10014 /* s_getreg_b32 */, MCK_ImmHwreg, 2 /* 1 */ },
   33266             :   { Feature_isGCN|Feature_isVI, 10014 /* s_getreg_b32 */, MCK_ImmHwreg, 2 /* 1 */ },
   33267             :   { Feature_isGCN|Feature_isSICI, 10055 /* s_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33268             :   { Feature_isGCN|Feature_isVI, 10055 /* s_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33269             :   { Feature_isGCN|Feature_isSICI, 10055 /* s_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33270             :   { Feature_isGCN|Feature_isSICI, 10055 /* s_load_dword */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33271             :   { Feature_isGCN|Feature_isVI, 10055 /* s_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33272             :   { Feature_isGCN|Feature_isVI, 10055 /* s_load_dword */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33273             :   { Feature_isGCN|Feature_isCIOnly, 10055 /* s_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33274             :   { Feature_isGCN|Feature_isCIOnly, 10055 /* s_load_dword */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33275             :   { Feature_isGCN|Feature_isSICI, 10068 /* s_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33276             :   { Feature_isGCN|Feature_isVI, 10068 /* s_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33277             :   { Feature_isGCN|Feature_isSICI, 10068 /* s_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33278             :   { Feature_isGCN|Feature_isSICI, 10068 /* s_load_dwordx16 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33279             :   { Feature_isGCN|Feature_isVI, 10068 /* s_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33280             :   { Feature_isGCN|Feature_isVI, 10068 /* s_load_dwordx16 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33281             :   { Feature_isGCN|Feature_isCIOnly, 10068 /* s_load_dwordx16 */, MCK_ImmGLC, 8 /* 3 */ },
   33282             :   { Feature_isGCN|Feature_isCIOnly, 10068 /* s_load_dwordx16 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33283             :   { Feature_isGCN|Feature_isSICI, 10084 /* s_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33284             :   { Feature_isGCN|Feature_isVI, 10084 /* s_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33285             :   { Feature_isGCN|Feature_isSICI, 10084 /* s_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33286             :   { Feature_isGCN|Feature_isSICI, 10084 /* s_load_dwordx2 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33287             :   { Feature_isGCN|Feature_isVI, 10084 /* s_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33288             :   { Feature_isGCN|Feature_isVI, 10084 /* s_load_dwordx2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33289             :   { Feature_isGCN|Feature_isCIOnly, 10084 /* s_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33290             :   { Feature_isGCN|Feature_isCIOnly, 10084 /* s_load_dwordx2 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33291             :   { Feature_isGCN|Feature_isSICI, 10099 /* s_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33292             :   { Feature_isGCN|Feature_isVI, 10099 /* s_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33293             :   { Feature_isGCN|Feature_isSICI, 10099 /* s_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33294             :   { Feature_isGCN|Feature_isSICI, 10099 /* s_load_dwordx4 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33295             :   { Feature_isGCN|Feature_isVI, 10099 /* s_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33296             :   { Feature_isGCN|Feature_isVI, 10099 /* s_load_dwordx4 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33297             :   { Feature_isGCN|Feature_isCIOnly, 10099 /* s_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33298             :   { Feature_isGCN|Feature_isCIOnly, 10099 /* s_load_dwordx4 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33299             :   { Feature_isGCN|Feature_isSICI, 10114 /* s_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33300             :   { Feature_isGCN|Feature_isVI, 10114 /* s_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33301             :   { Feature_isGCN|Feature_isSICI, 10114 /* s_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33302             :   { Feature_isGCN|Feature_isSICI, 10114 /* s_load_dwordx8 */, MCK_ImmSMRDOffset8, 4 /* 2 */ },
   33303             :   { Feature_isGCN|Feature_isVI, 10114 /* s_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33304             :   { Feature_isGCN|Feature_isVI, 10114 /* s_load_dwordx8 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33305             :   { Feature_isGCN|Feature_isCIOnly, 10114 /* s_load_dwordx8 */, MCK_ImmGLC, 8 /* 3 */ },
   33306             :   { Feature_isGCN|Feature_isCIOnly, 10114 /* s_load_dwordx8 */, MCK_ImmSMRDLiteralOffset, 4 /* 2 */ },
   33307             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10782 /* s_scratch_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33308             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10782 /* s_scratch_load_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33309             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10782 /* s_scratch_load_dword */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33310             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10803 /* s_scratch_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33311             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10803 /* s_scratch_load_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33312             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10803 /* s_scratch_load_dwordx2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33313             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10826 /* s_scratch_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33314             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10826 /* s_scratch_load_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33315             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10826 /* s_scratch_load_dwordx4 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33316             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10849 /* s_scratch_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33317             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10849 /* s_scratch_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33318             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10849 /* s_scratch_store_dword */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33319             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10871 /* s_scratch_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33320             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10871 /* s_scratch_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33321             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10871 /* s_scratch_store_dwordx2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33322             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10895 /* s_scratch_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33323             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10895 /* s_scratch_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33324             :   { Feature_HasFlatScratchInsts|Feature_isVI, 10895 /* s_scratch_store_dwordx4 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33325             :   { Feature_isGCN, 10919 /* s_sendmsg */, MCK_SendMsg, 1 /* 0 */ },
   33326             :   { Feature_isGCN, 10929 /* s_sendmsghalt */, MCK_SendMsg, 1 /* 0 */ },
   33327             :   { Feature_isGCN|Feature_isSICI, 11057 /* s_setreg_b32 */, MCK_ImmHwreg, 1 /* 0 */ },
   33328             :   { Feature_isGCN|Feature_isVI, 11057 /* s_setreg_b32 */, MCK_ImmHwreg, 1 /* 0 */ },
   33329             :   { Feature_isGCN|Feature_isSICI, 11070 /* s_setreg_imm32_b32 */, MCK_ImmHwreg, 1 /* 0 */ },
   33330             :   { Feature_isGCN|Feature_isVI, 11070 /* s_setreg_imm32_b32 */, MCK_ImmHwreg, 1 /* 0 */ },
   33331             :   { Feature_isGCN|Feature_isVI, 11137 /* s_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33332             :   { Feature_isGCN|Feature_isVI, 11137 /* s_store_dword */, MCK_ImmGLC, 8 /* 3 */ },
   33333             :   { Feature_isGCN|Feature_isVI, 11137 /* s_store_dword */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33334             :   { Feature_isGCN|Feature_isVI, 11151 /* s_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33335             :   { Feature_isGCN|Feature_isVI, 11151 /* s_store_dwordx2 */, MCK_ImmGLC, 8 /* 3 */ },
   33336             :   { Feature_isGCN|Feature_isVI, 11151 /* s_store_dwordx2 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33337             :   { Feature_isGCN|Feature_isVI, 11167 /* s_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33338             :   { Feature_isGCN|Feature_isVI, 11167 /* s_store_dwordx4 */, MCK_ImmGLC, 8 /* 3 */ },
   33339             :   { Feature_isGCN|Feature_isVI, 11167 /* s_store_dwordx4 */, MCK_ImmSMRDOffset20, 4 /* 2 */ },
   33340             :   { Feature_isGCN, 11247 /* s_waitcnt */, MCK_SWaitCnt, 1 /* 0 */ },
   33341             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11367 /* scratch_load_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33342             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11367 /* scratch_load_dword */, MCK_ImmGLC, 16 /* 4 */ },
   33343             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11367 /* scratch_load_dword */, MCK_ImmSLC, 32 /* 5 */ },
   33344             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11367 /* scratch_load_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33345             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11367 /* scratch_load_dword */, MCK_ImmGLC, 16 /* 4 */ },
   33346             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11367 /* scratch_load_dword */, MCK_ImmSLC, 32 /* 5 */ },
   33347             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11386 /* scratch_load_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33348             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11386 /* scratch_load_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   33349             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11386 /* scratch_load_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   33350             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11386 /* scratch_load_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33351             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11386 /* scratch_load_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   33352             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11386 /* scratch_load_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   33353             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11407 /* scratch_load_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33354             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11407 /* scratch_load_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   33355             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11407 /* scratch_load_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   33356             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11407 /* scratch_load_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33357             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11407 /* scratch_load_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   33358             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11407 /* scratch_load_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   33359             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11428 /* scratch_load_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33360             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11428 /* scratch_load_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   33361             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11428 /* scratch_load_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   33362             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11428 /* scratch_load_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33363             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11428 /* scratch_load_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   33364             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11428 /* scratch_load_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   33365             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11449 /* scratch_load_sbyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33366             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11449 /* scratch_load_sbyte */, MCK_ImmGLC, 16 /* 4 */ },
   33367             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11449 /* scratch_load_sbyte */, MCK_ImmSLC, 32 /* 5 */ },
   33368             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11449 /* scratch_load_sbyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33369             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11449 /* scratch_load_sbyte */, MCK_ImmGLC, 16 /* 4 */ },
   33370             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11449 /* scratch_load_sbyte */, MCK_ImmSLC, 32 /* 5 */ },
   33371             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11468 /* scratch_load_sbyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33372             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11468 /* scratch_load_sbyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   33373             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11468 /* scratch_load_sbyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   33374             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11468 /* scratch_load_sbyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33375             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11468 /* scratch_load_sbyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   33376             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11468 /* scratch_load_sbyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   33377             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11491 /* scratch_load_sbyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33378             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11491 /* scratch_load_sbyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33379             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11491 /* scratch_load_sbyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33380             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11491 /* scratch_load_sbyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33381             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11491 /* scratch_load_sbyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33382             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11491 /* scratch_load_sbyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33383             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11517 /* scratch_load_short_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33384             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11517 /* scratch_load_short_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   33385             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11517 /* scratch_load_short_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   33386             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11517 /* scratch_load_short_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33387             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11517 /* scratch_load_short_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   33388             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11517 /* scratch_load_short_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   33389             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11540 /* scratch_load_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33390             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11540 /* scratch_load_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33391             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11540 /* scratch_load_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33392             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11540 /* scratch_load_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33393             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11540 /* scratch_load_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33394             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11540 /* scratch_load_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33395             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11566 /* scratch_load_sshort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33396             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11566 /* scratch_load_sshort */, MCK_ImmGLC, 16 /* 4 */ },
   33397             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11566 /* scratch_load_sshort */, MCK_ImmSLC, 32 /* 5 */ },
   33398             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11566 /* scratch_load_sshort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33399             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11566 /* scratch_load_sshort */, MCK_ImmGLC, 16 /* 4 */ },
   33400             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11566 /* scratch_load_sshort */, MCK_ImmSLC, 32 /* 5 */ },
   33401             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11586 /* scratch_load_ubyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33402             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11586 /* scratch_load_ubyte */, MCK_ImmGLC, 16 /* 4 */ },
   33403             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11586 /* scratch_load_ubyte */, MCK_ImmSLC, 32 /* 5 */ },
   33404             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11586 /* scratch_load_ubyte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33405             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11586 /* scratch_load_ubyte */, MCK_ImmGLC, 16 /* 4 */ },
   33406             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11586 /* scratch_load_ubyte */, MCK_ImmSLC, 32 /* 5 */ },
   33407             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11605 /* scratch_load_ubyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33408             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11605 /* scratch_load_ubyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   33409             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11605 /* scratch_load_ubyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   33410             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11605 /* scratch_load_ubyte_d16 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33411             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11605 /* scratch_load_ubyte_d16 */, MCK_ImmGLC, 16 /* 4 */ },
   33412             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11605 /* scratch_load_ubyte_d16 */, MCK_ImmSLC, 32 /* 5 */ },
   33413             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11628 /* scratch_load_ubyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33414             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11628 /* scratch_load_ubyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33415             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11628 /* scratch_load_ubyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33416             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11628 /* scratch_load_ubyte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33417             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11628 /* scratch_load_ubyte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33418             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11628 /* scratch_load_ubyte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33419             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11654 /* scratch_load_ushort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33420             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11654 /* scratch_load_ushort */, MCK_ImmGLC, 16 /* 4 */ },
   33421             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11654 /* scratch_load_ushort */, MCK_ImmSLC, 32 /* 5 */ },
   33422             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11654 /* scratch_load_ushort */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33423             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11654 /* scratch_load_ushort */, MCK_ImmGLC, 16 /* 4 */ },
   33424             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11654 /* scratch_load_ushort */, MCK_ImmSLC, 32 /* 5 */ },
   33425             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11674 /* scratch_store_byte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33426             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11674 /* scratch_store_byte */, MCK_ImmGLC, 16 /* 4 */ },
   33427             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11674 /* scratch_store_byte */, MCK_ImmSLC, 32 /* 5 */ },
   33428             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11674 /* scratch_store_byte */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33429             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11674 /* scratch_store_byte */, MCK_ImmGLC, 16 /* 4 */ },
   33430             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11674 /* scratch_store_byte */, MCK_ImmSLC, 32 /* 5 */ },
   33431             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11693 /* scratch_store_byte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33432             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11693 /* scratch_store_byte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33433             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11693 /* scratch_store_byte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33434             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11693 /* scratch_store_byte_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33435             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11693 /* scratch_store_byte_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33436             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11693 /* scratch_store_byte_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33437             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11719 /* scratch_store_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33438             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11719 /* scratch_store_dword */, MCK_ImmGLC, 16 /* 4 */ },
   33439             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11719 /* scratch_store_dword */, MCK_ImmSLC, 32 /* 5 */ },
   33440             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11719 /* scratch_store_dword */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33441             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11719 /* scratch_store_dword */, MCK_ImmGLC, 16 /* 4 */ },
   33442             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11719 /* scratch_store_dword */, MCK_ImmSLC, 32 /* 5 */ },
   33443             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11739 /* scratch_store_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33444             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11739 /* scratch_store_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   33445             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11739 /* scratch_store_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   33446             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11739 /* scratch_store_dwordx2 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33447             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11739 /* scratch_store_dwordx2 */, MCK_ImmGLC, 16 /* 4 */ },
   33448             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11739 /* scratch_store_dwordx2 */, MCK_ImmSLC, 32 /* 5 */ },
   33449             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11761 /* scratch_store_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33450             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11761 /* scratch_store_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   33451             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11761 /* scratch_store_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   33452             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11761 /* scratch_store_dwordx3 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33453             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11761 /* scratch_store_dwordx3 */, MCK_ImmGLC, 16 /* 4 */ },
   33454             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11761 /* scratch_store_dwordx3 */, MCK_ImmSLC, 32 /* 5 */ },
   33455             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11783 /* scratch_store_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33456             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11783 /* scratch_store_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   33457             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11783 /* scratch_store_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   33458             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11783 /* scratch_store_dwordx4 */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33459             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11783 /* scratch_store_dwordx4 */, MCK_ImmGLC, 16 /* 4 */ },
   33460             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11783 /* scratch_store_dwordx4 */, MCK_ImmSLC, 32 /* 5 */ },
   33461             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11805 /* scratch_store_short */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33462             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11805 /* scratch_store_short */, MCK_ImmGLC, 16 /* 4 */ },
   33463             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11805 /* scratch_store_short */, MCK_ImmSLC, 32 /* 5 */ },
   33464             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11805 /* scratch_store_short */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33465             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11805 /* scratch_store_short */, MCK_ImmGLC, 16 /* 4 */ },
   33466             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11805 /* scratch_store_short */, MCK_ImmSLC, 32 /* 5 */ },
   33467             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11825 /* scratch_store_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33468             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11825 /* scratch_store_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33469             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11825 /* scratch_store_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33470             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11825 /* scratch_store_short_d16_hi */, MCK_ImmOffsetS13, 8 /* 3 */ },
   33471             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11825 /* scratch_store_short_d16_hi */, MCK_ImmGLC, 16 /* 4 */ },
   33472             :   { Feature_HasFlatScratchInsts|Feature_isVI, 11825 /* scratch_store_short_d16_hi */, MCK_ImmSLC, 32 /* 5 */ },
   33473             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   33474             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   33475             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   33476             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   33477             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33478             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   33479             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   33480             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   33481             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   33482             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33483             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33484             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33485             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33486             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33487             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33488             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33489             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33490             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33491             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33492             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33493             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33494             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33495             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33496             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33497             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33498             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33499             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33500             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33501             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33502             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33503             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 128 /* 7 */ },
   33504             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 256 /* 8 */ },
   33505             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 512 /* 9 */ },
   33506             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 1024 /* 10 */ },
   33507             :   { Feature_HasPackedD16VMem|Feature_isVI, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33508             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmOffset, 128 /* 7 */ },
   33509             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmGLC, 256 /* 8 */ },
   33510             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmSLC, 512 /* 9 */ },
   33511             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmTFE, 1024 /* 10 */ },
   33512             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11852 /* tbuffer_load_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33513             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   33514             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   33515             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   33516             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   33517             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33518             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   33519             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   33520             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   33521             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   33522             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33523             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33524             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33525             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33526             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33527             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33528             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33529             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33530             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33531             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33532             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33533             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33534             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33535             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33536             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33537             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33538             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33539             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33540             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33541             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33542             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33543             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 128 /* 7 */ },
   33544             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 256 /* 8 */ },
   33545             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 512 /* 9 */ },
   33546             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   33547             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33548             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmOffset, 128 /* 7 */ },
   33549             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmGLC, 256 /* 8 */ },
   33550             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmSLC, 512 /* 9 */ },
   33551             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   33552             :   { Feature_HasPackedD16VMem|Feature_isVI, 11878 /* tbuffer_load_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33553             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   33554             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   33555             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   33556             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   33557             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33558             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   33559             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   33560             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   33561             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   33562             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33563             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33564             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33565             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33566             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33567             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33568             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33569             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33570             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33571             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33572             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33573             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33574             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33575             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33576             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33577             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33578             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33579             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33580             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33581             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33582             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33583             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   33584             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   33585             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   33586             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   33587             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33588             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   33589             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   33590             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   33591             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   33592             :   { Feature_HasPackedD16VMem|Feature_isVI, 11905 /* tbuffer_load_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33593             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   33594             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   33595             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   33596             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   33597             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33598             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   33599             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   33600             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   33601             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   33602             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33603             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33604             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33605             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33606             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33607             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33608             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33609             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33610             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33611             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33612             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33613             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33614             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33615             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33616             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33617             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33618             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33619             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33620             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33621             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33622             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33623             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   33624             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   33625             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   33626             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   33627             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33628             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   33629             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   33630             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   33631             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   33632             :   { Feature_HasPackedD16VMem|Feature_isVI, 11933 /* tbuffer_load_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33633             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   33634             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   33635             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   33636             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   33637             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33638             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   33639             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   33640             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   33641             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   33642             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33643             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33644             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33645             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33646             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33647             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33648             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33649             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33650             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33651             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33652             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33653             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33654             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33655             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33656             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33657             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33658             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33659             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33660             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33661             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33662             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33663             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33664             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33665             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33666             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33667             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33668             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 128 /* 7 */ },
   33669             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 256 /* 8 */ },
   33670             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 512 /* 9 */ },
   33671             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 1024 /* 10 */ },
   33672             :   { Feature_isGCN|Feature_isSICI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33673             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmOffset, 128 /* 7 */ },
   33674             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmGLC, 256 /* 8 */ },
   33675             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmSLC, 512 /* 9 */ },
   33676             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmTFE, 1024 /* 10 */ },
   33677             :   { Feature_isGCN|Feature_isVI, 11962 /* tbuffer_load_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33678             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   33679             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   33680             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   33681             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   33682             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33683             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   33684             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   33685             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   33686             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   33687             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33688             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33689             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33690             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33691             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33692             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33693             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33694             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33695             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33696             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33697             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33698             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33699             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33700             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33701             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33702             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33703             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33704             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33705             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33706             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33707             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33708             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33709             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33710             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33711             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33712             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33713             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 128 /* 7 */ },
   33714             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 256 /* 8 */ },
   33715             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 512 /* 9 */ },
   33716             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   33717             :   { Feature_isGCN|Feature_isSICI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33718             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmOffset, 128 /* 7 */ },
   33719             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmGLC, 256 /* 8 */ },
   33720             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmSLC, 512 /* 9 */ },
   33721             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   33722             :   { Feature_isGCN|Feature_isVI, 11984 /* tbuffer_load_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33723             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   33724             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   33725             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   33726             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   33727             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33728             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   33729             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   33730             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   33731             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   33732             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33733             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33734             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33735             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33736             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33737             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33738             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33739             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33740             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33741             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33742             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33743             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33744             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33745             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33746             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33747             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33748             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33749             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33750             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33751             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33752             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33753             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33754             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33755             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33756             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33757             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33758             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   33759             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   33760             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   33761             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   33762             :   { Feature_isGCN|Feature_isSICI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33763             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   33764             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   33765             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   33766             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   33767             :   { Feature_isGCN|Feature_isVI, 12007 /* tbuffer_load_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33768             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   33769             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   33770             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   33771             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   33772             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33773             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   33774             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   33775             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   33776             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   33777             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33778             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33779             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33780             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33781             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33782             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33783             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33784             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33785             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33786             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33787             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33788             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33789             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33790             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33791             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33792             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33793             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33794             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33795             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33796             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33797             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33798             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33799             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33800             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33801             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33802             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33803             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   33804             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   33805             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   33806             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   33807             :   { Feature_isGCN|Feature_isSICI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33808             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   33809             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   33810             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   33811             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   33812             :   { Feature_isGCN|Feature_isVI, 12031 /* tbuffer_load_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33813             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   33814             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   33815             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   33816             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   33817             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33818             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 32 /* 5 */ },
   33819             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 64 /* 6 */ },
   33820             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 128 /* 7 */ },
   33821             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 256 /* 8 */ },
   33822             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33823             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33824             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33825             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33826             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33827             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33828             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33829             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33830             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33831             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33832             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33833             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33834             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33835             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33836             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33837             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33838             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 64 /* 6 */ },
   33839             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 128 /* 7 */ },
   33840             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 256 /* 8 */ },
   33841             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 512 /* 9 */ },
   33842             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33843             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 128 /* 7 */ },
   33844             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 256 /* 8 */ },
   33845             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 512 /* 9 */ },
   33846             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 1024 /* 10 */ },
   33847             :   { Feature_HasPackedD16VMem|Feature_isVI, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33848             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmOffset, 128 /* 7 */ },
   33849             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmGLC, 256 /* 8 */ },
   33850             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmSLC, 512 /* 9 */ },
   33851             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmTFE, 1024 /* 10 */ },
   33852             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12056 /* tbuffer_store_format_d16_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33853             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   33854             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   33855             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   33856             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   33857             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33858             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 32 /* 5 */ },
   33859             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 64 /* 6 */ },
   33860             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 128 /* 7 */ },
   33861             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 256 /* 8 */ },
   33862             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33863             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33864             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33865             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33866             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33867             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33868             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33869             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33870             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33871             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33872             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33873             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33874             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33875             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33876             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33877             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33878             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 64 /* 6 */ },
   33879             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 128 /* 7 */ },
   33880             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 256 /* 8 */ },
   33881             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 512 /* 9 */ },
   33882             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33883             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 128 /* 7 */ },
   33884             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 256 /* 8 */ },
   33885             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 512 /* 9 */ },
   33886             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   33887             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33888             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmOffset, 128 /* 7 */ },
   33889             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmGLC, 256 /* 8 */ },
   33890             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmSLC, 512 /* 9 */ },
   33891             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   33892             :   { Feature_HasPackedD16VMem|Feature_isVI, 12083 /* tbuffer_store_format_d16_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   33893             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   33894             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   33895             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   33896             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   33897             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33898             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   33899             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   33900             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   33901             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   33902             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33903             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33904             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33905             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33906             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33907             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33908             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33909             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33910             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33911             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33912             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33913             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33914             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33915             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33916             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33917             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33918             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   33919             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   33920             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   33921             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   33922             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33923             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   33924             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   33925             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   33926             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   33927             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33928             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   33929             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   33930             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   33931             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   33932             :   { Feature_HasPackedD16VMem|Feature_isVI, 12111 /* tbuffer_store_format_d16_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   33933             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   33934             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   33935             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   33936             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   33937             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33938             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   33939             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   33940             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   33941             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   33942             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33943             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33944             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33945             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33946             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33947             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33948             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33949             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33950             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33951             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33952             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33953             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33954             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33955             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33956             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33957             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33958             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   33959             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   33960             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   33961             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   33962             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33963             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   33964             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   33965             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   33966             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   33967             :   { Feature_HasUnpackedD16VMem|Feature_HasUnpackedD16VMem, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33968             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   33969             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   33970             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   33971             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   33972             :   { Feature_HasPackedD16VMem|Feature_isVI, 12140 /* tbuffer_store_format_d16_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   33973             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   33974             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   33975             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   33976             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   33977             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33978             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 32 /* 5 */ },
   33979             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 64 /* 6 */ },
   33980             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 128 /* 7 */ },
   33981             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 256 /* 8 */ },
   33982             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33983             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33984             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33985             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33986             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33987             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33988             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33989             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33990             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33991             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33992             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33993             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33994             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   33995             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   33996             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   33997             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   33998             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   33999             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   34000             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   34001             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   34002             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   34003             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 64 /* 6 */ },
   34004             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 128 /* 7 */ },
   34005             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 256 /* 8 */ },
   34006             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 512 /* 9 */ },
   34007             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   34008             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 128 /* 7 */ },
   34009             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 256 /* 8 */ },
   34010             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 512 /* 9 */ },
   34011             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 1024 /* 10 */ },
   34012             :   { Feature_isGCN|Feature_isSICI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   34013             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmOffset, 128 /* 7 */ },
   34014             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmGLC, 256 /* 8 */ },
   34015             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmSLC, 512 /* 9 */ },
   34016             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmTFE, 1024 /* 10 */ },
   34017             :   { Feature_isGCN|Feature_isVI, 12170 /* tbuffer_store_format_x */, MCK_ImmFORMAT, 8 /* 3 */ },
   34018             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   34019             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   34020             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   34021             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   34022             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34023             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 32 /* 5 */ },
   34024             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 64 /* 6 */ },
   34025             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 128 /* 7 */ },
   34026             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 256 /* 8 */ },
   34027             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34028             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   34029             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   34030             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   34031             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   34032             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34033             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   34034             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   34035             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   34036             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   34037             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34038             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   34039             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   34040             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   34041             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   34042             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34043             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   34044             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   34045             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   34046             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   34047             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34048             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 64 /* 6 */ },
   34049             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 128 /* 7 */ },
   34050             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 256 /* 8 */ },
   34051             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 512 /* 9 */ },
   34052             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34053             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 128 /* 7 */ },
   34054             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 256 /* 8 */ },
   34055             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 512 /* 9 */ },
   34056             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   34057             :   { Feature_isGCN|Feature_isSICI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34058             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmOffset, 128 /* 7 */ },
   34059             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmGLC, 256 /* 8 */ },
   34060             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmSLC, 512 /* 9 */ },
   34061             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmTFE, 1024 /* 10 */ },
   34062             :   { Feature_isGCN|Feature_isVI, 12193 /* tbuffer_store_format_xy */, MCK_ImmFORMAT, 8 /* 3 */ },
   34063             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   34064             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   34065             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   34066             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   34067             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34068             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 32 /* 5 */ },
   34069             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 64 /* 6 */ },
   34070             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 128 /* 7 */ },
   34071             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 256 /* 8 */ },
   34072             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34073             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   34074             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   34075             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   34076             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   34077             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34078             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   34079             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   34080             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   34081             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   34082             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34083             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   34084             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   34085             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   34086             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   34087             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34088             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   34089             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   34090             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   34091             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   34092             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34093             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 64 /* 6 */ },
   34094             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 128 /* 7 */ },
   34095             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 256 /* 8 */ },
   34096             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 512 /* 9 */ },
   34097             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34098             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   34099             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   34100             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   34101             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   34102             :   { Feature_isGCN|Feature_isSICI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34103             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmOffset, 128 /* 7 */ },
   34104             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmGLC, 256 /* 8 */ },
   34105             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmSLC, 512 /* 9 */ },
   34106             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmTFE, 1024 /* 10 */ },
   34107             :   { Feature_isGCN|Feature_isVI, 12217 /* tbuffer_store_format_xyz */, MCK_ImmFORMAT, 8 /* 3 */ },
   34108             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   34109             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   34110             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   34111             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   34112             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34113             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 32 /* 5 */ },
   34114             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 64 /* 6 */ },
   34115             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 128 /* 7 */ },
   34116             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 256 /* 8 */ },
   34117             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34118             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   34119             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   34120             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   34121             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   34122             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34123             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   34124             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   34125             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   34126             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   34127             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34128             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   34129             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   34130             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   34131             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   34132             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34133             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   34134             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   34135             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   34136             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   34137             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34138             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 64 /* 6 */ },
   34139             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 128 /* 7 */ },
   34140             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 256 /* 8 */ },
   34141             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 512 /* 9 */ },
   34142             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34143             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   34144             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   34145             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   34146             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   34147             :   { Feature_isGCN|Feature_isSICI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34148             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmOffset, 128 /* 7 */ },
   34149             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmGLC, 256 /* 8 */ },
   34150             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmSLC, 512 /* 9 */ },
   34151             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmTFE, 1024 /* 10 */ },
   34152             :   { Feature_isGCN|Feature_isVI, 12242 /* tbuffer_store_format_xyzw */, MCK_ImmFORMAT, 8 /* 3 */ },
   34153             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmDPPCtrl, 16 /* 4 */ },
   34154             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmRowMask, 32 /* 5 */ },
   34155             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmBankMask, 64 /* 6 */ },
   34156             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmBoundCtrl, 128 /* 7 */ },
   34157             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   34158             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   34159             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   34160             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   34161             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   34162             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12279 /* v_add_co_u32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   34163             :   { Feature_Has16BitInsts|Feature_isVI, 12292 /* v_add_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34164             :   { Feature_Has16BitInsts|Feature_isVI, 12292 /* v_add_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   34165             :   { Feature_Has16BitInsts|Feature_isVI, 12292 /* v_add_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34166             :   { Feature_HasDPP|Feature_HasDPP, 12292 /* v_add_f16 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   34167             :   { Feature_HasDPP|Feature_HasDPP, 12292 /* v_add_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   34168             :   { Feature_HasDPP|Feature_HasDPP, 12292 /* v_add_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   34169             :   { Feature_HasDPP|Feature_HasDPP, 12292 /* v_add_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   34170             :   { Feature_HasDPP|Feature_HasDPP, 12292 /* v_add_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   34171             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12292 /* v_add_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34172             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12292 /* v_add_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34173             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12292 /* v_add_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34174             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12292 /* v_add_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34175             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12292 /* v_add_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34176             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12292 /* v_add_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34177             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12292 /* v_add_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34178             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12292 /* v_add_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   34179             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12292 /* v_add_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34180             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12292 /* v_add_f16 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   34181             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12292 /* v_add_f16 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   34182             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12292 /* v_add_f16 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   34183             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12292 /* v_add_f16 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   34184             :   { Feature_isGCN|Feature_isSICI, 12302 /* v_add_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34185             :   { Feature_isGCN|Feature_isSICI, 12302 /* v_add_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   34186             :   { Feature_isGCN|Feature_isSICI, 12302 /* v_add_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34187             :   { Feature_isGCN|Feature_isVI, 12302 /* v_add_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34188             :   { Feature_isGCN|Feature_isVI, 12302 /* v_add_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   34189             :   { Feature_isGCN|Feature_isVI, 12302 /* v_add_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34190             :   { Feature_HasDPP|Feature_HasDPP, 12302 /* v_add_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   34191             :   { Feature_HasDPP|Feature_HasDPP, 12302 /* v_add_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   34192             :   { Feature_HasDPP|Feature_HasDPP, 12302 /* v_add_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   34193             :   { Feature_HasDPP|Feature_HasDPP, 12302 /* v_add_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   34194             :   { Feature_HasDPP|Feature_HasDPP, 12302 /* v_add_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   34195             :   { Feature_isGCN|Feature_HasSDWA, 12302 /* v_add_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34196             :   { Feature_isGCN|Feature_HasSDWA, 12302 /* v_add_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34197             :   { Feature_isGCN|Feature_HasSDWA, 12302 /* v_add_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34198             :   { Feature_isGCN|Feature_HasSDWA, 12302 /* v_add_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34199             :   { Feature_isGCN|Feature_HasSDWA, 12302 /* v_add_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34200             :   { Feature_isGCN|Feature_HasSDWA, 12302 /* v_add_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34201             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12302 /* v_add_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34202             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12302 /* v_add_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   34203             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12302 /* v_add_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34204             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12302 /* v_add_f32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   34205             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12302 /* v_add_f32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   34206             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12302 /* v_add_f32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   34207             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12302 /* v_add_f32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   34208             :   { Feature_isGCN|Feature_isSICI, 12312 /* v_add_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34209             :   { Feature_isGCN|Feature_isSICI, 12312 /* v_add_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   34210             :   { Feature_isGCN|Feature_isSICI, 12312 /* v_add_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34211             :   { Feature_isGCN|Feature_isVI, 12312 /* v_add_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34212             :   { Feature_isGCN|Feature_isVI, 12312 /* v_add_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   34213             :   { Feature_isGCN|Feature_isVI, 12312 /* v_add_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34214             :   { Feature_isGFX9|Feature_isVI, 12322 /* v_add_i16 */, MCK_ImmClampSI, 16 /* 4 */ },
   34215             :   { Feature_isGFX9|Feature_isVI, 12322 /* v_add_i16 */, MCK_ImmOpSel, 8 /* 3 */ },
   34216             :   { Feature_HasDPP|Feature_HasDPP, 12357 /* v_add_u16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   34217             :   { Feature_HasDPP|Feature_HasDPP, 12357 /* v_add_u16 */, MCK_ImmRowMask, 16 /* 4 */ },
   34218             :   { Feature_HasDPP|Feature_HasDPP, 12357 /* v_add_u16 */, MCK_ImmBankMask, 32 /* 5 */ },
   34219             :   { Feature_HasDPP|Feature_HasDPP, 12357 /* v_add_u16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   34220             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12357 /* v_add_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34221             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12357 /* v_add_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34222             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12357 /* v_add_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34223             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12357 /* v_add_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34224             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12357 /* v_add_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34225             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12357 /* v_add_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34226             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12357 /* v_add_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34227             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12357 /* v_add_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34228             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12357 /* v_add_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34229             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12357 /* v_add_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34230             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12357 /* v_add_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34231             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12357 /* v_add_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34232             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   34233             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmRowMask, 16 /* 4 */ },
   34234             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmBankMask, 32 /* 5 */ },
   34235             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   34236             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmDPPCtrl, 16 /* 4 */ },
   34237             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmRowMask, 32 /* 5 */ },
   34238             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmBankMask, 64 /* 6 */ },
   34239             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmBoundCtrl, 128 /* 7 */ },
   34240             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34241             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34242             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34243             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34244             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34245             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12367 /* v_add_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34246             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   34247             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   34248             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   34249             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   34250             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   34251             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12367 /* v_add_u32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   34252             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmDPPCtrl, 32 /* 5 */ },
   34253             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmRowMask, 64 /* 6 */ },
   34254             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmBankMask, 128 /* 7 */ },
   34255             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmBoundCtrl, 256 /* 8 */ },
   34256             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   34257             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   34258             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmSDWADstSel, 64 /* 6 */ },
   34259             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmSDWASrc0Sel, 256 /* 8 */ },
   34260             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmSDWASrc1Sel, 512 /* 9 */ },
   34261             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 12377 /* v_addc_co_u32 */, MCK_ImmSDWADstUnused, 128 /* 7 */ },
   34262             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmDPPCtrl, 32 /* 5 */ },
   34263             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmRowMask, 64 /* 6 */ },
   34264             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmBankMask, 128 /* 7 */ },
   34265             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmBoundCtrl, 256 /* 8 */ },
   34266             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   34267             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   34268             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmSDWADstSel, 64 /* 6 */ },
   34269             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmSDWASrc0Sel, 256 /* 8 */ },
   34270             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmSDWASrc1Sel, 512 /* 9 */ },
   34271             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 12391 /* v_addc_u32 */, MCK_ImmSDWADstUnused, 128 /* 7 */ },
   34272             :   { Feature_HasDPP|Feature_HasDPP, 12433 /* v_and_b32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   34273             :   { Feature_HasDPP|Feature_HasDPP, 12433 /* v_and_b32 */, MCK_ImmRowMask, 16 /* 4 */ },
   34274             :   { Feature_HasDPP|Feature_HasDPP, 12433 /* v_and_b32 */, MCK_ImmBankMask, 32 /* 5 */ },
   34275             :   { Feature_HasDPP|Feature_HasDPP, 12433 /* v_and_b32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   34276             :   { Feature_isGCN|Feature_HasSDWA, 12433 /* v_and_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34277             :   { Feature_isGCN|Feature_HasSDWA, 12433 /* v_and_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34278             :   { Feature_isGCN|Feature_HasSDWA, 12433 /* v_and_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34279             :   { Feature_isGCN|Feature_HasSDWA, 12433 /* v_and_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34280             :   { Feature_isGCN|Feature_HasSDWA, 12433 /* v_and_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34281             :   { Feature_isGCN|Feature_HasSDWA, 12433 /* v_and_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34282             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12433 /* v_and_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34283             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12433 /* v_and_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34284             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12433 /* v_and_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34285             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12433 /* v_and_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34286             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12433 /* v_and_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34287             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12433 /* v_and_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34288             :   { Feature_HasDPP|Feature_HasDPP, 12478 /* v_ashrrev_i16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   34289             :   { Feature_HasDPP|Feature_HasDPP, 12478 /* v_ashrrev_i16 */, MCK_ImmRowMask, 16 /* 4 */ },
   34290             :   { Feature_HasDPP|Feature_HasDPP, 12478 /* v_ashrrev_i16 */, MCK_ImmBankMask, 32 /* 5 */ },
   34291             :   { Feature_HasDPP|Feature_HasDPP, 12478 /* v_ashrrev_i16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   34292             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12478 /* v_ashrrev_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34293             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12478 /* v_ashrrev_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34294             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34295             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34296             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34297             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34298             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12478 /* v_ashrrev_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34299             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12478 /* v_ashrrev_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34300             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34301             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34302             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34303             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12478 /* v_ashrrev_i16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34304             :   { Feature_HasDPP|Feature_HasDPP, 12492 /* v_ashrrev_i32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   34305             :   { Feature_HasDPP|Feature_HasDPP, 12492 /* v_ashrrev_i32 */, MCK_ImmRowMask, 16 /* 4 */ },
   34306             :   { Feature_HasDPP|Feature_HasDPP, 12492 /* v_ashrrev_i32 */, MCK_ImmBankMask, 32 /* 5 */ },
   34307             :   { Feature_HasDPP|Feature_HasDPP, 12492 /* v_ashrrev_i32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   34308             :   { Feature_isGCN|Feature_HasSDWA, 12492 /* v_ashrrev_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34309             :   { Feature_isGCN|Feature_HasSDWA, 12492 /* v_ashrrev_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34310             :   { Feature_isGCN|Feature_HasSDWA, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34311             :   { Feature_isGCN|Feature_HasSDWA, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34312             :   { Feature_isGCN|Feature_HasSDWA, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34313             :   { Feature_isGCN|Feature_HasSDWA, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34314             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12492 /* v_ashrrev_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34315             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12492 /* v_ashrrev_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34316             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34317             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34318             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   34319             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12492 /* v_ashrrev_i32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34320             :   { Feature_HasDPP|Feature_HasDPP, 12575 /* v_bfrev_b32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   34321             :   { Feature_HasDPP|Feature_HasDPP, 12575 /* v_bfrev_b32 */, MCK_ImmRowMask, 8 /* 3 */ },
   34322             :   { Feature_HasDPP|Feature_HasDPP, 12575 /* v_bfrev_b32 */, MCK_ImmBankMask, 16 /* 4 */ },
   34323             :   { Feature_HasDPP|Feature_HasDPP, 12575 /* v_bfrev_b32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   34324             :   { Feature_HasSDWA|Feature_HasSDWA, 12575 /* v_bfrev_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   34325             :   { Feature_HasSDWA|Feature_HasSDWA, 12575 /* v_bfrev_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   34326             :   { Feature_HasSDWA|Feature_HasSDWA, 12575 /* v_bfrev_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   34327             :   { Feature_HasSDWA|Feature_HasSDWA, 12575 /* v_bfrev_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   34328             :   { Feature_HasSDWA|Feature_HasSDWA, 12575 /* v_bfrev_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   34329             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12575 /* v_bfrev_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   34330             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12575 /* v_bfrev_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   34331             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12575 /* v_bfrev_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   34332             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12575 /* v_bfrev_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   34333             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12575 /* v_bfrev_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   34334             :   { Feature_Has16BitInsts|Feature_isVI, 12587 /* v_ceil_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   34335             :   { Feature_Has16BitInsts|Feature_isVI, 12587 /* v_ceil_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   34336             :   { Feature_Has16BitInsts|Feature_isVI, 12587 /* v_ceil_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   34337             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12587 /* v_ceil_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   34338             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12587 /* v_ceil_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   34339             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12587 /* v_ceil_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   34340             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12587 /* v_ceil_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   34341             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12587 /* v_ceil_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   34342             :   { Feature_HasDPP|Feature_HasDPP, 12587 /* v_ceil_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   34343             :   { Feature_HasDPP|Feature_HasDPP, 12587 /* v_ceil_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   34344             :   { Feature_HasDPP|Feature_HasDPP, 12587 /* v_ceil_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   34345             :   { Feature_HasDPP|Feature_HasDPP, 12587 /* v_ceil_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   34346             :   { Feature_HasDPP|Feature_HasDPP, 12587 /* v_ceil_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   34347             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12587 /* v_ceil_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   34348             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12587 /* v_ceil_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   34349             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12587 /* v_ceil_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   34350             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12587 /* v_ceil_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34351             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12587 /* v_ceil_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34352             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12587 /* v_ceil_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34353             :   { Feature_isGCN|Feature_isSICI, 12598 /* v_ceil_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   34354             :   { Feature_isGCN|Feature_isSICI, 12598 /* v_ceil_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   34355             :   { Feature_isGCN|Feature_isSICI, 12598 /* v_ceil_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   34356             :   { Feature_isGCN|Feature_isVI, 12598 /* v_ceil_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   34357             :   { Feature_isGCN|Feature_isVI, 12598 /* v_ceil_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   34358             :   { Feature_isGCN|Feature_isVI, 12598 /* v_ceil_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   34359             :   { Feature_HasSDWA|Feature_HasSDWA, 12598 /* v_ceil_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   34360             :   { Feature_HasSDWA|Feature_HasSDWA, 12598 /* v_ceil_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   34361             :   { Feature_HasSDWA|Feature_HasSDWA, 12598 /* v_ceil_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   34362             :   { Feature_HasSDWA|Feature_HasSDWA, 12598 /* v_ceil_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   34363             :   { Feature_HasSDWA|Feature_HasSDWA, 12598 /* v_ceil_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   34364             :   { Feature_HasDPP|Feature_HasDPP, 12598 /* v_ceil_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   34365             :   { Feature_HasDPP|Feature_HasDPP, 12598 /* v_ceil_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   34366             :   { Feature_HasDPP|Feature_HasDPP, 12598 /* v_ceil_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   34367             :   { Feature_HasDPP|Feature_HasDPP, 12598 /* v_ceil_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   34368             :   { Feature_HasDPP|Feature_HasDPP, 12598 /* v_ceil_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   34369             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12598 /* v_ceil_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   34370             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12598 /* v_ceil_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   34371             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12598 /* v_ceil_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   34372             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12598 /* v_ceil_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   34373             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12598 /* v_ceil_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   34374             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12598 /* v_ceil_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   34375             :   { Feature_isCIVI|Feature_isCIOnly, 12609 /* v_ceil_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   34376             :   { Feature_isCIVI|Feature_isCIOnly, 12609 /* v_ceil_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   34377             :   { Feature_isCIVI|Feature_isCIOnly, 12609 /* v_ceil_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   34378             :   { Feature_isCIVI|Feature_isVI, 12609 /* v_ceil_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   34379             :   { Feature_isCIVI|Feature_isVI, 12609 /* v_ceil_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   34380             :   { Feature_isCIVI|Feature_isVI, 12609 /* v_ceil_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   34381             :   { Feature_isGCN|Feature_isVI, 12630 /* v_cmp_class_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   34382             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12630 /* v_cmp_class_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   34383             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12630 /* v_cmp_class_f16 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   34384             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12630 /* v_cmp_class_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34385             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12630 /* v_cmp_class_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34386             :   { Feature_HasSDWA|Feature_HasSDWA, 12630 /* v_cmp_class_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   34387             :   { Feature_HasSDWA|Feature_HasSDWA, 12630 /* v_cmp_class_f16 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   34388             :   { Feature_HasSDWA|Feature_HasSDWA, 12630 /* v_cmp_class_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34389             :   { Feature_HasSDWA|Feature_HasSDWA, 12630 /* v_cmp_class_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34390             :   { Feature_HasSDWA|Feature_HasSDWA, 12630 /* v_cmp_class_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34391             :   { Feature_isGCN|Feature_isSICI, 12666 /* v_cmp_class_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   34392             :   { Feature_isGCN|Feature_isVI, 12666 /* v_cmp_class_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   34393             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12666 /* v_cmp_class_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   34394             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12666 /* v_cmp_class_f32 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   34395             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12666 /* v_cmp_class_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34396             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12666 /* v_cmp_class_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34397             :   { Feature_HasSDWA|Feature_HasSDWA, 12666 /* v_cmp_class_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   34398             :   { Feature_HasSDWA|Feature_HasSDWA, 12666 /* v_cmp_class_f32 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   34399             :   { Feature_HasSDWA|Feature_HasSDWA, 12666 /* v_cmp_class_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34400             :   { Feature_HasSDWA|Feature_HasSDWA, 12666 /* v_cmp_class_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34401             :   { Feature_HasSDWA|Feature_HasSDWA, 12666 /* v_cmp_class_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34402             :   { Feature_isGCN|Feature_isSICI, 12702 /* v_cmp_class_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   34403             :   { Feature_isGCN|Feature_isVI, 12702 /* v_cmp_class_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   34404             :   { Feature_Has16BitInsts|Feature_isVI, 12738 /* v_cmp_eq_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34405             :   { Feature_Has16BitInsts|Feature_isVI, 12738 /* v_cmp_eq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34406             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12738 /* v_cmp_eq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34407             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12738 /* v_cmp_eq_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34408             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12738 /* v_cmp_eq_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34409             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12738 /* v_cmp_eq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34410             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12738 /* v_cmp_eq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34411             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12738 /* v_cmp_eq_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34412             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12738 /* v_cmp_eq_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34413             :   { Feature_isGCN|Feature_isSICI, 12768 /* v_cmp_eq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34414             :   { Feature_isGCN|Feature_isSICI, 12768 /* v_cmp_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34415             :   { Feature_isGCN|Feature_isVI, 12768 /* v_cmp_eq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34416             :   { Feature_isGCN|Feature_isVI, 12768 /* v_cmp_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34417             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12768 /* v_cmp_eq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34418             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12768 /* v_cmp_eq_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34419             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12768 /* v_cmp_eq_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34420             :   { Feature_HasSDWA|Feature_HasSDWA, 12768 /* v_cmp_eq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34421             :   { Feature_HasSDWA|Feature_HasSDWA, 12768 /* v_cmp_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34422             :   { Feature_HasSDWA|Feature_HasSDWA, 12768 /* v_cmp_eq_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34423             :   { Feature_HasSDWA|Feature_HasSDWA, 12768 /* v_cmp_eq_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34424             :   { Feature_isGCN|Feature_isSICI, 12798 /* v_cmp_eq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34425             :   { Feature_isGCN|Feature_isSICI, 12798 /* v_cmp_eq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34426             :   { Feature_isGCN|Feature_isVI, 12798 /* v_cmp_eq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34427             :   { Feature_isGCN|Feature_isVI, 12798 /* v_cmp_eq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34428             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12828 /* v_cmp_eq_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34429             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12828 /* v_cmp_eq_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34430             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12828 /* v_cmp_eq_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34431             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12828 /* v_cmp_eq_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34432             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12828 /* v_cmp_eq_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34433             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12828 /* v_cmp_eq_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34434             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12828 /* v_cmp_eq_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34435             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12858 /* v_cmp_eq_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34436             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12858 /* v_cmp_eq_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34437             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12858 /* v_cmp_eq_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34438             :   { Feature_HasSDWA|Feature_HasSDWA, 12858 /* v_cmp_eq_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34439             :   { Feature_HasSDWA|Feature_HasSDWA, 12858 /* v_cmp_eq_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34440             :   { Feature_HasSDWA|Feature_HasSDWA, 12858 /* v_cmp_eq_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34441             :   { Feature_HasSDWA|Feature_HasSDWA, 12858 /* v_cmp_eq_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34442             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12918 /* v_cmp_eq_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34443             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12918 /* v_cmp_eq_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34444             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12918 /* v_cmp_eq_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34445             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12918 /* v_cmp_eq_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34446             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12918 /* v_cmp_eq_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34447             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12918 /* v_cmp_eq_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34448             :   { Feature_Has16BitInsts|Feature_HasSDWA, 12918 /* v_cmp_eq_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34449             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12948 /* v_cmp_eq_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34450             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12948 /* v_cmp_eq_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34451             :   { Feature_HasSDWA9|Feature_HasSDWA9, 12948 /* v_cmp_eq_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34452             :   { Feature_HasSDWA|Feature_HasSDWA, 12948 /* v_cmp_eq_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34453             :   { Feature_HasSDWA|Feature_HasSDWA, 12948 /* v_cmp_eq_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34454             :   { Feature_HasSDWA|Feature_HasSDWA, 12948 /* v_cmp_eq_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34455             :   { Feature_HasSDWA|Feature_HasSDWA, 12948 /* v_cmp_eq_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34456             :   { Feature_Has16BitInsts|Feature_isVI, 13008 /* v_cmp_f_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34457             :   { Feature_Has16BitInsts|Feature_isVI, 13008 /* v_cmp_f_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34458             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13008 /* v_cmp_f_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34459             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13008 /* v_cmp_f_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34460             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13008 /* v_cmp_f_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34461             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13008 /* v_cmp_f_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34462             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13008 /* v_cmp_f_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34463             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13008 /* v_cmp_f_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34464             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13008 /* v_cmp_f_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34465             :   { Feature_isGCN|Feature_isSICI, 13036 /* v_cmp_f_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34466             :   { Feature_isGCN|Feature_isSICI, 13036 /* v_cmp_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34467             :   { Feature_isGCN|Feature_isVI, 13036 /* v_cmp_f_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34468             :   { Feature_isGCN|Feature_isVI, 13036 /* v_cmp_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34469             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13036 /* v_cmp_f_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34470             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13036 /* v_cmp_f_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34471             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13036 /* v_cmp_f_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34472             :   { Feature_HasSDWA|Feature_HasSDWA, 13036 /* v_cmp_f_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34473             :   { Feature_HasSDWA|Feature_HasSDWA, 13036 /* v_cmp_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34474             :   { Feature_HasSDWA|Feature_HasSDWA, 13036 /* v_cmp_f_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34475             :   { Feature_HasSDWA|Feature_HasSDWA, 13036 /* v_cmp_f_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34476             :   { Feature_isGCN|Feature_isSICI, 13064 /* v_cmp_f_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34477             :   { Feature_isGCN|Feature_isSICI, 13064 /* v_cmp_f_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34478             :   { Feature_isGCN|Feature_isVI, 13064 /* v_cmp_f_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34479             :   { Feature_isGCN|Feature_isVI, 13064 /* v_cmp_f_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34480             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13092 /* v_cmp_f_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34481             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13092 /* v_cmp_f_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34482             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13092 /* v_cmp_f_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34483             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13092 /* v_cmp_f_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34484             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13092 /* v_cmp_f_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34485             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13092 /* v_cmp_f_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34486             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13092 /* v_cmp_f_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34487             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13120 /* v_cmp_f_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34488             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13120 /* v_cmp_f_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34489             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13120 /* v_cmp_f_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34490             :   { Feature_HasSDWA|Feature_HasSDWA, 13120 /* v_cmp_f_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34491             :   { Feature_HasSDWA|Feature_HasSDWA, 13120 /* v_cmp_f_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34492             :   { Feature_HasSDWA|Feature_HasSDWA, 13120 /* v_cmp_f_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34493             :   { Feature_HasSDWA|Feature_HasSDWA, 13120 /* v_cmp_f_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34494             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13176 /* v_cmp_f_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34495             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13176 /* v_cmp_f_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34496             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13176 /* v_cmp_f_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34497             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13176 /* v_cmp_f_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34498             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13176 /* v_cmp_f_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34499             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13176 /* v_cmp_f_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34500             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13176 /* v_cmp_f_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34501             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13204 /* v_cmp_f_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34502             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13204 /* v_cmp_f_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34503             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13204 /* v_cmp_f_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34504             :   { Feature_HasSDWA|Feature_HasSDWA, 13204 /* v_cmp_f_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34505             :   { Feature_HasSDWA|Feature_HasSDWA, 13204 /* v_cmp_f_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34506             :   { Feature_HasSDWA|Feature_HasSDWA, 13204 /* v_cmp_f_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34507             :   { Feature_HasSDWA|Feature_HasSDWA, 13204 /* v_cmp_f_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34508             :   { Feature_Has16BitInsts|Feature_isVI, 13260 /* v_cmp_ge_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34509             :   { Feature_Has16BitInsts|Feature_isVI, 13260 /* v_cmp_ge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34510             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13260 /* v_cmp_ge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34511             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13260 /* v_cmp_ge_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34512             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13260 /* v_cmp_ge_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34513             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13260 /* v_cmp_ge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34514             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13260 /* v_cmp_ge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34515             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13260 /* v_cmp_ge_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34516             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13260 /* v_cmp_ge_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34517             :   { Feature_isGCN|Feature_isSICI, 13290 /* v_cmp_ge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34518             :   { Feature_isGCN|Feature_isSICI, 13290 /* v_cmp_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34519             :   { Feature_isGCN|Feature_isVI, 13290 /* v_cmp_ge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34520             :   { Feature_isGCN|Feature_isVI, 13290 /* v_cmp_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34521             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13290 /* v_cmp_ge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34522             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13290 /* v_cmp_ge_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34523             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13290 /* v_cmp_ge_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34524             :   { Feature_HasSDWA|Feature_HasSDWA, 13290 /* v_cmp_ge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34525             :   { Feature_HasSDWA|Feature_HasSDWA, 13290 /* v_cmp_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34526             :   { Feature_HasSDWA|Feature_HasSDWA, 13290 /* v_cmp_ge_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34527             :   { Feature_HasSDWA|Feature_HasSDWA, 13290 /* v_cmp_ge_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34528             :   { Feature_isGCN|Feature_isSICI, 13320 /* v_cmp_ge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34529             :   { Feature_isGCN|Feature_isSICI, 13320 /* v_cmp_ge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34530             :   { Feature_isGCN|Feature_isVI, 13320 /* v_cmp_ge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34531             :   { Feature_isGCN|Feature_isVI, 13320 /* v_cmp_ge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34532             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13350 /* v_cmp_ge_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34533             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13350 /* v_cmp_ge_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34534             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13350 /* v_cmp_ge_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34535             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13350 /* v_cmp_ge_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34536             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13350 /* v_cmp_ge_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34537             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13350 /* v_cmp_ge_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34538             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13350 /* v_cmp_ge_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34539             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13380 /* v_cmp_ge_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34540             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13380 /* v_cmp_ge_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34541             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13380 /* v_cmp_ge_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34542             :   { Feature_HasSDWA|Feature_HasSDWA, 13380 /* v_cmp_ge_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34543             :   { Feature_HasSDWA|Feature_HasSDWA, 13380 /* v_cmp_ge_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34544             :   { Feature_HasSDWA|Feature_HasSDWA, 13380 /* v_cmp_ge_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34545             :   { Feature_HasSDWA|Feature_HasSDWA, 13380 /* v_cmp_ge_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34546             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13440 /* v_cmp_ge_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34547             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13440 /* v_cmp_ge_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34548             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13440 /* v_cmp_ge_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34549             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13440 /* v_cmp_ge_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34550             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13440 /* v_cmp_ge_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34551             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13440 /* v_cmp_ge_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34552             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13440 /* v_cmp_ge_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34553             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13470 /* v_cmp_ge_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34554             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13470 /* v_cmp_ge_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34555             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13470 /* v_cmp_ge_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34556             :   { Feature_HasSDWA|Feature_HasSDWA, 13470 /* v_cmp_ge_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34557             :   { Feature_HasSDWA|Feature_HasSDWA, 13470 /* v_cmp_ge_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34558             :   { Feature_HasSDWA|Feature_HasSDWA, 13470 /* v_cmp_ge_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34559             :   { Feature_HasSDWA|Feature_HasSDWA, 13470 /* v_cmp_ge_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34560             :   { Feature_Has16BitInsts|Feature_isVI, 13530 /* v_cmp_gt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34561             :   { Feature_Has16BitInsts|Feature_isVI, 13530 /* v_cmp_gt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34562             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13530 /* v_cmp_gt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34563             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13530 /* v_cmp_gt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34564             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13530 /* v_cmp_gt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34565             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13530 /* v_cmp_gt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34566             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13530 /* v_cmp_gt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34567             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13530 /* v_cmp_gt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34568             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13530 /* v_cmp_gt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34569             :   { Feature_isGCN|Feature_isSICI, 13560 /* v_cmp_gt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34570             :   { Feature_isGCN|Feature_isSICI, 13560 /* v_cmp_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34571             :   { Feature_isGCN|Feature_isVI, 13560 /* v_cmp_gt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34572             :   { Feature_isGCN|Feature_isVI, 13560 /* v_cmp_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34573             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13560 /* v_cmp_gt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34574             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13560 /* v_cmp_gt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34575             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13560 /* v_cmp_gt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34576             :   { Feature_HasSDWA|Feature_HasSDWA, 13560 /* v_cmp_gt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34577             :   { Feature_HasSDWA|Feature_HasSDWA, 13560 /* v_cmp_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34578             :   { Feature_HasSDWA|Feature_HasSDWA, 13560 /* v_cmp_gt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34579             :   { Feature_HasSDWA|Feature_HasSDWA, 13560 /* v_cmp_gt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34580             :   { Feature_isGCN|Feature_isSICI, 13590 /* v_cmp_gt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34581             :   { Feature_isGCN|Feature_isSICI, 13590 /* v_cmp_gt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34582             :   { Feature_isGCN|Feature_isVI, 13590 /* v_cmp_gt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34583             :   { Feature_isGCN|Feature_isVI, 13590 /* v_cmp_gt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34584             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13620 /* v_cmp_gt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34585             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13620 /* v_cmp_gt_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34586             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13620 /* v_cmp_gt_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34587             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13620 /* v_cmp_gt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34588             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13620 /* v_cmp_gt_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34589             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13620 /* v_cmp_gt_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34590             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13620 /* v_cmp_gt_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34591             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13650 /* v_cmp_gt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34592             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13650 /* v_cmp_gt_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34593             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13650 /* v_cmp_gt_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34594             :   { Feature_HasSDWA|Feature_HasSDWA, 13650 /* v_cmp_gt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34595             :   { Feature_HasSDWA|Feature_HasSDWA, 13650 /* v_cmp_gt_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34596             :   { Feature_HasSDWA|Feature_HasSDWA, 13650 /* v_cmp_gt_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34597             :   { Feature_HasSDWA|Feature_HasSDWA, 13650 /* v_cmp_gt_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34598             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13710 /* v_cmp_gt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34599             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13710 /* v_cmp_gt_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34600             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13710 /* v_cmp_gt_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34601             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13710 /* v_cmp_gt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34602             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13710 /* v_cmp_gt_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34603             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13710 /* v_cmp_gt_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34604             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13710 /* v_cmp_gt_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34605             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13740 /* v_cmp_gt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34606             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13740 /* v_cmp_gt_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34607             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13740 /* v_cmp_gt_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34608             :   { Feature_HasSDWA|Feature_HasSDWA, 13740 /* v_cmp_gt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34609             :   { Feature_HasSDWA|Feature_HasSDWA, 13740 /* v_cmp_gt_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34610             :   { Feature_HasSDWA|Feature_HasSDWA, 13740 /* v_cmp_gt_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34611             :   { Feature_HasSDWA|Feature_HasSDWA, 13740 /* v_cmp_gt_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34612             :   { Feature_Has16BitInsts|Feature_isVI, 13800 /* v_cmp_le_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34613             :   { Feature_Has16BitInsts|Feature_isVI, 13800 /* v_cmp_le_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34614             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13800 /* v_cmp_le_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34615             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13800 /* v_cmp_le_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34616             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13800 /* v_cmp_le_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34617             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13800 /* v_cmp_le_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34618             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13800 /* v_cmp_le_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34619             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13800 /* v_cmp_le_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34620             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13800 /* v_cmp_le_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34621             :   { Feature_isGCN|Feature_isSICI, 13830 /* v_cmp_le_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34622             :   { Feature_isGCN|Feature_isSICI, 13830 /* v_cmp_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34623             :   { Feature_isGCN|Feature_isVI, 13830 /* v_cmp_le_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34624             :   { Feature_isGCN|Feature_isVI, 13830 /* v_cmp_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34625             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13830 /* v_cmp_le_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34626             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13830 /* v_cmp_le_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34627             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13830 /* v_cmp_le_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34628             :   { Feature_HasSDWA|Feature_HasSDWA, 13830 /* v_cmp_le_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34629             :   { Feature_HasSDWA|Feature_HasSDWA, 13830 /* v_cmp_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34630             :   { Feature_HasSDWA|Feature_HasSDWA, 13830 /* v_cmp_le_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34631             :   { Feature_HasSDWA|Feature_HasSDWA, 13830 /* v_cmp_le_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34632             :   { Feature_isGCN|Feature_isSICI, 13860 /* v_cmp_le_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34633             :   { Feature_isGCN|Feature_isSICI, 13860 /* v_cmp_le_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34634             :   { Feature_isGCN|Feature_isVI, 13860 /* v_cmp_le_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34635             :   { Feature_isGCN|Feature_isVI, 13860 /* v_cmp_le_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34636             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13890 /* v_cmp_le_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34637             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13890 /* v_cmp_le_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34638             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13890 /* v_cmp_le_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34639             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13890 /* v_cmp_le_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34640             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13890 /* v_cmp_le_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34641             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13890 /* v_cmp_le_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34642             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13890 /* v_cmp_le_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34643             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13920 /* v_cmp_le_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34644             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13920 /* v_cmp_le_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34645             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13920 /* v_cmp_le_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34646             :   { Feature_HasSDWA|Feature_HasSDWA, 13920 /* v_cmp_le_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34647             :   { Feature_HasSDWA|Feature_HasSDWA, 13920 /* v_cmp_le_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34648             :   { Feature_HasSDWA|Feature_HasSDWA, 13920 /* v_cmp_le_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34649             :   { Feature_HasSDWA|Feature_HasSDWA, 13920 /* v_cmp_le_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34650             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13980 /* v_cmp_le_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34651             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13980 /* v_cmp_le_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34652             :   { Feature_HasSDWA9|Feature_HasSDWA9, 13980 /* v_cmp_le_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34653             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13980 /* v_cmp_le_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34654             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13980 /* v_cmp_le_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34655             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13980 /* v_cmp_le_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34656             :   { Feature_Has16BitInsts|Feature_HasSDWA, 13980 /* v_cmp_le_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34657             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14010 /* v_cmp_le_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34658             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14010 /* v_cmp_le_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34659             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14010 /* v_cmp_le_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34660             :   { Feature_HasSDWA|Feature_HasSDWA, 14010 /* v_cmp_le_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34661             :   { Feature_HasSDWA|Feature_HasSDWA, 14010 /* v_cmp_le_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34662             :   { Feature_HasSDWA|Feature_HasSDWA, 14010 /* v_cmp_le_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34663             :   { Feature_HasSDWA|Feature_HasSDWA, 14010 /* v_cmp_le_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34664             :   { Feature_Has16BitInsts|Feature_isVI, 14070 /* v_cmp_lg_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34665             :   { Feature_Has16BitInsts|Feature_isVI, 14070 /* v_cmp_lg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34666             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14070 /* v_cmp_lg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34667             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14070 /* v_cmp_lg_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34668             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14070 /* v_cmp_lg_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34669             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14070 /* v_cmp_lg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34670             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14070 /* v_cmp_lg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34671             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14070 /* v_cmp_lg_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34672             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14070 /* v_cmp_lg_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34673             :   { Feature_isGCN|Feature_isSICI, 14100 /* v_cmp_lg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34674             :   { Feature_isGCN|Feature_isSICI, 14100 /* v_cmp_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34675             :   { Feature_isGCN|Feature_isVI, 14100 /* v_cmp_lg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34676             :   { Feature_isGCN|Feature_isVI, 14100 /* v_cmp_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34677             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14100 /* v_cmp_lg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34678             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14100 /* v_cmp_lg_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34679             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14100 /* v_cmp_lg_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34680             :   { Feature_HasSDWA|Feature_HasSDWA, 14100 /* v_cmp_lg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34681             :   { Feature_HasSDWA|Feature_HasSDWA, 14100 /* v_cmp_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34682             :   { Feature_HasSDWA|Feature_HasSDWA, 14100 /* v_cmp_lg_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34683             :   { Feature_HasSDWA|Feature_HasSDWA, 14100 /* v_cmp_lg_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34684             :   { Feature_isGCN|Feature_isSICI, 14130 /* v_cmp_lg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34685             :   { Feature_isGCN|Feature_isSICI, 14130 /* v_cmp_lg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34686             :   { Feature_isGCN|Feature_isVI, 14130 /* v_cmp_lg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34687             :   { Feature_isGCN|Feature_isVI, 14130 /* v_cmp_lg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34688             :   { Feature_Has16BitInsts|Feature_isVI, 14160 /* v_cmp_lt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34689             :   { Feature_Has16BitInsts|Feature_isVI, 14160 /* v_cmp_lt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34690             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14160 /* v_cmp_lt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34691             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14160 /* v_cmp_lt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34692             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14160 /* v_cmp_lt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34693             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14160 /* v_cmp_lt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34694             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14160 /* v_cmp_lt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34695             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14160 /* v_cmp_lt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34696             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14160 /* v_cmp_lt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34697             :   { Feature_isGCN|Feature_isSICI, 14190 /* v_cmp_lt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34698             :   { Feature_isGCN|Feature_isSICI, 14190 /* v_cmp_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34699             :   { Feature_isGCN|Feature_isVI, 14190 /* v_cmp_lt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34700             :   { Feature_isGCN|Feature_isVI, 14190 /* v_cmp_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34701             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14190 /* v_cmp_lt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34702             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14190 /* v_cmp_lt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34703             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14190 /* v_cmp_lt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34704             :   { Feature_HasSDWA|Feature_HasSDWA, 14190 /* v_cmp_lt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34705             :   { Feature_HasSDWA|Feature_HasSDWA, 14190 /* v_cmp_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34706             :   { Feature_HasSDWA|Feature_HasSDWA, 14190 /* v_cmp_lt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34707             :   { Feature_HasSDWA|Feature_HasSDWA, 14190 /* v_cmp_lt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34708             :   { Feature_isGCN|Feature_isSICI, 14220 /* v_cmp_lt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34709             :   { Feature_isGCN|Feature_isSICI, 14220 /* v_cmp_lt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34710             :   { Feature_isGCN|Feature_isVI, 14220 /* v_cmp_lt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34711             :   { Feature_isGCN|Feature_isVI, 14220 /* v_cmp_lt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34712             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14250 /* v_cmp_lt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34713             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14250 /* v_cmp_lt_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34714             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14250 /* v_cmp_lt_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34715             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14250 /* v_cmp_lt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34716             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14250 /* v_cmp_lt_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34717             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14250 /* v_cmp_lt_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34718             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14250 /* v_cmp_lt_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34719             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14280 /* v_cmp_lt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34720             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14280 /* v_cmp_lt_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34721             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14280 /* v_cmp_lt_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34722             :   { Feature_HasSDWA|Feature_HasSDWA, 14280 /* v_cmp_lt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34723             :   { Feature_HasSDWA|Feature_HasSDWA, 14280 /* v_cmp_lt_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34724             :   { Feature_HasSDWA|Feature_HasSDWA, 14280 /* v_cmp_lt_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34725             :   { Feature_HasSDWA|Feature_HasSDWA, 14280 /* v_cmp_lt_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34726             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14340 /* v_cmp_lt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34727             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14340 /* v_cmp_lt_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34728             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14340 /* v_cmp_lt_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34729             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14340 /* v_cmp_lt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34730             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14340 /* v_cmp_lt_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34731             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14340 /* v_cmp_lt_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34732             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14340 /* v_cmp_lt_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34733             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14370 /* v_cmp_lt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34734             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14370 /* v_cmp_lt_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34735             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14370 /* v_cmp_lt_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34736             :   { Feature_HasSDWA|Feature_HasSDWA, 14370 /* v_cmp_lt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34737             :   { Feature_HasSDWA|Feature_HasSDWA, 14370 /* v_cmp_lt_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34738             :   { Feature_HasSDWA|Feature_HasSDWA, 14370 /* v_cmp_lt_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34739             :   { Feature_HasSDWA|Feature_HasSDWA, 14370 /* v_cmp_lt_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34740             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14430 /* v_cmp_ne_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34741             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14430 /* v_cmp_ne_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34742             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14430 /* v_cmp_ne_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34743             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14430 /* v_cmp_ne_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34744             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14430 /* v_cmp_ne_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34745             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14430 /* v_cmp_ne_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34746             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14430 /* v_cmp_ne_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34747             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14460 /* v_cmp_ne_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34748             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14460 /* v_cmp_ne_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34749             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14460 /* v_cmp_ne_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34750             :   { Feature_HasSDWA|Feature_HasSDWA, 14460 /* v_cmp_ne_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34751             :   { Feature_HasSDWA|Feature_HasSDWA, 14460 /* v_cmp_ne_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34752             :   { Feature_HasSDWA|Feature_HasSDWA, 14460 /* v_cmp_ne_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34753             :   { Feature_HasSDWA|Feature_HasSDWA, 14460 /* v_cmp_ne_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34754             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14520 /* v_cmp_ne_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34755             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14520 /* v_cmp_ne_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34756             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14520 /* v_cmp_ne_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34757             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14520 /* v_cmp_ne_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34758             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14520 /* v_cmp_ne_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34759             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14520 /* v_cmp_ne_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34760             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14520 /* v_cmp_ne_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34761             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14550 /* v_cmp_ne_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34762             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14550 /* v_cmp_ne_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34763             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14550 /* v_cmp_ne_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34764             :   { Feature_HasSDWA|Feature_HasSDWA, 14550 /* v_cmp_ne_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34765             :   { Feature_HasSDWA|Feature_HasSDWA, 14550 /* v_cmp_ne_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34766             :   { Feature_HasSDWA|Feature_HasSDWA, 14550 /* v_cmp_ne_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34767             :   { Feature_HasSDWA|Feature_HasSDWA, 14550 /* v_cmp_ne_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34768             :   { Feature_Has16BitInsts|Feature_isVI, 14610 /* v_cmp_neq_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34769             :   { Feature_Has16BitInsts|Feature_isVI, 14610 /* v_cmp_neq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34770             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14610 /* v_cmp_neq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34771             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14610 /* v_cmp_neq_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34772             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14610 /* v_cmp_neq_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34773             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14610 /* v_cmp_neq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34774             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14610 /* v_cmp_neq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34775             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14610 /* v_cmp_neq_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34776             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14610 /* v_cmp_neq_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34777             :   { Feature_isGCN|Feature_isSICI, 14642 /* v_cmp_neq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34778             :   { Feature_isGCN|Feature_isSICI, 14642 /* v_cmp_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34779             :   { Feature_isGCN|Feature_isVI, 14642 /* v_cmp_neq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34780             :   { Feature_isGCN|Feature_isVI, 14642 /* v_cmp_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34781             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14642 /* v_cmp_neq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34782             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14642 /* v_cmp_neq_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34783             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14642 /* v_cmp_neq_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34784             :   { Feature_HasSDWA|Feature_HasSDWA, 14642 /* v_cmp_neq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34785             :   { Feature_HasSDWA|Feature_HasSDWA, 14642 /* v_cmp_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34786             :   { Feature_HasSDWA|Feature_HasSDWA, 14642 /* v_cmp_neq_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34787             :   { Feature_HasSDWA|Feature_HasSDWA, 14642 /* v_cmp_neq_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34788             :   { Feature_isGCN|Feature_isSICI, 14674 /* v_cmp_neq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34789             :   { Feature_isGCN|Feature_isSICI, 14674 /* v_cmp_neq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34790             :   { Feature_isGCN|Feature_isVI, 14674 /* v_cmp_neq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34791             :   { Feature_isGCN|Feature_isVI, 14674 /* v_cmp_neq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34792             :   { Feature_Has16BitInsts|Feature_isVI, 14706 /* v_cmp_nge_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34793             :   { Feature_Has16BitInsts|Feature_isVI, 14706 /* v_cmp_nge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34794             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14706 /* v_cmp_nge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34795             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14706 /* v_cmp_nge_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34796             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14706 /* v_cmp_nge_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34797             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14706 /* v_cmp_nge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34798             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14706 /* v_cmp_nge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34799             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14706 /* v_cmp_nge_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34800             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14706 /* v_cmp_nge_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34801             :   { Feature_isGCN|Feature_isSICI, 14738 /* v_cmp_nge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34802             :   { Feature_isGCN|Feature_isSICI, 14738 /* v_cmp_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34803             :   { Feature_isGCN|Feature_isVI, 14738 /* v_cmp_nge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34804             :   { Feature_isGCN|Feature_isVI, 14738 /* v_cmp_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34805             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14738 /* v_cmp_nge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34806             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14738 /* v_cmp_nge_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34807             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14738 /* v_cmp_nge_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34808             :   { Feature_HasSDWA|Feature_HasSDWA, 14738 /* v_cmp_nge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34809             :   { Feature_HasSDWA|Feature_HasSDWA, 14738 /* v_cmp_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34810             :   { Feature_HasSDWA|Feature_HasSDWA, 14738 /* v_cmp_nge_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34811             :   { Feature_HasSDWA|Feature_HasSDWA, 14738 /* v_cmp_nge_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34812             :   { Feature_isGCN|Feature_isSICI, 14770 /* v_cmp_nge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34813             :   { Feature_isGCN|Feature_isSICI, 14770 /* v_cmp_nge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34814             :   { Feature_isGCN|Feature_isVI, 14770 /* v_cmp_nge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34815             :   { Feature_isGCN|Feature_isVI, 14770 /* v_cmp_nge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34816             :   { Feature_Has16BitInsts|Feature_isVI, 14802 /* v_cmp_ngt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34817             :   { Feature_Has16BitInsts|Feature_isVI, 14802 /* v_cmp_ngt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34818             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14802 /* v_cmp_ngt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34819             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14802 /* v_cmp_ngt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34820             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14802 /* v_cmp_ngt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34821             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14802 /* v_cmp_ngt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34822             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14802 /* v_cmp_ngt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34823             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14802 /* v_cmp_ngt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34824             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14802 /* v_cmp_ngt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34825             :   { Feature_isGCN|Feature_isSICI, 14834 /* v_cmp_ngt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34826             :   { Feature_isGCN|Feature_isSICI, 14834 /* v_cmp_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34827             :   { Feature_isGCN|Feature_isVI, 14834 /* v_cmp_ngt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34828             :   { Feature_isGCN|Feature_isVI, 14834 /* v_cmp_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34829             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14834 /* v_cmp_ngt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34830             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14834 /* v_cmp_ngt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34831             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14834 /* v_cmp_ngt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34832             :   { Feature_HasSDWA|Feature_HasSDWA, 14834 /* v_cmp_ngt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34833             :   { Feature_HasSDWA|Feature_HasSDWA, 14834 /* v_cmp_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34834             :   { Feature_HasSDWA|Feature_HasSDWA, 14834 /* v_cmp_ngt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34835             :   { Feature_HasSDWA|Feature_HasSDWA, 14834 /* v_cmp_ngt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34836             :   { Feature_isGCN|Feature_isSICI, 14866 /* v_cmp_ngt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34837             :   { Feature_isGCN|Feature_isSICI, 14866 /* v_cmp_ngt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34838             :   { Feature_isGCN|Feature_isVI, 14866 /* v_cmp_ngt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34839             :   { Feature_isGCN|Feature_isVI, 14866 /* v_cmp_ngt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34840             :   { Feature_Has16BitInsts|Feature_isVI, 14898 /* v_cmp_nle_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34841             :   { Feature_Has16BitInsts|Feature_isVI, 14898 /* v_cmp_nle_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34842             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14898 /* v_cmp_nle_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34843             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14898 /* v_cmp_nle_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34844             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14898 /* v_cmp_nle_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34845             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14898 /* v_cmp_nle_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34846             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14898 /* v_cmp_nle_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34847             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14898 /* v_cmp_nle_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34848             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14898 /* v_cmp_nle_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34849             :   { Feature_isGCN|Feature_isSICI, 14930 /* v_cmp_nle_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34850             :   { Feature_isGCN|Feature_isSICI, 14930 /* v_cmp_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34851             :   { Feature_isGCN|Feature_isVI, 14930 /* v_cmp_nle_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34852             :   { Feature_isGCN|Feature_isVI, 14930 /* v_cmp_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34853             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14930 /* v_cmp_nle_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34854             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14930 /* v_cmp_nle_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34855             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14930 /* v_cmp_nle_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34856             :   { Feature_HasSDWA|Feature_HasSDWA, 14930 /* v_cmp_nle_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34857             :   { Feature_HasSDWA|Feature_HasSDWA, 14930 /* v_cmp_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34858             :   { Feature_HasSDWA|Feature_HasSDWA, 14930 /* v_cmp_nle_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34859             :   { Feature_HasSDWA|Feature_HasSDWA, 14930 /* v_cmp_nle_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34860             :   { Feature_isGCN|Feature_isSICI, 14962 /* v_cmp_nle_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34861             :   { Feature_isGCN|Feature_isSICI, 14962 /* v_cmp_nle_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34862             :   { Feature_isGCN|Feature_isVI, 14962 /* v_cmp_nle_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34863             :   { Feature_isGCN|Feature_isVI, 14962 /* v_cmp_nle_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34864             :   { Feature_Has16BitInsts|Feature_isVI, 14994 /* v_cmp_nlg_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34865             :   { Feature_Has16BitInsts|Feature_isVI, 14994 /* v_cmp_nlg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34866             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14994 /* v_cmp_nlg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34867             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14994 /* v_cmp_nlg_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34868             :   { Feature_HasSDWA9|Feature_HasSDWA9, 14994 /* v_cmp_nlg_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34869             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14994 /* v_cmp_nlg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34870             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14994 /* v_cmp_nlg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34871             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14994 /* v_cmp_nlg_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34872             :   { Feature_Has16BitInsts|Feature_HasSDWA, 14994 /* v_cmp_nlg_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34873             :   { Feature_isGCN|Feature_isSICI, 15026 /* v_cmp_nlg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34874             :   { Feature_isGCN|Feature_isSICI, 15026 /* v_cmp_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34875             :   { Feature_isGCN|Feature_isVI, 15026 /* v_cmp_nlg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34876             :   { Feature_isGCN|Feature_isVI, 15026 /* v_cmp_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34877             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15026 /* v_cmp_nlg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34878             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15026 /* v_cmp_nlg_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34879             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15026 /* v_cmp_nlg_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34880             :   { Feature_HasSDWA|Feature_HasSDWA, 15026 /* v_cmp_nlg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34881             :   { Feature_HasSDWA|Feature_HasSDWA, 15026 /* v_cmp_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34882             :   { Feature_HasSDWA|Feature_HasSDWA, 15026 /* v_cmp_nlg_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34883             :   { Feature_HasSDWA|Feature_HasSDWA, 15026 /* v_cmp_nlg_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34884             :   { Feature_isGCN|Feature_isSICI, 15058 /* v_cmp_nlg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34885             :   { Feature_isGCN|Feature_isSICI, 15058 /* v_cmp_nlg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34886             :   { Feature_isGCN|Feature_isVI, 15058 /* v_cmp_nlg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34887             :   { Feature_isGCN|Feature_isVI, 15058 /* v_cmp_nlg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34888             :   { Feature_Has16BitInsts|Feature_isVI, 15090 /* v_cmp_nlt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34889             :   { Feature_Has16BitInsts|Feature_isVI, 15090 /* v_cmp_nlt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34890             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15090 /* v_cmp_nlt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34891             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15090 /* v_cmp_nlt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34892             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15090 /* v_cmp_nlt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34893             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15090 /* v_cmp_nlt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34894             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15090 /* v_cmp_nlt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34895             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15090 /* v_cmp_nlt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34896             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15090 /* v_cmp_nlt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34897             :   { Feature_isGCN|Feature_isSICI, 15122 /* v_cmp_nlt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34898             :   { Feature_isGCN|Feature_isSICI, 15122 /* v_cmp_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34899             :   { Feature_isGCN|Feature_isVI, 15122 /* v_cmp_nlt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34900             :   { Feature_isGCN|Feature_isVI, 15122 /* v_cmp_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34901             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15122 /* v_cmp_nlt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34902             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15122 /* v_cmp_nlt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34903             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15122 /* v_cmp_nlt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34904             :   { Feature_HasSDWA|Feature_HasSDWA, 15122 /* v_cmp_nlt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34905             :   { Feature_HasSDWA|Feature_HasSDWA, 15122 /* v_cmp_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34906             :   { Feature_HasSDWA|Feature_HasSDWA, 15122 /* v_cmp_nlt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34907             :   { Feature_HasSDWA|Feature_HasSDWA, 15122 /* v_cmp_nlt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34908             :   { Feature_isGCN|Feature_isSICI, 15154 /* v_cmp_nlt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34909             :   { Feature_isGCN|Feature_isSICI, 15154 /* v_cmp_nlt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34910             :   { Feature_isGCN|Feature_isVI, 15154 /* v_cmp_nlt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34911             :   { Feature_isGCN|Feature_isVI, 15154 /* v_cmp_nlt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34912             :   { Feature_Has16BitInsts|Feature_isVI, 15186 /* v_cmp_o_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34913             :   { Feature_Has16BitInsts|Feature_isVI, 15186 /* v_cmp_o_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34914             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15186 /* v_cmp_o_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34915             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15186 /* v_cmp_o_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34916             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15186 /* v_cmp_o_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34917             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15186 /* v_cmp_o_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34918             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15186 /* v_cmp_o_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34919             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15186 /* v_cmp_o_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34920             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15186 /* v_cmp_o_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34921             :   { Feature_isGCN|Feature_isSICI, 15214 /* v_cmp_o_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34922             :   { Feature_isGCN|Feature_isSICI, 15214 /* v_cmp_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34923             :   { Feature_isGCN|Feature_isVI, 15214 /* v_cmp_o_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34924             :   { Feature_isGCN|Feature_isVI, 15214 /* v_cmp_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34925             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15214 /* v_cmp_o_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34926             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15214 /* v_cmp_o_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34927             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15214 /* v_cmp_o_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34928             :   { Feature_HasSDWA|Feature_HasSDWA, 15214 /* v_cmp_o_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34929             :   { Feature_HasSDWA|Feature_HasSDWA, 15214 /* v_cmp_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34930             :   { Feature_HasSDWA|Feature_HasSDWA, 15214 /* v_cmp_o_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34931             :   { Feature_HasSDWA|Feature_HasSDWA, 15214 /* v_cmp_o_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34932             :   { Feature_isGCN|Feature_isSICI, 15242 /* v_cmp_o_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34933             :   { Feature_isGCN|Feature_isSICI, 15242 /* v_cmp_o_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34934             :   { Feature_isGCN|Feature_isVI, 15242 /* v_cmp_o_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34935             :   { Feature_isGCN|Feature_isVI, 15242 /* v_cmp_o_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34936             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15270 /* v_cmp_t_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34937             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15270 /* v_cmp_t_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34938             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15270 /* v_cmp_t_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34939             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15270 /* v_cmp_t_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34940             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15270 /* v_cmp_t_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34941             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15270 /* v_cmp_t_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34942             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15270 /* v_cmp_t_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34943             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15298 /* v_cmp_t_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34944             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15298 /* v_cmp_t_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34945             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15298 /* v_cmp_t_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34946             :   { Feature_HasSDWA|Feature_HasSDWA, 15298 /* v_cmp_t_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34947             :   { Feature_HasSDWA|Feature_HasSDWA, 15298 /* v_cmp_t_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34948             :   { Feature_HasSDWA|Feature_HasSDWA, 15298 /* v_cmp_t_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34949             :   { Feature_HasSDWA|Feature_HasSDWA, 15298 /* v_cmp_t_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34950             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15354 /* v_cmp_t_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34951             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15354 /* v_cmp_t_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34952             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15354 /* v_cmp_t_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34953             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15354 /* v_cmp_t_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   34954             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15354 /* v_cmp_t_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34955             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15354 /* v_cmp_t_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34956             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15354 /* v_cmp_t_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34957             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15382 /* v_cmp_t_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34958             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15382 /* v_cmp_t_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34959             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15382 /* v_cmp_t_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34960             :   { Feature_HasSDWA|Feature_HasSDWA, 15382 /* v_cmp_t_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   34961             :   { Feature_HasSDWA|Feature_HasSDWA, 15382 /* v_cmp_t_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34962             :   { Feature_HasSDWA|Feature_HasSDWA, 15382 /* v_cmp_t_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34963             :   { Feature_HasSDWA|Feature_HasSDWA, 15382 /* v_cmp_t_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34964             :   { Feature_Has16BitInsts|Feature_isVI, 15438 /* v_cmp_tru_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34965             :   { Feature_Has16BitInsts|Feature_isVI, 15438 /* v_cmp_tru_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34966             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15438 /* v_cmp_tru_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34967             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15438 /* v_cmp_tru_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34968             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15438 /* v_cmp_tru_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34969             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15438 /* v_cmp_tru_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34970             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15438 /* v_cmp_tru_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34971             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15438 /* v_cmp_tru_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34972             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15438 /* v_cmp_tru_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34973             :   { Feature_isGCN|Feature_isSICI, 15470 /* v_cmp_tru_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34974             :   { Feature_isGCN|Feature_isSICI, 15470 /* v_cmp_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34975             :   { Feature_isGCN|Feature_isVI, 15470 /* v_cmp_tru_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34976             :   { Feature_isGCN|Feature_isVI, 15470 /* v_cmp_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34977             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15470 /* v_cmp_tru_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34978             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15470 /* v_cmp_tru_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34979             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15470 /* v_cmp_tru_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34980             :   { Feature_HasSDWA|Feature_HasSDWA, 15470 /* v_cmp_tru_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   34981             :   { Feature_HasSDWA|Feature_HasSDWA, 15470 /* v_cmp_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34982             :   { Feature_HasSDWA|Feature_HasSDWA, 15470 /* v_cmp_tru_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34983             :   { Feature_HasSDWA|Feature_HasSDWA, 15470 /* v_cmp_tru_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34984             :   { Feature_isGCN|Feature_isSICI, 15502 /* v_cmp_tru_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34985             :   { Feature_isGCN|Feature_isSICI, 15502 /* v_cmp_tru_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34986             :   { Feature_isGCN|Feature_isVI, 15502 /* v_cmp_tru_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   34987             :   { Feature_isGCN|Feature_isVI, 15502 /* v_cmp_tru_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   34988             :   { Feature_Has16BitInsts|Feature_isVI, 15534 /* v_cmp_u_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   34989             :   { Feature_Has16BitInsts|Feature_isVI, 15534 /* v_cmp_u_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34990             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15534 /* v_cmp_u_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34991             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15534 /* v_cmp_u_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   34992             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15534 /* v_cmp_u_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   34993             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15534 /* v_cmp_u_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   34994             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15534 /* v_cmp_u_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   34995             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15534 /* v_cmp_u_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   34996             :   { Feature_Has16BitInsts|Feature_HasSDWA, 15534 /* v_cmp_u_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   34997             :   { Feature_isGCN|Feature_isSICI, 15562 /* v_cmp_u_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   34998             :   { Feature_isGCN|Feature_isSICI, 15562 /* v_cmp_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   34999             :   { Feature_isGCN|Feature_isVI, 15562 /* v_cmp_u_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35000             :   { Feature_isGCN|Feature_isVI, 15562 /* v_cmp_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35001             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15562 /* v_cmp_u_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35002             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15562 /* v_cmp_u_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35003             :   { Feature_HasSDWA9|Feature_HasSDWA9, 15562 /* v_cmp_u_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35004             :   { Feature_HasSDWA|Feature_HasSDWA, 15562 /* v_cmp_u_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35005             :   { Feature_HasSDWA|Feature_HasSDWA, 15562 /* v_cmp_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35006             :   { Feature_HasSDWA|Feature_HasSDWA, 15562 /* v_cmp_u_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35007             :   { Feature_HasSDWA|Feature_HasSDWA, 15562 /* v_cmp_u_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35008             :   { Feature_isGCN|Feature_isSICI, 15590 /* v_cmp_u_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35009             :   { Feature_isGCN|Feature_isSICI, 15590 /* v_cmp_u_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35010             :   { Feature_isGCN|Feature_isVI, 15590 /* v_cmp_u_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35011             :   { Feature_isGCN|Feature_isVI, 15590 /* v_cmp_u_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35012             :   { Feature_isSICI|Feature_isSICI, 15618 /* v_cmps_eq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35013             :   { Feature_isSICI|Feature_isSICI, 15618 /* v_cmps_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35014             :   { Feature_isSICI|Feature_isSICI, 15650 /* v_cmps_eq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35015             :   { Feature_isSICI|Feature_isSICI, 15650 /* v_cmps_eq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35016             :   { Feature_isSICI|Feature_isSICI, 15682 /* v_cmps_f_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35017             :   { Feature_isSICI|Feature_isSICI, 15682 /* v_cmps_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35018             :   { Feature_isSICI|Feature_isSICI, 15712 /* v_cmps_f_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35019             :   { Feature_isSICI|Feature_isSICI, 15712 /* v_cmps_f_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35020             :   { Feature_isSICI|Feature_isSICI, 15742 /* v_cmps_ge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35021             :   { Feature_isSICI|Feature_isSICI, 15742 /* v_cmps_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35022             :   { Feature_isSICI|Feature_isSICI, 15774 /* v_cmps_ge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35023             :   { Feature_isSICI|Feature_isSICI, 15774 /* v_cmps_ge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35024             :   { Feature_isSICI|Feature_isSICI, 15806 /* v_cmps_gt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35025             :   { Feature_isSICI|Feature_isSICI, 15806 /* v_cmps_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35026             :   { Feature_isSICI|Feature_isSICI, 15838 /* v_cmps_gt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35027             :   { Feature_isSICI|Feature_isSICI, 15838 /* v_cmps_gt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35028             :   { Feature_isSICI|Feature_isSICI, 15870 /* v_cmps_le_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35029             :   { Feature_isSICI|Feature_isSICI, 15870 /* v_cmps_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35030             :   { Feature_isSICI|Feature_isSICI, 15902 /* v_cmps_le_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35031             :   { Feature_isSICI|Feature_isSICI, 15902 /* v_cmps_le_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35032             :   { Feature_isSICI|Feature_isSICI, 15934 /* v_cmps_lg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35033             :   { Feature_isSICI|Feature_isSICI, 15934 /* v_cmps_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35034             :   { Feature_isSICI|Feature_isSICI, 15966 /* v_cmps_lg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35035             :   { Feature_isSICI|Feature_isSICI, 15966 /* v_cmps_lg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35036             :   { Feature_isSICI|Feature_isSICI, 15998 /* v_cmps_lt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35037             :   { Feature_isSICI|Feature_isSICI, 15998 /* v_cmps_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35038             :   { Feature_isSICI|Feature_isSICI, 16030 /* v_cmps_lt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35039             :   { Feature_isSICI|Feature_isSICI, 16030 /* v_cmps_lt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35040             :   { Feature_isSICI|Feature_isSICI, 16062 /* v_cmps_neq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35041             :   { Feature_isSICI|Feature_isSICI, 16062 /* v_cmps_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35042             :   { Feature_isSICI|Feature_isSICI, 16096 /* v_cmps_neq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35043             :   { Feature_isSICI|Feature_isSICI, 16096 /* v_cmps_neq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35044             :   { Feature_isSICI|Feature_isSICI, 16130 /* v_cmps_nge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35045             :   { Feature_isSICI|Feature_isSICI, 16130 /* v_cmps_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35046             :   { Feature_isSICI|Feature_isSICI, 16164 /* v_cmps_nge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35047             :   { Feature_isSICI|Feature_isSICI, 16164 /* v_cmps_nge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35048             :   { Feature_isSICI|Feature_isSICI, 16198 /* v_cmps_ngt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35049             :   { Feature_isSICI|Feature_isSICI, 16198 /* v_cmps_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35050             :   { Feature_isSICI|Feature_isSICI, 16232 /* v_cmps_ngt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35051             :   { Feature_isSICI|Feature_isSICI, 16232 /* v_cmps_ngt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35052             :   { Feature_isSICI|Feature_isSICI, 16266 /* v_cmps_nle_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35053             :   { Feature_isSICI|Feature_isSICI, 16266 /* v_cmps_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35054             :   { Feature_isSICI|Feature_isSICI, 16300 /* v_cmps_nle_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35055             :   { Feature_isSICI|Feature_isSICI, 16300 /* v_cmps_nle_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35056             :   { Feature_isSICI|Feature_isSICI, 16334 /* v_cmps_nlg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35057             :   { Feature_isSICI|Feature_isSICI, 16334 /* v_cmps_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35058             :   { Feature_isSICI|Feature_isSICI, 16368 /* v_cmps_nlg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35059             :   { Feature_isSICI|Feature_isSICI, 16368 /* v_cmps_nlg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35060             :   { Feature_isSICI|Feature_isSICI, 16402 /* v_cmps_nlt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35061             :   { Feature_isSICI|Feature_isSICI, 16402 /* v_cmps_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35062             :   { Feature_isSICI|Feature_isSICI, 16436 /* v_cmps_nlt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35063             :   { Feature_isSICI|Feature_isSICI, 16436 /* v_cmps_nlt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35064             :   { Feature_isSICI|Feature_isSICI, 16470 /* v_cmps_o_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35065             :   { Feature_isSICI|Feature_isSICI, 16470 /* v_cmps_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35066             :   { Feature_isSICI|Feature_isSICI, 16500 /* v_cmps_o_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35067             :   { Feature_isSICI|Feature_isSICI, 16500 /* v_cmps_o_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35068             :   { Feature_isSICI|Feature_isSICI, 16530 /* v_cmps_tru_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35069             :   { Feature_isSICI|Feature_isSICI, 16530 /* v_cmps_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35070             :   { Feature_isSICI|Feature_isSICI, 16564 /* v_cmps_tru_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35071             :   { Feature_isSICI|Feature_isSICI, 16564 /* v_cmps_tru_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35072             :   { Feature_isSICI|Feature_isSICI, 16598 /* v_cmps_u_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35073             :   { Feature_isSICI|Feature_isSICI, 16598 /* v_cmps_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35074             :   { Feature_isSICI|Feature_isSICI, 16628 /* v_cmps_u_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35075             :   { Feature_isSICI|Feature_isSICI, 16628 /* v_cmps_u_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35076             :   { Feature_isSICI|Feature_isSICI, 16658 /* v_cmpsx_eq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35077             :   { Feature_isSICI|Feature_isSICI, 16658 /* v_cmpsx_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35078             :   { Feature_isSICI|Feature_isSICI, 16692 /* v_cmpsx_eq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35079             :   { Feature_isSICI|Feature_isSICI, 16692 /* v_cmpsx_eq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35080             :   { Feature_isSICI|Feature_isSICI, 16726 /* v_cmpsx_f_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35081             :   { Feature_isSICI|Feature_isSICI, 16726 /* v_cmpsx_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35082             :   { Feature_isSICI|Feature_isSICI, 16758 /* v_cmpsx_f_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35083             :   { Feature_isSICI|Feature_isSICI, 16758 /* v_cmpsx_f_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35084             :   { Feature_isSICI|Feature_isSICI, 16790 /* v_cmpsx_ge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35085             :   { Feature_isSICI|Feature_isSICI, 16790 /* v_cmpsx_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35086             :   { Feature_isSICI|Feature_isSICI, 16824 /* v_cmpsx_ge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35087             :   { Feature_isSICI|Feature_isSICI, 16824 /* v_cmpsx_ge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35088             :   { Feature_isSICI|Feature_isSICI, 16858 /* v_cmpsx_gt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35089             :   { Feature_isSICI|Feature_isSICI, 16858 /* v_cmpsx_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35090             :   { Feature_isSICI|Feature_isSICI, 16892 /* v_cmpsx_gt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35091             :   { Feature_isSICI|Feature_isSICI, 16892 /* v_cmpsx_gt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35092             :   { Feature_isSICI|Feature_isSICI, 16926 /* v_cmpsx_le_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35093             :   { Feature_isSICI|Feature_isSICI, 16926 /* v_cmpsx_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35094             :   { Feature_isSICI|Feature_isSICI, 16960 /* v_cmpsx_le_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35095             :   { Feature_isSICI|Feature_isSICI, 16960 /* v_cmpsx_le_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35096             :   { Feature_isSICI|Feature_isSICI, 16994 /* v_cmpsx_lg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35097             :   { Feature_isSICI|Feature_isSICI, 16994 /* v_cmpsx_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35098             :   { Feature_isSICI|Feature_isSICI, 17028 /* v_cmpsx_lg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35099             :   { Feature_isSICI|Feature_isSICI, 17028 /* v_cmpsx_lg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35100             :   { Feature_isSICI|Feature_isSICI, 17062 /* v_cmpsx_lt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35101             :   { Feature_isSICI|Feature_isSICI, 17062 /* v_cmpsx_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35102             :   { Feature_isSICI|Feature_isSICI, 17096 /* v_cmpsx_lt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35103             :   { Feature_isSICI|Feature_isSICI, 17096 /* v_cmpsx_lt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35104             :   { Feature_isSICI|Feature_isSICI, 17130 /* v_cmpsx_neq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35105             :   { Feature_isSICI|Feature_isSICI, 17130 /* v_cmpsx_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35106             :   { Feature_isSICI|Feature_isSICI, 17166 /* v_cmpsx_neq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35107             :   { Feature_isSICI|Feature_isSICI, 17166 /* v_cmpsx_neq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35108             :   { Feature_isSICI|Feature_isSICI, 17202 /* v_cmpsx_nge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35109             :   { Feature_isSICI|Feature_isSICI, 17202 /* v_cmpsx_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35110             :   { Feature_isSICI|Feature_isSICI, 17238 /* v_cmpsx_nge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35111             :   { Feature_isSICI|Feature_isSICI, 17238 /* v_cmpsx_nge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35112             :   { Feature_isSICI|Feature_isSICI, 17274 /* v_cmpsx_ngt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35113             :   { Feature_isSICI|Feature_isSICI, 17274 /* v_cmpsx_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35114             :   { Feature_isSICI|Feature_isSICI, 17310 /* v_cmpsx_ngt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35115             :   { Feature_isSICI|Feature_isSICI, 17310 /* v_cmpsx_ngt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35116             :   { Feature_isSICI|Feature_isSICI, 17346 /* v_cmpsx_nle_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35117             :   { Feature_isSICI|Feature_isSICI, 17346 /* v_cmpsx_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35118             :   { Feature_isSICI|Feature_isSICI, 17382 /* v_cmpsx_nle_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35119             :   { Feature_isSICI|Feature_isSICI, 17382 /* v_cmpsx_nle_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35120             :   { Feature_isSICI|Feature_isSICI, 17418 /* v_cmpsx_nlg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35121             :   { Feature_isSICI|Feature_isSICI, 17418 /* v_cmpsx_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35122             :   { Feature_isSICI|Feature_isSICI, 17454 /* v_cmpsx_nlg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35123             :   { Feature_isSICI|Feature_isSICI, 17454 /* v_cmpsx_nlg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35124             :   { Feature_isSICI|Feature_isSICI, 17490 /* v_cmpsx_nlt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35125             :   { Feature_isSICI|Feature_isSICI, 17490 /* v_cmpsx_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35126             :   { Feature_isSICI|Feature_isSICI, 17526 /* v_cmpsx_nlt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35127             :   { Feature_isSICI|Feature_isSICI, 17526 /* v_cmpsx_nlt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35128             :   { Feature_isSICI|Feature_isSICI, 17562 /* v_cmpsx_o_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35129             :   { Feature_isSICI|Feature_isSICI, 17562 /* v_cmpsx_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35130             :   { Feature_isSICI|Feature_isSICI, 17594 /* v_cmpsx_o_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35131             :   { Feature_isSICI|Feature_isSICI, 17594 /* v_cmpsx_o_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35132             :   { Feature_isSICI|Feature_isSICI, 17626 /* v_cmpsx_tru_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35133             :   { Feature_isSICI|Feature_isSICI, 17626 /* v_cmpsx_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35134             :   { Feature_isSICI|Feature_isSICI, 17662 /* v_cmpsx_tru_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35135             :   { Feature_isSICI|Feature_isSICI, 17662 /* v_cmpsx_tru_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35136             :   { Feature_isSICI|Feature_isSICI, 17698 /* v_cmpsx_u_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35137             :   { Feature_isSICI|Feature_isSICI, 17698 /* v_cmpsx_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35138             :   { Feature_isSICI|Feature_isSICI, 17730 /* v_cmpsx_u_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35139             :   { Feature_isSICI|Feature_isSICI, 17730 /* v_cmpsx_u_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35140             :   { Feature_isGCN|Feature_isVI, 17762 /* v_cmpx_class_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   35141             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17762 /* v_cmpx_class_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   35142             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17762 /* v_cmpx_class_f16 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   35143             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17762 /* v_cmpx_class_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35144             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17762 /* v_cmpx_class_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35145             :   { Feature_HasSDWA|Feature_HasSDWA, 17762 /* v_cmpx_class_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   35146             :   { Feature_HasSDWA|Feature_HasSDWA, 17762 /* v_cmpx_class_f16 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   35147             :   { Feature_HasSDWA|Feature_HasSDWA, 17762 /* v_cmpx_class_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35148             :   { Feature_HasSDWA|Feature_HasSDWA, 17762 /* v_cmpx_class_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35149             :   { Feature_HasSDWA|Feature_HasSDWA, 17762 /* v_cmpx_class_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35150             :   { Feature_isGCN|Feature_isSICI, 17800 /* v_cmpx_class_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   35151             :   { Feature_isGCN|Feature_isVI, 17800 /* v_cmpx_class_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   35152             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17800 /* v_cmpx_class_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   35153             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17800 /* v_cmpx_class_f32 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   35154             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17800 /* v_cmpx_class_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35155             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17800 /* v_cmpx_class_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35156             :   { Feature_HasSDWA|Feature_HasSDWA, 17800 /* v_cmpx_class_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   35157             :   { Feature_HasSDWA|Feature_HasSDWA, 17800 /* v_cmpx_class_f32 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   35158             :   { Feature_HasSDWA|Feature_HasSDWA, 17800 /* v_cmpx_class_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35159             :   { Feature_HasSDWA|Feature_HasSDWA, 17800 /* v_cmpx_class_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35160             :   { Feature_HasSDWA|Feature_HasSDWA, 17800 /* v_cmpx_class_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35161             :   { Feature_isGCN|Feature_isSICI, 17838 /* v_cmpx_class_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   35162             :   { Feature_isGCN|Feature_isVI, 17838 /* v_cmpx_class_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   35163             :   { Feature_Has16BitInsts|Feature_isVI, 17876 /* v_cmpx_eq_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35164             :   { Feature_Has16BitInsts|Feature_isVI, 17876 /* v_cmpx_eq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35165             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17876 /* v_cmpx_eq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35166             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17876 /* v_cmpx_eq_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35167             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17876 /* v_cmpx_eq_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35168             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17876 /* v_cmpx_eq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35169             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17876 /* v_cmpx_eq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35170             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17876 /* v_cmpx_eq_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35171             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17876 /* v_cmpx_eq_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35172             :   { Feature_isGCN|Feature_isSICI, 17908 /* v_cmpx_eq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35173             :   { Feature_isGCN|Feature_isSICI, 17908 /* v_cmpx_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35174             :   { Feature_isGCN|Feature_isVI, 17908 /* v_cmpx_eq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35175             :   { Feature_isGCN|Feature_isVI, 17908 /* v_cmpx_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35176             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17908 /* v_cmpx_eq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35177             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17908 /* v_cmpx_eq_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35178             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17908 /* v_cmpx_eq_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35179             :   { Feature_HasSDWA|Feature_HasSDWA, 17908 /* v_cmpx_eq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35180             :   { Feature_HasSDWA|Feature_HasSDWA, 17908 /* v_cmpx_eq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35181             :   { Feature_HasSDWA|Feature_HasSDWA, 17908 /* v_cmpx_eq_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35182             :   { Feature_HasSDWA|Feature_HasSDWA, 17908 /* v_cmpx_eq_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35183             :   { Feature_isGCN|Feature_isSICI, 17940 /* v_cmpx_eq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35184             :   { Feature_isGCN|Feature_isSICI, 17940 /* v_cmpx_eq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35185             :   { Feature_isGCN|Feature_isVI, 17940 /* v_cmpx_eq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35186             :   { Feature_isGCN|Feature_isVI, 17940 /* v_cmpx_eq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35187             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17972 /* v_cmpx_eq_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35188             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17972 /* v_cmpx_eq_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35189             :   { Feature_HasSDWA9|Feature_HasSDWA9, 17972 /* v_cmpx_eq_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35190             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17972 /* v_cmpx_eq_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35191             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17972 /* v_cmpx_eq_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35192             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17972 /* v_cmpx_eq_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35193             :   { Feature_Has16BitInsts|Feature_HasSDWA, 17972 /* v_cmpx_eq_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35194             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18004 /* v_cmpx_eq_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35195             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18004 /* v_cmpx_eq_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35196             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18004 /* v_cmpx_eq_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35197             :   { Feature_HasSDWA|Feature_HasSDWA, 18004 /* v_cmpx_eq_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35198             :   { Feature_HasSDWA|Feature_HasSDWA, 18004 /* v_cmpx_eq_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35199             :   { Feature_HasSDWA|Feature_HasSDWA, 18004 /* v_cmpx_eq_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35200             :   { Feature_HasSDWA|Feature_HasSDWA, 18004 /* v_cmpx_eq_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35201             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18068 /* v_cmpx_eq_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35202             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18068 /* v_cmpx_eq_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35203             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18068 /* v_cmpx_eq_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35204             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18068 /* v_cmpx_eq_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35205             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18068 /* v_cmpx_eq_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35206             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18068 /* v_cmpx_eq_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35207             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18068 /* v_cmpx_eq_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35208             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18100 /* v_cmpx_eq_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35209             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18100 /* v_cmpx_eq_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35210             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18100 /* v_cmpx_eq_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35211             :   { Feature_HasSDWA|Feature_HasSDWA, 18100 /* v_cmpx_eq_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35212             :   { Feature_HasSDWA|Feature_HasSDWA, 18100 /* v_cmpx_eq_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35213             :   { Feature_HasSDWA|Feature_HasSDWA, 18100 /* v_cmpx_eq_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35214             :   { Feature_HasSDWA|Feature_HasSDWA, 18100 /* v_cmpx_eq_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35215             :   { Feature_Has16BitInsts|Feature_isVI, 18164 /* v_cmpx_f_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35216             :   { Feature_Has16BitInsts|Feature_isVI, 18164 /* v_cmpx_f_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35217             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18164 /* v_cmpx_f_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35218             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18164 /* v_cmpx_f_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35219             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18164 /* v_cmpx_f_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35220             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18164 /* v_cmpx_f_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35221             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18164 /* v_cmpx_f_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35222             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18164 /* v_cmpx_f_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35223             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18164 /* v_cmpx_f_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35224             :   { Feature_isGCN|Feature_isSICI, 18194 /* v_cmpx_f_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35225             :   { Feature_isGCN|Feature_isSICI, 18194 /* v_cmpx_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35226             :   { Feature_isGCN|Feature_isVI, 18194 /* v_cmpx_f_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35227             :   { Feature_isGCN|Feature_isVI, 18194 /* v_cmpx_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35228             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18194 /* v_cmpx_f_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35229             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18194 /* v_cmpx_f_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35230             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18194 /* v_cmpx_f_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35231             :   { Feature_HasSDWA|Feature_HasSDWA, 18194 /* v_cmpx_f_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35232             :   { Feature_HasSDWA|Feature_HasSDWA, 18194 /* v_cmpx_f_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35233             :   { Feature_HasSDWA|Feature_HasSDWA, 18194 /* v_cmpx_f_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35234             :   { Feature_HasSDWA|Feature_HasSDWA, 18194 /* v_cmpx_f_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35235             :   { Feature_isGCN|Feature_isSICI, 18224 /* v_cmpx_f_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35236             :   { Feature_isGCN|Feature_isSICI, 18224 /* v_cmpx_f_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35237             :   { Feature_isGCN|Feature_isVI, 18224 /* v_cmpx_f_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35238             :   { Feature_isGCN|Feature_isVI, 18224 /* v_cmpx_f_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35239             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18254 /* v_cmpx_f_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35240             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18254 /* v_cmpx_f_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35241             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18254 /* v_cmpx_f_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35242             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18254 /* v_cmpx_f_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35243             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18254 /* v_cmpx_f_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35244             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18254 /* v_cmpx_f_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35245             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18254 /* v_cmpx_f_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35246             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18284 /* v_cmpx_f_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35247             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18284 /* v_cmpx_f_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35248             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18284 /* v_cmpx_f_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35249             :   { Feature_HasSDWA|Feature_HasSDWA, 18284 /* v_cmpx_f_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35250             :   { Feature_HasSDWA|Feature_HasSDWA, 18284 /* v_cmpx_f_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35251             :   { Feature_HasSDWA|Feature_HasSDWA, 18284 /* v_cmpx_f_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35252             :   { Feature_HasSDWA|Feature_HasSDWA, 18284 /* v_cmpx_f_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35253             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18344 /* v_cmpx_f_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35254             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18344 /* v_cmpx_f_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35255             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18344 /* v_cmpx_f_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35256             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18344 /* v_cmpx_f_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35257             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18344 /* v_cmpx_f_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35258             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18344 /* v_cmpx_f_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35259             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18344 /* v_cmpx_f_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35260             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18374 /* v_cmpx_f_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35261             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18374 /* v_cmpx_f_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35262             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18374 /* v_cmpx_f_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35263             :   { Feature_HasSDWA|Feature_HasSDWA, 18374 /* v_cmpx_f_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35264             :   { Feature_HasSDWA|Feature_HasSDWA, 18374 /* v_cmpx_f_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35265             :   { Feature_HasSDWA|Feature_HasSDWA, 18374 /* v_cmpx_f_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35266             :   { Feature_HasSDWA|Feature_HasSDWA, 18374 /* v_cmpx_f_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35267             :   { Feature_Has16BitInsts|Feature_isVI, 18434 /* v_cmpx_ge_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35268             :   { Feature_Has16BitInsts|Feature_isVI, 18434 /* v_cmpx_ge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35269             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18434 /* v_cmpx_ge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35270             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18434 /* v_cmpx_ge_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35271             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18434 /* v_cmpx_ge_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35272             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18434 /* v_cmpx_ge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35273             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18434 /* v_cmpx_ge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35274             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18434 /* v_cmpx_ge_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35275             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18434 /* v_cmpx_ge_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35276             :   { Feature_isGCN|Feature_isSICI, 18466 /* v_cmpx_ge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35277             :   { Feature_isGCN|Feature_isSICI, 18466 /* v_cmpx_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35278             :   { Feature_isGCN|Feature_isVI, 18466 /* v_cmpx_ge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35279             :   { Feature_isGCN|Feature_isVI, 18466 /* v_cmpx_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35280             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18466 /* v_cmpx_ge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35281             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18466 /* v_cmpx_ge_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35282             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18466 /* v_cmpx_ge_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35283             :   { Feature_HasSDWA|Feature_HasSDWA, 18466 /* v_cmpx_ge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35284             :   { Feature_HasSDWA|Feature_HasSDWA, 18466 /* v_cmpx_ge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35285             :   { Feature_HasSDWA|Feature_HasSDWA, 18466 /* v_cmpx_ge_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35286             :   { Feature_HasSDWA|Feature_HasSDWA, 18466 /* v_cmpx_ge_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35287             :   { Feature_isGCN|Feature_isSICI, 18498 /* v_cmpx_ge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35288             :   { Feature_isGCN|Feature_isSICI, 18498 /* v_cmpx_ge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35289             :   { Feature_isGCN|Feature_isVI, 18498 /* v_cmpx_ge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35290             :   { Feature_isGCN|Feature_isVI, 18498 /* v_cmpx_ge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35291             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18530 /* v_cmpx_ge_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35292             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18530 /* v_cmpx_ge_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35293             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18530 /* v_cmpx_ge_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35294             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18530 /* v_cmpx_ge_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35295             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18530 /* v_cmpx_ge_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35296             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18530 /* v_cmpx_ge_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35297             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18530 /* v_cmpx_ge_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35298             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18562 /* v_cmpx_ge_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35299             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18562 /* v_cmpx_ge_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35300             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18562 /* v_cmpx_ge_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35301             :   { Feature_HasSDWA|Feature_HasSDWA, 18562 /* v_cmpx_ge_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35302             :   { Feature_HasSDWA|Feature_HasSDWA, 18562 /* v_cmpx_ge_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35303             :   { Feature_HasSDWA|Feature_HasSDWA, 18562 /* v_cmpx_ge_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35304             :   { Feature_HasSDWA|Feature_HasSDWA, 18562 /* v_cmpx_ge_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35305             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18626 /* v_cmpx_ge_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35306             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18626 /* v_cmpx_ge_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35307             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18626 /* v_cmpx_ge_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35308             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18626 /* v_cmpx_ge_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35309             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18626 /* v_cmpx_ge_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35310             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18626 /* v_cmpx_ge_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35311             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18626 /* v_cmpx_ge_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35312             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18658 /* v_cmpx_ge_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35313             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18658 /* v_cmpx_ge_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35314             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18658 /* v_cmpx_ge_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35315             :   { Feature_HasSDWA|Feature_HasSDWA, 18658 /* v_cmpx_ge_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35316             :   { Feature_HasSDWA|Feature_HasSDWA, 18658 /* v_cmpx_ge_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35317             :   { Feature_HasSDWA|Feature_HasSDWA, 18658 /* v_cmpx_ge_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35318             :   { Feature_HasSDWA|Feature_HasSDWA, 18658 /* v_cmpx_ge_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35319             :   { Feature_Has16BitInsts|Feature_isVI, 18722 /* v_cmpx_gt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35320             :   { Feature_Has16BitInsts|Feature_isVI, 18722 /* v_cmpx_gt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35321             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18722 /* v_cmpx_gt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35322             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18722 /* v_cmpx_gt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35323             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18722 /* v_cmpx_gt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35324             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18722 /* v_cmpx_gt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35325             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18722 /* v_cmpx_gt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35326             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18722 /* v_cmpx_gt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35327             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18722 /* v_cmpx_gt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35328             :   { Feature_isGCN|Feature_isSICI, 18754 /* v_cmpx_gt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35329             :   { Feature_isGCN|Feature_isSICI, 18754 /* v_cmpx_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35330             :   { Feature_isGCN|Feature_isVI, 18754 /* v_cmpx_gt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35331             :   { Feature_isGCN|Feature_isVI, 18754 /* v_cmpx_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35332             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18754 /* v_cmpx_gt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35333             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18754 /* v_cmpx_gt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35334             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18754 /* v_cmpx_gt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35335             :   { Feature_HasSDWA|Feature_HasSDWA, 18754 /* v_cmpx_gt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35336             :   { Feature_HasSDWA|Feature_HasSDWA, 18754 /* v_cmpx_gt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35337             :   { Feature_HasSDWA|Feature_HasSDWA, 18754 /* v_cmpx_gt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35338             :   { Feature_HasSDWA|Feature_HasSDWA, 18754 /* v_cmpx_gt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35339             :   { Feature_isGCN|Feature_isSICI, 18786 /* v_cmpx_gt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35340             :   { Feature_isGCN|Feature_isSICI, 18786 /* v_cmpx_gt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35341             :   { Feature_isGCN|Feature_isVI, 18786 /* v_cmpx_gt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35342             :   { Feature_isGCN|Feature_isVI, 18786 /* v_cmpx_gt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35343             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18818 /* v_cmpx_gt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35344             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18818 /* v_cmpx_gt_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35345             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18818 /* v_cmpx_gt_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35346             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18818 /* v_cmpx_gt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35347             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18818 /* v_cmpx_gt_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35348             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18818 /* v_cmpx_gt_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35349             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18818 /* v_cmpx_gt_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35350             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18850 /* v_cmpx_gt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35351             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18850 /* v_cmpx_gt_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35352             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18850 /* v_cmpx_gt_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35353             :   { Feature_HasSDWA|Feature_HasSDWA, 18850 /* v_cmpx_gt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35354             :   { Feature_HasSDWA|Feature_HasSDWA, 18850 /* v_cmpx_gt_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35355             :   { Feature_HasSDWA|Feature_HasSDWA, 18850 /* v_cmpx_gt_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35356             :   { Feature_HasSDWA|Feature_HasSDWA, 18850 /* v_cmpx_gt_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35357             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18914 /* v_cmpx_gt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35358             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18914 /* v_cmpx_gt_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35359             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18914 /* v_cmpx_gt_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35360             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18914 /* v_cmpx_gt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35361             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18914 /* v_cmpx_gt_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35362             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18914 /* v_cmpx_gt_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35363             :   { Feature_Has16BitInsts|Feature_HasSDWA, 18914 /* v_cmpx_gt_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35364             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18946 /* v_cmpx_gt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35365             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18946 /* v_cmpx_gt_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35366             :   { Feature_HasSDWA9|Feature_HasSDWA9, 18946 /* v_cmpx_gt_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35367             :   { Feature_HasSDWA|Feature_HasSDWA, 18946 /* v_cmpx_gt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35368             :   { Feature_HasSDWA|Feature_HasSDWA, 18946 /* v_cmpx_gt_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35369             :   { Feature_HasSDWA|Feature_HasSDWA, 18946 /* v_cmpx_gt_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35370             :   { Feature_HasSDWA|Feature_HasSDWA, 18946 /* v_cmpx_gt_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35371             :   { Feature_Has16BitInsts|Feature_isVI, 19010 /* v_cmpx_le_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35372             :   { Feature_Has16BitInsts|Feature_isVI, 19010 /* v_cmpx_le_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35373             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19010 /* v_cmpx_le_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35374             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19010 /* v_cmpx_le_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35375             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19010 /* v_cmpx_le_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35376             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19010 /* v_cmpx_le_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35377             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19010 /* v_cmpx_le_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35378             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19010 /* v_cmpx_le_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35379             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19010 /* v_cmpx_le_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35380             :   { Feature_isGCN|Feature_isSICI, 19042 /* v_cmpx_le_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35381             :   { Feature_isGCN|Feature_isSICI, 19042 /* v_cmpx_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35382             :   { Feature_isGCN|Feature_isVI, 19042 /* v_cmpx_le_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35383             :   { Feature_isGCN|Feature_isVI, 19042 /* v_cmpx_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35384             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19042 /* v_cmpx_le_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35385             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19042 /* v_cmpx_le_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35386             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19042 /* v_cmpx_le_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35387             :   { Feature_HasSDWA|Feature_HasSDWA, 19042 /* v_cmpx_le_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35388             :   { Feature_HasSDWA|Feature_HasSDWA, 19042 /* v_cmpx_le_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35389             :   { Feature_HasSDWA|Feature_HasSDWA, 19042 /* v_cmpx_le_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35390             :   { Feature_HasSDWA|Feature_HasSDWA, 19042 /* v_cmpx_le_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35391             :   { Feature_isGCN|Feature_isSICI, 19074 /* v_cmpx_le_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35392             :   { Feature_isGCN|Feature_isSICI, 19074 /* v_cmpx_le_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35393             :   { Feature_isGCN|Feature_isVI, 19074 /* v_cmpx_le_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35394             :   { Feature_isGCN|Feature_isVI, 19074 /* v_cmpx_le_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35395             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19106 /* v_cmpx_le_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35396             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19106 /* v_cmpx_le_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35397             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19106 /* v_cmpx_le_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35398             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19106 /* v_cmpx_le_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35399             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19106 /* v_cmpx_le_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35400             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19106 /* v_cmpx_le_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35401             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19106 /* v_cmpx_le_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35402             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19138 /* v_cmpx_le_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35403             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19138 /* v_cmpx_le_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35404             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19138 /* v_cmpx_le_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35405             :   { Feature_HasSDWA|Feature_HasSDWA, 19138 /* v_cmpx_le_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35406             :   { Feature_HasSDWA|Feature_HasSDWA, 19138 /* v_cmpx_le_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35407             :   { Feature_HasSDWA|Feature_HasSDWA, 19138 /* v_cmpx_le_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35408             :   { Feature_HasSDWA|Feature_HasSDWA, 19138 /* v_cmpx_le_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35409             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19202 /* v_cmpx_le_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35410             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19202 /* v_cmpx_le_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35411             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19202 /* v_cmpx_le_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35412             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19202 /* v_cmpx_le_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35413             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19202 /* v_cmpx_le_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35414             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19202 /* v_cmpx_le_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35415             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19202 /* v_cmpx_le_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35416             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19234 /* v_cmpx_le_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35417             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19234 /* v_cmpx_le_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35418             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19234 /* v_cmpx_le_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35419             :   { Feature_HasSDWA|Feature_HasSDWA, 19234 /* v_cmpx_le_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35420             :   { Feature_HasSDWA|Feature_HasSDWA, 19234 /* v_cmpx_le_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35421             :   { Feature_HasSDWA|Feature_HasSDWA, 19234 /* v_cmpx_le_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35422             :   { Feature_HasSDWA|Feature_HasSDWA, 19234 /* v_cmpx_le_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35423             :   { Feature_Has16BitInsts|Feature_isVI, 19298 /* v_cmpx_lg_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35424             :   { Feature_Has16BitInsts|Feature_isVI, 19298 /* v_cmpx_lg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35425             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19298 /* v_cmpx_lg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35426             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19298 /* v_cmpx_lg_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35427             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19298 /* v_cmpx_lg_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35428             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19298 /* v_cmpx_lg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35429             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19298 /* v_cmpx_lg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35430             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19298 /* v_cmpx_lg_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35431             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19298 /* v_cmpx_lg_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35432             :   { Feature_isGCN|Feature_isSICI, 19330 /* v_cmpx_lg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35433             :   { Feature_isGCN|Feature_isSICI, 19330 /* v_cmpx_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35434             :   { Feature_isGCN|Feature_isVI, 19330 /* v_cmpx_lg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35435             :   { Feature_isGCN|Feature_isVI, 19330 /* v_cmpx_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35436             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19330 /* v_cmpx_lg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35437             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19330 /* v_cmpx_lg_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35438             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19330 /* v_cmpx_lg_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35439             :   { Feature_HasSDWA|Feature_HasSDWA, 19330 /* v_cmpx_lg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35440             :   { Feature_HasSDWA|Feature_HasSDWA, 19330 /* v_cmpx_lg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35441             :   { Feature_HasSDWA|Feature_HasSDWA, 19330 /* v_cmpx_lg_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35442             :   { Feature_HasSDWA|Feature_HasSDWA, 19330 /* v_cmpx_lg_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35443             :   { Feature_isGCN|Feature_isSICI, 19362 /* v_cmpx_lg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35444             :   { Feature_isGCN|Feature_isSICI, 19362 /* v_cmpx_lg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35445             :   { Feature_isGCN|Feature_isVI, 19362 /* v_cmpx_lg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35446             :   { Feature_isGCN|Feature_isVI, 19362 /* v_cmpx_lg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35447             :   { Feature_Has16BitInsts|Feature_isVI, 19394 /* v_cmpx_lt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35448             :   { Feature_Has16BitInsts|Feature_isVI, 19394 /* v_cmpx_lt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35449             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19394 /* v_cmpx_lt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35450             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19394 /* v_cmpx_lt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35451             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19394 /* v_cmpx_lt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35452             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19394 /* v_cmpx_lt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35453             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19394 /* v_cmpx_lt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35454             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19394 /* v_cmpx_lt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35455             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19394 /* v_cmpx_lt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35456             :   { Feature_isGCN|Feature_isSICI, 19426 /* v_cmpx_lt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35457             :   { Feature_isGCN|Feature_isSICI, 19426 /* v_cmpx_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35458             :   { Feature_isGCN|Feature_isVI, 19426 /* v_cmpx_lt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35459             :   { Feature_isGCN|Feature_isVI, 19426 /* v_cmpx_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35460             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19426 /* v_cmpx_lt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35461             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19426 /* v_cmpx_lt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35462             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19426 /* v_cmpx_lt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35463             :   { Feature_HasSDWA|Feature_HasSDWA, 19426 /* v_cmpx_lt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35464             :   { Feature_HasSDWA|Feature_HasSDWA, 19426 /* v_cmpx_lt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35465             :   { Feature_HasSDWA|Feature_HasSDWA, 19426 /* v_cmpx_lt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35466             :   { Feature_HasSDWA|Feature_HasSDWA, 19426 /* v_cmpx_lt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35467             :   { Feature_isGCN|Feature_isSICI, 19458 /* v_cmpx_lt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35468             :   { Feature_isGCN|Feature_isSICI, 19458 /* v_cmpx_lt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35469             :   { Feature_isGCN|Feature_isVI, 19458 /* v_cmpx_lt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35470             :   { Feature_isGCN|Feature_isVI, 19458 /* v_cmpx_lt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35471             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19490 /* v_cmpx_lt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35472             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19490 /* v_cmpx_lt_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35473             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19490 /* v_cmpx_lt_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35474             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19490 /* v_cmpx_lt_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35475             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19490 /* v_cmpx_lt_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35476             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19490 /* v_cmpx_lt_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35477             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19490 /* v_cmpx_lt_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35478             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19522 /* v_cmpx_lt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35479             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19522 /* v_cmpx_lt_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35480             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19522 /* v_cmpx_lt_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35481             :   { Feature_HasSDWA|Feature_HasSDWA, 19522 /* v_cmpx_lt_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35482             :   { Feature_HasSDWA|Feature_HasSDWA, 19522 /* v_cmpx_lt_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35483             :   { Feature_HasSDWA|Feature_HasSDWA, 19522 /* v_cmpx_lt_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35484             :   { Feature_HasSDWA|Feature_HasSDWA, 19522 /* v_cmpx_lt_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35485             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19586 /* v_cmpx_lt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35486             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19586 /* v_cmpx_lt_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35487             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19586 /* v_cmpx_lt_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35488             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19586 /* v_cmpx_lt_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35489             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19586 /* v_cmpx_lt_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35490             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19586 /* v_cmpx_lt_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35491             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19586 /* v_cmpx_lt_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35492             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19618 /* v_cmpx_lt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35493             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19618 /* v_cmpx_lt_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35494             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19618 /* v_cmpx_lt_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35495             :   { Feature_HasSDWA|Feature_HasSDWA, 19618 /* v_cmpx_lt_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35496             :   { Feature_HasSDWA|Feature_HasSDWA, 19618 /* v_cmpx_lt_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35497             :   { Feature_HasSDWA|Feature_HasSDWA, 19618 /* v_cmpx_lt_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35498             :   { Feature_HasSDWA|Feature_HasSDWA, 19618 /* v_cmpx_lt_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35499             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19682 /* v_cmpx_ne_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35500             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19682 /* v_cmpx_ne_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35501             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19682 /* v_cmpx_ne_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35502             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19682 /* v_cmpx_ne_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35503             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19682 /* v_cmpx_ne_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35504             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19682 /* v_cmpx_ne_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35505             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19682 /* v_cmpx_ne_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35506             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19714 /* v_cmpx_ne_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35507             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19714 /* v_cmpx_ne_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35508             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19714 /* v_cmpx_ne_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35509             :   { Feature_HasSDWA|Feature_HasSDWA, 19714 /* v_cmpx_ne_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35510             :   { Feature_HasSDWA|Feature_HasSDWA, 19714 /* v_cmpx_ne_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35511             :   { Feature_HasSDWA|Feature_HasSDWA, 19714 /* v_cmpx_ne_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35512             :   { Feature_HasSDWA|Feature_HasSDWA, 19714 /* v_cmpx_ne_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35513             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19778 /* v_cmpx_ne_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35514             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19778 /* v_cmpx_ne_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35515             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19778 /* v_cmpx_ne_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35516             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19778 /* v_cmpx_ne_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35517             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19778 /* v_cmpx_ne_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35518             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19778 /* v_cmpx_ne_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35519             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19778 /* v_cmpx_ne_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35520             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19810 /* v_cmpx_ne_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35521             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19810 /* v_cmpx_ne_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35522             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19810 /* v_cmpx_ne_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35523             :   { Feature_HasSDWA|Feature_HasSDWA, 19810 /* v_cmpx_ne_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35524             :   { Feature_HasSDWA|Feature_HasSDWA, 19810 /* v_cmpx_ne_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35525             :   { Feature_HasSDWA|Feature_HasSDWA, 19810 /* v_cmpx_ne_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35526             :   { Feature_HasSDWA|Feature_HasSDWA, 19810 /* v_cmpx_ne_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35527             :   { Feature_Has16BitInsts|Feature_isVI, 19874 /* v_cmpx_neq_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35528             :   { Feature_Has16BitInsts|Feature_isVI, 19874 /* v_cmpx_neq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35529             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19874 /* v_cmpx_neq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35530             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19874 /* v_cmpx_neq_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35531             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19874 /* v_cmpx_neq_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35532             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19874 /* v_cmpx_neq_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35533             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19874 /* v_cmpx_neq_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35534             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19874 /* v_cmpx_neq_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35535             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19874 /* v_cmpx_neq_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35536             :   { Feature_isGCN|Feature_isSICI, 19908 /* v_cmpx_neq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35537             :   { Feature_isGCN|Feature_isSICI, 19908 /* v_cmpx_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35538             :   { Feature_isGCN|Feature_isVI, 19908 /* v_cmpx_neq_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35539             :   { Feature_isGCN|Feature_isVI, 19908 /* v_cmpx_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35540             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19908 /* v_cmpx_neq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35541             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19908 /* v_cmpx_neq_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35542             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19908 /* v_cmpx_neq_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35543             :   { Feature_HasSDWA|Feature_HasSDWA, 19908 /* v_cmpx_neq_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35544             :   { Feature_HasSDWA|Feature_HasSDWA, 19908 /* v_cmpx_neq_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35545             :   { Feature_HasSDWA|Feature_HasSDWA, 19908 /* v_cmpx_neq_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35546             :   { Feature_HasSDWA|Feature_HasSDWA, 19908 /* v_cmpx_neq_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35547             :   { Feature_isGCN|Feature_isSICI, 19942 /* v_cmpx_neq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35548             :   { Feature_isGCN|Feature_isSICI, 19942 /* v_cmpx_neq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35549             :   { Feature_isGCN|Feature_isVI, 19942 /* v_cmpx_neq_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35550             :   { Feature_isGCN|Feature_isVI, 19942 /* v_cmpx_neq_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35551             :   { Feature_Has16BitInsts|Feature_isVI, 19976 /* v_cmpx_nge_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35552             :   { Feature_Has16BitInsts|Feature_isVI, 19976 /* v_cmpx_nge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35553             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19976 /* v_cmpx_nge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35554             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19976 /* v_cmpx_nge_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35555             :   { Feature_HasSDWA9|Feature_HasSDWA9, 19976 /* v_cmpx_nge_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35556             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19976 /* v_cmpx_nge_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35557             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19976 /* v_cmpx_nge_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35558             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19976 /* v_cmpx_nge_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35559             :   { Feature_Has16BitInsts|Feature_HasSDWA, 19976 /* v_cmpx_nge_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35560             :   { Feature_isGCN|Feature_isSICI, 20010 /* v_cmpx_nge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35561             :   { Feature_isGCN|Feature_isSICI, 20010 /* v_cmpx_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35562             :   { Feature_isGCN|Feature_isVI, 20010 /* v_cmpx_nge_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35563             :   { Feature_isGCN|Feature_isVI, 20010 /* v_cmpx_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35564             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20010 /* v_cmpx_nge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35565             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20010 /* v_cmpx_nge_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35566             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20010 /* v_cmpx_nge_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35567             :   { Feature_HasSDWA|Feature_HasSDWA, 20010 /* v_cmpx_nge_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35568             :   { Feature_HasSDWA|Feature_HasSDWA, 20010 /* v_cmpx_nge_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35569             :   { Feature_HasSDWA|Feature_HasSDWA, 20010 /* v_cmpx_nge_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35570             :   { Feature_HasSDWA|Feature_HasSDWA, 20010 /* v_cmpx_nge_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35571             :   { Feature_isGCN|Feature_isSICI, 20044 /* v_cmpx_nge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35572             :   { Feature_isGCN|Feature_isSICI, 20044 /* v_cmpx_nge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35573             :   { Feature_isGCN|Feature_isVI, 20044 /* v_cmpx_nge_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35574             :   { Feature_isGCN|Feature_isVI, 20044 /* v_cmpx_nge_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35575             :   { Feature_Has16BitInsts|Feature_isVI, 20078 /* v_cmpx_ngt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35576             :   { Feature_Has16BitInsts|Feature_isVI, 20078 /* v_cmpx_ngt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35577             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20078 /* v_cmpx_ngt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35578             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20078 /* v_cmpx_ngt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35579             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20078 /* v_cmpx_ngt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35580             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20078 /* v_cmpx_ngt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35581             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20078 /* v_cmpx_ngt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35582             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20078 /* v_cmpx_ngt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35583             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20078 /* v_cmpx_ngt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35584             :   { Feature_isGCN|Feature_isSICI, 20112 /* v_cmpx_ngt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35585             :   { Feature_isGCN|Feature_isSICI, 20112 /* v_cmpx_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35586             :   { Feature_isGCN|Feature_isVI, 20112 /* v_cmpx_ngt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35587             :   { Feature_isGCN|Feature_isVI, 20112 /* v_cmpx_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35588             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20112 /* v_cmpx_ngt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35589             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20112 /* v_cmpx_ngt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35590             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20112 /* v_cmpx_ngt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35591             :   { Feature_HasSDWA|Feature_HasSDWA, 20112 /* v_cmpx_ngt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35592             :   { Feature_HasSDWA|Feature_HasSDWA, 20112 /* v_cmpx_ngt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35593             :   { Feature_HasSDWA|Feature_HasSDWA, 20112 /* v_cmpx_ngt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35594             :   { Feature_HasSDWA|Feature_HasSDWA, 20112 /* v_cmpx_ngt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35595             :   { Feature_isGCN|Feature_isSICI, 20146 /* v_cmpx_ngt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35596             :   { Feature_isGCN|Feature_isSICI, 20146 /* v_cmpx_ngt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35597             :   { Feature_isGCN|Feature_isVI, 20146 /* v_cmpx_ngt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35598             :   { Feature_isGCN|Feature_isVI, 20146 /* v_cmpx_ngt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35599             :   { Feature_Has16BitInsts|Feature_isVI, 20180 /* v_cmpx_nle_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35600             :   { Feature_Has16BitInsts|Feature_isVI, 20180 /* v_cmpx_nle_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35601             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20180 /* v_cmpx_nle_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35602             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20180 /* v_cmpx_nle_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35603             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20180 /* v_cmpx_nle_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35604             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20180 /* v_cmpx_nle_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35605             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20180 /* v_cmpx_nle_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35606             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20180 /* v_cmpx_nle_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35607             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20180 /* v_cmpx_nle_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35608             :   { Feature_isGCN|Feature_isSICI, 20214 /* v_cmpx_nle_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35609             :   { Feature_isGCN|Feature_isSICI, 20214 /* v_cmpx_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35610             :   { Feature_isGCN|Feature_isVI, 20214 /* v_cmpx_nle_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35611             :   { Feature_isGCN|Feature_isVI, 20214 /* v_cmpx_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35612             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20214 /* v_cmpx_nle_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35613             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20214 /* v_cmpx_nle_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35614             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20214 /* v_cmpx_nle_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35615             :   { Feature_HasSDWA|Feature_HasSDWA, 20214 /* v_cmpx_nle_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35616             :   { Feature_HasSDWA|Feature_HasSDWA, 20214 /* v_cmpx_nle_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35617             :   { Feature_HasSDWA|Feature_HasSDWA, 20214 /* v_cmpx_nle_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35618             :   { Feature_HasSDWA|Feature_HasSDWA, 20214 /* v_cmpx_nle_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35619             :   { Feature_isGCN|Feature_isSICI, 20248 /* v_cmpx_nle_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35620             :   { Feature_isGCN|Feature_isSICI, 20248 /* v_cmpx_nle_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35621             :   { Feature_isGCN|Feature_isVI, 20248 /* v_cmpx_nle_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35622             :   { Feature_isGCN|Feature_isVI, 20248 /* v_cmpx_nle_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35623             :   { Feature_Has16BitInsts|Feature_isVI, 20282 /* v_cmpx_nlg_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35624             :   { Feature_Has16BitInsts|Feature_isVI, 20282 /* v_cmpx_nlg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35625             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20282 /* v_cmpx_nlg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35626             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20282 /* v_cmpx_nlg_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35627             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20282 /* v_cmpx_nlg_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35628             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20282 /* v_cmpx_nlg_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35629             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20282 /* v_cmpx_nlg_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35630             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20282 /* v_cmpx_nlg_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35631             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20282 /* v_cmpx_nlg_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35632             :   { Feature_isGCN|Feature_isSICI, 20316 /* v_cmpx_nlg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35633             :   { Feature_isGCN|Feature_isSICI, 20316 /* v_cmpx_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35634             :   { Feature_isGCN|Feature_isVI, 20316 /* v_cmpx_nlg_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35635             :   { Feature_isGCN|Feature_isVI, 20316 /* v_cmpx_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35636             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20316 /* v_cmpx_nlg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35637             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20316 /* v_cmpx_nlg_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35638             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20316 /* v_cmpx_nlg_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35639             :   { Feature_HasSDWA|Feature_HasSDWA, 20316 /* v_cmpx_nlg_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35640             :   { Feature_HasSDWA|Feature_HasSDWA, 20316 /* v_cmpx_nlg_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35641             :   { Feature_HasSDWA|Feature_HasSDWA, 20316 /* v_cmpx_nlg_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35642             :   { Feature_HasSDWA|Feature_HasSDWA, 20316 /* v_cmpx_nlg_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35643             :   { Feature_isGCN|Feature_isSICI, 20350 /* v_cmpx_nlg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35644             :   { Feature_isGCN|Feature_isSICI, 20350 /* v_cmpx_nlg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35645             :   { Feature_isGCN|Feature_isVI, 20350 /* v_cmpx_nlg_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35646             :   { Feature_isGCN|Feature_isVI, 20350 /* v_cmpx_nlg_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35647             :   { Feature_Has16BitInsts|Feature_isVI, 20384 /* v_cmpx_nlt_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35648             :   { Feature_Has16BitInsts|Feature_isVI, 20384 /* v_cmpx_nlt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35649             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20384 /* v_cmpx_nlt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35650             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20384 /* v_cmpx_nlt_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35651             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20384 /* v_cmpx_nlt_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35652             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20384 /* v_cmpx_nlt_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35653             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20384 /* v_cmpx_nlt_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35654             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20384 /* v_cmpx_nlt_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35655             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20384 /* v_cmpx_nlt_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35656             :   { Feature_isGCN|Feature_isSICI, 20418 /* v_cmpx_nlt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35657             :   { Feature_isGCN|Feature_isSICI, 20418 /* v_cmpx_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35658             :   { Feature_isGCN|Feature_isVI, 20418 /* v_cmpx_nlt_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35659             :   { Feature_isGCN|Feature_isVI, 20418 /* v_cmpx_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35660             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20418 /* v_cmpx_nlt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35661             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20418 /* v_cmpx_nlt_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35662             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20418 /* v_cmpx_nlt_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35663             :   { Feature_HasSDWA|Feature_HasSDWA, 20418 /* v_cmpx_nlt_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35664             :   { Feature_HasSDWA|Feature_HasSDWA, 20418 /* v_cmpx_nlt_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35665             :   { Feature_HasSDWA|Feature_HasSDWA, 20418 /* v_cmpx_nlt_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35666             :   { Feature_HasSDWA|Feature_HasSDWA, 20418 /* v_cmpx_nlt_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35667             :   { Feature_isGCN|Feature_isSICI, 20452 /* v_cmpx_nlt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35668             :   { Feature_isGCN|Feature_isSICI, 20452 /* v_cmpx_nlt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35669             :   { Feature_isGCN|Feature_isVI, 20452 /* v_cmpx_nlt_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35670             :   { Feature_isGCN|Feature_isVI, 20452 /* v_cmpx_nlt_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35671             :   { Feature_Has16BitInsts|Feature_isVI, 20486 /* v_cmpx_o_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35672             :   { Feature_Has16BitInsts|Feature_isVI, 20486 /* v_cmpx_o_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35673             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20486 /* v_cmpx_o_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35674             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20486 /* v_cmpx_o_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35675             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20486 /* v_cmpx_o_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35676             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20486 /* v_cmpx_o_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35677             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20486 /* v_cmpx_o_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35678             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20486 /* v_cmpx_o_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35679             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20486 /* v_cmpx_o_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35680             :   { Feature_isGCN|Feature_isSICI, 20516 /* v_cmpx_o_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35681             :   { Feature_isGCN|Feature_isSICI, 20516 /* v_cmpx_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35682             :   { Feature_isGCN|Feature_isVI, 20516 /* v_cmpx_o_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35683             :   { Feature_isGCN|Feature_isVI, 20516 /* v_cmpx_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35684             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20516 /* v_cmpx_o_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35685             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20516 /* v_cmpx_o_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35686             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20516 /* v_cmpx_o_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35687             :   { Feature_HasSDWA|Feature_HasSDWA, 20516 /* v_cmpx_o_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35688             :   { Feature_HasSDWA|Feature_HasSDWA, 20516 /* v_cmpx_o_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35689             :   { Feature_HasSDWA|Feature_HasSDWA, 20516 /* v_cmpx_o_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35690             :   { Feature_HasSDWA|Feature_HasSDWA, 20516 /* v_cmpx_o_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35691             :   { Feature_isGCN|Feature_isSICI, 20546 /* v_cmpx_o_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35692             :   { Feature_isGCN|Feature_isSICI, 20546 /* v_cmpx_o_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35693             :   { Feature_isGCN|Feature_isVI, 20546 /* v_cmpx_o_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35694             :   { Feature_isGCN|Feature_isVI, 20546 /* v_cmpx_o_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35695             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20576 /* v_cmpx_t_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35696             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20576 /* v_cmpx_t_i16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35697             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20576 /* v_cmpx_t_i16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35698             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20576 /* v_cmpx_t_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35699             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20576 /* v_cmpx_t_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35700             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20576 /* v_cmpx_t_i16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35701             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20576 /* v_cmpx_t_i16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35702             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20606 /* v_cmpx_t_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35703             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20606 /* v_cmpx_t_i32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35704             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20606 /* v_cmpx_t_i32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35705             :   { Feature_HasSDWA|Feature_HasSDWA, 20606 /* v_cmpx_t_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35706             :   { Feature_HasSDWA|Feature_HasSDWA, 20606 /* v_cmpx_t_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35707             :   { Feature_HasSDWA|Feature_HasSDWA, 20606 /* v_cmpx_t_i32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35708             :   { Feature_HasSDWA|Feature_HasSDWA, 20606 /* v_cmpx_t_i32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35709             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20666 /* v_cmpx_t_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35710             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20666 /* v_cmpx_t_u16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35711             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20666 /* v_cmpx_t_u16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35712             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20666 /* v_cmpx_t_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   35713             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20666 /* v_cmpx_t_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35714             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20666 /* v_cmpx_t_u16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35715             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20666 /* v_cmpx_t_u16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35716             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20696 /* v_cmpx_t_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35717             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20696 /* v_cmpx_t_u32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35718             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20696 /* v_cmpx_t_u32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35719             :   { Feature_HasSDWA|Feature_HasSDWA, 20696 /* v_cmpx_t_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35720             :   { Feature_HasSDWA|Feature_HasSDWA, 20696 /* v_cmpx_t_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35721             :   { Feature_HasSDWA|Feature_HasSDWA, 20696 /* v_cmpx_t_u32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35722             :   { Feature_HasSDWA|Feature_HasSDWA, 20696 /* v_cmpx_t_u32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35723             :   { Feature_Has16BitInsts|Feature_isVI, 20756 /* v_cmpx_tru_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35724             :   { Feature_Has16BitInsts|Feature_isVI, 20756 /* v_cmpx_tru_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35725             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20756 /* v_cmpx_tru_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35726             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20756 /* v_cmpx_tru_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35727             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20756 /* v_cmpx_tru_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35728             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20756 /* v_cmpx_tru_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35729             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20756 /* v_cmpx_tru_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35730             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20756 /* v_cmpx_tru_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35731             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20756 /* v_cmpx_tru_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35732             :   { Feature_isGCN|Feature_isSICI, 20790 /* v_cmpx_tru_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35733             :   { Feature_isGCN|Feature_isSICI, 20790 /* v_cmpx_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35734             :   { Feature_isGCN|Feature_isVI, 20790 /* v_cmpx_tru_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35735             :   { Feature_isGCN|Feature_isVI, 20790 /* v_cmpx_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35736             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20790 /* v_cmpx_tru_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35737             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20790 /* v_cmpx_tru_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35738             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20790 /* v_cmpx_tru_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35739             :   { Feature_HasSDWA|Feature_HasSDWA, 20790 /* v_cmpx_tru_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35740             :   { Feature_HasSDWA|Feature_HasSDWA, 20790 /* v_cmpx_tru_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35741             :   { Feature_HasSDWA|Feature_HasSDWA, 20790 /* v_cmpx_tru_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35742             :   { Feature_HasSDWA|Feature_HasSDWA, 20790 /* v_cmpx_tru_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35743             :   { Feature_isGCN|Feature_isSICI, 20824 /* v_cmpx_tru_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35744             :   { Feature_isGCN|Feature_isSICI, 20824 /* v_cmpx_tru_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35745             :   { Feature_isGCN|Feature_isVI, 20824 /* v_cmpx_tru_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35746             :   { Feature_isGCN|Feature_isVI, 20824 /* v_cmpx_tru_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35747             :   { Feature_Has16BitInsts|Feature_isVI, 20858 /* v_cmpx_u_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   35748             :   { Feature_Has16BitInsts|Feature_isVI, 20858 /* v_cmpx_u_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35749             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20858 /* v_cmpx_u_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35750             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20858 /* v_cmpx_u_f16 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35751             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20858 /* v_cmpx_u_f16 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35752             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20858 /* v_cmpx_u_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   35753             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20858 /* v_cmpx_u_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   35754             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20858 /* v_cmpx_u_f16 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35755             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20858 /* v_cmpx_u_f16 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35756             :   { Feature_isGCN|Feature_isSICI, 20888 /* v_cmpx_u_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35757             :   { Feature_isGCN|Feature_isSICI, 20888 /* v_cmpx_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35758             :   { Feature_isGCN|Feature_isVI, 20888 /* v_cmpx_u_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   35759             :   { Feature_isGCN|Feature_isVI, 20888 /* v_cmpx_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35760             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20888 /* v_cmpx_u_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35761             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20888 /* v_cmpx_u_f32 */, MCK_ImmSDWASrc0Sel, 8 /* 3 */ },
   35762             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20888 /* v_cmpx_u_f32 */, MCK_ImmSDWASrc1Sel, 16 /* 4 */ },
   35763             :   { Feature_HasSDWA|Feature_HasSDWA, 20888 /* v_cmpx_u_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   35764             :   { Feature_HasSDWA|Feature_HasSDWA, 20888 /* v_cmpx_u_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   35765             :   { Feature_HasSDWA|Feature_HasSDWA, 20888 /* v_cmpx_u_f32 */, MCK_ImmSDWASrc0Sel, 16 /* 4 */ },
   35766             :   { Feature_HasSDWA|Feature_HasSDWA, 20888 /* v_cmpx_u_f32 */, MCK_ImmSDWASrc1Sel, 32 /* 5 */ },
   35767             :   { Feature_isGCN|Feature_isSICI, 20918 /* v_cmpx_u_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35768             :   { Feature_isGCN|Feature_isSICI, 20918 /* v_cmpx_u_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35769             :   { Feature_isGCN|Feature_isVI, 20918 /* v_cmpx_u_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   35770             :   { Feature_isGCN|Feature_isVI, 20918 /* v_cmpx_u_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   35771             :   { Feature_HasDPP|Feature_HasDPP, 20948 /* v_cndmask_b32 */, MCK_ImmDPPCtrl, 16 /* 4 */ },
   35772             :   { Feature_HasDPP|Feature_HasDPP, 20948 /* v_cndmask_b32 */, MCK_ImmRowMask, 32 /* 5 */ },
   35773             :   { Feature_HasDPP|Feature_HasDPP, 20948 /* v_cndmask_b32 */, MCK_ImmBankMask, 64 /* 6 */ },
   35774             :   { Feature_HasDPP|Feature_HasDPP, 20948 /* v_cndmask_b32 */, MCK_ImmBoundCtrl, 128 /* 7 */ },
   35775             :   { Feature_isGCN|Feature_HasSDWA, 20948 /* v_cndmask_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35776             :   { Feature_isGCN|Feature_HasSDWA, 20948 /* v_cndmask_b32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35777             :   { Feature_isGCN|Feature_HasSDWA, 20948 /* v_cndmask_b32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   35778             :   { Feature_isGCN|Feature_HasSDWA, 20948 /* v_cndmask_b32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   35779             :   { Feature_isGCN|Feature_HasSDWA, 20948 /* v_cndmask_b32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   35780             :   { Feature_isGCN|Feature_HasSDWA, 20948 /* v_cndmask_b32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   35781             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20948 /* v_cndmask_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   35782             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20948 /* v_cndmask_b32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35783             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20948 /* v_cndmask_b32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   35784             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20948 /* v_cndmask_b32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   35785             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20948 /* v_cndmask_b32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   35786             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20948 /* v_cndmask_b32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   35787             :   { Feature_Has16BitInsts|Feature_isVI, 20962 /* v_cos_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   35788             :   { Feature_Has16BitInsts|Feature_isVI, 20962 /* v_cos_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35789             :   { Feature_Has16BitInsts|Feature_isVI, 20962 /* v_cos_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35790             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20962 /* v_cos_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   35791             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20962 /* v_cos_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35792             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20962 /* v_cos_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35793             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20962 /* v_cos_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35794             :   { Feature_Has16BitInsts|Feature_HasSDWA, 20962 /* v_cos_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35795             :   { Feature_HasDPP|Feature_HasDPP, 20962 /* v_cos_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   35796             :   { Feature_HasDPP|Feature_HasDPP, 20962 /* v_cos_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35797             :   { Feature_HasDPP|Feature_HasDPP, 20962 /* v_cos_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   35798             :   { Feature_HasDPP|Feature_HasDPP, 20962 /* v_cos_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   35799             :   { Feature_HasDPP|Feature_HasDPP, 20962 /* v_cos_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35800             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20962 /* v_cos_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   35801             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20962 /* v_cos_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35802             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20962 /* v_cos_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35803             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20962 /* v_cos_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35804             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20962 /* v_cos_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35805             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20962 /* v_cos_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35806             :   { Feature_isGCN|Feature_isSICI, 20972 /* v_cos_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   35807             :   { Feature_isGCN|Feature_isSICI, 20972 /* v_cos_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35808             :   { Feature_isGCN|Feature_isSICI, 20972 /* v_cos_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35809             :   { Feature_isGCN|Feature_isVI, 20972 /* v_cos_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   35810             :   { Feature_isGCN|Feature_isVI, 20972 /* v_cos_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35811             :   { Feature_isGCN|Feature_isVI, 20972 /* v_cos_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35812             :   { Feature_HasSDWA|Feature_HasSDWA, 20972 /* v_cos_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   35813             :   { Feature_HasSDWA|Feature_HasSDWA, 20972 /* v_cos_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35814             :   { Feature_HasSDWA|Feature_HasSDWA, 20972 /* v_cos_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35815             :   { Feature_HasSDWA|Feature_HasSDWA, 20972 /* v_cos_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35816             :   { Feature_HasSDWA|Feature_HasSDWA, 20972 /* v_cos_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35817             :   { Feature_HasDPP|Feature_HasDPP, 20972 /* v_cos_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   35818             :   { Feature_HasDPP|Feature_HasDPP, 20972 /* v_cos_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35819             :   { Feature_HasDPP|Feature_HasDPP, 20972 /* v_cos_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   35820             :   { Feature_HasDPP|Feature_HasDPP, 20972 /* v_cos_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   35821             :   { Feature_HasDPP|Feature_HasDPP, 20972 /* v_cos_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35822             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20972 /* v_cos_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   35823             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20972 /* v_cos_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35824             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20972 /* v_cos_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35825             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20972 /* v_cos_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35826             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20972 /* v_cos_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35827             :   { Feature_HasSDWA9|Feature_HasSDWA9, 20972 /* v_cos_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35828             :   { Feature_isGCN|Feature_isSICI, 20982 /* v_cubeid_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35829             :   { Feature_isGCN|Feature_isSICI, 20982 /* v_cubeid_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35830             :   { Feature_isGCN|Feature_isSICI, 20982 /* v_cubeid_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35831             :   { Feature_isGCN|Feature_isVI, 20982 /* v_cubeid_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35832             :   { Feature_isGCN|Feature_isVI, 20982 /* v_cubeid_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35833             :   { Feature_isGCN|Feature_isVI, 20982 /* v_cubeid_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35834             :   { Feature_isGCN|Feature_isSICI, 20995 /* v_cubema_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35835             :   { Feature_isGCN|Feature_isSICI, 20995 /* v_cubema_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35836             :   { Feature_isGCN|Feature_isSICI, 20995 /* v_cubema_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35837             :   { Feature_isGCN|Feature_isVI, 20995 /* v_cubema_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35838             :   { Feature_isGCN|Feature_isVI, 20995 /* v_cubema_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35839             :   { Feature_isGCN|Feature_isVI, 20995 /* v_cubema_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35840             :   { Feature_isGCN|Feature_isSICI, 21008 /* v_cubesc_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35841             :   { Feature_isGCN|Feature_isSICI, 21008 /* v_cubesc_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35842             :   { Feature_isGCN|Feature_isSICI, 21008 /* v_cubesc_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35843             :   { Feature_isGCN|Feature_isVI, 21008 /* v_cubesc_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35844             :   { Feature_isGCN|Feature_isVI, 21008 /* v_cubesc_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35845             :   { Feature_isGCN|Feature_isVI, 21008 /* v_cubesc_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35846             :   { Feature_isGCN|Feature_isSICI, 21021 /* v_cubetc_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35847             :   { Feature_isGCN|Feature_isSICI, 21021 /* v_cubetc_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35848             :   { Feature_isGCN|Feature_isSICI, 21021 /* v_cubetc_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35849             :   { Feature_isGCN|Feature_isVI, 21021 /* v_cubetc_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   35850             :   { Feature_isGCN|Feature_isVI, 21021 /* v_cubetc_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   35851             :   { Feature_isGCN|Feature_isVI, 21021 /* v_cubetc_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   35852             :   { Feature_isGCN|Feature_isSICI, 21034 /* v_cvt_f16_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   35853             :   { Feature_isGCN|Feature_isSICI, 21034 /* v_cvt_f16_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35854             :   { Feature_isGCN|Feature_isSICI, 21034 /* v_cvt_f16_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35855             :   { Feature_isGCN|Feature_isVI, 21034 /* v_cvt_f16_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   35856             :   { Feature_isGCN|Feature_isVI, 21034 /* v_cvt_f16_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35857             :   { Feature_isGCN|Feature_isVI, 21034 /* v_cvt_f16_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35858             :   { Feature_HasSDWA|Feature_HasSDWA, 21034 /* v_cvt_f16_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   35859             :   { Feature_HasSDWA|Feature_HasSDWA, 21034 /* v_cvt_f16_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35860             :   { Feature_HasSDWA|Feature_HasSDWA, 21034 /* v_cvt_f16_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35861             :   { Feature_HasSDWA|Feature_HasSDWA, 21034 /* v_cvt_f16_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35862             :   { Feature_HasSDWA|Feature_HasSDWA, 21034 /* v_cvt_f16_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35863             :   { Feature_HasDPP|Feature_HasDPP, 21034 /* v_cvt_f16_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   35864             :   { Feature_HasDPP|Feature_HasDPP, 21034 /* v_cvt_f16_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35865             :   { Feature_HasDPP|Feature_HasDPP, 21034 /* v_cvt_f16_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   35866             :   { Feature_HasDPP|Feature_HasDPP, 21034 /* v_cvt_f16_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   35867             :   { Feature_HasDPP|Feature_HasDPP, 21034 /* v_cvt_f16_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35868             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21034 /* v_cvt_f16_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   35869             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21034 /* v_cvt_f16_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35870             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21034 /* v_cvt_f16_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35871             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21034 /* v_cvt_f16_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35872             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21034 /* v_cvt_f16_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35873             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21034 /* v_cvt_f16_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35874             :   { Feature_Has16BitInsts|Feature_isVI, 21048 /* v_cvt_f16_i16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35875             :   { Feature_Has16BitInsts|Feature_isVI, 21048 /* v_cvt_f16_i16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35876             :   { Feature_HasDPP|Feature_HasDPP, 21048 /* v_cvt_f16_i16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35877             :   { Feature_HasDPP|Feature_HasDPP, 21048 /* v_cvt_f16_i16 */, MCK_ImmRowMask, 8 /* 3 */ },
   35878             :   { Feature_HasDPP|Feature_HasDPP, 21048 /* v_cvt_f16_i16 */, MCK_ImmBankMask, 16 /* 4 */ },
   35879             :   { Feature_HasDPP|Feature_HasDPP, 21048 /* v_cvt_f16_i16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35880             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21048 /* v_cvt_f16_i16 */, MCK_SDWAWithInt16InputMods, 2 /* 1 */ },
   35881             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21048 /* v_cvt_f16_i16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35882             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21048 /* v_cvt_f16_i16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35883             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21048 /* v_cvt_f16_i16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35884             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21048 /* v_cvt_f16_i16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35885             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21048 /* v_cvt_f16_i16 */, MCK_SDWAWithInt16InputMods, 2 /* 1 */ },
   35886             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21048 /* v_cvt_f16_i16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35887             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21048 /* v_cvt_f16_i16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35888             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21048 /* v_cvt_f16_i16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35889             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21048 /* v_cvt_f16_i16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35890             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21048 /* v_cvt_f16_i16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35891             :   { Feature_Has16BitInsts|Feature_isVI, 21062 /* v_cvt_f16_u16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35892             :   { Feature_Has16BitInsts|Feature_isVI, 21062 /* v_cvt_f16_u16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35893             :   { Feature_HasDPP|Feature_HasDPP, 21062 /* v_cvt_f16_u16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35894             :   { Feature_HasDPP|Feature_HasDPP, 21062 /* v_cvt_f16_u16 */, MCK_ImmRowMask, 8 /* 3 */ },
   35895             :   { Feature_HasDPP|Feature_HasDPP, 21062 /* v_cvt_f16_u16 */, MCK_ImmBankMask, 16 /* 4 */ },
   35896             :   { Feature_HasDPP|Feature_HasDPP, 21062 /* v_cvt_f16_u16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35897             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21062 /* v_cvt_f16_u16 */, MCK_SDWAWithInt16InputMods, 2 /* 1 */ },
   35898             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21062 /* v_cvt_f16_u16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35899             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21062 /* v_cvt_f16_u16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35900             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21062 /* v_cvt_f16_u16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35901             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21062 /* v_cvt_f16_u16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35902             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21062 /* v_cvt_f16_u16 */, MCK_SDWAWithInt16InputMods, 2 /* 1 */ },
   35903             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21062 /* v_cvt_f16_u16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35904             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21062 /* v_cvt_f16_u16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35905             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21062 /* v_cvt_f16_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35906             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21062 /* v_cvt_f16_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35907             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21062 /* v_cvt_f16_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35908             :   { Feature_isGCN|Feature_isSICI, 21076 /* v_cvt_f32_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   35909             :   { Feature_isGCN|Feature_isSICI, 21076 /* v_cvt_f32_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35910             :   { Feature_isGCN|Feature_isSICI, 21076 /* v_cvt_f32_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35911             :   { Feature_isGCN|Feature_isVI, 21076 /* v_cvt_f32_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   35912             :   { Feature_isGCN|Feature_isVI, 21076 /* v_cvt_f32_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35913             :   { Feature_isGCN|Feature_isVI, 21076 /* v_cvt_f32_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35914             :   { Feature_HasSDWA|Feature_HasSDWA, 21076 /* v_cvt_f32_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   35915             :   { Feature_HasSDWA|Feature_HasSDWA, 21076 /* v_cvt_f32_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35916             :   { Feature_HasSDWA|Feature_HasSDWA, 21076 /* v_cvt_f32_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35917             :   { Feature_HasSDWA|Feature_HasSDWA, 21076 /* v_cvt_f32_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35918             :   { Feature_HasSDWA|Feature_HasSDWA, 21076 /* v_cvt_f32_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35919             :   { Feature_HasDPP|Feature_HasDPP, 21076 /* v_cvt_f32_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   35920             :   { Feature_HasDPP|Feature_HasDPP, 21076 /* v_cvt_f32_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35921             :   { Feature_HasDPP|Feature_HasDPP, 21076 /* v_cvt_f32_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   35922             :   { Feature_HasDPP|Feature_HasDPP, 21076 /* v_cvt_f32_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   35923             :   { Feature_HasDPP|Feature_HasDPP, 21076 /* v_cvt_f32_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35924             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21076 /* v_cvt_f32_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   35925             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21076 /* v_cvt_f32_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   35926             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21076 /* v_cvt_f32_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   35927             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21076 /* v_cvt_f32_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35928             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21076 /* v_cvt_f32_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35929             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21076 /* v_cvt_f32_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35930             :   { Feature_isGCN|Feature_isSICI, 21090 /* v_cvt_f32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   35931             :   { Feature_isGCN|Feature_isSICI, 21090 /* v_cvt_f32_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   35932             :   { Feature_isGCN|Feature_isSICI, 21090 /* v_cvt_f32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   35933             :   { Feature_isGCN|Feature_isVI, 21090 /* v_cvt_f32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   35934             :   { Feature_isGCN|Feature_isVI, 21090 /* v_cvt_f32_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   35935             :   { Feature_isGCN|Feature_isVI, 21090 /* v_cvt_f32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   35936             :   { Feature_isGCN|Feature_isSICI, 21104 /* v_cvt_f32_i32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35937             :   { Feature_isGCN|Feature_isSICI, 21104 /* v_cvt_f32_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35938             :   { Feature_isGCN|Feature_isVI, 21104 /* v_cvt_f32_i32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35939             :   { Feature_isGCN|Feature_isVI, 21104 /* v_cvt_f32_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35940             :   { Feature_HasDPP|Feature_HasDPP, 21104 /* v_cvt_f32_i32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35941             :   { Feature_HasDPP|Feature_HasDPP, 21104 /* v_cvt_f32_i32 */, MCK_ImmRowMask, 8 /* 3 */ },
   35942             :   { Feature_HasDPP|Feature_HasDPP, 21104 /* v_cvt_f32_i32 */, MCK_ImmBankMask, 16 /* 4 */ },
   35943             :   { Feature_HasDPP|Feature_HasDPP, 21104 /* v_cvt_f32_i32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35944             :   { Feature_HasSDWA|Feature_HasSDWA, 21104 /* v_cvt_f32_i32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   35945             :   { Feature_HasSDWA|Feature_HasSDWA, 21104 /* v_cvt_f32_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35946             :   { Feature_HasSDWA|Feature_HasSDWA, 21104 /* v_cvt_f32_i32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35947             :   { Feature_HasSDWA|Feature_HasSDWA, 21104 /* v_cvt_f32_i32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35948             :   { Feature_HasSDWA|Feature_HasSDWA, 21104 /* v_cvt_f32_i32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35949             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21104 /* v_cvt_f32_i32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   35950             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21104 /* v_cvt_f32_i32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35951             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21104 /* v_cvt_f32_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35952             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21104 /* v_cvt_f32_i32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35953             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21104 /* v_cvt_f32_i32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35954             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21104 /* v_cvt_f32_i32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35955             :   { Feature_isGCN|Feature_isSICI, 21118 /* v_cvt_f32_u32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35956             :   { Feature_isGCN|Feature_isSICI, 21118 /* v_cvt_f32_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35957             :   { Feature_isGCN|Feature_isVI, 21118 /* v_cvt_f32_u32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35958             :   { Feature_isGCN|Feature_isVI, 21118 /* v_cvt_f32_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35959             :   { Feature_HasDPP|Feature_HasDPP, 21118 /* v_cvt_f32_u32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35960             :   { Feature_HasDPP|Feature_HasDPP, 21118 /* v_cvt_f32_u32 */, MCK_ImmRowMask, 8 /* 3 */ },
   35961             :   { Feature_HasDPP|Feature_HasDPP, 21118 /* v_cvt_f32_u32 */, MCK_ImmBankMask, 16 /* 4 */ },
   35962             :   { Feature_HasDPP|Feature_HasDPP, 21118 /* v_cvt_f32_u32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35963             :   { Feature_HasSDWA|Feature_HasSDWA, 21118 /* v_cvt_f32_u32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   35964             :   { Feature_HasSDWA|Feature_HasSDWA, 21118 /* v_cvt_f32_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35965             :   { Feature_HasSDWA|Feature_HasSDWA, 21118 /* v_cvt_f32_u32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35966             :   { Feature_HasSDWA|Feature_HasSDWA, 21118 /* v_cvt_f32_u32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35967             :   { Feature_HasSDWA|Feature_HasSDWA, 21118 /* v_cvt_f32_u32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35968             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21118 /* v_cvt_f32_u32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   35969             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21118 /* v_cvt_f32_u32 */, MCK_ImmOModSI, 8 /* 3 */ },
   35970             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21118 /* v_cvt_f32_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   35971             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21118 /* v_cvt_f32_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35972             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21118 /* v_cvt_f32_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35973             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21118 /* v_cvt_f32_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35974             :   { Feature_isGCN|Feature_isSICI, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmOModSI, 8 /* 3 */ },
   35975             :   { Feature_isGCN|Feature_isSICI, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmClampSI, 4 /* 2 */ },
   35976             :   { Feature_isGCN|Feature_isVI, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmOModSI, 8 /* 3 */ },
   35977             :   { Feature_isGCN|Feature_isVI, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmClampSI, 4 /* 2 */ },
   35978             :   { Feature_HasDPP|Feature_HasDPP, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35979             :   { Feature_HasDPP|Feature_HasDPP, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmRowMask, 8 /* 3 */ },
   35980             :   { Feature_HasDPP|Feature_HasDPP, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmBankMask, 16 /* 4 */ },
   35981             :   { Feature_HasDPP|Feature_HasDPP, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   35982             :   { Feature_HasSDWA|Feature_HasSDWA, 21132 /* v_cvt_f32_ubyte0 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   35983             :   { Feature_HasSDWA|Feature_HasSDWA, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmClampSI, 4 /* 2 */ },
   35984             :   { Feature_HasSDWA|Feature_HasSDWA, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   35985             :   { Feature_HasSDWA|Feature_HasSDWA, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   35986             :   { Feature_HasSDWA|Feature_HasSDWA, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   35987             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21132 /* v_cvt_f32_ubyte0 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   35988             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmOModSI, 8 /* 3 */ },
   35989             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmClampSI, 4 /* 2 */ },
   35990             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   35991             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   35992             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21132 /* v_cvt_f32_ubyte0 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   35993             :   { Feature_isGCN|Feature_isSICI, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmOModSI, 8 /* 3 */ },
   35994             :   { Feature_isGCN|Feature_isSICI, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmClampSI, 4 /* 2 */ },
   35995             :   { Feature_isGCN|Feature_isVI, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmOModSI, 8 /* 3 */ },
   35996             :   { Feature_isGCN|Feature_isVI, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmClampSI, 4 /* 2 */ },
   35997             :   { Feature_HasDPP|Feature_HasDPP, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   35998             :   { Feature_HasDPP|Feature_HasDPP, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmRowMask, 8 /* 3 */ },
   35999             :   { Feature_HasDPP|Feature_HasDPP, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmBankMask, 16 /* 4 */ },
   36000             :   { Feature_HasDPP|Feature_HasDPP, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36001             :   { Feature_HasSDWA|Feature_HasSDWA, 21149 /* v_cvt_f32_ubyte1 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36002             :   { Feature_HasSDWA|Feature_HasSDWA, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmClampSI, 4 /* 2 */ },
   36003             :   { Feature_HasSDWA|Feature_HasSDWA, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36004             :   { Feature_HasSDWA|Feature_HasSDWA, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36005             :   { Feature_HasSDWA|Feature_HasSDWA, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36006             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21149 /* v_cvt_f32_ubyte1 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36007             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmOModSI, 8 /* 3 */ },
   36008             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmClampSI, 4 /* 2 */ },
   36009             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36010             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36011             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21149 /* v_cvt_f32_ubyte1 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36012             :   { Feature_isGCN|Feature_isSICI, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmOModSI, 8 /* 3 */ },
   36013             :   { Feature_isGCN|Feature_isSICI, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmClampSI, 4 /* 2 */ },
   36014             :   { Feature_isGCN|Feature_isVI, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmOModSI, 8 /* 3 */ },
   36015             :   { Feature_isGCN|Feature_isVI, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmClampSI, 4 /* 2 */ },
   36016             :   { Feature_HasDPP|Feature_HasDPP, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36017             :   { Feature_HasDPP|Feature_HasDPP, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmRowMask, 8 /* 3 */ },
   36018             :   { Feature_HasDPP|Feature_HasDPP, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmBankMask, 16 /* 4 */ },
   36019             :   { Feature_HasDPP|Feature_HasDPP, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36020             :   { Feature_HasSDWA|Feature_HasSDWA, 21166 /* v_cvt_f32_ubyte2 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36021             :   { Feature_HasSDWA|Feature_HasSDWA, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmClampSI, 4 /* 2 */ },
   36022             :   { Feature_HasSDWA|Feature_HasSDWA, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36023             :   { Feature_HasSDWA|Feature_HasSDWA, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36024             :   { Feature_HasSDWA|Feature_HasSDWA, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36025             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21166 /* v_cvt_f32_ubyte2 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36026             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmOModSI, 8 /* 3 */ },
   36027             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmClampSI, 4 /* 2 */ },
   36028             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36029             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36030             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21166 /* v_cvt_f32_ubyte2 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36031             :   { Feature_isGCN|Feature_isSICI, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmOModSI, 8 /* 3 */ },
   36032             :   { Feature_isGCN|Feature_isSICI, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmClampSI, 4 /* 2 */ },
   36033             :   { Feature_isGCN|Feature_isVI, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmOModSI, 8 /* 3 */ },
   36034             :   { Feature_isGCN|Feature_isVI, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmClampSI, 4 /* 2 */ },
   36035             :   { Feature_HasDPP|Feature_HasDPP, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36036             :   { Feature_HasDPP|Feature_HasDPP, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmRowMask, 8 /* 3 */ },
   36037             :   { Feature_HasDPP|Feature_HasDPP, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmBankMask, 16 /* 4 */ },
   36038             :   { Feature_HasDPP|Feature_HasDPP, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36039             :   { Feature_HasSDWA|Feature_HasSDWA, 21183 /* v_cvt_f32_ubyte3 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36040             :   { Feature_HasSDWA|Feature_HasSDWA, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmClampSI, 4 /* 2 */ },
   36041             :   { Feature_HasSDWA|Feature_HasSDWA, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36042             :   { Feature_HasSDWA|Feature_HasSDWA, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36043             :   { Feature_HasSDWA|Feature_HasSDWA, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36044             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21183 /* v_cvt_f32_ubyte3 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36045             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmOModSI, 8 /* 3 */ },
   36046             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmClampSI, 4 /* 2 */ },
   36047             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36048             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36049             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21183 /* v_cvt_f32_ubyte3 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36050             :   { Feature_isGCN|Feature_isSICI, 21200 /* v_cvt_f64_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36051             :   { Feature_isGCN|Feature_isSICI, 21200 /* v_cvt_f64_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36052             :   { Feature_isGCN|Feature_isSICI, 21200 /* v_cvt_f64_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36053             :   { Feature_isGCN|Feature_isVI, 21200 /* v_cvt_f64_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36054             :   { Feature_isGCN|Feature_isVI, 21200 /* v_cvt_f64_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36055             :   { Feature_isGCN|Feature_isVI, 21200 /* v_cvt_f64_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36056             :   { Feature_isGCN|Feature_isSICI, 21214 /* v_cvt_f64_i32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36057             :   { Feature_isGCN|Feature_isSICI, 21214 /* v_cvt_f64_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36058             :   { Feature_isGCN|Feature_isVI, 21214 /* v_cvt_f64_i32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36059             :   { Feature_isGCN|Feature_isVI, 21214 /* v_cvt_f64_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36060             :   { Feature_isGCN|Feature_isSICI, 21228 /* v_cvt_f64_u32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36061             :   { Feature_isGCN|Feature_isSICI, 21228 /* v_cvt_f64_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36062             :   { Feature_isGCN|Feature_isVI, 21228 /* v_cvt_f64_u32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36063             :   { Feature_isGCN|Feature_isVI, 21228 /* v_cvt_f64_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36064             :   { Feature_isGCN|Feature_isSICI, 21242 /* v_cvt_flr_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36065             :   { Feature_isGCN|Feature_isSICI, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36066             :   { Feature_isGCN|Feature_isVI, 21242 /* v_cvt_flr_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36067             :   { Feature_isGCN|Feature_isVI, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36068             :   { Feature_HasSDWA|Feature_HasSDWA, 21242 /* v_cvt_flr_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36069             :   { Feature_HasSDWA|Feature_HasSDWA, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36070             :   { Feature_HasSDWA|Feature_HasSDWA, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36071             :   { Feature_HasSDWA|Feature_HasSDWA, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36072             :   { Feature_HasSDWA|Feature_HasSDWA, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36073             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21242 /* v_cvt_flr_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36074             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36075             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36076             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36077             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36078             :   { Feature_HasDPP|Feature_HasDPP, 21242 /* v_cvt_flr_i32_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36079             :   { Feature_HasDPP|Feature_HasDPP, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36080             :   { Feature_HasDPP|Feature_HasDPP, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36081             :   { Feature_HasDPP|Feature_HasDPP, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36082             :   { Feature_HasDPP|Feature_HasDPP, 21242 /* v_cvt_flr_i32_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36083             :   { Feature_Has16BitInsts|Feature_isVI, 21260 /* v_cvt_i16_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36084             :   { Feature_Has16BitInsts|Feature_isVI, 21260 /* v_cvt_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36085             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21260 /* v_cvt_i16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36086             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21260 /* v_cvt_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36087             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21260 /* v_cvt_i16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36088             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21260 /* v_cvt_i16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36089             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21260 /* v_cvt_i16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36090             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21260 /* v_cvt_i16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36091             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21260 /* v_cvt_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36092             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21260 /* v_cvt_i16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36093             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21260 /* v_cvt_i16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36094             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21260 /* v_cvt_i16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36095             :   { Feature_HasDPP|Feature_HasDPP, 21260 /* v_cvt_i16_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36096             :   { Feature_HasDPP|Feature_HasDPP, 21260 /* v_cvt_i16_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36097             :   { Feature_HasDPP|Feature_HasDPP, 21260 /* v_cvt_i16_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36098             :   { Feature_HasDPP|Feature_HasDPP, 21260 /* v_cvt_i16_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36099             :   { Feature_HasDPP|Feature_HasDPP, 21260 /* v_cvt_i16_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36100             :   { Feature_isGCN|Feature_isSICI, 21274 /* v_cvt_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36101             :   { Feature_isGCN|Feature_isSICI, 21274 /* v_cvt_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36102             :   { Feature_isGCN|Feature_isVI, 21274 /* v_cvt_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36103             :   { Feature_isGCN|Feature_isVI, 21274 /* v_cvt_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36104             :   { Feature_HasSDWA|Feature_HasSDWA, 21274 /* v_cvt_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36105             :   { Feature_HasSDWA|Feature_HasSDWA, 21274 /* v_cvt_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36106             :   { Feature_HasSDWA|Feature_HasSDWA, 21274 /* v_cvt_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36107             :   { Feature_HasSDWA|Feature_HasSDWA, 21274 /* v_cvt_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36108             :   { Feature_HasSDWA|Feature_HasSDWA, 21274 /* v_cvt_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36109             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21274 /* v_cvt_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36110             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21274 /* v_cvt_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36111             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21274 /* v_cvt_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36112             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21274 /* v_cvt_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36113             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21274 /* v_cvt_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36114             :   { Feature_HasDPP|Feature_HasDPP, 21274 /* v_cvt_i32_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36115             :   { Feature_HasDPP|Feature_HasDPP, 21274 /* v_cvt_i32_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36116             :   { Feature_HasDPP|Feature_HasDPP, 21274 /* v_cvt_i32_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36117             :   { Feature_HasDPP|Feature_HasDPP, 21274 /* v_cvt_i32_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36118             :   { Feature_HasDPP|Feature_HasDPP, 21274 /* v_cvt_i32_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36119             :   { Feature_isGCN|Feature_isSICI, 21288 /* v_cvt_i32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36120             :   { Feature_isGCN|Feature_isSICI, 21288 /* v_cvt_i32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36121             :   { Feature_isGCN|Feature_isVI, 21288 /* v_cvt_i32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36122             :   { Feature_isGCN|Feature_isVI, 21288 /* v_cvt_i32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36123             :   { Feature_isGFX9|Feature_isVI, 21302 /* v_cvt_norm_i16_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36124             :   { Feature_isGFX9|Feature_isVI, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36125             :   { Feature_isGFX9|Feature_HasSDWA, 21302 /* v_cvt_norm_i16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36126             :   { Feature_isGFX9|Feature_HasSDWA, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36127             :   { Feature_isGFX9|Feature_HasSDWA, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36128             :   { Feature_isGFX9|Feature_HasSDWA, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36129             :   { Feature_isGFX9|Feature_HasSDWA, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36130             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21302 /* v_cvt_norm_i16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36131             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36132             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36133             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36134             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36135             :   { Feature_HasDPP|Feature_HasDPP, 21302 /* v_cvt_norm_i16_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36136             :   { Feature_HasDPP|Feature_HasDPP, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36137             :   { Feature_HasDPP|Feature_HasDPP, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36138             :   { Feature_HasDPP|Feature_HasDPP, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36139             :   { Feature_HasDPP|Feature_HasDPP, 21302 /* v_cvt_norm_i16_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36140             :   { Feature_isGFX9|Feature_isVI, 21321 /* v_cvt_norm_u16_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36141             :   { Feature_isGFX9|Feature_isVI, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36142             :   { Feature_isGFX9|Feature_HasSDWA, 21321 /* v_cvt_norm_u16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36143             :   { Feature_isGFX9|Feature_HasSDWA, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36144             :   { Feature_isGFX9|Feature_HasSDWA, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36145             :   { Feature_isGFX9|Feature_HasSDWA, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36146             :   { Feature_isGFX9|Feature_HasSDWA, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36147             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21321 /* v_cvt_norm_u16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36148             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36149             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36150             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36151             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36152             :   { Feature_HasDPP|Feature_HasDPP, 21321 /* v_cvt_norm_u16_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36153             :   { Feature_HasDPP|Feature_HasDPP, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36154             :   { Feature_HasDPP|Feature_HasDPP, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36155             :   { Feature_HasDPP|Feature_HasDPP, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36156             :   { Feature_HasDPP|Feature_HasDPP, 21321 /* v_cvt_norm_u16_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36157             :   { Feature_isGCN|Feature_isSICI, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmOModSI, 8 /* 3 */ },
   36158             :   { Feature_isGCN|Feature_isSICI, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmClampSI, 4 /* 2 */ },
   36159             :   { Feature_isGCN|Feature_isVI, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmOModSI, 8 /* 3 */ },
   36160             :   { Feature_isGCN|Feature_isVI, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmClampSI, 4 /* 2 */ },
   36161             :   { Feature_HasDPP|Feature_HasDPP, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36162             :   { Feature_HasDPP|Feature_HasDPP, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmRowMask, 8 /* 3 */ },
   36163             :   { Feature_HasDPP|Feature_HasDPP, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmBankMask, 16 /* 4 */ },
   36164             :   { Feature_HasDPP|Feature_HasDPP, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36165             :   { Feature_HasSDWA|Feature_HasSDWA, 21340 /* v_cvt_off_f32_i4 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36166             :   { Feature_HasSDWA|Feature_HasSDWA, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmClampSI, 4 /* 2 */ },
   36167             :   { Feature_HasSDWA|Feature_HasSDWA, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36168             :   { Feature_HasSDWA|Feature_HasSDWA, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36169             :   { Feature_HasSDWA|Feature_HasSDWA, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36170             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21340 /* v_cvt_off_f32_i4 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36171             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmOModSI, 8 /* 3 */ },
   36172             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmClampSI, 4 /* 2 */ },
   36173             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36174             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36175             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21340 /* v_cvt_off_f32_i4 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36176             :   { Feature_isGCN|Feature_isSICI, 21391 /* v_cvt_pk_u8_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36177             :   { Feature_isGCN|Feature_isSICI, 21391 /* v_cvt_pk_u8_f32 */, MCK_RegOrImmWithInt32InputMods, 12 /* 2, 3 */ },
   36178             :   { Feature_isGCN|Feature_isSICI, 21391 /* v_cvt_pk_u8_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36179             :   { Feature_isGCN|Feature_isVI, 21391 /* v_cvt_pk_u8_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36180             :   { Feature_isGCN|Feature_isVI, 21391 /* v_cvt_pk_u8_f32 */, MCK_RegOrImmWithInt32InputMods, 12 /* 2, 3 */ },
   36181             :   { Feature_isGCN|Feature_isVI, 21391 /* v_cvt_pk_u8_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36182             :   { Feature_isGCN|Feature_isSICI, 21407 /* v_cvt_pkaccum_u8_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36183             :   { Feature_isGCN|Feature_isSICI, 21407 /* v_cvt_pkaccum_u8_f32 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   36184             :   { Feature_isGCN|Feature_isSICI, 21407 /* v_cvt_pkaccum_u8_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36185             :   { Feature_isGCN|Feature_isVI, 21407 /* v_cvt_pkaccum_u8_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36186             :   { Feature_isGCN|Feature_isVI, 21407 /* v_cvt_pkaccum_u8_f32 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   36187             :   { Feature_isGCN|Feature_isVI, 21407 /* v_cvt_pkaccum_u8_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36188             :   { Feature_isGFX9|Feature_isVI, 21428 /* v_cvt_pknorm_i16_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   36189             :   { Feature_isGFX9|Feature_isVI, 21428 /* v_cvt_pknorm_i16_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36190             :   { Feature_isGFX9|Feature_isVI, 21428 /* v_cvt_pknorm_i16_f16 */, MCK_ImmOpSel, 8 /* 3 */ },
   36191             :   { Feature_isGCN|Feature_isSICI, 21449 /* v_cvt_pknorm_i16_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36192             :   { Feature_isGCN|Feature_isSICI, 21449 /* v_cvt_pknorm_i16_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36193             :   { Feature_isGCN|Feature_isVI, 21449 /* v_cvt_pknorm_i16_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36194             :   { Feature_isGCN|Feature_isVI, 21449 /* v_cvt_pknorm_i16_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36195             :   { Feature_isGFX9|Feature_isVI, 21470 /* v_cvt_pknorm_u16_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   36196             :   { Feature_isGFX9|Feature_isVI, 21470 /* v_cvt_pknorm_u16_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36197             :   { Feature_isGFX9|Feature_isVI, 21470 /* v_cvt_pknorm_u16_f16 */, MCK_ImmOpSel, 8 /* 3 */ },
   36198             :   { Feature_isGCN|Feature_isSICI, 21491 /* v_cvt_pknorm_u16_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36199             :   { Feature_isGCN|Feature_isSICI, 21491 /* v_cvt_pknorm_u16_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36200             :   { Feature_isGCN|Feature_isVI, 21491 /* v_cvt_pknorm_u16_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36201             :   { Feature_isGCN|Feature_isVI, 21491 /* v_cvt_pknorm_u16_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36202             :   { Feature_isGCN|Feature_isSICI, 21512 /* v_cvt_pkrtz_f16_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36203             :   { Feature_isGCN|Feature_isSICI, 21512 /* v_cvt_pkrtz_f16_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36204             :   { Feature_isGCN|Feature_isSICI, 21512 /* v_cvt_pkrtz_f16_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36205             :   { Feature_isGCN|Feature_isVI, 21512 /* v_cvt_pkrtz_f16_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36206             :   { Feature_isGCN|Feature_isVI, 21512 /* v_cvt_pkrtz_f16_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36207             :   { Feature_isGCN|Feature_isVI, 21512 /* v_cvt_pkrtz_f16_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36208             :   { Feature_isGCN|Feature_isSICI, 21532 /* v_cvt_rpi_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36209             :   { Feature_isGCN|Feature_isSICI, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36210             :   { Feature_isGCN|Feature_isVI, 21532 /* v_cvt_rpi_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36211             :   { Feature_isGCN|Feature_isVI, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36212             :   { Feature_HasSDWA|Feature_HasSDWA, 21532 /* v_cvt_rpi_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36213             :   { Feature_HasSDWA|Feature_HasSDWA, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36214             :   { Feature_HasSDWA|Feature_HasSDWA, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36215             :   { Feature_HasSDWA|Feature_HasSDWA, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36216             :   { Feature_HasSDWA|Feature_HasSDWA, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36217             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21532 /* v_cvt_rpi_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36218             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36219             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36220             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36221             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36222             :   { Feature_HasDPP|Feature_HasDPP, 21532 /* v_cvt_rpi_i32_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36223             :   { Feature_HasDPP|Feature_HasDPP, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36224             :   { Feature_HasDPP|Feature_HasDPP, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36225             :   { Feature_HasDPP|Feature_HasDPP, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36226             :   { Feature_HasDPP|Feature_HasDPP, 21532 /* v_cvt_rpi_i32_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36227             :   { Feature_Has16BitInsts|Feature_isVI, 21550 /* v_cvt_u16_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36228             :   { Feature_Has16BitInsts|Feature_isVI, 21550 /* v_cvt_u16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36229             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21550 /* v_cvt_u16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36230             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21550 /* v_cvt_u16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36231             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21550 /* v_cvt_u16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36232             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21550 /* v_cvt_u16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36233             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21550 /* v_cvt_u16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36234             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21550 /* v_cvt_u16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36235             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21550 /* v_cvt_u16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36236             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21550 /* v_cvt_u16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36237             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21550 /* v_cvt_u16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36238             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21550 /* v_cvt_u16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36239             :   { Feature_HasDPP|Feature_HasDPP, 21550 /* v_cvt_u16_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36240             :   { Feature_HasDPP|Feature_HasDPP, 21550 /* v_cvt_u16_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36241             :   { Feature_HasDPP|Feature_HasDPP, 21550 /* v_cvt_u16_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36242             :   { Feature_HasDPP|Feature_HasDPP, 21550 /* v_cvt_u16_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36243             :   { Feature_HasDPP|Feature_HasDPP, 21550 /* v_cvt_u16_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36244             :   { Feature_isGCN|Feature_isSICI, 21564 /* v_cvt_u32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36245             :   { Feature_isGCN|Feature_isSICI, 21564 /* v_cvt_u32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36246             :   { Feature_isGCN|Feature_isVI, 21564 /* v_cvt_u32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36247             :   { Feature_isGCN|Feature_isVI, 21564 /* v_cvt_u32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36248             :   { Feature_HasSDWA|Feature_HasSDWA, 21564 /* v_cvt_u32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36249             :   { Feature_HasSDWA|Feature_HasSDWA, 21564 /* v_cvt_u32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36250             :   { Feature_HasSDWA|Feature_HasSDWA, 21564 /* v_cvt_u32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36251             :   { Feature_HasSDWA|Feature_HasSDWA, 21564 /* v_cvt_u32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36252             :   { Feature_HasSDWA|Feature_HasSDWA, 21564 /* v_cvt_u32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36253             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21564 /* v_cvt_u32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36254             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21564 /* v_cvt_u32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36255             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21564 /* v_cvt_u32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36256             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21564 /* v_cvt_u32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36257             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21564 /* v_cvt_u32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36258             :   { Feature_HasDPP|Feature_HasDPP, 21564 /* v_cvt_u32_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36259             :   { Feature_HasDPP|Feature_HasDPP, 21564 /* v_cvt_u32_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36260             :   { Feature_HasDPP|Feature_HasDPP, 21564 /* v_cvt_u32_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36261             :   { Feature_HasDPP|Feature_HasDPP, 21564 /* v_cvt_u32_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36262             :   { Feature_HasDPP|Feature_HasDPP, 21564 /* v_cvt_u32_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36263             :   { Feature_isGCN|Feature_isSICI, 21578 /* v_cvt_u32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36264             :   { Feature_isGCN|Feature_isSICI, 21578 /* v_cvt_u32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36265             :   { Feature_isGCN|Feature_isVI, 21578 /* v_cvt_u32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36266             :   { Feature_isGCN|Feature_isVI, 21578 /* v_cvt_u32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36267             :   { Feature_isGCN|Feature_isVIOnly, 21592 /* v_div_fixup_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36268             :   { Feature_isGCN|Feature_isVIOnly, 21592 /* v_div_fixup_f16 */, MCK_ImmOModSI, 32 /* 5 */ },
   36269             :   { Feature_isGCN|Feature_isVIOnly, 21592 /* v_div_fixup_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36270             :   { Feature_isGCN|Feature_isGFX9, 21592 /* v_div_fixup_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36271             :   { Feature_isGCN|Feature_isGFX9, 21592 /* v_div_fixup_f16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36272             :   { Feature_isGCN|Feature_isGFX9, 21592 /* v_div_fixup_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36273             :   { Feature_isGCN|Feature_isSICI, 21608 /* v_div_fixup_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36274             :   { Feature_isGCN|Feature_isSICI, 21608 /* v_div_fixup_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36275             :   { Feature_isGCN|Feature_isSICI, 21608 /* v_div_fixup_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36276             :   { Feature_isGCN|Feature_isVI, 21608 /* v_div_fixup_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36277             :   { Feature_isGCN|Feature_isVI, 21608 /* v_div_fixup_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36278             :   { Feature_isGCN|Feature_isVI, 21608 /* v_div_fixup_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36279             :   { Feature_isGCN|Feature_isSICI, 21624 /* v_div_fixup_f64 */, MCK_RegOrImmWithFP64InputMods, 14 /* 1, 2, 3 */ },
   36280             :   { Feature_isGCN|Feature_isSICI, 21624 /* v_div_fixup_f64 */, MCK_ImmOModSI, 32 /* 5 */ },
   36281             :   { Feature_isGCN|Feature_isSICI, 21624 /* v_div_fixup_f64 */, MCK_ImmClampSI, 16 /* 4 */ },
   36282             :   { Feature_isGCN|Feature_isVI, 21624 /* v_div_fixup_f64 */, MCK_RegOrImmWithFP64InputMods, 14 /* 1, 2, 3 */ },
   36283             :   { Feature_isGCN|Feature_isVI, 21624 /* v_div_fixup_f64 */, MCK_ImmOModSI, 32 /* 5 */ },
   36284             :   { Feature_isGCN|Feature_isVI, 21624 /* v_div_fixup_f64 */, MCK_ImmClampSI, 16 /* 4 */ },
   36285             :   { Feature_isGCN|Feature_isGFX9, 21640 /* v_div_fixup_legacy_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36286             :   { Feature_isGCN|Feature_isGFX9, 21640 /* v_div_fixup_legacy_f16 */, MCK_ImmOModSI, 32 /* 5 */ },
   36287             :   { Feature_isGCN|Feature_isGFX9, 21640 /* v_div_fixup_legacy_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36288             :   { Feature_isGCN|Feature_isSICI, 21663 /* v_div_fmas_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36289             :   { Feature_isGCN|Feature_isSICI, 21663 /* v_div_fmas_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36290             :   { Feature_isGCN|Feature_isSICI, 21663 /* v_div_fmas_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36291             :   { Feature_isGCN|Feature_isVI, 21663 /* v_div_fmas_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36292             :   { Feature_isGCN|Feature_isVI, 21663 /* v_div_fmas_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36293             :   { Feature_isGCN|Feature_isVI, 21663 /* v_div_fmas_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36294             :   { Feature_isGCN|Feature_isSICI, 21678 /* v_div_fmas_f64 */, MCK_RegOrImmWithFP64InputMods, 14 /* 1, 2, 3 */ },
   36295             :   { Feature_isGCN|Feature_isSICI, 21678 /* v_div_fmas_f64 */, MCK_ImmOModSI, 32 /* 5 */ },
   36296             :   { Feature_isGCN|Feature_isSICI, 21678 /* v_div_fmas_f64 */, MCK_ImmClampSI, 16 /* 4 */ },
   36297             :   { Feature_isGCN|Feature_isVI, 21678 /* v_div_fmas_f64 */, MCK_RegOrImmWithFP64InputMods, 14 /* 1, 2, 3 */ },
   36298             :   { Feature_isGCN|Feature_isVI, 21678 /* v_div_fmas_f64 */, MCK_ImmOModSI, 32 /* 5 */ },
   36299             :   { Feature_isGCN|Feature_isVI, 21678 /* v_div_fmas_f64 */, MCK_ImmClampSI, 16 /* 4 */ },
   36300             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21725 /* v_dot2_f32_f16 */, MCK_ImmClampSI, 256 /* 8 */ },
   36301             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21725 /* v_dot2_f32_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36302             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21725 /* v_dot2_f32_f16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36303             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21725 /* v_dot2_f32_f16 */, MCK_ImmNegLo, 64 /* 6 */ },
   36304             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21725 /* v_dot2_f32_f16 */, MCK_ImmNegHi, 128 /* 7 */ },
   36305             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21740 /* v_dot2_i32_i16 */, MCK_ImmClampSI, 256 /* 8 */ },
   36306             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21740 /* v_dot2_i32_i16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36307             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21740 /* v_dot2_i32_i16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36308             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21740 /* v_dot2_i32_i16 */, MCK_ImmNegLo, 64 /* 6 */ },
   36309             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21740 /* v_dot2_i32_i16 */, MCK_ImmNegHi, 128 /* 7 */ },
   36310             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21755 /* v_dot2_u32_u16 */, MCK_ImmClampSI, 256 /* 8 */ },
   36311             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21755 /* v_dot2_u32_u16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36312             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21755 /* v_dot2_u32_u16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36313             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21755 /* v_dot2_u32_u16 */, MCK_ImmNegLo, 64 /* 6 */ },
   36314             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21755 /* v_dot2_u32_u16 */, MCK_ImmNegHi, 128 /* 7 */ },
   36315             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21770 /* v_dot4_i32_i8 */, MCK_ImmClampSI, 256 /* 8 */ },
   36316             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21770 /* v_dot4_i32_i8 */, MCK_ImmOpSel, 16 /* 4 */ },
   36317             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21770 /* v_dot4_i32_i8 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36318             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21770 /* v_dot4_i32_i8 */, MCK_ImmNegLo, 64 /* 6 */ },
   36319             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21770 /* v_dot4_i32_i8 */, MCK_ImmNegHi, 128 /* 7 */ },
   36320             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21784 /* v_dot4_u32_u8 */, MCK_ImmClampSI, 256 /* 8 */ },
   36321             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21784 /* v_dot4_u32_u8 */, MCK_ImmOpSel, 16 /* 4 */ },
   36322             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21784 /* v_dot4_u32_u8 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36323             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21784 /* v_dot4_u32_u8 */, MCK_ImmNegLo, 64 /* 6 */ },
   36324             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21784 /* v_dot4_u32_u8 */, MCK_ImmNegHi, 128 /* 7 */ },
   36325             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21798 /* v_dot8_i32_i4 */, MCK_ImmClampSI, 256 /* 8 */ },
   36326             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21798 /* v_dot8_i32_i4 */, MCK_ImmOpSel, 16 /* 4 */ },
   36327             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21798 /* v_dot8_i32_i4 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36328             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21798 /* v_dot8_i32_i4 */, MCK_ImmNegLo, 64 /* 6 */ },
   36329             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21798 /* v_dot8_i32_i4 */, MCK_ImmNegHi, 128 /* 7 */ },
   36330             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21812 /* v_dot8_u32_u4 */, MCK_ImmClampSI, 256 /* 8 */ },
   36331             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21812 /* v_dot8_u32_u4 */, MCK_ImmOpSel, 16 /* 4 */ },
   36332             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21812 /* v_dot8_u32_u4 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36333             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21812 /* v_dot8_u32_u4 */, MCK_ImmNegLo, 64 /* 6 */ },
   36334             :   { Feature_HasDLInsts|Feature_HasVOP3PInsts, 21812 /* v_dot8_u32_u4 */, MCK_ImmNegHi, 128 /* 7 */ },
   36335             :   { Feature_Has16BitInsts|Feature_isVI, 21826 /* v_exp_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36336             :   { Feature_Has16BitInsts|Feature_isVI, 21826 /* v_exp_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36337             :   { Feature_Has16BitInsts|Feature_isVI, 21826 /* v_exp_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36338             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21826 /* v_exp_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36339             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21826 /* v_exp_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36340             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21826 /* v_exp_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36341             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21826 /* v_exp_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36342             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21826 /* v_exp_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36343             :   { Feature_HasDPP|Feature_HasDPP, 21826 /* v_exp_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36344             :   { Feature_HasDPP|Feature_HasDPP, 21826 /* v_exp_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36345             :   { Feature_HasDPP|Feature_HasDPP, 21826 /* v_exp_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36346             :   { Feature_HasDPP|Feature_HasDPP, 21826 /* v_exp_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36347             :   { Feature_HasDPP|Feature_HasDPP, 21826 /* v_exp_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36348             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21826 /* v_exp_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36349             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21826 /* v_exp_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36350             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21826 /* v_exp_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36351             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21826 /* v_exp_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36352             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21826 /* v_exp_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36353             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21826 /* v_exp_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36354             :   { Feature_isGCN|Feature_isSICI, 21836 /* v_exp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36355             :   { Feature_isGCN|Feature_isSICI, 21836 /* v_exp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36356             :   { Feature_isGCN|Feature_isSICI, 21836 /* v_exp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36357             :   { Feature_isGCN|Feature_isVI, 21836 /* v_exp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36358             :   { Feature_isGCN|Feature_isVI, 21836 /* v_exp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36359             :   { Feature_isGCN|Feature_isVI, 21836 /* v_exp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36360             :   { Feature_HasSDWA|Feature_HasSDWA, 21836 /* v_exp_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36361             :   { Feature_HasSDWA|Feature_HasSDWA, 21836 /* v_exp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36362             :   { Feature_HasSDWA|Feature_HasSDWA, 21836 /* v_exp_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36363             :   { Feature_HasSDWA|Feature_HasSDWA, 21836 /* v_exp_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36364             :   { Feature_HasSDWA|Feature_HasSDWA, 21836 /* v_exp_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36365             :   { Feature_HasDPP|Feature_HasDPP, 21836 /* v_exp_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36366             :   { Feature_HasDPP|Feature_HasDPP, 21836 /* v_exp_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36367             :   { Feature_HasDPP|Feature_HasDPP, 21836 /* v_exp_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36368             :   { Feature_HasDPP|Feature_HasDPP, 21836 /* v_exp_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36369             :   { Feature_HasDPP|Feature_HasDPP, 21836 /* v_exp_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36370             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21836 /* v_exp_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36371             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21836 /* v_exp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36372             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21836 /* v_exp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36373             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21836 /* v_exp_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36374             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21836 /* v_exp_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36375             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21836 /* v_exp_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36376             :   { Feature_isCIVI|Feature_isCIOnly, 21846 /* v_exp_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36377             :   { Feature_isCIVI|Feature_isCIOnly, 21846 /* v_exp_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36378             :   { Feature_isCIVI|Feature_isCIOnly, 21846 /* v_exp_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36379             :   { Feature_isCIVI|Feature_isVI, 21846 /* v_exp_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36380             :   { Feature_isCIVI|Feature_isVI, 21846 /* v_exp_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36381             :   { Feature_isCIVI|Feature_isVI, 21846 /* v_exp_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36382             :   { Feature_isCIVI|Feature_HasSDWA, 21846 /* v_exp_legacy_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36383             :   { Feature_isCIVI|Feature_HasSDWA, 21846 /* v_exp_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36384             :   { Feature_isCIVI|Feature_HasSDWA, 21846 /* v_exp_legacy_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36385             :   { Feature_isCIVI|Feature_HasSDWA, 21846 /* v_exp_legacy_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36386             :   { Feature_isCIVI|Feature_HasSDWA, 21846 /* v_exp_legacy_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36387             :   { Feature_HasDPP|Feature_HasDPP, 21846 /* v_exp_legacy_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36388             :   { Feature_HasDPP|Feature_HasDPP, 21846 /* v_exp_legacy_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36389             :   { Feature_HasDPP|Feature_HasDPP, 21846 /* v_exp_legacy_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36390             :   { Feature_HasDPP|Feature_HasDPP, 21846 /* v_exp_legacy_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36391             :   { Feature_HasDPP|Feature_HasDPP, 21846 /* v_exp_legacy_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36392             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21846 /* v_exp_legacy_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36393             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21846 /* v_exp_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36394             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21846 /* v_exp_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36395             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21846 /* v_exp_legacy_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36396             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21846 /* v_exp_legacy_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36397             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21846 /* v_exp_legacy_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36398             :   { Feature_HasDPP|Feature_HasDPP, 21863 /* v_ffbh_i32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36399             :   { Feature_HasDPP|Feature_HasDPP, 21863 /* v_ffbh_i32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36400             :   { Feature_HasDPP|Feature_HasDPP, 21863 /* v_ffbh_i32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36401             :   { Feature_HasDPP|Feature_HasDPP, 21863 /* v_ffbh_i32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36402             :   { Feature_HasSDWA|Feature_HasSDWA, 21863 /* v_ffbh_i32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36403             :   { Feature_HasSDWA|Feature_HasSDWA, 21863 /* v_ffbh_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36404             :   { Feature_HasSDWA|Feature_HasSDWA, 21863 /* v_ffbh_i32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36405             :   { Feature_HasSDWA|Feature_HasSDWA, 21863 /* v_ffbh_i32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36406             :   { Feature_HasSDWA|Feature_HasSDWA, 21863 /* v_ffbh_i32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36407             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21863 /* v_ffbh_i32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36408             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21863 /* v_ffbh_i32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36409             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21863 /* v_ffbh_i32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36410             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21863 /* v_ffbh_i32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36411             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21863 /* v_ffbh_i32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36412             :   { Feature_HasDPP|Feature_HasDPP, 21874 /* v_ffbh_u32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36413             :   { Feature_HasDPP|Feature_HasDPP, 21874 /* v_ffbh_u32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36414             :   { Feature_HasDPP|Feature_HasDPP, 21874 /* v_ffbh_u32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36415             :   { Feature_HasDPP|Feature_HasDPP, 21874 /* v_ffbh_u32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36416             :   { Feature_HasSDWA|Feature_HasSDWA, 21874 /* v_ffbh_u32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36417             :   { Feature_HasSDWA|Feature_HasSDWA, 21874 /* v_ffbh_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36418             :   { Feature_HasSDWA|Feature_HasSDWA, 21874 /* v_ffbh_u32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36419             :   { Feature_HasSDWA|Feature_HasSDWA, 21874 /* v_ffbh_u32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36420             :   { Feature_HasSDWA|Feature_HasSDWA, 21874 /* v_ffbh_u32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36421             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21874 /* v_ffbh_u32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36422             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21874 /* v_ffbh_u32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36423             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21874 /* v_ffbh_u32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36424             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21874 /* v_ffbh_u32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36425             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21874 /* v_ffbh_u32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36426             :   { Feature_HasDPP|Feature_HasDPP, 21885 /* v_ffbl_b32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36427             :   { Feature_HasDPP|Feature_HasDPP, 21885 /* v_ffbl_b32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36428             :   { Feature_HasDPP|Feature_HasDPP, 21885 /* v_ffbl_b32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36429             :   { Feature_HasDPP|Feature_HasDPP, 21885 /* v_ffbl_b32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36430             :   { Feature_HasSDWA|Feature_HasSDWA, 21885 /* v_ffbl_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36431             :   { Feature_HasSDWA|Feature_HasSDWA, 21885 /* v_ffbl_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36432             :   { Feature_HasSDWA|Feature_HasSDWA, 21885 /* v_ffbl_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36433             :   { Feature_HasSDWA|Feature_HasSDWA, 21885 /* v_ffbl_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36434             :   { Feature_HasSDWA|Feature_HasSDWA, 21885 /* v_ffbl_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36435             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21885 /* v_ffbl_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   36436             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21885 /* v_ffbl_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36437             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21885 /* v_ffbl_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36438             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21885 /* v_ffbl_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36439             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21885 /* v_ffbl_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36440             :   { Feature_Has16BitInsts|Feature_isVI, 21896 /* v_floor_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36441             :   { Feature_Has16BitInsts|Feature_isVI, 21896 /* v_floor_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36442             :   { Feature_Has16BitInsts|Feature_isVI, 21896 /* v_floor_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36443             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21896 /* v_floor_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36444             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21896 /* v_floor_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36445             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21896 /* v_floor_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36446             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21896 /* v_floor_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36447             :   { Feature_Has16BitInsts|Feature_HasSDWA, 21896 /* v_floor_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36448             :   { Feature_HasDPP|Feature_HasDPP, 21896 /* v_floor_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36449             :   { Feature_HasDPP|Feature_HasDPP, 21896 /* v_floor_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36450             :   { Feature_HasDPP|Feature_HasDPP, 21896 /* v_floor_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36451             :   { Feature_HasDPP|Feature_HasDPP, 21896 /* v_floor_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36452             :   { Feature_HasDPP|Feature_HasDPP, 21896 /* v_floor_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36453             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21896 /* v_floor_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36454             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21896 /* v_floor_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36455             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21896 /* v_floor_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36456             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21896 /* v_floor_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36457             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21896 /* v_floor_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36458             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21896 /* v_floor_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36459             :   { Feature_isGCN|Feature_isSICI, 21908 /* v_floor_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36460             :   { Feature_isGCN|Feature_isSICI, 21908 /* v_floor_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36461             :   { Feature_isGCN|Feature_isSICI, 21908 /* v_floor_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36462             :   { Feature_isGCN|Feature_isVI, 21908 /* v_floor_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36463             :   { Feature_isGCN|Feature_isVI, 21908 /* v_floor_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36464             :   { Feature_isGCN|Feature_isVI, 21908 /* v_floor_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36465             :   { Feature_HasSDWA|Feature_HasSDWA, 21908 /* v_floor_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36466             :   { Feature_HasSDWA|Feature_HasSDWA, 21908 /* v_floor_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36467             :   { Feature_HasSDWA|Feature_HasSDWA, 21908 /* v_floor_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36468             :   { Feature_HasSDWA|Feature_HasSDWA, 21908 /* v_floor_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36469             :   { Feature_HasSDWA|Feature_HasSDWA, 21908 /* v_floor_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36470             :   { Feature_HasDPP|Feature_HasDPP, 21908 /* v_floor_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36471             :   { Feature_HasDPP|Feature_HasDPP, 21908 /* v_floor_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36472             :   { Feature_HasDPP|Feature_HasDPP, 21908 /* v_floor_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36473             :   { Feature_HasDPP|Feature_HasDPP, 21908 /* v_floor_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36474             :   { Feature_HasDPP|Feature_HasDPP, 21908 /* v_floor_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36475             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21908 /* v_floor_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36476             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21908 /* v_floor_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36477             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21908 /* v_floor_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36478             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21908 /* v_floor_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36479             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21908 /* v_floor_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36480             :   { Feature_HasSDWA9|Feature_HasSDWA9, 21908 /* v_floor_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36481             :   { Feature_isCIVI|Feature_isCIOnly, 21920 /* v_floor_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36482             :   { Feature_isCIVI|Feature_isCIOnly, 21920 /* v_floor_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   36483             :   { Feature_isCIVI|Feature_isCIOnly, 21920 /* v_floor_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36484             :   { Feature_isCIVI|Feature_isVI, 21920 /* v_floor_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36485             :   { Feature_isCIVI|Feature_isVI, 21920 /* v_floor_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   36486             :   { Feature_isCIVI|Feature_isVI, 21920 /* v_floor_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36487             :   { Feature_Has16BitInsts|Feature_isVIOnly, 21932 /* v_fma_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36488             :   { Feature_Has16BitInsts|Feature_isVIOnly, 21932 /* v_fma_f16 */, MCK_ImmOModSI, 32 /* 5 */ },
   36489             :   { Feature_Has16BitInsts|Feature_isVIOnly, 21932 /* v_fma_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36490             :   { Feature_isGFX9|Feature_isGFX9, 21932 /* v_fma_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36491             :   { Feature_isGFX9|Feature_isGFX9, 21932 /* v_fma_f16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36492             :   { Feature_isGFX9|Feature_isGFX9, 21932 /* v_fma_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36493             :   { Feature_isGCN|Feature_isSICI, 21942 /* v_fma_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36494             :   { Feature_isGCN|Feature_isSICI, 21942 /* v_fma_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36495             :   { Feature_isGCN|Feature_isSICI, 21942 /* v_fma_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36496             :   { Feature_isGCN|Feature_isVI, 21942 /* v_fma_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36497             :   { Feature_isGCN|Feature_isVI, 21942 /* v_fma_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36498             :   { Feature_isGCN|Feature_isVI, 21942 /* v_fma_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36499             :   { Feature_isGCN|Feature_isSICI, 21952 /* v_fma_f64 */, MCK_RegOrImmWithFP64InputMods, 14 /* 1, 2, 3 */ },
   36500             :   { Feature_isGCN|Feature_isSICI, 21952 /* v_fma_f64 */, MCK_ImmOModSI, 32 /* 5 */ },
   36501             :   { Feature_isGCN|Feature_isSICI, 21952 /* v_fma_f64 */, MCK_ImmClampSI, 16 /* 4 */ },
   36502             :   { Feature_isGCN|Feature_isVI, 21952 /* v_fma_f64 */, MCK_RegOrImmWithFP64InputMods, 14 /* 1, 2, 3 */ },
   36503             :   { Feature_isGCN|Feature_isVI, 21952 /* v_fma_f64 */, MCK_ImmOModSI, 32 /* 5 */ },
   36504             :   { Feature_isGCN|Feature_isVI, 21952 /* v_fma_f64 */, MCK_ImmClampSI, 16 /* 4 */ },
   36505             :   { Feature_Has16BitInsts|Feature_isGFX9, 21962 /* v_fma_legacy_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36506             :   { Feature_Has16BitInsts|Feature_isGFX9, 21962 /* v_fma_legacy_f16 */, MCK_ImmOModSI, 32 /* 5 */ },
   36507             :   { Feature_Has16BitInsts|Feature_isGFX9, 21962 /* v_fma_legacy_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36508             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21979 /* v_fma_mix_f32 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36509             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21979 /* v_fma_mix_f32 */, MCK_ImmClampSI, 64 /* 6 */ },
   36510             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21979 /* v_fma_mix_f32 */, MCK_ImmOpSel, 16 /* 4 */ },
   36511             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21979 /* v_fma_mix_f32 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36512             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21993 /* v_fma_mixhi_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36513             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21993 /* v_fma_mixhi_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36514             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21993 /* v_fma_mixhi_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36515             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 21993 /* v_fma_mixhi_f16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36516             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 22009 /* v_fma_mixlo_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36517             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 22009 /* v_fma_mixlo_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36518             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 22009 /* v_fma_mixlo_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36519             :   { Feature_HasFmaMixInsts|Feature_HasVOP3PInsts, 22009 /* v_fma_mixlo_f16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36520             :   { Feature_HasDLInsts|Feature_isVI, 22025 /* v_fmac_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36521             :   { Feature_HasDLInsts|Feature_isVI, 22025 /* v_fmac_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36522             :   { Feature_HasDLInsts|Feature_isVI, 22025 /* v_fmac_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36523             :   { Feature_HasDLInsts|Feature_HasDPP, 22025 /* v_fmac_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   36524             :   { Feature_HasDLInsts|Feature_HasDPP, 22025 /* v_fmac_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36525             :   { Feature_HasDLInsts|Feature_HasDPP, 22025 /* v_fmac_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   36526             :   { Feature_HasDLInsts|Feature_HasDPP, 22025 /* v_fmac_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   36527             :   { Feature_HasDLInsts|Feature_HasDPP, 22025 /* v_fmac_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36528             :   { Feature_HasDLInsts|Feature_HasSDWA, 22025 /* v_fmac_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   36529             :   { Feature_HasDLInsts|Feature_HasSDWA, 22025 /* v_fmac_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36530             :   { Feature_HasDLInsts|Feature_HasSDWA, 22025 /* v_fmac_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36531             :   { Feature_HasDLInsts|Feature_HasSDWA, 22025 /* v_fmac_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36532             :   { Feature_HasDLInsts|Feature_HasSDWA, 22025 /* v_fmac_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36533             :   { Feature_HasDLInsts|Feature_HasSDWA, 22025 /* v_fmac_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36534             :   { Feature_Has16BitInsts|Feature_isVI, 22036 /* v_fract_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36535             :   { Feature_Has16BitInsts|Feature_isVI, 22036 /* v_fract_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36536             :   { Feature_Has16BitInsts|Feature_isVI, 22036 /* v_fract_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36537             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22036 /* v_fract_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36538             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22036 /* v_fract_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36539             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22036 /* v_fract_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36540             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22036 /* v_fract_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36541             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22036 /* v_fract_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36542             :   { Feature_HasDPP|Feature_HasDPP, 22036 /* v_fract_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36543             :   { Feature_HasDPP|Feature_HasDPP, 22036 /* v_fract_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36544             :   { Feature_HasDPP|Feature_HasDPP, 22036 /* v_fract_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36545             :   { Feature_HasDPP|Feature_HasDPP, 22036 /* v_fract_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36546             :   { Feature_HasDPP|Feature_HasDPP, 22036 /* v_fract_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36547             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22036 /* v_fract_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36548             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22036 /* v_fract_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36549             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22036 /* v_fract_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36550             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22036 /* v_fract_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36551             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22036 /* v_fract_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36552             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22036 /* v_fract_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36553             :   { Feature_isGCN|Feature_isSICI, 22048 /* v_fract_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36554             :   { Feature_isGCN|Feature_isSICI, 22048 /* v_fract_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36555             :   { Feature_isGCN|Feature_isSICI, 22048 /* v_fract_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36556             :   { Feature_isGCN|Feature_isVI, 22048 /* v_fract_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36557             :   { Feature_isGCN|Feature_isVI, 22048 /* v_fract_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36558             :   { Feature_isGCN|Feature_isVI, 22048 /* v_fract_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36559             :   { Feature_HasSDWA|Feature_HasSDWA, 22048 /* v_fract_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36560             :   { Feature_HasSDWA|Feature_HasSDWA, 22048 /* v_fract_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36561             :   { Feature_HasSDWA|Feature_HasSDWA, 22048 /* v_fract_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36562             :   { Feature_HasSDWA|Feature_HasSDWA, 22048 /* v_fract_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36563             :   { Feature_HasSDWA|Feature_HasSDWA, 22048 /* v_fract_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36564             :   { Feature_HasDPP|Feature_HasDPP, 22048 /* v_fract_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36565             :   { Feature_HasDPP|Feature_HasDPP, 22048 /* v_fract_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36566             :   { Feature_HasDPP|Feature_HasDPP, 22048 /* v_fract_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36567             :   { Feature_HasDPP|Feature_HasDPP, 22048 /* v_fract_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36568             :   { Feature_HasDPP|Feature_HasDPP, 22048 /* v_fract_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36569             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22048 /* v_fract_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36570             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22048 /* v_fract_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36571             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22048 /* v_fract_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36572             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22048 /* v_fract_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36573             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22048 /* v_fract_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36574             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22048 /* v_fract_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36575             :   { Feature_isGCN|Feature_isSICI, 22060 /* v_fract_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36576             :   { Feature_isGCN|Feature_isSICI, 22060 /* v_fract_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   36577             :   { Feature_isGCN|Feature_isSICI, 22060 /* v_fract_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36578             :   { Feature_isGCN|Feature_isVI, 22060 /* v_fract_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36579             :   { Feature_isGCN|Feature_isVI, 22060 /* v_fract_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   36580             :   { Feature_isGCN|Feature_isVI, 22060 /* v_fract_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36581             :   { Feature_Has16BitInsts|Feature_isVI, 22072 /* v_frexp_exp_i16_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36582             :   { Feature_Has16BitInsts|Feature_isVI, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36583             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22072 /* v_frexp_exp_i16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36584             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36585             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36586             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36587             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36588             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22072 /* v_frexp_exp_i16_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36589             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36590             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36591             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36592             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36593             :   { Feature_HasDPP|Feature_HasDPP, 22072 /* v_frexp_exp_i16_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36594             :   { Feature_HasDPP|Feature_HasDPP, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36595             :   { Feature_HasDPP|Feature_HasDPP, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36596             :   { Feature_HasDPP|Feature_HasDPP, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36597             :   { Feature_HasDPP|Feature_HasDPP, 22072 /* v_frexp_exp_i16_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36598             :   { Feature_isGCN|Feature_isSICI, 22092 /* v_frexp_exp_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36599             :   { Feature_isGCN|Feature_isSICI, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36600             :   { Feature_isGCN|Feature_isVI, 22092 /* v_frexp_exp_i32_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36601             :   { Feature_isGCN|Feature_isVI, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36602             :   { Feature_HasSDWA|Feature_HasSDWA, 22092 /* v_frexp_exp_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36603             :   { Feature_HasSDWA|Feature_HasSDWA, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36604             :   { Feature_HasSDWA|Feature_HasSDWA, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36605             :   { Feature_HasSDWA|Feature_HasSDWA, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36606             :   { Feature_HasSDWA|Feature_HasSDWA, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36607             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22092 /* v_frexp_exp_i32_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36608             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36609             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36610             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36611             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36612             :   { Feature_HasDPP|Feature_HasDPP, 22092 /* v_frexp_exp_i32_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36613             :   { Feature_HasDPP|Feature_HasDPP, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36614             :   { Feature_HasDPP|Feature_HasDPP, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36615             :   { Feature_HasDPP|Feature_HasDPP, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36616             :   { Feature_HasDPP|Feature_HasDPP, 22092 /* v_frexp_exp_i32_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36617             :   { Feature_isGCN|Feature_isSICI, 22112 /* v_frexp_exp_i32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36618             :   { Feature_isGCN|Feature_isSICI, 22112 /* v_frexp_exp_i32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36619             :   { Feature_isGCN|Feature_isVI, 22112 /* v_frexp_exp_i32_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36620             :   { Feature_isGCN|Feature_isVI, 22112 /* v_frexp_exp_i32_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36621             :   { Feature_Has16BitInsts|Feature_isVI, 22132 /* v_frexp_mant_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36622             :   { Feature_Has16BitInsts|Feature_isVI, 22132 /* v_frexp_mant_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36623             :   { Feature_Has16BitInsts|Feature_isVI, 22132 /* v_frexp_mant_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36624             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22132 /* v_frexp_mant_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36625             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22132 /* v_frexp_mant_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36626             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22132 /* v_frexp_mant_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36627             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22132 /* v_frexp_mant_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36628             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22132 /* v_frexp_mant_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36629             :   { Feature_HasDPP|Feature_HasDPP, 22132 /* v_frexp_mant_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36630             :   { Feature_HasDPP|Feature_HasDPP, 22132 /* v_frexp_mant_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36631             :   { Feature_HasDPP|Feature_HasDPP, 22132 /* v_frexp_mant_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36632             :   { Feature_HasDPP|Feature_HasDPP, 22132 /* v_frexp_mant_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36633             :   { Feature_HasDPP|Feature_HasDPP, 22132 /* v_frexp_mant_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36634             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22132 /* v_frexp_mant_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36635             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22132 /* v_frexp_mant_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36636             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22132 /* v_frexp_mant_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36637             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22132 /* v_frexp_mant_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36638             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22132 /* v_frexp_mant_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36639             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22132 /* v_frexp_mant_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36640             :   { Feature_isGCN|Feature_isSICI, 22149 /* v_frexp_mant_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36641             :   { Feature_isGCN|Feature_isSICI, 22149 /* v_frexp_mant_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36642             :   { Feature_isGCN|Feature_isSICI, 22149 /* v_frexp_mant_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36643             :   { Feature_isGCN|Feature_isVI, 22149 /* v_frexp_mant_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36644             :   { Feature_isGCN|Feature_isVI, 22149 /* v_frexp_mant_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36645             :   { Feature_isGCN|Feature_isVI, 22149 /* v_frexp_mant_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36646             :   { Feature_HasSDWA|Feature_HasSDWA, 22149 /* v_frexp_mant_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36647             :   { Feature_HasSDWA|Feature_HasSDWA, 22149 /* v_frexp_mant_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36648             :   { Feature_HasSDWA|Feature_HasSDWA, 22149 /* v_frexp_mant_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36649             :   { Feature_HasSDWA|Feature_HasSDWA, 22149 /* v_frexp_mant_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36650             :   { Feature_HasSDWA|Feature_HasSDWA, 22149 /* v_frexp_mant_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36651             :   { Feature_HasDPP|Feature_HasDPP, 22149 /* v_frexp_mant_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36652             :   { Feature_HasDPP|Feature_HasDPP, 22149 /* v_frexp_mant_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36653             :   { Feature_HasDPP|Feature_HasDPP, 22149 /* v_frexp_mant_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36654             :   { Feature_HasDPP|Feature_HasDPP, 22149 /* v_frexp_mant_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36655             :   { Feature_HasDPP|Feature_HasDPP, 22149 /* v_frexp_mant_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36656             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22149 /* v_frexp_mant_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36657             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22149 /* v_frexp_mant_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36658             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22149 /* v_frexp_mant_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36659             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22149 /* v_frexp_mant_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36660             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22149 /* v_frexp_mant_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36661             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22149 /* v_frexp_mant_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36662             :   { Feature_isGCN|Feature_isSICI, 22166 /* v_frexp_mant_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36663             :   { Feature_isGCN|Feature_isSICI, 22166 /* v_frexp_mant_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   36664             :   { Feature_isGCN|Feature_isSICI, 22166 /* v_frexp_mant_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36665             :   { Feature_isGCN|Feature_isVI, 22166 /* v_frexp_mant_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36666             :   { Feature_isGCN|Feature_isVI, 22166 /* v_frexp_mant_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   36667             :   { Feature_isGCN|Feature_isVI, 22166 /* v_frexp_mant_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   36668             :   { Feature_isGCN|Feature_isSICI, 22183 /* v_interp_mov_f32 */, MCK_Attr, 4 /* 2 */ },
   36669             :   { Feature_isGCN|Feature_isSICI, 22183 /* v_interp_mov_f32 */, MCK_InterpSlot, 2 /* 1 */ },
   36670             :   { Feature_isGCN|Feature_isVI, 22183 /* v_interp_mov_f32 */, MCK_Attr, 4 /* 2 */ },
   36671             :   { Feature_isGCN|Feature_isVI, 22183 /* v_interp_mov_f32 */, MCK_InterpSlot, 2 /* 1 */ },
   36672             :   { Feature_isVI|Feature_isVI, 22183 /* v_interp_mov_f32 */, MCK_Attr, 4 /* 2 */ },
   36673             :   { Feature_isVI|Feature_isVI, 22183 /* v_interp_mov_f32 */, MCK_InterpSlot, 2 /* 1 */ },
   36674             :   { Feature_isVI|Feature_isVI, 22183 /* v_interp_mov_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36675             :   { Feature_isVI|Feature_isVI, 22183 /* v_interp_mov_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36676             :   { Feature_isGCN|Feature_isSICI, 22200 /* v_interp_p1_f32 */, MCK_Attr, 4 /* 2 */ },
   36677             :   { Feature_isGCN|Feature_isVI, 22200 /* v_interp_p1_f32 */, MCK_Attr, 4 /* 2 */ },
   36678             :   { Feature_isGCN|Feature_isSICI, 22200 /* v_interp_p1_f32 */, MCK_Attr, 4 /* 2 */ },
   36679             :   { Feature_isGCN|Feature_isVI, 22200 /* v_interp_p1_f32 */, MCK_Attr, 4 /* 2 */ },
   36680             :   { Feature_isVI|Feature_isVI, 22200 /* v_interp_p1_f32 */, MCK_Attr, 4 /* 2 */ },
   36681             :   { Feature_isVI|Feature_isVI, 22200 /* v_interp_p1_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36682             :   { Feature_isVI|Feature_isVI, 22200 /* v_interp_p1_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36683             :   { Feature_isVI|Feature_isVI, 22200 /* v_interp_p1_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36684             :   { Feature_Has16BitInsts|Feature_isVI, 22216 /* v_interp_p1ll_f16 */, MCK_Attr, 4 /* 2 */ },
   36685             :   { Feature_Has16BitInsts|Feature_isVI, 22216 /* v_interp_p1ll_f16 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36686             :   { Feature_Has16BitInsts|Feature_isVI, 22216 /* v_interp_p1ll_f16 */, MCK_ImmOModSI, 64 /* 6 */ },
   36687             :   { Feature_Has16BitInsts|Feature_isVI, 22216 /* v_interp_p1ll_f16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36688             :   { Feature_Has16BitInsts|Feature_isVI, 22216 /* v_interp_p1ll_f16 */, MCK_ImmHigh, 16 /* 4 */ },
   36689             :   { Feature_Has16BitInsts|Feature_isVI, 22234 /* v_interp_p1lv_f16 */, MCK_Attr, 4 /* 2 */ },
   36690             :   { Feature_Has16BitInsts|Feature_isVI, 22234 /* v_interp_p1lv_f16 */, MCK_RegOrImmWithFP16InputMods, 16 /* 4 */ },
   36691             :   { Feature_Has16BitInsts|Feature_isVI, 22234 /* v_interp_p1lv_f16 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36692             :   { Feature_Has16BitInsts|Feature_isVI, 22234 /* v_interp_p1lv_f16 */, MCK_ImmOModSI, 128 /* 7 */ },
   36693             :   { Feature_Has16BitInsts|Feature_isVI, 22234 /* v_interp_p1lv_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36694             :   { Feature_Has16BitInsts|Feature_isVI, 22234 /* v_interp_p1lv_f16 */, MCK_ImmHigh, 32 /* 5 */ },
   36695             :   { Feature_isGFX9|Feature_isGFX9, 22252 /* v_interp_p2_f16 */, MCK_Attr, 4 /* 2 */ },
   36696             :   { Feature_isGFX9|Feature_isGFX9, 22252 /* v_interp_p2_f16 */, MCK_RegOrImmWithFP32InputMods, 18 /* 1, 4 */ },
   36697             :   { Feature_isGFX9|Feature_isGFX9, 22252 /* v_interp_p2_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36698             :   { Feature_isGFX9|Feature_isGFX9, 22252 /* v_interp_p2_f16 */, MCK_ImmHigh, 32 /* 5 */ },
   36699             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22252 /* v_interp_p2_f16 */, MCK_Attr, 4 /* 2 */ },
   36700             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22252 /* v_interp_p2_f16 */, MCK_RegOrImmWithFP32InputMods, 18 /* 1, 4 */ },
   36701             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22252 /* v_interp_p2_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36702             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22252 /* v_interp_p2_f16 */, MCK_ImmHigh, 32 /* 5 */ },
   36703             :   { Feature_isGCN|Feature_isSICI, 22268 /* v_interp_p2_f32 */, MCK_Attr, 4 /* 2 */ },
   36704             :   { Feature_isGCN|Feature_isVI, 22268 /* v_interp_p2_f32 */, MCK_Attr, 4 /* 2 */ },
   36705             :   { Feature_isVI|Feature_isVI, 22268 /* v_interp_p2_f32 */, MCK_Attr, 4 /* 2 */ },
   36706             :   { Feature_isVI|Feature_isVI, 22268 /* v_interp_p2_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36707             :   { Feature_isVI|Feature_isVI, 22268 /* v_interp_p2_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36708             :   { Feature_isVI|Feature_isVI, 22268 /* v_interp_p2_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36709             :   { Feature_Has16BitInsts|Feature_isGFX9, 22284 /* v_interp_p2_legacy_f16 */, MCK_Attr, 4 /* 2 */ },
   36710             :   { Feature_Has16BitInsts|Feature_isGFX9, 22284 /* v_interp_p2_legacy_f16 */, MCK_RegOrImmWithFP32InputMods, 18 /* 1, 4 */ },
   36711             :   { Feature_Has16BitInsts|Feature_isGFX9, 22284 /* v_interp_p2_legacy_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36712             :   { Feature_Has16BitInsts|Feature_isGFX9, 22284 /* v_interp_p2_legacy_f16 */, MCK_ImmHigh, 32 /* 5 */ },
   36713             :   { Feature_Has16BitInsts|Feature_isVI, 22307 /* v_ldexp_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36714             :   { Feature_Has16BitInsts|Feature_isVI, 22307 /* v_ldexp_f16 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   36715             :   { Feature_Has16BitInsts|Feature_isVI, 22307 /* v_ldexp_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   36716             :   { Feature_Has16BitInsts|Feature_isVI, 22307 /* v_ldexp_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36717             :   { Feature_HasDPP|Feature_HasDPP, 22307 /* v_ldexp_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36718             :   { Feature_HasDPP|Feature_HasDPP, 22307 /* v_ldexp_f16 */, MCK_VRegWithIntInputMods, 4 /* 2 */ },
   36719             :   { Feature_HasDPP|Feature_HasDPP, 22307 /* v_ldexp_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36720             :   { Feature_HasDPP|Feature_HasDPP, 22307 /* v_ldexp_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   36721             :   { Feature_HasDPP|Feature_HasDPP, 22307 /* v_ldexp_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   36722             :   { Feature_HasDPP|Feature_HasDPP, 22307 /* v_ldexp_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36723             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22307 /* v_ldexp_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36724             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22307 /* v_ldexp_f16 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   36725             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22307 /* v_ldexp_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36726             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22307 /* v_ldexp_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36727             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22307 /* v_ldexp_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36728             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22307 /* v_ldexp_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36729             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22307 /* v_ldexp_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36730             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36731             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_SDWAWithInt32InputMods, 4 /* 2 */ },
   36732             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   36733             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36734             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   36735             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   36736             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   36737             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22307 /* v_ldexp_f16 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   36738             :   { Feature_isGCN|Feature_isSICI, 22319 /* v_ldexp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36739             :   { Feature_isGCN|Feature_isSICI, 22319 /* v_ldexp_f32 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   36740             :   { Feature_isGCN|Feature_isSICI, 22319 /* v_ldexp_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36741             :   { Feature_isGCN|Feature_isSICI, 22319 /* v_ldexp_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36742             :   { Feature_isGCN|Feature_isVI, 22319 /* v_ldexp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36743             :   { Feature_isGCN|Feature_isVI, 22319 /* v_ldexp_f32 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   36744             :   { Feature_isGCN|Feature_isVI, 22319 /* v_ldexp_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36745             :   { Feature_isGCN|Feature_isVI, 22319 /* v_ldexp_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36746             :   { Feature_isGCN|Feature_isSICI, 22331 /* v_ldexp_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36747             :   { Feature_isGCN|Feature_isSICI, 22331 /* v_ldexp_f64 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   36748             :   { Feature_isGCN|Feature_isSICI, 22331 /* v_ldexp_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   36749             :   { Feature_isGCN|Feature_isSICI, 22331 /* v_ldexp_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   36750             :   { Feature_isGCN|Feature_isVI, 22331 /* v_ldexp_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   36751             :   { Feature_isGCN|Feature_isVI, 22331 /* v_ldexp_f64 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   36752             :   { Feature_isGCN|Feature_isVI, 22331 /* v_ldexp_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   36753             :   { Feature_isGCN|Feature_isVI, 22331 /* v_ldexp_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   36754             :   { Feature_isSICI|Feature_isSICI, 22353 /* v_log_clamp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36755             :   { Feature_isSICI|Feature_isSICI, 22353 /* v_log_clamp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36756             :   { Feature_isSICI|Feature_isSICI, 22353 /* v_log_clamp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36757             :   { Feature_Has16BitInsts|Feature_isVI, 22369 /* v_log_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   36758             :   { Feature_Has16BitInsts|Feature_isVI, 22369 /* v_log_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36759             :   { Feature_Has16BitInsts|Feature_isVI, 22369 /* v_log_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36760             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22369 /* v_log_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36761             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22369 /* v_log_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36762             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22369 /* v_log_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36763             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22369 /* v_log_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36764             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22369 /* v_log_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36765             :   { Feature_HasDPP|Feature_HasDPP, 22369 /* v_log_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36766             :   { Feature_HasDPP|Feature_HasDPP, 22369 /* v_log_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36767             :   { Feature_HasDPP|Feature_HasDPP, 22369 /* v_log_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   36768             :   { Feature_HasDPP|Feature_HasDPP, 22369 /* v_log_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   36769             :   { Feature_HasDPP|Feature_HasDPP, 22369 /* v_log_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36770             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22369 /* v_log_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   36771             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22369 /* v_log_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   36772             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22369 /* v_log_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   36773             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22369 /* v_log_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36774             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22369 /* v_log_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36775             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22369 /* v_log_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36776             :   { Feature_isGCN|Feature_isSICI, 22379 /* v_log_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36777             :   { Feature_isGCN|Feature_isSICI, 22379 /* v_log_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36778             :   { Feature_isGCN|Feature_isSICI, 22379 /* v_log_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36779             :   { Feature_isGCN|Feature_isVI, 22379 /* v_log_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36780             :   { Feature_isGCN|Feature_isVI, 22379 /* v_log_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36781             :   { Feature_isGCN|Feature_isVI, 22379 /* v_log_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36782             :   { Feature_HasSDWA|Feature_HasSDWA, 22379 /* v_log_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36783             :   { Feature_HasSDWA|Feature_HasSDWA, 22379 /* v_log_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36784             :   { Feature_HasSDWA|Feature_HasSDWA, 22379 /* v_log_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36785             :   { Feature_HasSDWA|Feature_HasSDWA, 22379 /* v_log_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36786             :   { Feature_HasSDWA|Feature_HasSDWA, 22379 /* v_log_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36787             :   { Feature_HasDPP|Feature_HasDPP, 22379 /* v_log_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36788             :   { Feature_HasDPP|Feature_HasDPP, 22379 /* v_log_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36789             :   { Feature_HasDPP|Feature_HasDPP, 22379 /* v_log_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36790             :   { Feature_HasDPP|Feature_HasDPP, 22379 /* v_log_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36791             :   { Feature_HasDPP|Feature_HasDPP, 22379 /* v_log_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36792             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22379 /* v_log_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36793             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22379 /* v_log_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36794             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22379 /* v_log_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36795             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22379 /* v_log_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36796             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22379 /* v_log_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36797             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22379 /* v_log_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36798             :   { Feature_isCIVI|Feature_isCIOnly, 22389 /* v_log_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36799             :   { Feature_isCIVI|Feature_isCIOnly, 22389 /* v_log_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36800             :   { Feature_isCIVI|Feature_isCIOnly, 22389 /* v_log_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36801             :   { Feature_isCIVI|Feature_isVI, 22389 /* v_log_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   36802             :   { Feature_isCIVI|Feature_isVI, 22389 /* v_log_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36803             :   { Feature_isCIVI|Feature_isVI, 22389 /* v_log_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36804             :   { Feature_isCIVI|Feature_HasSDWA, 22389 /* v_log_legacy_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36805             :   { Feature_isCIVI|Feature_HasSDWA, 22389 /* v_log_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36806             :   { Feature_isCIVI|Feature_HasSDWA, 22389 /* v_log_legacy_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   36807             :   { Feature_isCIVI|Feature_HasSDWA, 22389 /* v_log_legacy_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   36808             :   { Feature_isCIVI|Feature_HasSDWA, 22389 /* v_log_legacy_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   36809             :   { Feature_HasDPP|Feature_HasDPP, 22389 /* v_log_legacy_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   36810             :   { Feature_HasDPP|Feature_HasDPP, 22389 /* v_log_legacy_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   36811             :   { Feature_HasDPP|Feature_HasDPP, 22389 /* v_log_legacy_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   36812             :   { Feature_HasDPP|Feature_HasDPP, 22389 /* v_log_legacy_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   36813             :   { Feature_HasDPP|Feature_HasDPP, 22389 /* v_log_legacy_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   36814             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22389 /* v_log_legacy_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   36815             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22389 /* v_log_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   36816             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22389 /* v_log_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   36817             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22389 /* v_log_legacy_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36818             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22389 /* v_log_legacy_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36819             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22389 /* v_log_legacy_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36820             :   { Feature_HasDPP|Feature_HasDPP, 22457 /* v_lshlrev_b16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36821             :   { Feature_HasDPP|Feature_HasDPP, 22457 /* v_lshlrev_b16 */, MCK_ImmRowMask, 16 /* 4 */ },
   36822             :   { Feature_HasDPP|Feature_HasDPP, 22457 /* v_lshlrev_b16 */, MCK_ImmBankMask, 32 /* 5 */ },
   36823             :   { Feature_HasDPP|Feature_HasDPP, 22457 /* v_lshlrev_b16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36824             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22457 /* v_lshlrev_b16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   36825             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22457 /* v_lshlrev_b16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36826             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36827             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36828             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36829             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36830             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22457 /* v_lshlrev_b16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   36831             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22457 /* v_lshlrev_b16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36832             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36833             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36834             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36835             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22457 /* v_lshlrev_b16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36836             :   { Feature_HasDPP|Feature_HasDPP, 22471 /* v_lshlrev_b32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36837             :   { Feature_HasDPP|Feature_HasDPP, 22471 /* v_lshlrev_b32 */, MCK_ImmRowMask, 16 /* 4 */ },
   36838             :   { Feature_HasDPP|Feature_HasDPP, 22471 /* v_lshlrev_b32 */, MCK_ImmBankMask, 32 /* 5 */ },
   36839             :   { Feature_HasDPP|Feature_HasDPP, 22471 /* v_lshlrev_b32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36840             :   { Feature_isGCN|Feature_HasSDWA, 22471 /* v_lshlrev_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   36841             :   { Feature_isGCN|Feature_HasSDWA, 22471 /* v_lshlrev_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36842             :   { Feature_isGCN|Feature_HasSDWA, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36843             :   { Feature_isGCN|Feature_HasSDWA, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36844             :   { Feature_isGCN|Feature_HasSDWA, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36845             :   { Feature_isGCN|Feature_HasSDWA, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36846             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22471 /* v_lshlrev_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   36847             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22471 /* v_lshlrev_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36848             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36849             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36850             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36851             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22471 /* v_lshlrev_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36852             :   { Feature_HasDPP|Feature_HasDPP, 22521 /* v_lshrrev_b16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36853             :   { Feature_HasDPP|Feature_HasDPP, 22521 /* v_lshrrev_b16 */, MCK_ImmRowMask, 16 /* 4 */ },
   36854             :   { Feature_HasDPP|Feature_HasDPP, 22521 /* v_lshrrev_b16 */, MCK_ImmBankMask, 32 /* 5 */ },
   36855             :   { Feature_HasDPP|Feature_HasDPP, 22521 /* v_lshrrev_b16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36856             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22521 /* v_lshrrev_b16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   36857             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22521 /* v_lshrrev_b16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36858             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36859             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36860             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36861             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36862             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22521 /* v_lshrrev_b16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   36863             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22521 /* v_lshrrev_b16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36864             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36865             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36866             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36867             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22521 /* v_lshrrev_b16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36868             :   { Feature_HasDPP|Feature_HasDPP, 22535 /* v_lshrrev_b32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36869             :   { Feature_HasDPP|Feature_HasDPP, 22535 /* v_lshrrev_b32 */, MCK_ImmRowMask, 16 /* 4 */ },
   36870             :   { Feature_HasDPP|Feature_HasDPP, 22535 /* v_lshrrev_b32 */, MCK_ImmBankMask, 32 /* 5 */ },
   36871             :   { Feature_HasDPP|Feature_HasDPP, 22535 /* v_lshrrev_b32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36872             :   { Feature_isGCN|Feature_HasSDWA, 22535 /* v_lshrrev_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   36873             :   { Feature_isGCN|Feature_HasSDWA, 22535 /* v_lshrrev_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36874             :   { Feature_isGCN|Feature_HasSDWA, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36875             :   { Feature_isGCN|Feature_HasSDWA, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36876             :   { Feature_isGCN|Feature_HasSDWA, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36877             :   { Feature_isGCN|Feature_HasSDWA, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36878             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22535 /* v_lshrrev_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   36879             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22535 /* v_lshrrev_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36880             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36881             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36882             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36883             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22535 /* v_lshrrev_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36884             :   { Feature_Has16BitInsts|Feature_isVI, 22563 /* v_mac_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   36885             :   { Feature_Has16BitInsts|Feature_isVI, 22563 /* v_mac_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   36886             :   { Feature_Has16BitInsts|Feature_isVI, 22563 /* v_mac_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36887             :   { Feature_HasDPP|Feature_HasDPP, 22563 /* v_mac_f16 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   36888             :   { Feature_HasDPP|Feature_HasDPP, 22563 /* v_mac_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36889             :   { Feature_HasDPP|Feature_HasDPP, 22563 /* v_mac_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   36890             :   { Feature_HasDPP|Feature_HasDPP, 22563 /* v_mac_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   36891             :   { Feature_HasDPP|Feature_HasDPP, 22563 /* v_mac_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36892             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22563 /* v_mac_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   36893             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22563 /* v_mac_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36894             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22563 /* v_mac_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36895             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22563 /* v_mac_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36896             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22563 /* v_mac_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36897             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22563 /* v_mac_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36898             :   { Feature_isGCN|Feature_isSICI, 22573 /* v_mac_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36899             :   { Feature_isGCN|Feature_isSICI, 22573 /* v_mac_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36900             :   { Feature_isGCN|Feature_isSICI, 22573 /* v_mac_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36901             :   { Feature_isGCN|Feature_isVI, 22573 /* v_mac_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36902             :   { Feature_isGCN|Feature_isVI, 22573 /* v_mac_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36903             :   { Feature_isGCN|Feature_isVI, 22573 /* v_mac_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36904             :   { Feature_HasDPP|Feature_HasDPP, 22573 /* v_mac_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   36905             :   { Feature_HasDPP|Feature_HasDPP, 22573 /* v_mac_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36906             :   { Feature_HasDPP|Feature_HasDPP, 22573 /* v_mac_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   36907             :   { Feature_HasDPP|Feature_HasDPP, 22573 /* v_mac_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   36908             :   { Feature_HasDPP|Feature_HasDPP, 22573 /* v_mac_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36909             :   { Feature_isGCN|Feature_HasSDWA, 22573 /* v_mac_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   36910             :   { Feature_isGCN|Feature_HasSDWA, 22573 /* v_mac_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36911             :   { Feature_isGCN|Feature_HasSDWA, 22573 /* v_mac_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   36912             :   { Feature_isGCN|Feature_HasSDWA, 22573 /* v_mac_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   36913             :   { Feature_isGCN|Feature_HasSDWA, 22573 /* v_mac_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   36914             :   { Feature_isGCN|Feature_HasSDWA, 22573 /* v_mac_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   36915             :   { Feature_isSICI|Feature_isSICI, 22583 /* v_mac_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   36916             :   { Feature_isSICI|Feature_isSICI, 22583 /* v_mac_legacy_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   36917             :   { Feature_isSICI|Feature_isSICI, 22583 /* v_mac_legacy_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   36918             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22600 /* v_mad_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36919             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22600 /* v_mad_f16 */, MCK_ImmOModSI, 32 /* 5 */ },
   36920             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22600 /* v_mad_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36921             :   { Feature_isGFX9|Feature_isGFX9, 22600 /* v_mad_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36922             :   { Feature_isGFX9|Feature_isGFX9, 22600 /* v_mad_f16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36923             :   { Feature_isGFX9|Feature_isGFX9, 22600 /* v_mad_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36924             :   { Feature_isGCN|Feature_isSICI, 22610 /* v_mad_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36925             :   { Feature_isGCN|Feature_isSICI, 22610 /* v_mad_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36926             :   { Feature_isGCN|Feature_isSICI, 22610 /* v_mad_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36927             :   { Feature_isGCN|Feature_isVI, 22610 /* v_mad_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36928             :   { Feature_isGCN|Feature_isVI, 22610 /* v_mad_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36929             :   { Feature_isGCN|Feature_isVI, 22610 /* v_mad_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36930             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22620 /* v_mad_i16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36931             :   { Feature_isGFX9|Feature_isGFX9, 22620 /* v_mad_i16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36932             :   { Feature_isGFX9|Feature_isGFX9, 22620 /* v_mad_i16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36933             :   { Feature_isGFX9|Feature_isVI, 22630 /* v_mad_i32_i16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36934             :   { Feature_isGFX9|Feature_isVI, 22630 /* v_mad_i32_i16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36935             :   { Feature_isGCN|Feature_isSICI, 22644 /* v_mad_i32_i24 */, MCK_ImmClampSI, 16 /* 4 */ },
   36936             :   { Feature_isGCN|Feature_isVI, 22644 /* v_mad_i32_i24 */, MCK_ImmClampSI, 16 /* 4 */ },
   36937             :   { Feature_isCIVI|Feature_isCIOnly, 22658 /* v_mad_i64_i32 */, MCK_ImmClampSI, 32 /* 5 */ },
   36938             :   { Feature_isCIVI|Feature_isVI, 22658 /* v_mad_i64_i32 */, MCK_ImmClampSI, 32 /* 5 */ },
   36939             :   { Feature_Has16BitInsts|Feature_isGFX9, 22672 /* v_mad_legacy_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36940             :   { Feature_Has16BitInsts|Feature_isGFX9, 22672 /* v_mad_legacy_f16 */, MCK_ImmOModSI, 32 /* 5 */ },
   36941             :   { Feature_Has16BitInsts|Feature_isGFX9, 22672 /* v_mad_legacy_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36942             :   { Feature_isGCN|Feature_isSICI, 22689 /* v_mad_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36943             :   { Feature_isGCN|Feature_isSICI, 22689 /* v_mad_legacy_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36944             :   { Feature_isGCN|Feature_isSICI, 22689 /* v_mad_legacy_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36945             :   { Feature_isGCN|Feature_isVI, 22689 /* v_mad_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36946             :   { Feature_isGCN|Feature_isVI, 22689 /* v_mad_legacy_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36947             :   { Feature_isGCN|Feature_isVI, 22689 /* v_mad_legacy_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36948             :   { Feature_Has16BitInsts|Feature_isGFX9, 22706 /* v_mad_legacy_i16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36949             :   { Feature_Has16BitInsts|Feature_isGFX9, 22723 /* v_mad_legacy_u16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36950             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22740 /* v_mad_mix_f32 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36951             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22740 /* v_mad_mix_f32 */, MCK_ImmClampSI, 64 /* 6 */ },
   36952             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22740 /* v_mad_mix_f32 */, MCK_ImmOpSel, 16 /* 4 */ },
   36953             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22740 /* v_mad_mix_f32 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36954             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22754 /* v_mad_mixhi_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36955             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22754 /* v_mad_mixhi_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36956             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22754 /* v_mad_mixhi_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36957             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22754 /* v_mad_mixhi_f16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36958             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22770 /* v_mad_mixlo_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36959             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22770 /* v_mad_mixlo_f16 */, MCK_ImmClampSI, 64 /* 6 */ },
   36960             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22770 /* v_mad_mixlo_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36961             :   { Feature_HasMadMixInsts|Feature_HasVOP3PInsts, 22770 /* v_mad_mixlo_f16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   36962             :   { Feature_Has16BitInsts|Feature_isVIOnly, 22786 /* v_mad_u16 */, MCK_ImmClampSI, 16 /* 4 */ },
   36963             :   { Feature_isGFX9|Feature_isGFX9, 22786 /* v_mad_u16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36964             :   { Feature_isGFX9|Feature_isGFX9, 22786 /* v_mad_u16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36965             :   { Feature_isGFX9|Feature_isVI, 22796 /* v_mad_u32_u16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36966             :   { Feature_isGFX9|Feature_isVI, 22796 /* v_mad_u32_u16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36967             :   { Feature_isGCN|Feature_isSICI, 22810 /* v_mad_u32_u24 */, MCK_ImmClampSI, 16 /* 4 */ },
   36968             :   { Feature_isGCN|Feature_isVI, 22810 /* v_mad_u32_u24 */, MCK_ImmClampSI, 16 /* 4 */ },
   36969             :   { Feature_isCIVI|Feature_isCIOnly, 22824 /* v_mad_u64_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   36970             :   { Feature_isCIVI|Feature_isVI, 22824 /* v_mad_u64_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   36971             :   { Feature_Has16BitInsts|Feature_isVI, 22838 /* v_madak_f16 */, MCK_KImmFP16, 8 /* 3 */ },
   36972             :   { Feature_isGCN|Feature_isSICI, 22850 /* v_madak_f32 */, MCK_KImmFP32, 8 /* 3 */ },
   36973             :   { Feature_isGCN|Feature_isVI, 22850 /* v_madak_f32 */, MCK_KImmFP32, 8 /* 3 */ },
   36974             :   { Feature_Has16BitInsts|Feature_isVI, 22862 /* v_madmk_f16 */, MCK_KImmFP16, 4 /* 2 */ },
   36975             :   { Feature_isGCN|Feature_isSICI, 22874 /* v_madmk_f32 */, MCK_KImmFP32, 4 /* 2 */ },
   36976             :   { Feature_isGCN|Feature_isVI, 22874 /* v_madmk_f32 */, MCK_KImmFP32, 4 /* 2 */ },
   36977             :   { Feature_isGFX9|Feature_isVI, 22886 /* v_max3_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   36978             :   { Feature_isGFX9|Feature_isVI, 22886 /* v_max3_f16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36979             :   { Feature_isGFX9|Feature_isVI, 22886 /* v_max3_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36980             :   { Feature_isGCN|Feature_isSICI, 22897 /* v_max3_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36981             :   { Feature_isGCN|Feature_isSICI, 22897 /* v_max3_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36982             :   { Feature_isGCN|Feature_isSICI, 22897 /* v_max3_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36983             :   { Feature_isGCN|Feature_isVI, 22897 /* v_max3_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   36984             :   { Feature_isGCN|Feature_isVI, 22897 /* v_max3_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   36985             :   { Feature_isGCN|Feature_isVI, 22897 /* v_max3_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   36986             :   { Feature_isGFX9|Feature_isVI, 22908 /* v_max3_i16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36987             :   { Feature_isGFX9|Feature_isVI, 22908 /* v_max3_i16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36988             :   { Feature_isGFX9|Feature_isVI, 22930 /* v_max3_u16 */, MCK_ImmClampSI, 32 /* 5 */ },
   36989             :   { Feature_isGFX9|Feature_isVI, 22930 /* v_max3_u16 */, MCK_ImmOpSel, 16 /* 4 */ },
   36990             :   { Feature_Has16BitInsts|Feature_isVI, 22952 /* v_max_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   36991             :   { Feature_Has16BitInsts|Feature_isVI, 22952 /* v_max_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   36992             :   { Feature_Has16BitInsts|Feature_isVI, 22952 /* v_max_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   36993             :   { Feature_HasDPP|Feature_HasDPP, 22952 /* v_max_f16 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   36994             :   { Feature_HasDPP|Feature_HasDPP, 22952 /* v_max_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   36995             :   { Feature_HasDPP|Feature_HasDPP, 22952 /* v_max_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   36996             :   { Feature_HasDPP|Feature_HasDPP, 22952 /* v_max_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   36997             :   { Feature_HasDPP|Feature_HasDPP, 22952 /* v_max_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   36998             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22952 /* v_max_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   36999             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22952 /* v_max_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37000             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22952 /* v_max_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37001             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22952 /* v_max_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37002             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22952 /* v_max_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37003             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22952 /* v_max_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37004             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22952 /* v_max_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   37005             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22952 /* v_max_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   37006             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22952 /* v_max_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37007             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22952 /* v_max_f16 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37008             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22952 /* v_max_f16 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37009             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22952 /* v_max_f16 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37010             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22952 /* v_max_f16 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37011             :   { Feature_isGCN|Feature_isSICI, 22962 /* v_max_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37012             :   { Feature_isGCN|Feature_isSICI, 22962 /* v_max_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37013             :   { Feature_isGCN|Feature_isSICI, 22962 /* v_max_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37014             :   { Feature_isGCN|Feature_isVI, 22962 /* v_max_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37015             :   { Feature_isGCN|Feature_isVI, 22962 /* v_max_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37016             :   { Feature_isGCN|Feature_isVI, 22962 /* v_max_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37017             :   { Feature_HasDPP|Feature_HasDPP, 22962 /* v_max_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37018             :   { Feature_HasDPP|Feature_HasDPP, 22962 /* v_max_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37019             :   { Feature_HasDPP|Feature_HasDPP, 22962 /* v_max_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37020             :   { Feature_HasDPP|Feature_HasDPP, 22962 /* v_max_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37021             :   { Feature_HasDPP|Feature_HasDPP, 22962 /* v_max_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37022             :   { Feature_isGCN|Feature_HasSDWA, 22962 /* v_max_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37023             :   { Feature_isGCN|Feature_HasSDWA, 22962 /* v_max_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37024             :   { Feature_isGCN|Feature_HasSDWA, 22962 /* v_max_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37025             :   { Feature_isGCN|Feature_HasSDWA, 22962 /* v_max_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37026             :   { Feature_isGCN|Feature_HasSDWA, 22962 /* v_max_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37027             :   { Feature_isGCN|Feature_HasSDWA, 22962 /* v_max_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37028             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22962 /* v_max_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37029             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22962 /* v_max_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37030             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22962 /* v_max_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37031             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22962 /* v_max_f32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37032             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22962 /* v_max_f32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37033             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22962 /* v_max_f32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37034             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22962 /* v_max_f32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37035             :   { Feature_isGCN|Feature_isSICI, 22972 /* v_max_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   37036             :   { Feature_isGCN|Feature_isSICI, 22972 /* v_max_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   37037             :   { Feature_isGCN|Feature_isSICI, 22972 /* v_max_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   37038             :   { Feature_isGCN|Feature_isVI, 22972 /* v_max_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   37039             :   { Feature_isGCN|Feature_isVI, 22972 /* v_max_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   37040             :   { Feature_isGCN|Feature_isVI, 22972 /* v_max_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   37041             :   { Feature_HasDPP|Feature_HasDPP, 22982 /* v_max_i16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37042             :   { Feature_HasDPP|Feature_HasDPP, 22982 /* v_max_i16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37043             :   { Feature_HasDPP|Feature_HasDPP, 22982 /* v_max_i16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37044             :   { Feature_HasDPP|Feature_HasDPP, 22982 /* v_max_i16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37045             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22982 /* v_max_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37046             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22982 /* v_max_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37047             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22982 /* v_max_i16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37048             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22982 /* v_max_i16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37049             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22982 /* v_max_i16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37050             :   { Feature_Has16BitInsts|Feature_HasSDWA, 22982 /* v_max_i16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37051             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22982 /* v_max_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37052             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22982 /* v_max_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37053             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22982 /* v_max_i16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37054             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22982 /* v_max_i16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37055             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22982 /* v_max_i16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37056             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22982 /* v_max_i16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37057             :   { Feature_HasDPP|Feature_HasDPP, 22992 /* v_max_i32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37058             :   { Feature_HasDPP|Feature_HasDPP, 22992 /* v_max_i32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37059             :   { Feature_HasDPP|Feature_HasDPP, 22992 /* v_max_i32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37060             :   { Feature_HasDPP|Feature_HasDPP, 22992 /* v_max_i32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37061             :   { Feature_isGCN|Feature_HasSDWA, 22992 /* v_max_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37062             :   { Feature_isGCN|Feature_HasSDWA, 22992 /* v_max_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37063             :   { Feature_isGCN|Feature_HasSDWA, 22992 /* v_max_i32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37064             :   { Feature_isGCN|Feature_HasSDWA, 22992 /* v_max_i32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37065             :   { Feature_isGCN|Feature_HasSDWA, 22992 /* v_max_i32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37066             :   { Feature_isGCN|Feature_HasSDWA, 22992 /* v_max_i32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37067             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22992 /* v_max_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37068             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22992 /* v_max_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37069             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22992 /* v_max_i32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37070             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22992 /* v_max_i32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37071             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22992 /* v_max_i32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37072             :   { Feature_HasSDWA9|Feature_HasSDWA9, 22992 /* v_max_i32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37073             :   { Feature_isSICI|Feature_isSICI, 23002 /* v_max_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37074             :   { Feature_isSICI|Feature_isSICI, 23002 /* v_max_legacy_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37075             :   { Feature_isSICI|Feature_isSICI, 23002 /* v_max_legacy_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37076             :   { Feature_HasDPP|Feature_HasDPP, 23019 /* v_max_u16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37077             :   { Feature_HasDPP|Feature_HasDPP, 23019 /* v_max_u16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37078             :   { Feature_HasDPP|Feature_HasDPP, 23019 /* v_max_u16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37079             :   { Feature_HasDPP|Feature_HasDPP, 23019 /* v_max_u16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37080             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23019 /* v_max_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37081             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23019 /* v_max_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37082             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23019 /* v_max_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37083             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23019 /* v_max_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37084             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23019 /* v_max_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37085             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23019 /* v_max_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37086             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23019 /* v_max_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37087             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23019 /* v_max_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37088             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23019 /* v_max_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37089             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23019 /* v_max_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37090             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23019 /* v_max_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37091             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23019 /* v_max_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37092             :   { Feature_HasDPP|Feature_HasDPP, 23029 /* v_max_u32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37093             :   { Feature_HasDPP|Feature_HasDPP, 23029 /* v_max_u32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37094             :   { Feature_HasDPP|Feature_HasDPP, 23029 /* v_max_u32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37095             :   { Feature_HasDPP|Feature_HasDPP, 23029 /* v_max_u32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37096             :   { Feature_isGCN|Feature_HasSDWA, 23029 /* v_max_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37097             :   { Feature_isGCN|Feature_HasSDWA, 23029 /* v_max_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37098             :   { Feature_isGCN|Feature_HasSDWA, 23029 /* v_max_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37099             :   { Feature_isGCN|Feature_HasSDWA, 23029 /* v_max_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37100             :   { Feature_isGCN|Feature_HasSDWA, 23029 /* v_max_u32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37101             :   { Feature_isGCN|Feature_HasSDWA, 23029 /* v_max_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37102             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23029 /* v_max_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37103             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23029 /* v_max_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37104             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23029 /* v_max_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37105             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23029 /* v_max_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37106             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23029 /* v_max_u32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37107             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23029 /* v_max_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37108             :   { Feature_isGFX9|Feature_isVI, 23077 /* v_med3_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   37109             :   { Feature_isGFX9|Feature_isVI, 23077 /* v_med3_f16 */, MCK_ImmClampSI, 32 /* 5 */ },
   37110             :   { Feature_isGFX9|Feature_isVI, 23077 /* v_med3_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37111             :   { Feature_isGCN|Feature_isSICI, 23088 /* v_med3_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   37112             :   { Feature_isGCN|Feature_isSICI, 23088 /* v_med3_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   37113             :   { Feature_isGCN|Feature_isSICI, 23088 /* v_med3_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37114             :   { Feature_isGCN|Feature_isVI, 23088 /* v_med3_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   37115             :   { Feature_isGCN|Feature_isVI, 23088 /* v_med3_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   37116             :   { Feature_isGCN|Feature_isVI, 23088 /* v_med3_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37117             :   { Feature_isGFX9|Feature_isVI, 23099 /* v_med3_i16 */, MCK_ImmClampSI, 32 /* 5 */ },
   37118             :   { Feature_isGFX9|Feature_isVI, 23099 /* v_med3_i16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37119             :   { Feature_isGFX9|Feature_isVI, 23121 /* v_med3_u16 */, MCK_ImmClampSI, 32 /* 5 */ },
   37120             :   { Feature_isGFX9|Feature_isVI, 23121 /* v_med3_u16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37121             :   { Feature_isGFX9|Feature_isVI, 23143 /* v_min3_f16 */, MCK_RegOrImmWithFP16InputMods, 14 /* 1, 2, 3 */ },
   37122             :   { Feature_isGFX9|Feature_isVI, 23143 /* v_min3_f16 */, MCK_ImmClampSI, 32 /* 5 */ },
   37123             :   { Feature_isGFX9|Feature_isVI, 23143 /* v_min3_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37124             :   { Feature_isGCN|Feature_isSICI, 23154 /* v_min3_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   37125             :   { Feature_isGCN|Feature_isSICI, 23154 /* v_min3_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   37126             :   { Feature_isGCN|Feature_isSICI, 23154 /* v_min3_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37127             :   { Feature_isGCN|Feature_isVI, 23154 /* v_min3_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   37128             :   { Feature_isGCN|Feature_isVI, 23154 /* v_min3_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   37129             :   { Feature_isGCN|Feature_isVI, 23154 /* v_min3_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37130             :   { Feature_isGFX9|Feature_isVI, 23165 /* v_min3_i16 */, MCK_ImmClampSI, 32 /* 5 */ },
   37131             :   { Feature_isGFX9|Feature_isVI, 23165 /* v_min3_i16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37132             :   { Feature_isGFX9|Feature_isVI, 23187 /* v_min3_u16 */, MCK_ImmClampSI, 32 /* 5 */ },
   37133             :   { Feature_isGFX9|Feature_isVI, 23187 /* v_min3_u16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37134             :   { Feature_Has16BitInsts|Feature_isVI, 23209 /* v_min_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   37135             :   { Feature_Has16BitInsts|Feature_isVI, 23209 /* v_min_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   37136             :   { Feature_Has16BitInsts|Feature_isVI, 23209 /* v_min_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37137             :   { Feature_HasDPP|Feature_HasDPP, 23209 /* v_min_f16 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37138             :   { Feature_HasDPP|Feature_HasDPP, 23209 /* v_min_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37139             :   { Feature_HasDPP|Feature_HasDPP, 23209 /* v_min_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37140             :   { Feature_HasDPP|Feature_HasDPP, 23209 /* v_min_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37141             :   { Feature_HasDPP|Feature_HasDPP, 23209 /* v_min_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37142             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23209 /* v_min_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   37143             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23209 /* v_min_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37144             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23209 /* v_min_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37145             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23209 /* v_min_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37146             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23209 /* v_min_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37147             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23209 /* v_min_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37148             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23209 /* v_min_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   37149             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23209 /* v_min_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   37150             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23209 /* v_min_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37151             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23209 /* v_min_f16 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37152             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23209 /* v_min_f16 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37153             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23209 /* v_min_f16 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37154             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23209 /* v_min_f16 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37155             :   { Feature_isGCN|Feature_isSICI, 23219 /* v_min_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37156             :   { Feature_isGCN|Feature_isSICI, 23219 /* v_min_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37157             :   { Feature_isGCN|Feature_isSICI, 23219 /* v_min_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37158             :   { Feature_isGCN|Feature_isVI, 23219 /* v_min_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37159             :   { Feature_isGCN|Feature_isVI, 23219 /* v_min_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37160             :   { Feature_isGCN|Feature_isVI, 23219 /* v_min_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37161             :   { Feature_HasDPP|Feature_HasDPP, 23219 /* v_min_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37162             :   { Feature_HasDPP|Feature_HasDPP, 23219 /* v_min_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37163             :   { Feature_HasDPP|Feature_HasDPP, 23219 /* v_min_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37164             :   { Feature_HasDPP|Feature_HasDPP, 23219 /* v_min_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37165             :   { Feature_HasDPP|Feature_HasDPP, 23219 /* v_min_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37166             :   { Feature_isGCN|Feature_HasSDWA, 23219 /* v_min_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37167             :   { Feature_isGCN|Feature_HasSDWA, 23219 /* v_min_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37168             :   { Feature_isGCN|Feature_HasSDWA, 23219 /* v_min_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37169             :   { Feature_isGCN|Feature_HasSDWA, 23219 /* v_min_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37170             :   { Feature_isGCN|Feature_HasSDWA, 23219 /* v_min_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37171             :   { Feature_isGCN|Feature_HasSDWA, 23219 /* v_min_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37172             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23219 /* v_min_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37173             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23219 /* v_min_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37174             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23219 /* v_min_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37175             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23219 /* v_min_f32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37176             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23219 /* v_min_f32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37177             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23219 /* v_min_f32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37178             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23219 /* v_min_f32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37179             :   { Feature_isGCN|Feature_isSICI, 23229 /* v_min_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   37180             :   { Feature_isGCN|Feature_isSICI, 23229 /* v_min_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   37181             :   { Feature_isGCN|Feature_isSICI, 23229 /* v_min_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   37182             :   { Feature_isGCN|Feature_isVI, 23229 /* v_min_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   37183             :   { Feature_isGCN|Feature_isVI, 23229 /* v_min_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   37184             :   { Feature_isGCN|Feature_isVI, 23229 /* v_min_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   37185             :   { Feature_HasDPP|Feature_HasDPP, 23239 /* v_min_i16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37186             :   { Feature_HasDPP|Feature_HasDPP, 23239 /* v_min_i16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37187             :   { Feature_HasDPP|Feature_HasDPP, 23239 /* v_min_i16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37188             :   { Feature_HasDPP|Feature_HasDPP, 23239 /* v_min_i16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37189             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23239 /* v_min_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37190             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23239 /* v_min_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37191             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23239 /* v_min_i16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37192             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23239 /* v_min_i16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37193             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23239 /* v_min_i16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37194             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23239 /* v_min_i16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37195             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23239 /* v_min_i16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37196             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23239 /* v_min_i16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37197             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23239 /* v_min_i16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37198             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23239 /* v_min_i16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37199             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23239 /* v_min_i16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37200             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23239 /* v_min_i16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37201             :   { Feature_HasDPP|Feature_HasDPP, 23249 /* v_min_i32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37202             :   { Feature_HasDPP|Feature_HasDPP, 23249 /* v_min_i32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37203             :   { Feature_HasDPP|Feature_HasDPP, 23249 /* v_min_i32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37204             :   { Feature_HasDPP|Feature_HasDPP, 23249 /* v_min_i32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37205             :   { Feature_isGCN|Feature_HasSDWA, 23249 /* v_min_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37206             :   { Feature_isGCN|Feature_HasSDWA, 23249 /* v_min_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37207             :   { Feature_isGCN|Feature_HasSDWA, 23249 /* v_min_i32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37208             :   { Feature_isGCN|Feature_HasSDWA, 23249 /* v_min_i32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37209             :   { Feature_isGCN|Feature_HasSDWA, 23249 /* v_min_i32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37210             :   { Feature_isGCN|Feature_HasSDWA, 23249 /* v_min_i32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37211             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23249 /* v_min_i32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37212             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23249 /* v_min_i32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37213             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23249 /* v_min_i32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37214             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23249 /* v_min_i32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37215             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23249 /* v_min_i32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37216             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23249 /* v_min_i32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37217             :   { Feature_isSICI|Feature_isSICI, 23259 /* v_min_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37218             :   { Feature_isSICI|Feature_isSICI, 23259 /* v_min_legacy_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37219             :   { Feature_isSICI|Feature_isSICI, 23259 /* v_min_legacy_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37220             :   { Feature_HasDPP|Feature_HasDPP, 23276 /* v_min_u16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37221             :   { Feature_HasDPP|Feature_HasDPP, 23276 /* v_min_u16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37222             :   { Feature_HasDPP|Feature_HasDPP, 23276 /* v_min_u16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37223             :   { Feature_HasDPP|Feature_HasDPP, 23276 /* v_min_u16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37224             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23276 /* v_min_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37225             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23276 /* v_min_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37226             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23276 /* v_min_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37227             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23276 /* v_min_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37228             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23276 /* v_min_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37229             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23276 /* v_min_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37230             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23276 /* v_min_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37231             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23276 /* v_min_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37232             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23276 /* v_min_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37233             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23276 /* v_min_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37234             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23276 /* v_min_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37235             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23276 /* v_min_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37236             :   { Feature_HasDPP|Feature_HasDPP, 23286 /* v_min_u32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37237             :   { Feature_HasDPP|Feature_HasDPP, 23286 /* v_min_u32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37238             :   { Feature_HasDPP|Feature_HasDPP, 23286 /* v_min_u32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37239             :   { Feature_HasDPP|Feature_HasDPP, 23286 /* v_min_u32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37240             :   { Feature_isGCN|Feature_HasSDWA, 23286 /* v_min_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37241             :   { Feature_isGCN|Feature_HasSDWA, 23286 /* v_min_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37242             :   { Feature_isGCN|Feature_HasSDWA, 23286 /* v_min_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37243             :   { Feature_isGCN|Feature_HasSDWA, 23286 /* v_min_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37244             :   { Feature_isGCN|Feature_HasSDWA, 23286 /* v_min_u32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37245             :   { Feature_isGCN|Feature_HasSDWA, 23286 /* v_min_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37246             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23286 /* v_min_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37247             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23286 /* v_min_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37248             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23286 /* v_min_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37249             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23286 /* v_min_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37250             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23286 /* v_min_u32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37251             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23286 /* v_min_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37252             :   { Feature_HasDPP|Feature_HasDPP, 23296 /* v_mov_b32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37253             :   { Feature_HasDPP|Feature_HasDPP, 23296 /* v_mov_b32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37254             :   { Feature_HasDPP|Feature_HasDPP, 23296 /* v_mov_b32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37255             :   { Feature_HasDPP|Feature_HasDPP, 23296 /* v_mov_b32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37256             :   { Feature_HasSDWA|Feature_HasSDWA, 23296 /* v_mov_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37257             :   { Feature_HasSDWA|Feature_HasSDWA, 23296 /* v_mov_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37258             :   { Feature_HasSDWA|Feature_HasSDWA, 23296 /* v_mov_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37259             :   { Feature_HasSDWA|Feature_HasSDWA, 23296 /* v_mov_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37260             :   { Feature_HasSDWA|Feature_HasSDWA, 23296 /* v_mov_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37261             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23296 /* v_mov_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37262             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23296 /* v_mov_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37263             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23296 /* v_mov_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37264             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23296 /* v_mov_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37265             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23296 /* v_mov_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37266             :   { Feature_HasDPP|Feature_HasDPP, 23306 /* v_mov_fed_b32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37267             :   { Feature_HasDPP|Feature_HasDPP, 23306 /* v_mov_fed_b32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37268             :   { Feature_HasDPP|Feature_HasDPP, 23306 /* v_mov_fed_b32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37269             :   { Feature_HasDPP|Feature_HasDPP, 23306 /* v_mov_fed_b32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37270             :   { Feature_HasSDWA|Feature_HasSDWA, 23306 /* v_mov_fed_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37271             :   { Feature_HasSDWA|Feature_HasSDWA, 23306 /* v_mov_fed_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37272             :   { Feature_HasSDWA|Feature_HasSDWA, 23306 /* v_mov_fed_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37273             :   { Feature_HasSDWA|Feature_HasSDWA, 23306 /* v_mov_fed_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37274             :   { Feature_HasSDWA|Feature_HasSDWA, 23306 /* v_mov_fed_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37275             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23306 /* v_mov_fed_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37276             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23306 /* v_mov_fed_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37277             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23306 /* v_mov_fed_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37278             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23306 /* v_mov_fed_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37279             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23306 /* v_mov_fed_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37280             :   { Feature_isGCN|Feature_isSICI, 23363 /* v_mqsad_pk_u16_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37281             :   { Feature_isGCN|Feature_isVI, 23363 /* v_mqsad_pk_u16_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37282             :   { Feature_isCIVI|Feature_isCIOnly, 23381 /* v_mqsad_u32_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37283             :   { Feature_isCIVI|Feature_isVI, 23381 /* v_mqsad_u32_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37284             :   { Feature_isGCN|Feature_isSICI, 23396 /* v_msad_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37285             :   { Feature_isGCN|Feature_isVI, 23396 /* v_msad_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37286             :   { Feature_Has16BitInsts|Feature_isVI, 23406 /* v_mul_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   37287             :   { Feature_Has16BitInsts|Feature_isVI, 23406 /* v_mul_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   37288             :   { Feature_Has16BitInsts|Feature_isVI, 23406 /* v_mul_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37289             :   { Feature_HasDPP|Feature_HasDPP, 23406 /* v_mul_f16 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37290             :   { Feature_HasDPP|Feature_HasDPP, 23406 /* v_mul_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37291             :   { Feature_HasDPP|Feature_HasDPP, 23406 /* v_mul_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37292             :   { Feature_HasDPP|Feature_HasDPP, 23406 /* v_mul_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37293             :   { Feature_HasDPP|Feature_HasDPP, 23406 /* v_mul_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37294             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23406 /* v_mul_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   37295             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23406 /* v_mul_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37296             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23406 /* v_mul_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37297             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23406 /* v_mul_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37298             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23406 /* v_mul_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37299             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23406 /* v_mul_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37300             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23406 /* v_mul_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   37301             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23406 /* v_mul_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   37302             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23406 /* v_mul_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37303             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23406 /* v_mul_f16 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37304             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23406 /* v_mul_f16 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37305             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23406 /* v_mul_f16 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37306             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23406 /* v_mul_f16 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37307             :   { Feature_isGCN|Feature_isSICI, 23416 /* v_mul_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37308             :   { Feature_isGCN|Feature_isSICI, 23416 /* v_mul_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37309             :   { Feature_isGCN|Feature_isSICI, 23416 /* v_mul_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37310             :   { Feature_isGCN|Feature_isVI, 23416 /* v_mul_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37311             :   { Feature_isGCN|Feature_isVI, 23416 /* v_mul_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37312             :   { Feature_isGCN|Feature_isVI, 23416 /* v_mul_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37313             :   { Feature_HasDPP|Feature_HasDPP, 23416 /* v_mul_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37314             :   { Feature_HasDPP|Feature_HasDPP, 23416 /* v_mul_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37315             :   { Feature_HasDPP|Feature_HasDPP, 23416 /* v_mul_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37316             :   { Feature_HasDPP|Feature_HasDPP, 23416 /* v_mul_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37317             :   { Feature_HasDPP|Feature_HasDPP, 23416 /* v_mul_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37318             :   { Feature_isGCN|Feature_HasSDWA, 23416 /* v_mul_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37319             :   { Feature_isGCN|Feature_HasSDWA, 23416 /* v_mul_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37320             :   { Feature_isGCN|Feature_HasSDWA, 23416 /* v_mul_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37321             :   { Feature_isGCN|Feature_HasSDWA, 23416 /* v_mul_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37322             :   { Feature_isGCN|Feature_HasSDWA, 23416 /* v_mul_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37323             :   { Feature_isGCN|Feature_HasSDWA, 23416 /* v_mul_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37324             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23416 /* v_mul_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37325             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23416 /* v_mul_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37326             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23416 /* v_mul_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37327             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23416 /* v_mul_f32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37328             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23416 /* v_mul_f32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37329             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23416 /* v_mul_f32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37330             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23416 /* v_mul_f32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37331             :   { Feature_isGCN|Feature_isSICI, 23426 /* v_mul_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   37332             :   { Feature_isGCN|Feature_isSICI, 23426 /* v_mul_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   37333             :   { Feature_isGCN|Feature_isSICI, 23426 /* v_mul_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   37334             :   { Feature_isGCN|Feature_isVI, 23426 /* v_mul_f64 */, MCK_RegOrImmWithFP64InputMods, 6 /* 1, 2 */ },
   37335             :   { Feature_isGCN|Feature_isVI, 23426 /* v_mul_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   37336             :   { Feature_isGCN|Feature_isVI, 23426 /* v_mul_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   37337             :   { Feature_HasDPP|Feature_HasDPP, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37338             :   { Feature_HasDPP|Feature_HasDPP, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmRowMask, 16 /* 4 */ },
   37339             :   { Feature_HasDPP|Feature_HasDPP, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmBankMask, 32 /* 5 */ },
   37340             :   { Feature_HasDPP|Feature_HasDPP, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37341             :   { Feature_isGCN|Feature_HasSDWA, 23449 /* v_mul_hi_i32_i24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37342             :   { Feature_isGCN|Feature_HasSDWA, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37343             :   { Feature_isGCN|Feature_HasSDWA, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37344             :   { Feature_isGCN|Feature_HasSDWA, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37345             :   { Feature_isGCN|Feature_HasSDWA, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37346             :   { Feature_isGCN|Feature_HasSDWA, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37347             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23449 /* v_mul_hi_i32_i24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37348             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37349             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37350             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37351             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37352             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23449 /* v_mul_hi_i32_i24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37353             :   { Feature_HasDPP|Feature_HasDPP, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37354             :   { Feature_HasDPP|Feature_HasDPP, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmRowMask, 16 /* 4 */ },
   37355             :   { Feature_HasDPP|Feature_HasDPP, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmBankMask, 32 /* 5 */ },
   37356             :   { Feature_HasDPP|Feature_HasDPP, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37357             :   { Feature_isGCN|Feature_HasSDWA, 23479 /* v_mul_hi_u32_u24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37358             :   { Feature_isGCN|Feature_HasSDWA, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37359             :   { Feature_isGCN|Feature_HasSDWA, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37360             :   { Feature_isGCN|Feature_HasSDWA, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37361             :   { Feature_isGCN|Feature_HasSDWA, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37362             :   { Feature_isGCN|Feature_HasSDWA, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37363             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23479 /* v_mul_hi_u32_u24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37364             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37365             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37366             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37367             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37368             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23479 /* v_mul_hi_u32_u24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37369             :   { Feature_HasDPP|Feature_HasDPP, 23496 /* v_mul_i32_i24 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37370             :   { Feature_HasDPP|Feature_HasDPP, 23496 /* v_mul_i32_i24 */, MCK_ImmRowMask, 16 /* 4 */ },
   37371             :   { Feature_HasDPP|Feature_HasDPP, 23496 /* v_mul_i32_i24 */, MCK_ImmBankMask, 32 /* 5 */ },
   37372             :   { Feature_HasDPP|Feature_HasDPP, 23496 /* v_mul_i32_i24 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37373             :   { Feature_isGCN|Feature_HasSDWA, 23496 /* v_mul_i32_i24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37374             :   { Feature_isGCN|Feature_HasSDWA, 23496 /* v_mul_i32_i24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37375             :   { Feature_isGCN|Feature_HasSDWA, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37376             :   { Feature_isGCN|Feature_HasSDWA, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37377             :   { Feature_isGCN|Feature_HasSDWA, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37378             :   { Feature_isGCN|Feature_HasSDWA, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37379             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23496 /* v_mul_i32_i24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37380             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23496 /* v_mul_i32_i24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37381             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37382             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37383             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37384             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23496 /* v_mul_i32_i24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37385             :   { Feature_isGCN|Feature_isSICI, 23510 /* v_mul_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37386             :   { Feature_isGCN|Feature_isSICI, 23510 /* v_mul_legacy_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37387             :   { Feature_isGCN|Feature_isSICI, 23510 /* v_mul_legacy_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37388             :   { Feature_isGCN|Feature_isVI, 23510 /* v_mul_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37389             :   { Feature_isGCN|Feature_isVI, 23510 /* v_mul_legacy_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37390             :   { Feature_isGCN|Feature_isVI, 23510 /* v_mul_legacy_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37391             :   { Feature_HasDPP|Feature_HasDPP, 23510 /* v_mul_legacy_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37392             :   { Feature_HasDPP|Feature_HasDPP, 23510 /* v_mul_legacy_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37393             :   { Feature_HasDPP|Feature_HasDPP, 23510 /* v_mul_legacy_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37394             :   { Feature_HasDPP|Feature_HasDPP, 23510 /* v_mul_legacy_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37395             :   { Feature_HasDPP|Feature_HasDPP, 23510 /* v_mul_legacy_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37396             :   { Feature_isGCN|Feature_HasSDWA, 23510 /* v_mul_legacy_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37397             :   { Feature_isGCN|Feature_HasSDWA, 23510 /* v_mul_legacy_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37398             :   { Feature_isGCN|Feature_HasSDWA, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37399             :   { Feature_isGCN|Feature_HasSDWA, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37400             :   { Feature_isGCN|Feature_HasSDWA, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37401             :   { Feature_isGCN|Feature_HasSDWA, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37402             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23510 /* v_mul_legacy_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37403             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23510 /* v_mul_legacy_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37404             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23510 /* v_mul_legacy_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37405             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37406             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37407             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37408             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23510 /* v_mul_legacy_f32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37409             :   { Feature_HasDPP|Feature_HasDPP, 23540 /* v_mul_lo_u16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37410             :   { Feature_HasDPP|Feature_HasDPP, 23540 /* v_mul_lo_u16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37411             :   { Feature_HasDPP|Feature_HasDPP, 23540 /* v_mul_lo_u16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37412             :   { Feature_HasDPP|Feature_HasDPP, 23540 /* v_mul_lo_u16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37413             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23540 /* v_mul_lo_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37414             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23540 /* v_mul_lo_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37415             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37416             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37417             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37418             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37419             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23540 /* v_mul_lo_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37420             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23540 /* v_mul_lo_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37421             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37422             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37423             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37424             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23540 /* v_mul_lo_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37425             :   { Feature_HasDPP|Feature_HasDPP, 23566 /* v_mul_u32_u24 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37426             :   { Feature_HasDPP|Feature_HasDPP, 23566 /* v_mul_u32_u24 */, MCK_ImmRowMask, 16 /* 4 */ },
   37427             :   { Feature_HasDPP|Feature_HasDPP, 23566 /* v_mul_u32_u24 */, MCK_ImmBankMask, 32 /* 5 */ },
   37428             :   { Feature_HasDPP|Feature_HasDPP, 23566 /* v_mul_u32_u24 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37429             :   { Feature_isGCN|Feature_HasSDWA, 23566 /* v_mul_u32_u24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37430             :   { Feature_isGCN|Feature_HasSDWA, 23566 /* v_mul_u32_u24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37431             :   { Feature_isGCN|Feature_HasSDWA, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37432             :   { Feature_isGCN|Feature_HasSDWA, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37433             :   { Feature_isGCN|Feature_HasSDWA, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37434             :   { Feature_isGCN|Feature_HasSDWA, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37435             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23566 /* v_mul_u32_u24 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37436             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23566 /* v_mul_u32_u24 */, MCK_ImmClampSI, 8 /* 3 */ },
   37437             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37438             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37439             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37440             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23566 /* v_mul_u32_u24 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37441             :   { Feature_isSICI|Feature_isSICI, 23580 /* v_mullit_f32 */, MCK_RegOrImmWithFP32InputMods, 14 /* 1, 2, 3 */ },
   37442             :   { Feature_isSICI|Feature_isSICI, 23580 /* v_mullit_f32 */, MCK_ImmOModSI, 32 /* 5 */ },
   37443             :   { Feature_isSICI|Feature_isSICI, 23580 /* v_mullit_f32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37444             :   { Feature_HasDPP|Feature_HasDPP, 23593 /* v_nop */, MCK_ImmDPPCtrl, 1 /* 0 */ },
   37445             :   { Feature_HasDPP|Feature_HasDPP, 23593 /* v_nop */, MCK_ImmRowMask, 2 /* 1 */ },
   37446             :   { Feature_HasDPP|Feature_HasDPP, 23593 /* v_nop */, MCK_ImmBankMask, 4 /* 2 */ },
   37447             :   { Feature_HasDPP|Feature_HasDPP, 23593 /* v_nop */, MCK_ImmBoundCtrl, 8 /* 3 */ },
   37448             :   { Feature_HasDPP|Feature_HasDPP, 23599 /* v_not_b32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37449             :   { Feature_HasDPP|Feature_HasDPP, 23599 /* v_not_b32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37450             :   { Feature_HasDPP|Feature_HasDPP, 23599 /* v_not_b32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37451             :   { Feature_HasDPP|Feature_HasDPP, 23599 /* v_not_b32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37452             :   { Feature_HasSDWA|Feature_HasSDWA, 23599 /* v_not_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37453             :   { Feature_HasSDWA|Feature_HasSDWA, 23599 /* v_not_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37454             :   { Feature_HasSDWA|Feature_HasSDWA, 23599 /* v_not_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37455             :   { Feature_HasSDWA|Feature_HasSDWA, 23599 /* v_not_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37456             :   { Feature_HasSDWA|Feature_HasSDWA, 23599 /* v_not_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37457             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23599 /* v_not_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37458             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23599 /* v_not_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37459             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23599 /* v_not_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37460             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23599 /* v_not_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37461             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23599 /* v_not_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37462             :   { Feature_HasDPP|Feature_HasDPP, 23619 /* v_or_b32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37463             :   { Feature_HasDPP|Feature_HasDPP, 23619 /* v_or_b32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37464             :   { Feature_HasDPP|Feature_HasDPP, 23619 /* v_or_b32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37465             :   { Feature_HasDPP|Feature_HasDPP, 23619 /* v_or_b32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37466             :   { Feature_isGCN|Feature_HasSDWA, 23619 /* v_or_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37467             :   { Feature_isGCN|Feature_HasSDWA, 23619 /* v_or_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37468             :   { Feature_isGCN|Feature_HasSDWA, 23619 /* v_or_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37469             :   { Feature_isGCN|Feature_HasSDWA, 23619 /* v_or_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37470             :   { Feature_isGCN|Feature_HasSDWA, 23619 /* v_or_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37471             :   { Feature_isGCN|Feature_HasSDWA, 23619 /* v_or_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37472             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23619 /* v_or_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37473             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23619 /* v_or_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37474             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23619 /* v_or_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37475             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23619 /* v_or_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37476             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23619 /* v_or_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37477             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23619 /* v_or_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37478             :   { Feature_isGFX9|Feature_isVI, 23628 /* v_pack_b32_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   37479             :   { Feature_isGFX9|Feature_isVI, 23628 /* v_pack_b32_f16 */, MCK_ImmClampSI, 16 /* 4 */ },
   37480             :   { Feature_isGFX9|Feature_isVI, 23628 /* v_pack_b32_f16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37481             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23654 /* v_pk_add_f16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37482             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23654 /* v_pk_add_f16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37483             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23654 /* v_pk_add_f16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37484             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23654 /* v_pk_add_f16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37485             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23654 /* v_pk_add_f16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37486             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23667 /* v_pk_add_i16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37487             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23667 /* v_pk_add_i16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37488             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23667 /* v_pk_add_i16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37489             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23667 /* v_pk_add_i16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37490             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23667 /* v_pk_add_i16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37491             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23680 /* v_pk_add_u16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37492             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23680 /* v_pk_add_u16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37493             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23680 /* v_pk_add_u16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37494             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23680 /* v_pk_add_u16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37495             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23680 /* v_pk_add_u16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37496             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23693 /* v_pk_ashrrev_i16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37497             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23693 /* v_pk_ashrrev_i16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37498             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23693 /* v_pk_ashrrev_i16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37499             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23693 /* v_pk_ashrrev_i16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37500             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23693 /* v_pk_ashrrev_i16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37501             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23710 /* v_pk_fma_f16 */, MCK_ImmClampSI, 256 /* 8 */ },
   37502             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23710 /* v_pk_fma_f16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37503             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23710 /* v_pk_fma_f16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   37504             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23710 /* v_pk_fma_f16 */, MCK_ImmNegLo, 64 /* 6 */ },
   37505             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23710 /* v_pk_fma_f16 */, MCK_ImmNegHi, 128 /* 7 */ },
   37506             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23723 /* v_pk_lshlrev_b16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37507             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23723 /* v_pk_lshlrev_b16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37508             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23723 /* v_pk_lshlrev_b16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37509             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23723 /* v_pk_lshlrev_b16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37510             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23723 /* v_pk_lshlrev_b16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37511             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23740 /* v_pk_lshrrev_b16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37512             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23740 /* v_pk_lshrrev_b16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37513             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23740 /* v_pk_lshrrev_b16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37514             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23740 /* v_pk_lshrrev_b16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37515             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23740 /* v_pk_lshrrev_b16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37516             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23757 /* v_pk_mad_i16 */, MCK_ImmClampSI, 256 /* 8 */ },
   37517             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23757 /* v_pk_mad_i16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37518             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23757 /* v_pk_mad_i16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   37519             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23757 /* v_pk_mad_i16 */, MCK_ImmNegLo, 64 /* 6 */ },
   37520             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23757 /* v_pk_mad_i16 */, MCK_ImmNegHi, 128 /* 7 */ },
   37521             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23770 /* v_pk_mad_u16 */, MCK_ImmClampSI, 256 /* 8 */ },
   37522             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23770 /* v_pk_mad_u16 */, MCK_ImmOpSel, 16 /* 4 */ },
   37523             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23770 /* v_pk_mad_u16 */, MCK_ImmOpSelHi, 32 /* 5 */ },
   37524             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23770 /* v_pk_mad_u16 */, MCK_ImmNegLo, 64 /* 6 */ },
   37525             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23770 /* v_pk_mad_u16 */, MCK_ImmNegHi, 128 /* 7 */ },
   37526             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23783 /* v_pk_max_f16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37527             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23783 /* v_pk_max_f16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37528             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23783 /* v_pk_max_f16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37529             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23783 /* v_pk_max_f16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37530             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23783 /* v_pk_max_f16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37531             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23796 /* v_pk_max_i16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37532             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23796 /* v_pk_max_i16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37533             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23796 /* v_pk_max_i16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37534             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23796 /* v_pk_max_i16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37535             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23796 /* v_pk_max_i16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37536             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23809 /* v_pk_max_u16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37537             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23809 /* v_pk_max_u16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37538             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23809 /* v_pk_max_u16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37539             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23809 /* v_pk_max_u16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37540             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23809 /* v_pk_max_u16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37541             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23822 /* v_pk_min_f16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37542             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23822 /* v_pk_min_f16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37543             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23822 /* v_pk_min_f16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37544             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23822 /* v_pk_min_f16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37545             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23822 /* v_pk_min_f16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37546             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23835 /* v_pk_min_i16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37547             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23835 /* v_pk_min_i16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37548             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23835 /* v_pk_min_i16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37549             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23835 /* v_pk_min_i16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37550             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23835 /* v_pk_min_i16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37551             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23848 /* v_pk_min_u16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37552             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23848 /* v_pk_min_u16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37553             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23848 /* v_pk_min_u16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37554             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23848 /* v_pk_min_u16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37555             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23848 /* v_pk_min_u16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37556             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23861 /* v_pk_mul_f16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37557             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23861 /* v_pk_mul_f16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37558             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23861 /* v_pk_mul_f16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37559             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23861 /* v_pk_mul_f16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37560             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23861 /* v_pk_mul_f16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37561             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23874 /* v_pk_mul_lo_u16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37562             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23874 /* v_pk_mul_lo_u16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37563             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23874 /* v_pk_mul_lo_u16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37564             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23874 /* v_pk_mul_lo_u16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37565             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23874 /* v_pk_mul_lo_u16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37566             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23890 /* v_pk_sub_i16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37567             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23890 /* v_pk_sub_i16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37568             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23890 /* v_pk_sub_i16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37569             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23890 /* v_pk_sub_i16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37570             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23890 /* v_pk_sub_i16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37571             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23903 /* v_pk_sub_u16 */, MCK_ImmClampSI, 128 /* 7 */ },
   37572             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23903 /* v_pk_sub_u16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37573             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23903 /* v_pk_sub_u16 */, MCK_ImmOpSelHi, 16 /* 4 */ },
   37574             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23903 /* v_pk_sub_u16 */, MCK_ImmNegLo, 32 /* 5 */ },
   37575             :   { Feature_isGCN|Feature_HasVOP3PInsts, 23903 /* v_pk_sub_u16 */, MCK_ImmNegHi, 64 /* 6 */ },
   37576             :   { Feature_isCIVI|Feature_isCIOnly, 23916 /* v_qsad_pk_u16_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37577             :   { Feature_isCIVI|Feature_isVI, 23916 /* v_qsad_pk_u16_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37578             :   { Feature_isSICI|Feature_isSICI, 23933 /* v_rcp_clamp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37579             :   { Feature_isSICI|Feature_isSICI, 23933 /* v_rcp_clamp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37580             :   { Feature_isSICI|Feature_isSICI, 23933 /* v_rcp_clamp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37581             :   { Feature_isSICI|Feature_isSICI, 23949 /* v_rcp_clamp_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37582             :   { Feature_isSICI|Feature_isSICI, 23949 /* v_rcp_clamp_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37583             :   { Feature_isSICI|Feature_isSICI, 23949 /* v_rcp_clamp_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37584             :   { Feature_Has16BitInsts|Feature_isVI, 23965 /* v_rcp_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   37585             :   { Feature_Has16BitInsts|Feature_isVI, 23965 /* v_rcp_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37586             :   { Feature_Has16BitInsts|Feature_isVI, 23965 /* v_rcp_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37587             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23965 /* v_rcp_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37588             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23965 /* v_rcp_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37589             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23965 /* v_rcp_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37590             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23965 /* v_rcp_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37591             :   { Feature_Has16BitInsts|Feature_HasSDWA, 23965 /* v_rcp_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37592             :   { Feature_HasDPP|Feature_HasDPP, 23965 /* v_rcp_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37593             :   { Feature_HasDPP|Feature_HasDPP, 23965 /* v_rcp_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37594             :   { Feature_HasDPP|Feature_HasDPP, 23965 /* v_rcp_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   37595             :   { Feature_HasDPP|Feature_HasDPP, 23965 /* v_rcp_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   37596             :   { Feature_HasDPP|Feature_HasDPP, 23965 /* v_rcp_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37597             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23965 /* v_rcp_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37598             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23965 /* v_rcp_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37599             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23965 /* v_rcp_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37600             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23965 /* v_rcp_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37601             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23965 /* v_rcp_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37602             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23965 /* v_rcp_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37603             :   { Feature_isGCN|Feature_isSICI, 23975 /* v_rcp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37604             :   { Feature_isGCN|Feature_isSICI, 23975 /* v_rcp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37605             :   { Feature_isGCN|Feature_isSICI, 23975 /* v_rcp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37606             :   { Feature_isGCN|Feature_isVI, 23975 /* v_rcp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37607             :   { Feature_isGCN|Feature_isVI, 23975 /* v_rcp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37608             :   { Feature_isGCN|Feature_isVI, 23975 /* v_rcp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37609             :   { Feature_HasSDWA|Feature_HasSDWA, 23975 /* v_rcp_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37610             :   { Feature_HasSDWA|Feature_HasSDWA, 23975 /* v_rcp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37611             :   { Feature_HasSDWA|Feature_HasSDWA, 23975 /* v_rcp_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37612             :   { Feature_HasSDWA|Feature_HasSDWA, 23975 /* v_rcp_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37613             :   { Feature_HasSDWA|Feature_HasSDWA, 23975 /* v_rcp_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37614             :   { Feature_HasDPP|Feature_HasDPP, 23975 /* v_rcp_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37615             :   { Feature_HasDPP|Feature_HasDPP, 23975 /* v_rcp_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37616             :   { Feature_HasDPP|Feature_HasDPP, 23975 /* v_rcp_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37617             :   { Feature_HasDPP|Feature_HasDPP, 23975 /* v_rcp_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37618             :   { Feature_HasDPP|Feature_HasDPP, 23975 /* v_rcp_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37619             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23975 /* v_rcp_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37620             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23975 /* v_rcp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37621             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23975 /* v_rcp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37622             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23975 /* v_rcp_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37623             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23975 /* v_rcp_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37624             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23975 /* v_rcp_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37625             :   { Feature_isGCN|Feature_isSICI, 23985 /* v_rcp_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37626             :   { Feature_isGCN|Feature_isSICI, 23985 /* v_rcp_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37627             :   { Feature_isGCN|Feature_isSICI, 23985 /* v_rcp_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37628             :   { Feature_isGCN|Feature_isVI, 23985 /* v_rcp_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37629             :   { Feature_isGCN|Feature_isVI, 23985 /* v_rcp_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37630             :   { Feature_isGCN|Feature_isVI, 23985 /* v_rcp_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37631             :   { Feature_isGCN|Feature_isSICI, 23995 /* v_rcp_iflag_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37632             :   { Feature_isGCN|Feature_isSICI, 23995 /* v_rcp_iflag_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37633             :   { Feature_isGCN|Feature_isSICI, 23995 /* v_rcp_iflag_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37634             :   { Feature_isGCN|Feature_isVI, 23995 /* v_rcp_iflag_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37635             :   { Feature_isGCN|Feature_isVI, 23995 /* v_rcp_iflag_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37636             :   { Feature_isGCN|Feature_isVI, 23995 /* v_rcp_iflag_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37637             :   { Feature_HasSDWA|Feature_HasSDWA, 23995 /* v_rcp_iflag_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37638             :   { Feature_HasSDWA|Feature_HasSDWA, 23995 /* v_rcp_iflag_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37639             :   { Feature_HasSDWA|Feature_HasSDWA, 23995 /* v_rcp_iflag_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37640             :   { Feature_HasSDWA|Feature_HasSDWA, 23995 /* v_rcp_iflag_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37641             :   { Feature_HasSDWA|Feature_HasSDWA, 23995 /* v_rcp_iflag_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37642             :   { Feature_HasDPP|Feature_HasDPP, 23995 /* v_rcp_iflag_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37643             :   { Feature_HasDPP|Feature_HasDPP, 23995 /* v_rcp_iflag_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37644             :   { Feature_HasDPP|Feature_HasDPP, 23995 /* v_rcp_iflag_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37645             :   { Feature_HasDPP|Feature_HasDPP, 23995 /* v_rcp_iflag_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37646             :   { Feature_HasDPP|Feature_HasDPP, 23995 /* v_rcp_iflag_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37647             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23995 /* v_rcp_iflag_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37648             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23995 /* v_rcp_iflag_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37649             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23995 /* v_rcp_iflag_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37650             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23995 /* v_rcp_iflag_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37651             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23995 /* v_rcp_iflag_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37652             :   { Feature_HasSDWA9|Feature_HasSDWA9, 23995 /* v_rcp_iflag_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37653             :   { Feature_isSICI|Feature_isSICI, 24011 /* v_rcp_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37654             :   { Feature_isSICI|Feature_isSICI, 24011 /* v_rcp_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37655             :   { Feature_isSICI|Feature_isSICI, 24011 /* v_rcp_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37656             :   { Feature_Has16BitInsts|Feature_isVI, 24063 /* v_rndne_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   37657             :   { Feature_Has16BitInsts|Feature_isVI, 24063 /* v_rndne_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37658             :   { Feature_Has16BitInsts|Feature_isVI, 24063 /* v_rndne_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37659             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24063 /* v_rndne_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37660             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24063 /* v_rndne_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37661             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24063 /* v_rndne_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37662             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24063 /* v_rndne_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37663             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24063 /* v_rndne_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37664             :   { Feature_HasDPP|Feature_HasDPP, 24063 /* v_rndne_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37665             :   { Feature_HasDPP|Feature_HasDPP, 24063 /* v_rndne_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37666             :   { Feature_HasDPP|Feature_HasDPP, 24063 /* v_rndne_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   37667             :   { Feature_HasDPP|Feature_HasDPP, 24063 /* v_rndne_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   37668             :   { Feature_HasDPP|Feature_HasDPP, 24063 /* v_rndne_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37669             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24063 /* v_rndne_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37670             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24063 /* v_rndne_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37671             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24063 /* v_rndne_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37672             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24063 /* v_rndne_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37673             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24063 /* v_rndne_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37674             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24063 /* v_rndne_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37675             :   { Feature_isGCN|Feature_isSICI, 24075 /* v_rndne_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37676             :   { Feature_isGCN|Feature_isSICI, 24075 /* v_rndne_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37677             :   { Feature_isGCN|Feature_isSICI, 24075 /* v_rndne_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37678             :   { Feature_isGCN|Feature_isVI, 24075 /* v_rndne_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37679             :   { Feature_isGCN|Feature_isVI, 24075 /* v_rndne_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37680             :   { Feature_isGCN|Feature_isVI, 24075 /* v_rndne_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37681             :   { Feature_HasSDWA|Feature_HasSDWA, 24075 /* v_rndne_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37682             :   { Feature_HasSDWA|Feature_HasSDWA, 24075 /* v_rndne_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37683             :   { Feature_HasSDWA|Feature_HasSDWA, 24075 /* v_rndne_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37684             :   { Feature_HasSDWA|Feature_HasSDWA, 24075 /* v_rndne_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37685             :   { Feature_HasSDWA|Feature_HasSDWA, 24075 /* v_rndne_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37686             :   { Feature_HasDPP|Feature_HasDPP, 24075 /* v_rndne_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37687             :   { Feature_HasDPP|Feature_HasDPP, 24075 /* v_rndne_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37688             :   { Feature_HasDPP|Feature_HasDPP, 24075 /* v_rndne_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37689             :   { Feature_HasDPP|Feature_HasDPP, 24075 /* v_rndne_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37690             :   { Feature_HasDPP|Feature_HasDPP, 24075 /* v_rndne_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37691             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24075 /* v_rndne_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37692             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24075 /* v_rndne_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37693             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24075 /* v_rndne_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37694             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24075 /* v_rndne_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37695             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24075 /* v_rndne_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37696             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24075 /* v_rndne_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37697             :   { Feature_isCIVI|Feature_isCIOnly, 24087 /* v_rndne_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37698             :   { Feature_isCIVI|Feature_isCIOnly, 24087 /* v_rndne_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37699             :   { Feature_isCIVI|Feature_isCIOnly, 24087 /* v_rndne_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37700             :   { Feature_isCIVI|Feature_isVI, 24087 /* v_rndne_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37701             :   { Feature_isCIVI|Feature_isVI, 24087 /* v_rndne_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37702             :   { Feature_isCIVI|Feature_isVI, 24087 /* v_rndne_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37703             :   { Feature_isSICI|Feature_isSICI, 24099 /* v_rsq_clamp_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37704             :   { Feature_isSICI|Feature_isSICI, 24099 /* v_rsq_clamp_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37705             :   { Feature_isSICI|Feature_isSICI, 24099 /* v_rsq_clamp_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37706             :   { Feature_isSICI|Feature_isSICI, 24115 /* v_rsq_clamp_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37707             :   { Feature_isSICI|Feature_isSICI, 24115 /* v_rsq_clamp_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37708             :   { Feature_isSICI|Feature_isSICI, 24115 /* v_rsq_clamp_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37709             :   { Feature_Has16BitInsts|Feature_isVI, 24131 /* v_rsq_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   37710             :   { Feature_Has16BitInsts|Feature_isVI, 24131 /* v_rsq_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37711             :   { Feature_Has16BitInsts|Feature_isVI, 24131 /* v_rsq_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37712             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24131 /* v_rsq_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37713             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24131 /* v_rsq_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37714             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24131 /* v_rsq_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37715             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24131 /* v_rsq_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37716             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24131 /* v_rsq_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37717             :   { Feature_HasDPP|Feature_HasDPP, 24131 /* v_rsq_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37718             :   { Feature_HasDPP|Feature_HasDPP, 24131 /* v_rsq_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37719             :   { Feature_HasDPP|Feature_HasDPP, 24131 /* v_rsq_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   37720             :   { Feature_HasDPP|Feature_HasDPP, 24131 /* v_rsq_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   37721             :   { Feature_HasDPP|Feature_HasDPP, 24131 /* v_rsq_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37722             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24131 /* v_rsq_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37723             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24131 /* v_rsq_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37724             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24131 /* v_rsq_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37725             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24131 /* v_rsq_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37726             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24131 /* v_rsq_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37727             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24131 /* v_rsq_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37728             :   { Feature_isGCN|Feature_isSICI, 24141 /* v_rsq_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37729             :   { Feature_isGCN|Feature_isSICI, 24141 /* v_rsq_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37730             :   { Feature_isGCN|Feature_isSICI, 24141 /* v_rsq_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37731             :   { Feature_isGCN|Feature_isVI, 24141 /* v_rsq_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37732             :   { Feature_isGCN|Feature_isVI, 24141 /* v_rsq_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37733             :   { Feature_isGCN|Feature_isVI, 24141 /* v_rsq_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37734             :   { Feature_HasSDWA|Feature_HasSDWA, 24141 /* v_rsq_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37735             :   { Feature_HasSDWA|Feature_HasSDWA, 24141 /* v_rsq_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37736             :   { Feature_HasSDWA|Feature_HasSDWA, 24141 /* v_rsq_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37737             :   { Feature_HasSDWA|Feature_HasSDWA, 24141 /* v_rsq_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37738             :   { Feature_HasSDWA|Feature_HasSDWA, 24141 /* v_rsq_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37739             :   { Feature_HasDPP|Feature_HasDPP, 24141 /* v_rsq_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37740             :   { Feature_HasDPP|Feature_HasDPP, 24141 /* v_rsq_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37741             :   { Feature_HasDPP|Feature_HasDPP, 24141 /* v_rsq_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37742             :   { Feature_HasDPP|Feature_HasDPP, 24141 /* v_rsq_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37743             :   { Feature_HasDPP|Feature_HasDPP, 24141 /* v_rsq_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37744             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24141 /* v_rsq_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37745             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24141 /* v_rsq_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37746             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24141 /* v_rsq_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37747             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24141 /* v_rsq_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37748             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24141 /* v_rsq_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37749             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24141 /* v_rsq_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37750             :   { Feature_isGCN|Feature_isSICI, 24151 /* v_rsq_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37751             :   { Feature_isGCN|Feature_isSICI, 24151 /* v_rsq_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37752             :   { Feature_isGCN|Feature_isSICI, 24151 /* v_rsq_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37753             :   { Feature_isGCN|Feature_isVI, 24151 /* v_rsq_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37754             :   { Feature_isGCN|Feature_isVI, 24151 /* v_rsq_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37755             :   { Feature_isGCN|Feature_isVI, 24151 /* v_rsq_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37756             :   { Feature_isSICI|Feature_isSICI, 24161 /* v_rsq_legacy_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37757             :   { Feature_isSICI|Feature_isSICI, 24161 /* v_rsq_legacy_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37758             :   { Feature_isSICI|Feature_isSICI, 24161 /* v_rsq_legacy_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37759             :   { Feature_isGCN|Feature_isSICI, 24178 /* v_sad_hi_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37760             :   { Feature_isGCN|Feature_isVI, 24178 /* v_sad_hi_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37761             :   { Feature_isGCN|Feature_isSICI, 24190 /* v_sad_u16 */, MCK_ImmClampSI, 16 /* 4 */ },
   37762             :   { Feature_isGCN|Feature_isVI, 24190 /* v_sad_u16 */, MCK_ImmClampSI, 16 /* 4 */ },
   37763             :   { Feature_isGCN|Feature_isSICI, 24200 /* v_sad_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37764             :   { Feature_isGCN|Feature_isVI, 24200 /* v_sad_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37765             :   { Feature_isGCN|Feature_isSICI, 24210 /* v_sad_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37766             :   { Feature_isGCN|Feature_isVI, 24210 /* v_sad_u8 */, MCK_ImmClampSI, 16 /* 4 */ },
   37767             :   { Feature_HasDPP|Feature_HasDPP, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37768             :   { Feature_HasDPP|Feature_HasDPP, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmRowMask, 8 /* 3 */ },
   37769             :   { Feature_HasDPP|Feature_HasDPP, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmBankMask, 16 /* 4 */ },
   37770             :   { Feature_HasDPP|Feature_HasDPP, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37771             :   { Feature_isGFX9|Feature_HasSDWA, 24219 /* v_sat_pk_u8_i16 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37772             :   { Feature_isGFX9|Feature_HasSDWA, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37773             :   { Feature_isGFX9|Feature_HasSDWA, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37774             :   { Feature_isGFX9|Feature_HasSDWA, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37775             :   { Feature_isGFX9|Feature_HasSDWA, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37776             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24219 /* v_sat_pk_u8_i16 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37777             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37778             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37779             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37780             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24219 /* v_sat_pk_u8_i16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37781             :   { Feature_HasDPP|Feature_HasDPP, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37782             :   { Feature_HasDPP|Feature_HasDPP, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37783             :   { Feature_HasDPP|Feature_HasDPP, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37784             :   { Feature_HasDPP|Feature_HasDPP, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37785             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24235 /* v_screen_partition_4se_b32 */, MCK_SDWAWithInt32InputMods, 2 /* 1 */ },
   37786             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37787             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37788             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37789             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24235 /* v_screen_partition_4se_b32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37790             :   { Feature_Has16BitInsts|Feature_isVI, 24262 /* v_sin_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   37791             :   { Feature_Has16BitInsts|Feature_isVI, 24262 /* v_sin_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37792             :   { Feature_Has16BitInsts|Feature_isVI, 24262 /* v_sin_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37793             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24262 /* v_sin_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37794             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24262 /* v_sin_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37795             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24262 /* v_sin_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37796             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24262 /* v_sin_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37797             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24262 /* v_sin_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37798             :   { Feature_HasDPP|Feature_HasDPP, 24262 /* v_sin_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37799             :   { Feature_HasDPP|Feature_HasDPP, 24262 /* v_sin_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37800             :   { Feature_HasDPP|Feature_HasDPP, 24262 /* v_sin_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   37801             :   { Feature_HasDPP|Feature_HasDPP, 24262 /* v_sin_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   37802             :   { Feature_HasDPP|Feature_HasDPP, 24262 /* v_sin_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37803             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24262 /* v_sin_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37804             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24262 /* v_sin_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37805             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24262 /* v_sin_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37806             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24262 /* v_sin_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37807             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24262 /* v_sin_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37808             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24262 /* v_sin_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37809             :   { Feature_isGCN|Feature_isSICI, 24272 /* v_sin_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37810             :   { Feature_isGCN|Feature_isSICI, 24272 /* v_sin_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37811             :   { Feature_isGCN|Feature_isSICI, 24272 /* v_sin_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37812             :   { Feature_isGCN|Feature_isVI, 24272 /* v_sin_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37813             :   { Feature_isGCN|Feature_isVI, 24272 /* v_sin_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37814             :   { Feature_isGCN|Feature_isVI, 24272 /* v_sin_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37815             :   { Feature_HasSDWA|Feature_HasSDWA, 24272 /* v_sin_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37816             :   { Feature_HasSDWA|Feature_HasSDWA, 24272 /* v_sin_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37817             :   { Feature_HasSDWA|Feature_HasSDWA, 24272 /* v_sin_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37818             :   { Feature_HasSDWA|Feature_HasSDWA, 24272 /* v_sin_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37819             :   { Feature_HasSDWA|Feature_HasSDWA, 24272 /* v_sin_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37820             :   { Feature_HasDPP|Feature_HasDPP, 24272 /* v_sin_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37821             :   { Feature_HasDPP|Feature_HasDPP, 24272 /* v_sin_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37822             :   { Feature_HasDPP|Feature_HasDPP, 24272 /* v_sin_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37823             :   { Feature_HasDPP|Feature_HasDPP, 24272 /* v_sin_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37824             :   { Feature_HasDPP|Feature_HasDPP, 24272 /* v_sin_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37825             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24272 /* v_sin_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37826             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24272 /* v_sin_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37827             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24272 /* v_sin_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37828             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24272 /* v_sin_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37829             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24272 /* v_sin_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37830             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24272 /* v_sin_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37831             :   { Feature_Has16BitInsts|Feature_isVI, 24282 /* v_sqrt_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   37832             :   { Feature_Has16BitInsts|Feature_isVI, 24282 /* v_sqrt_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37833             :   { Feature_Has16BitInsts|Feature_isVI, 24282 /* v_sqrt_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37834             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24282 /* v_sqrt_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37835             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24282 /* v_sqrt_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37836             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24282 /* v_sqrt_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37837             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24282 /* v_sqrt_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37838             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24282 /* v_sqrt_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37839             :   { Feature_HasDPP|Feature_HasDPP, 24282 /* v_sqrt_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37840             :   { Feature_HasDPP|Feature_HasDPP, 24282 /* v_sqrt_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37841             :   { Feature_HasDPP|Feature_HasDPP, 24282 /* v_sqrt_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   37842             :   { Feature_HasDPP|Feature_HasDPP, 24282 /* v_sqrt_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   37843             :   { Feature_HasDPP|Feature_HasDPP, 24282 /* v_sqrt_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37844             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24282 /* v_sqrt_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   37845             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24282 /* v_sqrt_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   37846             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24282 /* v_sqrt_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   37847             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24282 /* v_sqrt_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37848             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24282 /* v_sqrt_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37849             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24282 /* v_sqrt_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37850             :   { Feature_isGCN|Feature_isSICI, 24293 /* v_sqrt_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37851             :   { Feature_isGCN|Feature_isSICI, 24293 /* v_sqrt_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37852             :   { Feature_isGCN|Feature_isSICI, 24293 /* v_sqrt_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37853             :   { Feature_isGCN|Feature_isVI, 24293 /* v_sqrt_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   37854             :   { Feature_isGCN|Feature_isVI, 24293 /* v_sqrt_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37855             :   { Feature_isGCN|Feature_isVI, 24293 /* v_sqrt_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37856             :   { Feature_HasSDWA|Feature_HasSDWA, 24293 /* v_sqrt_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37857             :   { Feature_HasSDWA|Feature_HasSDWA, 24293 /* v_sqrt_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37858             :   { Feature_HasSDWA|Feature_HasSDWA, 24293 /* v_sqrt_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   37859             :   { Feature_HasSDWA|Feature_HasSDWA, 24293 /* v_sqrt_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   37860             :   { Feature_HasSDWA|Feature_HasSDWA, 24293 /* v_sqrt_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   37861             :   { Feature_HasDPP|Feature_HasDPP, 24293 /* v_sqrt_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   37862             :   { Feature_HasDPP|Feature_HasDPP, 24293 /* v_sqrt_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   37863             :   { Feature_HasDPP|Feature_HasDPP, 24293 /* v_sqrt_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   37864             :   { Feature_HasDPP|Feature_HasDPP, 24293 /* v_sqrt_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   37865             :   { Feature_HasDPP|Feature_HasDPP, 24293 /* v_sqrt_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   37866             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24293 /* v_sqrt_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   37867             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24293 /* v_sqrt_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   37868             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24293 /* v_sqrt_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   37869             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24293 /* v_sqrt_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37870             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24293 /* v_sqrt_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37871             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24293 /* v_sqrt_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37872             :   { Feature_isGCN|Feature_isSICI, 24304 /* v_sqrt_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37873             :   { Feature_isGCN|Feature_isSICI, 24304 /* v_sqrt_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37874             :   { Feature_isGCN|Feature_isSICI, 24304 /* v_sqrt_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37875             :   { Feature_isGCN|Feature_isVI, 24304 /* v_sqrt_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   37876             :   { Feature_isGCN|Feature_isVI, 24304 /* v_sqrt_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   37877             :   { Feature_isGCN|Feature_isVI, 24304 /* v_sqrt_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   37878             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmDPPCtrl, 16 /* 4 */ },
   37879             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmRowMask, 32 /* 5 */ },
   37880             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmBankMask, 64 /* 6 */ },
   37881             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmBoundCtrl, 128 /* 7 */ },
   37882             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   37883             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37884             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37885             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37886             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37887             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24315 /* v_sub_co_u32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37888             :   { Feature_Has16BitInsts|Feature_isVI, 24328 /* v_sub_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   37889             :   { Feature_Has16BitInsts|Feature_isVI, 24328 /* v_sub_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   37890             :   { Feature_Has16BitInsts|Feature_isVI, 24328 /* v_sub_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37891             :   { Feature_HasDPP|Feature_HasDPP, 24328 /* v_sub_f16 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37892             :   { Feature_HasDPP|Feature_HasDPP, 24328 /* v_sub_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37893             :   { Feature_HasDPP|Feature_HasDPP, 24328 /* v_sub_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37894             :   { Feature_HasDPP|Feature_HasDPP, 24328 /* v_sub_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37895             :   { Feature_HasDPP|Feature_HasDPP, 24328 /* v_sub_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37896             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24328 /* v_sub_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   37897             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24328 /* v_sub_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37898             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24328 /* v_sub_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37899             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24328 /* v_sub_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37900             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24328 /* v_sub_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37901             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24328 /* v_sub_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37902             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24328 /* v_sub_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   37903             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24328 /* v_sub_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   37904             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24328 /* v_sub_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37905             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24328 /* v_sub_f16 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37906             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24328 /* v_sub_f16 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37907             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24328 /* v_sub_f16 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37908             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24328 /* v_sub_f16 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37909             :   { Feature_isGCN|Feature_isSICI, 24338 /* v_sub_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37910             :   { Feature_isGCN|Feature_isSICI, 24338 /* v_sub_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37911             :   { Feature_isGCN|Feature_isSICI, 24338 /* v_sub_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37912             :   { Feature_isGCN|Feature_isVI, 24338 /* v_sub_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   37913             :   { Feature_isGCN|Feature_isVI, 24338 /* v_sub_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37914             :   { Feature_isGCN|Feature_isVI, 24338 /* v_sub_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37915             :   { Feature_HasDPP|Feature_HasDPP, 24338 /* v_sub_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   37916             :   { Feature_HasDPP|Feature_HasDPP, 24338 /* v_sub_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37917             :   { Feature_HasDPP|Feature_HasDPP, 24338 /* v_sub_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37918             :   { Feature_HasDPP|Feature_HasDPP, 24338 /* v_sub_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37919             :   { Feature_HasDPP|Feature_HasDPP, 24338 /* v_sub_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37920             :   { Feature_isGCN|Feature_HasSDWA, 24338 /* v_sub_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37921             :   { Feature_isGCN|Feature_HasSDWA, 24338 /* v_sub_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37922             :   { Feature_isGCN|Feature_HasSDWA, 24338 /* v_sub_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37923             :   { Feature_isGCN|Feature_HasSDWA, 24338 /* v_sub_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37924             :   { Feature_isGCN|Feature_HasSDWA, 24338 /* v_sub_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37925             :   { Feature_isGCN|Feature_HasSDWA, 24338 /* v_sub_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37926             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24338 /* v_sub_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   37927             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24338 /* v_sub_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   37928             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24338 /* v_sub_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37929             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24338 /* v_sub_f32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37930             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24338 /* v_sub_f32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37931             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24338 /* v_sub_f32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37932             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24338 /* v_sub_f32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37933             :   { Feature_isGFX9|Feature_isVI, 24348 /* v_sub_i16 */, MCK_ImmClampSI, 16 /* 4 */ },
   37934             :   { Feature_isGFX9|Feature_isVI, 24348 /* v_sub_i16 */, MCK_ImmOpSel, 8 /* 3 */ },
   37935             :   { Feature_HasDPP|Feature_HasDPP, 24368 /* v_sub_u16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37936             :   { Feature_HasDPP|Feature_HasDPP, 24368 /* v_sub_u16 */, MCK_ImmRowMask, 16 /* 4 */ },
   37937             :   { Feature_HasDPP|Feature_HasDPP, 24368 /* v_sub_u16 */, MCK_ImmBankMask, 32 /* 5 */ },
   37938             :   { Feature_HasDPP|Feature_HasDPP, 24368 /* v_sub_u16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37939             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24368 /* v_sub_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37940             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24368 /* v_sub_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37941             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24368 /* v_sub_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37942             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24368 /* v_sub_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37943             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24368 /* v_sub_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37944             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24368 /* v_sub_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37945             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24368 /* v_sub_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   37946             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24368 /* v_sub_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   37947             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24368 /* v_sub_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37948             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24368 /* v_sub_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37949             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24368 /* v_sub_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37950             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24368 /* v_sub_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37951             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   37952             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmRowMask, 16 /* 4 */ },
   37953             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmBankMask, 32 /* 5 */ },
   37954             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   37955             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmDPPCtrl, 16 /* 4 */ },
   37956             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmRowMask, 32 /* 5 */ },
   37957             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmBankMask, 64 /* 6 */ },
   37958             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmBoundCtrl, 128 /* 7 */ },
   37959             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   37960             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   37961             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   37962             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   37963             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   37964             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24378 /* v_sub_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   37965             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   37966             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   37967             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   37968             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   37969             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   37970             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24378 /* v_sub_u32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   37971             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmDPPCtrl, 32 /* 5 */ },
   37972             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmRowMask, 64 /* 6 */ },
   37973             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmBankMask, 128 /* 7 */ },
   37974             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmBoundCtrl, 256 /* 8 */ },
   37975             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   37976             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   37977             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmSDWADstSel, 64 /* 6 */ },
   37978             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmSDWASrc0Sel, 256 /* 8 */ },
   37979             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmSDWASrc1Sel, 512 /* 9 */ },
   37980             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24388 /* v_subb_co_u32 */, MCK_ImmSDWADstUnused, 128 /* 7 */ },
   37981             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmDPPCtrl, 32 /* 5 */ },
   37982             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmRowMask, 64 /* 6 */ },
   37983             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmBankMask, 128 /* 7 */ },
   37984             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmBoundCtrl, 256 /* 8 */ },
   37985             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   37986             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   37987             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmSDWADstSel, 64 /* 6 */ },
   37988             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmSDWASrc0Sel, 256 /* 8 */ },
   37989             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmSDWASrc1Sel, 512 /* 9 */ },
   37990             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24402 /* v_subb_u32 */, MCK_ImmSDWADstUnused, 128 /* 7 */ },
   37991             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmDPPCtrl, 32 /* 5 */ },
   37992             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmRowMask, 64 /* 6 */ },
   37993             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmBankMask, 128 /* 7 */ },
   37994             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmBoundCtrl, 256 /* 8 */ },
   37995             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   37996             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   37997             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmSDWADstSel, 64 /* 6 */ },
   37998             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmSDWASrc0Sel, 256 /* 8 */ },
   37999             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmSDWASrc1Sel, 512 /* 9 */ },
   38000             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24413 /* v_subbrev_co_u32 */, MCK_ImmSDWADstUnused, 128 /* 7 */ },
   38001             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmDPPCtrl, 32 /* 5 */ },
   38002             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmRowMask, 64 /* 6 */ },
   38003             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmBankMask, 128 /* 7 */ },
   38004             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmBoundCtrl, 256 /* 8 */ },
   38005             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   38006             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmClampSI, 32 /* 5 */ },
   38007             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmSDWADstSel, 64 /* 6 */ },
   38008             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmSDWASrc0Sel, 256 /* 8 */ },
   38009             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmSDWASrc1Sel, 512 /* 9 */ },
   38010             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24430 /* v_subbrev_u32 */, MCK_ImmSDWADstUnused, 128 /* 7 */ },
   38011             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmDPPCtrl, 16 /* 4 */ },
   38012             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmRowMask, 32 /* 5 */ },
   38013             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmBankMask, 64 /* 6 */ },
   38014             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmBoundCtrl, 128 /* 7 */ },
   38015             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   38016             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   38017             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   38018             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   38019             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   38020             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24444 /* v_subrev_co_u32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   38021             :   { Feature_Has16BitInsts|Feature_isVI, 24460 /* v_subrev_f16 */, MCK_RegOrImmWithFP16InputMods, 6 /* 1, 2 */ },
   38022             :   { Feature_Has16BitInsts|Feature_isVI, 24460 /* v_subrev_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   38023             :   { Feature_Has16BitInsts|Feature_isVI, 24460 /* v_subrev_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   38024             :   { Feature_HasDPP|Feature_HasDPP, 24460 /* v_subrev_f16 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   38025             :   { Feature_HasDPP|Feature_HasDPP, 24460 /* v_subrev_f16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   38026             :   { Feature_HasDPP|Feature_HasDPP, 24460 /* v_subrev_f16 */, MCK_ImmRowMask, 16 /* 4 */ },
   38027             :   { Feature_HasDPP|Feature_HasDPP, 24460 /* v_subrev_f16 */, MCK_ImmBankMask, 32 /* 5 */ },
   38028             :   { Feature_HasDPP|Feature_HasDPP, 24460 /* v_subrev_f16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   38029             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24460 /* v_subrev_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   38030             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24460 /* v_subrev_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   38031             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24460 /* v_subrev_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38032             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24460 /* v_subrev_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38033             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24460 /* v_subrev_f16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38034             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24460 /* v_subrev_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38035             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24460 /* v_subrev_f16 */, MCK_SDWAWithFP16InputMods, 6 /* 1, 2 */ },
   38036             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24460 /* v_subrev_f16 */, MCK_ImmOModSI, 16 /* 4 */ },
   38037             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24460 /* v_subrev_f16 */, MCK_ImmClampSI, 8 /* 3 */ },
   38038             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24460 /* v_subrev_f16 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   38039             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24460 /* v_subrev_f16 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   38040             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24460 /* v_subrev_f16 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   38041             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24460 /* v_subrev_f16 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   38042             :   { Feature_isGCN|Feature_isSICI, 24473 /* v_subrev_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   38043             :   { Feature_isGCN|Feature_isSICI, 24473 /* v_subrev_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   38044             :   { Feature_isGCN|Feature_isSICI, 24473 /* v_subrev_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38045             :   { Feature_isGCN|Feature_isVI, 24473 /* v_subrev_f32 */, MCK_RegOrImmWithFP32InputMods, 6 /* 1, 2 */ },
   38046             :   { Feature_isGCN|Feature_isVI, 24473 /* v_subrev_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   38047             :   { Feature_isGCN|Feature_isVI, 24473 /* v_subrev_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38048             :   { Feature_HasDPP|Feature_HasDPP, 24473 /* v_subrev_f32 */, MCK_VRegWithFPInputMods, 6 /* 1, 2 */ },
   38049             :   { Feature_HasDPP|Feature_HasDPP, 24473 /* v_subrev_f32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   38050             :   { Feature_HasDPP|Feature_HasDPP, 24473 /* v_subrev_f32 */, MCK_ImmRowMask, 16 /* 4 */ },
   38051             :   { Feature_HasDPP|Feature_HasDPP, 24473 /* v_subrev_f32 */, MCK_ImmBankMask, 32 /* 5 */ },
   38052             :   { Feature_HasDPP|Feature_HasDPP, 24473 /* v_subrev_f32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   38053             :   { Feature_isGCN|Feature_HasSDWA, 24473 /* v_subrev_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   38054             :   { Feature_isGCN|Feature_HasSDWA, 24473 /* v_subrev_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38055             :   { Feature_isGCN|Feature_HasSDWA, 24473 /* v_subrev_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38056             :   { Feature_isGCN|Feature_HasSDWA, 24473 /* v_subrev_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38057             :   { Feature_isGCN|Feature_HasSDWA, 24473 /* v_subrev_f32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38058             :   { Feature_isGCN|Feature_HasSDWA, 24473 /* v_subrev_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38059             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24473 /* v_subrev_f32 */, MCK_SDWAWithFP32InputMods, 6 /* 1, 2 */ },
   38060             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24473 /* v_subrev_f32 */, MCK_ImmOModSI, 16 /* 4 */ },
   38061             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24473 /* v_subrev_f32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38062             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24473 /* v_subrev_f32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   38063             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24473 /* v_subrev_f32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   38064             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24473 /* v_subrev_f32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   38065             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24473 /* v_subrev_f32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   38066             :   { Feature_HasDPP|Feature_HasDPP, 24499 /* v_subrev_u16 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   38067             :   { Feature_HasDPP|Feature_HasDPP, 24499 /* v_subrev_u16 */, MCK_ImmRowMask, 16 /* 4 */ },
   38068             :   { Feature_HasDPP|Feature_HasDPP, 24499 /* v_subrev_u16 */, MCK_ImmBankMask, 32 /* 5 */ },
   38069             :   { Feature_HasDPP|Feature_HasDPP, 24499 /* v_subrev_u16 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   38070             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24499 /* v_subrev_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   38071             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24499 /* v_subrev_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   38072             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24499 /* v_subrev_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38073             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24499 /* v_subrev_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38074             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24499 /* v_subrev_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38075             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24499 /* v_subrev_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38076             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24499 /* v_subrev_u16 */, MCK_SDWAWithInt16InputMods, 6 /* 1, 2 */ },
   38077             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24499 /* v_subrev_u16 */, MCK_ImmClampSI, 8 /* 3 */ },
   38078             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24499 /* v_subrev_u16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38079             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24499 /* v_subrev_u16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38080             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24499 /* v_subrev_u16 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38081             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24499 /* v_subrev_u16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38082             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   38083             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmRowMask, 16 /* 4 */ },
   38084             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmBankMask, 32 /* 5 */ },
   38085             :   { Feature_HasDPP|Feature_HasDPP|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   38086             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmDPPCtrl, 16 /* 4 */ },
   38087             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmRowMask, 32 /* 5 */ },
   38088             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmBankMask, 64 /* 6 */ },
   38089             :   { Feature_HasDPP|Feature_HasDPP|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmBoundCtrl, 128 /* 7 */ },
   38090             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   38091             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38092             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38093             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38094             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38095             :   { Feature_HasSDWA9|Feature_HasSDWA9|Feature_isGFX9, 24512 /* v_subrev_u32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38096             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_SDWAWithInt32InputMods, 12 /* 2, 3 */ },
   38097             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmClampSI, 16 /* 4 */ },
   38098             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmSDWADstSel, 32 /* 5 */ },
   38099             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmSDWASrc0Sel, 128 /* 7 */ },
   38100             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmSDWASrc1Sel, 256 /* 8 */ },
   38101             :   { Feature_isGCN|Feature_HasSDWA|Feature_isVIOnly, 24512 /* v_subrev_u32 */, MCK_ImmSDWADstUnused, 64 /* 6 */ },
   38102             :   { Feature_isGCN|Feature_isSICI, 24536 /* v_trig_preop_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   38103             :   { Feature_isGCN|Feature_isSICI, 24536 /* v_trig_preop_f64 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   38104             :   { Feature_isGCN|Feature_isSICI, 24536 /* v_trig_preop_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   38105             :   { Feature_isGCN|Feature_isSICI, 24536 /* v_trig_preop_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   38106             :   { Feature_isGCN|Feature_isVI, 24536 /* v_trig_preop_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   38107             :   { Feature_isGCN|Feature_isVI, 24536 /* v_trig_preop_f64 */, MCK_RegOrImmWithInt32InputMods, 4 /* 2 */ },
   38108             :   { Feature_isGCN|Feature_isVI, 24536 /* v_trig_preop_f64 */, MCK_ImmOModSI, 16 /* 4 */ },
   38109             :   { Feature_isGCN|Feature_isVI, 24536 /* v_trig_preop_f64 */, MCK_ImmClampSI, 8 /* 3 */ },
   38110             :   { Feature_Has16BitInsts|Feature_isVI, 24553 /* v_trunc_f16 */, MCK_RegOrImmWithFP16InputMods, 2 /* 1 */ },
   38111             :   { Feature_Has16BitInsts|Feature_isVI, 24553 /* v_trunc_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   38112             :   { Feature_Has16BitInsts|Feature_isVI, 24553 /* v_trunc_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   38113             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24553 /* v_trunc_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   38114             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24553 /* v_trunc_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   38115             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24553 /* v_trunc_f16 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   38116             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24553 /* v_trunc_f16 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   38117             :   { Feature_Has16BitInsts|Feature_HasSDWA, 24553 /* v_trunc_f16 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   38118             :   { Feature_HasDPP|Feature_HasDPP, 24553 /* v_trunc_f16 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   38119             :   { Feature_HasDPP|Feature_HasDPP, 24553 /* v_trunc_f16 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   38120             :   { Feature_HasDPP|Feature_HasDPP, 24553 /* v_trunc_f16 */, MCK_ImmRowMask, 8 /* 3 */ },
   38121             :   { Feature_HasDPP|Feature_HasDPP, 24553 /* v_trunc_f16 */, MCK_ImmBankMask, 16 /* 4 */ },
   38122             :   { Feature_HasDPP|Feature_HasDPP, 24553 /* v_trunc_f16 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   38123             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24553 /* v_trunc_f16 */, MCK_SDWAWithFP16InputMods, 2 /* 1 */ },
   38124             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24553 /* v_trunc_f16 */, MCK_ImmOModSI, 8 /* 3 */ },
   38125             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24553 /* v_trunc_f16 */, MCK_ImmClampSI, 4 /* 2 */ },
   38126             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24553 /* v_trunc_f16 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38127             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24553 /* v_trunc_f16 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38128             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24553 /* v_trunc_f16 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38129             :   { Feature_isGCN|Feature_isSICI, 24565 /* v_trunc_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   38130             :   { Feature_isGCN|Feature_isSICI, 24565 /* v_trunc_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   38131             :   { Feature_isGCN|Feature_isSICI, 24565 /* v_trunc_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   38132             :   { Feature_isGCN|Feature_isVI, 24565 /* v_trunc_f32 */, MCK_RegOrImmWithFP32InputMods, 2 /* 1 */ },
   38133             :   { Feature_isGCN|Feature_isVI, 24565 /* v_trunc_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   38134             :   { Feature_isGCN|Feature_isVI, 24565 /* v_trunc_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   38135             :   { Feature_HasSDWA|Feature_HasSDWA, 24565 /* v_trunc_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   38136             :   { Feature_HasSDWA|Feature_HasSDWA, 24565 /* v_trunc_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   38137             :   { Feature_HasSDWA|Feature_HasSDWA, 24565 /* v_trunc_f32 */, MCK_ImmSDWADstSel, 8 /* 3 */ },
   38138             :   { Feature_HasSDWA|Feature_HasSDWA, 24565 /* v_trunc_f32 */, MCK_ImmSDWASrc0Sel, 32 /* 5 */ },
   38139             :   { Feature_HasSDWA|Feature_HasSDWA, 24565 /* v_trunc_f32 */, MCK_ImmSDWADstUnused, 16 /* 4 */ },
   38140             :   { Feature_HasDPP|Feature_HasDPP, 24565 /* v_trunc_f32 */, MCK_VRegWithFPInputMods, 2 /* 1 */ },
   38141             :   { Feature_HasDPP|Feature_HasDPP, 24565 /* v_trunc_f32 */, MCK_ImmDPPCtrl, 4 /* 2 */ },
   38142             :   { Feature_HasDPP|Feature_HasDPP, 24565 /* v_trunc_f32 */, MCK_ImmRowMask, 8 /* 3 */ },
   38143             :   { Feature_HasDPP|Feature_HasDPP, 24565 /* v_trunc_f32 */, MCK_ImmBankMask, 16 /* 4 */ },
   38144             :   { Feature_HasDPP|Feature_HasDPP, 24565 /* v_trunc_f32 */, MCK_ImmBoundCtrl, 32 /* 5 */ },
   38145             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24565 /* v_trunc_f32 */, MCK_SDWAWithFP32InputMods, 2 /* 1 */ },
   38146             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24565 /* v_trunc_f32 */, MCK_ImmOModSI, 8 /* 3 */ },
   38147             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24565 /* v_trunc_f32 */, MCK_ImmClampSI, 4 /* 2 */ },
   38148             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24565 /* v_trunc_f32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38149             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24565 /* v_trunc_f32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38150             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24565 /* v_trunc_f32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38151             :   { Feature_isCIVI|Feature_isCIOnly, 24577 /* v_trunc_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   38152             :   { Feature_isCIVI|Feature_isCIOnly, 24577 /* v_trunc_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   38153             :   { Feature_isCIVI|Feature_isCIOnly, 24577 /* v_trunc_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   38154             :   { Feature_isCIVI|Feature_isVI, 24577 /* v_trunc_f64 */, MCK_RegOrImmWithFP64InputMods, 2 /* 1 */ },
   38155             :   { Feature_isCIVI|Feature_isVI, 24577 /* v_trunc_f64 */, MCK_ImmOModSI, 8 /* 3 */ },
   38156             :   { Feature_isCIVI|Feature_isVI, 24577 /* v_trunc_f64 */, MCK_ImmClampSI, 4 /* 2 */ },
   38157             :   { Feature_HasDLInsts|Feature_HasDPP, 24615 /* v_xnor_b32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   38158             :   { Feature_HasDLInsts|Feature_HasDPP, 24615 /* v_xnor_b32 */, MCK_ImmRowMask, 16 /* 4 */ },
   38159             :   { Feature_HasDLInsts|Feature_HasDPP, 24615 /* v_xnor_b32 */, MCK_ImmBankMask, 32 /* 5 */ },
   38160             :   { Feature_HasDLInsts|Feature_HasDPP, 24615 /* v_xnor_b32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   38161             :   { Feature_HasDLInsts|Feature_HasSDWA, 24615 /* v_xnor_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   38162             :   { Feature_HasDLInsts|Feature_HasSDWA, 24615 /* v_xnor_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38163             :   { Feature_HasDLInsts|Feature_HasSDWA, 24615 /* v_xnor_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38164             :   { Feature_HasDLInsts|Feature_HasSDWA, 24615 /* v_xnor_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38165             :   { Feature_HasDLInsts|Feature_HasSDWA, 24615 /* v_xnor_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38166             :   { Feature_HasDLInsts|Feature_HasSDWA, 24615 /* v_xnor_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38167             :   { Feature_HasDLInsts|Feature_HasSDWA9, 24615 /* v_xnor_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   38168             :   { Feature_HasDLInsts|Feature_HasSDWA9, 24615 /* v_xnor_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38169             :   { Feature_HasDLInsts|Feature_HasSDWA9, 24615 /* v_xnor_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38170             :   { Feature_HasDLInsts|Feature_HasSDWA9, 24615 /* v_xnor_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38171             :   { Feature_HasDLInsts|Feature_HasSDWA9, 24615 /* v_xnor_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38172             :   { Feature_HasDLInsts|Feature_HasSDWA9, 24615 /* v_xnor_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38173             :   { Feature_HasDPP|Feature_HasDPP, 24626 /* v_xor_b32 */, MCK_ImmDPPCtrl, 8 /* 3 */ },
   38174             :   { Feature_HasDPP|Feature_HasDPP, 24626 /* v_xor_b32 */, MCK_ImmRowMask, 16 /* 4 */ },
   38175             :   { Feature_HasDPP|Feature_HasDPP, 24626 /* v_xor_b32 */, MCK_ImmBankMask, 32 /* 5 */ },
   38176             :   { Feature_HasDPP|Feature_HasDPP, 24626 /* v_xor_b32 */, MCK_ImmBoundCtrl, 64 /* 6 */ },
   38177             :   { Feature_isGCN|Feature_HasSDWA, 24626 /* v_xor_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   38178             :   { Feature_isGCN|Feature_HasSDWA, 24626 /* v_xor_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38179             :   { Feature_isGCN|Feature_HasSDWA, 24626 /* v_xor_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38180             :   { Feature_isGCN|Feature_HasSDWA, 24626 /* v_xor_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38181             :   { Feature_isGCN|Feature_HasSDWA, 24626 /* v_xor_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38182             :   { Feature_isGCN|Feature_HasSDWA, 24626 /* v_xor_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38183             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24626 /* v_xor_b32 */, MCK_SDWAWithInt32InputMods, 6 /* 1, 2 */ },
   38184             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24626 /* v_xor_b32 */, MCK_ImmClampSI, 8 /* 3 */ },
   38185             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24626 /* v_xor_b32 */, MCK_ImmSDWADstSel, 16 /* 4 */ },
   38186             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24626 /* v_xor_b32 */, MCK_ImmSDWASrc0Sel, 64 /* 6 */ },
   38187             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24626 /* v_xor_b32 */, MCK_ImmSDWASrc1Sel, 128 /* 7 */ },
   38188             :   { Feature_HasSDWA9|Feature_HasSDWA9, 24626 /* v_xor_b32 */, MCK_ImmSDWADstUnused, 32 /* 5 */ },
   38189             : };
   38190             : 
   38191      276261 : OperandMatchResultTy AMDGPUAsmParser::
   38192             : tryCustomParseOperand(OperandVector &Operands,
   38193             :                       unsigned MCK) {
   38194             : 
   38195      276261 :   switch(MCK) {
   38196         728 :   case MCK_Attr:
   38197         728 :     return parseInterpAttr(Operands);
   38198           0 :   case MCK_ExpTgt:
   38199           0 :     return parseExpTgt(Operands);
   38200       36113 :   case MCK_RegOrImmWithFP16InputMods:
   38201       36113 :     return parseRegOrImmWithFPInputMods(Operands);
   38202           1 :   case MCK_SDWAWithFP16InputMods:
   38203           1 :     return parseRegOrImmWithFPInputMods(Operands);
   38204       58762 :   case MCK_RegOrImmWithFP32InputMods:
   38205       58762 :     return parseRegOrImmWithFPInputMods(Operands);
   38206           7 :   case MCK_SDWAWithFP32InputMods:
   38207           7 :     return parseRegOrImmWithFPInputMods(Operands);
   38208       23196 :   case MCK_RegOrImmWithFP64InputMods:
   38209       23196 :     return parseRegOrImmWithFPInputMods(Operands);
   38210             :   case MCK_VRegWithFPInputMods:
   38211          25 :     return parseRegWithFPInputMods(Operands);
   38212       25776 :   case MCK_SDWAWithInt16InputMods:
   38213       25776 :     return parseRegOrImmWithIntInputMods(Operands);
   38214        1485 :   case MCK_RegOrImmWithInt32InputMods:
   38215        1485 :     return parseRegOrImmWithIntInputMods(Operands);
   38216       39384 :   case MCK_SDWAWithInt32InputMods:
   38217       39384 :     return parseRegOrImmWithIntInputMods(Operands);
   38218           0 :   case MCK_RegOrImmWithInt64InputMods:
   38219           0 :     return parseRegOrImmWithIntInputMods(Operands);
   38220           0 :   case MCK_OpSelMods:
   38221           0 :     return parseRegOrImm(Operands);
   38222             :   case MCK_VRegWithIntInputMods:
   38223           0 :     return parseRegWithIntInputMods(Operands);
   38224         176 :   case MCK_InterpSlot:
   38225         176 :     return parseInterpSlot(Operands);
   38226          62 :   case MCK_KImmFP16:
   38227          62 :     return parseImm(Operands);
   38228         102 :   case MCK_KImmFP32:
   38229         102 :     return parseImm(Operands);
   38230           0 :   case MCK_PackedFP16InputMods:
   38231           0 :     return parseRegOrImm(Operands);
   38232           0 :   case MCK_PackedInt16InputMods:
   38233           0 :     return parseRegOrImm(Operands);
   38234         126 :   case MCK_SWaitCnt:
   38235         126 :     return parseSWaitCntOps(Operands);
   38236         160 :   case MCK_SendMsg:
   38237         160 :     return parseSendMsgOp(Operands);
   38238         130 :   case MCK_SoppBrTarget:
   38239         130 :     return parseSOppBrTarget(Operands);
   38240         320 :   case MCK_Swizzle:
   38241         320 :     return parseSwizzleOp(Operands);
   38242         920 :   case MCK_VReg32OrOff:
   38243         920 :     return parseVReg32OrOff(Operands);
   38244           0 :   case MCK_ImmOffen:
   38245           0 :     return parseOptionalOperand(Operands);
   38246           0 :   case MCK_ImmIdxen:
   38247           0 :     return parseOptionalOperand(Operands);
   38248           0 :   case MCK_ImmAddr64:
   38249           0 :     return parseOptionalOperand(Operands);
   38250        1067 :   case MCK_ImmOffsetU12:
   38251        1067 :     return parseOptionalOperand(Operands);
   38252         860 :   case MCK_ImmOffsetS13:
   38253         860 :     return parseOptionalOperand(Operands);
   38254        7885 :   case MCK_ImmOffset:
   38255        7885 :     return parseOptionalOperand(Operands);
   38256         606 :   case MCK_ImmOffset0:
   38257         606 :     return parseOptionalOperand(Operands);
   38258           0 :   case MCK_ImmOffset1:
   38259           0 :     return parseOptionalOperand(Operands);
   38260           4 :   case MCK_ImmGDS:
   38261           4 :     return parseOptionalOperand(Operands);
   38262        5731 :   case MCK_ImmOModSI:
   38263        5731 :     return parseOptionalOperand(Operands);
   38264       29268 :   case MCK_ImmClampSI:
   38265       29268 :     return parseOptionalOperand(Operands);
   38266          68 :   case MCK_ImmHigh:
   38267          68 :     return parseOptionalOperand(Operands);
   38268          99 :   case MCK_ImmGLC:
   38269          99 :     return parseOptionalOperand(Operands);
   38270         585 :   case MCK_ImmSLC:
   38271         585 :     return parseOptionalOperand(Operands);
   38272           0 :   case MCK_ImmTFE:
   38273           0 :     return parseOptionalOperand(Operands);
   38274           0 :   case MCK_ImmUNorm:
   38275           0 :     return parseOptionalOperand(Operands);
   38276           0 :   case MCK_ImmDA:
   38277           0 :     return parseOptionalOperand(Operands);
   38278           0 :   case MCK_ImmR128A16:
   38279           0 :     return parseOptionalOperand(Operands);
   38280           0 :   case MCK_ImmD16:
   38281           0 :     return parseOptionalOperand(Operands);
   38282           0 :   case MCK_ImmLWE:
   38283           0 :     return parseOptionalOperand(Operands);
   38284          58 :   case MCK_ImmExpCompr:
   38285          58 :     return parseOptionalOperand(Operands);
   38286           2 :   case MCK_ImmExpVM:
   38287           2 :     return parseOptionalOperand(Operands);
   38288         346 :   case MCK_ImmFORMAT:
   38289         346 :     return parseOptionalOperand(Operands);
   38290        4273 :   case MCK_ImmDMask:
   38291        4273 :     return parseOptionalOperand(Operands);
   38292       14403 :   case MCK_ImmDPPCtrl:
   38293       14403 :     return parseDPPCtrl(Operands);
   38294        3677 :   case MCK_ImmRowMask:
   38295        3677 :     return parseOptionalOperand(Operands);
   38296        7756 :   case MCK_ImmBankMask:
   38297        7756 :     return parseOptionalOperand(Operands);
   38298         664 :   case MCK_ImmBoundCtrl:
   38299         664 :     return parseOptionalOperand(Operands);
   38300         802 :   case MCK_ImmSDWADstSel:
   38301         802 :     return parseOptionalOperand(Operands);
   38302        5089 :   case MCK_ImmSDWASrc0Sel:
   38303        5089 :     return parseOptionalOperand(Operands);
   38304          10 :   case MCK_ImmSDWASrc1Sel:
   38305          10 :     return parseOptionalOperand(Operands);
   38306        1653 :   case MCK_ImmSDWADstUnused:
   38307        1653 :     return parseOptionalOperand(Operands);
   38308        1160 :   case MCK_ImmOpSel:
   38309        1160 :     return parseOptionalOperand(Operands);
   38310           9 :   case MCK_ImmOpSelHi:
   38311           9 :     return parseOptionalOperand(Operands);
   38312          12 :   case MCK_ImmNegLo:
   38313          12 :     return parseOptionalOperand(Operands);
   38314           0 :   case MCK_ImmNegHi:
   38315           0 :     return parseOptionalOperand(Operands);
   38316         260 :   case MCK_ImmHwreg:
   38317         260 :     return parseHwreg(Operands);
   38318         240 :   case MCK_ImmExpTgt:
   38319         240 :     return parseExpTgt(Operands);
   38320         561 :   case MCK_ImmSMRDOffset8:
   38321         561 :     return parseOptionalOperand(Operands);
   38322        1337 :   case MCK_ImmSMRDOffset20:
   38323        1337 :     return parseOptionalOperand(Operands);
   38324         303 :   case MCK_ImmSMRDLiteralOffset:
   38325         303 :     return parseOptionalOperand(Operands);
   38326             :   default:
   38327             :     return MatchOperand_NoMatch;
   38328             :   }
   38329             :   return MatchOperand_NoMatch;
   38330             : }
   38331             : 
   38332      561962 : OperandMatchResultTy AMDGPUAsmParser::
   38333             : MatchOperandParserImpl(OperandVector &Operands,
   38334             :                        StringRef Mnemonic,
   38335             :                        bool ParseForAllFeatures) {
   38336             :   // Get the current feature set.
   38337      561962 :   uint64_t AvailableFeatures = getAvailableFeatures();
   38338             : 
   38339             :   // Get the next operand index.
   38340      561962 :   unsigned NextOpNum = Operands.size() - 1;
   38341             :   // Search the table.
   38342             :   auto MnemonicRange =
   38343             :     std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
   38344             :                      Mnemonic, LessOpcodeOperand());
   38345             : 
   38346      561962 :   if (MnemonicRange.first == MnemonicRange.second)
   38347             :     return MatchOperand_NoMatch;
   38348             : 
   38349     4995970 :   for (const OperandMatchEntry *it = MnemonicRange.first,
   38350     5473973 :        *ie = MnemonicRange.second; it != ie; ++it) {
   38351             :     // equal_range guarantees that instruction mnemonic matches.
   38352             :     assert(Mnemonic == it->getMnemonic());
   38353             : 
   38354             :     // check if the available features match
   38355     5256465 :     if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures)
   38356             :         continue;
   38357             : 
   38358             :     // check if the operand in question has a custom parser.
   38359     3426165 :     if (!(it->OperandMask & (1 << NextOpNum)))
   38360             :       continue;
   38361             : 
   38362             :     // call custom parse method to handle the operand
   38363      276261 :     OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
   38364      276261 :     if (Result != MatchOperand_NoMatch)
   38365      260495 :       return Result;
   38366             :   }
   38367             : 
   38368             :   // Okay, we had no match.
   38369             :   return MatchOperand_NoMatch;
   38370             : }
   38371             : 
   38372             : #endif // GET_MATCHER_IMPLEMENTATION
   38373             : 
   38374             : 
   38375             : #ifdef GET_MNEMONIC_SPELL_CHECKER
   38376             : #undef GET_MNEMONIC_SPELL_CHECKER
   38377             : 
   38378          10 : static std::string AMDGPUMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {
   38379             :   const unsigned MaxEditDist = 2;
   38380             :   std::vector<StringRef> Candidates;
   38381             :   StringRef Prev = "";
   38382             : 
   38383             :   // Find the appropriate table for this asm variant.
   38384             :   const MatchEntry *Start, *End;
   38385          10 :   switch (VariantID) {
   38386           0 :   default: llvm_unreachable("invalid variant!");
   38387             :   case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
   38388           0 :   case 1: Start = std::begin(MatchTable1); End = std::end(MatchTable1); break;
   38389           0 :   case 2: Start = std::begin(MatchTable2); End = std::end(MatchTable2); break;
   38390           0 :   case 3: Start = std::begin(MatchTable3); End = std::end(MatchTable3); break;
   38391           0 :   case 4: Start = std::begin(MatchTable4); End = std::end(MatchTable4); break;
   38392             :   }
   38393             : 
   38394       44010 :   for (auto I = Start; I < End; I++) {
   38395             :     // Ignore unsupported instructions.
   38396       44000 :     if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)
   38397       33536 :       continue;
   38398             : 
   38399       24534 :     StringRef T = I->getMnemonic();
   38400             :     // Avoid recomputing the edit distance for the same string.
   38401             :     if (T.equals(Prev))
   38402             :       continue;
   38403             : 
   38404             :     Prev = T;
   38405       10464 :     unsigned Dist = S.edit_distance(T, false, MaxEditDist);
   38406       10464 :     if (Dist <= MaxEditDist)
   38407           9 :       Candidates.push_back(T);
   38408             :   }
   38409             : 
   38410          10 :   if (Candidates.empty())
   38411           6 :     return "";
   38412             : 
   38413           4 :   std::string Res = ", did you mean: ";
   38414             :   unsigned i = 0;
   38415          18 :   for( ; i < Candidates.size() - 1; i++)
   38416          15 :     Res += Candidates[i].str() + ", ";
   38417          12 :   return Res + Candidates[i].str() + "?";
   38418             : }
   38419             : 
   38420             : #endif // GET_MNEMONIC_SPELL_CHECKER
   38421             : 

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