Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Calling Convention Implementation Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
10 : MVT LocVT, CCValAssign::LocInfo LocInfo,
11 : ISD::ArgFlagsTy ArgFlags, CCState &State);
12 : static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
13 : MVT LocVT, CCValAssign::LocInfo LocInfo,
14 : ISD::ArgFlagsTy ArgFlags, CCState &State);
15 : static bool CC_SI(unsigned ValNo, MVT ValVT,
16 : MVT LocVT, CCValAssign::LocInfo LocInfo,
17 : ISD::ArgFlagsTy ArgFlags, CCState &State);
18 : static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
19 : MVT LocVT, CCValAssign::LocInfo LocInfo,
20 : ISD::ArgFlagsTy ArgFlags, CCState &State);
21 : static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
22 : MVT LocVT, CCValAssign::LocInfo LocInfo,
23 : ISD::ArgFlagsTy ArgFlags, CCState &State);
24 :
25 :
26 13760 : static bool CC_AMDGPU(unsigned ValNo, MVT ValVT,
27 : MVT LocVT, CCValAssign::LocInfo LocInfo,
28 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
29 :
30 13760 : if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
31 13760 : if (!CC_SI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
32 : return false;
33 : }
34 :
35 0 : if (static_cast<const GCNSubtarget&>(State.getMachineFunction().getSubtarget()).getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C) {
36 0 : if (!CC_AMDGPU_Func(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
37 0 : return false;
38 : }
39 :
40 : return true; // CC didn't match.
41 : }
42 :
43 :
44 9285 : static bool CC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
45 : MVT LocVT, CCValAssign::LocInfo LocInfo,
46 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
47 :
48 9285 : if (ArgFlags.isByVal()) {
49 118 : State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
50 118 : return false;
51 : }
52 :
53 9167 : if (LocVT == MVT::i1) {
54 : LocVT = MVT::i32;
55 28 : if (ArgFlags.isSExt())
56 : LocInfo = CCValAssign::SExt;
57 21 : else if (ArgFlags.isZExt())
58 : LocInfo = CCValAssign::ZExt;
59 : else
60 : LocInfo = CCValAssign::AExt;
61 : }
62 :
63 9167 : if (LocVT == MVT::i1 ||
64 18334 : LocVT == MVT::i8 ||
65 : LocVT == MVT::i16) {
66 238 : if (ArgFlags.isSExt() || ArgFlags.isZExt()) {
67 : LocVT = MVT::i32;
68 26 : if (ArgFlags.isSExt())
69 : LocInfo = CCValAssign::SExt;
70 15 : else if (ArgFlags.isZExt())
71 : LocInfo = CCValAssign::ZExt;
72 : else
73 : LocInfo = CCValAssign::AExt;
74 : }
75 : }
76 :
77 2926 : if (LocVT == MVT::i32 ||
78 1814 : LocVT == MVT::f32 ||
79 1591 : LocVT == MVT::i16 ||
80 1065 : LocVT == MVT::f16 ||
81 898 : LocVT == MVT::v2i16 ||
82 9589 : LocVT == MVT::v2f16 ||
83 : LocVT == MVT::i1) {
84 : static const MCPhysReg RegList1[] = {
85 : AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
86 : };
87 8745 : if (unsigned Reg = State.AllocateReg(RegList1)) {
88 8361 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
89 8361 : return false;
90 : }
91 : }
92 :
93 429 : if (LocVT == MVT::i64 ||
94 384 : LocVT == MVT::f64 ||
95 384 : LocVT == MVT::v2i32 ||
96 384 : LocVT == MVT::v2f32 ||
97 384 : LocVT == MVT::v4i32 ||
98 384 : LocVT == MVT::v4f32 ||
99 384 : LocVT == MVT::v8i32 ||
100 384 : LocVT == MVT::v8f32 ||
101 384 : LocVT == MVT::v16i32 ||
102 384 : LocVT == MVT::v16f32 ||
103 384 : LocVT == MVT::v2i64 ||
104 384 : LocVT == MVT::v2f64 ||
105 1190 : LocVT == MVT::v4i16 ||
106 : LocVT == MVT::v4f16) {
107 422 : if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
108 : return false;
109 : }
110 :
111 158 : if (LocVT == MVT::i32 ||
112 65 : LocVT == MVT::f32 ||
113 63 : LocVT == MVT::v2i16 ||
114 61 : LocVT == MVT::v2f16 ||
115 25 : LocVT == MVT::i16 ||
116 430 : LocVT == MVT::f16 ||
117 : LocVT == MVT::i1) {
118 384 : unsigned Offset2 = State.AllocateStack(4, 4);
119 384 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
120 384 : return false;
121 : }
122 :
123 20 : if (LocVT == MVT::i64 ||
124 0 : LocVT == MVT::f64 ||
125 23 : LocVT == MVT::v2i32 ||
126 : LocVT == MVT::v2f32) {
127 23 : unsigned Offset3 = State.AllocateStack(8, 4);
128 23 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
129 23 : return false;
130 : }
131 :
132 0 : if (LocVT == MVT::v4i32 ||
133 0 : LocVT == MVT::v4f32 ||
134 0 : LocVT == MVT::v2i64 ||
135 : LocVT == MVT::v2f64) {
136 0 : unsigned Offset4 = State.AllocateStack(16, 4);
137 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
138 0 : return false;
139 : }
140 :
141 0 : if (LocVT == MVT::v8i32 ||
142 : LocVT == MVT::v8f32) {
143 0 : unsigned Offset5 = State.AllocateStack(32, 4);
144 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
145 0 : return false;
146 : }
147 :
148 0 : if (LocVT == MVT::v16i32 ||
149 : LocVT == MVT::v16f32) {
150 0 : unsigned Offset6 = State.AllocateStack(64, 4);
151 0 : State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
152 0 : return false;
153 : }
154 :
155 : return true; // CC didn't match.
156 : }
157 :
158 :
159 13760 : static bool CC_SI(unsigned ValNo, MVT ValVT,
160 : MVT LocVT, CCValAssign::LocInfo LocInfo,
161 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
162 :
163 13760 : if (ArgFlags.isInReg()) {
164 9326 : if (LocVT == MVT::f32 ||
165 311 : LocVT == MVT::i32 ||
166 310 : LocVT == MVT::f16 ||
167 9701 : LocVT == MVT::v2i16 ||
168 : LocVT == MVT::v2f16) {
169 : static const MCPhysReg RegList1[] = {
170 : AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
171 : };
172 9084 : if (unsigned Reg = State.AllocateReg(RegList1)) {
173 9084 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
174 9084 : return false;
175 : }
176 : }
177 : }
178 :
179 4676 : if (ArgFlags.isInReg()) {
180 308 : if (LocVT == MVT::i64) {
181 308 : if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
182 : return false;
183 : }
184 : }
185 :
186 4368 : if (ArgFlags.isByVal()) {
187 166 : if (LocVT == MVT::i64) {
188 166 : if (allocateSGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
189 : return false;
190 : }
191 : }
192 :
193 4202 : if (!ArgFlags.isInReg()) {
194 1839 : if (LocVT == MVT::f32 ||
195 224 : LocVT == MVT::i32 ||
196 2 : LocVT == MVT::f16 ||
197 4203 : LocVT == MVT::v2i16 ||
198 : LocVT == MVT::v2f16) {
199 : static const MCPhysReg RegList2[] = {
200 : AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
201 : };
202 4202 : if (unsigned Reg = State.AllocateReg(RegList2)) {
203 4202 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
204 4202 : return false;
205 : }
206 : }
207 : }
208 :
209 : return true; // CC didn't match.
210 : }
211 :
212 :
213 4616 : static bool RetCC_AMDGPU_Func(unsigned ValNo, MVT ValVT,
214 : MVT LocVT, CCValAssign::LocInfo LocInfo,
215 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
216 :
217 4616 : if (LocVT == MVT::i1) {
218 : LocVT = MVT::i32;
219 24 : if (ArgFlags.isSExt())
220 : LocInfo = CCValAssign::SExt;
221 21 : else if (ArgFlags.isZExt())
222 : LocInfo = CCValAssign::ZExt;
223 : else
224 : LocInfo = CCValAssign::AExt;
225 : }
226 :
227 4616 : if (LocVT == MVT::i1 ||
228 : LocVT == MVT::i16) {
229 176 : if (ArgFlags.isSExt() || ArgFlags.isZExt()) {
230 : LocVT = MVT::i32;
231 8 : if (ArgFlags.isSExt())
232 : LocInfo = CCValAssign::SExt;
233 4 : else if (ArgFlags.isZExt())
234 : LocInfo = CCValAssign::ZExt;
235 : else
236 : LocInfo = CCValAssign::AExt;
237 : }
238 : }
239 :
240 2262 : if (LocVT == MVT::i32 ||
241 1106 : LocVT == MVT::f32 ||
242 938 : LocVT == MVT::i16 ||
243 838 : LocVT == MVT::f16 ||
244 5280 : LocVT == MVT::v2i16 ||
245 : LocVT == MVT::v2f16) {
246 : static const MCPhysReg RegList1[] = {
247 : AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31
248 : };
249 4390 : if (unsigned Reg = State.AllocateReg(RegList1)) {
250 4378 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
251 4378 : return false;
252 : }
253 : }
254 :
255 58 : if (LocVT == MVT::i64 ||
256 12 : LocVT == MVT::f64 ||
257 12 : LocVT == MVT::v2i32 ||
258 12 : LocVT == MVT::v2f32 ||
259 12 : LocVT == MVT::v4i32 ||
260 12 : LocVT == MVT::v4f32 ||
261 12 : LocVT == MVT::v8i32 ||
262 12 : LocVT == MVT::v8f32 ||
263 12 : LocVT == MVT::v16i32 ||
264 12 : LocVT == MVT::v16f32 ||
265 12 : LocVT == MVT::v2i64 ||
266 12 : LocVT == MVT::v2f64 ||
267 250 : LocVT == MVT::v4i16 ||
268 : LocVT == MVT::v4f16) {
269 226 : if (allocateVGPRTuple(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
270 226 : return false;
271 : }
272 :
273 : return true; // CC didn't match.
274 : }
275 :
276 :
277 3831 : static bool RetCC_SI_Shader(unsigned ValNo, MVT ValVT,
278 : MVT LocVT, CCValAssign::LocInfo LocInfo,
279 : ISD::ArgFlagsTy ArgFlags, CCState &State) {
280 :
281 3831 : if (LocVT == MVT::i32) {
282 : static const MCPhysReg RegList1[] = {
283 : AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3, AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7, AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11, AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15, AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19, AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23, AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27, AMDGPU::SGPR28, AMDGPU::SGPR29, AMDGPU::SGPR30, AMDGPU::SGPR31, AMDGPU::SGPR32, AMDGPU::SGPR33, AMDGPU::SGPR34, AMDGPU::SGPR35, AMDGPU::SGPR36, AMDGPU::SGPR37, AMDGPU::SGPR38, AMDGPU::SGPR39
284 : };
285 151 : if (unsigned Reg = State.AllocateReg(RegList1)) {
286 151 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
287 151 : return false;
288 : }
289 : }
290 :
291 81 : if (LocVT == MVT::f32 ||
292 3682 : LocVT == MVT::f16 ||
293 : LocVT == MVT::v2f16) {
294 : static const MCPhysReg RegList2[] = {
295 : AMDGPU::VGPR0, AMDGPU::VGPR1, AMDGPU::VGPR2, AMDGPU::VGPR3, AMDGPU::VGPR4, AMDGPU::VGPR5, AMDGPU::VGPR6, AMDGPU::VGPR7, AMDGPU::VGPR8, AMDGPU::VGPR9, AMDGPU::VGPR10, AMDGPU::VGPR11, AMDGPU::VGPR12, AMDGPU::VGPR13, AMDGPU::VGPR14, AMDGPU::VGPR15, AMDGPU::VGPR16, AMDGPU::VGPR17, AMDGPU::VGPR18, AMDGPU::VGPR19, AMDGPU::VGPR20, AMDGPU::VGPR21, AMDGPU::VGPR22, AMDGPU::VGPR23, AMDGPU::VGPR24, AMDGPU::VGPR25, AMDGPU::VGPR26, AMDGPU::VGPR27, AMDGPU::VGPR28, AMDGPU::VGPR29, AMDGPU::VGPR30, AMDGPU::VGPR31, AMDGPU::VGPR32, AMDGPU::VGPR33, AMDGPU::VGPR34, AMDGPU::VGPR35, AMDGPU::VGPR36, AMDGPU::VGPR37, AMDGPU::VGPR38, AMDGPU::VGPR39, AMDGPU::VGPR40, AMDGPU::VGPR41, AMDGPU::VGPR42, AMDGPU::VGPR43, AMDGPU::VGPR44, AMDGPU::VGPR45, AMDGPU::VGPR46, AMDGPU::VGPR47, AMDGPU::VGPR48, AMDGPU::VGPR49, AMDGPU::VGPR50, AMDGPU::VGPR51, AMDGPU::VGPR52, AMDGPU::VGPR53, AMDGPU::VGPR54, AMDGPU::VGPR55, AMDGPU::VGPR56, AMDGPU::VGPR57, AMDGPU::VGPR58, AMDGPU::VGPR59, AMDGPU::VGPR60, AMDGPU::VGPR61, AMDGPU::VGPR62, AMDGPU::VGPR63, AMDGPU::VGPR64, AMDGPU::VGPR65, AMDGPU::VGPR66, AMDGPU::VGPR67, AMDGPU::VGPR68, AMDGPU::VGPR69, AMDGPU::VGPR70, AMDGPU::VGPR71, AMDGPU::VGPR72, AMDGPU::VGPR73, AMDGPU::VGPR74, AMDGPU::VGPR75, AMDGPU::VGPR76, AMDGPU::VGPR77, AMDGPU::VGPR78, AMDGPU::VGPR79, AMDGPU::VGPR80, AMDGPU::VGPR81, AMDGPU::VGPR82, AMDGPU::VGPR83, AMDGPU::VGPR84, AMDGPU::VGPR85, AMDGPU::VGPR86, AMDGPU::VGPR87, AMDGPU::VGPR88, AMDGPU::VGPR89, AMDGPU::VGPR90, AMDGPU::VGPR91, AMDGPU::VGPR92, AMDGPU::VGPR93, AMDGPU::VGPR94, AMDGPU::VGPR95, AMDGPU::VGPR96, AMDGPU::VGPR97, AMDGPU::VGPR98, AMDGPU::VGPR99, AMDGPU::VGPR100, AMDGPU::VGPR101, AMDGPU::VGPR102, AMDGPU::VGPR103, AMDGPU::VGPR104, AMDGPU::VGPR105, AMDGPU::VGPR106, AMDGPU::VGPR107, AMDGPU::VGPR108, AMDGPU::VGPR109, AMDGPU::VGPR110, AMDGPU::VGPR111, AMDGPU::VGPR112, AMDGPU::VGPR113, AMDGPU::VGPR114, AMDGPU::VGPR115, AMDGPU::VGPR116, AMDGPU::VGPR117, AMDGPU::VGPR118, AMDGPU::VGPR119, AMDGPU::VGPR120, AMDGPU::VGPR121, AMDGPU::VGPR122, AMDGPU::VGPR123, AMDGPU::VGPR124, AMDGPU::VGPR125, AMDGPU::VGPR126, AMDGPU::VGPR127, AMDGPU::VGPR128, AMDGPU::VGPR129, AMDGPU::VGPR130, AMDGPU::VGPR131, AMDGPU::VGPR132, AMDGPU::VGPR133, AMDGPU::VGPR134, AMDGPU::VGPR135
296 : };
297 3680 : if (unsigned Reg = State.AllocateReg(RegList2)) {
298 3680 : State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
299 3680 : return false;
300 : }
301 : }
302 :
303 : return true; // CC didn't match.
304 : }
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