LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - AMDGPUGenGlobalISel.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 48 61 78.7 %
Date: 2018-10-20 13:21:21 Functions: 4 8 50.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Global Instruction Selector for the AMDGPU target                          *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : #ifdef GET_GLOBALISEL_PREDICATE_BITSET
      10             : const unsigned MAX_SUBTARGET_PREDICATES = 32;
      11             : using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
      12             : #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
      13             : 
      14             : #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      15             :   mutable MatcherState State;
      16             :   typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
      17             :   typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
      18             :   const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
      19             :   static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
      20             :   static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
      21             :   bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
      22             :   bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
      23             :   bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
      24             :   const int64_t *getMatchTable() const override;
      25             :   bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
      26             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
      27             : 
      28             : #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      29             : , State(3),
      30        4984 : ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
      31             : #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
      32             : 
      33             : #ifdef GET_GLOBALISEL_IMPL
      34             : // Bits for subtarget features that participate in instruction matching.
      35             : enum SubtargetFeatureBits : uint8_t {
      36             :   Feature_isSICIBit = 3,
      37             :   Feature_isVIBit = 2,
      38             :   Feature_isGFX9Bit = 6,
      39             :   Feature_isCIVIBit = 7,
      40             :   Feature_HasFlatAddressSpaceBit = 8,
      41             :   Feature_HasFlatGlobalInstsBit = 9,
      42             :   Feature_HasUnpackedD16VMemBit = 20,
      43             :   Feature_HasPackedD16VMemBit = 21,
      44             :   Feature_D16PreservesUnusedBitsBit = 19,
      45             :   Feature_LDSRequiresM0InitBit = 30,
      46             :   Feature_NotLDSRequiresM0InitBit = 31,
      47             :   Feature_HasAddNoCarryInstsBit = 14,
      48             :   Feature_Has16BitInstsBit = 4,
      49             :   Feature_HasVOP3PInstsBit = 23,
      50             :   Feature_HasMadMixInstsBit = 15,
      51             :   Feature_has16BankLDSBit = 12,
      52             :   Feature_has32BankLDSBit = 11,
      53             :   Feature_HasFmaMixInstsBit = 16,
      54             :   Feature_HasDLInstsBit = 17,
      55             :   Feature_EnableLateCFGStructurizeBit = 13,
      56             :   Feature_TruePredicateBit = 0,
      57             :   Feature_FP16DenormalsBit = 25,
      58             :   Feature_FP32DenormalsBit = 27,
      59             :   Feature_FP64DenormalsBit = 29,
      60             :   Feature_NoFP16DenormalsBit = 24,
      61             :   Feature_NoFP32DenormalsBit = 26,
      62             :   Feature_NoFP64DenormalsBit = 28,
      63             :   Feature_UnsafeFPMathBit = 22,
      64             :   Feature_isCIOnlyBit = 18,
      65             :   Feature_isVIOnlyBit = 5,
      66             :   Feature_isGCNBit = 1,
      67             :   Feature_isSIBit = 10,
      68             : };
      69             : 
      70        2492 : PredicateBitset AMDGPUInstructionSelector::
      71             : computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
      72        2492 :   PredicateBitset Features;
      73        2492 :   if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
      74             :     Features[Feature_isSICIBit] = 1;
      75        2492 :   if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
      76             :     Features[Feature_isVIBit] = 1;
      77        2492 :   if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
      78             :     Features[Feature_isGFX9Bit] = 1;
      79        2492 :   if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
      80             :     Features[Feature_isCIVIBit] = 1;
      81        2492 :   if (Subtarget->hasFlatAddressSpace())
      82             :     Features[Feature_HasFlatAddressSpaceBit] = 1;
      83        2492 :   if (Subtarget->hasFlatGlobalInsts())
      84             :     Features[Feature_HasFlatGlobalInstsBit] = 1;
      85        2492 :   if (Subtarget->hasUnpackedD16VMem())
      86             :     Features[Feature_HasUnpackedD16VMemBit] = 1;
      87        2492 :   if (!Subtarget->hasUnpackedD16VMem())
      88             :     Features[Feature_HasPackedD16VMemBit] = 1;
      89        2492 :   if (Subtarget->d16PreservesUnusedBits())
      90             :     Features[Feature_D16PreservesUnusedBitsBit] = 1;
      91        2492 :   if (Subtarget->ldsRequiresM0Init())
      92             :     Features[Feature_LDSRequiresM0InitBit] = 1;
      93        2492 :   if (!Subtarget->ldsRequiresM0Init())
      94             :     Features[Feature_NotLDSRequiresM0InitBit] = 1;
      95        2492 :   if (Subtarget->hasAddNoCarry())
      96             :     Features[Feature_HasAddNoCarryInstsBit] = 1;
      97        2492 :   if (Subtarget->has16BitInsts())
      98             :     Features[Feature_Has16BitInstsBit] = 1;
      99        2492 :   if (Subtarget->hasVOP3PInsts())
     100             :     Features[Feature_HasVOP3PInstsBit] = 1;
     101        2492 :   if (Subtarget->hasMadMixInsts())
     102             :     Features[Feature_HasMadMixInstsBit] = 1;
     103        2492 :   if (Subtarget->getLDSBankCount() == 16)
     104             :     Features[Feature_has16BankLDSBit] = 1;
     105        2492 :   if (Subtarget->getLDSBankCount() == 32)
     106             :     Features[Feature_has32BankLDSBit] = 1;
     107        2492 :   if (Subtarget->hasFmaMixInsts())
     108             :     Features[Feature_HasFmaMixInstsBit] = 1;
     109        2492 :   if (Subtarget->hasDLInsts())
     110             :     Features[Feature_HasDLInstsBit] = 1;
     111        2492 :   if (EnableLateStructurizeCFG)
     112             :     Features[Feature_EnableLateCFGStructurizeBit] = 1;
     113             :   if (true)
     114             :     Features[Feature_TruePredicateBit] = 1;
     115        2492 :   if (Subtarget->hasFP16Denormals())
     116             :     Features[Feature_FP16DenormalsBit] = 1;
     117        2492 :   if (Subtarget->hasFP32Denormals())
     118             :     Features[Feature_FP32DenormalsBit] = 1;
     119        2492 :   if (Subtarget->hasFP64Denormals())
     120             :     Features[Feature_FP64DenormalsBit] = 1;
     121        2492 :   if (!Subtarget->hasFP16Denormals())
     122             :     Features[Feature_NoFP16DenormalsBit] = 1;
     123        2492 :   if (!Subtarget->hasFP32Denormals())
     124             :     Features[Feature_NoFP32DenormalsBit] = 1;
     125        2492 :   if (!Subtarget->hasFP64Denormals())
     126             :     Features[Feature_NoFP64DenormalsBit] = 1;
     127        2492 :   if (TM.Options.UnsafeFPMath)
     128             :     Features[Feature_UnsafeFPMathBit] = 1;
     129        2492 :   if (Subtarget->getGeneration() ==AMDGPUSubtarget::SEA_ISLANDS)
     130             :     Features[Feature_isCIOnlyBit] = 1;
     131        2492 :   if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
     132             :     Features[Feature_isVIOnlyBit] = 1;
     133        2492 :   if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
     134             :     Features[Feature_isGCNBit] = 1;
     135        2492 :   if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
     136             :     Features[Feature_isSIBit] = 1;
     137        2492 :   return Features;
     138             : }
     139             : 
     140          56 : PredicateBitset AMDGPUInstructionSelector::
     141             : computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
     142             :   PredicateBitset Features;
     143          56 :   return Features;
     144             : }
     145             : 
     146             : // LLT Objects.
     147             : enum {
     148             :   GILLT_s1,
     149             :   GILLT_s16,
     150             :   GILLT_s32,
     151             :   GILLT_s64,
     152             :   GILLT_v2s16,
     153             :   GILLT_v2s32,
     154             :   GILLT_v2s64,
     155             :   GILLT_v4s16,
     156             :   GILLT_v4s32,
     157             :   GILLT_v8s32,
     158             :   GILLT_v16s32,
     159             : };
     160             : const static size_t NumTypeObjects = 11;
     161             : const static LLT TypeObjects[] = {
     162             :   LLT::scalar(1),
     163             :   LLT::scalar(16),
     164             :   LLT::scalar(32),
     165             :   LLT::scalar(64),
     166             :   LLT::vector(2, 16),
     167             :   LLT::vector(2, 32),
     168             :   LLT::vector(2, 64),
     169             :   LLT::vector(4, 16),
     170             :   LLT::vector(4, 32),
     171             :   LLT::vector(8, 32),
     172             :   LLT::vector(16, 32),
     173             : };
     174             : 
     175             : // Feature bitsets.
     176             : enum {
     177             :   GIFBS_Invalid,
     178             :   GIFBS_Has16BitInsts,
     179             :   GIFBS_isGCN,
     180             :   GIFBS_isSICI,
     181             :   GIFBS_TruePredicate_isCIVI,
     182             :   GIFBS_TruePredicate_isGCN,
     183             :   GIFBS_TruePredicate_isSI,
     184             :   GIFBS_TruePredicate_isSICI,
     185             :   GIFBS_TruePredicate_isVI,
     186             : };
     187             : const static PredicateBitset FeatureBitsets[] {
     188             :   {}, // GIFBS_Invalid
     189             :   {Feature_Has16BitInstsBit, },
     190             :   {Feature_isGCNBit, },
     191             :   {Feature_isSICIBit, },
     192             :   {Feature_TruePredicateBit, Feature_isCIVIBit, },
     193             :   {Feature_TruePredicateBit, Feature_isGCNBit, },
     194             :   {Feature_TruePredicateBit, Feature_isSIBit, },
     195             :   {Feature_TruePredicateBit, Feature_isSICIBit, },
     196             :   {Feature_TruePredicateBit, Feature_isVIBit, },
     197             : };
     198             : 
     199             : // ComplexPattern predicates.
     200             : enum {
     201             :   GICP_Invalid,
     202             :   GICP_gi_vcsrc,
     203             :   GICP_gi_vop3mods,
     204             :   GICP_gi_vop3mods0,
     205             :   GICP_gi_vop3omods,
     206             :   GICP_gi_vsrc0,
     207             : };
     208             : // See constructor for table contents
     209             : 
     210             : // PatFrag predicates.
     211             : enum {
     212             :   GIPFP_I64_Predicate_NegSubInlineConst16 = GIPFP_I64_Invalid + 1,
     213             :   GIPFP_I64_Predicate_NegSubInlineConst32,
     214             : };
     215           0 : bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
     216           0 :   switch (PredicateID) {
     217           0 :   case GIPFP_I64_Predicate_NegSubInlineConst16: {
     218             :     
     219           0 :   return Imm < -16 && Imm >= -64;
     220             : 
     221             :     llvm_unreachable("ImmediateCode should have returned");
     222             :     return false;
     223             :   }
     224           0 :   case GIPFP_I64_Predicate_NegSubInlineConst32: {
     225             :     
     226           0 :   return Imm < -16 && Imm >= -64;
     227             : 
     228             :     llvm_unreachable("ImmediateCode should have returned");
     229             :     return false;
     230             :   }
     231             :   }
     232           0 :   llvm_unreachable("Unknown predicate");
     233             :   return false;
     234             : }
     235           0 : bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
     236           0 :   llvm_unreachable("Unknown predicate");
     237             :   return false;
     238             : }
     239           0 : bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
     240           0 :   llvm_unreachable("Unknown predicate");
     241             :   return false;
     242             : }
     243           0 : bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
     244             :   const MachineFunction &MF = *MI.getParent()->getParent();
     245             :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     246             :   (void)MRI;
     247           0 :   llvm_unreachable("Unknown predicate");
     248             :   return false;
     249             : }
     250             : 
     251             : AMDGPUInstructionSelector::ComplexMatcherMemFn
     252             : AMDGPUInstructionSelector::ComplexPredicateFns[] = {
     253             :   nullptr, // GICP_Invalid
     254             :   &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
     255             :   &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
     256             :   &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
     257             :   &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
     258             :   &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
     259             : };
     260             : 
     261             : // Custom renderers.
     262             : enum {
     263             :   GICR_Invalid,
     264             : };
     265             : AMDGPUInstructionSelector::CustomRendererFn
     266             : AMDGPUInstructionSelector::CustomRenderers[] = {
     267             :   nullptr, // GICP_Invalid
     268             : };
     269             : 
     270          56 : bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
     271          56 :   MachineFunction &MF = *I.getParent()->getParent();
     272          56 :   MachineRegisterInfo &MRI = MF.getRegInfo();
     273             :   // FIXME: This should be computed on a per-function basis rather than per-insn.
     274          56 :   AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
     275          56 :   const PredicateBitset AvailableFeatures = getAvailableFeatures();
     276             :   NewMIVector OutMIs;
     277             :   State.MIs.clear();
     278          56 :   State.MIs.push_back(&I);
     279             : 
     280          56 :   if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
     281          56 :     return true;
     282             :   }
     283             : 
     284             :   return false;
     285             : }
     286             : 
     287          56 : const int64_t *AMDGPUInstructionSelector::getMatchTable() const {
     288             :   constexpr static int64_t MatchTable0[] = {
     289             :     GIM_SwitchOpcode, /*MI*/0, /*[*/34, 134, /*)*//*default:*//*Label 28*/ 9732,
     290             :     /*TargetOpcode::G_ADD*//*Label 0*/ 105,
     291             :     /*TargetOpcode::G_SUB*//*Label 1*/ 302,
     292             :     /*TargetOpcode::G_MUL*//*Label 2*/ 333, 0, 0, 0, 0,
     293             :     /*TargetOpcode::G_AND*//*Label 3*/ 361,
     294             :     /*TargetOpcode::G_OR*//*Label 4*/ 392,
     295             :     /*TargetOpcode::G_XOR*//*Label 5*/ 2141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
     296             :     /*TargetOpcode::G_BITCAST*//*Label 6*/ 2245, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
     297             :     /*TargetOpcode::G_INTRINSIC*//*Label 7*/ 4387,
     298             :     /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 8*/ 6839, 0, 0,
     299             :     /*TargetOpcode::G_CONSTANT*//*Label 9*/ 7138, 0, 0, 0, 0, 0,
     300             :     /*TargetOpcode::G_SHL*//*Label 10*/ 7195,
     301             :     /*TargetOpcode::G_LSHR*//*Label 11*/ 7226,
     302             :     /*TargetOpcode::G_ASHR*//*Label 12*/ 7257, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
     303             :     /*TargetOpcode::G_FADD*//*Label 13*/ 7424,
     304             :     /*TargetOpcode::G_FSUB*//*Label 14*/ 7774,
     305             :     /*TargetOpcode::G_FMUL*//*Label 15*/ 7907,
     306             :     /*TargetOpcode::G_FMA*//*Label 16*/ 8257, 0, 0,
     307             :     /*TargetOpcode::G_FPOW*//*Label 17*/ 8501, 0,
     308             :     /*TargetOpcode::G_FEXP2*//*Label 18*/ 8574, 0,
     309             :     /*TargetOpcode::G_FLOG2*//*Label 19*/ 8671, 0,
     310             :     /*TargetOpcode::G_FPEXT*//*Label 20*/ 8768,
     311             :     /*TargetOpcode::G_FPTRUNC*//*Label 21*/ 8865,
     312             :     /*TargetOpcode::G_FPTOSI*//*Label 22*/ 8962,
     313             :     /*TargetOpcode::G_FPTOUI*//*Label 23*/ 9196,
     314             :     /*TargetOpcode::G_SITOFP*//*Label 24*/ 9430,
     315             :     /*TargetOpcode::G_UITOFP*//*Label 25*/ 9560, 0, 0, 0,
     316             :     /*TargetOpcode::G_BR*//*Label 26*/ 9690, 0, 0, 0, 0, 0, 0, 0,
     317             :     /*TargetOpcode::G_CTPOP*//*Label 27*/ 9705,
     318             :     // Label 0: @105
     319             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 31*/ 301,
     320             :     /*GILLT_s16*//*Label 29*/ 114, 0,
     321             :     /*GILLT_s64*//*Label 30*/ 274,
     322             :     // Label 29: @114
     323             :     GIM_Try, /*On fail goto*//*Label 32*/ 273,
     324             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
     325             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
     326             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
     327             :       GIM_Try, /*On fail goto*//*Label 33*/ 176, // Rule ID 958 //
     328             :         GIM_CheckFeatures, GIFBS_Has16BitInsts,
     329             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     330             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
     331             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     332             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     333             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     334             :         // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
     335             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
     336             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     337             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     338             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     339             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
     340             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
     341             :         GIR_EraseFromParent, /*InsnID*/0,
     342             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     343             :         // GIR_Coverage, 958,
     344             :         GIR_Done,
     345             :       // Label 33: @176
     346             :       GIM_Try, /*On fail goto*//*Label 34*/ 224, // Rule ID 959 //
     347             :         GIM_CheckFeatures, GIFBS_Has16BitInsts,
     348             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     349             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
     350             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     351             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     352             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     353             :         // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_I16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
     354             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
     355             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     356             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     357             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     358             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
     359             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
     360             :         GIR_EraseFromParent, /*InsnID*/0,
     361             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     362             :         // GIR_Coverage, 959,
     363             :         GIR_Done,
     364             :       // Label 34: @224
     365             :       GIM_Try, /*On fail goto*//*Label 35*/ 272, // Rule ID 2010 //
     366             :         GIM_CheckFeatures, GIFBS_Has16BitInsts,
     367             :         GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     368             :         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
     369             :         GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     370             :         GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     371             :         GIM_CheckIsSafeToFold, /*InsnID*/1,
     372             :         // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
     373             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
     374             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     375             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
     376             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
     377             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
     378             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
     379             :         GIR_EraseFromParent, /*InsnID*/0,
     380             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     381             :         // GIR_Coverage, 2010,
     382             :         GIR_Done,
     383             :       // Label 35: @272
     384             :       GIM_Reject,
     385             :     // Label 32: @273
     386             :     GIM_Reject,
     387             :     // Label 30: @274
     388             :     GIM_Try, /*On fail goto*//*Label 36*/ 300, // Rule ID 653 //
     389             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     390             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
     391             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
     392             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
     393             :       // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     394             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ADD_U64_PSEUDO,
     395             :       GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
     396             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     397             :       // GIR_Coverage, 653,
     398             :       GIR_Done,
     399             :     // Label 36: @300
     400             :     GIM_Reject,
     401             :     // Label 31: @301
     402             :     GIM_Reject,
     403             :     // Label 1: @302
     404             :     GIM_Try, /*On fail goto*//*Label 37*/ 332, // Rule ID 654 //
     405             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     406             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
     407             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
     408             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
     409             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
     410             :       // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
     411             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_SUB_U64_PSEUDO,
     412             :       GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
     413             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     414             :       // GIR_Coverage, 654,
     415             :       GIR_Done,
     416             :     // Label 37: @332
     417             :     GIM_Reject,
     418             :     // Label 2: @333
     419             :     GIM_Try, /*On fail goto*//*Label 38*/ 360, // Rule ID 35 //
     420             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     421             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     422             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
     423             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     424             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
     425             :       // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     426             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_MUL_I32,
     427             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     428             :       // GIR_Coverage, 35,
     429             :       GIR_Done,
     430             :     // Label 38: @360
     431             :     GIM_Reject,
     432             :     // Label 3: @361
     433             :     GIM_Try, /*On fail goto*//*Label 39*/ 391, // Rule ID 411 //
     434             :       GIM_CheckFeatures, GIFBS_isGCN,
     435             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     436             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
     437             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     438             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
     439             :       // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
     440             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e64,
     441             :       GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
     442             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     443             :       // GIR_Coverage, 411,
     444             :       GIR_Done,
     445             :     // Label 39: @391
     446             :     GIM_Reject,
     447             :     // Label 4: @392
     448             :     GIM_Try, /*On fail goto*//*Label 40*/ 2140,
     449             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
     450             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
     451             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
     452             :       GIM_Try, /*On fail goto*//*Label 41*/ 2095,
     453             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
     454             :         GIM_Try, /*On fail goto*//*Label 42*/ 513, // Rule ID 1987 //
     455             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     456             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     457             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     458             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     459             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     460             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     461             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     462             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     463             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     464             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     465             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     466             :           // MIs[3] x
     467             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     468             :           // MIs[3] z
     469             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     470             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     471             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     472             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     473             :           // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     474             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     475             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     476             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     477             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     478             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
     479             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     480             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     481             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     482             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     483             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
     484             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
     485             :           GIR_EraseFromParent, /*InsnID*/0,
     486             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     487             :           // GIR_Coverage, 1987,
     488             :           GIR_Done,
     489             :         // Label 42: @513
     490             :         GIM_Try, /*On fail goto*//*Label 43*/ 614, // Rule ID 1988 //
     491             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     492             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     493             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     494             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     495             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     496             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     497             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     498             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     499             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     500             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     501             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     502             :           // MIs[3] z
     503             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     504             :           // MIs[3] x
     505             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     506             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     507             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     508             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     509             :           // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     510             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     511             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     512             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     513             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     514             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
     515             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     516             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     517             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     518             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     519             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
     520             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
     521             :           GIR_EraseFromParent, /*InsnID*/0,
     522             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     523             :           // GIR_Coverage, 1988,
     524             :           GIR_Done,
     525             :         // Label 43: @614
     526             :         GIM_Try, /*On fail goto*//*Label 44*/ 715, // Rule ID 1989 //
     527             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     528             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     529             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     530             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     531             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     532             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     533             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     534             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     535             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     536             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     537             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     538             :           // MIs[3] x
     539             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     540             :           // MIs[3] z
     541             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     542             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     543             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     544             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     545             :           // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     546             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     547             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     548             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     549             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
     550             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
     551             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     552             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     553             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     554             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     555             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
     556             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
     557             :           GIR_EraseFromParent, /*InsnID*/0,
     558             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     559             :           // GIR_Coverage, 1989,
     560             :           GIR_Done,
     561             :         // Label 44: @715
     562             :         GIM_Try, /*On fail goto*//*Label 45*/ 816, // Rule ID 1990 //
     563             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     564             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     565             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     566             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     567             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     568             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     569             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     570             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     571             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     572             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     573             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     574             :           // MIs[3] z
     575             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     576             :           // MIs[3] x
     577             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     578             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     579             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     580             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     581             :           // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     582             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     583             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     584             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     585             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
     586             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
     587             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     588             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     589             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     590             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     591             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
     592             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
     593             :           GIR_EraseFromParent, /*InsnID*/0,
     594             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     595             :           // GIR_Coverage, 1990,
     596             :           GIR_Done,
     597             :         // Label 45: @816
     598             :         GIM_Try, /*On fail goto*//*Label 46*/ 917, // Rule ID 1983 //
     599             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     600             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     601             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     602             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     603             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     604             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     605             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     606             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     607             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     608             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     609             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     610             :           // MIs[3] x
     611             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     612             :           // MIs[3] z
     613             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     614             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     615             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     616             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     617             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     618             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     619             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     620             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     621             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     622             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
     623             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     624             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     625             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     626             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     627             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
     628             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
     629             :           GIR_EraseFromParent, /*InsnID*/0,
     630             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     631             :           // GIR_Coverage, 1983,
     632             :           GIR_Done,
     633             :         // Label 46: @917
     634             :         GIM_Try, /*On fail goto*//*Label 47*/ 1018, // Rule ID 1984 //
     635             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     636             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     637             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     638             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     639             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     640             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     641             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     642             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     643             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     644             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     645             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     646             :           // MIs[3] z
     647             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     648             :           // MIs[3] x
     649             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     650             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     651             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     652             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     653             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     654             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     655             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     656             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     657             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
     658             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
     659             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     660             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     661             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     662             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     663             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
     664             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
     665             :           GIR_EraseFromParent, /*InsnID*/0,
     666             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     667             :           // GIR_Coverage, 1984,
     668             :           GIR_Done,
     669             :         // Label 47: @1018
     670             :         GIM_Try, /*On fail goto*//*Label 48*/ 1119, // Rule ID 1985 //
     671             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     672             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     673             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     674             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     675             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     676             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     677             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     678             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     679             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     680             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     681             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     682             :           // MIs[3] x
     683             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     684             :           // MIs[3] z
     685             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     686             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     687             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     688             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     689             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     690             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     691             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     692             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     693             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
     694             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
     695             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     696             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     697             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     698             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     699             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
     700             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
     701             :           GIR_EraseFromParent, /*InsnID*/0,
     702             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     703             :           // GIR_Coverage, 1985,
     704             :           GIR_Done,
     705             :         // Label 48: @1119
     706             :         GIM_Try, /*On fail goto*//*Label 49*/ 1220, // Rule ID 1986 //
     707             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     708             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     709             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     710             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     711             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     712             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     713             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
     714             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     715             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     716             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     717             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
     718             :           // MIs[3] z
     719             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     720             :           // MIs[3] x
     721             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     722             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     723             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     724             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     725             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     726             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     727             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     728             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     729             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
     730             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
     731             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     732             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     733             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     734             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     735             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
     736             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
     737             :           GIR_EraseFromParent, /*InsnID*/0,
     738             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     739             :           // GIR_Coverage, 1986,
     740             :           GIR_Done,
     741             :         // Label 49: @1220
     742             :         GIM_Try, /*On fail goto*//*Label 50*/ 1321, // Rule ID 1977 //
     743             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     744             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     745             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     746             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     747             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     748             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     749             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
     750             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     751             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     752             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     753             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
     754             :           // MIs[3] x
     755             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     756             :           // MIs[3] z
     757             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     758             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     759             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     760             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     761             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     762             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     763             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     764             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     765             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     766             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
     767             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     768             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     769             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     770             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     771             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
     772             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
     773             :           GIR_EraseFromParent, /*InsnID*/0,
     774             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     775             :           // GIR_Coverage, 1977,
     776             :           GIR_Done,
     777             :         // Label 50: @1321
     778             :         GIM_Try, /*On fail goto*//*Label 51*/ 1422, // Rule ID 1978 //
     779             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     780             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     781             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     782             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     783             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     784             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     785             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
     786             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     787             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     788             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     789             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
     790             :           // MIs[3] z
     791             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     792             :           // MIs[3] x
     793             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     794             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     795             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     796             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     797             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     798             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     799             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     800             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     801             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     802             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
     803             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     804             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     805             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     806             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     807             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
     808             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
     809             :           GIR_EraseFromParent, /*InsnID*/0,
     810             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     811             :           // GIR_Coverage, 1978,
     812             :           GIR_Done,
     813             :         // Label 51: @1422
     814             :         GIM_Try, /*On fail goto*//*Label 52*/ 1523, // Rule ID 1981 //
     815             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     816             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     817             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     818             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     819             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     820             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     821             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
     822             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     823             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     824             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     825             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
     826             :           // MIs[3] x
     827             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     828             :           // MIs[3] z
     829             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     830             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     831             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     832             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     833             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     834             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     835             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     836             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     837             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     838             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
     839             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     840             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     841             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     842             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     843             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
     844             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
     845             :           GIR_EraseFromParent, /*InsnID*/0,
     846             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     847             :           // GIR_Coverage, 1981,
     848             :           GIR_Done,
     849             :         // Label 52: @1523
     850             :         GIM_Try, /*On fail goto*//*Label 53*/ 1624, // Rule ID 1982 //
     851             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     852             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     853             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     854             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     855             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     856             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     857             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
     858             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     859             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     860             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     861             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
     862             :           // MIs[3] z
     863             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     864             :           // MIs[3] x
     865             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     866             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     867             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     868             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     869             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     870             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     871             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     872             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     873             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     874             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
     875             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     876             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     877             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     878             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     879             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
     880             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
     881             :           GIR_EraseFromParent, /*InsnID*/0,
     882             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     883             :           // GIR_Coverage, 1982,
     884             :           GIR_Done,
     885             :         // Label 53: @1624
     886             :         GIM_Try, /*On fail goto*//*Label 54*/ 1725, // Rule ID 806 //
     887             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     888             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     889             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     890             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     891             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     892             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     893             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
     894             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     895             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     896             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     897             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
     898             :           // MIs[3] x
     899             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     900             :           // MIs[3] z
     901             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     902             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     903             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     904             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     905             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     906             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     907             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     908             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     909             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     910             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
     911             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     912             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     913             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     914             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     915             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
     916             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
     917             :           GIR_EraseFromParent, /*InsnID*/0,
     918             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     919             :           // GIR_Coverage, 806,
     920             :           GIR_Done,
     921             :         // Label 54: @1725
     922             :         GIM_Try, /*On fail goto*//*Label 55*/ 1826, // Rule ID 1976 //
     923             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     924             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     925             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     926             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     927             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     928             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     929             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
     930             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     931             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     932             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     933             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
     934             :           // MIs[3] z
     935             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     936             :           // MIs[3] x
     937             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     938             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     939             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     940             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     941             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     942             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     943             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     944             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     945             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
     946             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
     947             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     948             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     949             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     950             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     951             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
     952             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
     953             :           GIR_EraseFromParent, /*InsnID*/0,
     954             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     955             :           // GIR_Coverage, 1976,
     956             :           GIR_Done,
     957             :         // Label 55: @1826
     958             :         GIM_Try, /*On fail goto*//*Label 56*/ 1927, // Rule ID 1979 //
     959             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     960             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     961             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     962             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     963             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     964             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     965             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
     966             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     967             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     968             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     969             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
     970             :           // MIs[3] x
     971             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     972             :           // MIs[3] z
     973             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     974             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
     975             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
     976             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
     977             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
     978             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     979             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
     980             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
     981             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
     982             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
     983             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     984             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
     985             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
     986             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
     987             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
     988             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
     989             :           GIR_EraseFromParent, /*InsnID*/0,
     990             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
     991             :           // GIR_Coverage, 1979,
     992             :           GIR_Done,
     993             :         // Label 56: @1927
     994             :         GIM_Try, /*On fail goto*//*Label 57*/ 2028, // Rule ID 1980 //
     995             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
     996             :           GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     997             :           GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
     998             :           GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     999             :           GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
    1000             :           GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
    1001             :           GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
    1002             :           GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
    1003             :           GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
    1004             :           GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
    1005             :           GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
    1006             :           // MIs[3] z
    1007             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
    1008             :           // MIs[3] x
    1009             :           GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
    1010             :           GIM_CheckIsSafeToFold, /*InsnID*/1,
    1011             :           GIM_CheckIsSafeToFold, /*InsnID*/2,
    1012             :           GIM_CheckIsSafeToFold, /*InsnID*/3,
    1013             :           // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))  =>  (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
    1014             :           GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
    1015             :           GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
    1016             :           GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    1017             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
    1018             :           GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
    1019             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    1020             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
    1021             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    1022             :           GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    1023             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
    1024             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
    1025             :           GIR_EraseFromParent, /*InsnID*/0,
    1026             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1027             :           // GIR_Coverage, 1980,
    1028             :           GIR_Done,
    1029             :         // Label 57: @2028
    1030             :         GIM_Try, /*On fail goto*//*Label 58*/ 2061, // Rule ID 1914 //
    1031             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1032             :           GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
    1033             :           GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
    1034             :           // (or:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    1035             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
    1036             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    1037             :           GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    1038             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    1039             :           GIR_EraseFromParent, /*InsnID*/0,
    1040             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1041             :           // GIR_Coverage, 1914,
    1042             :           GIR_Done,
    1043             :         // Label 58: @2061
    1044             :         GIM_Try, /*On fail goto*//*Label 59*/ 2094, // Rule ID 2656 //
    1045             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1046             :           GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
    1047             :           GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
    1048             :           // (or:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_OR_B32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    1049             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e32,
    1050             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    1051             :           GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    1052             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
    1053             :           GIR_EraseFromParent, /*InsnID*/0,
    1054             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1055             :           // GIR_Coverage, 2656,
    1056             :           GIR_Done,
    1057             :         // Label 59: @2094
    1058             :         GIM_Reject,
    1059             :       // Label 41: @2095
    1060             :       GIM_Try, /*On fail goto*//*Label 60*/ 2121, // Rule ID 1913 //
    1061             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1062             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1063             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1064             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
    1065             :         // (or:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    1066             :         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_OR_B32,
    1067             :         GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
    1068             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1069             :         // GIR_Coverage, 1913,
    1070             :         GIR_Done,
    1071             :       // Label 60: @2121
    1072             :       GIM_Try, /*On fail goto*//*Label 61*/ 2139, // Rule ID 413 //
    1073             :         GIM_CheckFeatures, GIFBS_isGCN,
    1074             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    1075             :         // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    1076             :         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e64,
    1077             :         GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
    1078             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1079             :         // GIR_Coverage, 413,
    1080             :         GIR_Done,
    1081             :       // Label 61: @2139
    1082             :       GIM_Reject,
    1083             :     // Label 40: @2140
    1084             :     GIM_Reject,
    1085             :     // Label 5: @2141
    1086             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 64*/ 2244,
    1087             :     /*GILLT_s32*//*Label 62*/ 2149,
    1088             :     /*GILLT_s64*//*Label 63*/ 2207,
    1089             :     // Label 62: @2149
    1090             :     GIM_Try, /*On fail goto*//*Label 65*/ 2206,
    1091             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1092             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    1093             :       GIM_Try, /*On fail goto*//*Label 66*/ 2187, // Rule ID 0 //
    1094             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1095             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1096             :         GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
    1097             :         // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })  =>  (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
    1098             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B32,
    1099             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    1100             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1101             :         GIR_EraseFromParent, /*InsnID*/0,
    1102             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1103             :         // GIR_Coverage, 0,
    1104             :         GIR_Done,
    1105             :       // Label 66: @2187
    1106             :       GIM_Try, /*On fail goto*//*Label 67*/ 2205, // Rule ID 415 //
    1107             :         GIM_CheckFeatures, GIFBS_isGCN,
    1108             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    1109             :         // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    1110             :         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_XOR_B32_e64,
    1111             :         GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
    1112             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1113             :         // GIR_Coverage, 415,
    1114             :         GIR_Done,
    1115             :       // Label 67: @2205
    1116             :       GIM_Reject,
    1117             :     // Label 65: @2206
    1118             :     GIM_Reject,
    1119             :     // Label 63: @2207
    1120             :     GIM_Try, /*On fail goto*//*Label 68*/ 2243, // Rule ID 1 //
    1121             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1122             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1123             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    1124             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    1125             :       GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
    1126             :       // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })  =>  (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
    1127             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_NOT_B64,
    1128             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    1129             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1130             :       GIR_EraseFromParent, /*InsnID*/0,
    1131             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    1132             :       // GIR_Coverage, 1,
    1133             :       GIR_Done,
    1134             :     // Label 68: @2243
    1135             :     GIM_Reject,
    1136             :     // Label 64: @2244
    1137             :     GIM_Reject,
    1138             :     // Label 6: @2245
    1139             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 79*/ 4386,
    1140             :     /*GILLT_s16*//*Label 69*/ 2261,
    1141             :     /*GILLT_s32*//*Label 70*/ 2389,
    1142             :     /*GILLT_s64*//*Label 71*/ 2662,
    1143             :     /*GILLT_v2s16*//*Label 72*/ 3003,
    1144             :     /*GILLT_v2s32*//*Label 73*/ 3208,
    1145             :     /*GILLT_v2s64*//*Label 74*/ 3583,
    1146             :     /*GILLT_v4s16*//*Label 75*/ 3754,
    1147             :     /*GILLT_v4s32*//*Label 76*/ 4027,
    1148             :     /*GILLT_v8s32*//*Label 77*/ 4198,
    1149             :     /*GILLT_v16s32*//*Label 78*/ 4326,
    1150             :     // Label 69: @2261
    1151             :     GIM_Try, /*On fail goto*//*Label 80*/ 2388,
    1152             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    1153             :       GIM_Try, /*On fail goto*//*Label 81*/ 2297, // Rule ID 1599 //
    1154             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1155             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    1156             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
    1157             :         // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
    1158             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1159             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1160             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1161             :         GIR_EraseFromParent, /*InsnID*/0,
    1162             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
    1163             :         // GIR_Coverage, 1599,
    1164             :         GIR_Done,
    1165             :       // Label 81: @2297
    1166             :       GIM_Try, /*On fail goto*//*Label 82*/ 2327, // Rule ID 1600 //
    1167             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1168             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    1169             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
    1170             :         // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
    1171             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1172             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1173             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1174             :         GIR_EraseFromParent, /*InsnID*/0,
    1175             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
    1176             :         // GIR_Coverage, 1600,
    1177             :         GIR_Done,
    1178             :       // Label 82: @2327
    1179             :       GIM_Try, /*On fail goto*//*Label 83*/ 2357, // Rule ID 1601 //
    1180             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1181             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1182             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1183             :         // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
    1184             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1185             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1186             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1187             :         GIR_EraseFromParent, /*InsnID*/0,
    1188             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1189             :         // GIR_Coverage, 1601,
    1190             :         GIR_Done,
    1191             :       // Label 83: @2357
    1192             :       GIM_Try, /*On fail goto*//*Label 84*/ 2387, // Rule ID 1602 //
    1193             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1194             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1195             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1196             :         // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
    1197             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1198             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1199             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1200             :         GIR_EraseFromParent, /*InsnID*/0,
    1201             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1202             :         // GIR_Coverage, 1602,
    1203             :         GIR_Done,
    1204             :       // Label 84: @2387
    1205             :       GIM_Reject,
    1206             :     // Label 80: @2388
    1207             :     GIM_Reject,
    1208             :     // Label 70: @2389
    1209             :     GIM_Try, /*On fail goto*//*Label 85*/ 2423, // Rule ID 1603 //
    1210             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1211             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1212             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    1213             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
    1214             :       // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
    1215             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1216             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1217             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1218             :       GIR_EraseFromParent, /*InsnID*/0,
    1219             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
    1220             :       // GIR_Coverage, 1603,
    1221             :       GIR_Done,
    1222             :     // Label 85: @2423
    1223             :     GIM_Try, /*On fail goto*//*Label 86*/ 2457, // Rule ID 1604 //
    1224             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1225             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1226             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    1227             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
    1228             :       // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
    1229             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1230             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1231             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1232             :       GIR_EraseFromParent, /*InsnID*/0,
    1233             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VGPR_32*/2,
    1234             :       // GIR_Coverage, 1604,
    1235             :       GIR_Done,
    1236             :     // Label 86: @2457
    1237             :     GIM_Try, /*On fail goto*//*Label 87*/ 2491, // Rule ID 1605 //
    1238             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1239             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1240             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1241             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1242             :       // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
    1243             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1244             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1245             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1246             :       GIR_EraseFromParent, /*InsnID*/0,
    1247             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1248             :       // GIR_Coverage, 1605,
    1249             :       GIR_Done,
    1250             :     // Label 87: @2491
    1251             :     GIM_Try, /*On fail goto*//*Label 88*/ 2525, // Rule ID 1606 //
    1252             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1253             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1254             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1255             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1256             :       // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
    1257             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1258             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1259             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1260             :       GIR_EraseFromParent, /*InsnID*/0,
    1261             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1262             :       // GIR_Coverage, 1606,
    1263             :       GIR_Done,
    1264             :     // Label 88: @2525
    1265             :     GIM_Try, /*On fail goto*//*Label 89*/ 2559, // Rule ID 1608 //
    1266             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1267             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
    1268             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1269             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1270             :       // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
    1271             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1272             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1273             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1274             :       GIR_EraseFromParent, /*InsnID*/0,
    1275             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1276             :       // GIR_Coverage, 1608,
    1277             :       GIR_Done,
    1278             :     // Label 89: @2559
    1279             :     GIM_Try, /*On fail goto*//*Label 90*/ 2593, // Rule ID 1610 //
    1280             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1281             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
    1282             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1283             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1284             :       // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
    1285             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1286             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1287             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1288             :       GIR_EraseFromParent, /*InsnID*/0,
    1289             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1290             :       // GIR_Coverage, 1610,
    1291             :       GIR_Done,
    1292             :     // Label 90: @2593
    1293             :     GIM_Try, /*On fail goto*//*Label 91*/ 2627, // Rule ID 1614 //
    1294             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1295             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
    1296             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1297             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1298             :       // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
    1299             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1300             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1301             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1302             :       GIR_EraseFromParent, /*InsnID*/0,
    1303             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1304             :       // GIR_Coverage, 1614,
    1305             :       GIR_Done,
    1306             :     // Label 91: @2627
    1307             :     GIM_Try, /*On fail goto*//*Label 92*/ 2661, // Rule ID 1616 //
    1308             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1309             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
    1310             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1311             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1312             :       // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
    1313             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1314             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1315             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1316             :       GIR_EraseFromParent, /*InsnID*/0,
    1317             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1318             :       // GIR_Coverage, 1616,
    1319             :       GIR_Done,
    1320             :     // Label 92: @2661
    1321             :     GIM_Reject,
    1322             :     // Label 71: @2662
    1323             :     GIM_Try, /*On fail goto*//*Label 93*/ 2696, // Rule ID 1617 //
    1324             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1325             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1326             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1327             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1328             :       // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
    1329             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1330             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1331             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1332             :       GIR_EraseFromParent, /*InsnID*/0,
    1333             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1334             :       // GIR_Coverage, 1617,
    1335             :       GIR_Done,
    1336             :     // Label 93: @2696
    1337             :     GIM_Try, /*On fail goto*//*Label 94*/ 2730, // Rule ID 1618 //
    1338             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1339             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1340             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1341             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1342             :       // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
    1343             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1344             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1345             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1346             :       GIR_EraseFromParent, /*InsnID*/0,
    1347             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1348             :       // GIR_Coverage, 1618,
    1349             :       GIR_Done,
    1350             :     // Label 94: @2730
    1351             :     GIM_Try, /*On fail goto*//*Label 95*/ 2764, // Rule ID 1621 //
    1352             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1353             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1354             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1355             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1356             :       // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
    1357             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1358             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1359             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1360             :       GIR_EraseFromParent, /*InsnID*/0,
    1361             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1362             :       // GIR_Coverage, 1621,
    1363             :       GIR_Done,
    1364             :     // Label 95: @2764
    1365             :     GIM_Try, /*On fail goto*//*Label 96*/ 2798, // Rule ID 1623 //
    1366             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1367             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1368             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1369             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1370             :       // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
    1371             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1372             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1373             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1374             :       GIR_EraseFromParent, /*InsnID*/0,
    1375             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1376             :       // GIR_Coverage, 1623,
    1377             :       GIR_Done,
    1378             :     // Label 96: @2798
    1379             :     GIM_Try, /*On fail goto*//*Label 97*/ 2832, // Rule ID 1625 //
    1380             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1381             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1382             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1383             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1384             :       // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
    1385             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1386             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1387             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1388             :       GIR_EraseFromParent, /*InsnID*/0,
    1389             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1390             :       // GIR_Coverage, 1625,
    1391             :       GIR_Done,
    1392             :     // Label 97: @2832
    1393             :     GIM_Try, /*On fail goto*//*Label 98*/ 2866, // Rule ID 1627 //
    1394             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1395             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1396             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1397             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1398             :       // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
    1399             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1400             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1401             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1402             :       GIR_EraseFromParent, /*InsnID*/0,
    1403             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1404             :       // GIR_Coverage, 1627,
    1405             :       GIR_Done,
    1406             :     // Label 98: @2866
    1407             :     GIM_Try, /*On fail goto*//*Label 99*/ 2900, // Rule ID 1640 //
    1408             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1409             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1410             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1411             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1412             :       // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
    1413             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1414             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1415             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1416             :       GIR_EraseFromParent, /*InsnID*/0,
    1417             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1418             :       // GIR_Coverage, 1640,
    1419             :       GIR_Done,
    1420             :     // Label 99: @2900
    1421             :     GIM_Try, /*On fail goto*//*Label 100*/ 2934, // Rule ID 1641 //
    1422             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1423             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1424             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1425             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1426             :       // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
    1427             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1428             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1429             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1430             :       GIR_EraseFromParent, /*InsnID*/0,
    1431             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1432             :       // GIR_Coverage, 1641,
    1433             :       GIR_Done,
    1434             :     // Label 100: @2934
    1435             :     GIM_Try, /*On fail goto*//*Label 101*/ 2968, // Rule ID 1644 //
    1436             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1437             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1438             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1439             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1440             :       // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
    1441             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1442             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1443             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1444             :       GIR_EraseFromParent, /*InsnID*/0,
    1445             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1446             :       // GIR_Coverage, 1644,
    1447             :       GIR_Done,
    1448             :     // Label 101: @2968
    1449             :     GIM_Try, /*On fail goto*//*Label 102*/ 3002, // Rule ID 1645 //
    1450             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1451             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1452             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1453             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1454             :       // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
    1455             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1456             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1457             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1458             :       GIR_EraseFromParent, /*InsnID*/0,
    1459             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1460             :       // GIR_Coverage, 1645,
    1461             :       GIR_Done,
    1462             :     // Label 102: @3002
    1463             :     GIM_Reject,
    1464             :     // Label 72: @3003
    1465             :     GIM_Try, /*On fail goto*//*Label 103*/ 3037, // Rule ID 1607 //
    1466             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1467             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1468             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1469             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1470             :       // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
    1471             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1472             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1473             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1474             :       GIR_EraseFromParent, /*InsnID*/0,
    1475             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1476             :       // GIR_Coverage, 1607,
    1477             :       GIR_Done,
    1478             :     // Label 103: @3037
    1479             :     GIM_Try, /*On fail goto*//*Label 104*/ 3071, // Rule ID 1609 //
    1480             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1481             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1482             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1483             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1484             :       // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
    1485             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1486             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1487             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1488             :       GIR_EraseFromParent, /*InsnID*/0,
    1489             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1490             :       // GIR_Coverage, 1609,
    1491             :       GIR_Done,
    1492             :     // Label 104: @3071
    1493             :     GIM_Try, /*On fail goto*//*Label 105*/ 3105, // Rule ID 1611 //
    1494             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1495             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
    1496             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1497             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1498             :       // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
    1499             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1500             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1501             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1502             :       GIR_EraseFromParent, /*InsnID*/0,
    1503             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1504             :       // GIR_Coverage, 1611,
    1505             :       GIR_Done,
    1506             :     // Label 105: @3105
    1507             :     GIM_Try, /*On fail goto*//*Label 106*/ 3139, // Rule ID 1612 //
    1508             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1509             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
    1510             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1511             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1512             :       // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
    1513             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1514             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1515             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1516             :       GIR_EraseFromParent, /*InsnID*/0,
    1517             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1518             :       // GIR_Coverage, 1612,
    1519             :       GIR_Done,
    1520             :     // Label 106: @3139
    1521             :     GIM_Try, /*On fail goto*//*Label 107*/ 3173, // Rule ID 1613 //
    1522             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1523             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1524             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1525             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1526             :       // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
    1527             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1528             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1529             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1530             :       GIR_EraseFromParent, /*InsnID*/0,
    1531             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1532             :       // GIR_Coverage, 1613,
    1533             :       GIR_Done,
    1534             :     // Label 107: @3173
    1535             :     GIM_Try, /*On fail goto*//*Label 108*/ 3207, // Rule ID 1615 //
    1536             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1537             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    1538             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    1539             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    1540             :       // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
    1541             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1542             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1543             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1544             :       GIR_EraseFromParent, /*InsnID*/0,
    1545             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_32*/4,
    1546             :       // GIR_Coverage, 1615,
    1547             :       GIR_Done,
    1548             :     // Label 108: @3207
    1549             :     GIM_Reject,
    1550             :     // Label 73: @3208
    1551             :     GIM_Try, /*On fail goto*//*Label 109*/ 3242, // Rule ID 1619 //
    1552             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1553             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1554             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1555             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1556             :       // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
    1557             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1558             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1559             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1560             :       GIR_EraseFromParent, /*InsnID*/0,
    1561             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1562             :       // GIR_Coverage, 1619,
    1563             :       GIR_Done,
    1564             :     // Label 109: @3242
    1565             :     GIM_Try, /*On fail goto*//*Label 110*/ 3276, // Rule ID 1620 //
    1566             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1567             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1568             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1569             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1570             :       // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
    1571             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1572             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1573             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1574             :       GIR_EraseFromParent, /*InsnID*/0,
    1575             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1576             :       // GIR_Coverage, 1620,
    1577             :       GIR_Done,
    1578             :     // Label 110: @3276
    1579             :     GIM_Try, /*On fail goto*//*Label 111*/ 3310, // Rule ID 1622 //
    1580             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1581             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1582             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1583             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1584             :       // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
    1585             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1586             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1587             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1588             :       GIR_EraseFromParent, /*InsnID*/0,
    1589             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1590             :       // GIR_Coverage, 1622,
    1591             :       GIR_Done,
    1592             :     // Label 111: @3310
    1593             :     GIM_Try, /*On fail goto*//*Label 112*/ 3344, // Rule ID 1624 //
    1594             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1595             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1596             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1597             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1598             :       // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
    1599             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1600             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1601             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1602             :       GIR_EraseFromParent, /*InsnID*/0,
    1603             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1604             :       // GIR_Coverage, 1624,
    1605             :       GIR_Done,
    1606             :     // Label 112: @3344
    1607             :     GIM_Try, /*On fail goto*//*Label 113*/ 3378, // Rule ID 1626 //
    1608             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1609             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1610             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1611             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1612             :       // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
    1613             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1614             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1615             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1616             :       GIR_EraseFromParent, /*InsnID*/0,
    1617             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1618             :       // GIR_Coverage, 1626,
    1619             :       GIR_Done,
    1620             :     // Label 113: @3378
    1621             :     GIM_Try, /*On fail goto*//*Label 114*/ 3412, // Rule ID 1628 //
    1622             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1623             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1624             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1625             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1626             :       // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
    1627             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1628             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1629             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1630             :       GIR_EraseFromParent, /*InsnID*/0,
    1631             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1632             :       // GIR_Coverage, 1628,
    1633             :       GIR_Done,
    1634             :     // Label 114: @3412
    1635             :     GIM_Try, /*On fail goto*//*Label 115*/ 3446, // Rule ID 1629 //
    1636             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1637             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1638             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1639             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1640             :       // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
    1641             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1642             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1643             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1644             :       GIR_EraseFromParent, /*InsnID*/0,
    1645             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1646             :       // GIR_Coverage, 1629,
    1647             :       GIR_Done,
    1648             :     // Label 115: @3446
    1649             :     GIM_Try, /*On fail goto*//*Label 116*/ 3480, // Rule ID 1631 //
    1650             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1651             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1652             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1653             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1654             :       // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
    1655             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1656             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1657             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1658             :       GIR_EraseFromParent, /*InsnID*/0,
    1659             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1660             :       // GIR_Coverage, 1631,
    1661             :       GIR_Done,
    1662             :     // Label 116: @3480
    1663             :     GIM_Try, /*On fail goto*//*Label 117*/ 3514, // Rule ID 1632 //
    1664             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1665             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1666             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1667             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1668             :       // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
    1669             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1670             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1671             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1672             :       GIR_EraseFromParent, /*InsnID*/0,
    1673             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1674             :       // GIR_Coverage, 1632,
    1675             :       GIR_Done,
    1676             :     // Label 117: @3514
    1677             :     GIM_Try, /*On fail goto*//*Label 118*/ 3548, // Rule ID 1634 //
    1678             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1679             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1680             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1681             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1682             :       // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
    1683             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1684             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1685             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1686             :       GIR_EraseFromParent, /*InsnID*/0,
    1687             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1688             :       // GIR_Coverage, 1634,
    1689             :       GIR_Done,
    1690             :     // Label 118: @3548
    1691             :     GIM_Try, /*On fail goto*//*Label 119*/ 3582, // Rule ID 1636 //
    1692             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1693             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
    1694             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1695             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1696             :       // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
    1697             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1698             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1699             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1700             :       GIR_EraseFromParent, /*InsnID*/0,
    1701             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1702             :       // GIR_Coverage, 1636,
    1703             :       GIR_Done,
    1704             :     // Label 119: @3582
    1705             :     GIM_Reject,
    1706             :     // Label 74: @3583
    1707             :     GIM_Try, /*On fail goto*//*Label 120*/ 3617, // Rule ID 1648 //
    1708             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1709             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    1710             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
    1711             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
    1712             :       // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
    1713             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1714             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1715             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1716             :       GIR_EraseFromParent, /*InsnID*/0,
    1717             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
    1718             :       // GIR_Coverage, 1648,
    1719             :       GIR_Done,
    1720             :     // Label 120: @3617
    1721             :     GIM_Try, /*On fail goto*//*Label 121*/ 3651, // Rule ID 1650 //
    1722             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1723             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    1724             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1725             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1726             :       // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
    1727             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1728             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1729             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1730             :       GIR_EraseFromParent, /*InsnID*/0,
    1731             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1732             :       // GIR_Coverage, 1650,
    1733             :       GIR_Done,
    1734             :     // Label 121: @3651
    1735             :     GIM_Try, /*On fail goto*//*Label 122*/ 3685, // Rule ID 1651 //
    1736             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1737             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    1738             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1739             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1740             :       // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
    1741             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1742             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1743             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1744             :       GIR_EraseFromParent, /*InsnID*/0,
    1745             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1746             :       // GIR_Coverage, 1651,
    1747             :       GIR_Done,
    1748             :     // Label 122: @3685
    1749             :     GIM_Try, /*On fail goto*//*Label 123*/ 3719, // Rule ID 1654 //
    1750             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1751             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    1752             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1753             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1754             :       // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
    1755             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1756             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1757             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1758             :       GIR_EraseFromParent, /*InsnID*/0,
    1759             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1760             :       // GIR_Coverage, 1654,
    1761             :       GIR_Done,
    1762             :     // Label 123: @3719
    1763             :     GIM_Try, /*On fail goto*//*Label 124*/ 3753, // Rule ID 1655 //
    1764             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1765             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    1766             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1767             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1768             :       // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
    1769             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1770             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1771             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1772             :       GIR_EraseFromParent, /*InsnID*/0,
    1773             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1774             :       // GIR_Coverage, 1655,
    1775             :       GIR_Done,
    1776             :     // Label 124: @3753
    1777             :     GIM_Reject,
    1778             :     // Label 75: @3754
    1779             :     GIM_Try, /*On fail goto*//*Label 125*/ 3788, // Rule ID 1630 //
    1780             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1781             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1782             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1783             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1784             :       // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
    1785             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1786             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1787             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1788             :       GIR_EraseFromParent, /*InsnID*/0,
    1789             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1790             :       // GIR_Coverage, 1630,
    1791             :       GIR_Done,
    1792             :     // Label 125: @3788
    1793             :     GIM_Try, /*On fail goto*//*Label 126*/ 3822, // Rule ID 1633 //
    1794             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1795             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1796             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1797             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1798             :       // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
    1799             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1800             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1801             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1802             :       GIR_EraseFromParent, /*InsnID*/0,
    1803             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1804             :       // GIR_Coverage, 1633,
    1805             :       GIR_Done,
    1806             :     // Label 126: @3822
    1807             :     GIM_Try, /*On fail goto*//*Label 127*/ 3856, // Rule ID 1635 //
    1808             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1809             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1810             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1811             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1812             :       // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
    1813             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1814             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1815             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1816             :       GIR_EraseFromParent, /*InsnID*/0,
    1817             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1818             :       // GIR_Coverage, 1635,
    1819             :       GIR_Done,
    1820             :     // Label 127: @3856
    1821             :     GIM_Try, /*On fail goto*//*Label 128*/ 3890, // Rule ID 1637 //
    1822             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1823             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
    1824             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1825             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1826             :       // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
    1827             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1828             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1829             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1830             :       GIR_EraseFromParent, /*InsnID*/0,
    1831             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1832             :       // GIR_Coverage, 1637,
    1833             :       GIR_Done,
    1834             :     // Label 128: @3890
    1835             :     GIM_Try, /*On fail goto*//*Label 129*/ 3924, // Rule ID 1638 //
    1836             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1837             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1838             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1839             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1840             :       // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
    1841             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1842             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1843             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1844             :       GIR_EraseFromParent, /*InsnID*/0,
    1845             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1846             :       // GIR_Coverage, 1638,
    1847             :       GIR_Done,
    1848             :     // Label 129: @3924
    1849             :     GIM_Try, /*On fail goto*//*Label 130*/ 3958, // Rule ID 1639 //
    1850             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1851             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1852             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1853             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1854             :       // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
    1855             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1856             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1857             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1858             :       GIR_EraseFromParent, /*InsnID*/0,
    1859             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1860             :       // GIR_Coverage, 1639,
    1861             :       GIR_Done,
    1862             :     // Label 130: @3958
    1863             :     GIM_Try, /*On fail goto*//*Label 131*/ 3992, // Rule ID 1642 //
    1864             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1865             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1866             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1867             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1868             :       // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
    1869             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1870             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1871             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1872             :       GIR_EraseFromParent, /*InsnID*/0,
    1873             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1874             :       // GIR_Coverage, 1642,
    1875             :       GIR_Done,
    1876             :     // Label 131: @3992
    1877             :     GIM_Try, /*On fail goto*//*Label 132*/ 4026, // Rule ID 1643 //
    1878             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1879             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    1880             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    1881             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_64RegClassID,
    1882             :       // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
    1883             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1884             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1885             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1886             :       GIR_EraseFromParent, /*InsnID*/0,
    1887             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_64*/14,
    1888             :       // GIR_Coverage, 1643,
    1889             :       GIR_Done,
    1890             :     // Label 132: @4026
    1891             :     GIM_Reject,
    1892             :     // Label 76: @4027
    1893             :     GIM_Try, /*On fail goto*//*Label 133*/ 4061, // Rule ID 1646 //
    1894             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1895             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    1896             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1897             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1898             :       // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
    1899             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1900             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1901             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1902             :       GIR_EraseFromParent, /*InsnID*/0,
    1903             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1904             :       // GIR_Coverage, 1646,
    1905             :       GIR_Done,
    1906             :     // Label 133: @4061
    1907             :     GIM_Try, /*On fail goto*//*Label 134*/ 4095, // Rule ID 1647 //
    1908             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1909             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
    1910             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1911             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1912             :       // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
    1913             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1914             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1915             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1916             :       GIR_EraseFromParent, /*InsnID*/0,
    1917             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1918             :       // GIR_Coverage, 1647,
    1919             :       GIR_Done,
    1920             :     // Label 134: @4095
    1921             :     GIM_Try, /*On fail goto*//*Label 135*/ 4129, // Rule ID 1649 //
    1922             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1923             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    1924             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_128RegClassID,
    1925             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_128RegClassID,
    1926             :       // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
    1927             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1928             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1929             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1930             :       GIR_EraseFromParent, /*InsnID*/0,
    1931             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_128*/21,
    1932             :       // GIR_Coverage, 1649,
    1933             :       GIR_Done,
    1934             :     // Label 135: @4129
    1935             :     GIM_Try, /*On fail goto*//*Label 136*/ 4163, // Rule ID 1652 //
    1936             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1937             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    1938             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1939             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1940             :       // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
    1941             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1942             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1943             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1944             :       GIR_EraseFromParent, /*InsnID*/0,
    1945             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1946             :       // GIR_Coverage, 1652,
    1947             :       GIR_Done,
    1948             :     // Label 136: @4163
    1949             :     GIM_Try, /*On fail goto*//*Label 137*/ 4197, // Rule ID 1653 //
    1950             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1951             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
    1952             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    1953             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_128RegClassID,
    1954             :       // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
    1955             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1956             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1957             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1958             :       GIR_EraseFromParent, /*InsnID*/0,
    1959             :       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_128*/20,
    1960             :       // GIR_Coverage, 1653,
    1961             :       GIR_Done,
    1962             :     // Label 137: @4197
    1963             :     GIM_Reject,
    1964             :     // Label 77: @4198
    1965             :     GIM_Try, /*On fail goto*//*Label 138*/ 4325,
    1966             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
    1967             :       GIM_Try, /*On fail goto*//*Label 139*/ 4234, // Rule ID 1656 //
    1968             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1969             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
    1970             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
    1971             :         // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
    1972             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1973             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1974             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1975             :         GIR_EraseFromParent, /*InsnID*/0,
    1976             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
    1977             :         // GIR_Coverage, 1656,
    1978             :         GIR_Done,
    1979             :       // Label 139: @4234
    1980             :       GIM_Try, /*On fail goto*//*Label 140*/ 4264, // Rule ID 1657 //
    1981             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1982             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_256RegClassID,
    1983             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_256RegClassID,
    1984             :         // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
    1985             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1986             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    1987             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    1988             :         GIR_EraseFromParent, /*InsnID*/0,
    1989             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SReg_256*/26,
    1990             :         // GIR_Coverage, 1657,
    1991             :         GIR_Done,
    1992             :       // Label 140: @4264
    1993             :       GIM_Try, /*On fail goto*//*Label 141*/ 4294, // Rule ID 1658 //
    1994             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    1995             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
    1996             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
    1997             :         // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
    1998             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    1999             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2000             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    2001             :         GIR_EraseFromParent, /*InsnID*/0,
    2002             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
    2003             :         // GIR_Coverage, 1658,
    2004             :         GIR_Done,
    2005             :       // Label 141: @4294
    2006             :       GIM_Try, /*On fail goto*//*Label 142*/ 4324, // Rule ID 1659 //
    2007             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2008             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_256RegClassID,
    2009             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_256RegClassID,
    2010             :         // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
    2011             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    2012             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2013             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    2014             :         GIR_EraseFromParent, /*InsnID*/0,
    2015             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_256*/25,
    2016             :         // GIR_Coverage, 1659,
    2017             :         GIR_Done,
    2018             :       // Label 142: @4324
    2019             :       GIM_Reject,
    2020             :     // Label 138: @4325
    2021             :     GIM_Reject,
    2022             :     // Label 78: @4326
    2023             :     GIM_Try, /*On fail goto*//*Label 143*/ 4385,
    2024             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
    2025             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_512RegClassID,
    2026             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VReg_512RegClassID,
    2027             :       GIM_Try, /*On fail goto*//*Label 144*/ 4362, // Rule ID 1660 //
    2028             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2029             :         // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
    2030             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    2031             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2032             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    2033             :         GIR_EraseFromParent, /*InsnID*/0,
    2034             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
    2035             :         // GIR_Coverage, 1660,
    2036             :         GIR_Done,
    2037             :       // Label 144: @4362
    2038             :       GIM_Try, /*On fail goto*//*Label 145*/ 4384, // Rule ID 1661 //
    2039             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2040             :         // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
    2041             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
    2042             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2043             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
    2044             :         GIR_EraseFromParent, /*InsnID*/0,
    2045             :         GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VReg_512*/29,
    2046             :         // GIR_Coverage, 1661,
    2047             :         GIR_Done,
    2048             :       // Label 145: @4384
    2049             :       GIM_Reject,
    2050             :     // Label 143: @4385
    2051             :     GIM_Reject,
    2052             :     // Label 79: @4386
    2053             :     GIM_Reject,
    2054             :     // Label 7: @4387
    2055             :     GIM_Try, /*On fail goto*//*Label 146*/ 4477,
    2056             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    2057             :       GIM_Try, /*On fail goto*//*Label 147*/ 4420, // Rule ID 10 //
    2058             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2059             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_getpc,
    2060             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2061             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    2062             :         // (intrinsic_wo_chain:{ *:[i64] } 951:{ *:[iPTR] })  =>  (S_GETPC_B64:{ *:[i64] })
    2063             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_GETPC_B64,
    2064             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    2065             :         GIR_EraseFromParent, /*InsnID*/0,
    2066             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2067             :         // GIR_Coverage, 10,
    2068             :         GIR_Done,
    2069             :       // Label 147: @4420
    2070             :       GIM_Try, /*On fail goto*//*Label 148*/ 4448, // Rule ID 655 //
    2071             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2072             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_groupstaticsize,
    2073             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2074             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    2075             :         // (intrinsic_wo_chain:{ *:[i32] } 436:{ *:[iPTR] })  =>  (GET_GROUPSTATICSIZE:{ *:[i32] })
    2076             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::GET_GROUPSTATICSIZE,
    2077             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    2078             :         GIR_EraseFromParent, /*InsnID*/0,
    2079             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2080             :         // GIR_Coverage, 655,
    2081             :         GIR_Done,
    2082             :       // Label 148: @4448
    2083             :       GIM_Try, /*On fail goto*//*Label 149*/ 4476, // Rule ID 664 //
    2084             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2085             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_ps_live,
    2086             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
    2087             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    2088             :         // (intrinsic_wo_chain:{ *:[i1] } 917:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
    2089             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_PS_LIVE,
    2090             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2091             :         GIR_EraseFromParent, /*InsnID*/0,
    2092             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2093             :         // GIR_Coverage, 664,
    2094             :         GIR_Done,
    2095             :       // Label 149: @4476
    2096             :       GIM_Reject,
    2097             :     // Label 146: @4477
    2098             :     GIM_Try, /*On fail goto*//*Label 150*/ 4948,
    2099             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
    2100             :       GIM_Try, /*On fail goto*//*Label 151*/ 4518, // Rule ID 2 //
    2101             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2102             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_wqm_vote,
    2103             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
    2104             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
    2105             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    2106             :         // (intrinsic_wo_chain:{ *:[i1] } 1004:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B64:{ *:[i1] }:{ *:[i1] } i1:{ *:[i1] }:$src0)
    2107             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_WQM_B64,
    2108             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    2109             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2110             :         GIR_EraseFromParent, /*InsnID*/0,
    2111             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2112             :         // GIR_Coverage, 2,
    2113             :         GIR_Done,
    2114             :       // Label 151: @4518
    2115             :       GIM_Try, /*On fail goto*//*Label 152*/ 4554, // Rule ID 321 //
    2116             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2117             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readfirstlane,
    2118             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2119             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2120             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    2121             :         // (intrinsic_wo_chain:{ *:[i32] } 939:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
    2122             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READFIRSTLANE_B32,
    2123             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2124             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2125             :         GIR_EraseFromParent, /*InsnID*/0,
    2126             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2127             :         // GIR_Coverage, 321,
    2128             :         GIR_Done,
    2129             :       // Label 152: @4554
    2130             :       GIM_Try, /*On fail goto*//*Label 153*/ 4590, // Rule ID 661 //
    2131             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2132             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_break,
    2133             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2134             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2135             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    2136             :         // (intrinsic_wo_chain:{ *:[i64] } 380:{ *:[iPTR] }, i64:{ *:[i64] }:$src)  =>  (SI_BREAK:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src)
    2137             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_BREAK,
    2138             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2139             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
    2140             :         GIR_EraseFromParent, /*InsnID*/0,
    2141             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2142             :         // GIR_Coverage, 661,
    2143             :         GIR_Done,
    2144             :       // Label 153: @4590
    2145             :       GIM_Try, /*On fail goto*//*Label 154*/ 4641, // Rule ID 356 //
    2146             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
    2147             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2148             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2149             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2150             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2151             :         // (intrinsic_wo_chain:{ *:[i32] } 434:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2152             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F64_e64,
    2153             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2154             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2155             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2156             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2157             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2158             :         GIR_EraseFromParent, /*InsnID*/0,
    2159             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2160             :         // GIR_Coverage, 356,
    2161             :         GIR_Done,
    2162             :       // Label 154: @4641
    2163             :       GIM_Try, /*On fail goto*//*Label 155*/ 4692, // Rule ID 357 //
    2164             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
    2165             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2166             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2167             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2168             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2169             :         // (intrinsic_wo_chain:{ *:[f64] } 435:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2170             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F64_e64,
    2171             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2172             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2173             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2174             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2175             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2176             :         GIR_EraseFromParent, /*InsnID*/0,
    2177             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2178             :         // GIR_Coverage, 357,
    2179             :         GIR_Done,
    2180             :       // Label 155: @4692
    2181             :       GIM_Try, /*On fail goto*//*Label 156*/ 4743, // Rule ID 359 //
    2182             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
    2183             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2184             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2185             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2186             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2187             :         // (intrinsic_wo_chain:{ *:[i32] } 434:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2188             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I32_F32_e64,
    2189             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2190             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2191             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2192             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2193             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2194             :         GIR_EraseFromParent, /*InsnID*/0,
    2195             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2196             :         // GIR_Coverage, 359,
    2197             :         GIR_Done,
    2198             :       // Label 156: @4743
    2199             :       GIM_Try, /*On fail goto*//*Label 157*/ 4794, // Rule ID 360 //
    2200             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
    2201             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2202             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2203             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2204             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2205             :         // (intrinsic_wo_chain:{ *:[f32] } 435:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2206             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F32_e64,
    2207             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2208             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2209             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2210             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2211             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2212             :         GIR_EraseFromParent, /*InsnID*/0,
    2213             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2214             :         // GIR_Coverage, 360,
    2215             :         GIR_Done,
    2216             :       // Label 157: @4794
    2217             :       GIM_Try, /*On fail goto*//*Label 158*/ 4845, // Rule ID 361 //
    2218             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_log_clamp,
    2219             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2220             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2221             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2222             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2223             :         // (intrinsic_wo_chain:{ *:[f32] } 909:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2224             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_CLAMP_F32_e64,
    2225             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2226             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2227             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2228             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2229             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2230             :         GIR_EraseFromParent, /*InsnID*/0,
    2231             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2232             :         // GIR_Coverage, 361,
    2233             :         GIR_Done,
    2234             :       // Label 158: @4845
    2235             :       GIM_Try, /*On fail goto*//*Label 159*/ 4896, // Rule ID 381 //
    2236             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_mant,
    2237             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    2238             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
    2239             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2240             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2241             :         // (intrinsic_wo_chain:{ *:[f16] } 435:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2242             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_MANT_F16_e64,
    2243             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2244             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2245             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2246             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2247             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2248             :         GIR_EraseFromParent, /*InsnID*/0,
    2249             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2250             :         // GIR_Coverage, 381,
    2251             :         GIR_Done,
    2252             :       // Label 159: @4896
    2253             :       GIM_Try, /*On fail goto*//*Label 160*/ 4947, // Rule ID 382 //
    2254             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_frexp_exp,
    2255             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
    2256             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
    2257             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2258             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2259             :         // (intrinsic_wo_chain:{ *:[i16] } 434:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2260             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FREXP_EXP_I16_F16_e64,
    2261             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2262             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2263             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2264             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2265             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2266             :         GIR_EraseFromParent, /*InsnID*/0,
    2267             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2268             :         // GIR_Coverage, 382,
    2269             :         GIR_Done,
    2270             :       // Label 160: @4947
    2271             :       GIM_Reject,
    2272             :     // Label 150: @4948
    2273             :     GIM_Try, /*On fail goto*//*Label 161*/ 5824,
    2274             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
    2275             :       GIM_Try, /*On fail goto*//*Label 162*/ 5023, // Rule ID 1919 //
    2276             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2277             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pkrtz,
    2278             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
    2279             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2280             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2281             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2282             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2283             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2284             :         // (intrinsic_wo_chain:{ *:[v2f16] } 410:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKRTZ_F16_F32_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
    2285             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PKRTZ_F16_F32_e64,
    2286             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2287             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2288             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2289             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2290             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2291             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2292             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
    2293             :         GIR_EraseFromParent, /*InsnID*/0,
    2294             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2295             :         // GIR_Coverage, 1919,
    2296             :         GIR_Done,
    2297             :       // Label 162: @5023
    2298             :       GIM_Try, /*On fail goto*//*Label 163*/ 5093, // Rule ID 1920 //
    2299             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2300             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
    2301             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2302             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2303             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2304             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2305             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2306             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2307             :         // (intrinsic_wo_chain:{ *:[f64] } 132:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
    2308             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
    2309             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2310             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2311             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2312             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2313             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2314             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2315             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
    2316             :         GIR_EraseFromParent, /*InsnID*/0,
    2317             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2318             :         // GIR_Coverage, 1920,
    2319             :         GIR_Done,
    2320             :       // Label 163: @5093
    2321             :       GIM_Try, /*On fail goto*//*Label 164*/ 5163, // Rule ID 1923 //
    2322             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2323             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
    2324             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2325             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2326             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2327             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2328             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2329             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2330             :         // (intrinsic_wo_chain:{ *:[f64] } 140:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
    2331             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
    2332             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2333             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2334             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2335             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2336             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2337             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2338             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omods
    2339             :         GIR_EraseFromParent, /*InsnID*/0,
    2340             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2341             :         // GIR_Coverage, 1923,
    2342             :         GIR_Done,
    2343             :       // Label 164: @5163
    2344             :       GIM_Try, /*On fail goto*//*Label 165*/ 5233, // Rule ID 2657 //
    2345             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2346             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
    2347             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2348             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2349             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2350             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2351             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
    2352             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
    2353             :         // (intrinsic_wo_chain:{ *:[f64] } 132:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MAX_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
    2354             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F64,
    2355             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2356             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    2357             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    2358             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    2359             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    2360             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    2361             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
    2362             :         GIR_EraseFromParent, /*InsnID*/0,
    2363             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2364             :         // GIR_Coverage, 2657,
    2365             :         GIR_Done,
    2366             :       // Label 165: @5233
    2367             :       GIM_Try, /*On fail goto*//*Label 166*/ 5303, // Rule ID 2658 //
    2368             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2369             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
    2370             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2371             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2372             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2373             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2374             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods,
    2375             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods0,
    2376             :         // (intrinsic_wo_chain:{ *:[f64] } 140:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omods))  =>  (V_MIN_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omods)
    2377             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F64,
    2378             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2379             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    2380             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    2381             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    2382             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    2383             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    2384             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omods
    2385             :         GIR_EraseFromParent, /*InsnID*/0,
    2386             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2387             :         // GIR_Coverage, 2658,
    2388             :         GIR_Done,
    2389             :       // Label 166: @5303
    2390             :       GIM_Try, /*On fail goto*//*Label 167*/ 5356, // Rule ID 1911 //
    2391             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2392             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
    2393             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2394             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2395             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2396             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2397             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
    2398             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
    2399             :         // (intrinsic_wo_chain:{ *:[f32] } 132:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
    2400             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
    2401             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2402             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2403             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2404             :         GIR_EraseFromParent, /*InsnID*/0,
    2405             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2406             :         // GIR_Coverage, 1911,
    2407             :         GIR_Done,
    2408             :       // Label 167: @5356
    2409             :       GIM_Try, /*On fail goto*//*Label 168*/ 5409, // Rule ID 1921 //
    2410             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2411             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
    2412             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2413             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2414             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2415             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2416             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/AMDGPU::VGPR_32RegClassID,
    2417             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
    2418             :         // (intrinsic_wo_chain:{ *:[f32] } 140:{ *:[iPTR] }, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0), VGPR_32:{ *:[f32] }:$src1)  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
    2419             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
    2420             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2421             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2422             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2423             :         GIR_EraseFromParent, /*InsnID*/0,
    2424             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2425             :         // GIR_Coverage, 1921,
    2426             :         GIR_Done,
    2427             :       // Label 168: @5409
    2428             :       GIM_Try, /*On fail goto*//*Label 169*/ 5462, // Rule ID 1912 //
    2429             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2430             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::maxnum,
    2431             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2432             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2433             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2434             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2435             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
    2436             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
    2437             :         // (intrinsic_wo_chain:{ *:[f32] } 132:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MAX_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
    2438             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAX_F32_e32,
    2439             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2440             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2441             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2442             :         GIR_EraseFromParent, /*InsnID*/0,
    2443             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2444             :         // GIR_Coverage, 1912,
    2445             :         GIR_Done,
    2446             :       // Label 169: @5462
    2447             :       GIM_Try, /*On fail goto*//*Label 170*/ 5515, // Rule ID 1922 //
    2448             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2449             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::minnum,
    2450             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2451             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2452             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2453             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2454             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
    2455             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/0, GICP_gi_vsrc0,
    2456             :         // (intrinsic_wo_chain:{ *:[f32] } 140:{ *:[iPTR] }, VGPR_32:{ *:[f32] }:$src1, (sd_vsrc0:{ *:[f32] } f32:{ *:[f32] }:$src0))  =>  (V_MIN_F32_e32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)
    2457             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MIN_F32_e32,
    2458             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2459             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2460             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    2461             :         GIR_EraseFromParent, /*InsnID*/0,
    2462             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2463             :         // GIR_Coverage, 1922,
    2464             :         GIR_Done,
    2465             :       // Label 170: @5515
    2466             :       GIM_Try, /*On fail goto*//*Label 171*/ 5559, // Rule ID 416 //
    2467             :         GIM_CheckFeatures, GIFBS_isGCN,
    2468             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_readlane,
    2469             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2470             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2471             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2472             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    2473             :         // (intrinsic_wo_chain:{ *:[i32] } 940:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    2474             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_READLANE_B32,
    2475             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2476             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2477             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2478             :         GIR_EraseFromParent, /*InsnID*/0,
    2479             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2480             :         // GIR_Coverage, 416,
    2481             :         GIR_Done,
    2482             :       // Label 171: @5559
    2483             :       GIM_Try, /*On fail goto*//*Label 172*/ 5603, // Rule ID 651 //
    2484             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2485             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
    2486             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2487             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2488             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2489             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2490             :         // (intrinsic_wo_chain:{ *:[i32] } 967:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)
    2491             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B32,
    2492             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2493             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
    2494             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
    2495             :         GIR_EraseFromParent, /*InsnID*/0,
    2496             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2497             :         // GIR_Coverage, 651,
    2498             :         GIR_Done,
    2499             :       // Label 172: @5603
    2500             :       GIM_Try, /*On fail goto*//*Label 173*/ 5647, // Rule ID 652 //
    2501             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2502             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_set_inactive,
    2503             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2504             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2505             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2506             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2507             :         // (intrinsic_wo_chain:{ *:[i64] } 967:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)  =>  (V_SET_INACTIVE_B64:{ *:[i64] } i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)
    2508             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SET_INACTIVE_B64,
    2509             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2510             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
    2511             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
    2512             :         GIR_EraseFromParent, /*InsnID*/0,
    2513             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2514             :         // GIR_Coverage, 652,
    2515             :         GIR_Done,
    2516             :       // Label 173: @5647
    2517             :       GIM_Try, /*On fail goto*//*Label 174*/ 5691, // Rule ID 662 //
    2518             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2519             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_if_break,
    2520             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2521             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
    2522             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2523             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    2524             :         // (intrinsic_wo_chain:{ *:[i64] } 439:{ *:[iPTR] }, i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)  =>  (SI_IF_BREAK:{ *:[i64] }:{ *:[i1] } i1:{ *:[i1] }:$vcc, i64:{ *:[i64] }:$src)
    2525             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_IF_BREAK,
    2526             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2527             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vcc
    2528             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
    2529             :         GIR_EraseFromParent, /*InsnID*/0,
    2530             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2531             :         // GIR_Coverage, 662,
    2532             :         GIR_Done,
    2533             :       // Label 174: @5691
    2534             :       GIM_Try, /*On fail goto*//*Label 175*/ 5735, // Rule ID 663 //
    2535             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2536             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_else_break,
    2537             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2538             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2539             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    2540             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    2541             :         // (intrinsic_wo_chain:{ *:[i64] } 423:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)  =>  (SI_ELSE_BREAK:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
    2542             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_ELSE_BREAK,
    2543             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
    2544             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2545             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2546             :         GIR_EraseFromParent, /*InsnID*/0,
    2547             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2548             :         // GIR_Coverage, 663,
    2549             :         GIR_Done,
    2550             :       // Label 175: @5735
    2551             :       GIM_Try, /*On fail goto*//*Label 176*/ 5779, // Rule ID 418 //
    2552             :         GIM_CheckFeatures, GIFBS_isGCN,
    2553             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_lo,
    2554             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2555             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2556             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2557             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2558             :         // (intrinsic_wo_chain:{ *:[i32] } 912:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    2559             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_LO_U32_B32_e64,
    2560             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2561             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2562             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2563             :         GIR_EraseFromParent, /*InsnID*/0,
    2564             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2565             :         // GIR_Coverage, 418,
    2566             :         GIR_Done,
    2567             :       // Label 176: @5779
    2568             :       GIM_Try, /*On fail goto*//*Label 177*/ 5823, // Rule ID 419 //
    2569             :         GIM_CheckFeatures, GIFBS_isGCN,
    2570             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mbcnt_hi,
    2571             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2572             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2573             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2574             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2575             :         // (intrinsic_wo_chain:{ *:[i32] } 911:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    2576             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MBCNT_HI_U32_B32_e64,
    2577             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2578             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2579             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2580             :         GIR_EraseFromParent, /*InsnID*/0,
    2581             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2582             :         // GIR_Coverage, 419,
    2583             :         GIR_Done,
    2584             :       // Label 177: @5823
    2585             :       GIM_Reject,
    2586             :     // Label 161: @5824
    2587             :     GIM_Try, /*On fail goto*//*Label 178*/ 6838,
    2588             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
    2589             :       GIM_Try, /*On fail goto*//*Label 179*/ 5881, // Rule ID 417 //
    2590             :         GIM_CheckFeatures, GIFBS_isGCN,
    2591             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_writelane,
    2592             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2593             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2594             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2595             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2596             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2597             :         // (intrinsic_wo_chain:{ *:[i32] } 1005:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)  =>  (V_WRITELANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)
    2598             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_WRITELANE_B32,
    2599             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2600             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2601             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2602             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vdst_in
    2603             :         GIR_EraseFromParent, /*InsnID*/0,
    2604             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2605             :         // GIR_Coverage, 417,
    2606             :         GIR_Done,
    2607             :       // Label 179: @5881
    2608             :       GIM_Try, /*On fail goto*//*Label 180*/ 5936, // Rule ID 962 //
    2609             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2610             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u8,
    2611             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2612             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2613             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2614             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2615             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2616             :         // (intrinsic_wo_chain:{ *:[i32] } 962:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
    2617             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U8,
    2618             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2619             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2620             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2621             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2622             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    2623             :         GIR_EraseFromParent, /*InsnID*/0,
    2624             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2625             :         // GIR_Coverage, 962,
    2626             :         GIR_Done,
    2627             :       // Label 180: @5936
    2628             :       GIM_Try, /*On fail goto*//*Label 181*/ 5991, // Rule ID 963 //
    2629             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2630             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_hi_u8,
    2631             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2632             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2633             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2634             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2635             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2636             :         // (intrinsic_wo_chain:{ *:[i32] } 960:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_HI_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
    2637             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_HI_U8,
    2638             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2639             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2640             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2641             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2642             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    2643             :         GIR_EraseFromParent, /*InsnID*/0,
    2644             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2645             :         // GIR_Coverage, 963,
    2646             :         GIR_Done,
    2647             :       // Label 181: @5991
    2648             :       GIM_Try, /*On fail goto*//*Label 182*/ 6046, // Rule ID 964 //
    2649             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2650             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_sad_u16,
    2651             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2652             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2653             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2654             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2655             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2656             :         // (intrinsic_wo_chain:{ *:[i32] } 961:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U16:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
    2657             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SAD_U16,
    2658             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2659             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2660             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2661             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2662             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    2663             :         GIR_EraseFromParent, /*InsnID*/0,
    2664             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2665             :         // GIR_Coverage, 964,
    2666             :         GIR_Done,
    2667             :       // Label 182: @6046
    2668             :       GIM_Try, /*On fail goto*//*Label 183*/ 6101, // Rule ID 965 //
    2669             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2670             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_msad_u8,
    2671             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2672             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2673             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2674             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2675             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2676             :         // (intrinsic_wo_chain:{ *:[i32] } 916:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MSAD_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
    2677             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MSAD_U8,
    2678             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2679             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2680             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2681             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2682             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    2683             :         GIR_EraseFromParent, /*InsnID*/0,
    2684             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2685             :         // GIR_Coverage, 965,
    2686             :         GIR_Done,
    2687             :       // Label 183: @6101
    2688             :       GIM_Try, /*On fail goto*//*Label 184*/ 6156, // Rule ID 966 //
    2689             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2690             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_pk_u16_u8,
    2691             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2692             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2693             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2694             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
    2695             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2696             :         // (intrinsic_wo_chain:{ *:[i64] } 914:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
    2697             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_PK_U16_U8,
    2698             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2699             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2700             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2701             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2702             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    2703             :         GIR_EraseFromParent, /*InsnID*/0,
    2704             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2705             :         // GIR_Coverage, 966,
    2706             :         GIR_Done,
    2707             :       // Label 184: @6156
    2708             :       GIM_Try, /*On fail goto*//*Label 185*/ 6211, // Rule ID 967 //
    2709             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2710             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_qsad_pk_u16_u8,
    2711             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    2712             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2713             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2714             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
    2715             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    2716             :         // (intrinsic_wo_chain:{ *:[i64] } 918:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
    2717             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_QSAD_PK_U16_U8,
    2718             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2719             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2720             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2721             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2722             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    2723             :         GIR_EraseFromParent, /*InsnID*/0,
    2724             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2725             :         // GIR_Coverage, 967,
    2726             :         GIR_Done,
    2727             :       // Label 185: @6211
    2728             :       GIM_Try, /*On fail goto*//*Label 186*/ 6266, // Rule ID 968 //
    2729             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2730             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_mqsad_u32_u8,
    2731             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
    2732             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    2733             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2734             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
    2735             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_128RegClassID,
    2736             :         // (intrinsic_wo_chain:{ *:[v4i32] } 915:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
    2737             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MQSAD_U32_U8,
    2738             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2739             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2740             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2741             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2742             :         GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    2743             :         GIR_EraseFromParent, /*InsnID*/0,
    2744             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2745             :         // GIR_Coverage, 968,
    2746             :         GIR_Done,
    2747             :       // Label 186: @6266
    2748             :       GIM_Try, /*On fail goto*//*Label 187*/ 6351, // Rule ID 452 //
    2749             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubeid,
    2750             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2751             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2752             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2753             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2754             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2755             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2756             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2757             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
    2758             :         // (intrinsic_wo_chain:{ *:[f32] } 401:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEID_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2759             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEID_F32,
    2760             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2761             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2762             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2763             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2764             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2765             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    2766             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    2767             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2768             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2769             :         GIR_EraseFromParent, /*InsnID*/0,
    2770             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2771             :         // GIR_Coverage, 452,
    2772             :         GIR_Done,
    2773             :       // Label 187: @6351
    2774             :       GIM_Try, /*On fail goto*//*Label 188*/ 6436, // Rule ID 453 //
    2775             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubesc,
    2776             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2777             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2778             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2779             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2780             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2781             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2782             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2783             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
    2784             :         // (intrinsic_wo_chain:{ *:[f32] } 403:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBESC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2785             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBESC_F32,
    2786             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2787             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2788             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2789             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2790             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2791             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    2792             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    2793             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2794             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2795             :         GIR_EraseFromParent, /*InsnID*/0,
    2796             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2797             :         // GIR_Coverage, 453,
    2798             :         GIR_Done,
    2799             :       // Label 188: @6436
    2800             :       GIM_Try, /*On fail goto*//*Label 189*/ 6521, // Rule ID 454 //
    2801             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubetc,
    2802             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2803             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2804             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2805             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2806             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2807             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2808             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2809             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
    2810             :         // (intrinsic_wo_chain:{ *:[f32] } 404:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBETC_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2811             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBETC_F32,
    2812             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2813             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2814             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2815             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2816             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2817             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    2818             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    2819             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2820             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2821             :         GIR_EraseFromParent, /*InsnID*/0,
    2822             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2823             :         // GIR_Coverage, 454,
    2824             :         GIR_Done,
    2825             :       // Label 189: @6521
    2826             :       GIM_Try, /*On fail goto*//*Label 190*/ 6606, // Rule ID 455 //
    2827             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cubema,
    2828             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2829             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2830             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2831             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2832             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2833             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2834             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2835             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
    2836             :         // (intrinsic_wo_chain:{ *:[f32] } 402:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    2837             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CUBEMA_F32,
    2838             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2839             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2840             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2841             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2842             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2843             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    2844             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    2845             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2846             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    2847             :         GIR_EraseFromParent, /*InsnID*/0,
    2848             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2849             :         // GIR_Coverage, 455,
    2850             :         GIR_Done,
    2851             :       // Label 190: @6606
    2852             :       GIM_Try, /*On fail goto*//*Label 191*/ 6687, // Rule ID 470 //
    2853             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_cvt_pk_u8_f32,
    2854             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2855             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2856             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2857             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2858             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2859             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vop3mods0,
    2860             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_vop3mods,
    2861             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/2, GICP_gi_vop3mods,
    2862             :         // (intrinsic_wo_chain:{ *:[i32] } 407:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_PK_U8_F32:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
    2863             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_PK_U8_F32,
    2864             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2865             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    2866             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    2867             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    2868             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    2869             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    2870             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    2871             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    2872             :         GIR_EraseFromParent, /*InsnID*/0,
    2873             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2874             :         // GIR_Coverage, 470,
    2875             :         GIR_Done,
    2876             :       // Label 191: @6687
    2877             :       GIM_Try, /*On fail goto*//*Label 192*/ 6737, // Rule ID 442 //
    2878             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_lerp,
    2879             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2880             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2881             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2882             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2883             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2884             :         // (intrinsic_wo_chain:{ *:[i32] } 908:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_LERP_U8:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
    2885             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LERP_U8,
    2886             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2887             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2888             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2889             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2890             :         GIR_EraseFromParent, /*InsnID*/0,
    2891             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2892             :         // GIR_Coverage, 442,
    2893             :         GIR_Done,
    2894             :       // Label 192: @6737
    2895             :       GIM_Try, /*On fail goto*//*Label 193*/ 6787, // Rule ID 459 //
    2896             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbit,
    2897             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2898             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2899             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2900             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2901             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2902             :         // (intrinsic_wo_chain:{ *:[i32] } 376:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
    2903             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBIT_B32,
    2904             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2905             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2906             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2907             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2908             :         GIR_EraseFromParent, /*InsnID*/0,
    2909             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2910             :         // GIR_Coverage, 459,
    2911             :         GIR_Done,
    2912             :       // Label 193: @6787
    2913             :       GIM_Try, /*On fail goto*//*Label 194*/ 6837, // Rule ID 460 //
    2914             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_alignbyte,
    2915             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    2916             :         GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    2917             :         GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    2918             :         GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
    2919             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    2920             :         // (intrinsic_wo_chain:{ *:[i32] } 377:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBYTE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
    2921             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ALIGNBYTE_B32,
    2922             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    2923             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
    2924             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
    2925             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
    2926             :         GIR_EraseFromParent, /*InsnID*/0,
    2927             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2928             :         // GIR_Coverage, 460,
    2929             :         GIR_Done,
    2930             :       // Label 194: @6837
    2931             :       GIM_Reject,
    2932             :     // Label 178: @6838
    2933             :     GIM_Reject,
    2934             :     // Label 8: @6839
    2935             :     GIM_Try, /*On fail goto*//*Label 195*/ 6859, // Rule ID 53 //
    2936             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2937             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_barrier,
    2938             :       // (intrinsic_void 944:{ *:[iPTR] })  =>  (S_BARRIER)
    2939             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_BARRIER,
    2940             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    2941             :       GIR_EraseFromParent, /*InsnID*/0,
    2942             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2943             :       // GIR_Coverage, 53,
    2944             :       GIR_Done,
    2945             :     // Label 195: @6859
    2946             :     GIM_Try, /*On fail goto*//*Label 196*/ 6879, // Rule ID 508 //
    2947             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    2948             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv,
    2949             :       // (intrinsic_void 946:{ *:[iPTR] })  =>  (S_DCACHE_INV)
    2950             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV,
    2951             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    2952             :       GIR_EraseFromParent, /*InsnID*/0,
    2953             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2954             :       // GIR_Coverage, 508,
    2955             :       GIR_Done,
    2956             :     // Label 196: @6879
    2957             :     GIM_Try, /*On fail goto*//*Label 197*/ 6899, // Rule ID 509 //
    2958             :       GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
    2959             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_inv_vol,
    2960             :       // (intrinsic_void 947:{ *:[iPTR] })  =>  (S_DCACHE_INV_VOL)
    2961             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_INV_VOL,
    2962             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    2963             :       GIR_EraseFromParent, /*InsnID*/0,
    2964             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2965             :       // GIR_Coverage, 509,
    2966             :       GIR_Done,
    2967             :     // Label 197: @6899
    2968             :     GIM_Try, /*On fail goto*//*Label 198*/ 6919, // Rule ID 510 //
    2969             :       GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
    2970             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb,
    2971             :       // (intrinsic_void 948:{ *:[iPTR] })  =>  (S_DCACHE_WB)
    2972             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB,
    2973             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    2974             :       GIR_EraseFromParent, /*InsnID*/0,
    2975             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2976             :       // GIR_Coverage, 510,
    2977             :       GIR_Done,
    2978             :     // Label 198: @6919
    2979             :     GIM_Try, /*On fail goto*//*Label 199*/ 6939, // Rule ID 511 //
    2980             :       GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
    2981             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_s_dcache_wb_vol,
    2982             :       // (intrinsic_void 949:{ *:[iPTR] })  =>  (S_DCACHE_WB_VOL)
    2983             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_DCACHE_WB_VOL,
    2984             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    2985             :       GIR_EraseFromParent, /*InsnID*/0,
    2986             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2987             :       // GIR_Coverage, 511,
    2988             :       GIR_Done,
    2989             :     // Label 199: @6939
    2990             :     GIM_Try, /*On fail goto*//*Label 200*/ 6959, // Rule ID 641 //
    2991             :       GIM_CheckFeatures, GIFBS_TruePredicate_isSI,
    2992             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_sc,
    2993             :       // (intrinsic_void 397:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_SC)
    2994             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_SC,
    2995             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    2996             :       GIR_EraseFromParent, /*InsnID*/0,
    2997             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    2998             :       // GIR_Coverage, 641,
    2999             :       GIR_Done,
    3000             :     // Label 200: @6959
    3001             :     GIM_Try, /*On fail goto*//*Label 201*/ 6979, // Rule ID 642 //
    3002             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3003             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1,
    3004             :       // (intrinsic_void 396:{ *:[iPTR] })  =>  (BUFFER_WBINVL1)
    3005             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1,
    3006             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    3007             :       GIR_EraseFromParent, /*InsnID*/0,
    3008             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3009             :       // GIR_Coverage, 642,
    3010             :       GIR_Done,
    3011             :     // Label 201: @6979
    3012             :     GIM_Try, /*On fail goto*//*Label 202*/ 6999, // Rule ID 643 //
    3013             :       GIM_CheckFeatures, GIFBS_TruePredicate_isCIVI,
    3014             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_buffer_wbinvl1_vol,
    3015             :       // (intrinsic_void 398:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_VOL)
    3016             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::BUFFER_WBINVL1_VOL,
    3017             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    3018             :       GIR_EraseFromParent, /*InsnID*/0,
    3019             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3020             :       // GIR_Coverage, 643,
    3021             :       GIR_Done,
    3022             :     // Label 202: @6999
    3023             :     GIM_Try, /*On fail goto*//*Label 203*/ 7019, // Rule ID 656 //
    3024             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3025             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_wave_barrier,
    3026             :       // (intrinsic_void 996:{ *:[iPTR] })  =>  (WAVE_BARRIER)
    3027             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::WAVE_BARRIER,
    3028             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    3029             :       GIR_EraseFromParent, /*InsnID*/0,
    3030             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3031             :       // GIR_Coverage, 656,
    3032             :       GIR_Done,
    3033             :     // Label 203: @7019
    3034             :     GIM_Try, /*On fail goto*//*Label 204*/ 7039, // Rule ID 665 //
    3035             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3036             :       GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_unreachable,
    3037             :       // (intrinsic_void 994:{ *:[iPTR] })  =>  (SI_MASKED_UNREACHABLE)
    3038             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_MASKED_UNREACHABLE,
    3039             :       GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    3040             :       GIR_EraseFromParent, /*InsnID*/0,
    3041             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3042             :       // GIR_Coverage, 665,
    3043             :       GIR_Done,
    3044             :     // Label 204: @7039
    3045             :     GIM_Try, /*On fail goto*//*Label 205*/ 7137,
    3046             :       GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
    3047             :       GIM_Try, /*On fail goto*//*Label 206*/ 7076, // Rule ID 507 //
    3048             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3049             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memtime,
    3050             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3051             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
    3052             :         // (intrinsic_w_chain:{ *:[i64] } 955:{ *:[iPTR] })  =>  (S_MEMTIME:{ *:[i64] })
    3053             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMTIME,
    3054             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3055             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    3056             :         GIR_EraseFromParent, /*InsnID*/0,
    3057             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3058             :         // GIR_Coverage, 507,
    3059             :         GIR_Done,
    3060             :       // Label 206: @7076
    3061             :       GIM_Try, /*On fail goto*//*Label 207*/ 7108, // Rule ID 512 //
    3062             :         GIM_CheckFeatures, GIFBS_TruePredicate_isVI,
    3063             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::amdgcn_s_memrealtime,
    3064             :         GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
    3065             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64_XEXECRegClassID,
    3066             :         // (intrinsic_w_chain:{ *:[i64] } 954:{ *:[iPTR] })  =>  (S_MEMREALTIME:{ *:[i64] })
    3067             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MEMREALTIME,
    3068             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3069             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    3070             :         GIR_EraseFromParent, /*InsnID*/0,
    3071             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3072             :         // GIR_Coverage, 512,
    3073             :         GIR_Done,
    3074             :       // Label 207: @7108
    3075             :       GIM_Try, /*On fail goto*//*Label 208*/ 7136, // Rule ID 660 //
    3076             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3077             :         GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::amdgcn_end_cf,
    3078             :         GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3079             :         // (intrinsic_void 424:{ *:[iPTR] }, i64:{ *:[i64] }:$saved)  =>  (SI_END_CF i64:{ *:[i64] }:$saved)
    3080             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::SI_END_CF,
    3081             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // saved
    3082             :         GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
    3083             :         GIR_EraseFromParent, /*InsnID*/0,
    3084             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3085             :         // GIR_Coverage, 660,
    3086             :         GIR_Done,
    3087             :       // Label 208: @7136
    3088             :       GIM_Reject,
    3089             :     // Label 205: @7137
    3090             :     GIM_Reject,
    3091             :     // Label 9: @7138
    3092             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 211*/ 7194,
    3093             :     /*GILLT_s16*//*Label 209*/ 7146,
    3094             :     /*GILLT_s32*//*Label 210*/ 7170,
    3095             :     // Label 209: @7146
    3096             :     GIM_Try, /*On fail goto*//*Label 212*/ 7169, // Rule ID 817 //
    3097             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3098             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    3099             :       // MIs[0] Operand 1
    3100             :       // No operand predicates
    3101             :       // (imm:{ *:[i16] }):$imm  =>  (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
    3102             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
    3103             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3104             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
    3105             :       GIR_EraseFromParent, /*InsnID*/0,
    3106             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3107             :       // GIR_Coverage, 817,
    3108             :       GIR_Done,
    3109             :     // Label 212: @7169
    3110             :     GIM_Reject,
    3111             :     // Label 210: @7170
    3112             :     GIM_Try, /*On fail goto*//*Label 213*/ 7193, // Rule ID 1686 //
    3113             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3114             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    3115             :       // MIs[0] Operand 1
    3116             :       // No operand predicates
    3117             :       // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
    3118             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
    3119             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3120             :       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
    3121             :       GIR_EraseFromParent, /*InsnID*/0,
    3122             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3123             :       // GIR_Coverage, 1686,
    3124             :       GIR_Done,
    3125             :     // Label 213: @7193
    3126             :     GIM_Reject,
    3127             :     // Label 211: @7194
    3128             :     GIM_Reject,
    3129             :     // Label 10: @7195
    3130             :     GIM_Try, /*On fail goto*//*Label 214*/ 7225, // Rule ID 433 //
    3131             :       GIM_CheckFeatures, GIFBS_isSICI,
    3132             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3133             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3134             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3135             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3136             :       // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    3137             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHL_B32_e64,
    3138             :       GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
    3139             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3140             :       // GIR_Coverage, 433,
    3141             :       GIR_Done,
    3142             :     // Label 214: @7225
    3143             :     GIM_Reject,
    3144             :     // Label 11: @7226
    3145             :     GIM_Try, /*On fail goto*//*Label 215*/ 7256, // Rule ID 429 //
    3146             :       GIM_CheckFeatures, GIFBS_isSICI,
    3147             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3148             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3149             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3150             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3151             :       // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    3152             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_LSHR_B32_e64,
    3153             :       GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
    3154             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3155             :       // GIR_Coverage, 429,
    3156             :       GIR_Done,
    3157             :     // Label 215: @7256
    3158             :     GIM_Reject,
    3159             :     // Label 12: @7257
    3160             :     GIM_Try, /*On fail goto*//*Label 216*/ 7423,
    3161             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3162             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3163             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3164             :       GIM_Try, /*On fail goto*//*Label 217*/ 7378,
    3165             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3166             :         GIM_Try, /*On fail goto*//*Label 218*/ 7310, // Rule ID 1916 //
    3167             :           GIM_CheckFeatures, GIFBS_TruePredicate_isSICI,
    3168             :           GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::VGPR_32RegClassID,
    3169             :           GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vsrc0,
    3170             :           // (sra:{ *:[i32] } (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0), VGPR_32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    3171             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e32,
    3172             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3173             :           GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3174             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
    3175             :           GIR_EraseFromParent, /*InsnID*/0,
    3176             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3177             :           // GIR_Coverage, 1916,
    3178             :           GIR_Done,
    3179             :         // Label 218: @7310
    3180             :         GIM_Try, /*On fail goto*//*Label 219*/ 7343, // Rule ID 1917 //
    3181             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3182             :           GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::VGPR_32RegClassID,
    3183             :           GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_vsrc0,
    3184             :           // (sra:{ *:[i32] } VGPR_32:{ *:[i32] }:$src1, (sd_vsrc0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I32_e32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    3185             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e32,
    3186             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3187             :           GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3188             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
    3189             :           GIR_EraseFromParent, /*InsnID*/0,
    3190             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3191             :           // GIR_Coverage, 1917,
    3192             :           GIR_Done,
    3193             :         // Label 219: @7343
    3194             :         GIM_Try, /*On fail goto*//*Label 220*/ 7377, // Rule ID 1918 //
    3195             :           GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3196             :           GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vcsrc,
    3197             :           GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vcsrc,
    3198             :           // (sra:{ *:[i32] } (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src0), (sd_vcsrc:{ *:[i32] } i32:{ *:[i32] }:$src1))  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)
    3199             :           GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ASHRREV_I32_e64,
    3200             :           GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3201             :           GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3202             :           GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3203             :           GIR_EraseFromParent, /*InsnID*/0,
    3204             :           GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3205             :           // GIR_Coverage, 1918,
    3206             :           GIR_Done,
    3207             :         // Label 220: @7377
    3208             :         GIM_Reject,
    3209             :       // Label 217: @7378
    3210             :       GIM_Try, /*On fail goto*//*Label 221*/ 7404, // Rule ID 1915 //
    3211             :         GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3212             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    3213             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AMDGPU::SReg_32RegClassID,
    3214             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AMDGPU::SReg_32RegClassID,
    3215             :         // (sra:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    3216             :         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ASHR_I32,
    3217             :         GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
    3218             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3219             :         // GIR_Coverage, 1915,
    3220             :         GIR_Done,
    3221             :       // Label 221: @7404
    3222             :       GIM_Try, /*On fail goto*//*Label 222*/ 7422, // Rule ID 431 //
    3223             :         GIM_CheckFeatures, GIFBS_isSICI,
    3224             :         GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3225             :         // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
    3226             :         GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_ASHR_I32_e64,
    3227             :         GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
    3228             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3229             :         // GIR_Coverage, 431,
    3230             :         GIR_Done,
    3231             :       // Label 222: @7422
    3232             :       GIM_Reject,
    3233             :     // Label 216: @7423
    3234             :     GIM_Reject,
    3235             :     // Label 13: @7424
    3236             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 226*/ 7773,
    3237             :     /*GILLT_s16*//*Label 223*/ 7433,
    3238             :     /*GILLT_s32*//*Label 224*/ 7545,
    3239             :     /*GILLT_s64*//*Label 225*/ 7661,
    3240             :     // Label 223: @7433
    3241             :     GIM_Try, /*On fail goto*//*Label 227*/ 7544,
    3242             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3243             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
    3244             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3245             :       GIM_Try, /*On fail goto*//*Label 228*/ 7495, // Rule ID 435 //
    3246             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3247             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3248             :         // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3249             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
    3250             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3251             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3252             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3253             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3254             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3255             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3256             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3257             :         GIR_EraseFromParent, /*InsnID*/0,
    3258             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3259             :         // GIR_Coverage, 435,
    3260             :         GIR_Done,
    3261             :       // Label 228: @7495
    3262             :       GIM_Try, /*On fail goto*//*Label 229*/ 7543, // Rule ID 1930 //
    3263             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3264             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
    3265             :         // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3266             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F16_e64,
    3267             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3268             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    3269             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    3270             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    3271             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    3272             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    3273             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
    3274             :         GIR_EraseFromParent, /*InsnID*/0,
    3275             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3276             :         // GIR_Coverage, 1930,
    3277             :         GIR_Done,
    3278             :       // Label 229: @7543
    3279             :       GIM_Reject,
    3280             :     // Label 227: @7544
    3281             :     GIM_Reject,
    3282             :     // Label 224: @7545
    3283             :     GIM_Try, /*On fail goto*//*Label 230*/ 7660,
    3284             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3285             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3286             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3287             :       GIM_Try, /*On fail goto*//*Label 231*/ 7609, // Rule ID 388 //
    3288             :         GIM_CheckFeatures, GIFBS_isGCN,
    3289             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3290             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3291             :         // (fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3292             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
    3293             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3294             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3295             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3296             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3297             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3298             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3299             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3300             :         GIR_EraseFromParent, /*InsnID*/0,
    3301             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3302             :         // GIR_Coverage, 388,
    3303             :         GIR_Done,
    3304             :       // Label 231: @7609
    3305             :       GIM_Try, /*On fail goto*//*Label 232*/ 7659, // Rule ID 1925 //
    3306             :         GIM_CheckFeatures, GIFBS_isGCN,
    3307             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3308             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
    3309             :         // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3310             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F32_e64,
    3311             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3312             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    3313             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    3314             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    3315             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    3316             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    3317             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
    3318             :         GIR_EraseFromParent, /*InsnID*/0,
    3319             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3320             :         // GIR_Coverage, 1925,
    3321             :         GIR_Done,
    3322             :       // Label 232: @7659
    3323             :       GIM_Reject,
    3324             :     // Label 230: @7660
    3325             :     GIM_Reject,
    3326             :     // Label 225: @7661
    3327             :     GIM_Try, /*On fail goto*//*Label 233*/ 7772,
    3328             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3329             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3330             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    3331             :       GIM_Try, /*On fail goto*//*Label 234*/ 7723, // Rule ID 444 //
    3332             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3333             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3334             :         // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3335             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
    3336             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3337             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3338             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3339             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3340             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3341             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3342             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3343             :         GIR_EraseFromParent, /*InsnID*/0,
    3344             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3345             :         // GIR_Coverage, 444,
    3346             :         GIR_Done,
    3347             :       // Label 234: @7723
    3348             :       GIM_Try, /*On fail goto*//*Label 235*/ 7771, // Rule ID 1934 //
    3349             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3350             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
    3351             :         // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3352             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_ADD_F64,
    3353             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3354             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    3355             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    3356             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    3357             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    3358             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    3359             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
    3360             :         GIR_EraseFromParent, /*InsnID*/0,
    3361             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3362             :         // GIR_Coverage, 1934,
    3363             :         GIR_Done,
    3364             :       // Label 235: @7771
    3365             :       GIM_Reject,
    3366             :     // Label 233: @7772
    3367             :     GIM_Reject,
    3368             :     // Label 226: @7773
    3369             :     GIM_Reject,
    3370             :     // Label 14: @7774
    3371             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 238*/ 7906,
    3372             :     /*GILLT_s16*//*Label 236*/ 7782,
    3373             :     /*GILLT_s32*//*Label 237*/ 7843,
    3374             :     // Label 236: @7782
    3375             :     GIM_Try, /*On fail goto*//*Label 239*/ 7842, // Rule ID 436 //
    3376             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3377             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
    3378             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3379             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3380             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3381             :       // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3382             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F16_e64,
    3383             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3384             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3385             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3386             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3387             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3388             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3389             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3390             :       GIR_EraseFromParent, /*InsnID*/0,
    3391             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3392             :       // GIR_Coverage, 436,
    3393             :       GIR_Done,
    3394             :     // Label 239: @7842
    3395             :     GIM_Reject,
    3396             :     // Label 237: @7843
    3397             :     GIM_Try, /*On fail goto*//*Label 240*/ 7905, // Rule ID 389 //
    3398             :       GIM_CheckFeatures, GIFBS_isGCN,
    3399             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3400             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3401             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3402             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3403             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3404             :       // (fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3405             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_SUB_F32_e64,
    3406             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3407             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3408             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3409             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3410             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3411             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3412             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3413             :       GIR_EraseFromParent, /*InsnID*/0,
    3414             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3415             :       // GIR_Coverage, 389,
    3416             :       GIR_Done,
    3417             :     // Label 240: @7905
    3418             :     GIM_Reject,
    3419             :     // Label 238: @7906
    3420             :     GIM_Reject,
    3421             :     // Label 15: @7907
    3422             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 244*/ 8256,
    3423             :     /*GILLT_s16*//*Label 241*/ 7916,
    3424             :     /*GILLT_s32*//*Label 242*/ 8028,
    3425             :     /*GILLT_s64*//*Label 243*/ 8144,
    3426             :     // Label 241: @7916
    3427             :     GIM_Try, /*On fail goto*//*Label 245*/ 8027,
    3428             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3429             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
    3430             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3431             :       GIM_Try, /*On fail goto*//*Label 246*/ 7978, // Rule ID 437 //
    3432             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3433             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3434             :         // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3435             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
    3436             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3437             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3438             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3439             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3440             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3441             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3442             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3443             :         GIR_EraseFromParent, /*InsnID*/0,
    3444             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3445             :         // GIR_Coverage, 437,
    3446             :         GIR_Done,
    3447             :       // Label 246: @7978
    3448             :       GIM_Try, /*On fail goto*//*Label 247*/ 8026, // Rule ID 1931 //
    3449             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3450             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
    3451             :         // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3452             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F16_e64,
    3453             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3454             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    3455             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    3456             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    3457             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    3458             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    3459             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
    3460             :         GIR_EraseFromParent, /*InsnID*/0,
    3461             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3462             :         // GIR_Coverage, 1931,
    3463             :         GIR_Done,
    3464             :       // Label 247: @8026
    3465             :       GIM_Reject,
    3466             :     // Label 245: @8027
    3467             :     GIM_Reject,
    3468             :     // Label 242: @8028
    3469             :     GIM_Try, /*On fail goto*//*Label 248*/ 8143,
    3470             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3471             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3472             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3473             :       GIM_Try, /*On fail goto*//*Label 249*/ 8092, // Rule ID 391 //
    3474             :         GIM_CheckFeatures, GIFBS_isGCN,
    3475             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3476             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3477             :         // (fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3478             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
    3479             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3480             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3481             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3482             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3483             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3484             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3485             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3486             :         GIR_EraseFromParent, /*InsnID*/0,
    3487             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3488             :         // GIR_Coverage, 391,
    3489             :         GIR_Done,
    3490             :       // Label 249: @8092
    3491             :       GIM_Try, /*On fail goto*//*Label 250*/ 8142, // Rule ID 1927 //
    3492             :         GIM_CheckFeatures, GIFBS_isGCN,
    3493             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3494             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
    3495             :         // (fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3496             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F32_e64,
    3497             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3498             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    3499             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    3500             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    3501             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    3502             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    3503             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
    3504             :         GIR_EraseFromParent, /*InsnID*/0,
    3505             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3506             :         // GIR_Coverage, 1927,
    3507             :         GIR_Done,
    3508             :       // Label 250: @8142
    3509             :       GIM_Reject,
    3510             :     // Label 248: @8143
    3511             :     GIM_Reject,
    3512             :     // Label 243: @8144
    3513             :     GIM_Try, /*On fail goto*//*Label 251*/ 8255,
    3514             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3515             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3516             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    3517             :       GIM_Try, /*On fail goto*//*Label 252*/ 8206, // Rule ID 445 //
    3518             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3519             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3520             :         // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3521             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
    3522             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3523             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3524             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3525             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3526             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3527             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3528             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3529             :         GIR_EraseFromParent, /*InsnID*/0,
    3530             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3531             :         // GIR_Coverage, 445,
    3532             :         GIR_Done,
    3533             :       // Label 252: @8206
    3534             :       GIM_Try, /*On fail goto*//*Label 253*/ 8254, // Rule ID 1935 //
    3535             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3536             :         GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods0,
    3537             :         // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3538             :         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MUL_F64,
    3539             :         GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3540             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src0_modifiers
    3541             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src0
    3542             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src1_modifiers
    3543             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src1
    3544             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/2, // clamp
    3545             :         GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/3, // omod
    3546             :         GIR_EraseFromParent, /*InsnID*/0,
    3547             :         GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3548             :         // GIR_Coverage, 1935,
    3549             :         GIR_Done,
    3550             :       // Label 253: @8254
    3551             :       GIM_Reject,
    3552             :     // Label 251: @8255
    3553             :     GIM_Reject,
    3554             :     // Label 244: @8256
    3555             :     GIM_Reject,
    3556             :     // Label 16: @8257
    3557             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 257*/ 8500,
    3558             :     /*GILLT_s16*//*Label 254*/ 8266,
    3559             :     /*GILLT_s32*//*Label 255*/ 8344,
    3560             :     /*GILLT_s64*//*Label 256*/ 8422,
    3561             :     // Label 254: @8266
    3562             :     GIM_Try, /*On fail goto*//*Label 258*/ 8343, // Rule ID 481 //
    3563             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3564             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
    3565             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
    3566             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3567             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3568             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3569             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
    3570             :       // (fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3571             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F16,
    3572             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3573             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3574             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3575             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3576             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3577             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    3578             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    3579             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3580             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3581             :       GIR_EraseFromParent, /*InsnID*/0,
    3582             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3583             :       // GIR_Coverage, 481,
    3584             :       GIR_Done,
    3585             :     // Label 258: @8343
    3586             :     GIM_Reject,
    3587             :     // Label 255: @8344
    3588             :     GIM_Try, /*On fail goto*//*Label 259*/ 8421, // Rule ID 441 //
    3589             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3590             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3591             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
    3592             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3593             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3594             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3595             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
    3596             :       // (fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3597             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F32,
    3598             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3599             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3600             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3601             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3602             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3603             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    3604             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    3605             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3606             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3607             :       GIR_EraseFromParent, /*InsnID*/0,
    3608             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3609             :       // GIR_Coverage, 441,
    3610             :       GIR_Done,
    3611             :     // Label 259: @8421
    3612             :     GIM_Reject,
    3613             :     // Label 256: @8422
    3614             :     GIM_Try, /*On fail goto*//*Label 260*/ 8499, // Rule ID 443 //
    3615             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3616             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
    3617             :       GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
    3618             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    3619             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3620             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_vop3mods,
    3621             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/2, GICP_gi_vop3mods,
    3622             :       // (fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3623             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_FMA_F64,
    3624             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3625             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3626             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3627             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // src1_modifiers
    3628             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
    3629             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/1, // src2_modifiers
    3630             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/2, /*SubOperand*/0, // src2
    3631             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3632             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3633             :       GIR_EraseFromParent, /*InsnID*/0,
    3634             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3635             :       // GIR_Coverage, 443,
    3636             :       GIR_Done,
    3637             :     // Label 260: @8499
    3638             :     GIM_Reject,
    3639             :     // Label 257: @8500
    3640             :     GIM_Reject,
    3641             :     // Label 17: @8501
    3642             :     GIM_Try, /*On fail goto*//*Label 261*/ 8573, // Rule ID 1694 //
    3643             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3644             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    3645             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3646             :       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
    3647             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3648             :       // (fpow:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_EXP_F32_e32:{ *:[f32] } (V_MUL_LEGACY_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src1, (V_LOG_F32_e32:{ *:[i16] } f32:{ *:[f32] }:$src0)))
    3649             :       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
    3650             :       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
    3651             :       GIR_BuildMI, /*InsnID*/2, /*Opcode*/AMDGPU::V_LOG_F32_e32,
    3652             :       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
    3653             :       GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src0
    3654             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
    3655             :       GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_MUL_LEGACY_F32_e32,
    3656             :       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
    3657             :       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src1
    3658             :       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
    3659             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
    3660             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e32,
    3661             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3662             :       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
    3663             :       GIR_EraseFromParent, /*InsnID*/0,
    3664             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3665             :       // GIR_Coverage, 1694,
    3666             :       GIR_Done,
    3667             :     // Label 261: @8573
    3668             :     GIM_Reject,
    3669             :     // Label 18: @8574
    3670             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 264*/ 8670,
    3671             :     /*GILLT_s16*//*Label 262*/ 8582,
    3672             :     /*GILLT_s32*//*Label 263*/ 8626,
    3673             :     // Label 262: @8582
    3674             :     GIM_Try, /*On fail goto*//*Label 265*/ 8625, // Rule ID 378 //
    3675             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3676             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3677             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3678             :       // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3679             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F16_e64,
    3680             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3681             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3682             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3683             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3684             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3685             :       GIR_EraseFromParent, /*InsnID*/0,
    3686             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3687             :       // GIR_Coverage, 378,
    3688             :       GIR_Done,
    3689             :     // Label 265: @8625
    3690             :     GIM_Reject,
    3691             :     // Label 263: @8626
    3692             :     GIM_Try, /*On fail goto*//*Label 266*/ 8669, // Rule ID 345 //
    3693             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3694             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3695             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3696             :       // (fexp2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3697             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_EXP_F32_e64,
    3698             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3699             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3700             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3701             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3702             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3703             :       GIR_EraseFromParent, /*InsnID*/0,
    3704             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3705             :       // GIR_Coverage, 345,
    3706             :       GIR_Done,
    3707             :     // Label 266: @8669
    3708             :     GIM_Reject,
    3709             :     // Label 264: @8670
    3710             :     GIM_Reject,
    3711             :     // Label 19: @8671
    3712             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 269*/ 8767,
    3713             :     /*GILLT_s16*//*Label 267*/ 8679,
    3714             :     /*GILLT_s32*//*Label 268*/ 8723,
    3715             :     // Label 267: @8679
    3716             :     GIM_Try, /*On fail goto*//*Label 270*/ 8722, // Rule ID 377 //
    3717             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3718             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3719             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3720             :       // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3721             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F16_e64,
    3722             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3723             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3724             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3725             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3726             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3727             :       GIR_EraseFromParent, /*InsnID*/0,
    3728             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3729             :       // GIR_Coverage, 377,
    3730             :       GIR_Done,
    3731             :     // Label 270: @8722
    3732             :     GIM_Reject,
    3733             :     // Label 268: @8723
    3734             :     GIM_Try, /*On fail goto*//*Label 271*/ 8766, // Rule ID 346 //
    3735             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3736             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3737             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3738             :       // (flog2:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3739             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_LOG_F32_e64,
    3740             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3741             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3742             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3743             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3744             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3745             :       GIR_EraseFromParent, /*InsnID*/0,
    3746             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3747             :       // GIR_Coverage, 346,
    3748             :       GIR_Done,
    3749             :     // Label 271: @8766
    3750             :     GIM_Reject,
    3751             :     // Label 269: @8767
    3752             :     GIM_Reject,
    3753             :     // Label 20: @8768
    3754             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 4, /*)*//*default:*//*Label 274*/ 8864,
    3755             :     /*GILLT_s32*//*Label 272*/ 8776,
    3756             :     /*GILLT_s64*//*Label 273*/ 8820,
    3757             :     // Label 272: @8776
    3758             :     GIM_Try, /*On fail goto*//*Label 275*/ 8819, // Rule ID 329 //
    3759             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3760             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3761             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3762             :       // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3763             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F16_e64,
    3764             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3765             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3766             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3767             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3768             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3769             :       GIR_EraseFromParent, /*InsnID*/0,
    3770             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3771             :       // GIR_Coverage, 329,
    3772             :       GIR_Done,
    3773             :     // Label 275: @8819
    3774             :     GIM_Reject,
    3775             :     // Label 273: @8820
    3776             :     GIM_Try, /*On fail goto*//*Label 276*/ 8863, // Rule ID 333 //
    3777             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3778             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    3779             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3780             :       // (fpextend:{ *:[f64] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_F32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3781             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_F32_e64,
    3782             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3783             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3784             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3785             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3786             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3787             :       GIR_EraseFromParent, /*InsnID*/0,
    3788             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3789             :       // GIR_Coverage, 333,
    3790             :       GIR_Done,
    3791             :     // Label 276: @8863
    3792             :     GIM_Reject,
    3793             :     // Label 274: @8864
    3794             :     GIM_Reject,
    3795             :     // Label 21: @8865
    3796             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 279*/ 8961,
    3797             :     /*GILLT_s16*//*Label 277*/ 8873,
    3798             :     /*GILLT_s32*//*Label 278*/ 8917,
    3799             :     // Label 277: @8873
    3800             :     GIM_Try, /*On fail goto*//*Label 280*/ 8916, // Rule ID 328 //
    3801             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3802             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3803             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3804             :       // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_F32_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3805             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_F32_e64,
    3806             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3807             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3808             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3809             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3810             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3811             :       GIR_EraseFromParent, /*InsnID*/0,
    3812             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3813             :       // GIR_Coverage, 328,
    3814             :       GIR_Done,
    3815             :     // Label 280: @8916
    3816             :     GIM_Reject,
    3817             :     // Label 278: @8917
    3818             :     GIM_Try, /*On fail goto*//*Label 281*/ 8960, // Rule ID 332 //
    3819             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3820             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3821             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3822             :       // (fpround:{ *:[f32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F64_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3823             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_F64_e64,
    3824             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3825             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3826             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3827             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3828             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3829             :       GIR_EraseFromParent, /*InsnID*/0,
    3830             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3831             :       // GIR_Coverage, 332,
    3832             :       GIR_Done,
    3833             :     // Label 281: @8960
    3834             :     GIM_Reject,
    3835             :     // Label 279: @8961
    3836             :     GIM_Reject,
    3837             :     // Label 22: @8962
    3838             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 285*/ 9195,
    3839             :     /*GILLT_s1*//*Label 282*/ 8971,
    3840             :     /*GILLT_s16*//*Label 283*/ 9064,
    3841             :     /*GILLT_s32*//*Label 284*/ 9108,
    3842             :     // Label 282: @8971
    3843             :     GIM_Try, /*On fail goto*//*Label 286*/ 9017, // Rule ID 1736 //
    3844             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3845             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3846             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    3847             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3848             :       // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
    3849             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
    3850             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3851             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3852             :       GIR_AddImm, /*InsnID*/0, /*Imm*/3212836864,
    3853             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3854             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3855             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3856             :       GIR_EraseFromParent, /*InsnID*/0,
    3857             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3858             :       // GIR_Coverage, 1736,
    3859             :       GIR_Done,
    3860             :     // Label 286: @9017
    3861             :     GIM_Try, /*On fail goto*//*Label 287*/ 9063, // Rule ID 1738 //
    3862             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3863             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3864             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    3865             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3866             :       // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, -4616189618054758400:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
    3867             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
    3868             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3869             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3870             :       GIR_AddImm, /*InsnID*/0, /*Imm*/-4616189618054758400,
    3871             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3872             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3873             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3874             :       GIR_EraseFromParent, /*InsnID*/0,
    3875             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3876             :       // GIR_Coverage, 1738,
    3877             :       GIR_Done,
    3878             :     // Label 287: @9063
    3879             :     GIM_Reject,
    3880             :     // Label 283: @9064
    3881             :     GIM_Try, /*On fail goto*//*Label 288*/ 9107, // Rule ID 373 //
    3882             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3883             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3884             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3885             :       // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3886             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I16_F16_e64,
    3887             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3888             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3889             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3890             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3891             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3892             :       GIR_EraseFromParent, /*InsnID*/0,
    3893             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3894             :       // GIR_Coverage, 373,
    3895             :       GIR_Done,
    3896             :     // Label 288: @9107
    3897             :     GIM_Reject,
    3898             :     // Label 284: @9108
    3899             :     GIM_Try, /*On fail goto*//*Label 289*/ 9151, // Rule ID 322 //
    3900             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3901             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3902             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3903             :       // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3904             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F64_e64,
    3905             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3906             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3907             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3908             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3909             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3910             :       GIR_EraseFromParent, /*InsnID*/0,
    3911             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3912             :       // GIR_Coverage, 322,
    3913             :       GIR_Done,
    3914             :     // Label 289: @9151
    3915             :     GIM_Try, /*On fail goto*//*Label 290*/ 9194, // Rule ID 327 //
    3916             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3917             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3918             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3919             :       // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3920             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_I32_F32_e64,
    3921             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3922             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3923             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3924             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3925             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3926             :       GIR_EraseFromParent, /*InsnID*/0,
    3927             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3928             :       // GIR_Coverage, 327,
    3929             :       GIR_Done,
    3930             :     // Label 290: @9194
    3931             :     GIM_Reject,
    3932             :     // Label 285: @9195
    3933             :     GIM_Reject,
    3934             :     // Label 23: @9196
    3935             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 294*/ 9429,
    3936             :     /*GILLT_s1*//*Label 291*/ 9205,
    3937             :     /*GILLT_s16*//*Label 292*/ 9298,
    3938             :     /*GILLT_s32*//*Label 293*/ 9342,
    3939             :     // Label 291: @9205
    3940             :     GIM_Try, /*On fail goto*//*Label 295*/ 9251, // Rule ID 1735 //
    3941             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3942             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3943             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    3944             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3945             :       // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
    3946             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F32_e64,
    3947             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3948             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3949             :       GIR_AddImm, /*InsnID*/0, /*Imm*/1065353216,
    3950             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3951             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3952             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3953             :       GIR_EraseFromParent, /*InsnID*/0,
    3954             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3955             :       // GIR_Coverage, 1735,
    3956             :       GIR_Done,
    3957             :     // Label 295: @9251
    3958             :     GIM_Try, /*On fail goto*//*Label 296*/ 9297, // Rule ID 1737 //
    3959             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    3960             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    3961             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
    3962             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods,
    3963             :       // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
    3964             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CMP_EQ_F64_e64,
    3965             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sdst
    3966             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3967             :       GIR_AddImm, /*InsnID*/0, /*Imm*/4607182418800017408,
    3968             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3969             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3970             :       GIR_AddImm, /*InsnID*/0, /*Imm*/0,
    3971             :       GIR_EraseFromParent, /*InsnID*/0,
    3972             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3973             :       // GIR_Coverage, 1737,
    3974             :       GIR_Done,
    3975             :     // Label 296: @9297
    3976             :     GIM_Reject,
    3977             :     // Label 292: @9298
    3978             :     GIM_Try, /*On fail goto*//*Label 297*/ 9341, // Rule ID 372 //
    3979             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    3980             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3981             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    3982             :       // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    3983             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U16_F16_e64,
    3984             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    3985             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    3986             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    3987             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    3988             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    3989             :       GIR_EraseFromParent, /*InsnID*/0,
    3990             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    3991             :       // GIR_Coverage, 372,
    3992             :       GIR_Done,
    3993             :     // Label 297: @9341
    3994             :     GIM_Reject,
    3995             :     // Label 293: @9342
    3996             :     GIM_Try, /*On fail goto*//*Label 298*/ 9385, // Rule ID 326 //
    3997             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    3998             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    3999             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    4000             :       // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4001             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F32_e64,
    4002             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4003             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    4004             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4005             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    4006             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    4007             :       GIR_EraseFromParent, /*InsnID*/0,
    4008             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4009             :       // GIR_Coverage, 326,
    4010             :       GIR_Done,
    4011             :     // Label 298: @9385
    4012             :     GIM_Try, /*On fail goto*//*Label 299*/ 9428, // Rule ID 338 //
    4013             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
    4014             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    4015             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3mods0,
    4016             :       // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4017             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_U32_F64_e64,
    4018             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4019             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src0_modifiers
    4020             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4021             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
    4022             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/3, // omod
    4023             :       GIR_EraseFromParent, /*InsnID*/0,
    4024             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4025             :       // GIR_Coverage, 338,
    4026             :       GIR_Done,
    4027             :     // Label 299: @9428
    4028             :     GIM_Reject,
    4029             :     // Label 294: @9429
    4030             :     GIM_Reject,
    4031             :     // Label 24: @9430
    4032             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 303*/ 9559,
    4033             :     /*GILLT_s16*//*Label 300*/ 9439,
    4034             :     /*GILLT_s32*//*Label 301*/ 9479,
    4035             :     /*GILLT_s64*//*Label 302*/ 9519,
    4036             :     // Label 300: @9439
    4037             :     GIM_Try, /*On fail goto*//*Label 304*/ 9478, // Rule ID 371 //
    4038             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    4039             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    4040             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
    4041             :       // (sint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_I16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4042             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_I16_e64,
    4043             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4044             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4045             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
    4046             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
    4047             :       GIR_EraseFromParent, /*InsnID*/0,
    4048             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4049             :       // GIR_Coverage, 371,
    4050             :       GIR_Done,
    4051             :     // Label 304: @9478
    4052             :     GIM_Reject,
    4053             :     // Label 301: @9479
    4054             :     GIM_Try, /*On fail goto*//*Label 305*/ 9518, // Rule ID 324 //
    4055             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    4056             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    4057             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
    4058             :       // (sint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_I32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4059             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_I32_e64,
    4060             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4061             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4062             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
    4063             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
    4064             :       GIR_EraseFromParent, /*InsnID*/0,
    4065             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4066             :       // GIR_Coverage, 324,
    4067             :       GIR_Done,
    4068             :     // Label 305: @9518
    4069             :     GIM_Reject,
    4070             :     // Label 302: @9519
    4071             :     GIM_Try, /*On fail goto*//*Label 306*/ 9558, // Rule ID 323 //
    4072             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    4073             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    4074             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
    4075             :       // (sint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_I32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4076             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_I32_e64,
    4077             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4078             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4079             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
    4080             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
    4081             :       GIR_EraseFromParent, /*InsnID*/0,
    4082             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4083             :       // GIR_Coverage, 323,
    4084             :       GIR_Done,
    4085             :     // Label 306: @9558
    4086             :     GIM_Reject,
    4087             :     // Label 303: @9559
    4088             :     GIM_Reject,
    4089             :     // Label 25: @9560
    4090             :     GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 4, /*)*//*default:*//*Label 310*/ 9689,
    4091             :     /*GILLT_s16*//*Label 307*/ 9569,
    4092             :     /*GILLT_s32*//*Label 308*/ 9609,
    4093             :     /*GILLT_s64*//*Label 309*/ 9649,
    4094             :     // Label 307: @9569
    4095             :     GIM_Try, /*On fail goto*//*Label 311*/ 9608, // Rule ID 370 //
    4096             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
    4097             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    4098             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
    4099             :       // (uint_to_fp:{ *:[f16] } (VOP3OMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_U16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4100             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F16_U16_e64,
    4101             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4102             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4103             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
    4104             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
    4105             :       GIR_EraseFromParent, /*InsnID*/0,
    4106             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4107             :       // GIR_Coverage, 370,
    4108             :       GIR_Done,
    4109             :     // Label 311: @9608
    4110             :     GIM_Reject,
    4111             :     // Label 308: @9609
    4112             :     GIM_Try, /*On fail goto*//*Label 312*/ 9648, // Rule ID 325 //
    4113             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    4114             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
    4115             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
    4116             :       // (uint_to_fp:{ *:[f32] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_U32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4117             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F32_U32_e64,
    4118             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4119             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4120             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
    4121             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
    4122             :       GIR_EraseFromParent, /*InsnID*/0,
    4123             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4124             :       // GIR_Coverage, 325,
    4125             :       GIR_Done,
    4126             :     // Label 312: @9648
    4127             :     GIM_Reject,
    4128             :     // Label 309: @9649
    4129             :     GIM_Try, /*On fail goto*//*Label 313*/ 9688, // Rule ID 339 //
    4130             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    4131             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VReg_64RegClassID,
    4132             :       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_vop3omods,
    4133             :       // (uint_to_fp:{ *:[f64] } (VOP3OMods:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_U32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
    4134             :       GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_CVT_F64_U32_e64,
    4135             :       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
    4136             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
    4137             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
    4138             :       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // omod
    4139             :       GIR_EraseFromParent, /*InsnID*/0,
    4140             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4141             :       // GIR_Coverage, 339,
    4142             :       GIR_Done,
    4143             :     // Label 313: @9688
    4144             :     GIM_Reject,
    4145             :     // Label 310: @9689
    4146             :     GIM_Reject,
    4147             :     // Label 26: @9690
    4148             :     GIM_Try, /*On fail goto*//*Label 314*/ 9704, // Rule ID 52 //
    4149             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    4150             :       // MIs[0] simm16
    4151             :       GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
    4152             :       // (br (bb:{ *:[Other] }):$simm16)  =>  (S_BRANCH (bb:{ *:[Other] }):$simm16)
    4153             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BRANCH,
    4154             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4155             :       // GIR_Coverage, 52,
    4156             :       GIR_Done,
    4157             :     // Label 314: @9704
    4158             :     GIM_Reject,
    4159             :     // Label 27: @9705
    4160             :     GIM_Try, /*On fail goto*//*Label 315*/ 9731, // Rule ID 4 //
    4161             :       GIM_CheckFeatures, GIFBS_TruePredicate_isGCN,
    4162             :       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
    4163             :       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
    4164             :       GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
    4165             :       // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)  =>  (S_BCNT1_I32_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
    4166             :       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_BCNT1_I32_B32,
    4167             :       GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
    4168             :       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
    4169             :       // GIR_Coverage, 4,
    4170             :       GIR_Done,
    4171             :     // Label 315: @9731
    4172             :     GIM_Reject,
    4173             :     // Label 28: @9732
    4174             :     GIM_Reject,
    4175             :     };
    4176          56 :   return MatchTable0;
    4177             : }
    4178             : #endif // ifdef GET_GLOBALISEL_IMPL
    4179             : #ifdef GET_GLOBALISEL_PREDICATES_DECL
    4180             : PredicateBitset AvailableModuleFeatures;
    4181             : mutable PredicateBitset AvailableFunctionFeatures;
    4182             : PredicateBitset getAvailableFeatures() const {
    4183             :   return AvailableModuleFeatures | AvailableFunctionFeatures;
    4184             : }
    4185             : PredicateBitset
    4186             : computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const;
    4187             : PredicateBitset
    4188             : computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget,
    4189             :                                  const MachineFunction *MF) const;
    4190             : #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
    4191             : #ifdef GET_GLOBALISEL_PREDICATES_INIT
    4192        2492 : AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
    4193             : AvailableFunctionFeatures()
    4194             : #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT

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