Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Target Instruction Enum Values and Descriptors *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : #ifdef GET_INSTRINFO_ENUM
10 : #undef GET_INSTRINFO_ENUM
11 : namespace llvm {
12 :
13 : namespace AMDGPU {
14 : enum {
15 : PHI = 0,
16 : INLINEASM = 1,
17 : CFI_INSTRUCTION = 2,
18 : EH_LABEL = 3,
19 : GC_LABEL = 4,
20 : ANNOTATION_LABEL = 5,
21 : KILL = 6,
22 : EXTRACT_SUBREG = 7,
23 : INSERT_SUBREG = 8,
24 : IMPLICIT_DEF = 9,
25 : SUBREG_TO_REG = 10,
26 : COPY_TO_REGCLASS = 11,
27 : DBG_VALUE = 12,
28 : DBG_LABEL = 13,
29 : REG_SEQUENCE = 14,
30 : COPY = 15,
31 : BUNDLE = 16,
32 : LIFETIME_START = 17,
33 : LIFETIME_END = 18,
34 : STACKMAP = 19,
35 : FENTRY_CALL = 20,
36 : PATCHPOINT = 21,
37 : LOAD_STACK_GUARD = 22,
38 : STATEPOINT = 23,
39 : LOCAL_ESCAPE = 24,
40 : FAULTING_OP = 25,
41 : PATCHABLE_OP = 26,
42 : PATCHABLE_FUNCTION_ENTER = 27,
43 : PATCHABLE_RET = 28,
44 : PATCHABLE_FUNCTION_EXIT = 29,
45 : PATCHABLE_TAIL_CALL = 30,
46 : PATCHABLE_EVENT_CALL = 31,
47 : PATCHABLE_TYPED_EVENT_CALL = 32,
48 : ICALL_BRANCH_FUNNEL = 33,
49 : G_ADD = 34,
50 : G_SUB = 35,
51 : G_MUL = 36,
52 : G_SDIV = 37,
53 : G_UDIV = 38,
54 : G_SREM = 39,
55 : G_UREM = 40,
56 : G_AND = 41,
57 : G_OR = 42,
58 : G_XOR = 43,
59 : G_IMPLICIT_DEF = 44,
60 : G_PHI = 45,
61 : G_FRAME_INDEX = 46,
62 : G_GLOBAL_VALUE = 47,
63 : G_EXTRACT = 48,
64 : G_UNMERGE_VALUES = 49,
65 : G_INSERT = 50,
66 : G_MERGE_VALUES = 51,
67 : G_PTRTOINT = 52,
68 : G_INTTOPTR = 53,
69 : G_BITCAST = 54,
70 : G_INTRINSIC_TRUNC = 55,
71 : G_INTRINSIC_ROUND = 56,
72 : G_LOAD = 57,
73 : G_SEXTLOAD = 58,
74 : G_ZEXTLOAD = 59,
75 : G_STORE = 60,
76 : G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77 : G_ATOMIC_CMPXCHG = 62,
78 : G_ATOMICRMW_XCHG = 63,
79 : G_ATOMICRMW_ADD = 64,
80 : G_ATOMICRMW_SUB = 65,
81 : G_ATOMICRMW_AND = 66,
82 : G_ATOMICRMW_NAND = 67,
83 : G_ATOMICRMW_OR = 68,
84 : G_ATOMICRMW_XOR = 69,
85 : G_ATOMICRMW_MAX = 70,
86 : G_ATOMICRMW_MIN = 71,
87 : G_ATOMICRMW_UMAX = 72,
88 : G_ATOMICRMW_UMIN = 73,
89 : G_BRCOND = 74,
90 : G_BRINDIRECT = 75,
91 : G_INTRINSIC = 76,
92 : G_INTRINSIC_W_SIDE_EFFECTS = 77,
93 : G_ANYEXT = 78,
94 : G_TRUNC = 79,
95 : G_CONSTANT = 80,
96 : G_FCONSTANT = 81,
97 : G_VASTART = 82,
98 : G_VAARG = 83,
99 : G_SEXT = 84,
100 : G_ZEXT = 85,
101 : G_SHL = 86,
102 : G_LSHR = 87,
103 : G_ASHR = 88,
104 : G_ICMP = 89,
105 : G_FCMP = 90,
106 : G_SELECT = 91,
107 : G_UADDO = 92,
108 : G_UADDE = 93,
109 : G_USUBO = 94,
110 : G_USUBE = 95,
111 : G_SADDO = 96,
112 : G_SADDE = 97,
113 : G_SSUBO = 98,
114 : G_SSUBE = 99,
115 : G_UMULO = 100,
116 : G_SMULO = 101,
117 : G_UMULH = 102,
118 : G_SMULH = 103,
119 : G_FADD = 104,
120 : G_FSUB = 105,
121 : G_FMUL = 106,
122 : G_FMA = 107,
123 : G_FDIV = 108,
124 : G_FREM = 109,
125 : G_FPOW = 110,
126 : G_FEXP = 111,
127 : G_FEXP2 = 112,
128 : G_FLOG = 113,
129 : G_FLOG2 = 114,
130 : G_FNEG = 115,
131 : G_FPEXT = 116,
132 : G_FPTRUNC = 117,
133 : G_FPTOSI = 118,
134 : G_FPTOUI = 119,
135 : G_SITOFP = 120,
136 : G_UITOFP = 121,
137 : G_FABS = 122,
138 : G_GEP = 123,
139 : G_PTR_MASK = 124,
140 : G_BR = 125,
141 : G_INSERT_VECTOR_ELT = 126,
142 : G_EXTRACT_VECTOR_ELT = 127,
143 : G_SHUFFLE_VECTOR = 128,
144 : G_CTTZ = 129,
145 : G_CTTZ_ZERO_UNDEF = 130,
146 : G_CTLZ = 131,
147 : G_CTLZ_ZERO_UNDEF = 132,
148 : G_CTPOP = 133,
149 : G_BSWAP = 134,
150 : G_ADDRSPACE_CAST = 135,
151 : G_BLOCK_ADDR = 136,
152 : ADJCALLSTACKDOWN = 137,
153 : ADJCALLSTACKUP = 138,
154 : ATOMIC_FENCE = 139,
155 : BUFFER_ATOMIC_ADD_ADDR64 = 140,
156 : BUFFER_ATOMIC_ADD_ADDR64_RTN = 141,
157 : BUFFER_ATOMIC_ADD_BOTHEN = 142,
158 : BUFFER_ATOMIC_ADD_BOTHEN_RTN = 143,
159 : BUFFER_ATOMIC_ADD_IDXEN = 144,
160 : BUFFER_ATOMIC_ADD_IDXEN_RTN = 145,
161 : BUFFER_ATOMIC_ADD_OFFEN = 146,
162 : BUFFER_ATOMIC_ADD_OFFEN_RTN = 147,
163 : BUFFER_ATOMIC_ADD_OFFSET = 148,
164 : BUFFER_ATOMIC_ADD_OFFSET_RTN = 149,
165 : BUFFER_ATOMIC_ADD_X2_ADDR64 = 150,
166 : BUFFER_ATOMIC_ADD_X2_ADDR64_RTN = 151,
167 : BUFFER_ATOMIC_ADD_X2_BOTHEN = 152,
168 : BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN = 153,
169 : BUFFER_ATOMIC_ADD_X2_IDXEN = 154,
170 : BUFFER_ATOMIC_ADD_X2_IDXEN_RTN = 155,
171 : BUFFER_ATOMIC_ADD_X2_OFFEN = 156,
172 : BUFFER_ATOMIC_ADD_X2_OFFEN_RTN = 157,
173 : BUFFER_ATOMIC_ADD_X2_OFFSET = 158,
174 : BUFFER_ATOMIC_ADD_X2_OFFSET_RTN = 159,
175 : BUFFER_ATOMIC_AND_ADDR64 = 160,
176 : BUFFER_ATOMIC_AND_ADDR64_RTN = 161,
177 : BUFFER_ATOMIC_AND_BOTHEN = 162,
178 : BUFFER_ATOMIC_AND_BOTHEN_RTN = 163,
179 : BUFFER_ATOMIC_AND_IDXEN = 164,
180 : BUFFER_ATOMIC_AND_IDXEN_RTN = 165,
181 : BUFFER_ATOMIC_AND_OFFEN = 166,
182 : BUFFER_ATOMIC_AND_OFFEN_RTN = 167,
183 : BUFFER_ATOMIC_AND_OFFSET = 168,
184 : BUFFER_ATOMIC_AND_OFFSET_RTN = 169,
185 : BUFFER_ATOMIC_AND_X2_ADDR64 = 170,
186 : BUFFER_ATOMIC_AND_X2_ADDR64_RTN = 171,
187 : BUFFER_ATOMIC_AND_X2_BOTHEN = 172,
188 : BUFFER_ATOMIC_AND_X2_BOTHEN_RTN = 173,
189 : BUFFER_ATOMIC_AND_X2_IDXEN = 174,
190 : BUFFER_ATOMIC_AND_X2_IDXEN_RTN = 175,
191 : BUFFER_ATOMIC_AND_X2_OFFEN = 176,
192 : BUFFER_ATOMIC_AND_X2_OFFEN_RTN = 177,
193 : BUFFER_ATOMIC_AND_X2_OFFSET = 178,
194 : BUFFER_ATOMIC_AND_X2_OFFSET_RTN = 179,
195 : BUFFER_ATOMIC_CMPSWAP_ADDR64 = 180,
196 : BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN = 181,
197 : BUFFER_ATOMIC_CMPSWAP_BOTHEN = 182,
198 : BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN = 183,
199 : BUFFER_ATOMIC_CMPSWAP_IDXEN = 184,
200 : BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN = 185,
201 : BUFFER_ATOMIC_CMPSWAP_OFFEN = 186,
202 : BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN = 187,
203 : BUFFER_ATOMIC_CMPSWAP_OFFSET = 188,
204 : BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN = 189,
205 : BUFFER_ATOMIC_CMPSWAP_X2_ADDR64 = 190,
206 : BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN = 191,
207 : BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN = 192,
208 : BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN = 193,
209 : BUFFER_ATOMIC_CMPSWAP_X2_IDXEN = 194,
210 : BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN = 195,
211 : BUFFER_ATOMIC_CMPSWAP_X2_OFFEN = 196,
212 : BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN = 197,
213 : BUFFER_ATOMIC_CMPSWAP_X2_OFFSET = 198,
214 : BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN = 199,
215 : BUFFER_ATOMIC_DEC_ADDR64 = 200,
216 : BUFFER_ATOMIC_DEC_ADDR64_RTN = 201,
217 : BUFFER_ATOMIC_DEC_BOTHEN = 202,
218 : BUFFER_ATOMIC_DEC_BOTHEN_RTN = 203,
219 : BUFFER_ATOMIC_DEC_IDXEN = 204,
220 : BUFFER_ATOMIC_DEC_IDXEN_RTN = 205,
221 : BUFFER_ATOMIC_DEC_OFFEN = 206,
222 : BUFFER_ATOMIC_DEC_OFFEN_RTN = 207,
223 : BUFFER_ATOMIC_DEC_OFFSET = 208,
224 : BUFFER_ATOMIC_DEC_OFFSET_RTN = 209,
225 : BUFFER_ATOMIC_DEC_X2_ADDR64 = 210,
226 : BUFFER_ATOMIC_DEC_X2_ADDR64_RTN = 211,
227 : BUFFER_ATOMIC_DEC_X2_BOTHEN = 212,
228 : BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN = 213,
229 : BUFFER_ATOMIC_DEC_X2_IDXEN = 214,
230 : BUFFER_ATOMIC_DEC_X2_IDXEN_RTN = 215,
231 : BUFFER_ATOMIC_DEC_X2_OFFEN = 216,
232 : BUFFER_ATOMIC_DEC_X2_OFFEN_RTN = 217,
233 : BUFFER_ATOMIC_DEC_X2_OFFSET = 218,
234 : BUFFER_ATOMIC_DEC_X2_OFFSET_RTN = 219,
235 : BUFFER_ATOMIC_INC_ADDR64 = 220,
236 : BUFFER_ATOMIC_INC_ADDR64_RTN = 221,
237 : BUFFER_ATOMIC_INC_BOTHEN = 222,
238 : BUFFER_ATOMIC_INC_BOTHEN_RTN = 223,
239 : BUFFER_ATOMIC_INC_IDXEN = 224,
240 : BUFFER_ATOMIC_INC_IDXEN_RTN = 225,
241 : BUFFER_ATOMIC_INC_OFFEN = 226,
242 : BUFFER_ATOMIC_INC_OFFEN_RTN = 227,
243 : BUFFER_ATOMIC_INC_OFFSET = 228,
244 : BUFFER_ATOMIC_INC_OFFSET_RTN = 229,
245 : BUFFER_ATOMIC_INC_X2_ADDR64 = 230,
246 : BUFFER_ATOMIC_INC_X2_ADDR64_RTN = 231,
247 : BUFFER_ATOMIC_INC_X2_BOTHEN = 232,
248 : BUFFER_ATOMIC_INC_X2_BOTHEN_RTN = 233,
249 : BUFFER_ATOMIC_INC_X2_IDXEN = 234,
250 : BUFFER_ATOMIC_INC_X2_IDXEN_RTN = 235,
251 : BUFFER_ATOMIC_INC_X2_OFFEN = 236,
252 : BUFFER_ATOMIC_INC_X2_OFFEN_RTN = 237,
253 : BUFFER_ATOMIC_INC_X2_OFFSET = 238,
254 : BUFFER_ATOMIC_INC_X2_OFFSET_RTN = 239,
255 : BUFFER_ATOMIC_OR_ADDR64 = 240,
256 : BUFFER_ATOMIC_OR_ADDR64_RTN = 241,
257 : BUFFER_ATOMIC_OR_BOTHEN = 242,
258 : BUFFER_ATOMIC_OR_BOTHEN_RTN = 243,
259 : BUFFER_ATOMIC_OR_IDXEN = 244,
260 : BUFFER_ATOMIC_OR_IDXEN_RTN = 245,
261 : BUFFER_ATOMIC_OR_OFFEN = 246,
262 : BUFFER_ATOMIC_OR_OFFEN_RTN = 247,
263 : BUFFER_ATOMIC_OR_OFFSET = 248,
264 : BUFFER_ATOMIC_OR_OFFSET_RTN = 249,
265 : BUFFER_ATOMIC_OR_X2_ADDR64 = 250,
266 : BUFFER_ATOMIC_OR_X2_ADDR64_RTN = 251,
267 : BUFFER_ATOMIC_OR_X2_BOTHEN = 252,
268 : BUFFER_ATOMIC_OR_X2_BOTHEN_RTN = 253,
269 : BUFFER_ATOMIC_OR_X2_IDXEN = 254,
270 : BUFFER_ATOMIC_OR_X2_IDXEN_RTN = 255,
271 : BUFFER_ATOMIC_OR_X2_OFFEN = 256,
272 : BUFFER_ATOMIC_OR_X2_OFFEN_RTN = 257,
273 : BUFFER_ATOMIC_OR_X2_OFFSET = 258,
274 : BUFFER_ATOMIC_OR_X2_OFFSET_RTN = 259,
275 : BUFFER_ATOMIC_SMAX_ADDR64 = 260,
276 : BUFFER_ATOMIC_SMAX_ADDR64_RTN = 261,
277 : BUFFER_ATOMIC_SMAX_BOTHEN = 262,
278 : BUFFER_ATOMIC_SMAX_BOTHEN_RTN = 263,
279 : BUFFER_ATOMIC_SMAX_IDXEN = 264,
280 : BUFFER_ATOMIC_SMAX_IDXEN_RTN = 265,
281 : BUFFER_ATOMIC_SMAX_OFFEN = 266,
282 : BUFFER_ATOMIC_SMAX_OFFEN_RTN = 267,
283 : BUFFER_ATOMIC_SMAX_OFFSET = 268,
284 : BUFFER_ATOMIC_SMAX_OFFSET_RTN = 269,
285 : BUFFER_ATOMIC_SMAX_X2_ADDR64 = 270,
286 : BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN = 271,
287 : BUFFER_ATOMIC_SMAX_X2_BOTHEN = 272,
288 : BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN = 273,
289 : BUFFER_ATOMIC_SMAX_X2_IDXEN = 274,
290 : BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN = 275,
291 : BUFFER_ATOMIC_SMAX_X2_OFFEN = 276,
292 : BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN = 277,
293 : BUFFER_ATOMIC_SMAX_X2_OFFSET = 278,
294 : BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN = 279,
295 : BUFFER_ATOMIC_SMIN_ADDR64 = 280,
296 : BUFFER_ATOMIC_SMIN_ADDR64_RTN = 281,
297 : BUFFER_ATOMIC_SMIN_BOTHEN = 282,
298 : BUFFER_ATOMIC_SMIN_BOTHEN_RTN = 283,
299 : BUFFER_ATOMIC_SMIN_IDXEN = 284,
300 : BUFFER_ATOMIC_SMIN_IDXEN_RTN = 285,
301 : BUFFER_ATOMIC_SMIN_OFFEN = 286,
302 : BUFFER_ATOMIC_SMIN_OFFEN_RTN = 287,
303 : BUFFER_ATOMIC_SMIN_OFFSET = 288,
304 : BUFFER_ATOMIC_SMIN_OFFSET_RTN = 289,
305 : BUFFER_ATOMIC_SMIN_X2_ADDR64 = 290,
306 : BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN = 291,
307 : BUFFER_ATOMIC_SMIN_X2_BOTHEN = 292,
308 : BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN = 293,
309 : BUFFER_ATOMIC_SMIN_X2_IDXEN = 294,
310 : BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN = 295,
311 : BUFFER_ATOMIC_SMIN_X2_OFFEN = 296,
312 : BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN = 297,
313 : BUFFER_ATOMIC_SMIN_X2_OFFSET = 298,
314 : BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN = 299,
315 : BUFFER_ATOMIC_SUB_ADDR64 = 300,
316 : BUFFER_ATOMIC_SUB_ADDR64_RTN = 301,
317 : BUFFER_ATOMIC_SUB_BOTHEN = 302,
318 : BUFFER_ATOMIC_SUB_BOTHEN_RTN = 303,
319 : BUFFER_ATOMIC_SUB_IDXEN = 304,
320 : BUFFER_ATOMIC_SUB_IDXEN_RTN = 305,
321 : BUFFER_ATOMIC_SUB_OFFEN = 306,
322 : BUFFER_ATOMIC_SUB_OFFEN_RTN = 307,
323 : BUFFER_ATOMIC_SUB_OFFSET = 308,
324 : BUFFER_ATOMIC_SUB_OFFSET_RTN = 309,
325 : BUFFER_ATOMIC_SUB_X2_ADDR64 = 310,
326 : BUFFER_ATOMIC_SUB_X2_ADDR64_RTN = 311,
327 : BUFFER_ATOMIC_SUB_X2_BOTHEN = 312,
328 : BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN = 313,
329 : BUFFER_ATOMIC_SUB_X2_IDXEN = 314,
330 : BUFFER_ATOMIC_SUB_X2_IDXEN_RTN = 315,
331 : BUFFER_ATOMIC_SUB_X2_OFFEN = 316,
332 : BUFFER_ATOMIC_SUB_X2_OFFEN_RTN = 317,
333 : BUFFER_ATOMIC_SUB_X2_OFFSET = 318,
334 : BUFFER_ATOMIC_SUB_X2_OFFSET_RTN = 319,
335 : BUFFER_ATOMIC_SWAP_ADDR64 = 320,
336 : BUFFER_ATOMIC_SWAP_ADDR64_RTN = 321,
337 : BUFFER_ATOMIC_SWAP_BOTHEN = 322,
338 : BUFFER_ATOMIC_SWAP_BOTHEN_RTN = 323,
339 : BUFFER_ATOMIC_SWAP_IDXEN = 324,
340 : BUFFER_ATOMIC_SWAP_IDXEN_RTN = 325,
341 : BUFFER_ATOMIC_SWAP_OFFEN = 326,
342 : BUFFER_ATOMIC_SWAP_OFFEN_RTN = 327,
343 : BUFFER_ATOMIC_SWAP_OFFSET = 328,
344 : BUFFER_ATOMIC_SWAP_OFFSET_RTN = 329,
345 : BUFFER_ATOMIC_SWAP_X2_ADDR64 = 330,
346 : BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN = 331,
347 : BUFFER_ATOMIC_SWAP_X2_BOTHEN = 332,
348 : BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN = 333,
349 : BUFFER_ATOMIC_SWAP_X2_IDXEN = 334,
350 : BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN = 335,
351 : BUFFER_ATOMIC_SWAP_X2_OFFEN = 336,
352 : BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN = 337,
353 : BUFFER_ATOMIC_SWAP_X2_OFFSET = 338,
354 : BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN = 339,
355 : BUFFER_ATOMIC_UMAX_ADDR64 = 340,
356 : BUFFER_ATOMIC_UMAX_ADDR64_RTN = 341,
357 : BUFFER_ATOMIC_UMAX_BOTHEN = 342,
358 : BUFFER_ATOMIC_UMAX_BOTHEN_RTN = 343,
359 : BUFFER_ATOMIC_UMAX_IDXEN = 344,
360 : BUFFER_ATOMIC_UMAX_IDXEN_RTN = 345,
361 : BUFFER_ATOMIC_UMAX_OFFEN = 346,
362 : BUFFER_ATOMIC_UMAX_OFFEN_RTN = 347,
363 : BUFFER_ATOMIC_UMAX_OFFSET = 348,
364 : BUFFER_ATOMIC_UMAX_OFFSET_RTN = 349,
365 : BUFFER_ATOMIC_UMAX_X2_ADDR64 = 350,
366 : BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN = 351,
367 : BUFFER_ATOMIC_UMAX_X2_BOTHEN = 352,
368 : BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN = 353,
369 : BUFFER_ATOMIC_UMAX_X2_IDXEN = 354,
370 : BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN = 355,
371 : BUFFER_ATOMIC_UMAX_X2_OFFEN = 356,
372 : BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN = 357,
373 : BUFFER_ATOMIC_UMAX_X2_OFFSET = 358,
374 : BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN = 359,
375 : BUFFER_ATOMIC_UMIN_ADDR64 = 360,
376 : BUFFER_ATOMIC_UMIN_ADDR64_RTN = 361,
377 : BUFFER_ATOMIC_UMIN_BOTHEN = 362,
378 : BUFFER_ATOMIC_UMIN_BOTHEN_RTN = 363,
379 : BUFFER_ATOMIC_UMIN_IDXEN = 364,
380 : BUFFER_ATOMIC_UMIN_IDXEN_RTN = 365,
381 : BUFFER_ATOMIC_UMIN_OFFEN = 366,
382 : BUFFER_ATOMIC_UMIN_OFFEN_RTN = 367,
383 : BUFFER_ATOMIC_UMIN_OFFSET = 368,
384 : BUFFER_ATOMIC_UMIN_OFFSET_RTN = 369,
385 : BUFFER_ATOMIC_UMIN_X2_ADDR64 = 370,
386 : BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN = 371,
387 : BUFFER_ATOMIC_UMIN_X2_BOTHEN = 372,
388 : BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN = 373,
389 : BUFFER_ATOMIC_UMIN_X2_IDXEN = 374,
390 : BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN = 375,
391 : BUFFER_ATOMIC_UMIN_X2_OFFEN = 376,
392 : BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN = 377,
393 : BUFFER_ATOMIC_UMIN_X2_OFFSET = 378,
394 : BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN = 379,
395 : BUFFER_ATOMIC_XOR_ADDR64 = 380,
396 : BUFFER_ATOMIC_XOR_ADDR64_RTN = 381,
397 : BUFFER_ATOMIC_XOR_BOTHEN = 382,
398 : BUFFER_ATOMIC_XOR_BOTHEN_RTN = 383,
399 : BUFFER_ATOMIC_XOR_IDXEN = 384,
400 : BUFFER_ATOMIC_XOR_IDXEN_RTN = 385,
401 : BUFFER_ATOMIC_XOR_OFFEN = 386,
402 : BUFFER_ATOMIC_XOR_OFFEN_RTN = 387,
403 : BUFFER_ATOMIC_XOR_OFFSET = 388,
404 : BUFFER_ATOMIC_XOR_OFFSET_RTN = 389,
405 : BUFFER_ATOMIC_XOR_X2_ADDR64 = 390,
406 : BUFFER_ATOMIC_XOR_X2_ADDR64_RTN = 391,
407 : BUFFER_ATOMIC_XOR_X2_BOTHEN = 392,
408 : BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN = 393,
409 : BUFFER_ATOMIC_XOR_X2_IDXEN = 394,
410 : BUFFER_ATOMIC_XOR_X2_IDXEN_RTN = 395,
411 : BUFFER_ATOMIC_XOR_X2_OFFEN = 396,
412 : BUFFER_ATOMIC_XOR_X2_OFFEN_RTN = 397,
413 : BUFFER_ATOMIC_XOR_X2_OFFSET = 398,
414 : BUFFER_ATOMIC_XOR_X2_OFFSET_RTN = 399,
415 : BUFFER_LOAD_DWORDX2_ADDR64 = 400,
416 : BUFFER_LOAD_DWORDX2_BOTHEN = 401,
417 : BUFFER_LOAD_DWORDX2_BOTHEN_exact = 402,
418 : BUFFER_LOAD_DWORDX2_IDXEN = 403,
419 : BUFFER_LOAD_DWORDX2_IDXEN_exact = 404,
420 : BUFFER_LOAD_DWORDX2_LDS_ADDR64 = 405,
421 : BUFFER_LOAD_DWORDX2_LDS_BOTHEN = 406,
422 : BUFFER_LOAD_DWORDX2_LDS_BOTHEN_exact = 407,
423 : BUFFER_LOAD_DWORDX2_LDS_IDXEN = 408,
424 : BUFFER_LOAD_DWORDX2_LDS_IDXEN_exact = 409,
425 : BUFFER_LOAD_DWORDX2_LDS_OFFEN = 410,
426 : BUFFER_LOAD_DWORDX2_LDS_OFFEN_exact = 411,
427 : BUFFER_LOAD_DWORDX2_LDS_OFFSET = 412,
428 : BUFFER_LOAD_DWORDX2_LDS_OFFSET_exact = 413,
429 : BUFFER_LOAD_DWORDX2_OFFEN = 414,
430 : BUFFER_LOAD_DWORDX2_OFFEN_exact = 415,
431 : BUFFER_LOAD_DWORDX2_OFFSET = 416,
432 : BUFFER_LOAD_DWORDX2_OFFSET_exact = 417,
433 : BUFFER_LOAD_DWORDX3_ADDR64 = 418,
434 : BUFFER_LOAD_DWORDX3_BOTHEN = 419,
435 : BUFFER_LOAD_DWORDX3_BOTHEN_exact = 420,
436 : BUFFER_LOAD_DWORDX3_IDXEN = 421,
437 : BUFFER_LOAD_DWORDX3_IDXEN_exact = 422,
438 : BUFFER_LOAD_DWORDX3_LDS_ADDR64 = 423,
439 : BUFFER_LOAD_DWORDX3_LDS_BOTHEN = 424,
440 : BUFFER_LOAD_DWORDX3_LDS_BOTHEN_exact = 425,
441 : BUFFER_LOAD_DWORDX3_LDS_IDXEN = 426,
442 : BUFFER_LOAD_DWORDX3_LDS_IDXEN_exact = 427,
443 : BUFFER_LOAD_DWORDX3_LDS_OFFEN = 428,
444 : BUFFER_LOAD_DWORDX3_LDS_OFFEN_exact = 429,
445 : BUFFER_LOAD_DWORDX3_LDS_OFFSET = 430,
446 : BUFFER_LOAD_DWORDX3_LDS_OFFSET_exact = 431,
447 : BUFFER_LOAD_DWORDX3_OFFEN = 432,
448 : BUFFER_LOAD_DWORDX3_OFFEN_exact = 433,
449 : BUFFER_LOAD_DWORDX3_OFFSET = 434,
450 : BUFFER_LOAD_DWORDX3_OFFSET_exact = 435,
451 : BUFFER_LOAD_DWORDX4_ADDR64 = 436,
452 : BUFFER_LOAD_DWORDX4_BOTHEN = 437,
453 : BUFFER_LOAD_DWORDX4_BOTHEN_exact = 438,
454 : BUFFER_LOAD_DWORDX4_IDXEN = 439,
455 : BUFFER_LOAD_DWORDX4_IDXEN_exact = 440,
456 : BUFFER_LOAD_DWORDX4_LDS_ADDR64 = 441,
457 : BUFFER_LOAD_DWORDX4_LDS_BOTHEN = 442,
458 : BUFFER_LOAD_DWORDX4_LDS_BOTHEN_exact = 443,
459 : BUFFER_LOAD_DWORDX4_LDS_IDXEN = 444,
460 : BUFFER_LOAD_DWORDX4_LDS_IDXEN_exact = 445,
461 : BUFFER_LOAD_DWORDX4_LDS_OFFEN = 446,
462 : BUFFER_LOAD_DWORDX4_LDS_OFFEN_exact = 447,
463 : BUFFER_LOAD_DWORDX4_LDS_OFFSET = 448,
464 : BUFFER_LOAD_DWORDX4_LDS_OFFSET_exact = 449,
465 : BUFFER_LOAD_DWORDX4_OFFEN = 450,
466 : BUFFER_LOAD_DWORDX4_OFFEN_exact = 451,
467 : BUFFER_LOAD_DWORDX4_OFFSET = 452,
468 : BUFFER_LOAD_DWORDX4_OFFSET_exact = 453,
469 : BUFFER_LOAD_DWORD_ADDR64 = 454,
470 : BUFFER_LOAD_DWORD_BOTHEN = 455,
471 : BUFFER_LOAD_DWORD_BOTHEN_exact = 456,
472 : BUFFER_LOAD_DWORD_IDXEN = 457,
473 : BUFFER_LOAD_DWORD_IDXEN_exact = 458,
474 : BUFFER_LOAD_DWORD_LDS_ADDR64 = 459,
475 : BUFFER_LOAD_DWORD_LDS_BOTHEN = 460,
476 : BUFFER_LOAD_DWORD_LDS_BOTHEN_exact = 461,
477 : BUFFER_LOAD_DWORD_LDS_IDXEN = 462,
478 : BUFFER_LOAD_DWORD_LDS_IDXEN_exact = 463,
479 : BUFFER_LOAD_DWORD_LDS_OFFEN = 464,
480 : BUFFER_LOAD_DWORD_LDS_OFFEN_exact = 465,
481 : BUFFER_LOAD_DWORD_LDS_OFFSET = 466,
482 : BUFFER_LOAD_DWORD_LDS_OFFSET_exact = 467,
483 : BUFFER_LOAD_DWORD_OFFEN = 468,
484 : BUFFER_LOAD_DWORD_OFFEN_exact = 469,
485 : BUFFER_LOAD_DWORD_OFFSET = 470,
486 : BUFFER_LOAD_DWORD_OFFSET_exact = 471,
487 : BUFFER_LOAD_FORMAT_D16_HI_X_ADDR64 = 472,
488 : BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN = 473,
489 : BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_exact = 474,
490 : BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN = 475,
491 : BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_exact = 476,
492 : BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN = 477,
493 : BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_exact = 478,
494 : BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET = 479,
495 : BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_exact = 480,
496 : BUFFER_LOAD_FORMAT_D16_XYZW_ADDR64 = 481,
497 : BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN = 482,
498 : BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_exact = 483,
499 : BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN = 484,
500 : BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_exact = 485,
501 : BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN = 486,
502 : BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_exact = 487,
503 : BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET = 488,
504 : BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_exact = 489,
505 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_ADDR64 = 490,
506 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN = 491,
507 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_exact = 492,
508 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN = 493,
509 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_exact = 494,
510 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN = 495,
511 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_exact = 496,
512 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET = 497,
513 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_exact = 498,
514 : BUFFER_LOAD_FORMAT_D16_XYZ_ADDR64 = 499,
515 : BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN = 500,
516 : BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_exact = 501,
517 : BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN = 502,
518 : BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_exact = 503,
519 : BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN = 504,
520 : BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_exact = 505,
521 : BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET = 506,
522 : BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_exact = 507,
523 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_ADDR64 = 508,
524 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN = 509,
525 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_exact = 510,
526 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN = 511,
527 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_exact = 512,
528 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN = 513,
529 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_exact = 514,
530 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET = 515,
531 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_exact = 516,
532 : BUFFER_LOAD_FORMAT_D16_XY_ADDR64 = 517,
533 : BUFFER_LOAD_FORMAT_D16_XY_BOTHEN = 518,
534 : BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_exact = 519,
535 : BUFFER_LOAD_FORMAT_D16_XY_IDXEN = 520,
536 : BUFFER_LOAD_FORMAT_D16_XY_IDXEN_exact = 521,
537 : BUFFER_LOAD_FORMAT_D16_XY_OFFEN = 522,
538 : BUFFER_LOAD_FORMAT_D16_XY_OFFEN_exact = 523,
539 : BUFFER_LOAD_FORMAT_D16_XY_OFFSET = 524,
540 : BUFFER_LOAD_FORMAT_D16_XY_OFFSET_exact = 525,
541 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_ADDR64 = 526,
542 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN = 527,
543 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_exact = 528,
544 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN = 529,
545 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_exact = 530,
546 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN = 531,
547 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_exact = 532,
548 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET = 533,
549 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_exact = 534,
550 : BUFFER_LOAD_FORMAT_D16_X_ADDR64 = 535,
551 : BUFFER_LOAD_FORMAT_D16_X_BOTHEN = 536,
552 : BUFFER_LOAD_FORMAT_D16_X_BOTHEN_exact = 537,
553 : BUFFER_LOAD_FORMAT_D16_X_IDXEN = 538,
554 : BUFFER_LOAD_FORMAT_D16_X_IDXEN_exact = 539,
555 : BUFFER_LOAD_FORMAT_D16_X_OFFEN = 540,
556 : BUFFER_LOAD_FORMAT_D16_X_OFFEN_exact = 541,
557 : BUFFER_LOAD_FORMAT_D16_X_OFFSET = 542,
558 : BUFFER_LOAD_FORMAT_D16_X_OFFSET_exact = 543,
559 : BUFFER_LOAD_FORMAT_D16_X_gfx80_ADDR64 = 544,
560 : BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN = 545,
561 : BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_exact = 546,
562 : BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN = 547,
563 : BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_exact = 548,
564 : BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN = 549,
565 : BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_exact = 550,
566 : BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET = 551,
567 : BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_exact = 552,
568 : BUFFER_LOAD_FORMAT_XYZW_ADDR64 = 553,
569 : BUFFER_LOAD_FORMAT_XYZW_BOTHEN = 554,
570 : BUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact = 555,
571 : BUFFER_LOAD_FORMAT_XYZW_IDXEN = 556,
572 : BUFFER_LOAD_FORMAT_XYZW_IDXEN_exact = 557,
573 : BUFFER_LOAD_FORMAT_XYZW_OFFEN = 558,
574 : BUFFER_LOAD_FORMAT_XYZW_OFFEN_exact = 559,
575 : BUFFER_LOAD_FORMAT_XYZW_OFFSET = 560,
576 : BUFFER_LOAD_FORMAT_XYZW_OFFSET_exact = 561,
577 : BUFFER_LOAD_FORMAT_XYZ_ADDR64 = 562,
578 : BUFFER_LOAD_FORMAT_XYZ_BOTHEN = 563,
579 : BUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact = 564,
580 : BUFFER_LOAD_FORMAT_XYZ_IDXEN = 565,
581 : BUFFER_LOAD_FORMAT_XYZ_IDXEN_exact = 566,
582 : BUFFER_LOAD_FORMAT_XYZ_OFFEN = 567,
583 : BUFFER_LOAD_FORMAT_XYZ_OFFEN_exact = 568,
584 : BUFFER_LOAD_FORMAT_XYZ_OFFSET = 569,
585 : BUFFER_LOAD_FORMAT_XYZ_OFFSET_exact = 570,
586 : BUFFER_LOAD_FORMAT_XY_ADDR64 = 571,
587 : BUFFER_LOAD_FORMAT_XY_BOTHEN = 572,
588 : BUFFER_LOAD_FORMAT_XY_BOTHEN_exact = 573,
589 : BUFFER_LOAD_FORMAT_XY_IDXEN = 574,
590 : BUFFER_LOAD_FORMAT_XY_IDXEN_exact = 575,
591 : BUFFER_LOAD_FORMAT_XY_OFFEN = 576,
592 : BUFFER_LOAD_FORMAT_XY_OFFEN_exact = 577,
593 : BUFFER_LOAD_FORMAT_XY_OFFSET = 578,
594 : BUFFER_LOAD_FORMAT_XY_OFFSET_exact = 579,
595 : BUFFER_LOAD_FORMAT_X_ADDR64 = 580,
596 : BUFFER_LOAD_FORMAT_X_BOTHEN = 581,
597 : BUFFER_LOAD_FORMAT_X_BOTHEN_exact = 582,
598 : BUFFER_LOAD_FORMAT_X_IDXEN = 583,
599 : BUFFER_LOAD_FORMAT_X_IDXEN_exact = 584,
600 : BUFFER_LOAD_FORMAT_X_LDS_ADDR64 = 585,
601 : BUFFER_LOAD_FORMAT_X_LDS_BOTHEN = 586,
602 : BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_exact = 587,
603 : BUFFER_LOAD_FORMAT_X_LDS_IDXEN = 588,
604 : BUFFER_LOAD_FORMAT_X_LDS_IDXEN_exact = 589,
605 : BUFFER_LOAD_FORMAT_X_LDS_OFFEN = 590,
606 : BUFFER_LOAD_FORMAT_X_LDS_OFFEN_exact = 591,
607 : BUFFER_LOAD_FORMAT_X_LDS_OFFSET = 592,
608 : BUFFER_LOAD_FORMAT_X_LDS_OFFSET_exact = 593,
609 : BUFFER_LOAD_FORMAT_X_OFFEN = 594,
610 : BUFFER_LOAD_FORMAT_X_OFFEN_exact = 595,
611 : BUFFER_LOAD_FORMAT_X_OFFSET = 596,
612 : BUFFER_LOAD_FORMAT_X_OFFSET_exact = 597,
613 : BUFFER_LOAD_SBYTE_ADDR64 = 598,
614 : BUFFER_LOAD_SBYTE_BOTHEN = 599,
615 : BUFFER_LOAD_SBYTE_BOTHEN_exact = 600,
616 : BUFFER_LOAD_SBYTE_D16_ADDR64 = 601,
617 : BUFFER_LOAD_SBYTE_D16_BOTHEN = 602,
618 : BUFFER_LOAD_SBYTE_D16_BOTHEN_exact = 603,
619 : BUFFER_LOAD_SBYTE_D16_HI_ADDR64 = 604,
620 : BUFFER_LOAD_SBYTE_D16_HI_BOTHEN = 605,
621 : BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_exact = 606,
622 : BUFFER_LOAD_SBYTE_D16_HI_IDXEN = 607,
623 : BUFFER_LOAD_SBYTE_D16_HI_IDXEN_exact = 608,
624 : BUFFER_LOAD_SBYTE_D16_HI_OFFEN = 609,
625 : BUFFER_LOAD_SBYTE_D16_HI_OFFEN_exact = 610,
626 : BUFFER_LOAD_SBYTE_D16_HI_OFFSET = 611,
627 : BUFFER_LOAD_SBYTE_D16_HI_OFFSET_exact = 612,
628 : BUFFER_LOAD_SBYTE_D16_IDXEN = 613,
629 : BUFFER_LOAD_SBYTE_D16_IDXEN_exact = 614,
630 : BUFFER_LOAD_SBYTE_D16_OFFEN = 615,
631 : BUFFER_LOAD_SBYTE_D16_OFFEN_exact = 616,
632 : BUFFER_LOAD_SBYTE_D16_OFFSET = 617,
633 : BUFFER_LOAD_SBYTE_D16_OFFSET_exact = 618,
634 : BUFFER_LOAD_SBYTE_IDXEN = 619,
635 : BUFFER_LOAD_SBYTE_IDXEN_exact = 620,
636 : BUFFER_LOAD_SBYTE_LDS_ADDR64 = 621,
637 : BUFFER_LOAD_SBYTE_LDS_BOTHEN = 622,
638 : BUFFER_LOAD_SBYTE_LDS_BOTHEN_exact = 623,
639 : BUFFER_LOAD_SBYTE_LDS_IDXEN = 624,
640 : BUFFER_LOAD_SBYTE_LDS_IDXEN_exact = 625,
641 : BUFFER_LOAD_SBYTE_LDS_OFFEN = 626,
642 : BUFFER_LOAD_SBYTE_LDS_OFFEN_exact = 627,
643 : BUFFER_LOAD_SBYTE_LDS_OFFSET = 628,
644 : BUFFER_LOAD_SBYTE_LDS_OFFSET_exact = 629,
645 : BUFFER_LOAD_SBYTE_OFFEN = 630,
646 : BUFFER_LOAD_SBYTE_OFFEN_exact = 631,
647 : BUFFER_LOAD_SBYTE_OFFSET = 632,
648 : BUFFER_LOAD_SBYTE_OFFSET_exact = 633,
649 : BUFFER_LOAD_SHORT_D16_ADDR64 = 634,
650 : BUFFER_LOAD_SHORT_D16_BOTHEN = 635,
651 : BUFFER_LOAD_SHORT_D16_BOTHEN_exact = 636,
652 : BUFFER_LOAD_SHORT_D16_HI_ADDR64 = 637,
653 : BUFFER_LOAD_SHORT_D16_HI_BOTHEN = 638,
654 : BUFFER_LOAD_SHORT_D16_HI_BOTHEN_exact = 639,
655 : BUFFER_LOAD_SHORT_D16_HI_IDXEN = 640,
656 : BUFFER_LOAD_SHORT_D16_HI_IDXEN_exact = 641,
657 : BUFFER_LOAD_SHORT_D16_HI_OFFEN = 642,
658 : BUFFER_LOAD_SHORT_D16_HI_OFFEN_exact = 643,
659 : BUFFER_LOAD_SHORT_D16_HI_OFFSET = 644,
660 : BUFFER_LOAD_SHORT_D16_HI_OFFSET_exact = 645,
661 : BUFFER_LOAD_SHORT_D16_IDXEN = 646,
662 : BUFFER_LOAD_SHORT_D16_IDXEN_exact = 647,
663 : BUFFER_LOAD_SHORT_D16_OFFEN = 648,
664 : BUFFER_LOAD_SHORT_D16_OFFEN_exact = 649,
665 : BUFFER_LOAD_SHORT_D16_OFFSET = 650,
666 : BUFFER_LOAD_SHORT_D16_OFFSET_exact = 651,
667 : BUFFER_LOAD_SSHORT_ADDR64 = 652,
668 : BUFFER_LOAD_SSHORT_BOTHEN = 653,
669 : BUFFER_LOAD_SSHORT_BOTHEN_exact = 654,
670 : BUFFER_LOAD_SSHORT_IDXEN = 655,
671 : BUFFER_LOAD_SSHORT_IDXEN_exact = 656,
672 : BUFFER_LOAD_SSHORT_LDS_ADDR64 = 657,
673 : BUFFER_LOAD_SSHORT_LDS_BOTHEN = 658,
674 : BUFFER_LOAD_SSHORT_LDS_BOTHEN_exact = 659,
675 : BUFFER_LOAD_SSHORT_LDS_IDXEN = 660,
676 : BUFFER_LOAD_SSHORT_LDS_IDXEN_exact = 661,
677 : BUFFER_LOAD_SSHORT_LDS_OFFEN = 662,
678 : BUFFER_LOAD_SSHORT_LDS_OFFEN_exact = 663,
679 : BUFFER_LOAD_SSHORT_LDS_OFFSET = 664,
680 : BUFFER_LOAD_SSHORT_LDS_OFFSET_exact = 665,
681 : BUFFER_LOAD_SSHORT_OFFEN = 666,
682 : BUFFER_LOAD_SSHORT_OFFEN_exact = 667,
683 : BUFFER_LOAD_SSHORT_OFFSET = 668,
684 : BUFFER_LOAD_SSHORT_OFFSET_exact = 669,
685 : BUFFER_LOAD_UBYTE_ADDR64 = 670,
686 : BUFFER_LOAD_UBYTE_BOTHEN = 671,
687 : BUFFER_LOAD_UBYTE_BOTHEN_exact = 672,
688 : BUFFER_LOAD_UBYTE_D16_ADDR64 = 673,
689 : BUFFER_LOAD_UBYTE_D16_BOTHEN = 674,
690 : BUFFER_LOAD_UBYTE_D16_BOTHEN_exact = 675,
691 : BUFFER_LOAD_UBYTE_D16_HI_ADDR64 = 676,
692 : BUFFER_LOAD_UBYTE_D16_HI_BOTHEN = 677,
693 : BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_exact = 678,
694 : BUFFER_LOAD_UBYTE_D16_HI_IDXEN = 679,
695 : BUFFER_LOAD_UBYTE_D16_HI_IDXEN_exact = 680,
696 : BUFFER_LOAD_UBYTE_D16_HI_OFFEN = 681,
697 : BUFFER_LOAD_UBYTE_D16_HI_OFFEN_exact = 682,
698 : BUFFER_LOAD_UBYTE_D16_HI_OFFSET = 683,
699 : BUFFER_LOAD_UBYTE_D16_HI_OFFSET_exact = 684,
700 : BUFFER_LOAD_UBYTE_D16_IDXEN = 685,
701 : BUFFER_LOAD_UBYTE_D16_IDXEN_exact = 686,
702 : BUFFER_LOAD_UBYTE_D16_OFFEN = 687,
703 : BUFFER_LOAD_UBYTE_D16_OFFEN_exact = 688,
704 : BUFFER_LOAD_UBYTE_D16_OFFSET = 689,
705 : BUFFER_LOAD_UBYTE_D16_OFFSET_exact = 690,
706 : BUFFER_LOAD_UBYTE_IDXEN = 691,
707 : BUFFER_LOAD_UBYTE_IDXEN_exact = 692,
708 : BUFFER_LOAD_UBYTE_LDS_ADDR64 = 693,
709 : BUFFER_LOAD_UBYTE_LDS_BOTHEN = 694,
710 : BUFFER_LOAD_UBYTE_LDS_BOTHEN_exact = 695,
711 : BUFFER_LOAD_UBYTE_LDS_IDXEN = 696,
712 : BUFFER_LOAD_UBYTE_LDS_IDXEN_exact = 697,
713 : BUFFER_LOAD_UBYTE_LDS_OFFEN = 698,
714 : BUFFER_LOAD_UBYTE_LDS_OFFEN_exact = 699,
715 : BUFFER_LOAD_UBYTE_LDS_OFFSET = 700,
716 : BUFFER_LOAD_UBYTE_LDS_OFFSET_exact = 701,
717 : BUFFER_LOAD_UBYTE_OFFEN = 702,
718 : BUFFER_LOAD_UBYTE_OFFEN_exact = 703,
719 : BUFFER_LOAD_UBYTE_OFFSET = 704,
720 : BUFFER_LOAD_UBYTE_OFFSET_exact = 705,
721 : BUFFER_LOAD_USHORT_ADDR64 = 706,
722 : BUFFER_LOAD_USHORT_BOTHEN = 707,
723 : BUFFER_LOAD_USHORT_BOTHEN_exact = 708,
724 : BUFFER_LOAD_USHORT_IDXEN = 709,
725 : BUFFER_LOAD_USHORT_IDXEN_exact = 710,
726 : BUFFER_LOAD_USHORT_LDS_ADDR64 = 711,
727 : BUFFER_LOAD_USHORT_LDS_BOTHEN = 712,
728 : BUFFER_LOAD_USHORT_LDS_BOTHEN_exact = 713,
729 : BUFFER_LOAD_USHORT_LDS_IDXEN = 714,
730 : BUFFER_LOAD_USHORT_LDS_IDXEN_exact = 715,
731 : BUFFER_LOAD_USHORT_LDS_OFFEN = 716,
732 : BUFFER_LOAD_USHORT_LDS_OFFEN_exact = 717,
733 : BUFFER_LOAD_USHORT_LDS_OFFSET = 718,
734 : BUFFER_LOAD_USHORT_LDS_OFFSET_exact = 719,
735 : BUFFER_LOAD_USHORT_OFFEN = 720,
736 : BUFFER_LOAD_USHORT_OFFEN_exact = 721,
737 : BUFFER_LOAD_USHORT_OFFSET = 722,
738 : BUFFER_LOAD_USHORT_OFFSET_exact = 723,
739 : BUFFER_STORE_BYTE_ADDR64 = 724,
740 : BUFFER_STORE_BYTE_BOTHEN = 725,
741 : BUFFER_STORE_BYTE_BOTHEN_exact = 726,
742 : BUFFER_STORE_BYTE_D16_HI_ADDR64 = 727,
743 : BUFFER_STORE_BYTE_D16_HI_BOTHEN = 728,
744 : BUFFER_STORE_BYTE_D16_HI_BOTHEN_exact = 729,
745 : BUFFER_STORE_BYTE_D16_HI_IDXEN = 730,
746 : BUFFER_STORE_BYTE_D16_HI_IDXEN_exact = 731,
747 : BUFFER_STORE_BYTE_D16_HI_OFFEN = 732,
748 : BUFFER_STORE_BYTE_D16_HI_OFFEN_exact = 733,
749 : BUFFER_STORE_BYTE_D16_HI_OFFSET = 734,
750 : BUFFER_STORE_BYTE_D16_HI_OFFSET_exact = 735,
751 : BUFFER_STORE_BYTE_IDXEN = 736,
752 : BUFFER_STORE_BYTE_IDXEN_exact = 737,
753 : BUFFER_STORE_BYTE_OFFEN = 738,
754 : BUFFER_STORE_BYTE_OFFEN_exact = 739,
755 : BUFFER_STORE_BYTE_OFFSET = 740,
756 : BUFFER_STORE_BYTE_OFFSET_exact = 741,
757 : BUFFER_STORE_DWORDX2_ADDR64 = 742,
758 : BUFFER_STORE_DWORDX2_BOTHEN = 743,
759 : BUFFER_STORE_DWORDX2_BOTHEN_exact = 744,
760 : BUFFER_STORE_DWORDX2_IDXEN = 745,
761 : BUFFER_STORE_DWORDX2_IDXEN_exact = 746,
762 : BUFFER_STORE_DWORDX2_OFFEN = 747,
763 : BUFFER_STORE_DWORDX2_OFFEN_exact = 748,
764 : BUFFER_STORE_DWORDX2_OFFSET = 749,
765 : BUFFER_STORE_DWORDX2_OFFSET_exact = 750,
766 : BUFFER_STORE_DWORDX3_ADDR64 = 751,
767 : BUFFER_STORE_DWORDX3_BOTHEN = 752,
768 : BUFFER_STORE_DWORDX3_BOTHEN_exact = 753,
769 : BUFFER_STORE_DWORDX3_IDXEN = 754,
770 : BUFFER_STORE_DWORDX3_IDXEN_exact = 755,
771 : BUFFER_STORE_DWORDX3_OFFEN = 756,
772 : BUFFER_STORE_DWORDX3_OFFEN_exact = 757,
773 : BUFFER_STORE_DWORDX3_OFFSET = 758,
774 : BUFFER_STORE_DWORDX3_OFFSET_exact = 759,
775 : BUFFER_STORE_DWORDX4_ADDR64 = 760,
776 : BUFFER_STORE_DWORDX4_BOTHEN = 761,
777 : BUFFER_STORE_DWORDX4_BOTHEN_exact = 762,
778 : BUFFER_STORE_DWORDX4_IDXEN = 763,
779 : BUFFER_STORE_DWORDX4_IDXEN_exact = 764,
780 : BUFFER_STORE_DWORDX4_OFFEN = 765,
781 : BUFFER_STORE_DWORDX4_OFFEN_exact = 766,
782 : BUFFER_STORE_DWORDX4_OFFSET = 767,
783 : BUFFER_STORE_DWORDX4_OFFSET_exact = 768,
784 : BUFFER_STORE_DWORD_ADDR64 = 769,
785 : BUFFER_STORE_DWORD_BOTHEN = 770,
786 : BUFFER_STORE_DWORD_BOTHEN_exact = 771,
787 : BUFFER_STORE_DWORD_IDXEN = 772,
788 : BUFFER_STORE_DWORD_IDXEN_exact = 773,
789 : BUFFER_STORE_DWORD_OFFEN = 774,
790 : BUFFER_STORE_DWORD_OFFEN_exact = 775,
791 : BUFFER_STORE_DWORD_OFFSET = 776,
792 : BUFFER_STORE_DWORD_OFFSET_exact = 777,
793 : BUFFER_STORE_FORMAT_D16_HI_X_ADDR64 = 778,
794 : BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN = 779,
795 : BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_exact = 780,
796 : BUFFER_STORE_FORMAT_D16_HI_X_IDXEN = 781,
797 : BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_exact = 782,
798 : BUFFER_STORE_FORMAT_D16_HI_X_OFFEN = 783,
799 : BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_exact = 784,
800 : BUFFER_STORE_FORMAT_D16_HI_X_OFFSET = 785,
801 : BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_exact = 786,
802 : BUFFER_STORE_FORMAT_D16_XYZW_ADDR64 = 787,
803 : BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN = 788,
804 : BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact = 789,
805 : BUFFER_STORE_FORMAT_D16_XYZW_IDXEN = 790,
806 : BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact = 791,
807 : BUFFER_STORE_FORMAT_D16_XYZW_OFFEN = 792,
808 : BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact = 793,
809 : BUFFER_STORE_FORMAT_D16_XYZW_OFFSET = 794,
810 : BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact = 795,
811 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_ADDR64 = 796,
812 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN = 797,
813 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact = 798,
814 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN = 799,
815 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact = 800,
816 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN = 801,
817 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact = 802,
818 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET = 803,
819 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact = 804,
820 : BUFFER_STORE_FORMAT_D16_XYZ_ADDR64 = 805,
821 : BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN = 806,
822 : BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact = 807,
823 : BUFFER_STORE_FORMAT_D16_XYZ_IDXEN = 808,
824 : BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_exact = 809,
825 : BUFFER_STORE_FORMAT_D16_XYZ_OFFEN = 810,
826 : BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact = 811,
827 : BUFFER_STORE_FORMAT_D16_XYZ_OFFSET = 812,
828 : BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_exact = 813,
829 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_ADDR64 = 814,
830 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN = 815,
831 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact = 816,
832 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN = 817,
833 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact = 818,
834 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN = 819,
835 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact = 820,
836 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET = 821,
837 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact = 822,
838 : BUFFER_STORE_FORMAT_D16_XY_ADDR64 = 823,
839 : BUFFER_STORE_FORMAT_D16_XY_BOTHEN = 824,
840 : BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact = 825,
841 : BUFFER_STORE_FORMAT_D16_XY_IDXEN = 826,
842 : BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact = 827,
843 : BUFFER_STORE_FORMAT_D16_XY_OFFEN = 828,
844 : BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact = 829,
845 : BUFFER_STORE_FORMAT_D16_XY_OFFSET = 830,
846 : BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact = 831,
847 : BUFFER_STORE_FORMAT_D16_XY_gfx80_ADDR64 = 832,
848 : BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN = 833,
849 : BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact = 834,
850 : BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN = 835,
851 : BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact = 836,
852 : BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN = 837,
853 : BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact = 838,
854 : BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET = 839,
855 : BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact = 840,
856 : BUFFER_STORE_FORMAT_D16_X_ADDR64 = 841,
857 : BUFFER_STORE_FORMAT_D16_X_BOTHEN = 842,
858 : BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact = 843,
859 : BUFFER_STORE_FORMAT_D16_X_IDXEN = 844,
860 : BUFFER_STORE_FORMAT_D16_X_IDXEN_exact = 845,
861 : BUFFER_STORE_FORMAT_D16_X_OFFEN = 846,
862 : BUFFER_STORE_FORMAT_D16_X_OFFEN_exact = 847,
863 : BUFFER_STORE_FORMAT_D16_X_OFFSET = 848,
864 : BUFFER_STORE_FORMAT_D16_X_OFFSET_exact = 849,
865 : BUFFER_STORE_FORMAT_D16_X_gfx80_ADDR64 = 850,
866 : BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN = 851,
867 : BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact = 852,
868 : BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN = 853,
869 : BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact = 854,
870 : BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN = 855,
871 : BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact = 856,
872 : BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET = 857,
873 : BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact = 858,
874 : BUFFER_STORE_FORMAT_XYZW_ADDR64 = 859,
875 : BUFFER_STORE_FORMAT_XYZW_BOTHEN = 860,
876 : BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact = 861,
877 : BUFFER_STORE_FORMAT_XYZW_IDXEN = 862,
878 : BUFFER_STORE_FORMAT_XYZW_IDXEN_exact = 863,
879 : BUFFER_STORE_FORMAT_XYZW_OFFEN = 864,
880 : BUFFER_STORE_FORMAT_XYZW_OFFEN_exact = 865,
881 : BUFFER_STORE_FORMAT_XYZW_OFFSET = 866,
882 : BUFFER_STORE_FORMAT_XYZW_OFFSET_exact = 867,
883 : BUFFER_STORE_FORMAT_XYZ_ADDR64 = 868,
884 : BUFFER_STORE_FORMAT_XYZ_BOTHEN = 869,
885 : BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact = 870,
886 : BUFFER_STORE_FORMAT_XYZ_IDXEN = 871,
887 : BUFFER_STORE_FORMAT_XYZ_IDXEN_exact = 872,
888 : BUFFER_STORE_FORMAT_XYZ_OFFEN = 873,
889 : BUFFER_STORE_FORMAT_XYZ_OFFEN_exact = 874,
890 : BUFFER_STORE_FORMAT_XYZ_OFFSET = 875,
891 : BUFFER_STORE_FORMAT_XYZ_OFFSET_exact = 876,
892 : BUFFER_STORE_FORMAT_XY_ADDR64 = 877,
893 : BUFFER_STORE_FORMAT_XY_BOTHEN = 878,
894 : BUFFER_STORE_FORMAT_XY_BOTHEN_exact = 879,
895 : BUFFER_STORE_FORMAT_XY_IDXEN = 880,
896 : BUFFER_STORE_FORMAT_XY_IDXEN_exact = 881,
897 : BUFFER_STORE_FORMAT_XY_OFFEN = 882,
898 : BUFFER_STORE_FORMAT_XY_OFFEN_exact = 883,
899 : BUFFER_STORE_FORMAT_XY_OFFSET = 884,
900 : BUFFER_STORE_FORMAT_XY_OFFSET_exact = 885,
901 : BUFFER_STORE_FORMAT_X_ADDR64 = 886,
902 : BUFFER_STORE_FORMAT_X_BOTHEN = 887,
903 : BUFFER_STORE_FORMAT_X_BOTHEN_exact = 888,
904 : BUFFER_STORE_FORMAT_X_IDXEN = 889,
905 : BUFFER_STORE_FORMAT_X_IDXEN_exact = 890,
906 : BUFFER_STORE_FORMAT_X_OFFEN = 891,
907 : BUFFER_STORE_FORMAT_X_OFFEN_exact = 892,
908 : BUFFER_STORE_FORMAT_X_OFFSET = 893,
909 : BUFFER_STORE_FORMAT_X_OFFSET_exact = 894,
910 : BUFFER_STORE_LDS_DWORD = 895,
911 : BUFFER_STORE_SHORT_ADDR64 = 896,
912 : BUFFER_STORE_SHORT_BOTHEN = 897,
913 : BUFFER_STORE_SHORT_BOTHEN_exact = 898,
914 : BUFFER_STORE_SHORT_D16_HI_ADDR64 = 899,
915 : BUFFER_STORE_SHORT_D16_HI_BOTHEN = 900,
916 : BUFFER_STORE_SHORT_D16_HI_BOTHEN_exact = 901,
917 : BUFFER_STORE_SHORT_D16_HI_IDXEN = 902,
918 : BUFFER_STORE_SHORT_D16_HI_IDXEN_exact = 903,
919 : BUFFER_STORE_SHORT_D16_HI_OFFEN = 904,
920 : BUFFER_STORE_SHORT_D16_HI_OFFEN_exact = 905,
921 : BUFFER_STORE_SHORT_D16_HI_OFFSET = 906,
922 : BUFFER_STORE_SHORT_D16_HI_OFFSET_exact = 907,
923 : BUFFER_STORE_SHORT_IDXEN = 908,
924 : BUFFER_STORE_SHORT_IDXEN_exact = 909,
925 : BUFFER_STORE_SHORT_OFFEN = 910,
926 : BUFFER_STORE_SHORT_OFFEN_exact = 911,
927 : BUFFER_STORE_SHORT_OFFSET = 912,
928 : BUFFER_STORE_SHORT_OFFSET_exact = 913,
929 : BUFFER_WBINVL1 = 914,
930 : BUFFER_WBINVL1_SC = 915,
931 : BUFFER_WBINVL1_VOL = 916,
932 : DS_ADD_F32 = 917,
933 : DS_ADD_F32_gfx9 = 918,
934 : DS_ADD_RTN_F32 = 919,
935 : DS_ADD_RTN_F32_gfx9 = 920,
936 : DS_ADD_RTN_U32 = 921,
937 : DS_ADD_RTN_U32_gfx9 = 922,
938 : DS_ADD_RTN_U64 = 923,
939 : DS_ADD_RTN_U64_gfx9 = 924,
940 : DS_ADD_SRC2_F32 = 925,
941 : DS_ADD_SRC2_U32 = 926,
942 : DS_ADD_SRC2_U64 = 927,
943 : DS_ADD_U32 = 928,
944 : DS_ADD_U32_gfx9 = 929,
945 : DS_ADD_U64 = 930,
946 : DS_ADD_U64_gfx9 = 931,
947 : DS_AND_B32 = 932,
948 : DS_AND_B32_gfx9 = 933,
949 : DS_AND_B64 = 934,
950 : DS_AND_B64_gfx9 = 935,
951 : DS_AND_RTN_B32 = 936,
952 : DS_AND_RTN_B32_gfx9 = 937,
953 : DS_AND_RTN_B64 = 938,
954 : DS_AND_RTN_B64_gfx9 = 939,
955 : DS_AND_SRC2_B32 = 940,
956 : DS_AND_SRC2_B64 = 941,
957 : DS_APPEND = 942,
958 : DS_BPERMUTE_B32 = 943,
959 : DS_CMPST_B32 = 944,
960 : DS_CMPST_B32_gfx9 = 945,
961 : DS_CMPST_B64 = 946,
962 : DS_CMPST_B64_gfx9 = 947,
963 : DS_CMPST_F32 = 948,
964 : DS_CMPST_F32_gfx9 = 949,
965 : DS_CMPST_F64 = 950,
966 : DS_CMPST_F64_gfx9 = 951,
967 : DS_CMPST_RTN_B32 = 952,
968 : DS_CMPST_RTN_B32_gfx9 = 953,
969 : DS_CMPST_RTN_B64 = 954,
970 : DS_CMPST_RTN_B64_gfx9 = 955,
971 : DS_CMPST_RTN_F32 = 956,
972 : DS_CMPST_RTN_F32_gfx9 = 957,
973 : DS_CMPST_RTN_F64 = 958,
974 : DS_CMPST_RTN_F64_gfx9 = 959,
975 : DS_CONDXCHG32_RTN_B64 = 960,
976 : DS_CONDXCHG32_RTN_B64_gfx9 = 961,
977 : DS_CONSUME = 962,
978 : DS_DEC_RTN_U32 = 963,
979 : DS_DEC_RTN_U32_gfx9 = 964,
980 : DS_DEC_RTN_U64 = 965,
981 : DS_DEC_RTN_U64_gfx9 = 966,
982 : DS_DEC_SRC2_U32 = 967,
983 : DS_DEC_SRC2_U64 = 968,
984 : DS_DEC_U32 = 969,
985 : DS_DEC_U32_gfx9 = 970,
986 : DS_DEC_U64 = 971,
987 : DS_DEC_U64_gfx9 = 972,
988 : DS_GWS_BARRIER = 973,
989 : DS_GWS_INIT = 974,
990 : DS_GWS_SEMA_BR = 975,
991 : DS_GWS_SEMA_P = 976,
992 : DS_GWS_SEMA_RELEASE_ALL = 977,
993 : DS_GWS_SEMA_V = 978,
994 : DS_INC_RTN_U32 = 979,
995 : DS_INC_RTN_U32_gfx9 = 980,
996 : DS_INC_RTN_U64 = 981,
997 : DS_INC_RTN_U64_gfx9 = 982,
998 : DS_INC_SRC2_U32 = 983,
999 : DS_INC_SRC2_U64 = 984,
1000 : DS_INC_U32 = 985,
1001 : DS_INC_U32_gfx9 = 986,
1002 : DS_INC_U64 = 987,
1003 : DS_INC_U64_gfx9 = 988,
1004 : DS_MAX_F32 = 989,
1005 : DS_MAX_F32_gfx9 = 990,
1006 : DS_MAX_F64 = 991,
1007 : DS_MAX_F64_gfx9 = 992,
1008 : DS_MAX_I32 = 993,
1009 : DS_MAX_I32_gfx9 = 994,
1010 : DS_MAX_I64 = 995,
1011 : DS_MAX_I64_gfx9 = 996,
1012 : DS_MAX_RTN_F32 = 997,
1013 : DS_MAX_RTN_F32_gfx9 = 998,
1014 : DS_MAX_RTN_F64 = 999,
1015 : DS_MAX_RTN_F64_gfx9 = 1000,
1016 : DS_MAX_RTN_I32 = 1001,
1017 : DS_MAX_RTN_I32_gfx9 = 1002,
1018 : DS_MAX_RTN_I64 = 1003,
1019 : DS_MAX_RTN_I64_gfx9 = 1004,
1020 : DS_MAX_RTN_U32 = 1005,
1021 : DS_MAX_RTN_U32_gfx9 = 1006,
1022 : DS_MAX_RTN_U64 = 1007,
1023 : DS_MAX_RTN_U64_gfx9 = 1008,
1024 : DS_MAX_SRC2_F32 = 1009,
1025 : DS_MAX_SRC2_F64 = 1010,
1026 : DS_MAX_SRC2_I32 = 1011,
1027 : DS_MAX_SRC2_I64 = 1012,
1028 : DS_MAX_SRC2_U32 = 1013,
1029 : DS_MAX_SRC2_U64 = 1014,
1030 : DS_MAX_U32 = 1015,
1031 : DS_MAX_U32_gfx9 = 1016,
1032 : DS_MAX_U64 = 1017,
1033 : DS_MAX_U64_gfx9 = 1018,
1034 : DS_MIN_F32 = 1019,
1035 : DS_MIN_F32_gfx9 = 1020,
1036 : DS_MIN_F64 = 1021,
1037 : DS_MIN_F64_gfx9 = 1022,
1038 : DS_MIN_I32 = 1023,
1039 : DS_MIN_I32_gfx9 = 1024,
1040 : DS_MIN_I64 = 1025,
1041 : DS_MIN_I64_gfx9 = 1026,
1042 : DS_MIN_RTN_F32 = 1027,
1043 : DS_MIN_RTN_F32_gfx9 = 1028,
1044 : DS_MIN_RTN_F64 = 1029,
1045 : DS_MIN_RTN_F64_gfx9 = 1030,
1046 : DS_MIN_RTN_I32 = 1031,
1047 : DS_MIN_RTN_I32_gfx9 = 1032,
1048 : DS_MIN_RTN_I64 = 1033,
1049 : DS_MIN_RTN_I64_gfx9 = 1034,
1050 : DS_MIN_RTN_U32 = 1035,
1051 : DS_MIN_RTN_U32_gfx9 = 1036,
1052 : DS_MIN_RTN_U64 = 1037,
1053 : DS_MIN_RTN_U64_gfx9 = 1038,
1054 : DS_MIN_SRC2_F32 = 1039,
1055 : DS_MIN_SRC2_F64 = 1040,
1056 : DS_MIN_SRC2_I32 = 1041,
1057 : DS_MIN_SRC2_I64 = 1042,
1058 : DS_MIN_SRC2_U32 = 1043,
1059 : DS_MIN_SRC2_U64 = 1044,
1060 : DS_MIN_U32 = 1045,
1061 : DS_MIN_U32_gfx9 = 1046,
1062 : DS_MIN_U64 = 1047,
1063 : DS_MIN_U64_gfx9 = 1048,
1064 : DS_MSKOR_B32 = 1049,
1065 : DS_MSKOR_B32_gfx9 = 1050,
1066 : DS_MSKOR_B64 = 1051,
1067 : DS_MSKOR_B64_gfx9 = 1052,
1068 : DS_MSKOR_RTN_B32 = 1053,
1069 : DS_MSKOR_RTN_B32_gfx9 = 1054,
1070 : DS_MSKOR_RTN_B64 = 1055,
1071 : DS_MSKOR_RTN_B64_gfx9 = 1056,
1072 : DS_NOP = 1057,
1073 : DS_ORDERED_COUNT = 1058,
1074 : DS_OR_B32 = 1059,
1075 : DS_OR_B32_gfx9 = 1060,
1076 : DS_OR_B64 = 1061,
1077 : DS_OR_B64_gfx9 = 1062,
1078 : DS_OR_RTN_B32 = 1063,
1079 : DS_OR_RTN_B32_gfx9 = 1064,
1080 : DS_OR_RTN_B64 = 1065,
1081 : DS_OR_RTN_B64_gfx9 = 1066,
1082 : DS_OR_SRC2_B32 = 1067,
1083 : DS_OR_SRC2_B64 = 1068,
1084 : DS_PERMUTE_B32 = 1069,
1085 : DS_READ2ST64_B32 = 1070,
1086 : DS_READ2ST64_B32_gfx9 = 1071,
1087 : DS_READ2ST64_B64 = 1072,
1088 : DS_READ2ST64_B64_gfx9 = 1073,
1089 : DS_READ2_B32 = 1074,
1090 : DS_READ2_B32_gfx9 = 1075,
1091 : DS_READ2_B64 = 1076,
1092 : DS_READ2_B64_gfx9 = 1077,
1093 : DS_READ_ADDTID_B32 = 1078,
1094 : DS_READ_B128 = 1079,
1095 : DS_READ_B128_gfx9 = 1080,
1096 : DS_READ_B32 = 1081,
1097 : DS_READ_B32_gfx9 = 1082,
1098 : DS_READ_B64 = 1083,
1099 : DS_READ_B64_gfx9 = 1084,
1100 : DS_READ_B96 = 1085,
1101 : DS_READ_B96_gfx9 = 1086,
1102 : DS_READ_I16 = 1087,
1103 : DS_READ_I16_gfx9 = 1088,
1104 : DS_READ_I8 = 1089,
1105 : DS_READ_I8_D16 = 1090,
1106 : DS_READ_I8_D16_HI = 1091,
1107 : DS_READ_I8_gfx9 = 1092,
1108 : DS_READ_U16 = 1093,
1109 : DS_READ_U16_D16 = 1094,
1110 : DS_READ_U16_D16_HI = 1095,
1111 : DS_READ_U16_gfx9 = 1096,
1112 : DS_READ_U8 = 1097,
1113 : DS_READ_U8_D16 = 1098,
1114 : DS_READ_U8_D16_HI = 1099,
1115 : DS_READ_U8_gfx9 = 1100,
1116 : DS_RSUB_RTN_U32 = 1101,
1117 : DS_RSUB_RTN_U32_gfx9 = 1102,
1118 : DS_RSUB_RTN_U64 = 1103,
1119 : DS_RSUB_RTN_U64_gfx9 = 1104,
1120 : DS_RSUB_SRC2_U32 = 1105,
1121 : DS_RSUB_SRC2_U64 = 1106,
1122 : DS_RSUB_U32 = 1107,
1123 : DS_RSUB_U32_gfx9 = 1108,
1124 : DS_RSUB_U64 = 1109,
1125 : DS_RSUB_U64_gfx9 = 1110,
1126 : DS_SUB_RTN_U32 = 1111,
1127 : DS_SUB_RTN_U32_gfx9 = 1112,
1128 : DS_SUB_RTN_U64 = 1113,
1129 : DS_SUB_RTN_U64_gfx9 = 1114,
1130 : DS_SUB_SRC2_U32 = 1115,
1131 : DS_SUB_SRC2_U64 = 1116,
1132 : DS_SUB_U32 = 1117,
1133 : DS_SUB_U32_gfx9 = 1118,
1134 : DS_SUB_U64 = 1119,
1135 : DS_SUB_U64_gfx9 = 1120,
1136 : DS_SWIZZLE_B32 = 1121,
1137 : DS_WRAP_RTN_B32 = 1122,
1138 : DS_WRAP_RTN_B32_gfx9 = 1123,
1139 : DS_WRITE2ST64_B32 = 1124,
1140 : DS_WRITE2ST64_B32_gfx9 = 1125,
1141 : DS_WRITE2ST64_B64 = 1126,
1142 : DS_WRITE2ST64_B64_gfx9 = 1127,
1143 : DS_WRITE2_B32 = 1128,
1144 : DS_WRITE2_B32_gfx9 = 1129,
1145 : DS_WRITE2_B64 = 1130,
1146 : DS_WRITE2_B64_gfx9 = 1131,
1147 : DS_WRITE_ADDTID_B32 = 1132,
1148 : DS_WRITE_B128 = 1133,
1149 : DS_WRITE_B128_gfx9 = 1134,
1150 : DS_WRITE_B16 = 1135,
1151 : DS_WRITE_B16_D16_HI = 1136,
1152 : DS_WRITE_B16_gfx9 = 1137,
1153 : DS_WRITE_B32 = 1138,
1154 : DS_WRITE_B32_gfx9 = 1139,
1155 : DS_WRITE_B64 = 1140,
1156 : DS_WRITE_B64_gfx9 = 1141,
1157 : DS_WRITE_B8 = 1142,
1158 : DS_WRITE_B8_D16_HI = 1143,
1159 : DS_WRITE_B8_gfx9 = 1144,
1160 : DS_WRITE_B96 = 1145,
1161 : DS_WRITE_B96_gfx9 = 1146,
1162 : DS_WRITE_SRC2_B32 = 1147,
1163 : DS_WRITE_SRC2_B64 = 1148,
1164 : DS_WRXCHG2ST64_RTN_B32 = 1149,
1165 : DS_WRXCHG2ST64_RTN_B32_gfx9 = 1150,
1166 : DS_WRXCHG2ST64_RTN_B64 = 1151,
1167 : DS_WRXCHG2ST64_RTN_B64_gfx9 = 1152,
1168 : DS_WRXCHG2_RTN_B32 = 1153,
1169 : DS_WRXCHG2_RTN_B32_gfx9 = 1154,
1170 : DS_WRXCHG2_RTN_B64 = 1155,
1171 : DS_WRXCHG2_RTN_B64_gfx9 = 1156,
1172 : DS_WRXCHG_RTN_B32 = 1157,
1173 : DS_WRXCHG_RTN_B32_gfx9 = 1158,
1174 : DS_WRXCHG_RTN_B64 = 1159,
1175 : DS_WRXCHG_RTN_B64_gfx9 = 1160,
1176 : DS_XOR_B32 = 1161,
1177 : DS_XOR_B32_gfx9 = 1162,
1178 : DS_XOR_B64 = 1163,
1179 : DS_XOR_B64_gfx9 = 1164,
1180 : DS_XOR_RTN_B32 = 1165,
1181 : DS_XOR_RTN_B32_gfx9 = 1166,
1182 : DS_XOR_RTN_B64 = 1167,
1183 : DS_XOR_RTN_B64_gfx9 = 1168,
1184 : DS_XOR_SRC2_B32 = 1169,
1185 : DS_XOR_SRC2_B64 = 1170,
1186 : EXIT_WWM = 1171,
1187 : EXP = 1172,
1188 : EXP_DONE = 1173,
1189 : FLAT_ATOMIC_ADD = 1174,
1190 : FLAT_ATOMIC_ADD_RTN = 1175,
1191 : FLAT_ATOMIC_ADD_X2 = 1176,
1192 : FLAT_ATOMIC_ADD_X2_RTN = 1177,
1193 : FLAT_ATOMIC_AND = 1178,
1194 : FLAT_ATOMIC_AND_RTN = 1179,
1195 : FLAT_ATOMIC_AND_X2 = 1180,
1196 : FLAT_ATOMIC_AND_X2_RTN = 1181,
1197 : FLAT_ATOMIC_CMPSWAP = 1182,
1198 : FLAT_ATOMIC_CMPSWAP_RTN = 1183,
1199 : FLAT_ATOMIC_CMPSWAP_X2 = 1184,
1200 : FLAT_ATOMIC_CMPSWAP_X2_RTN = 1185,
1201 : FLAT_ATOMIC_DEC = 1186,
1202 : FLAT_ATOMIC_DEC_RTN = 1187,
1203 : FLAT_ATOMIC_DEC_X2 = 1188,
1204 : FLAT_ATOMIC_DEC_X2_RTN = 1189,
1205 : FLAT_ATOMIC_FCMPSWAP = 1190,
1206 : FLAT_ATOMIC_FCMPSWAP_RTN = 1191,
1207 : FLAT_ATOMIC_FCMPSWAP_X2 = 1192,
1208 : FLAT_ATOMIC_FCMPSWAP_X2_RTN = 1193,
1209 : FLAT_ATOMIC_FMAX = 1194,
1210 : FLAT_ATOMIC_FMAX_RTN = 1195,
1211 : FLAT_ATOMIC_FMAX_X2 = 1196,
1212 : FLAT_ATOMIC_FMAX_X2_RTN = 1197,
1213 : FLAT_ATOMIC_FMIN = 1198,
1214 : FLAT_ATOMIC_FMIN_RTN = 1199,
1215 : FLAT_ATOMIC_FMIN_X2 = 1200,
1216 : FLAT_ATOMIC_FMIN_X2_RTN = 1201,
1217 : FLAT_ATOMIC_INC = 1202,
1218 : FLAT_ATOMIC_INC_RTN = 1203,
1219 : FLAT_ATOMIC_INC_X2 = 1204,
1220 : FLAT_ATOMIC_INC_X2_RTN = 1205,
1221 : FLAT_ATOMIC_OR = 1206,
1222 : FLAT_ATOMIC_OR_RTN = 1207,
1223 : FLAT_ATOMIC_OR_X2 = 1208,
1224 : FLAT_ATOMIC_OR_X2_RTN = 1209,
1225 : FLAT_ATOMIC_SMAX = 1210,
1226 : FLAT_ATOMIC_SMAX_RTN = 1211,
1227 : FLAT_ATOMIC_SMAX_X2 = 1212,
1228 : FLAT_ATOMIC_SMAX_X2_RTN = 1213,
1229 : FLAT_ATOMIC_SMIN = 1214,
1230 : FLAT_ATOMIC_SMIN_RTN = 1215,
1231 : FLAT_ATOMIC_SMIN_X2 = 1216,
1232 : FLAT_ATOMIC_SMIN_X2_RTN = 1217,
1233 : FLAT_ATOMIC_SUB = 1218,
1234 : FLAT_ATOMIC_SUB_RTN = 1219,
1235 : FLAT_ATOMIC_SUB_X2 = 1220,
1236 : FLAT_ATOMIC_SUB_X2_RTN = 1221,
1237 : FLAT_ATOMIC_SWAP = 1222,
1238 : FLAT_ATOMIC_SWAP_RTN = 1223,
1239 : FLAT_ATOMIC_SWAP_X2 = 1224,
1240 : FLAT_ATOMIC_SWAP_X2_RTN = 1225,
1241 : FLAT_ATOMIC_UMAX = 1226,
1242 : FLAT_ATOMIC_UMAX_RTN = 1227,
1243 : FLAT_ATOMIC_UMAX_X2 = 1228,
1244 : FLAT_ATOMIC_UMAX_X2_RTN = 1229,
1245 : FLAT_ATOMIC_UMIN = 1230,
1246 : FLAT_ATOMIC_UMIN_RTN = 1231,
1247 : FLAT_ATOMIC_UMIN_X2 = 1232,
1248 : FLAT_ATOMIC_UMIN_X2_RTN = 1233,
1249 : FLAT_ATOMIC_XOR = 1234,
1250 : FLAT_ATOMIC_XOR_RTN = 1235,
1251 : FLAT_ATOMIC_XOR_X2 = 1236,
1252 : FLAT_ATOMIC_XOR_X2_RTN = 1237,
1253 : FLAT_LOAD_DWORD = 1238,
1254 : FLAT_LOAD_DWORDX2 = 1239,
1255 : FLAT_LOAD_DWORDX3 = 1240,
1256 : FLAT_LOAD_DWORDX4 = 1241,
1257 : FLAT_LOAD_SBYTE = 1242,
1258 : FLAT_LOAD_SBYTE_D16 = 1243,
1259 : FLAT_LOAD_SBYTE_D16_HI = 1244,
1260 : FLAT_LOAD_SHORT_D16 = 1245,
1261 : FLAT_LOAD_SHORT_D16_HI = 1246,
1262 : FLAT_LOAD_SSHORT = 1247,
1263 : FLAT_LOAD_UBYTE = 1248,
1264 : FLAT_LOAD_UBYTE_D16 = 1249,
1265 : FLAT_LOAD_UBYTE_D16_HI = 1250,
1266 : FLAT_LOAD_USHORT = 1251,
1267 : FLAT_STORE_BYTE = 1252,
1268 : FLAT_STORE_BYTE_D16_HI = 1253,
1269 : FLAT_STORE_DWORD = 1254,
1270 : FLAT_STORE_DWORDX2 = 1255,
1271 : FLAT_STORE_DWORDX3 = 1256,
1272 : FLAT_STORE_DWORDX4 = 1257,
1273 : FLAT_STORE_SHORT = 1258,
1274 : FLAT_STORE_SHORT_D16_HI = 1259,
1275 : GET_GROUPSTATICSIZE = 1260,
1276 : GLOBAL_ATOMIC_ADD = 1261,
1277 : GLOBAL_ATOMIC_ADD_RTN = 1262,
1278 : GLOBAL_ATOMIC_ADD_SADDR = 1263,
1279 : GLOBAL_ATOMIC_ADD_SADDR_RTN = 1264,
1280 : GLOBAL_ATOMIC_ADD_X2 = 1265,
1281 : GLOBAL_ATOMIC_ADD_X2_RTN = 1266,
1282 : GLOBAL_ATOMIC_ADD_X2_SADDR = 1267,
1283 : GLOBAL_ATOMIC_ADD_X2_SADDR_RTN = 1268,
1284 : GLOBAL_ATOMIC_AND = 1269,
1285 : GLOBAL_ATOMIC_AND_RTN = 1270,
1286 : GLOBAL_ATOMIC_AND_SADDR = 1271,
1287 : GLOBAL_ATOMIC_AND_SADDR_RTN = 1272,
1288 : GLOBAL_ATOMIC_AND_X2 = 1273,
1289 : GLOBAL_ATOMIC_AND_X2_RTN = 1274,
1290 : GLOBAL_ATOMIC_AND_X2_SADDR = 1275,
1291 : GLOBAL_ATOMIC_AND_X2_SADDR_RTN = 1276,
1292 : GLOBAL_ATOMIC_CMPSWAP = 1277,
1293 : GLOBAL_ATOMIC_CMPSWAP_RTN = 1278,
1294 : GLOBAL_ATOMIC_CMPSWAP_SADDR = 1279,
1295 : GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN = 1280,
1296 : GLOBAL_ATOMIC_CMPSWAP_X2 = 1281,
1297 : GLOBAL_ATOMIC_CMPSWAP_X2_RTN = 1282,
1298 : GLOBAL_ATOMIC_CMPSWAP_X2_SADDR = 1283,
1299 : GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN = 1284,
1300 : GLOBAL_ATOMIC_DEC = 1285,
1301 : GLOBAL_ATOMIC_DEC_RTN = 1286,
1302 : GLOBAL_ATOMIC_DEC_SADDR = 1287,
1303 : GLOBAL_ATOMIC_DEC_SADDR_RTN = 1288,
1304 : GLOBAL_ATOMIC_DEC_X2 = 1289,
1305 : GLOBAL_ATOMIC_DEC_X2_RTN = 1290,
1306 : GLOBAL_ATOMIC_DEC_X2_SADDR = 1291,
1307 : GLOBAL_ATOMIC_DEC_X2_SADDR_RTN = 1292,
1308 : GLOBAL_ATOMIC_INC = 1293,
1309 : GLOBAL_ATOMIC_INC_RTN = 1294,
1310 : GLOBAL_ATOMIC_INC_SADDR = 1295,
1311 : GLOBAL_ATOMIC_INC_SADDR_RTN = 1296,
1312 : GLOBAL_ATOMIC_INC_X2 = 1297,
1313 : GLOBAL_ATOMIC_INC_X2_RTN = 1298,
1314 : GLOBAL_ATOMIC_INC_X2_SADDR = 1299,
1315 : GLOBAL_ATOMIC_INC_X2_SADDR_RTN = 1300,
1316 : GLOBAL_ATOMIC_OR = 1301,
1317 : GLOBAL_ATOMIC_OR_RTN = 1302,
1318 : GLOBAL_ATOMIC_OR_SADDR = 1303,
1319 : GLOBAL_ATOMIC_OR_SADDR_RTN = 1304,
1320 : GLOBAL_ATOMIC_OR_X2 = 1305,
1321 : GLOBAL_ATOMIC_OR_X2_RTN = 1306,
1322 : GLOBAL_ATOMIC_OR_X2_SADDR = 1307,
1323 : GLOBAL_ATOMIC_OR_X2_SADDR_RTN = 1308,
1324 : GLOBAL_ATOMIC_SMAX = 1309,
1325 : GLOBAL_ATOMIC_SMAX_RTN = 1310,
1326 : GLOBAL_ATOMIC_SMAX_SADDR = 1311,
1327 : GLOBAL_ATOMIC_SMAX_SADDR_RTN = 1312,
1328 : GLOBAL_ATOMIC_SMAX_X2 = 1313,
1329 : GLOBAL_ATOMIC_SMAX_X2_RTN = 1314,
1330 : GLOBAL_ATOMIC_SMAX_X2_SADDR = 1315,
1331 : GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN = 1316,
1332 : GLOBAL_ATOMIC_SMIN = 1317,
1333 : GLOBAL_ATOMIC_SMIN_RTN = 1318,
1334 : GLOBAL_ATOMIC_SMIN_SADDR = 1319,
1335 : GLOBAL_ATOMIC_SMIN_SADDR_RTN = 1320,
1336 : GLOBAL_ATOMIC_SMIN_X2 = 1321,
1337 : GLOBAL_ATOMIC_SMIN_X2_RTN = 1322,
1338 : GLOBAL_ATOMIC_SMIN_X2_SADDR = 1323,
1339 : GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN = 1324,
1340 : GLOBAL_ATOMIC_SUB = 1325,
1341 : GLOBAL_ATOMIC_SUB_RTN = 1326,
1342 : GLOBAL_ATOMIC_SUB_SADDR = 1327,
1343 : GLOBAL_ATOMIC_SUB_SADDR_RTN = 1328,
1344 : GLOBAL_ATOMIC_SUB_X2 = 1329,
1345 : GLOBAL_ATOMIC_SUB_X2_RTN = 1330,
1346 : GLOBAL_ATOMIC_SUB_X2_SADDR = 1331,
1347 : GLOBAL_ATOMIC_SUB_X2_SADDR_RTN = 1332,
1348 : GLOBAL_ATOMIC_SWAP = 1333,
1349 : GLOBAL_ATOMIC_SWAP_RTN = 1334,
1350 : GLOBAL_ATOMIC_SWAP_SADDR = 1335,
1351 : GLOBAL_ATOMIC_SWAP_SADDR_RTN = 1336,
1352 : GLOBAL_ATOMIC_SWAP_X2 = 1337,
1353 : GLOBAL_ATOMIC_SWAP_X2_RTN = 1338,
1354 : GLOBAL_ATOMIC_SWAP_X2_SADDR = 1339,
1355 : GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN = 1340,
1356 : GLOBAL_ATOMIC_UMAX = 1341,
1357 : GLOBAL_ATOMIC_UMAX_RTN = 1342,
1358 : GLOBAL_ATOMIC_UMAX_SADDR = 1343,
1359 : GLOBAL_ATOMIC_UMAX_SADDR_RTN = 1344,
1360 : GLOBAL_ATOMIC_UMAX_X2 = 1345,
1361 : GLOBAL_ATOMIC_UMAX_X2_RTN = 1346,
1362 : GLOBAL_ATOMIC_UMAX_X2_SADDR = 1347,
1363 : GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN = 1348,
1364 : GLOBAL_ATOMIC_UMIN = 1349,
1365 : GLOBAL_ATOMIC_UMIN_RTN = 1350,
1366 : GLOBAL_ATOMIC_UMIN_SADDR = 1351,
1367 : GLOBAL_ATOMIC_UMIN_SADDR_RTN = 1352,
1368 : GLOBAL_ATOMIC_UMIN_X2 = 1353,
1369 : GLOBAL_ATOMIC_UMIN_X2_RTN = 1354,
1370 : GLOBAL_ATOMIC_UMIN_X2_SADDR = 1355,
1371 : GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN = 1356,
1372 : GLOBAL_ATOMIC_XOR = 1357,
1373 : GLOBAL_ATOMIC_XOR_RTN = 1358,
1374 : GLOBAL_ATOMIC_XOR_SADDR = 1359,
1375 : GLOBAL_ATOMIC_XOR_SADDR_RTN = 1360,
1376 : GLOBAL_ATOMIC_XOR_X2 = 1361,
1377 : GLOBAL_ATOMIC_XOR_X2_RTN = 1362,
1378 : GLOBAL_ATOMIC_XOR_X2_SADDR = 1363,
1379 : GLOBAL_ATOMIC_XOR_X2_SADDR_RTN = 1364,
1380 : GLOBAL_LOAD_DWORD = 1365,
1381 : GLOBAL_LOAD_DWORDX2 = 1366,
1382 : GLOBAL_LOAD_DWORDX2_SADDR = 1367,
1383 : GLOBAL_LOAD_DWORDX3 = 1368,
1384 : GLOBAL_LOAD_DWORDX3_SADDR = 1369,
1385 : GLOBAL_LOAD_DWORDX4 = 1370,
1386 : GLOBAL_LOAD_DWORDX4_SADDR = 1371,
1387 : GLOBAL_LOAD_DWORD_SADDR = 1372,
1388 : GLOBAL_LOAD_SBYTE = 1373,
1389 : GLOBAL_LOAD_SBYTE_D16 = 1374,
1390 : GLOBAL_LOAD_SBYTE_D16_HI = 1375,
1391 : GLOBAL_LOAD_SBYTE_D16_HI_SADDR = 1376,
1392 : GLOBAL_LOAD_SBYTE_D16_SADDR = 1377,
1393 : GLOBAL_LOAD_SBYTE_SADDR = 1378,
1394 : GLOBAL_LOAD_SHORT_D16 = 1379,
1395 : GLOBAL_LOAD_SHORT_D16_HI = 1380,
1396 : GLOBAL_LOAD_SHORT_D16_HI_SADDR = 1381,
1397 : GLOBAL_LOAD_SHORT_D16_SADDR = 1382,
1398 : GLOBAL_LOAD_SSHORT = 1383,
1399 : GLOBAL_LOAD_SSHORT_SADDR = 1384,
1400 : GLOBAL_LOAD_UBYTE = 1385,
1401 : GLOBAL_LOAD_UBYTE_D16 = 1386,
1402 : GLOBAL_LOAD_UBYTE_D16_HI = 1387,
1403 : GLOBAL_LOAD_UBYTE_D16_HI_SADDR = 1388,
1404 : GLOBAL_LOAD_UBYTE_D16_SADDR = 1389,
1405 : GLOBAL_LOAD_UBYTE_SADDR = 1390,
1406 : GLOBAL_LOAD_USHORT = 1391,
1407 : GLOBAL_LOAD_USHORT_SADDR = 1392,
1408 : GLOBAL_STORE_BYTE = 1393,
1409 : GLOBAL_STORE_BYTE_D16_HI = 1394,
1410 : GLOBAL_STORE_BYTE_D16_HI_SADDR = 1395,
1411 : GLOBAL_STORE_BYTE_SADDR = 1396,
1412 : GLOBAL_STORE_DWORD = 1397,
1413 : GLOBAL_STORE_DWORDX2 = 1398,
1414 : GLOBAL_STORE_DWORDX2_SADDR = 1399,
1415 : GLOBAL_STORE_DWORDX3 = 1400,
1416 : GLOBAL_STORE_DWORDX3_SADDR = 1401,
1417 : GLOBAL_STORE_DWORDX4 = 1402,
1418 : GLOBAL_STORE_DWORDX4_SADDR = 1403,
1419 : GLOBAL_STORE_DWORD_SADDR = 1404,
1420 : GLOBAL_STORE_SHORT = 1405,
1421 : GLOBAL_STORE_SHORT_D16_HI = 1406,
1422 : GLOBAL_STORE_SHORT_D16_HI_SADDR = 1407,
1423 : GLOBAL_STORE_SHORT_SADDR = 1408,
1424 : SCRATCH_LOAD_DWORD = 1409,
1425 : SCRATCH_LOAD_DWORDX2 = 1410,
1426 : SCRATCH_LOAD_DWORDX2_SADDR = 1411,
1427 : SCRATCH_LOAD_DWORDX3 = 1412,
1428 : SCRATCH_LOAD_DWORDX3_SADDR = 1413,
1429 : SCRATCH_LOAD_DWORDX4 = 1414,
1430 : SCRATCH_LOAD_DWORDX4_SADDR = 1415,
1431 : SCRATCH_LOAD_DWORD_SADDR = 1416,
1432 : SCRATCH_LOAD_SBYTE = 1417,
1433 : SCRATCH_LOAD_SBYTE_D16 = 1418,
1434 : SCRATCH_LOAD_SBYTE_D16_HI = 1419,
1435 : SCRATCH_LOAD_SBYTE_D16_HI_SADDR = 1420,
1436 : SCRATCH_LOAD_SBYTE_D16_SADDR = 1421,
1437 : SCRATCH_LOAD_SBYTE_SADDR = 1422,
1438 : SCRATCH_LOAD_SHORT_D16 = 1423,
1439 : SCRATCH_LOAD_SHORT_D16_HI = 1424,
1440 : SCRATCH_LOAD_SHORT_D16_HI_SADDR = 1425,
1441 : SCRATCH_LOAD_SHORT_D16_SADDR = 1426,
1442 : SCRATCH_LOAD_SSHORT = 1427,
1443 : SCRATCH_LOAD_SSHORT_SADDR = 1428,
1444 : SCRATCH_LOAD_UBYTE = 1429,
1445 : SCRATCH_LOAD_UBYTE_D16 = 1430,
1446 : SCRATCH_LOAD_UBYTE_D16_HI = 1431,
1447 : SCRATCH_LOAD_UBYTE_D16_HI_SADDR = 1432,
1448 : SCRATCH_LOAD_UBYTE_D16_SADDR = 1433,
1449 : SCRATCH_LOAD_UBYTE_SADDR = 1434,
1450 : SCRATCH_LOAD_USHORT = 1435,
1451 : SCRATCH_LOAD_USHORT_SADDR = 1436,
1452 : SCRATCH_STORE_BYTE = 1437,
1453 : SCRATCH_STORE_BYTE_D16_HI = 1438,
1454 : SCRATCH_STORE_BYTE_D16_HI_SADDR = 1439,
1455 : SCRATCH_STORE_BYTE_SADDR = 1440,
1456 : SCRATCH_STORE_DWORD = 1441,
1457 : SCRATCH_STORE_DWORDX2 = 1442,
1458 : SCRATCH_STORE_DWORDX2_SADDR = 1443,
1459 : SCRATCH_STORE_DWORDX3 = 1444,
1460 : SCRATCH_STORE_DWORDX3_SADDR = 1445,
1461 : SCRATCH_STORE_DWORDX4 = 1446,
1462 : SCRATCH_STORE_DWORDX4_SADDR = 1447,
1463 : SCRATCH_STORE_DWORD_SADDR = 1448,
1464 : SCRATCH_STORE_SHORT = 1449,
1465 : SCRATCH_STORE_SHORT_D16_HI = 1450,
1466 : SCRATCH_STORE_SHORT_D16_HI_SADDR = 1451,
1467 : SCRATCH_STORE_SHORT_SADDR = 1452,
1468 : SI_BREAK = 1453,
1469 : SI_BR_UNDEF = 1454,
1470 : SI_CALL = 1455,
1471 : SI_CALL_ISEL = 1456,
1472 : SI_ELSE = 1457,
1473 : SI_ELSE_BREAK = 1458,
1474 : SI_END_CF = 1459,
1475 : SI_IF = 1460,
1476 : SI_IF_BREAK = 1461,
1477 : SI_ILLEGAL_COPY = 1462,
1478 : SI_INDIRECT_DST_V1 = 1463,
1479 : SI_INDIRECT_DST_V16 = 1464,
1480 : SI_INDIRECT_DST_V2 = 1465,
1481 : SI_INDIRECT_DST_V4 = 1466,
1482 : SI_INDIRECT_DST_V8 = 1467,
1483 : SI_INDIRECT_SRC_V1 = 1468,
1484 : SI_INDIRECT_SRC_V16 = 1469,
1485 : SI_INDIRECT_SRC_V2 = 1470,
1486 : SI_INDIRECT_SRC_V4 = 1471,
1487 : SI_INDIRECT_SRC_V8 = 1472,
1488 : SI_INIT_EXEC = 1473,
1489 : SI_INIT_EXEC_FROM_INPUT = 1474,
1490 : SI_INIT_M0 = 1475,
1491 : SI_KILL_F32_COND_IMM_PSEUDO = 1476,
1492 : SI_KILL_F32_COND_IMM_TERMINATOR = 1477,
1493 : SI_KILL_I1_PSEUDO = 1478,
1494 : SI_KILL_I1_TERMINATOR = 1479,
1495 : SI_LOOP = 1480,
1496 : SI_MASKED_UNREACHABLE = 1481,
1497 : SI_MASK_BRANCH = 1482,
1498 : SI_NON_UNIFORM_BRCOND_PSEUDO = 1483,
1499 : SI_PC_ADD_REL_OFFSET = 1484,
1500 : SI_PS_LIVE = 1485,
1501 : SI_RETURN = 1486,
1502 : SI_RETURN_TO_EPILOG = 1487,
1503 : SI_SPILL_S128_RESTORE = 1488,
1504 : SI_SPILL_S128_SAVE = 1489,
1505 : SI_SPILL_S256_RESTORE = 1490,
1506 : SI_SPILL_S256_SAVE = 1491,
1507 : SI_SPILL_S32_RESTORE = 1492,
1508 : SI_SPILL_S32_SAVE = 1493,
1509 : SI_SPILL_S512_RESTORE = 1494,
1510 : SI_SPILL_S512_SAVE = 1495,
1511 : SI_SPILL_S64_RESTORE = 1496,
1512 : SI_SPILL_S64_SAVE = 1497,
1513 : SI_SPILL_V128_RESTORE = 1498,
1514 : SI_SPILL_V128_SAVE = 1499,
1515 : SI_SPILL_V256_RESTORE = 1500,
1516 : SI_SPILL_V256_SAVE = 1501,
1517 : SI_SPILL_V32_RESTORE = 1502,
1518 : SI_SPILL_V32_SAVE = 1503,
1519 : SI_SPILL_V512_RESTORE = 1504,
1520 : SI_SPILL_V512_SAVE = 1505,
1521 : SI_SPILL_V64_RESTORE = 1506,
1522 : SI_SPILL_V64_SAVE = 1507,
1523 : SI_SPILL_V96_RESTORE = 1508,
1524 : SI_SPILL_V96_SAVE = 1509,
1525 : SI_TCRETURN = 1510,
1526 : SI_TCRETURN_ISEL = 1511,
1527 : S_ABSDIFF_I32 = 1512,
1528 : S_ABS_I32 = 1513,
1529 : S_ADDC_U32 = 1514,
1530 : S_ADDK_I32 = 1515,
1531 : S_ADD_I32 = 1516,
1532 : S_ADD_U32 = 1517,
1533 : S_ADD_U64_CO_PSEUDO = 1518,
1534 : S_ADD_U64_PSEUDO = 1519,
1535 : S_ANDN1_SAVEEXEC_B64 = 1520,
1536 : S_ANDN1_WREXEC_B64 = 1521,
1537 : S_ANDN2_B32 = 1522,
1538 : S_ANDN2_B64 = 1523,
1539 : S_ANDN2_B64_term = 1524,
1540 : S_ANDN2_SAVEEXEC_B64 = 1525,
1541 : S_ANDN2_WREXEC_B64 = 1526,
1542 : S_AND_B32 = 1527,
1543 : S_AND_B64 = 1528,
1544 : S_AND_SAVEEXEC_B64 = 1529,
1545 : S_ASHR_I32 = 1530,
1546 : S_ASHR_I64 = 1531,
1547 : S_ATC_PROBE_BUFFER_IMM = 1532,
1548 : S_ATC_PROBE_BUFFER_SGPR = 1533,
1549 : S_ATC_PROBE_IMM = 1534,
1550 : S_ATC_PROBE_SGPR = 1535,
1551 : S_ATOMIC_ADD_IMM = 1536,
1552 : S_ATOMIC_ADD_IMM_RTN = 1537,
1553 : S_ATOMIC_ADD_SGPR = 1538,
1554 : S_ATOMIC_ADD_SGPR_RTN = 1539,
1555 : S_ATOMIC_ADD_X2_IMM = 1540,
1556 : S_ATOMIC_ADD_X2_IMM_RTN = 1541,
1557 : S_ATOMIC_ADD_X2_SGPR = 1542,
1558 : S_ATOMIC_ADD_X2_SGPR_RTN = 1543,
1559 : S_ATOMIC_AND_IMM = 1544,
1560 : S_ATOMIC_AND_IMM_RTN = 1545,
1561 : S_ATOMIC_AND_SGPR = 1546,
1562 : S_ATOMIC_AND_SGPR_RTN = 1547,
1563 : S_ATOMIC_AND_X2_IMM = 1548,
1564 : S_ATOMIC_AND_X2_IMM_RTN = 1549,
1565 : S_ATOMIC_AND_X2_SGPR = 1550,
1566 : S_ATOMIC_AND_X2_SGPR_RTN = 1551,
1567 : S_ATOMIC_CMPSWAP_IMM = 1552,
1568 : S_ATOMIC_CMPSWAP_IMM_RTN = 1553,
1569 : S_ATOMIC_CMPSWAP_SGPR = 1554,
1570 : S_ATOMIC_CMPSWAP_SGPR_RTN = 1555,
1571 : S_ATOMIC_CMPSWAP_X2_IMM = 1556,
1572 : S_ATOMIC_CMPSWAP_X2_IMM_RTN = 1557,
1573 : S_ATOMIC_CMPSWAP_X2_SGPR = 1558,
1574 : S_ATOMIC_CMPSWAP_X2_SGPR_RTN = 1559,
1575 : S_ATOMIC_DEC_IMM = 1560,
1576 : S_ATOMIC_DEC_IMM_RTN = 1561,
1577 : S_ATOMIC_DEC_SGPR = 1562,
1578 : S_ATOMIC_DEC_SGPR_RTN = 1563,
1579 : S_ATOMIC_DEC_X2_IMM = 1564,
1580 : S_ATOMIC_DEC_X2_IMM_RTN = 1565,
1581 : S_ATOMIC_DEC_X2_SGPR = 1566,
1582 : S_ATOMIC_DEC_X2_SGPR_RTN = 1567,
1583 : S_ATOMIC_INC_IMM = 1568,
1584 : S_ATOMIC_INC_IMM_RTN = 1569,
1585 : S_ATOMIC_INC_SGPR = 1570,
1586 : S_ATOMIC_INC_SGPR_RTN = 1571,
1587 : S_ATOMIC_INC_X2_IMM = 1572,
1588 : S_ATOMIC_INC_X2_IMM_RTN = 1573,
1589 : S_ATOMIC_INC_X2_SGPR = 1574,
1590 : S_ATOMIC_INC_X2_SGPR_RTN = 1575,
1591 : S_ATOMIC_OR_IMM = 1576,
1592 : S_ATOMIC_OR_IMM_RTN = 1577,
1593 : S_ATOMIC_OR_SGPR = 1578,
1594 : S_ATOMIC_OR_SGPR_RTN = 1579,
1595 : S_ATOMIC_OR_X2_IMM = 1580,
1596 : S_ATOMIC_OR_X2_IMM_RTN = 1581,
1597 : S_ATOMIC_OR_X2_SGPR = 1582,
1598 : S_ATOMIC_OR_X2_SGPR_RTN = 1583,
1599 : S_ATOMIC_SMAX_IMM = 1584,
1600 : S_ATOMIC_SMAX_IMM_RTN = 1585,
1601 : S_ATOMIC_SMAX_SGPR = 1586,
1602 : S_ATOMIC_SMAX_SGPR_RTN = 1587,
1603 : S_ATOMIC_SMAX_X2_IMM = 1588,
1604 : S_ATOMIC_SMAX_X2_IMM_RTN = 1589,
1605 : S_ATOMIC_SMAX_X2_SGPR = 1590,
1606 : S_ATOMIC_SMAX_X2_SGPR_RTN = 1591,
1607 : S_ATOMIC_SMIN_IMM = 1592,
1608 : S_ATOMIC_SMIN_IMM_RTN = 1593,
1609 : S_ATOMIC_SMIN_SGPR = 1594,
1610 : S_ATOMIC_SMIN_SGPR_RTN = 1595,
1611 : S_ATOMIC_SMIN_X2_IMM = 1596,
1612 : S_ATOMIC_SMIN_X2_IMM_RTN = 1597,
1613 : S_ATOMIC_SMIN_X2_SGPR = 1598,
1614 : S_ATOMIC_SMIN_X2_SGPR_RTN = 1599,
1615 : S_ATOMIC_SUB_IMM = 1600,
1616 : S_ATOMIC_SUB_IMM_RTN = 1601,
1617 : S_ATOMIC_SUB_SGPR = 1602,
1618 : S_ATOMIC_SUB_SGPR_RTN = 1603,
1619 : S_ATOMIC_SUB_X2_IMM = 1604,
1620 : S_ATOMIC_SUB_X2_IMM_RTN = 1605,
1621 : S_ATOMIC_SUB_X2_SGPR = 1606,
1622 : S_ATOMIC_SUB_X2_SGPR_RTN = 1607,
1623 : S_ATOMIC_SWAP_IMM = 1608,
1624 : S_ATOMIC_SWAP_IMM_RTN = 1609,
1625 : S_ATOMIC_SWAP_SGPR = 1610,
1626 : S_ATOMIC_SWAP_SGPR_RTN = 1611,
1627 : S_ATOMIC_SWAP_X2_IMM = 1612,
1628 : S_ATOMIC_SWAP_X2_IMM_RTN = 1613,
1629 : S_ATOMIC_SWAP_X2_SGPR = 1614,
1630 : S_ATOMIC_SWAP_X2_SGPR_RTN = 1615,
1631 : S_ATOMIC_UMAX_IMM = 1616,
1632 : S_ATOMIC_UMAX_IMM_RTN = 1617,
1633 : S_ATOMIC_UMAX_SGPR = 1618,
1634 : S_ATOMIC_UMAX_SGPR_RTN = 1619,
1635 : S_ATOMIC_UMAX_X2_IMM = 1620,
1636 : S_ATOMIC_UMAX_X2_IMM_RTN = 1621,
1637 : S_ATOMIC_UMAX_X2_SGPR = 1622,
1638 : S_ATOMIC_UMAX_X2_SGPR_RTN = 1623,
1639 : S_ATOMIC_UMIN_IMM = 1624,
1640 : S_ATOMIC_UMIN_IMM_RTN = 1625,
1641 : S_ATOMIC_UMIN_SGPR = 1626,
1642 : S_ATOMIC_UMIN_SGPR_RTN = 1627,
1643 : S_ATOMIC_UMIN_X2_IMM = 1628,
1644 : S_ATOMIC_UMIN_X2_IMM_RTN = 1629,
1645 : S_ATOMIC_UMIN_X2_SGPR = 1630,
1646 : S_ATOMIC_UMIN_X2_SGPR_RTN = 1631,
1647 : S_ATOMIC_XOR_IMM = 1632,
1648 : S_ATOMIC_XOR_IMM_RTN = 1633,
1649 : S_ATOMIC_XOR_SGPR = 1634,
1650 : S_ATOMIC_XOR_SGPR_RTN = 1635,
1651 : S_ATOMIC_XOR_X2_IMM = 1636,
1652 : S_ATOMIC_XOR_X2_IMM_RTN = 1637,
1653 : S_ATOMIC_XOR_X2_SGPR = 1638,
1654 : S_ATOMIC_XOR_X2_SGPR_RTN = 1639,
1655 : S_BCNT0_I32_B32 = 1640,
1656 : S_BCNT0_I32_B64 = 1641,
1657 : S_BCNT1_I32_B32 = 1642,
1658 : S_BCNT1_I32_B64 = 1643,
1659 : S_BFE_I32 = 1644,
1660 : S_BFE_I64 = 1645,
1661 : S_BFE_U32 = 1646,
1662 : S_BFE_U64 = 1647,
1663 : S_BFM_B32 = 1648,
1664 : S_BFM_B64 = 1649,
1665 : S_BITREPLICATE_B64_B32 = 1650,
1666 : S_BITSET0_B32 = 1651,
1667 : S_BITSET0_B64 = 1652,
1668 : S_BITSET1_B32 = 1653,
1669 : S_BITSET1_B64 = 1654,
1670 : S_BREV_B32 = 1655,
1671 : S_BREV_B64 = 1656,
1672 : S_BUFFER_ATOMIC_ADD_IMM = 1657,
1673 : S_BUFFER_ATOMIC_ADD_IMM_RTN = 1658,
1674 : S_BUFFER_ATOMIC_ADD_SGPR = 1659,
1675 : S_BUFFER_ATOMIC_ADD_SGPR_RTN = 1660,
1676 : S_BUFFER_ATOMIC_ADD_X2_IMM = 1661,
1677 : S_BUFFER_ATOMIC_ADD_X2_IMM_RTN = 1662,
1678 : S_BUFFER_ATOMIC_ADD_X2_SGPR = 1663,
1679 : S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN = 1664,
1680 : S_BUFFER_ATOMIC_AND_IMM = 1665,
1681 : S_BUFFER_ATOMIC_AND_IMM_RTN = 1666,
1682 : S_BUFFER_ATOMIC_AND_SGPR = 1667,
1683 : S_BUFFER_ATOMIC_AND_SGPR_RTN = 1668,
1684 : S_BUFFER_ATOMIC_AND_X2_IMM = 1669,
1685 : S_BUFFER_ATOMIC_AND_X2_IMM_RTN = 1670,
1686 : S_BUFFER_ATOMIC_AND_X2_SGPR = 1671,
1687 : S_BUFFER_ATOMIC_AND_X2_SGPR_RTN = 1672,
1688 : S_BUFFER_ATOMIC_CMPSWAP_IMM = 1673,
1689 : S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN = 1674,
1690 : S_BUFFER_ATOMIC_CMPSWAP_SGPR = 1675,
1691 : S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN = 1676,
1692 : S_BUFFER_ATOMIC_CMPSWAP_X2_IMM = 1677,
1693 : S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN = 1678,
1694 : S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR = 1679,
1695 : S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN = 1680,
1696 : S_BUFFER_ATOMIC_DEC_IMM = 1681,
1697 : S_BUFFER_ATOMIC_DEC_IMM_RTN = 1682,
1698 : S_BUFFER_ATOMIC_DEC_SGPR = 1683,
1699 : S_BUFFER_ATOMIC_DEC_SGPR_RTN = 1684,
1700 : S_BUFFER_ATOMIC_DEC_X2_IMM = 1685,
1701 : S_BUFFER_ATOMIC_DEC_X2_IMM_RTN = 1686,
1702 : S_BUFFER_ATOMIC_DEC_X2_SGPR = 1687,
1703 : S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN = 1688,
1704 : S_BUFFER_ATOMIC_INC_IMM = 1689,
1705 : S_BUFFER_ATOMIC_INC_IMM_RTN = 1690,
1706 : S_BUFFER_ATOMIC_INC_SGPR = 1691,
1707 : S_BUFFER_ATOMIC_INC_SGPR_RTN = 1692,
1708 : S_BUFFER_ATOMIC_INC_X2_IMM = 1693,
1709 : S_BUFFER_ATOMIC_INC_X2_IMM_RTN = 1694,
1710 : S_BUFFER_ATOMIC_INC_X2_SGPR = 1695,
1711 : S_BUFFER_ATOMIC_INC_X2_SGPR_RTN = 1696,
1712 : S_BUFFER_ATOMIC_OR_IMM = 1697,
1713 : S_BUFFER_ATOMIC_OR_IMM_RTN = 1698,
1714 : S_BUFFER_ATOMIC_OR_SGPR = 1699,
1715 : S_BUFFER_ATOMIC_OR_SGPR_RTN = 1700,
1716 : S_BUFFER_ATOMIC_OR_X2_IMM = 1701,
1717 : S_BUFFER_ATOMIC_OR_X2_IMM_RTN = 1702,
1718 : S_BUFFER_ATOMIC_OR_X2_SGPR = 1703,
1719 : S_BUFFER_ATOMIC_OR_X2_SGPR_RTN = 1704,
1720 : S_BUFFER_ATOMIC_SMAX_IMM = 1705,
1721 : S_BUFFER_ATOMIC_SMAX_IMM_RTN = 1706,
1722 : S_BUFFER_ATOMIC_SMAX_SGPR = 1707,
1723 : S_BUFFER_ATOMIC_SMAX_SGPR_RTN = 1708,
1724 : S_BUFFER_ATOMIC_SMAX_X2_IMM = 1709,
1725 : S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN = 1710,
1726 : S_BUFFER_ATOMIC_SMAX_X2_SGPR = 1711,
1727 : S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN = 1712,
1728 : S_BUFFER_ATOMIC_SMIN_IMM = 1713,
1729 : S_BUFFER_ATOMIC_SMIN_IMM_RTN = 1714,
1730 : S_BUFFER_ATOMIC_SMIN_SGPR = 1715,
1731 : S_BUFFER_ATOMIC_SMIN_SGPR_RTN = 1716,
1732 : S_BUFFER_ATOMIC_SMIN_X2_IMM = 1717,
1733 : S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN = 1718,
1734 : S_BUFFER_ATOMIC_SMIN_X2_SGPR = 1719,
1735 : S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN = 1720,
1736 : S_BUFFER_ATOMIC_SUB_IMM = 1721,
1737 : S_BUFFER_ATOMIC_SUB_IMM_RTN = 1722,
1738 : S_BUFFER_ATOMIC_SUB_SGPR = 1723,
1739 : S_BUFFER_ATOMIC_SUB_SGPR_RTN = 1724,
1740 : S_BUFFER_ATOMIC_SUB_X2_IMM = 1725,
1741 : S_BUFFER_ATOMIC_SUB_X2_IMM_RTN = 1726,
1742 : S_BUFFER_ATOMIC_SUB_X2_SGPR = 1727,
1743 : S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN = 1728,
1744 : S_BUFFER_ATOMIC_SWAP_IMM = 1729,
1745 : S_BUFFER_ATOMIC_SWAP_IMM_RTN = 1730,
1746 : S_BUFFER_ATOMIC_SWAP_SGPR = 1731,
1747 : S_BUFFER_ATOMIC_SWAP_SGPR_RTN = 1732,
1748 : S_BUFFER_ATOMIC_SWAP_X2_IMM = 1733,
1749 : S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN = 1734,
1750 : S_BUFFER_ATOMIC_SWAP_X2_SGPR = 1735,
1751 : S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN = 1736,
1752 : S_BUFFER_ATOMIC_UMAX_IMM = 1737,
1753 : S_BUFFER_ATOMIC_UMAX_IMM_RTN = 1738,
1754 : S_BUFFER_ATOMIC_UMAX_SGPR = 1739,
1755 : S_BUFFER_ATOMIC_UMAX_SGPR_RTN = 1740,
1756 : S_BUFFER_ATOMIC_UMAX_X2_IMM = 1741,
1757 : S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN = 1742,
1758 : S_BUFFER_ATOMIC_UMAX_X2_SGPR = 1743,
1759 : S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN = 1744,
1760 : S_BUFFER_ATOMIC_UMIN_IMM = 1745,
1761 : S_BUFFER_ATOMIC_UMIN_IMM_RTN = 1746,
1762 : S_BUFFER_ATOMIC_UMIN_SGPR = 1747,
1763 : S_BUFFER_ATOMIC_UMIN_SGPR_RTN = 1748,
1764 : S_BUFFER_ATOMIC_UMIN_X2_IMM = 1749,
1765 : S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN = 1750,
1766 : S_BUFFER_ATOMIC_UMIN_X2_SGPR = 1751,
1767 : S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN = 1752,
1768 : S_BUFFER_ATOMIC_XOR_IMM = 1753,
1769 : S_BUFFER_ATOMIC_XOR_IMM_RTN = 1754,
1770 : S_BUFFER_ATOMIC_XOR_SGPR = 1755,
1771 : S_BUFFER_ATOMIC_XOR_SGPR_RTN = 1756,
1772 : S_BUFFER_ATOMIC_XOR_X2_IMM = 1757,
1773 : S_BUFFER_ATOMIC_XOR_X2_IMM_RTN = 1758,
1774 : S_BUFFER_ATOMIC_XOR_X2_SGPR = 1759,
1775 : S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN = 1760,
1776 : S_BUFFER_LOAD_DWORDX16_IMM = 1761,
1777 : S_BUFFER_LOAD_DWORDX16_SGPR = 1762,
1778 : S_BUFFER_LOAD_DWORDX2_IMM = 1763,
1779 : S_BUFFER_LOAD_DWORDX2_SGPR = 1764,
1780 : S_BUFFER_LOAD_DWORDX4_IMM = 1765,
1781 : S_BUFFER_LOAD_DWORDX4_SGPR = 1766,
1782 : S_BUFFER_LOAD_DWORDX8_IMM = 1767,
1783 : S_BUFFER_LOAD_DWORDX8_SGPR = 1768,
1784 : S_BUFFER_LOAD_DWORD_IMM = 1769,
1785 : S_BUFFER_LOAD_DWORD_SGPR = 1770,
1786 : S_BUFFER_STORE_DWORDX2_IMM = 1771,
1787 : S_BUFFER_STORE_DWORDX2_SGPR = 1772,
1788 : S_BUFFER_STORE_DWORDX4_IMM = 1773,
1789 : S_BUFFER_STORE_DWORDX4_SGPR = 1774,
1790 : S_BUFFER_STORE_DWORD_IMM = 1775,
1791 : S_BUFFER_STORE_DWORD_SGPR = 1776,
1792 : S_CALL_B64 = 1777,
1793 : S_CBRANCH_G_FORK = 1778,
1794 : S_CBRANCH_I_FORK = 1779,
1795 : S_CBRANCH_JOIN = 1780,
1796 : S_CMOVK_I32 = 1781,
1797 : S_CMOV_B32 = 1782,
1798 : S_CMOV_B64 = 1783,
1799 : S_CMPK_EQ_I32 = 1784,
1800 : S_CMPK_EQ_U32 = 1785,
1801 : S_CMPK_GE_I32 = 1786,
1802 : S_CMPK_GE_U32 = 1787,
1803 : S_CMPK_GT_I32 = 1788,
1804 : S_CMPK_GT_U32 = 1789,
1805 : S_CMPK_LE_I32 = 1790,
1806 : S_CMPK_LE_U32 = 1791,
1807 : S_CMPK_LG_I32 = 1792,
1808 : S_CMPK_LG_U32 = 1793,
1809 : S_CMPK_LT_I32 = 1794,
1810 : S_CMPK_LT_U32 = 1795,
1811 : S_CSELECT_B32 = 1796,
1812 : S_CSELECT_B64 = 1797,
1813 : S_DCACHE_DISCARD_IMM = 1798,
1814 : S_DCACHE_DISCARD_SGPR = 1799,
1815 : S_DCACHE_DISCARD_X2_IMM = 1800,
1816 : S_DCACHE_DISCARD_X2_SGPR = 1801,
1817 : S_DCACHE_INV = 1802,
1818 : S_DCACHE_INV_VOL = 1803,
1819 : S_DCACHE_WB = 1804,
1820 : S_DCACHE_WB_VOL = 1805,
1821 : S_FF0_I32_B32 = 1806,
1822 : S_FF0_I32_B64 = 1807,
1823 : S_FF1_I32_B32 = 1808,
1824 : S_FF1_I32_B64 = 1809,
1825 : S_FLBIT_I32 = 1810,
1826 : S_FLBIT_I32_B32 = 1811,
1827 : S_FLBIT_I32_B64 = 1812,
1828 : S_FLBIT_I32_I64 = 1813,
1829 : S_GETPC_B64 = 1814,
1830 : S_GETREG_B32 = 1815,
1831 : S_LOAD_DWORDX16_IMM = 1816,
1832 : S_LOAD_DWORDX16_SGPR = 1817,
1833 : S_LOAD_DWORDX2_IMM = 1818,
1834 : S_LOAD_DWORDX2_SGPR = 1819,
1835 : S_LOAD_DWORDX4_IMM = 1820,
1836 : S_LOAD_DWORDX4_SGPR = 1821,
1837 : S_LOAD_DWORDX8_IMM = 1822,
1838 : S_LOAD_DWORDX8_SGPR = 1823,
1839 : S_LOAD_DWORD_IMM = 1824,
1840 : S_LOAD_DWORD_SGPR = 1825,
1841 : S_LSHL1_ADD_U32 = 1826,
1842 : S_LSHL2_ADD_U32 = 1827,
1843 : S_LSHL3_ADD_U32 = 1828,
1844 : S_LSHL4_ADD_U32 = 1829,
1845 : S_LSHL_B32 = 1830,
1846 : S_LSHL_B64 = 1831,
1847 : S_LSHR_B32 = 1832,
1848 : S_LSHR_B64 = 1833,
1849 : S_MAX_I32 = 1834,
1850 : S_MAX_U32 = 1835,
1851 : S_MEMREALTIME = 1836,
1852 : S_MEMTIME = 1837,
1853 : S_MIN_I32 = 1838,
1854 : S_MIN_U32 = 1839,
1855 : S_MOVK_I32 = 1840,
1856 : S_MOVRELD_B32 = 1841,
1857 : S_MOVRELD_B64 = 1842,
1858 : S_MOVRELS_B32 = 1843,
1859 : S_MOVRELS_B64 = 1844,
1860 : S_MOV_B32 = 1845,
1861 : S_MOV_B64 = 1846,
1862 : S_MOV_B64_term = 1847,
1863 : S_MOV_FED_B32 = 1848,
1864 : S_MOV_REGRD_B32 = 1849,
1865 : S_MULK_I32 = 1850,
1866 : S_MUL_HI_I32 = 1851,
1867 : S_MUL_HI_U32 = 1852,
1868 : S_MUL_I32 = 1853,
1869 : S_NAND_B32 = 1854,
1870 : S_NAND_B64 = 1855,
1871 : S_NAND_SAVEEXEC_B64 = 1856,
1872 : S_NOR_B32 = 1857,
1873 : S_NOR_B64 = 1858,
1874 : S_NOR_SAVEEXEC_B64 = 1859,
1875 : S_NOT_B32 = 1860,
1876 : S_NOT_B64 = 1861,
1877 : S_ORN1_SAVEEXEC_B64 = 1862,
1878 : S_ORN2_B32 = 1863,
1879 : S_ORN2_B64 = 1864,
1880 : S_ORN2_SAVEEXEC_B64 = 1865,
1881 : S_OR_B32 = 1866,
1882 : S_OR_B64 = 1867,
1883 : S_OR_SAVEEXEC_B64 = 1868,
1884 : S_PACK_HH_B32_B16 = 1869,
1885 : S_PACK_LH_B32_B16 = 1870,
1886 : S_PACK_LL_B32_B16 = 1871,
1887 : S_QUADMASK_B32 = 1872,
1888 : S_QUADMASK_B64 = 1873,
1889 : S_RFE_B64 = 1874,
1890 : S_RFE_RESTORE_B64 = 1875,
1891 : S_SCRATCH_LOAD_DWORDX2_IMM = 1876,
1892 : S_SCRATCH_LOAD_DWORDX2_SGPR = 1877,
1893 : S_SCRATCH_LOAD_DWORDX4_IMM = 1878,
1894 : S_SCRATCH_LOAD_DWORDX4_SGPR = 1879,
1895 : S_SCRATCH_LOAD_DWORD_IMM = 1880,
1896 : S_SCRATCH_LOAD_DWORD_SGPR = 1881,
1897 : S_SCRATCH_STORE_DWORDX2_IMM = 1882,
1898 : S_SCRATCH_STORE_DWORDX2_SGPR = 1883,
1899 : S_SCRATCH_STORE_DWORDX4_IMM = 1884,
1900 : S_SCRATCH_STORE_DWORDX4_SGPR = 1885,
1901 : S_SCRATCH_STORE_DWORD_IMM = 1886,
1902 : S_SCRATCH_STORE_DWORD_SGPR = 1887,
1903 : S_SETPC_B64 = 1888,
1904 : S_SETPC_B64_return = 1889,
1905 : S_SETREG_B32 = 1890,
1906 : S_SETREG_IMM32_B32 = 1891,
1907 : S_SET_GPR_IDX_IDX = 1892,
1908 : S_SEXT_I32_I16 = 1893,
1909 : S_SEXT_I32_I8 = 1894,
1910 : S_STORE_DWORDX2_IMM = 1895,
1911 : S_STORE_DWORDX2_SGPR = 1896,
1912 : S_STORE_DWORDX4_IMM = 1897,
1913 : S_STORE_DWORDX4_SGPR = 1898,
1914 : S_STORE_DWORD_IMM = 1899,
1915 : S_STORE_DWORD_SGPR = 1900,
1916 : S_SUBB_U32 = 1901,
1917 : S_SUB_I32 = 1902,
1918 : S_SUB_U32 = 1903,
1919 : S_SUB_U64_CO_PSEUDO = 1904,
1920 : S_SUB_U64_PSEUDO = 1905,
1921 : S_SWAPPC_B64 = 1906,
1922 : S_WQM_B32 = 1907,
1923 : S_WQM_B64 = 1908,
1924 : S_XNOR_B32 = 1909,
1925 : S_XNOR_B64 = 1910,
1926 : S_XNOR_SAVEEXEC_B64 = 1911,
1927 : S_XOR_B32 = 1912,
1928 : S_XOR_B64 = 1913,
1929 : S_XOR_B64_term = 1914,
1930 : S_XOR_SAVEEXEC_B64 = 1915,
1931 : TBUFFER_LOAD_FORMAT_D16_XYZW_ADDR64 = 1916,
1932 : TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN = 1917,
1933 : TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_exact = 1918,
1934 : TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN = 1919,
1935 : TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_exact = 1920,
1936 : TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN = 1921,
1937 : TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_exact = 1922,
1938 : TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET = 1923,
1939 : TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_exact = 1924,
1940 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_ADDR64 = 1925,
1941 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN = 1926,
1942 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_exact = 1927,
1943 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN = 1928,
1944 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_exact = 1929,
1945 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN = 1930,
1946 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_exact = 1931,
1947 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET = 1932,
1948 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_exact = 1933,
1949 : TBUFFER_LOAD_FORMAT_D16_XYZ_ADDR64 = 1934,
1950 : TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN = 1935,
1951 : TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_exact = 1936,
1952 : TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN = 1937,
1953 : TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_exact = 1938,
1954 : TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN = 1939,
1955 : TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_exact = 1940,
1956 : TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET = 1941,
1957 : TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_exact = 1942,
1958 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_ADDR64 = 1943,
1959 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN = 1944,
1960 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_exact = 1945,
1961 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN = 1946,
1962 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_exact = 1947,
1963 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN = 1948,
1964 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_exact = 1949,
1965 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET = 1950,
1966 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_exact = 1951,
1967 : TBUFFER_LOAD_FORMAT_D16_XY_ADDR64 = 1952,
1968 : TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN = 1953,
1969 : TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_exact = 1954,
1970 : TBUFFER_LOAD_FORMAT_D16_XY_IDXEN = 1955,
1971 : TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_exact = 1956,
1972 : TBUFFER_LOAD_FORMAT_D16_XY_OFFEN = 1957,
1973 : TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_exact = 1958,
1974 : TBUFFER_LOAD_FORMAT_D16_XY_OFFSET = 1959,
1975 : TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_exact = 1960,
1976 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_ADDR64 = 1961,
1977 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN = 1962,
1978 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_exact = 1963,
1979 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN = 1964,
1980 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_exact = 1965,
1981 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN = 1966,
1982 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_exact = 1967,
1983 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET = 1968,
1984 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_exact = 1969,
1985 : TBUFFER_LOAD_FORMAT_D16_X_ADDR64 = 1970,
1986 : TBUFFER_LOAD_FORMAT_D16_X_BOTHEN = 1971,
1987 : TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_exact = 1972,
1988 : TBUFFER_LOAD_FORMAT_D16_X_IDXEN = 1973,
1989 : TBUFFER_LOAD_FORMAT_D16_X_IDXEN_exact = 1974,
1990 : TBUFFER_LOAD_FORMAT_D16_X_OFFEN = 1975,
1991 : TBUFFER_LOAD_FORMAT_D16_X_OFFEN_exact = 1976,
1992 : TBUFFER_LOAD_FORMAT_D16_X_OFFSET = 1977,
1993 : TBUFFER_LOAD_FORMAT_D16_X_OFFSET_exact = 1978,
1994 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_ADDR64 = 1979,
1995 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN = 1980,
1996 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_exact = 1981,
1997 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN = 1982,
1998 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_exact = 1983,
1999 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN = 1984,
2000 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_exact = 1985,
2001 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET = 1986,
2002 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_exact = 1987,
2003 : TBUFFER_LOAD_FORMAT_XYZW_ADDR64 = 1988,
2004 : TBUFFER_LOAD_FORMAT_XYZW_BOTHEN = 1989,
2005 : TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_exact = 1990,
2006 : TBUFFER_LOAD_FORMAT_XYZW_IDXEN = 1991,
2007 : TBUFFER_LOAD_FORMAT_XYZW_IDXEN_exact = 1992,
2008 : TBUFFER_LOAD_FORMAT_XYZW_OFFEN = 1993,
2009 : TBUFFER_LOAD_FORMAT_XYZW_OFFEN_exact = 1994,
2010 : TBUFFER_LOAD_FORMAT_XYZW_OFFSET = 1995,
2011 : TBUFFER_LOAD_FORMAT_XYZW_OFFSET_exact = 1996,
2012 : TBUFFER_LOAD_FORMAT_XYZ_ADDR64 = 1997,
2013 : TBUFFER_LOAD_FORMAT_XYZ_BOTHEN = 1998,
2014 : TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_exact = 1999,
2015 : TBUFFER_LOAD_FORMAT_XYZ_IDXEN = 2000,
2016 : TBUFFER_LOAD_FORMAT_XYZ_IDXEN_exact = 2001,
2017 : TBUFFER_LOAD_FORMAT_XYZ_OFFEN = 2002,
2018 : TBUFFER_LOAD_FORMAT_XYZ_OFFEN_exact = 2003,
2019 : TBUFFER_LOAD_FORMAT_XYZ_OFFSET = 2004,
2020 : TBUFFER_LOAD_FORMAT_XYZ_OFFSET_exact = 2005,
2021 : TBUFFER_LOAD_FORMAT_XY_ADDR64 = 2006,
2022 : TBUFFER_LOAD_FORMAT_XY_BOTHEN = 2007,
2023 : TBUFFER_LOAD_FORMAT_XY_BOTHEN_exact = 2008,
2024 : TBUFFER_LOAD_FORMAT_XY_IDXEN = 2009,
2025 : TBUFFER_LOAD_FORMAT_XY_IDXEN_exact = 2010,
2026 : TBUFFER_LOAD_FORMAT_XY_OFFEN = 2011,
2027 : TBUFFER_LOAD_FORMAT_XY_OFFEN_exact = 2012,
2028 : TBUFFER_LOAD_FORMAT_XY_OFFSET = 2013,
2029 : TBUFFER_LOAD_FORMAT_XY_OFFSET_exact = 2014,
2030 : TBUFFER_LOAD_FORMAT_X_ADDR64 = 2015,
2031 : TBUFFER_LOAD_FORMAT_X_BOTHEN = 2016,
2032 : TBUFFER_LOAD_FORMAT_X_BOTHEN_exact = 2017,
2033 : TBUFFER_LOAD_FORMAT_X_IDXEN = 2018,
2034 : TBUFFER_LOAD_FORMAT_X_IDXEN_exact = 2019,
2035 : TBUFFER_LOAD_FORMAT_X_OFFEN = 2020,
2036 : TBUFFER_LOAD_FORMAT_X_OFFEN_exact = 2021,
2037 : TBUFFER_LOAD_FORMAT_X_OFFSET = 2022,
2038 : TBUFFER_LOAD_FORMAT_X_OFFSET_exact = 2023,
2039 : TBUFFER_STORE_FORMAT_D16_XYZW_ADDR64 = 2024,
2040 : TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN = 2025,
2041 : TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact = 2026,
2042 : TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN = 2027,
2043 : TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact = 2028,
2044 : TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN = 2029,
2045 : TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact = 2030,
2046 : TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET = 2031,
2047 : TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact = 2032,
2048 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_ADDR64 = 2033,
2049 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN = 2034,
2050 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact = 2035,
2051 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN = 2036,
2052 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact = 2037,
2053 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN = 2038,
2054 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact = 2039,
2055 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET = 2040,
2056 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact = 2041,
2057 : TBUFFER_STORE_FORMAT_D16_XYZ_ADDR64 = 2042,
2058 : TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN = 2043,
2059 : TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact = 2044,
2060 : TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN = 2045,
2061 : TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_exact = 2046,
2062 : TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN = 2047,
2063 : TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact = 2048,
2064 : TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET = 2049,
2065 : TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_exact = 2050,
2066 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_ADDR64 = 2051,
2067 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN = 2052,
2068 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact = 2053,
2069 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN = 2054,
2070 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact = 2055,
2071 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN = 2056,
2072 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact = 2057,
2073 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET = 2058,
2074 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact = 2059,
2075 : TBUFFER_STORE_FORMAT_D16_XY_ADDR64 = 2060,
2076 : TBUFFER_STORE_FORMAT_D16_XY_BOTHEN = 2061,
2077 : TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact = 2062,
2078 : TBUFFER_STORE_FORMAT_D16_XY_IDXEN = 2063,
2079 : TBUFFER_STORE_FORMAT_D16_XY_IDXEN_exact = 2064,
2080 : TBUFFER_STORE_FORMAT_D16_XY_OFFEN = 2065,
2081 : TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact = 2066,
2082 : TBUFFER_STORE_FORMAT_D16_XY_OFFSET = 2067,
2083 : TBUFFER_STORE_FORMAT_D16_XY_OFFSET_exact = 2068,
2084 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_ADDR64 = 2069,
2085 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN = 2070,
2086 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact = 2071,
2087 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN = 2072,
2088 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact = 2073,
2089 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN = 2074,
2090 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact = 2075,
2091 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET = 2076,
2092 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact = 2077,
2093 : TBUFFER_STORE_FORMAT_D16_X_ADDR64 = 2078,
2094 : TBUFFER_STORE_FORMAT_D16_X_BOTHEN = 2079,
2095 : TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact = 2080,
2096 : TBUFFER_STORE_FORMAT_D16_X_IDXEN = 2081,
2097 : TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact = 2082,
2098 : TBUFFER_STORE_FORMAT_D16_X_OFFEN = 2083,
2099 : TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact = 2084,
2100 : TBUFFER_STORE_FORMAT_D16_X_OFFSET = 2085,
2101 : TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact = 2086,
2102 : TBUFFER_STORE_FORMAT_D16_X_gfx80_ADDR64 = 2087,
2103 : TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN = 2088,
2104 : TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact = 2089,
2105 : TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN = 2090,
2106 : TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact = 2091,
2107 : TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN = 2092,
2108 : TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact = 2093,
2109 : TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET = 2094,
2110 : TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact = 2095,
2111 : TBUFFER_STORE_FORMAT_XYZW_ADDR64 = 2096,
2112 : TBUFFER_STORE_FORMAT_XYZW_BOTHEN = 2097,
2113 : TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact = 2098,
2114 : TBUFFER_STORE_FORMAT_XYZW_IDXEN = 2099,
2115 : TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact = 2100,
2116 : TBUFFER_STORE_FORMAT_XYZW_OFFEN = 2101,
2117 : TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact = 2102,
2118 : TBUFFER_STORE_FORMAT_XYZW_OFFSET = 2103,
2119 : TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact = 2104,
2120 : TBUFFER_STORE_FORMAT_XYZ_ADDR64 = 2105,
2121 : TBUFFER_STORE_FORMAT_XYZ_BOTHEN = 2106,
2122 : TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact = 2107,
2123 : TBUFFER_STORE_FORMAT_XYZ_IDXEN = 2108,
2124 : TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact = 2109,
2125 : TBUFFER_STORE_FORMAT_XYZ_OFFEN = 2110,
2126 : TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact = 2111,
2127 : TBUFFER_STORE_FORMAT_XYZ_OFFSET = 2112,
2128 : TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact = 2113,
2129 : TBUFFER_STORE_FORMAT_XY_ADDR64 = 2114,
2130 : TBUFFER_STORE_FORMAT_XY_BOTHEN = 2115,
2131 : TBUFFER_STORE_FORMAT_XY_BOTHEN_exact = 2116,
2132 : TBUFFER_STORE_FORMAT_XY_IDXEN = 2117,
2133 : TBUFFER_STORE_FORMAT_XY_IDXEN_exact = 2118,
2134 : TBUFFER_STORE_FORMAT_XY_OFFEN = 2119,
2135 : TBUFFER_STORE_FORMAT_XY_OFFEN_exact = 2120,
2136 : TBUFFER_STORE_FORMAT_XY_OFFSET = 2121,
2137 : TBUFFER_STORE_FORMAT_XY_OFFSET_exact = 2122,
2138 : TBUFFER_STORE_FORMAT_X_ADDR64 = 2123,
2139 : TBUFFER_STORE_FORMAT_X_BOTHEN = 2124,
2140 : TBUFFER_STORE_FORMAT_X_BOTHEN_exact = 2125,
2141 : TBUFFER_STORE_FORMAT_X_IDXEN = 2126,
2142 : TBUFFER_STORE_FORMAT_X_IDXEN_exact = 2127,
2143 : TBUFFER_STORE_FORMAT_X_OFFEN = 2128,
2144 : TBUFFER_STORE_FORMAT_X_OFFEN_exact = 2129,
2145 : TBUFFER_STORE_FORMAT_X_OFFSET = 2130,
2146 : TBUFFER_STORE_FORMAT_X_OFFSET_exact = 2131,
2147 : V_ADD3_U32 = 2132,
2148 : V_ADDC_U32_e32 = 2133,
2149 : V_ADDC_U32_e64 = 2134,
2150 : V_ADDC_U32_sdwa = 2135,
2151 : V_ADD_F16_e32 = 2136,
2152 : V_ADD_F16_e64 = 2137,
2153 : V_ADD_F16_sdwa = 2138,
2154 : V_ADD_F32_e32 = 2139,
2155 : V_ADD_F32_e64 = 2140,
2156 : V_ADD_F32_sdwa = 2141,
2157 : V_ADD_F64 = 2142,
2158 : V_ADD_I16 = 2143,
2159 : V_ADD_I32_e32 = 2144,
2160 : V_ADD_I32_e64 = 2145,
2161 : V_ADD_I32_gfx9 = 2146,
2162 : V_ADD_I32_sdwa = 2147,
2163 : V_ADD_LSHL_U32 = 2148,
2164 : V_ADD_U16_e32 = 2149,
2165 : V_ADD_U16_e64 = 2150,
2166 : V_ADD_U16_sdwa = 2151,
2167 : V_ADD_U32_e32 = 2152,
2168 : V_ADD_U32_e64 = 2153,
2169 : V_ADD_U32_sdwa = 2154,
2170 : V_ALIGNBIT_B32 = 2155,
2171 : V_ALIGNBYTE_B32 = 2156,
2172 : V_AND_B32_e32 = 2157,
2173 : V_AND_B32_e64 = 2158,
2174 : V_AND_B32_sdwa = 2159,
2175 : V_AND_OR_B32 = 2160,
2176 : V_ASHRREV_I16_e32 = 2161,
2177 : V_ASHRREV_I16_e64 = 2162,
2178 : V_ASHRREV_I16_sdwa = 2163,
2179 : V_ASHRREV_I32_e32 = 2164,
2180 : V_ASHRREV_I32_e64 = 2165,
2181 : V_ASHRREV_I32_sdwa = 2166,
2182 : V_ASHRREV_I64 = 2167,
2183 : V_ASHR_I32_e32 = 2168,
2184 : V_ASHR_I32_e64 = 2169,
2185 : V_ASHR_I32_sdwa = 2170,
2186 : V_ASHR_I64 = 2171,
2187 : V_BCNT_U32_B32_e32 = 2172,
2188 : V_BCNT_U32_B32_e64 = 2173,
2189 : V_BCNT_U32_B32_sdwa = 2174,
2190 : V_BFE_I32 = 2175,
2191 : V_BFE_U32 = 2176,
2192 : V_BFI_B32 = 2177,
2193 : V_BFM_B32_e32 = 2178,
2194 : V_BFM_B32_e64 = 2179,
2195 : V_BFM_B32_sdwa = 2180,
2196 : V_BFREV_B32_e32 = 2181,
2197 : V_BFREV_B32_e64 = 2182,
2198 : V_BFREV_B32_sdwa = 2183,
2199 : V_CEIL_F16_e32 = 2184,
2200 : V_CEIL_F16_e64 = 2185,
2201 : V_CEIL_F16_sdwa = 2186,
2202 : V_CEIL_F32_e32 = 2187,
2203 : V_CEIL_F32_e64 = 2188,
2204 : V_CEIL_F32_sdwa = 2189,
2205 : V_CEIL_F64_e32 = 2190,
2206 : V_CEIL_F64_e64 = 2191,
2207 : V_CEIL_F64_sdwa = 2192,
2208 : V_CLREXCP_e32 = 2193,
2209 : V_CLREXCP_e64 = 2194,
2210 : V_CLREXCP_sdwa = 2195,
2211 : V_CMPSX_EQ_F32_e32 = 2196,
2212 : V_CMPSX_EQ_F32_e64 = 2197,
2213 : V_CMPSX_EQ_F32_sdwa = 2198,
2214 : V_CMPSX_EQ_F64_e32 = 2199,
2215 : V_CMPSX_EQ_F64_e64 = 2200,
2216 : V_CMPSX_EQ_F64_sdwa = 2201,
2217 : V_CMPSX_F_F32_e32 = 2202,
2218 : V_CMPSX_F_F32_e64 = 2203,
2219 : V_CMPSX_F_F32_sdwa = 2204,
2220 : V_CMPSX_F_F64_e32 = 2205,
2221 : V_CMPSX_F_F64_e64 = 2206,
2222 : V_CMPSX_F_F64_sdwa = 2207,
2223 : V_CMPSX_GE_F32_e32 = 2208,
2224 : V_CMPSX_GE_F32_e64 = 2209,
2225 : V_CMPSX_GE_F32_sdwa = 2210,
2226 : V_CMPSX_GE_F64_e32 = 2211,
2227 : V_CMPSX_GE_F64_e64 = 2212,
2228 : V_CMPSX_GE_F64_sdwa = 2213,
2229 : V_CMPSX_GT_F32_e32 = 2214,
2230 : V_CMPSX_GT_F32_e64 = 2215,
2231 : V_CMPSX_GT_F32_sdwa = 2216,
2232 : V_CMPSX_GT_F64_e32 = 2217,
2233 : V_CMPSX_GT_F64_e64 = 2218,
2234 : V_CMPSX_GT_F64_sdwa = 2219,
2235 : V_CMPSX_LE_F32_e32 = 2220,
2236 : V_CMPSX_LE_F32_e64 = 2221,
2237 : V_CMPSX_LE_F32_sdwa = 2222,
2238 : V_CMPSX_LE_F64_e32 = 2223,
2239 : V_CMPSX_LE_F64_e64 = 2224,
2240 : V_CMPSX_LE_F64_sdwa = 2225,
2241 : V_CMPSX_LG_F32_e32 = 2226,
2242 : V_CMPSX_LG_F32_e64 = 2227,
2243 : V_CMPSX_LG_F32_sdwa = 2228,
2244 : V_CMPSX_LG_F64_e32 = 2229,
2245 : V_CMPSX_LG_F64_e64 = 2230,
2246 : V_CMPSX_LG_F64_sdwa = 2231,
2247 : V_CMPSX_LT_F32_e32 = 2232,
2248 : V_CMPSX_LT_F32_e64 = 2233,
2249 : V_CMPSX_LT_F32_sdwa = 2234,
2250 : V_CMPSX_LT_F64_e32 = 2235,
2251 : V_CMPSX_LT_F64_e64 = 2236,
2252 : V_CMPSX_LT_F64_sdwa = 2237,
2253 : V_CMPSX_NEQ_F32_e32 = 2238,
2254 : V_CMPSX_NEQ_F32_e64 = 2239,
2255 : V_CMPSX_NEQ_F32_sdwa = 2240,
2256 : V_CMPSX_NEQ_F64_e32 = 2241,
2257 : V_CMPSX_NEQ_F64_e64 = 2242,
2258 : V_CMPSX_NEQ_F64_sdwa = 2243,
2259 : V_CMPSX_NGE_F32_e32 = 2244,
2260 : V_CMPSX_NGE_F32_e64 = 2245,
2261 : V_CMPSX_NGE_F32_sdwa = 2246,
2262 : V_CMPSX_NGE_F64_e32 = 2247,
2263 : V_CMPSX_NGE_F64_e64 = 2248,
2264 : V_CMPSX_NGE_F64_sdwa = 2249,
2265 : V_CMPSX_NGT_F32_e32 = 2250,
2266 : V_CMPSX_NGT_F32_e64 = 2251,
2267 : V_CMPSX_NGT_F32_sdwa = 2252,
2268 : V_CMPSX_NGT_F64_e32 = 2253,
2269 : V_CMPSX_NGT_F64_e64 = 2254,
2270 : V_CMPSX_NGT_F64_sdwa = 2255,
2271 : V_CMPSX_NLE_F32_e32 = 2256,
2272 : V_CMPSX_NLE_F32_e64 = 2257,
2273 : V_CMPSX_NLE_F32_sdwa = 2258,
2274 : V_CMPSX_NLE_F64_e32 = 2259,
2275 : V_CMPSX_NLE_F64_e64 = 2260,
2276 : V_CMPSX_NLE_F64_sdwa = 2261,
2277 : V_CMPSX_NLG_F32_e32 = 2262,
2278 : V_CMPSX_NLG_F32_e64 = 2263,
2279 : V_CMPSX_NLG_F32_sdwa = 2264,
2280 : V_CMPSX_NLG_F64_e32 = 2265,
2281 : V_CMPSX_NLG_F64_e64 = 2266,
2282 : V_CMPSX_NLG_F64_sdwa = 2267,
2283 : V_CMPSX_NLT_F32_e32 = 2268,
2284 : V_CMPSX_NLT_F32_e64 = 2269,
2285 : V_CMPSX_NLT_F32_sdwa = 2270,
2286 : V_CMPSX_NLT_F64_e32 = 2271,
2287 : V_CMPSX_NLT_F64_e64 = 2272,
2288 : V_CMPSX_NLT_F64_sdwa = 2273,
2289 : V_CMPSX_O_F32_e32 = 2274,
2290 : V_CMPSX_O_F32_e64 = 2275,
2291 : V_CMPSX_O_F32_sdwa = 2276,
2292 : V_CMPSX_O_F64_e32 = 2277,
2293 : V_CMPSX_O_F64_e64 = 2278,
2294 : V_CMPSX_O_F64_sdwa = 2279,
2295 : V_CMPSX_TRU_F32_e32 = 2280,
2296 : V_CMPSX_TRU_F32_e64 = 2281,
2297 : V_CMPSX_TRU_F32_sdwa = 2282,
2298 : V_CMPSX_TRU_F64_e32 = 2283,
2299 : V_CMPSX_TRU_F64_e64 = 2284,
2300 : V_CMPSX_TRU_F64_sdwa = 2285,
2301 : V_CMPSX_U_F32_e32 = 2286,
2302 : V_CMPSX_U_F32_e64 = 2287,
2303 : V_CMPSX_U_F32_sdwa = 2288,
2304 : V_CMPSX_U_F64_e32 = 2289,
2305 : V_CMPSX_U_F64_e64 = 2290,
2306 : V_CMPSX_U_F64_sdwa = 2291,
2307 : V_CMPS_EQ_F32_e32 = 2292,
2308 : V_CMPS_EQ_F32_e64 = 2293,
2309 : V_CMPS_EQ_F32_sdwa = 2294,
2310 : V_CMPS_EQ_F64_e32 = 2295,
2311 : V_CMPS_EQ_F64_e64 = 2296,
2312 : V_CMPS_EQ_F64_sdwa = 2297,
2313 : V_CMPS_F_F32_e32 = 2298,
2314 : V_CMPS_F_F32_e64 = 2299,
2315 : V_CMPS_F_F32_sdwa = 2300,
2316 : V_CMPS_F_F64_e32 = 2301,
2317 : V_CMPS_F_F64_e64 = 2302,
2318 : V_CMPS_F_F64_sdwa = 2303,
2319 : V_CMPS_GE_F32_e32 = 2304,
2320 : V_CMPS_GE_F32_e64 = 2305,
2321 : V_CMPS_GE_F32_sdwa = 2306,
2322 : V_CMPS_GE_F64_e32 = 2307,
2323 : V_CMPS_GE_F64_e64 = 2308,
2324 : V_CMPS_GE_F64_sdwa = 2309,
2325 : V_CMPS_GT_F32_e32 = 2310,
2326 : V_CMPS_GT_F32_e64 = 2311,
2327 : V_CMPS_GT_F32_sdwa = 2312,
2328 : V_CMPS_GT_F64_e32 = 2313,
2329 : V_CMPS_GT_F64_e64 = 2314,
2330 : V_CMPS_GT_F64_sdwa = 2315,
2331 : V_CMPS_LE_F32_e32 = 2316,
2332 : V_CMPS_LE_F32_e64 = 2317,
2333 : V_CMPS_LE_F32_sdwa = 2318,
2334 : V_CMPS_LE_F64_e32 = 2319,
2335 : V_CMPS_LE_F64_e64 = 2320,
2336 : V_CMPS_LE_F64_sdwa = 2321,
2337 : V_CMPS_LG_F32_e32 = 2322,
2338 : V_CMPS_LG_F32_e64 = 2323,
2339 : V_CMPS_LG_F32_sdwa = 2324,
2340 : V_CMPS_LG_F64_e32 = 2325,
2341 : V_CMPS_LG_F64_e64 = 2326,
2342 : V_CMPS_LG_F64_sdwa = 2327,
2343 : V_CMPS_LT_F32_e32 = 2328,
2344 : V_CMPS_LT_F32_e64 = 2329,
2345 : V_CMPS_LT_F32_sdwa = 2330,
2346 : V_CMPS_LT_F64_e32 = 2331,
2347 : V_CMPS_LT_F64_e64 = 2332,
2348 : V_CMPS_LT_F64_sdwa = 2333,
2349 : V_CMPS_NEQ_F32_e32 = 2334,
2350 : V_CMPS_NEQ_F32_e64 = 2335,
2351 : V_CMPS_NEQ_F32_sdwa = 2336,
2352 : V_CMPS_NEQ_F64_e32 = 2337,
2353 : V_CMPS_NEQ_F64_e64 = 2338,
2354 : V_CMPS_NEQ_F64_sdwa = 2339,
2355 : V_CMPS_NGE_F32_e32 = 2340,
2356 : V_CMPS_NGE_F32_e64 = 2341,
2357 : V_CMPS_NGE_F32_sdwa = 2342,
2358 : V_CMPS_NGE_F64_e32 = 2343,
2359 : V_CMPS_NGE_F64_e64 = 2344,
2360 : V_CMPS_NGE_F64_sdwa = 2345,
2361 : V_CMPS_NGT_F32_e32 = 2346,
2362 : V_CMPS_NGT_F32_e64 = 2347,
2363 : V_CMPS_NGT_F32_sdwa = 2348,
2364 : V_CMPS_NGT_F64_e32 = 2349,
2365 : V_CMPS_NGT_F64_e64 = 2350,
2366 : V_CMPS_NGT_F64_sdwa = 2351,
2367 : V_CMPS_NLE_F32_e32 = 2352,
2368 : V_CMPS_NLE_F32_e64 = 2353,
2369 : V_CMPS_NLE_F32_sdwa = 2354,
2370 : V_CMPS_NLE_F64_e32 = 2355,
2371 : V_CMPS_NLE_F64_e64 = 2356,
2372 : V_CMPS_NLE_F64_sdwa = 2357,
2373 : V_CMPS_NLG_F32_e32 = 2358,
2374 : V_CMPS_NLG_F32_e64 = 2359,
2375 : V_CMPS_NLG_F32_sdwa = 2360,
2376 : V_CMPS_NLG_F64_e32 = 2361,
2377 : V_CMPS_NLG_F64_e64 = 2362,
2378 : V_CMPS_NLG_F64_sdwa = 2363,
2379 : V_CMPS_NLT_F32_e32 = 2364,
2380 : V_CMPS_NLT_F32_e64 = 2365,
2381 : V_CMPS_NLT_F32_sdwa = 2366,
2382 : V_CMPS_NLT_F64_e32 = 2367,
2383 : V_CMPS_NLT_F64_e64 = 2368,
2384 : V_CMPS_NLT_F64_sdwa = 2369,
2385 : V_CMPS_O_F32_e32 = 2370,
2386 : V_CMPS_O_F32_e64 = 2371,
2387 : V_CMPS_O_F32_sdwa = 2372,
2388 : V_CMPS_O_F64_e32 = 2373,
2389 : V_CMPS_O_F64_e64 = 2374,
2390 : V_CMPS_O_F64_sdwa = 2375,
2391 : V_CMPS_TRU_F32_e32 = 2376,
2392 : V_CMPS_TRU_F32_e64 = 2377,
2393 : V_CMPS_TRU_F32_sdwa = 2378,
2394 : V_CMPS_TRU_F64_e32 = 2379,
2395 : V_CMPS_TRU_F64_e64 = 2380,
2396 : V_CMPS_TRU_F64_sdwa = 2381,
2397 : V_CMPS_U_F32_e32 = 2382,
2398 : V_CMPS_U_F32_e64 = 2383,
2399 : V_CMPS_U_F32_sdwa = 2384,
2400 : V_CMPS_U_F64_e32 = 2385,
2401 : V_CMPS_U_F64_e64 = 2386,
2402 : V_CMPS_U_F64_sdwa = 2387,
2403 : V_CMPX_CLASS_F16_e32 = 2388,
2404 : V_CMPX_CLASS_F16_e64 = 2389,
2405 : V_CMPX_CLASS_F16_sdwa = 2390,
2406 : V_CMPX_CLASS_F32_e32 = 2391,
2407 : V_CMPX_CLASS_F32_e64 = 2392,
2408 : V_CMPX_CLASS_F32_sdwa = 2393,
2409 : V_CMPX_CLASS_F64_e32 = 2394,
2410 : V_CMPX_CLASS_F64_e64 = 2395,
2411 : V_CMPX_CLASS_F64_sdwa = 2396,
2412 : V_CMPX_EQ_F16_e32 = 2397,
2413 : V_CMPX_EQ_F16_e64 = 2398,
2414 : V_CMPX_EQ_F16_sdwa = 2399,
2415 : V_CMPX_EQ_F32_e32 = 2400,
2416 : V_CMPX_EQ_F32_e64 = 2401,
2417 : V_CMPX_EQ_F32_sdwa = 2402,
2418 : V_CMPX_EQ_F64_e32 = 2403,
2419 : V_CMPX_EQ_F64_e64 = 2404,
2420 : V_CMPX_EQ_F64_sdwa = 2405,
2421 : V_CMPX_EQ_I16_e32 = 2406,
2422 : V_CMPX_EQ_I16_e64 = 2407,
2423 : V_CMPX_EQ_I16_sdwa = 2408,
2424 : V_CMPX_EQ_I32_e32 = 2409,
2425 : V_CMPX_EQ_I32_e64 = 2410,
2426 : V_CMPX_EQ_I32_sdwa = 2411,
2427 : V_CMPX_EQ_I64_e32 = 2412,
2428 : V_CMPX_EQ_I64_e64 = 2413,
2429 : V_CMPX_EQ_I64_sdwa = 2414,
2430 : V_CMPX_EQ_U16_e32 = 2415,
2431 : V_CMPX_EQ_U16_e64 = 2416,
2432 : V_CMPX_EQ_U16_sdwa = 2417,
2433 : V_CMPX_EQ_U32_e32 = 2418,
2434 : V_CMPX_EQ_U32_e64 = 2419,
2435 : V_CMPX_EQ_U32_sdwa = 2420,
2436 : V_CMPX_EQ_U64_e32 = 2421,
2437 : V_CMPX_EQ_U64_e64 = 2422,
2438 : V_CMPX_EQ_U64_sdwa = 2423,
2439 : V_CMPX_F_F16_e32 = 2424,
2440 : V_CMPX_F_F16_e64 = 2425,
2441 : V_CMPX_F_F16_sdwa = 2426,
2442 : V_CMPX_F_F32_e32 = 2427,
2443 : V_CMPX_F_F32_e64 = 2428,
2444 : V_CMPX_F_F32_sdwa = 2429,
2445 : V_CMPX_F_F64_e32 = 2430,
2446 : V_CMPX_F_F64_e64 = 2431,
2447 : V_CMPX_F_F64_sdwa = 2432,
2448 : V_CMPX_F_I16_e32 = 2433,
2449 : V_CMPX_F_I16_e64 = 2434,
2450 : V_CMPX_F_I16_sdwa = 2435,
2451 : V_CMPX_F_I32_e32 = 2436,
2452 : V_CMPX_F_I32_e64 = 2437,
2453 : V_CMPX_F_I32_sdwa = 2438,
2454 : V_CMPX_F_I64_e32 = 2439,
2455 : V_CMPX_F_I64_e64 = 2440,
2456 : V_CMPX_F_I64_sdwa = 2441,
2457 : V_CMPX_F_U16_e32 = 2442,
2458 : V_CMPX_F_U16_e64 = 2443,
2459 : V_CMPX_F_U16_sdwa = 2444,
2460 : V_CMPX_F_U32_e32 = 2445,
2461 : V_CMPX_F_U32_e64 = 2446,
2462 : V_CMPX_F_U32_sdwa = 2447,
2463 : V_CMPX_F_U64_e32 = 2448,
2464 : V_CMPX_F_U64_e64 = 2449,
2465 : V_CMPX_F_U64_sdwa = 2450,
2466 : V_CMPX_GE_F16_e32 = 2451,
2467 : V_CMPX_GE_F16_e64 = 2452,
2468 : V_CMPX_GE_F16_sdwa = 2453,
2469 : V_CMPX_GE_F32_e32 = 2454,
2470 : V_CMPX_GE_F32_e64 = 2455,
2471 : V_CMPX_GE_F32_sdwa = 2456,
2472 : V_CMPX_GE_F64_e32 = 2457,
2473 : V_CMPX_GE_F64_e64 = 2458,
2474 : V_CMPX_GE_F64_sdwa = 2459,
2475 : V_CMPX_GE_I16_e32 = 2460,
2476 : V_CMPX_GE_I16_e64 = 2461,
2477 : V_CMPX_GE_I16_sdwa = 2462,
2478 : V_CMPX_GE_I32_e32 = 2463,
2479 : V_CMPX_GE_I32_e64 = 2464,
2480 : V_CMPX_GE_I32_sdwa = 2465,
2481 : V_CMPX_GE_I64_e32 = 2466,
2482 : V_CMPX_GE_I64_e64 = 2467,
2483 : V_CMPX_GE_I64_sdwa = 2468,
2484 : V_CMPX_GE_U16_e32 = 2469,
2485 : V_CMPX_GE_U16_e64 = 2470,
2486 : V_CMPX_GE_U16_sdwa = 2471,
2487 : V_CMPX_GE_U32_e32 = 2472,
2488 : V_CMPX_GE_U32_e64 = 2473,
2489 : V_CMPX_GE_U32_sdwa = 2474,
2490 : V_CMPX_GE_U64_e32 = 2475,
2491 : V_CMPX_GE_U64_e64 = 2476,
2492 : V_CMPX_GE_U64_sdwa = 2477,
2493 : V_CMPX_GT_F16_e32 = 2478,
2494 : V_CMPX_GT_F16_e64 = 2479,
2495 : V_CMPX_GT_F16_sdwa = 2480,
2496 : V_CMPX_GT_F32_e32 = 2481,
2497 : V_CMPX_GT_F32_e64 = 2482,
2498 : V_CMPX_GT_F32_sdwa = 2483,
2499 : V_CMPX_GT_F64_e32 = 2484,
2500 : V_CMPX_GT_F64_e64 = 2485,
2501 : V_CMPX_GT_F64_sdwa = 2486,
2502 : V_CMPX_GT_I16_e32 = 2487,
2503 : V_CMPX_GT_I16_e64 = 2488,
2504 : V_CMPX_GT_I16_sdwa = 2489,
2505 : V_CMPX_GT_I32_e32 = 2490,
2506 : V_CMPX_GT_I32_e64 = 2491,
2507 : V_CMPX_GT_I32_sdwa = 2492,
2508 : V_CMPX_GT_I64_e32 = 2493,
2509 : V_CMPX_GT_I64_e64 = 2494,
2510 : V_CMPX_GT_I64_sdwa = 2495,
2511 : V_CMPX_GT_U16_e32 = 2496,
2512 : V_CMPX_GT_U16_e64 = 2497,
2513 : V_CMPX_GT_U16_sdwa = 2498,
2514 : V_CMPX_GT_U32_e32 = 2499,
2515 : V_CMPX_GT_U32_e64 = 2500,
2516 : V_CMPX_GT_U32_sdwa = 2501,
2517 : V_CMPX_GT_U64_e32 = 2502,
2518 : V_CMPX_GT_U64_e64 = 2503,
2519 : V_CMPX_GT_U64_sdwa = 2504,
2520 : V_CMPX_LE_F16_e32 = 2505,
2521 : V_CMPX_LE_F16_e64 = 2506,
2522 : V_CMPX_LE_F16_sdwa = 2507,
2523 : V_CMPX_LE_F32_e32 = 2508,
2524 : V_CMPX_LE_F32_e64 = 2509,
2525 : V_CMPX_LE_F32_sdwa = 2510,
2526 : V_CMPX_LE_F64_e32 = 2511,
2527 : V_CMPX_LE_F64_e64 = 2512,
2528 : V_CMPX_LE_F64_sdwa = 2513,
2529 : V_CMPX_LE_I16_e32 = 2514,
2530 : V_CMPX_LE_I16_e64 = 2515,
2531 : V_CMPX_LE_I16_sdwa = 2516,
2532 : V_CMPX_LE_I32_e32 = 2517,
2533 : V_CMPX_LE_I32_e64 = 2518,
2534 : V_CMPX_LE_I32_sdwa = 2519,
2535 : V_CMPX_LE_I64_e32 = 2520,
2536 : V_CMPX_LE_I64_e64 = 2521,
2537 : V_CMPX_LE_I64_sdwa = 2522,
2538 : V_CMPX_LE_U16_e32 = 2523,
2539 : V_CMPX_LE_U16_e64 = 2524,
2540 : V_CMPX_LE_U16_sdwa = 2525,
2541 : V_CMPX_LE_U32_e32 = 2526,
2542 : V_CMPX_LE_U32_e64 = 2527,
2543 : V_CMPX_LE_U32_sdwa = 2528,
2544 : V_CMPX_LE_U64_e32 = 2529,
2545 : V_CMPX_LE_U64_e64 = 2530,
2546 : V_CMPX_LE_U64_sdwa = 2531,
2547 : V_CMPX_LG_F16_e32 = 2532,
2548 : V_CMPX_LG_F16_e64 = 2533,
2549 : V_CMPX_LG_F16_sdwa = 2534,
2550 : V_CMPX_LG_F32_e32 = 2535,
2551 : V_CMPX_LG_F32_e64 = 2536,
2552 : V_CMPX_LG_F32_sdwa = 2537,
2553 : V_CMPX_LG_F64_e32 = 2538,
2554 : V_CMPX_LG_F64_e64 = 2539,
2555 : V_CMPX_LG_F64_sdwa = 2540,
2556 : V_CMPX_LT_F16_e32 = 2541,
2557 : V_CMPX_LT_F16_e64 = 2542,
2558 : V_CMPX_LT_F16_sdwa = 2543,
2559 : V_CMPX_LT_F32_e32 = 2544,
2560 : V_CMPX_LT_F32_e64 = 2545,
2561 : V_CMPX_LT_F32_sdwa = 2546,
2562 : V_CMPX_LT_F64_e32 = 2547,
2563 : V_CMPX_LT_F64_e64 = 2548,
2564 : V_CMPX_LT_F64_sdwa = 2549,
2565 : V_CMPX_LT_I16_e32 = 2550,
2566 : V_CMPX_LT_I16_e64 = 2551,
2567 : V_CMPX_LT_I16_sdwa = 2552,
2568 : V_CMPX_LT_I32_e32 = 2553,
2569 : V_CMPX_LT_I32_e64 = 2554,
2570 : V_CMPX_LT_I32_sdwa = 2555,
2571 : V_CMPX_LT_I64_e32 = 2556,
2572 : V_CMPX_LT_I64_e64 = 2557,
2573 : V_CMPX_LT_I64_sdwa = 2558,
2574 : V_CMPX_LT_U16_e32 = 2559,
2575 : V_CMPX_LT_U16_e64 = 2560,
2576 : V_CMPX_LT_U16_sdwa = 2561,
2577 : V_CMPX_LT_U32_e32 = 2562,
2578 : V_CMPX_LT_U32_e64 = 2563,
2579 : V_CMPX_LT_U32_sdwa = 2564,
2580 : V_CMPX_LT_U64_e32 = 2565,
2581 : V_CMPX_LT_U64_e64 = 2566,
2582 : V_CMPX_LT_U64_sdwa = 2567,
2583 : V_CMPX_NEQ_F16_e32 = 2568,
2584 : V_CMPX_NEQ_F16_e64 = 2569,
2585 : V_CMPX_NEQ_F16_sdwa = 2570,
2586 : V_CMPX_NEQ_F32_e32 = 2571,
2587 : V_CMPX_NEQ_F32_e64 = 2572,
2588 : V_CMPX_NEQ_F32_sdwa = 2573,
2589 : V_CMPX_NEQ_F64_e32 = 2574,
2590 : V_CMPX_NEQ_F64_e64 = 2575,
2591 : V_CMPX_NEQ_F64_sdwa = 2576,
2592 : V_CMPX_NE_I16_e32 = 2577,
2593 : V_CMPX_NE_I16_e64 = 2578,
2594 : V_CMPX_NE_I16_sdwa = 2579,
2595 : V_CMPX_NE_I32_e32 = 2580,
2596 : V_CMPX_NE_I32_e64 = 2581,
2597 : V_CMPX_NE_I32_sdwa = 2582,
2598 : V_CMPX_NE_I64_e32 = 2583,
2599 : V_CMPX_NE_I64_e64 = 2584,
2600 : V_CMPX_NE_I64_sdwa = 2585,
2601 : V_CMPX_NE_U16_e32 = 2586,
2602 : V_CMPX_NE_U16_e64 = 2587,
2603 : V_CMPX_NE_U16_sdwa = 2588,
2604 : V_CMPX_NE_U32_e32 = 2589,
2605 : V_CMPX_NE_U32_e64 = 2590,
2606 : V_CMPX_NE_U32_sdwa = 2591,
2607 : V_CMPX_NE_U64_e32 = 2592,
2608 : V_CMPX_NE_U64_e64 = 2593,
2609 : V_CMPX_NE_U64_sdwa = 2594,
2610 : V_CMPX_NGE_F16_e32 = 2595,
2611 : V_CMPX_NGE_F16_e64 = 2596,
2612 : V_CMPX_NGE_F16_sdwa = 2597,
2613 : V_CMPX_NGE_F32_e32 = 2598,
2614 : V_CMPX_NGE_F32_e64 = 2599,
2615 : V_CMPX_NGE_F32_sdwa = 2600,
2616 : V_CMPX_NGE_F64_e32 = 2601,
2617 : V_CMPX_NGE_F64_e64 = 2602,
2618 : V_CMPX_NGE_F64_sdwa = 2603,
2619 : V_CMPX_NGT_F16_e32 = 2604,
2620 : V_CMPX_NGT_F16_e64 = 2605,
2621 : V_CMPX_NGT_F16_sdwa = 2606,
2622 : V_CMPX_NGT_F32_e32 = 2607,
2623 : V_CMPX_NGT_F32_e64 = 2608,
2624 : V_CMPX_NGT_F32_sdwa = 2609,
2625 : V_CMPX_NGT_F64_e32 = 2610,
2626 : V_CMPX_NGT_F64_e64 = 2611,
2627 : V_CMPX_NGT_F64_sdwa = 2612,
2628 : V_CMPX_NLE_F16_e32 = 2613,
2629 : V_CMPX_NLE_F16_e64 = 2614,
2630 : V_CMPX_NLE_F16_sdwa = 2615,
2631 : V_CMPX_NLE_F32_e32 = 2616,
2632 : V_CMPX_NLE_F32_e64 = 2617,
2633 : V_CMPX_NLE_F32_sdwa = 2618,
2634 : V_CMPX_NLE_F64_e32 = 2619,
2635 : V_CMPX_NLE_F64_e64 = 2620,
2636 : V_CMPX_NLE_F64_sdwa = 2621,
2637 : V_CMPX_NLG_F16_e32 = 2622,
2638 : V_CMPX_NLG_F16_e64 = 2623,
2639 : V_CMPX_NLG_F16_sdwa = 2624,
2640 : V_CMPX_NLG_F32_e32 = 2625,
2641 : V_CMPX_NLG_F32_e64 = 2626,
2642 : V_CMPX_NLG_F32_sdwa = 2627,
2643 : V_CMPX_NLG_F64_e32 = 2628,
2644 : V_CMPX_NLG_F64_e64 = 2629,
2645 : V_CMPX_NLG_F64_sdwa = 2630,
2646 : V_CMPX_NLT_F16_e32 = 2631,
2647 : V_CMPX_NLT_F16_e64 = 2632,
2648 : V_CMPX_NLT_F16_sdwa = 2633,
2649 : V_CMPX_NLT_F32_e32 = 2634,
2650 : V_CMPX_NLT_F32_e64 = 2635,
2651 : V_CMPX_NLT_F32_sdwa = 2636,
2652 : V_CMPX_NLT_F64_e32 = 2637,
2653 : V_CMPX_NLT_F64_e64 = 2638,
2654 : V_CMPX_NLT_F64_sdwa = 2639,
2655 : V_CMPX_O_F16_e32 = 2640,
2656 : V_CMPX_O_F16_e64 = 2641,
2657 : V_CMPX_O_F16_sdwa = 2642,
2658 : V_CMPX_O_F32_e32 = 2643,
2659 : V_CMPX_O_F32_e64 = 2644,
2660 : V_CMPX_O_F32_sdwa = 2645,
2661 : V_CMPX_O_F64_e32 = 2646,
2662 : V_CMPX_O_F64_e64 = 2647,
2663 : V_CMPX_O_F64_sdwa = 2648,
2664 : V_CMPX_TRU_F16_e32 = 2649,
2665 : V_CMPX_TRU_F16_e64 = 2650,
2666 : V_CMPX_TRU_F16_sdwa = 2651,
2667 : V_CMPX_TRU_F32_e32 = 2652,
2668 : V_CMPX_TRU_F32_e64 = 2653,
2669 : V_CMPX_TRU_F32_sdwa = 2654,
2670 : V_CMPX_TRU_F64_e32 = 2655,
2671 : V_CMPX_TRU_F64_e64 = 2656,
2672 : V_CMPX_TRU_F64_sdwa = 2657,
2673 : V_CMPX_T_I16_e32 = 2658,
2674 : V_CMPX_T_I16_e64 = 2659,
2675 : V_CMPX_T_I16_sdwa = 2660,
2676 : V_CMPX_T_I32_e32 = 2661,
2677 : V_CMPX_T_I32_e64 = 2662,
2678 : V_CMPX_T_I32_sdwa = 2663,
2679 : V_CMPX_T_I64_e32 = 2664,
2680 : V_CMPX_T_I64_e64 = 2665,
2681 : V_CMPX_T_I64_sdwa = 2666,
2682 : V_CMPX_T_U16_e32 = 2667,
2683 : V_CMPX_T_U16_e64 = 2668,
2684 : V_CMPX_T_U16_sdwa = 2669,
2685 : V_CMPX_T_U32_e32 = 2670,
2686 : V_CMPX_T_U32_e64 = 2671,
2687 : V_CMPX_T_U32_sdwa = 2672,
2688 : V_CMPX_T_U64_e32 = 2673,
2689 : V_CMPX_T_U64_e64 = 2674,
2690 : V_CMPX_T_U64_sdwa = 2675,
2691 : V_CMPX_U_F16_e32 = 2676,
2692 : V_CMPX_U_F16_e64 = 2677,
2693 : V_CMPX_U_F16_sdwa = 2678,
2694 : V_CMPX_U_F32_e32 = 2679,
2695 : V_CMPX_U_F32_e64 = 2680,
2696 : V_CMPX_U_F32_sdwa = 2681,
2697 : V_CMPX_U_F64_e32 = 2682,
2698 : V_CMPX_U_F64_e64 = 2683,
2699 : V_CMPX_U_F64_sdwa = 2684,
2700 : V_CMP_CLASS_F16_e32 = 2685,
2701 : V_CMP_CLASS_F16_e64 = 2686,
2702 : V_CMP_CLASS_F16_sdwa = 2687,
2703 : V_CMP_CLASS_F32_e32 = 2688,
2704 : V_CMP_CLASS_F32_e64 = 2689,
2705 : V_CMP_CLASS_F32_sdwa = 2690,
2706 : V_CMP_CLASS_F64_e32 = 2691,
2707 : V_CMP_CLASS_F64_e64 = 2692,
2708 : V_CMP_CLASS_F64_sdwa = 2693,
2709 : V_CMP_EQ_F16_e32 = 2694,
2710 : V_CMP_EQ_F16_e64 = 2695,
2711 : V_CMP_EQ_F16_sdwa = 2696,
2712 : V_CMP_EQ_F32_e32 = 2697,
2713 : V_CMP_EQ_F32_e64 = 2698,
2714 : V_CMP_EQ_F32_sdwa = 2699,
2715 : V_CMP_EQ_F64_e32 = 2700,
2716 : V_CMP_EQ_F64_e64 = 2701,
2717 : V_CMP_EQ_F64_sdwa = 2702,
2718 : V_CMP_EQ_I16_e32 = 2703,
2719 : V_CMP_EQ_I16_e64 = 2704,
2720 : V_CMP_EQ_I16_sdwa = 2705,
2721 : V_CMP_EQ_I32_e32 = 2706,
2722 : V_CMP_EQ_I32_e64 = 2707,
2723 : V_CMP_EQ_I32_sdwa = 2708,
2724 : V_CMP_EQ_I64_e32 = 2709,
2725 : V_CMP_EQ_I64_e64 = 2710,
2726 : V_CMP_EQ_I64_sdwa = 2711,
2727 : V_CMP_EQ_U16_e32 = 2712,
2728 : V_CMP_EQ_U16_e64 = 2713,
2729 : V_CMP_EQ_U16_sdwa = 2714,
2730 : V_CMP_EQ_U32_e32 = 2715,
2731 : V_CMP_EQ_U32_e64 = 2716,
2732 : V_CMP_EQ_U32_sdwa = 2717,
2733 : V_CMP_EQ_U64_e32 = 2718,
2734 : V_CMP_EQ_U64_e64 = 2719,
2735 : V_CMP_EQ_U64_sdwa = 2720,
2736 : V_CMP_F_F16_e32 = 2721,
2737 : V_CMP_F_F16_e64 = 2722,
2738 : V_CMP_F_F16_sdwa = 2723,
2739 : V_CMP_F_F32_e32 = 2724,
2740 : V_CMP_F_F32_e64 = 2725,
2741 : V_CMP_F_F32_sdwa = 2726,
2742 : V_CMP_F_F64_e32 = 2727,
2743 : V_CMP_F_F64_e64 = 2728,
2744 : V_CMP_F_F64_sdwa = 2729,
2745 : V_CMP_F_I16_e32 = 2730,
2746 : V_CMP_F_I16_e64 = 2731,
2747 : V_CMP_F_I16_sdwa = 2732,
2748 : V_CMP_F_I32_e32 = 2733,
2749 : V_CMP_F_I32_e64 = 2734,
2750 : V_CMP_F_I32_sdwa = 2735,
2751 : V_CMP_F_I64_e32 = 2736,
2752 : V_CMP_F_I64_e64 = 2737,
2753 : V_CMP_F_I64_sdwa = 2738,
2754 : V_CMP_F_U16_e32 = 2739,
2755 : V_CMP_F_U16_e64 = 2740,
2756 : V_CMP_F_U16_sdwa = 2741,
2757 : V_CMP_F_U32_e32 = 2742,
2758 : V_CMP_F_U32_e64 = 2743,
2759 : V_CMP_F_U32_sdwa = 2744,
2760 : V_CMP_F_U64_e32 = 2745,
2761 : V_CMP_F_U64_e64 = 2746,
2762 : V_CMP_F_U64_sdwa = 2747,
2763 : V_CMP_GE_F16_e32 = 2748,
2764 : V_CMP_GE_F16_e64 = 2749,
2765 : V_CMP_GE_F16_sdwa = 2750,
2766 : V_CMP_GE_F32_e32 = 2751,
2767 : V_CMP_GE_F32_e64 = 2752,
2768 : V_CMP_GE_F32_sdwa = 2753,
2769 : V_CMP_GE_F64_e32 = 2754,
2770 : V_CMP_GE_F64_e64 = 2755,
2771 : V_CMP_GE_F64_sdwa = 2756,
2772 : V_CMP_GE_I16_e32 = 2757,
2773 : V_CMP_GE_I16_e64 = 2758,
2774 : V_CMP_GE_I16_sdwa = 2759,
2775 : V_CMP_GE_I32_e32 = 2760,
2776 : V_CMP_GE_I32_e64 = 2761,
2777 : V_CMP_GE_I32_sdwa = 2762,
2778 : V_CMP_GE_I64_e32 = 2763,
2779 : V_CMP_GE_I64_e64 = 2764,
2780 : V_CMP_GE_I64_sdwa = 2765,
2781 : V_CMP_GE_U16_e32 = 2766,
2782 : V_CMP_GE_U16_e64 = 2767,
2783 : V_CMP_GE_U16_sdwa = 2768,
2784 : V_CMP_GE_U32_e32 = 2769,
2785 : V_CMP_GE_U32_e64 = 2770,
2786 : V_CMP_GE_U32_sdwa = 2771,
2787 : V_CMP_GE_U64_e32 = 2772,
2788 : V_CMP_GE_U64_e64 = 2773,
2789 : V_CMP_GE_U64_sdwa = 2774,
2790 : V_CMP_GT_F16_e32 = 2775,
2791 : V_CMP_GT_F16_e64 = 2776,
2792 : V_CMP_GT_F16_sdwa = 2777,
2793 : V_CMP_GT_F32_e32 = 2778,
2794 : V_CMP_GT_F32_e64 = 2779,
2795 : V_CMP_GT_F32_sdwa = 2780,
2796 : V_CMP_GT_F64_e32 = 2781,
2797 : V_CMP_GT_F64_e64 = 2782,
2798 : V_CMP_GT_F64_sdwa = 2783,
2799 : V_CMP_GT_I16_e32 = 2784,
2800 : V_CMP_GT_I16_e64 = 2785,
2801 : V_CMP_GT_I16_sdwa = 2786,
2802 : V_CMP_GT_I32_e32 = 2787,
2803 : V_CMP_GT_I32_e64 = 2788,
2804 : V_CMP_GT_I32_sdwa = 2789,
2805 : V_CMP_GT_I64_e32 = 2790,
2806 : V_CMP_GT_I64_e64 = 2791,
2807 : V_CMP_GT_I64_sdwa = 2792,
2808 : V_CMP_GT_U16_e32 = 2793,
2809 : V_CMP_GT_U16_e64 = 2794,
2810 : V_CMP_GT_U16_sdwa = 2795,
2811 : V_CMP_GT_U32_e32 = 2796,
2812 : V_CMP_GT_U32_e64 = 2797,
2813 : V_CMP_GT_U32_sdwa = 2798,
2814 : V_CMP_GT_U64_e32 = 2799,
2815 : V_CMP_GT_U64_e64 = 2800,
2816 : V_CMP_GT_U64_sdwa = 2801,
2817 : V_CMP_LE_F16_e32 = 2802,
2818 : V_CMP_LE_F16_e64 = 2803,
2819 : V_CMP_LE_F16_sdwa = 2804,
2820 : V_CMP_LE_F32_e32 = 2805,
2821 : V_CMP_LE_F32_e64 = 2806,
2822 : V_CMP_LE_F32_sdwa = 2807,
2823 : V_CMP_LE_F64_e32 = 2808,
2824 : V_CMP_LE_F64_e64 = 2809,
2825 : V_CMP_LE_F64_sdwa = 2810,
2826 : V_CMP_LE_I16_e32 = 2811,
2827 : V_CMP_LE_I16_e64 = 2812,
2828 : V_CMP_LE_I16_sdwa = 2813,
2829 : V_CMP_LE_I32_e32 = 2814,
2830 : V_CMP_LE_I32_e64 = 2815,
2831 : V_CMP_LE_I32_sdwa = 2816,
2832 : V_CMP_LE_I64_e32 = 2817,
2833 : V_CMP_LE_I64_e64 = 2818,
2834 : V_CMP_LE_I64_sdwa = 2819,
2835 : V_CMP_LE_U16_e32 = 2820,
2836 : V_CMP_LE_U16_e64 = 2821,
2837 : V_CMP_LE_U16_sdwa = 2822,
2838 : V_CMP_LE_U32_e32 = 2823,
2839 : V_CMP_LE_U32_e64 = 2824,
2840 : V_CMP_LE_U32_sdwa = 2825,
2841 : V_CMP_LE_U64_e32 = 2826,
2842 : V_CMP_LE_U64_e64 = 2827,
2843 : V_CMP_LE_U64_sdwa = 2828,
2844 : V_CMP_LG_F16_e32 = 2829,
2845 : V_CMP_LG_F16_e64 = 2830,
2846 : V_CMP_LG_F16_sdwa = 2831,
2847 : V_CMP_LG_F32_e32 = 2832,
2848 : V_CMP_LG_F32_e64 = 2833,
2849 : V_CMP_LG_F32_sdwa = 2834,
2850 : V_CMP_LG_F64_e32 = 2835,
2851 : V_CMP_LG_F64_e64 = 2836,
2852 : V_CMP_LG_F64_sdwa = 2837,
2853 : V_CMP_LT_F16_e32 = 2838,
2854 : V_CMP_LT_F16_e64 = 2839,
2855 : V_CMP_LT_F16_sdwa = 2840,
2856 : V_CMP_LT_F32_e32 = 2841,
2857 : V_CMP_LT_F32_e64 = 2842,
2858 : V_CMP_LT_F32_sdwa = 2843,
2859 : V_CMP_LT_F64_e32 = 2844,
2860 : V_CMP_LT_F64_e64 = 2845,
2861 : V_CMP_LT_F64_sdwa = 2846,
2862 : V_CMP_LT_I16_e32 = 2847,
2863 : V_CMP_LT_I16_e64 = 2848,
2864 : V_CMP_LT_I16_sdwa = 2849,
2865 : V_CMP_LT_I32_e32 = 2850,
2866 : V_CMP_LT_I32_e64 = 2851,
2867 : V_CMP_LT_I32_sdwa = 2852,
2868 : V_CMP_LT_I64_e32 = 2853,
2869 : V_CMP_LT_I64_e64 = 2854,
2870 : V_CMP_LT_I64_sdwa = 2855,
2871 : V_CMP_LT_U16_e32 = 2856,
2872 : V_CMP_LT_U16_e64 = 2857,
2873 : V_CMP_LT_U16_sdwa = 2858,
2874 : V_CMP_LT_U32_e32 = 2859,
2875 : V_CMP_LT_U32_e64 = 2860,
2876 : V_CMP_LT_U32_sdwa = 2861,
2877 : V_CMP_LT_U64_e32 = 2862,
2878 : V_CMP_LT_U64_e64 = 2863,
2879 : V_CMP_LT_U64_sdwa = 2864,
2880 : V_CMP_NEQ_F16_e32 = 2865,
2881 : V_CMP_NEQ_F16_e64 = 2866,
2882 : V_CMP_NEQ_F16_sdwa = 2867,
2883 : V_CMP_NEQ_F32_e32 = 2868,
2884 : V_CMP_NEQ_F32_e64 = 2869,
2885 : V_CMP_NEQ_F32_sdwa = 2870,
2886 : V_CMP_NEQ_F64_e32 = 2871,
2887 : V_CMP_NEQ_F64_e64 = 2872,
2888 : V_CMP_NEQ_F64_sdwa = 2873,
2889 : V_CMP_NE_I16_e32 = 2874,
2890 : V_CMP_NE_I16_e64 = 2875,
2891 : V_CMP_NE_I16_sdwa = 2876,
2892 : V_CMP_NE_I32_e32 = 2877,
2893 : V_CMP_NE_I32_e64 = 2878,
2894 : V_CMP_NE_I32_sdwa = 2879,
2895 : V_CMP_NE_I64_e32 = 2880,
2896 : V_CMP_NE_I64_e64 = 2881,
2897 : V_CMP_NE_I64_sdwa = 2882,
2898 : V_CMP_NE_U16_e32 = 2883,
2899 : V_CMP_NE_U16_e64 = 2884,
2900 : V_CMP_NE_U16_sdwa = 2885,
2901 : V_CMP_NE_U32_e32 = 2886,
2902 : V_CMP_NE_U32_e64 = 2887,
2903 : V_CMP_NE_U32_sdwa = 2888,
2904 : V_CMP_NE_U64_e32 = 2889,
2905 : V_CMP_NE_U64_e64 = 2890,
2906 : V_CMP_NE_U64_sdwa = 2891,
2907 : V_CMP_NGE_F16_e32 = 2892,
2908 : V_CMP_NGE_F16_e64 = 2893,
2909 : V_CMP_NGE_F16_sdwa = 2894,
2910 : V_CMP_NGE_F32_e32 = 2895,
2911 : V_CMP_NGE_F32_e64 = 2896,
2912 : V_CMP_NGE_F32_sdwa = 2897,
2913 : V_CMP_NGE_F64_e32 = 2898,
2914 : V_CMP_NGE_F64_e64 = 2899,
2915 : V_CMP_NGE_F64_sdwa = 2900,
2916 : V_CMP_NGT_F16_e32 = 2901,
2917 : V_CMP_NGT_F16_e64 = 2902,
2918 : V_CMP_NGT_F16_sdwa = 2903,
2919 : V_CMP_NGT_F32_e32 = 2904,
2920 : V_CMP_NGT_F32_e64 = 2905,
2921 : V_CMP_NGT_F32_sdwa = 2906,
2922 : V_CMP_NGT_F64_e32 = 2907,
2923 : V_CMP_NGT_F64_e64 = 2908,
2924 : V_CMP_NGT_F64_sdwa = 2909,
2925 : V_CMP_NLE_F16_e32 = 2910,
2926 : V_CMP_NLE_F16_e64 = 2911,
2927 : V_CMP_NLE_F16_sdwa = 2912,
2928 : V_CMP_NLE_F32_e32 = 2913,
2929 : V_CMP_NLE_F32_e64 = 2914,
2930 : V_CMP_NLE_F32_sdwa = 2915,
2931 : V_CMP_NLE_F64_e32 = 2916,
2932 : V_CMP_NLE_F64_e64 = 2917,
2933 : V_CMP_NLE_F64_sdwa = 2918,
2934 : V_CMP_NLG_F16_e32 = 2919,
2935 : V_CMP_NLG_F16_e64 = 2920,
2936 : V_CMP_NLG_F16_sdwa = 2921,
2937 : V_CMP_NLG_F32_e32 = 2922,
2938 : V_CMP_NLG_F32_e64 = 2923,
2939 : V_CMP_NLG_F32_sdwa = 2924,
2940 : V_CMP_NLG_F64_e32 = 2925,
2941 : V_CMP_NLG_F64_e64 = 2926,
2942 : V_CMP_NLG_F64_sdwa = 2927,
2943 : V_CMP_NLT_F16_e32 = 2928,
2944 : V_CMP_NLT_F16_e64 = 2929,
2945 : V_CMP_NLT_F16_sdwa = 2930,
2946 : V_CMP_NLT_F32_e32 = 2931,
2947 : V_CMP_NLT_F32_e64 = 2932,
2948 : V_CMP_NLT_F32_sdwa = 2933,
2949 : V_CMP_NLT_F64_e32 = 2934,
2950 : V_CMP_NLT_F64_e64 = 2935,
2951 : V_CMP_NLT_F64_sdwa = 2936,
2952 : V_CMP_O_F16_e32 = 2937,
2953 : V_CMP_O_F16_e64 = 2938,
2954 : V_CMP_O_F16_sdwa = 2939,
2955 : V_CMP_O_F32_e32 = 2940,
2956 : V_CMP_O_F32_e64 = 2941,
2957 : V_CMP_O_F32_sdwa = 2942,
2958 : V_CMP_O_F64_e32 = 2943,
2959 : V_CMP_O_F64_e64 = 2944,
2960 : V_CMP_O_F64_sdwa = 2945,
2961 : V_CMP_TRU_F16_e32 = 2946,
2962 : V_CMP_TRU_F16_e64 = 2947,
2963 : V_CMP_TRU_F16_sdwa = 2948,
2964 : V_CMP_TRU_F32_e32 = 2949,
2965 : V_CMP_TRU_F32_e64 = 2950,
2966 : V_CMP_TRU_F32_sdwa = 2951,
2967 : V_CMP_TRU_F64_e32 = 2952,
2968 : V_CMP_TRU_F64_e64 = 2953,
2969 : V_CMP_TRU_F64_sdwa = 2954,
2970 : V_CMP_T_I16_e32 = 2955,
2971 : V_CMP_T_I16_e64 = 2956,
2972 : V_CMP_T_I16_sdwa = 2957,
2973 : V_CMP_T_I32_e32 = 2958,
2974 : V_CMP_T_I32_e64 = 2959,
2975 : V_CMP_T_I32_sdwa = 2960,
2976 : V_CMP_T_I64_e32 = 2961,
2977 : V_CMP_T_I64_e64 = 2962,
2978 : V_CMP_T_I64_sdwa = 2963,
2979 : V_CMP_T_U16_e32 = 2964,
2980 : V_CMP_T_U16_e64 = 2965,
2981 : V_CMP_T_U16_sdwa = 2966,
2982 : V_CMP_T_U32_e32 = 2967,
2983 : V_CMP_T_U32_e64 = 2968,
2984 : V_CMP_T_U32_sdwa = 2969,
2985 : V_CMP_T_U64_e32 = 2970,
2986 : V_CMP_T_U64_e64 = 2971,
2987 : V_CMP_T_U64_sdwa = 2972,
2988 : V_CMP_U_F16_e32 = 2973,
2989 : V_CMP_U_F16_e64 = 2974,
2990 : V_CMP_U_F16_sdwa = 2975,
2991 : V_CMP_U_F32_e32 = 2976,
2992 : V_CMP_U_F32_e64 = 2977,
2993 : V_CMP_U_F32_sdwa = 2978,
2994 : V_CMP_U_F64_e32 = 2979,
2995 : V_CMP_U_F64_e64 = 2980,
2996 : V_CMP_U_F64_sdwa = 2981,
2997 : V_CNDMASK_B32_e32 = 2982,
2998 : V_CNDMASK_B32_e64 = 2983,
2999 : V_CNDMASK_B32_sdwa = 2984,
3000 : V_CNDMASK_B64_PSEUDO = 2985,
3001 : V_COS_F16_e32 = 2986,
3002 : V_COS_F16_e64 = 2987,
3003 : V_COS_F16_sdwa = 2988,
3004 : V_COS_F32_e32 = 2989,
3005 : V_COS_F32_e64 = 2990,
3006 : V_COS_F32_sdwa = 2991,
3007 : V_CUBEID_F32 = 2992,
3008 : V_CUBEMA_F32 = 2993,
3009 : V_CUBESC_F32 = 2994,
3010 : V_CUBETC_F32 = 2995,
3011 : V_CVT_F16_F32_e32 = 2996,
3012 : V_CVT_F16_F32_e64 = 2997,
3013 : V_CVT_F16_F32_sdwa = 2998,
3014 : V_CVT_F16_I16_e32 = 2999,
3015 : V_CVT_F16_I16_e64 = 3000,
3016 : V_CVT_F16_I16_sdwa = 3001,
3017 : V_CVT_F16_U16_e32 = 3002,
3018 : V_CVT_F16_U16_e64 = 3003,
3019 : V_CVT_F16_U16_sdwa = 3004,
3020 : V_CVT_F32_F16_e32 = 3005,
3021 : V_CVT_F32_F16_e64 = 3006,
3022 : V_CVT_F32_F16_sdwa = 3007,
3023 : V_CVT_F32_F64_e32 = 3008,
3024 : V_CVT_F32_F64_e64 = 3009,
3025 : V_CVT_F32_F64_sdwa = 3010,
3026 : V_CVT_F32_I32_e32 = 3011,
3027 : V_CVT_F32_I32_e64 = 3012,
3028 : V_CVT_F32_I32_sdwa = 3013,
3029 : V_CVT_F32_U32_e32 = 3014,
3030 : V_CVT_F32_U32_e64 = 3015,
3031 : V_CVT_F32_U32_sdwa = 3016,
3032 : V_CVT_F32_UBYTE0_e32 = 3017,
3033 : V_CVT_F32_UBYTE0_e64 = 3018,
3034 : V_CVT_F32_UBYTE0_sdwa = 3019,
3035 : V_CVT_F32_UBYTE1_e32 = 3020,
3036 : V_CVT_F32_UBYTE1_e64 = 3021,
3037 : V_CVT_F32_UBYTE1_sdwa = 3022,
3038 : V_CVT_F32_UBYTE2_e32 = 3023,
3039 : V_CVT_F32_UBYTE2_e64 = 3024,
3040 : V_CVT_F32_UBYTE2_sdwa = 3025,
3041 : V_CVT_F32_UBYTE3_e32 = 3026,
3042 : V_CVT_F32_UBYTE3_e64 = 3027,
3043 : V_CVT_F32_UBYTE3_sdwa = 3028,
3044 : V_CVT_F64_F32_e32 = 3029,
3045 : V_CVT_F64_F32_e64 = 3030,
3046 : V_CVT_F64_F32_sdwa = 3031,
3047 : V_CVT_F64_I32_e32 = 3032,
3048 : V_CVT_F64_I32_e64 = 3033,
3049 : V_CVT_F64_I32_sdwa = 3034,
3050 : V_CVT_F64_U32_e32 = 3035,
3051 : V_CVT_F64_U32_e64 = 3036,
3052 : V_CVT_F64_U32_sdwa = 3037,
3053 : V_CVT_FLR_I32_F32_e32 = 3038,
3054 : V_CVT_FLR_I32_F32_e64 = 3039,
3055 : V_CVT_FLR_I32_F32_sdwa = 3040,
3056 : V_CVT_I16_F16_e32 = 3041,
3057 : V_CVT_I16_F16_e64 = 3042,
3058 : V_CVT_I16_F16_sdwa = 3043,
3059 : V_CVT_I32_F32_e32 = 3044,
3060 : V_CVT_I32_F32_e64 = 3045,
3061 : V_CVT_I32_F32_sdwa = 3046,
3062 : V_CVT_I32_F64_e32 = 3047,
3063 : V_CVT_I32_F64_e64 = 3048,
3064 : V_CVT_I32_F64_sdwa = 3049,
3065 : V_CVT_NORM_I16_F16_e32 = 3050,
3066 : V_CVT_NORM_I16_F16_e64 = 3051,
3067 : V_CVT_NORM_I16_F16_sdwa = 3052,
3068 : V_CVT_NORM_U16_F16_e32 = 3053,
3069 : V_CVT_NORM_U16_F16_e64 = 3054,
3070 : V_CVT_NORM_U16_F16_sdwa = 3055,
3071 : V_CVT_OFF_F32_I4_e32 = 3056,
3072 : V_CVT_OFF_F32_I4_e64 = 3057,
3073 : V_CVT_OFF_F32_I4_sdwa = 3058,
3074 : V_CVT_PKACCUM_U8_F32_e32 = 3059,
3075 : V_CVT_PKACCUM_U8_F32_e64 = 3060,
3076 : V_CVT_PKACCUM_U8_F32_sdwa = 3061,
3077 : V_CVT_PKNORM_I16_F16 = 3062,
3078 : V_CVT_PKNORM_I16_F32_e32 = 3063,
3079 : V_CVT_PKNORM_I16_F32_e64 = 3064,
3080 : V_CVT_PKNORM_I16_F32_sdwa = 3065,
3081 : V_CVT_PKNORM_U16_F16 = 3066,
3082 : V_CVT_PKNORM_U16_F32_e32 = 3067,
3083 : V_CVT_PKNORM_U16_F32_e64 = 3068,
3084 : V_CVT_PKNORM_U16_F32_sdwa = 3069,
3085 : V_CVT_PKRTZ_F16_F32_e32 = 3070,
3086 : V_CVT_PKRTZ_F16_F32_e64 = 3071,
3087 : V_CVT_PKRTZ_F16_F32_sdwa = 3072,
3088 : V_CVT_PK_I16_I32_e32 = 3073,
3089 : V_CVT_PK_I16_I32_e64 = 3074,
3090 : V_CVT_PK_I16_I32_sdwa = 3075,
3091 : V_CVT_PK_U16_U32_e32 = 3076,
3092 : V_CVT_PK_U16_U32_e64 = 3077,
3093 : V_CVT_PK_U16_U32_sdwa = 3078,
3094 : V_CVT_PK_U8_F32 = 3079,
3095 : V_CVT_RPI_I32_F32_e32 = 3080,
3096 : V_CVT_RPI_I32_F32_e64 = 3081,
3097 : V_CVT_RPI_I32_F32_sdwa = 3082,
3098 : V_CVT_U16_F16_e32 = 3083,
3099 : V_CVT_U16_F16_e64 = 3084,
3100 : V_CVT_U16_F16_sdwa = 3085,
3101 : V_CVT_U32_F32_e32 = 3086,
3102 : V_CVT_U32_F32_e64 = 3087,
3103 : V_CVT_U32_F32_sdwa = 3088,
3104 : V_CVT_U32_F64_e32 = 3089,
3105 : V_CVT_U32_F64_e64 = 3090,
3106 : V_CVT_U32_F64_sdwa = 3091,
3107 : V_DIV_FIXUP_F16 = 3092,
3108 : V_DIV_FIXUP_F16_gfx9 = 3093,
3109 : V_DIV_FIXUP_F32 = 3094,
3110 : V_DIV_FIXUP_F64 = 3095,
3111 : V_DIV_FMAS_F32 = 3096,
3112 : V_DIV_FMAS_F64 = 3097,
3113 : V_DIV_SCALE_F32 = 3098,
3114 : V_DIV_SCALE_F64 = 3099,
3115 : V_DOT2_F32_F16 = 3100,
3116 : V_DOT2_I32_I16 = 3101,
3117 : V_DOT2_U32_U16 = 3102,
3118 : V_DOT4_I32_I8 = 3103,
3119 : V_DOT4_U32_U8 = 3104,
3120 : V_DOT8_I32_I4 = 3105,
3121 : V_DOT8_U32_U4 = 3106,
3122 : V_EXP_F16_e32 = 3107,
3123 : V_EXP_F16_e64 = 3108,
3124 : V_EXP_F16_sdwa = 3109,
3125 : V_EXP_F32_e32 = 3110,
3126 : V_EXP_F32_e64 = 3111,
3127 : V_EXP_F32_sdwa = 3112,
3128 : V_EXP_LEGACY_F32_e32 = 3113,
3129 : V_EXP_LEGACY_F32_e64 = 3114,
3130 : V_EXP_LEGACY_F32_sdwa = 3115,
3131 : V_FFBH_I32_e32 = 3116,
3132 : V_FFBH_I32_e64 = 3117,
3133 : V_FFBH_I32_sdwa = 3118,
3134 : V_FFBH_U32_e32 = 3119,
3135 : V_FFBH_U32_e64 = 3120,
3136 : V_FFBH_U32_sdwa = 3121,
3137 : V_FFBL_B32_e32 = 3122,
3138 : V_FFBL_B32_e64 = 3123,
3139 : V_FFBL_B32_sdwa = 3124,
3140 : V_FLOOR_F16_e32 = 3125,
3141 : V_FLOOR_F16_e64 = 3126,
3142 : V_FLOOR_F16_sdwa = 3127,
3143 : V_FLOOR_F32_e32 = 3128,
3144 : V_FLOOR_F32_e64 = 3129,
3145 : V_FLOOR_F32_sdwa = 3130,
3146 : V_FLOOR_F64_e32 = 3131,
3147 : V_FLOOR_F64_e64 = 3132,
3148 : V_FLOOR_F64_sdwa = 3133,
3149 : V_FMAC_F32_e32 = 3134,
3150 : V_FMAC_F32_e64 = 3135,
3151 : V_FMAC_F32_sdwa = 3136,
3152 : V_FMA_F16 = 3137,
3153 : V_FMA_F16_gfx9 = 3138,
3154 : V_FMA_F32 = 3139,
3155 : V_FMA_F64 = 3140,
3156 : V_FMA_MIXHI_F16 = 3141,
3157 : V_FMA_MIXLO_F16 = 3142,
3158 : V_FMA_MIX_F32 = 3143,
3159 : V_FRACT_F16_e32 = 3144,
3160 : V_FRACT_F16_e64 = 3145,
3161 : V_FRACT_F16_sdwa = 3146,
3162 : V_FRACT_F32_e32 = 3147,
3163 : V_FRACT_F32_e64 = 3148,
3164 : V_FRACT_F32_sdwa = 3149,
3165 : V_FRACT_F64_e32 = 3150,
3166 : V_FRACT_F64_e64 = 3151,
3167 : V_FRACT_F64_sdwa = 3152,
3168 : V_FREXP_EXP_I16_F16_e32 = 3153,
3169 : V_FREXP_EXP_I16_F16_e64 = 3154,
3170 : V_FREXP_EXP_I16_F16_sdwa = 3155,
3171 : V_FREXP_EXP_I32_F32_e32 = 3156,
3172 : V_FREXP_EXP_I32_F32_e64 = 3157,
3173 : V_FREXP_EXP_I32_F32_sdwa = 3158,
3174 : V_FREXP_EXP_I32_F64_e32 = 3159,
3175 : V_FREXP_EXP_I32_F64_e64 = 3160,
3176 : V_FREXP_EXP_I32_F64_sdwa = 3161,
3177 : V_FREXP_MANT_F16_e32 = 3162,
3178 : V_FREXP_MANT_F16_e64 = 3163,
3179 : V_FREXP_MANT_F16_sdwa = 3164,
3180 : V_FREXP_MANT_F32_e32 = 3165,
3181 : V_FREXP_MANT_F32_e64 = 3166,
3182 : V_FREXP_MANT_F32_sdwa = 3167,
3183 : V_FREXP_MANT_F64_e32 = 3168,
3184 : V_FREXP_MANT_F64_e64 = 3169,
3185 : V_FREXP_MANT_F64_sdwa = 3170,
3186 : V_INTERP_MOV_F32 = 3171,
3187 : V_INTERP_MOV_F32_e64 = 3172,
3188 : V_INTERP_P1LL_F16 = 3173,
3189 : V_INTERP_P1LV_F16 = 3174,
3190 : V_INTERP_P1_F32 = 3175,
3191 : V_INTERP_P1_F32_16bank = 3176,
3192 : V_INTERP_P1_F32_e64 = 3177,
3193 : V_INTERP_P2_F16 = 3178,
3194 : V_INTERP_P2_F16_gfx9 = 3179,
3195 : V_INTERP_P2_F32 = 3180,
3196 : V_INTERP_P2_F32_e64 = 3181,
3197 : V_LDEXP_F16_e32 = 3182,
3198 : V_LDEXP_F16_e64 = 3183,
3199 : V_LDEXP_F16_sdwa = 3184,
3200 : V_LDEXP_F32_e32 = 3185,
3201 : V_LDEXP_F32_e64 = 3186,
3202 : V_LDEXP_F32_sdwa = 3187,
3203 : V_LDEXP_F64 = 3188,
3204 : V_LERP_U8 = 3189,
3205 : V_LOG_CLAMP_F32_e32 = 3190,
3206 : V_LOG_CLAMP_F32_e64 = 3191,
3207 : V_LOG_CLAMP_F32_sdwa = 3192,
3208 : V_LOG_F16_e32 = 3193,
3209 : V_LOG_F16_e64 = 3194,
3210 : V_LOG_F16_sdwa = 3195,
3211 : V_LOG_F32_e32 = 3196,
3212 : V_LOG_F32_e64 = 3197,
3213 : V_LOG_F32_sdwa = 3198,
3214 : V_LOG_LEGACY_F32_e32 = 3199,
3215 : V_LOG_LEGACY_F32_e64 = 3200,
3216 : V_LOG_LEGACY_F32_sdwa = 3201,
3217 : V_LSHLREV_B16_e32 = 3202,
3218 : V_LSHLREV_B16_e64 = 3203,
3219 : V_LSHLREV_B16_sdwa = 3204,
3220 : V_LSHLREV_B32_e32 = 3205,
3221 : V_LSHLREV_B32_e64 = 3206,
3222 : V_LSHLREV_B32_sdwa = 3207,
3223 : V_LSHLREV_B64 = 3208,
3224 : V_LSHL_ADD_U32 = 3209,
3225 : V_LSHL_B32_e32 = 3210,
3226 : V_LSHL_B32_e64 = 3211,
3227 : V_LSHL_B32_sdwa = 3212,
3228 : V_LSHL_B64 = 3213,
3229 : V_LSHL_OR_B32 = 3214,
3230 : V_LSHRREV_B16_e32 = 3215,
3231 : V_LSHRREV_B16_e64 = 3216,
3232 : V_LSHRREV_B16_sdwa = 3217,
3233 : V_LSHRREV_B32_e32 = 3218,
3234 : V_LSHRREV_B32_e64 = 3219,
3235 : V_LSHRREV_B32_sdwa = 3220,
3236 : V_LSHRREV_B64 = 3221,
3237 : V_LSHR_B32_e32 = 3222,
3238 : V_LSHR_B32_e64 = 3223,
3239 : V_LSHR_B32_sdwa = 3224,
3240 : V_LSHR_B64 = 3225,
3241 : V_MAC_F16_e32 = 3226,
3242 : V_MAC_F16_e64 = 3227,
3243 : V_MAC_F16_sdwa = 3228,
3244 : V_MAC_F32_e32 = 3229,
3245 : V_MAC_F32_e64 = 3230,
3246 : V_MAC_F32_sdwa = 3231,
3247 : V_MAC_LEGACY_F32_e32 = 3232,
3248 : V_MAC_LEGACY_F32_e64 = 3233,
3249 : V_MAC_LEGACY_F32_sdwa = 3234,
3250 : V_MADAK_F16 = 3235,
3251 : V_MADAK_F32 = 3236,
3252 : V_MADMK_F16 = 3237,
3253 : V_MADMK_F32 = 3238,
3254 : V_MAD_F16 = 3239,
3255 : V_MAD_F16_gfx9 = 3240,
3256 : V_MAD_F32 = 3241,
3257 : V_MAD_I16 = 3242,
3258 : V_MAD_I16_gfx9 = 3243,
3259 : V_MAD_I32_I16 = 3244,
3260 : V_MAD_I32_I24 = 3245,
3261 : V_MAD_I64_I32 = 3246,
3262 : V_MAD_LEGACY_F32 = 3247,
3263 : V_MAD_MIXHI_F16 = 3248,
3264 : V_MAD_MIXLO_F16 = 3249,
3265 : V_MAD_MIX_F32 = 3250,
3266 : V_MAD_U16 = 3251,
3267 : V_MAD_U16_gfx9 = 3252,
3268 : V_MAD_U32_U16 = 3253,
3269 : V_MAD_U32_U24 = 3254,
3270 : V_MAD_U64_U32 = 3255,
3271 : V_MAX3_F16 = 3256,
3272 : V_MAX3_F32 = 3257,
3273 : V_MAX3_I16 = 3258,
3274 : V_MAX3_I32 = 3259,
3275 : V_MAX3_U16 = 3260,
3276 : V_MAX3_U32 = 3261,
3277 : V_MAX_F16_e32 = 3262,
3278 : V_MAX_F16_e64 = 3263,
3279 : V_MAX_F16_sdwa = 3264,
3280 : V_MAX_F32_e32 = 3265,
3281 : V_MAX_F32_e64 = 3266,
3282 : V_MAX_F32_sdwa = 3267,
3283 : V_MAX_F64 = 3268,
3284 : V_MAX_I16_e32 = 3269,
3285 : V_MAX_I16_e64 = 3270,
3286 : V_MAX_I16_sdwa = 3271,
3287 : V_MAX_I32_e32 = 3272,
3288 : V_MAX_I32_e64 = 3273,
3289 : V_MAX_I32_sdwa = 3274,
3290 : V_MAX_LEGACY_F32_e32 = 3275,
3291 : V_MAX_LEGACY_F32_e64 = 3276,
3292 : V_MAX_LEGACY_F32_sdwa = 3277,
3293 : V_MAX_U16_e32 = 3278,
3294 : V_MAX_U16_e64 = 3279,
3295 : V_MAX_U16_sdwa = 3280,
3296 : V_MAX_U32_e32 = 3281,
3297 : V_MAX_U32_e64 = 3282,
3298 : V_MAX_U32_sdwa = 3283,
3299 : V_MBCNT_HI_U32_B32_e32 = 3284,
3300 : V_MBCNT_HI_U32_B32_e64 = 3285,
3301 : V_MBCNT_HI_U32_B32_sdwa = 3286,
3302 : V_MBCNT_LO_U32_B32_e32 = 3287,
3303 : V_MBCNT_LO_U32_B32_e64 = 3288,
3304 : V_MBCNT_LO_U32_B32_sdwa = 3289,
3305 : V_MED3_F16 = 3290,
3306 : V_MED3_F32 = 3291,
3307 : V_MED3_I16 = 3292,
3308 : V_MED3_I32 = 3293,
3309 : V_MED3_U16 = 3294,
3310 : V_MED3_U32 = 3295,
3311 : V_MIN3_F16 = 3296,
3312 : V_MIN3_F32 = 3297,
3313 : V_MIN3_I16 = 3298,
3314 : V_MIN3_I32 = 3299,
3315 : V_MIN3_U16 = 3300,
3316 : V_MIN3_U32 = 3301,
3317 : V_MIN_F16_e32 = 3302,
3318 : V_MIN_F16_e64 = 3303,
3319 : V_MIN_F16_sdwa = 3304,
3320 : V_MIN_F32_e32 = 3305,
3321 : V_MIN_F32_e64 = 3306,
3322 : V_MIN_F32_sdwa = 3307,
3323 : V_MIN_F64 = 3308,
3324 : V_MIN_I16_e32 = 3309,
3325 : V_MIN_I16_e64 = 3310,
3326 : V_MIN_I16_sdwa = 3311,
3327 : V_MIN_I32_e32 = 3312,
3328 : V_MIN_I32_e64 = 3313,
3329 : V_MIN_I32_sdwa = 3314,
3330 : V_MIN_LEGACY_F32_e32 = 3315,
3331 : V_MIN_LEGACY_F32_e64 = 3316,
3332 : V_MIN_LEGACY_F32_sdwa = 3317,
3333 : V_MIN_U16_e32 = 3318,
3334 : V_MIN_U16_e64 = 3319,
3335 : V_MIN_U16_sdwa = 3320,
3336 : V_MIN_U32_e32 = 3321,
3337 : V_MIN_U32_e64 = 3322,
3338 : V_MIN_U32_sdwa = 3323,
3339 : V_MOVRELD_B32_V1 = 3324,
3340 : V_MOVRELD_B32_V16 = 3325,
3341 : V_MOVRELD_B32_V2 = 3326,
3342 : V_MOVRELD_B32_V4 = 3327,
3343 : V_MOVRELD_B32_V8 = 3328,
3344 : V_MOVRELD_B32_e32 = 3329,
3345 : V_MOVRELD_B32_e64 = 3330,
3346 : V_MOVRELD_B32_sdwa = 3331,
3347 : V_MOVRELSD_B32_e32 = 3332,
3348 : V_MOVRELSD_B32_e64 = 3333,
3349 : V_MOVRELSD_B32_sdwa = 3334,
3350 : V_MOVRELS_B32_e32 = 3335,
3351 : V_MOVRELS_B32_e64 = 3336,
3352 : V_MOVRELS_B32_sdwa = 3337,
3353 : V_MOV_B32_e32 = 3338,
3354 : V_MOV_B32_e64 = 3339,
3355 : V_MOV_B32_indirect = 3340,
3356 : V_MOV_B32_sdwa = 3341,
3357 : V_MOV_B64_PSEUDO = 3342,
3358 : V_MOV_FED_B32_e32 = 3343,
3359 : V_MOV_FED_B32_e64 = 3344,
3360 : V_MOV_FED_B32_sdwa = 3345,
3361 : V_MQSAD_PK_U16_U8 = 3346,
3362 : V_MQSAD_U32_U8 = 3347,
3363 : V_MSAD_U8 = 3348,
3364 : V_MULLIT_F32 = 3349,
3365 : V_MUL_F16_e32 = 3350,
3366 : V_MUL_F16_e64 = 3351,
3367 : V_MUL_F16_sdwa = 3352,
3368 : V_MUL_F32_e32 = 3353,
3369 : V_MUL_F32_e64 = 3354,
3370 : V_MUL_F32_sdwa = 3355,
3371 : V_MUL_F64 = 3356,
3372 : V_MUL_HI_I32 = 3357,
3373 : V_MUL_HI_I32_I24_e32 = 3358,
3374 : V_MUL_HI_I32_I24_e64 = 3359,
3375 : V_MUL_HI_I32_I24_sdwa = 3360,
3376 : V_MUL_HI_U32 = 3361,
3377 : V_MUL_HI_U32_U24_e32 = 3362,
3378 : V_MUL_HI_U32_U24_e64 = 3363,
3379 : V_MUL_HI_U32_U24_sdwa = 3364,
3380 : V_MUL_I32_I24_e32 = 3365,
3381 : V_MUL_I32_I24_e64 = 3366,
3382 : V_MUL_I32_I24_sdwa = 3367,
3383 : V_MUL_LEGACY_F32_e32 = 3368,
3384 : V_MUL_LEGACY_F32_e64 = 3369,
3385 : V_MUL_LEGACY_F32_sdwa = 3370,
3386 : V_MUL_LO_I32 = 3371,
3387 : V_MUL_LO_U16_e32 = 3372,
3388 : V_MUL_LO_U16_e64 = 3373,
3389 : V_MUL_LO_U16_sdwa = 3374,
3390 : V_MUL_LO_U32 = 3375,
3391 : V_MUL_U32_U24_e32 = 3376,
3392 : V_MUL_U32_U24_e64 = 3377,
3393 : V_MUL_U32_U24_sdwa = 3378,
3394 : V_NOP_e32 = 3379,
3395 : V_NOP_e64 = 3380,
3396 : V_NOP_sdwa = 3381,
3397 : V_NOT_B32_e32 = 3382,
3398 : V_NOT_B32_e64 = 3383,
3399 : V_NOT_B32_sdwa = 3384,
3400 : V_OR3_B32 = 3385,
3401 : V_OR_B32_e32 = 3386,
3402 : V_OR_B32_e64 = 3387,
3403 : V_OR_B32_sdwa = 3388,
3404 : V_PACK_B32_F16 = 3389,
3405 : V_PERM_B32 = 3390,
3406 : V_PK_ADD_F16 = 3391,
3407 : V_PK_ADD_I16 = 3392,
3408 : V_PK_ADD_U16 = 3393,
3409 : V_PK_ASHRREV_I16 = 3394,
3410 : V_PK_FMA_F16 = 3395,
3411 : V_PK_LSHLREV_B16 = 3396,
3412 : V_PK_LSHRREV_B16 = 3397,
3413 : V_PK_MAD_I16 = 3398,
3414 : V_PK_MAD_U16 = 3399,
3415 : V_PK_MAX_F16 = 3400,
3416 : V_PK_MAX_I16 = 3401,
3417 : V_PK_MAX_U16 = 3402,
3418 : V_PK_MIN_F16 = 3403,
3419 : V_PK_MIN_I16 = 3404,
3420 : V_PK_MIN_U16 = 3405,
3421 : V_PK_MUL_F16 = 3406,
3422 : V_PK_MUL_LO_U16 = 3407,
3423 : V_PK_SUB_I16 = 3408,
3424 : V_PK_SUB_U16 = 3409,
3425 : V_QSAD_PK_U16_U8 = 3410,
3426 : V_RCP_CLAMP_F32_e32 = 3411,
3427 : V_RCP_CLAMP_F32_e64 = 3412,
3428 : V_RCP_CLAMP_F32_sdwa = 3413,
3429 : V_RCP_CLAMP_F64_e32 = 3414,
3430 : V_RCP_CLAMP_F64_e64 = 3415,
3431 : V_RCP_CLAMP_F64_sdwa = 3416,
3432 : V_RCP_F16_e32 = 3417,
3433 : V_RCP_F16_e64 = 3418,
3434 : V_RCP_F16_sdwa = 3419,
3435 : V_RCP_F32_e32 = 3420,
3436 : V_RCP_F32_e64 = 3421,
3437 : V_RCP_F32_sdwa = 3422,
3438 : V_RCP_F64_e32 = 3423,
3439 : V_RCP_F64_e64 = 3424,
3440 : V_RCP_F64_sdwa = 3425,
3441 : V_RCP_IFLAG_F32_e32 = 3426,
3442 : V_RCP_IFLAG_F32_e64 = 3427,
3443 : V_RCP_IFLAG_F32_sdwa = 3428,
3444 : V_RCP_LEGACY_F32_e32 = 3429,
3445 : V_RCP_LEGACY_F32_e64 = 3430,
3446 : V_RCP_LEGACY_F32_sdwa = 3431,
3447 : V_READLANE_B32 = 3432,
3448 : V_RNDNE_F16_e32 = 3433,
3449 : V_RNDNE_F16_e64 = 3434,
3450 : V_RNDNE_F16_sdwa = 3435,
3451 : V_RNDNE_F32_e32 = 3436,
3452 : V_RNDNE_F32_e64 = 3437,
3453 : V_RNDNE_F32_sdwa = 3438,
3454 : V_RNDNE_F64_e32 = 3439,
3455 : V_RNDNE_F64_e64 = 3440,
3456 : V_RNDNE_F64_sdwa = 3441,
3457 : V_RSQ_CLAMP_F32_e32 = 3442,
3458 : V_RSQ_CLAMP_F32_e64 = 3443,
3459 : V_RSQ_CLAMP_F32_sdwa = 3444,
3460 : V_RSQ_CLAMP_F64_e32 = 3445,
3461 : V_RSQ_CLAMP_F64_e64 = 3446,
3462 : V_RSQ_CLAMP_F64_sdwa = 3447,
3463 : V_RSQ_F16_e32 = 3448,
3464 : V_RSQ_F16_e64 = 3449,
3465 : V_RSQ_F16_sdwa = 3450,
3466 : V_RSQ_F32_e32 = 3451,
3467 : V_RSQ_F32_e64 = 3452,
3468 : V_RSQ_F32_sdwa = 3453,
3469 : V_RSQ_F64_e32 = 3454,
3470 : V_RSQ_F64_e64 = 3455,
3471 : V_RSQ_F64_sdwa = 3456,
3472 : V_RSQ_LEGACY_F32_e32 = 3457,
3473 : V_RSQ_LEGACY_F32_e64 = 3458,
3474 : V_RSQ_LEGACY_F32_sdwa = 3459,
3475 : V_SAD_HI_U8 = 3460,
3476 : V_SAD_U16 = 3461,
3477 : V_SAD_U32 = 3462,
3478 : V_SAD_U8 = 3463,
3479 : V_SAT_PK_U8_I16_e32 = 3464,
3480 : V_SAT_PK_U8_I16_e64 = 3465,
3481 : V_SAT_PK_U8_I16_sdwa = 3466,
3482 : V_SCREEN_PARTITION_4SE_B32_e32 = 3467,
3483 : V_SCREEN_PARTITION_4SE_B32_e64 = 3468,
3484 : V_SCREEN_PARTITION_4SE_B32_sdwa = 3469,
3485 : V_SET_INACTIVE_B32 = 3470,
3486 : V_SET_INACTIVE_B64 = 3471,
3487 : V_SIN_F16_e32 = 3472,
3488 : V_SIN_F16_e64 = 3473,
3489 : V_SIN_F16_sdwa = 3474,
3490 : V_SIN_F32_e32 = 3475,
3491 : V_SIN_F32_e64 = 3476,
3492 : V_SIN_F32_sdwa = 3477,
3493 : V_SQRT_F16_e32 = 3478,
3494 : V_SQRT_F16_e64 = 3479,
3495 : V_SQRT_F16_sdwa = 3480,
3496 : V_SQRT_F32_e32 = 3481,
3497 : V_SQRT_F32_e64 = 3482,
3498 : V_SQRT_F32_sdwa = 3483,
3499 : V_SQRT_F64_e32 = 3484,
3500 : V_SQRT_F64_e64 = 3485,
3501 : V_SQRT_F64_sdwa = 3486,
3502 : V_SUBBREV_U32_e32 = 3487,
3503 : V_SUBBREV_U32_e64 = 3488,
3504 : V_SUBBREV_U32_sdwa = 3489,
3505 : V_SUBB_U32_e32 = 3490,
3506 : V_SUBB_U32_e64 = 3491,
3507 : V_SUBB_U32_sdwa = 3492,
3508 : V_SUBREV_F16_e32 = 3493,
3509 : V_SUBREV_F16_e64 = 3494,
3510 : V_SUBREV_F16_sdwa = 3495,
3511 : V_SUBREV_F32_e32 = 3496,
3512 : V_SUBREV_F32_e64 = 3497,
3513 : V_SUBREV_F32_sdwa = 3498,
3514 : V_SUBREV_I32_e32 = 3499,
3515 : V_SUBREV_I32_e64 = 3500,
3516 : V_SUBREV_I32_sdwa = 3501,
3517 : V_SUBREV_U16_e32 = 3502,
3518 : V_SUBREV_U16_e64 = 3503,
3519 : V_SUBREV_U16_sdwa = 3504,
3520 : V_SUBREV_U32_e32 = 3505,
3521 : V_SUBREV_U32_e64 = 3506,
3522 : V_SUBREV_U32_sdwa = 3507,
3523 : V_SUB_F16_e32 = 3508,
3524 : V_SUB_F16_e64 = 3509,
3525 : V_SUB_F16_sdwa = 3510,
3526 : V_SUB_F32_e32 = 3511,
3527 : V_SUB_F32_e64 = 3512,
3528 : V_SUB_F32_sdwa = 3513,
3529 : V_SUB_I16 = 3514,
3530 : V_SUB_I32_e32 = 3515,
3531 : V_SUB_I32_e64 = 3516,
3532 : V_SUB_I32_gfx9 = 3517,
3533 : V_SUB_I32_sdwa = 3518,
3534 : V_SUB_U16_e32 = 3519,
3535 : V_SUB_U16_e64 = 3520,
3536 : V_SUB_U16_sdwa = 3521,
3537 : V_SUB_U32_e32 = 3522,
3538 : V_SUB_U32_e64 = 3523,
3539 : V_SUB_U32_sdwa = 3524,
3540 : V_SWAP_B32 = 3525,
3541 : V_TRIG_PREOP_F64 = 3526,
3542 : V_TRUNC_F16_e32 = 3527,
3543 : V_TRUNC_F16_e64 = 3528,
3544 : V_TRUNC_F16_sdwa = 3529,
3545 : V_TRUNC_F32_e32 = 3530,
3546 : V_TRUNC_F32_e64 = 3531,
3547 : V_TRUNC_F32_sdwa = 3532,
3548 : V_TRUNC_F64_e32 = 3533,
3549 : V_TRUNC_F64_e64 = 3534,
3550 : V_TRUNC_F64_sdwa = 3535,
3551 : V_WRITELANE_B32 = 3536,
3552 : V_XAD_U32 = 3537,
3553 : V_XNOR_B32_e32 = 3538,
3554 : V_XNOR_B32_e64 = 3539,
3555 : V_XNOR_B32_sdwa = 3540,
3556 : V_XOR_B32_e32 = 3541,
3557 : V_XOR_B32_e64 = 3542,
3558 : V_XOR_B32_sdwa = 3543,
3559 : WAVE_BARRIER = 3544,
3560 : WQM = 3545,
3561 : WWM = 3546,
3562 : BUFFER_ATOMIC_ADD_ADDR64_RTN_si = 3547,
3563 : BUFFER_ATOMIC_ADD_ADDR64_si = 3548,
3564 : BUFFER_ATOMIC_ADD_BOTHEN_RTN_si = 3549,
3565 : BUFFER_ATOMIC_ADD_BOTHEN_RTN_vi = 3550,
3566 : BUFFER_ATOMIC_ADD_BOTHEN_si = 3551,
3567 : BUFFER_ATOMIC_ADD_BOTHEN_vi = 3552,
3568 : BUFFER_ATOMIC_ADD_IDXEN_RTN_si = 3553,
3569 : BUFFER_ATOMIC_ADD_IDXEN_RTN_vi = 3554,
3570 : BUFFER_ATOMIC_ADD_IDXEN_si = 3555,
3571 : BUFFER_ATOMIC_ADD_IDXEN_vi = 3556,
3572 : BUFFER_ATOMIC_ADD_OFFEN_RTN_si = 3557,
3573 : BUFFER_ATOMIC_ADD_OFFEN_RTN_vi = 3558,
3574 : BUFFER_ATOMIC_ADD_OFFEN_si = 3559,
3575 : BUFFER_ATOMIC_ADD_OFFEN_vi = 3560,
3576 : BUFFER_ATOMIC_ADD_OFFSET_RTN_si = 3561,
3577 : BUFFER_ATOMIC_ADD_OFFSET_RTN_vi = 3562,
3578 : BUFFER_ATOMIC_ADD_OFFSET_si = 3563,
3579 : BUFFER_ATOMIC_ADD_OFFSET_vi = 3564,
3580 : BUFFER_ATOMIC_ADD_X2_ADDR64_RTN_si = 3565,
3581 : BUFFER_ATOMIC_ADD_X2_ADDR64_si = 3566,
3582 : BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_si = 3567,
3583 : BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN_vi = 3568,
3584 : BUFFER_ATOMIC_ADD_X2_BOTHEN_si = 3569,
3585 : BUFFER_ATOMIC_ADD_X2_BOTHEN_vi = 3570,
3586 : BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_si = 3571,
3587 : BUFFER_ATOMIC_ADD_X2_IDXEN_RTN_vi = 3572,
3588 : BUFFER_ATOMIC_ADD_X2_IDXEN_si = 3573,
3589 : BUFFER_ATOMIC_ADD_X2_IDXEN_vi = 3574,
3590 : BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_si = 3575,
3591 : BUFFER_ATOMIC_ADD_X2_OFFEN_RTN_vi = 3576,
3592 : BUFFER_ATOMIC_ADD_X2_OFFEN_si = 3577,
3593 : BUFFER_ATOMIC_ADD_X2_OFFEN_vi = 3578,
3594 : BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_si = 3579,
3595 : BUFFER_ATOMIC_ADD_X2_OFFSET_RTN_vi = 3580,
3596 : BUFFER_ATOMIC_ADD_X2_OFFSET_si = 3581,
3597 : BUFFER_ATOMIC_ADD_X2_OFFSET_vi = 3582,
3598 : BUFFER_ATOMIC_AND_ADDR64_RTN_si = 3583,
3599 : BUFFER_ATOMIC_AND_ADDR64_si = 3584,
3600 : BUFFER_ATOMIC_AND_BOTHEN_RTN_si = 3585,
3601 : BUFFER_ATOMIC_AND_BOTHEN_RTN_vi = 3586,
3602 : BUFFER_ATOMIC_AND_BOTHEN_si = 3587,
3603 : BUFFER_ATOMIC_AND_BOTHEN_vi = 3588,
3604 : BUFFER_ATOMIC_AND_IDXEN_RTN_si = 3589,
3605 : BUFFER_ATOMIC_AND_IDXEN_RTN_vi = 3590,
3606 : BUFFER_ATOMIC_AND_IDXEN_si = 3591,
3607 : BUFFER_ATOMIC_AND_IDXEN_vi = 3592,
3608 : BUFFER_ATOMIC_AND_OFFEN_RTN_si = 3593,
3609 : BUFFER_ATOMIC_AND_OFFEN_RTN_vi = 3594,
3610 : BUFFER_ATOMIC_AND_OFFEN_si = 3595,
3611 : BUFFER_ATOMIC_AND_OFFEN_vi = 3596,
3612 : BUFFER_ATOMIC_AND_OFFSET_RTN_si = 3597,
3613 : BUFFER_ATOMIC_AND_OFFSET_RTN_vi = 3598,
3614 : BUFFER_ATOMIC_AND_OFFSET_si = 3599,
3615 : BUFFER_ATOMIC_AND_OFFSET_vi = 3600,
3616 : BUFFER_ATOMIC_AND_X2_ADDR64_RTN_si = 3601,
3617 : BUFFER_ATOMIC_AND_X2_ADDR64_si = 3602,
3618 : BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_si = 3603,
3619 : BUFFER_ATOMIC_AND_X2_BOTHEN_RTN_vi = 3604,
3620 : BUFFER_ATOMIC_AND_X2_BOTHEN_si = 3605,
3621 : BUFFER_ATOMIC_AND_X2_BOTHEN_vi = 3606,
3622 : BUFFER_ATOMIC_AND_X2_IDXEN_RTN_si = 3607,
3623 : BUFFER_ATOMIC_AND_X2_IDXEN_RTN_vi = 3608,
3624 : BUFFER_ATOMIC_AND_X2_IDXEN_si = 3609,
3625 : BUFFER_ATOMIC_AND_X2_IDXEN_vi = 3610,
3626 : BUFFER_ATOMIC_AND_X2_OFFEN_RTN_si = 3611,
3627 : BUFFER_ATOMIC_AND_X2_OFFEN_RTN_vi = 3612,
3628 : BUFFER_ATOMIC_AND_X2_OFFEN_si = 3613,
3629 : BUFFER_ATOMIC_AND_X2_OFFEN_vi = 3614,
3630 : BUFFER_ATOMIC_AND_X2_OFFSET_RTN_si = 3615,
3631 : BUFFER_ATOMIC_AND_X2_OFFSET_RTN_vi = 3616,
3632 : BUFFER_ATOMIC_AND_X2_OFFSET_si = 3617,
3633 : BUFFER_ATOMIC_AND_X2_OFFSET_vi = 3618,
3634 : BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN_si = 3619,
3635 : BUFFER_ATOMIC_CMPSWAP_ADDR64_si = 3620,
3636 : BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_si = 3621,
3637 : BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN_vi = 3622,
3638 : BUFFER_ATOMIC_CMPSWAP_BOTHEN_si = 3623,
3639 : BUFFER_ATOMIC_CMPSWAP_BOTHEN_vi = 3624,
3640 : BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_si = 3625,
3641 : BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN_vi = 3626,
3642 : BUFFER_ATOMIC_CMPSWAP_IDXEN_si = 3627,
3643 : BUFFER_ATOMIC_CMPSWAP_IDXEN_vi = 3628,
3644 : BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_si = 3629,
3645 : BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN_vi = 3630,
3646 : BUFFER_ATOMIC_CMPSWAP_OFFEN_si = 3631,
3647 : BUFFER_ATOMIC_CMPSWAP_OFFEN_vi = 3632,
3648 : BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_si = 3633,
3649 : BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN_vi = 3634,
3650 : BUFFER_ATOMIC_CMPSWAP_OFFSET_si = 3635,
3651 : BUFFER_ATOMIC_CMPSWAP_OFFSET_vi = 3636,
3652 : BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN_si = 3637,
3653 : BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_si = 3638,
3654 : BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_si = 3639,
3655 : BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN_vi = 3640,
3656 : BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_si = 3641,
3657 : BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_vi = 3642,
3658 : BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_si = 3643,
3659 : BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN_vi = 3644,
3660 : BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_si = 3645,
3661 : BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_vi = 3646,
3662 : BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_si = 3647,
3663 : BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN_vi = 3648,
3664 : BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_si = 3649,
3665 : BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_vi = 3650,
3666 : BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_si = 3651,
3667 : BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN_vi = 3652,
3668 : BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_si = 3653,
3669 : BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_vi = 3654,
3670 : BUFFER_ATOMIC_DEC_ADDR64_RTN_si = 3655,
3671 : BUFFER_ATOMIC_DEC_ADDR64_si = 3656,
3672 : BUFFER_ATOMIC_DEC_BOTHEN_RTN_si = 3657,
3673 : BUFFER_ATOMIC_DEC_BOTHEN_RTN_vi = 3658,
3674 : BUFFER_ATOMIC_DEC_BOTHEN_si = 3659,
3675 : BUFFER_ATOMIC_DEC_BOTHEN_vi = 3660,
3676 : BUFFER_ATOMIC_DEC_IDXEN_RTN_si = 3661,
3677 : BUFFER_ATOMIC_DEC_IDXEN_RTN_vi = 3662,
3678 : BUFFER_ATOMIC_DEC_IDXEN_si = 3663,
3679 : BUFFER_ATOMIC_DEC_IDXEN_vi = 3664,
3680 : BUFFER_ATOMIC_DEC_OFFEN_RTN_si = 3665,
3681 : BUFFER_ATOMIC_DEC_OFFEN_RTN_vi = 3666,
3682 : BUFFER_ATOMIC_DEC_OFFEN_si = 3667,
3683 : BUFFER_ATOMIC_DEC_OFFEN_vi = 3668,
3684 : BUFFER_ATOMIC_DEC_OFFSET_RTN_si = 3669,
3685 : BUFFER_ATOMIC_DEC_OFFSET_RTN_vi = 3670,
3686 : BUFFER_ATOMIC_DEC_OFFSET_si = 3671,
3687 : BUFFER_ATOMIC_DEC_OFFSET_vi = 3672,
3688 : BUFFER_ATOMIC_DEC_X2_ADDR64_RTN_si = 3673,
3689 : BUFFER_ATOMIC_DEC_X2_ADDR64_si = 3674,
3690 : BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_si = 3675,
3691 : BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN_vi = 3676,
3692 : BUFFER_ATOMIC_DEC_X2_BOTHEN_si = 3677,
3693 : BUFFER_ATOMIC_DEC_X2_BOTHEN_vi = 3678,
3694 : BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_si = 3679,
3695 : BUFFER_ATOMIC_DEC_X2_IDXEN_RTN_vi = 3680,
3696 : BUFFER_ATOMIC_DEC_X2_IDXEN_si = 3681,
3697 : BUFFER_ATOMIC_DEC_X2_IDXEN_vi = 3682,
3698 : BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_si = 3683,
3699 : BUFFER_ATOMIC_DEC_X2_OFFEN_RTN_vi = 3684,
3700 : BUFFER_ATOMIC_DEC_X2_OFFEN_si = 3685,
3701 : BUFFER_ATOMIC_DEC_X2_OFFEN_vi = 3686,
3702 : BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_si = 3687,
3703 : BUFFER_ATOMIC_DEC_X2_OFFSET_RTN_vi = 3688,
3704 : BUFFER_ATOMIC_DEC_X2_OFFSET_si = 3689,
3705 : BUFFER_ATOMIC_DEC_X2_OFFSET_vi = 3690,
3706 : BUFFER_ATOMIC_INC_ADDR64_RTN_si = 3691,
3707 : BUFFER_ATOMIC_INC_ADDR64_si = 3692,
3708 : BUFFER_ATOMIC_INC_BOTHEN_RTN_si = 3693,
3709 : BUFFER_ATOMIC_INC_BOTHEN_RTN_vi = 3694,
3710 : BUFFER_ATOMIC_INC_BOTHEN_si = 3695,
3711 : BUFFER_ATOMIC_INC_BOTHEN_vi = 3696,
3712 : BUFFER_ATOMIC_INC_IDXEN_RTN_si = 3697,
3713 : BUFFER_ATOMIC_INC_IDXEN_RTN_vi = 3698,
3714 : BUFFER_ATOMIC_INC_IDXEN_si = 3699,
3715 : BUFFER_ATOMIC_INC_IDXEN_vi = 3700,
3716 : BUFFER_ATOMIC_INC_OFFEN_RTN_si = 3701,
3717 : BUFFER_ATOMIC_INC_OFFEN_RTN_vi = 3702,
3718 : BUFFER_ATOMIC_INC_OFFEN_si = 3703,
3719 : BUFFER_ATOMIC_INC_OFFEN_vi = 3704,
3720 : BUFFER_ATOMIC_INC_OFFSET_RTN_si = 3705,
3721 : BUFFER_ATOMIC_INC_OFFSET_RTN_vi = 3706,
3722 : BUFFER_ATOMIC_INC_OFFSET_si = 3707,
3723 : BUFFER_ATOMIC_INC_OFFSET_vi = 3708,
3724 : BUFFER_ATOMIC_INC_X2_ADDR64_RTN_si = 3709,
3725 : BUFFER_ATOMIC_INC_X2_ADDR64_si = 3710,
3726 : BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_si = 3711,
3727 : BUFFER_ATOMIC_INC_X2_BOTHEN_RTN_vi = 3712,
3728 : BUFFER_ATOMIC_INC_X2_BOTHEN_si = 3713,
3729 : BUFFER_ATOMIC_INC_X2_BOTHEN_vi = 3714,
3730 : BUFFER_ATOMIC_INC_X2_IDXEN_RTN_si = 3715,
3731 : BUFFER_ATOMIC_INC_X2_IDXEN_RTN_vi = 3716,
3732 : BUFFER_ATOMIC_INC_X2_IDXEN_si = 3717,
3733 : BUFFER_ATOMIC_INC_X2_IDXEN_vi = 3718,
3734 : BUFFER_ATOMIC_INC_X2_OFFEN_RTN_si = 3719,
3735 : BUFFER_ATOMIC_INC_X2_OFFEN_RTN_vi = 3720,
3736 : BUFFER_ATOMIC_INC_X2_OFFEN_si = 3721,
3737 : BUFFER_ATOMIC_INC_X2_OFFEN_vi = 3722,
3738 : BUFFER_ATOMIC_INC_X2_OFFSET_RTN_si = 3723,
3739 : BUFFER_ATOMIC_INC_X2_OFFSET_RTN_vi = 3724,
3740 : BUFFER_ATOMIC_INC_X2_OFFSET_si = 3725,
3741 : BUFFER_ATOMIC_INC_X2_OFFSET_vi = 3726,
3742 : BUFFER_ATOMIC_OR_ADDR64_RTN_si = 3727,
3743 : BUFFER_ATOMIC_OR_ADDR64_si = 3728,
3744 : BUFFER_ATOMIC_OR_BOTHEN_RTN_si = 3729,
3745 : BUFFER_ATOMIC_OR_BOTHEN_RTN_vi = 3730,
3746 : BUFFER_ATOMIC_OR_BOTHEN_si = 3731,
3747 : BUFFER_ATOMIC_OR_BOTHEN_vi = 3732,
3748 : BUFFER_ATOMIC_OR_IDXEN_RTN_si = 3733,
3749 : BUFFER_ATOMIC_OR_IDXEN_RTN_vi = 3734,
3750 : BUFFER_ATOMIC_OR_IDXEN_si = 3735,
3751 : BUFFER_ATOMIC_OR_IDXEN_vi = 3736,
3752 : BUFFER_ATOMIC_OR_OFFEN_RTN_si = 3737,
3753 : BUFFER_ATOMIC_OR_OFFEN_RTN_vi = 3738,
3754 : BUFFER_ATOMIC_OR_OFFEN_si = 3739,
3755 : BUFFER_ATOMIC_OR_OFFEN_vi = 3740,
3756 : BUFFER_ATOMIC_OR_OFFSET_RTN_si = 3741,
3757 : BUFFER_ATOMIC_OR_OFFSET_RTN_vi = 3742,
3758 : BUFFER_ATOMIC_OR_OFFSET_si = 3743,
3759 : BUFFER_ATOMIC_OR_OFFSET_vi = 3744,
3760 : BUFFER_ATOMIC_OR_X2_ADDR64_RTN_si = 3745,
3761 : BUFFER_ATOMIC_OR_X2_ADDR64_si = 3746,
3762 : BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_si = 3747,
3763 : BUFFER_ATOMIC_OR_X2_BOTHEN_RTN_vi = 3748,
3764 : BUFFER_ATOMIC_OR_X2_BOTHEN_si = 3749,
3765 : BUFFER_ATOMIC_OR_X2_BOTHEN_vi = 3750,
3766 : BUFFER_ATOMIC_OR_X2_IDXEN_RTN_si = 3751,
3767 : BUFFER_ATOMIC_OR_X2_IDXEN_RTN_vi = 3752,
3768 : BUFFER_ATOMIC_OR_X2_IDXEN_si = 3753,
3769 : BUFFER_ATOMIC_OR_X2_IDXEN_vi = 3754,
3770 : BUFFER_ATOMIC_OR_X2_OFFEN_RTN_si = 3755,
3771 : BUFFER_ATOMIC_OR_X2_OFFEN_RTN_vi = 3756,
3772 : BUFFER_ATOMIC_OR_X2_OFFEN_si = 3757,
3773 : BUFFER_ATOMIC_OR_X2_OFFEN_vi = 3758,
3774 : BUFFER_ATOMIC_OR_X2_OFFSET_RTN_si = 3759,
3775 : BUFFER_ATOMIC_OR_X2_OFFSET_RTN_vi = 3760,
3776 : BUFFER_ATOMIC_OR_X2_OFFSET_si = 3761,
3777 : BUFFER_ATOMIC_OR_X2_OFFSET_vi = 3762,
3778 : BUFFER_ATOMIC_SMAX_ADDR64_RTN_si = 3763,
3779 : BUFFER_ATOMIC_SMAX_ADDR64_si = 3764,
3780 : BUFFER_ATOMIC_SMAX_BOTHEN_RTN_si = 3765,
3781 : BUFFER_ATOMIC_SMAX_BOTHEN_RTN_vi = 3766,
3782 : BUFFER_ATOMIC_SMAX_BOTHEN_si = 3767,
3783 : BUFFER_ATOMIC_SMAX_BOTHEN_vi = 3768,
3784 : BUFFER_ATOMIC_SMAX_IDXEN_RTN_si = 3769,
3785 : BUFFER_ATOMIC_SMAX_IDXEN_RTN_vi = 3770,
3786 : BUFFER_ATOMIC_SMAX_IDXEN_si = 3771,
3787 : BUFFER_ATOMIC_SMAX_IDXEN_vi = 3772,
3788 : BUFFER_ATOMIC_SMAX_OFFEN_RTN_si = 3773,
3789 : BUFFER_ATOMIC_SMAX_OFFEN_RTN_vi = 3774,
3790 : BUFFER_ATOMIC_SMAX_OFFEN_si = 3775,
3791 : BUFFER_ATOMIC_SMAX_OFFEN_vi = 3776,
3792 : BUFFER_ATOMIC_SMAX_OFFSET_RTN_si = 3777,
3793 : BUFFER_ATOMIC_SMAX_OFFSET_RTN_vi = 3778,
3794 : BUFFER_ATOMIC_SMAX_OFFSET_si = 3779,
3795 : BUFFER_ATOMIC_SMAX_OFFSET_vi = 3780,
3796 : BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN_si = 3781,
3797 : BUFFER_ATOMIC_SMAX_X2_ADDR64_si = 3782,
3798 : BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_si = 3783,
3799 : BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN_vi = 3784,
3800 : BUFFER_ATOMIC_SMAX_X2_BOTHEN_si = 3785,
3801 : BUFFER_ATOMIC_SMAX_X2_BOTHEN_vi = 3786,
3802 : BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_si = 3787,
3803 : BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN_vi = 3788,
3804 : BUFFER_ATOMIC_SMAX_X2_IDXEN_si = 3789,
3805 : BUFFER_ATOMIC_SMAX_X2_IDXEN_vi = 3790,
3806 : BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_si = 3791,
3807 : BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN_vi = 3792,
3808 : BUFFER_ATOMIC_SMAX_X2_OFFEN_si = 3793,
3809 : BUFFER_ATOMIC_SMAX_X2_OFFEN_vi = 3794,
3810 : BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_si = 3795,
3811 : BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN_vi = 3796,
3812 : BUFFER_ATOMIC_SMAX_X2_OFFSET_si = 3797,
3813 : BUFFER_ATOMIC_SMAX_X2_OFFSET_vi = 3798,
3814 : BUFFER_ATOMIC_SMIN_ADDR64_RTN_si = 3799,
3815 : BUFFER_ATOMIC_SMIN_ADDR64_si = 3800,
3816 : BUFFER_ATOMIC_SMIN_BOTHEN_RTN_si = 3801,
3817 : BUFFER_ATOMIC_SMIN_BOTHEN_RTN_vi = 3802,
3818 : BUFFER_ATOMIC_SMIN_BOTHEN_si = 3803,
3819 : BUFFER_ATOMIC_SMIN_BOTHEN_vi = 3804,
3820 : BUFFER_ATOMIC_SMIN_IDXEN_RTN_si = 3805,
3821 : BUFFER_ATOMIC_SMIN_IDXEN_RTN_vi = 3806,
3822 : BUFFER_ATOMIC_SMIN_IDXEN_si = 3807,
3823 : BUFFER_ATOMIC_SMIN_IDXEN_vi = 3808,
3824 : BUFFER_ATOMIC_SMIN_OFFEN_RTN_si = 3809,
3825 : BUFFER_ATOMIC_SMIN_OFFEN_RTN_vi = 3810,
3826 : BUFFER_ATOMIC_SMIN_OFFEN_si = 3811,
3827 : BUFFER_ATOMIC_SMIN_OFFEN_vi = 3812,
3828 : BUFFER_ATOMIC_SMIN_OFFSET_RTN_si = 3813,
3829 : BUFFER_ATOMIC_SMIN_OFFSET_RTN_vi = 3814,
3830 : BUFFER_ATOMIC_SMIN_OFFSET_si = 3815,
3831 : BUFFER_ATOMIC_SMIN_OFFSET_vi = 3816,
3832 : BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN_si = 3817,
3833 : BUFFER_ATOMIC_SMIN_X2_ADDR64_si = 3818,
3834 : BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_si = 3819,
3835 : BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN_vi = 3820,
3836 : BUFFER_ATOMIC_SMIN_X2_BOTHEN_si = 3821,
3837 : BUFFER_ATOMIC_SMIN_X2_BOTHEN_vi = 3822,
3838 : BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_si = 3823,
3839 : BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN_vi = 3824,
3840 : BUFFER_ATOMIC_SMIN_X2_IDXEN_si = 3825,
3841 : BUFFER_ATOMIC_SMIN_X2_IDXEN_vi = 3826,
3842 : BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_si = 3827,
3843 : BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN_vi = 3828,
3844 : BUFFER_ATOMIC_SMIN_X2_OFFEN_si = 3829,
3845 : BUFFER_ATOMIC_SMIN_X2_OFFEN_vi = 3830,
3846 : BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_si = 3831,
3847 : BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN_vi = 3832,
3848 : BUFFER_ATOMIC_SMIN_X2_OFFSET_si = 3833,
3849 : BUFFER_ATOMIC_SMIN_X2_OFFSET_vi = 3834,
3850 : BUFFER_ATOMIC_SUB_ADDR64_RTN_si = 3835,
3851 : BUFFER_ATOMIC_SUB_ADDR64_si = 3836,
3852 : BUFFER_ATOMIC_SUB_BOTHEN_RTN_si = 3837,
3853 : BUFFER_ATOMIC_SUB_BOTHEN_RTN_vi = 3838,
3854 : BUFFER_ATOMIC_SUB_BOTHEN_si = 3839,
3855 : BUFFER_ATOMIC_SUB_BOTHEN_vi = 3840,
3856 : BUFFER_ATOMIC_SUB_IDXEN_RTN_si = 3841,
3857 : BUFFER_ATOMIC_SUB_IDXEN_RTN_vi = 3842,
3858 : BUFFER_ATOMIC_SUB_IDXEN_si = 3843,
3859 : BUFFER_ATOMIC_SUB_IDXEN_vi = 3844,
3860 : BUFFER_ATOMIC_SUB_OFFEN_RTN_si = 3845,
3861 : BUFFER_ATOMIC_SUB_OFFEN_RTN_vi = 3846,
3862 : BUFFER_ATOMIC_SUB_OFFEN_si = 3847,
3863 : BUFFER_ATOMIC_SUB_OFFEN_vi = 3848,
3864 : BUFFER_ATOMIC_SUB_OFFSET_RTN_si = 3849,
3865 : BUFFER_ATOMIC_SUB_OFFSET_RTN_vi = 3850,
3866 : BUFFER_ATOMIC_SUB_OFFSET_si = 3851,
3867 : BUFFER_ATOMIC_SUB_OFFSET_vi = 3852,
3868 : BUFFER_ATOMIC_SUB_X2_ADDR64_RTN_si = 3853,
3869 : BUFFER_ATOMIC_SUB_X2_ADDR64_si = 3854,
3870 : BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_si = 3855,
3871 : BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN_vi = 3856,
3872 : BUFFER_ATOMIC_SUB_X2_BOTHEN_si = 3857,
3873 : BUFFER_ATOMIC_SUB_X2_BOTHEN_vi = 3858,
3874 : BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_si = 3859,
3875 : BUFFER_ATOMIC_SUB_X2_IDXEN_RTN_vi = 3860,
3876 : BUFFER_ATOMIC_SUB_X2_IDXEN_si = 3861,
3877 : BUFFER_ATOMIC_SUB_X2_IDXEN_vi = 3862,
3878 : BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_si = 3863,
3879 : BUFFER_ATOMIC_SUB_X2_OFFEN_RTN_vi = 3864,
3880 : BUFFER_ATOMIC_SUB_X2_OFFEN_si = 3865,
3881 : BUFFER_ATOMIC_SUB_X2_OFFEN_vi = 3866,
3882 : BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_si = 3867,
3883 : BUFFER_ATOMIC_SUB_X2_OFFSET_RTN_vi = 3868,
3884 : BUFFER_ATOMIC_SUB_X2_OFFSET_si = 3869,
3885 : BUFFER_ATOMIC_SUB_X2_OFFSET_vi = 3870,
3886 : BUFFER_ATOMIC_SWAP_ADDR64_RTN_si = 3871,
3887 : BUFFER_ATOMIC_SWAP_ADDR64_si = 3872,
3888 : BUFFER_ATOMIC_SWAP_BOTHEN_RTN_si = 3873,
3889 : BUFFER_ATOMIC_SWAP_BOTHEN_RTN_vi = 3874,
3890 : BUFFER_ATOMIC_SWAP_BOTHEN_si = 3875,
3891 : BUFFER_ATOMIC_SWAP_BOTHEN_vi = 3876,
3892 : BUFFER_ATOMIC_SWAP_IDXEN_RTN_si = 3877,
3893 : BUFFER_ATOMIC_SWAP_IDXEN_RTN_vi = 3878,
3894 : BUFFER_ATOMIC_SWAP_IDXEN_si = 3879,
3895 : BUFFER_ATOMIC_SWAP_IDXEN_vi = 3880,
3896 : BUFFER_ATOMIC_SWAP_OFFEN_RTN_si = 3881,
3897 : BUFFER_ATOMIC_SWAP_OFFEN_RTN_vi = 3882,
3898 : BUFFER_ATOMIC_SWAP_OFFEN_si = 3883,
3899 : BUFFER_ATOMIC_SWAP_OFFEN_vi = 3884,
3900 : BUFFER_ATOMIC_SWAP_OFFSET_RTN_si = 3885,
3901 : BUFFER_ATOMIC_SWAP_OFFSET_RTN_vi = 3886,
3902 : BUFFER_ATOMIC_SWAP_OFFSET_si = 3887,
3903 : BUFFER_ATOMIC_SWAP_OFFSET_vi = 3888,
3904 : BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN_si = 3889,
3905 : BUFFER_ATOMIC_SWAP_X2_ADDR64_si = 3890,
3906 : BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_si = 3891,
3907 : BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN_vi = 3892,
3908 : BUFFER_ATOMIC_SWAP_X2_BOTHEN_si = 3893,
3909 : BUFFER_ATOMIC_SWAP_X2_BOTHEN_vi = 3894,
3910 : BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_si = 3895,
3911 : BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN_vi = 3896,
3912 : BUFFER_ATOMIC_SWAP_X2_IDXEN_si = 3897,
3913 : BUFFER_ATOMIC_SWAP_X2_IDXEN_vi = 3898,
3914 : BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_si = 3899,
3915 : BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN_vi = 3900,
3916 : BUFFER_ATOMIC_SWAP_X2_OFFEN_si = 3901,
3917 : BUFFER_ATOMIC_SWAP_X2_OFFEN_vi = 3902,
3918 : BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_si = 3903,
3919 : BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN_vi = 3904,
3920 : BUFFER_ATOMIC_SWAP_X2_OFFSET_si = 3905,
3921 : BUFFER_ATOMIC_SWAP_X2_OFFSET_vi = 3906,
3922 : BUFFER_ATOMIC_UMAX_ADDR64_RTN_si = 3907,
3923 : BUFFER_ATOMIC_UMAX_ADDR64_si = 3908,
3924 : BUFFER_ATOMIC_UMAX_BOTHEN_RTN_si = 3909,
3925 : BUFFER_ATOMIC_UMAX_BOTHEN_RTN_vi = 3910,
3926 : BUFFER_ATOMIC_UMAX_BOTHEN_si = 3911,
3927 : BUFFER_ATOMIC_UMAX_BOTHEN_vi = 3912,
3928 : BUFFER_ATOMIC_UMAX_IDXEN_RTN_si = 3913,
3929 : BUFFER_ATOMIC_UMAX_IDXEN_RTN_vi = 3914,
3930 : BUFFER_ATOMIC_UMAX_IDXEN_si = 3915,
3931 : BUFFER_ATOMIC_UMAX_IDXEN_vi = 3916,
3932 : BUFFER_ATOMIC_UMAX_OFFEN_RTN_si = 3917,
3933 : BUFFER_ATOMIC_UMAX_OFFEN_RTN_vi = 3918,
3934 : BUFFER_ATOMIC_UMAX_OFFEN_si = 3919,
3935 : BUFFER_ATOMIC_UMAX_OFFEN_vi = 3920,
3936 : BUFFER_ATOMIC_UMAX_OFFSET_RTN_si = 3921,
3937 : BUFFER_ATOMIC_UMAX_OFFSET_RTN_vi = 3922,
3938 : BUFFER_ATOMIC_UMAX_OFFSET_si = 3923,
3939 : BUFFER_ATOMIC_UMAX_OFFSET_vi = 3924,
3940 : BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN_si = 3925,
3941 : BUFFER_ATOMIC_UMAX_X2_ADDR64_si = 3926,
3942 : BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_si = 3927,
3943 : BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN_vi = 3928,
3944 : BUFFER_ATOMIC_UMAX_X2_BOTHEN_si = 3929,
3945 : BUFFER_ATOMIC_UMAX_X2_BOTHEN_vi = 3930,
3946 : BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_si = 3931,
3947 : BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN_vi = 3932,
3948 : BUFFER_ATOMIC_UMAX_X2_IDXEN_si = 3933,
3949 : BUFFER_ATOMIC_UMAX_X2_IDXEN_vi = 3934,
3950 : BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_si = 3935,
3951 : BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN_vi = 3936,
3952 : BUFFER_ATOMIC_UMAX_X2_OFFEN_si = 3937,
3953 : BUFFER_ATOMIC_UMAX_X2_OFFEN_vi = 3938,
3954 : BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_si = 3939,
3955 : BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN_vi = 3940,
3956 : BUFFER_ATOMIC_UMAX_X2_OFFSET_si = 3941,
3957 : BUFFER_ATOMIC_UMAX_X2_OFFSET_vi = 3942,
3958 : BUFFER_ATOMIC_UMIN_ADDR64_RTN_si = 3943,
3959 : BUFFER_ATOMIC_UMIN_ADDR64_si = 3944,
3960 : BUFFER_ATOMIC_UMIN_BOTHEN_RTN_si = 3945,
3961 : BUFFER_ATOMIC_UMIN_BOTHEN_RTN_vi = 3946,
3962 : BUFFER_ATOMIC_UMIN_BOTHEN_si = 3947,
3963 : BUFFER_ATOMIC_UMIN_BOTHEN_vi = 3948,
3964 : BUFFER_ATOMIC_UMIN_IDXEN_RTN_si = 3949,
3965 : BUFFER_ATOMIC_UMIN_IDXEN_RTN_vi = 3950,
3966 : BUFFER_ATOMIC_UMIN_IDXEN_si = 3951,
3967 : BUFFER_ATOMIC_UMIN_IDXEN_vi = 3952,
3968 : BUFFER_ATOMIC_UMIN_OFFEN_RTN_si = 3953,
3969 : BUFFER_ATOMIC_UMIN_OFFEN_RTN_vi = 3954,
3970 : BUFFER_ATOMIC_UMIN_OFFEN_si = 3955,
3971 : BUFFER_ATOMIC_UMIN_OFFEN_vi = 3956,
3972 : BUFFER_ATOMIC_UMIN_OFFSET_RTN_si = 3957,
3973 : BUFFER_ATOMIC_UMIN_OFFSET_RTN_vi = 3958,
3974 : BUFFER_ATOMIC_UMIN_OFFSET_si = 3959,
3975 : BUFFER_ATOMIC_UMIN_OFFSET_vi = 3960,
3976 : BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN_si = 3961,
3977 : BUFFER_ATOMIC_UMIN_X2_ADDR64_si = 3962,
3978 : BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_si = 3963,
3979 : BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN_vi = 3964,
3980 : BUFFER_ATOMIC_UMIN_X2_BOTHEN_si = 3965,
3981 : BUFFER_ATOMIC_UMIN_X2_BOTHEN_vi = 3966,
3982 : BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_si = 3967,
3983 : BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN_vi = 3968,
3984 : BUFFER_ATOMIC_UMIN_X2_IDXEN_si = 3969,
3985 : BUFFER_ATOMIC_UMIN_X2_IDXEN_vi = 3970,
3986 : BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_si = 3971,
3987 : BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN_vi = 3972,
3988 : BUFFER_ATOMIC_UMIN_X2_OFFEN_si = 3973,
3989 : BUFFER_ATOMIC_UMIN_X2_OFFEN_vi = 3974,
3990 : BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_si = 3975,
3991 : BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN_vi = 3976,
3992 : BUFFER_ATOMIC_UMIN_X2_OFFSET_si = 3977,
3993 : BUFFER_ATOMIC_UMIN_X2_OFFSET_vi = 3978,
3994 : BUFFER_ATOMIC_XOR_ADDR64_RTN_si = 3979,
3995 : BUFFER_ATOMIC_XOR_ADDR64_si = 3980,
3996 : BUFFER_ATOMIC_XOR_BOTHEN_RTN_si = 3981,
3997 : BUFFER_ATOMIC_XOR_BOTHEN_RTN_vi = 3982,
3998 : BUFFER_ATOMIC_XOR_BOTHEN_si = 3983,
3999 : BUFFER_ATOMIC_XOR_BOTHEN_vi = 3984,
4000 : BUFFER_ATOMIC_XOR_IDXEN_RTN_si = 3985,
4001 : BUFFER_ATOMIC_XOR_IDXEN_RTN_vi = 3986,
4002 : BUFFER_ATOMIC_XOR_IDXEN_si = 3987,
4003 : BUFFER_ATOMIC_XOR_IDXEN_vi = 3988,
4004 : BUFFER_ATOMIC_XOR_OFFEN_RTN_si = 3989,
4005 : BUFFER_ATOMIC_XOR_OFFEN_RTN_vi = 3990,
4006 : BUFFER_ATOMIC_XOR_OFFEN_si = 3991,
4007 : BUFFER_ATOMIC_XOR_OFFEN_vi = 3992,
4008 : BUFFER_ATOMIC_XOR_OFFSET_RTN_si = 3993,
4009 : BUFFER_ATOMIC_XOR_OFFSET_RTN_vi = 3994,
4010 : BUFFER_ATOMIC_XOR_OFFSET_si = 3995,
4011 : BUFFER_ATOMIC_XOR_OFFSET_vi = 3996,
4012 : BUFFER_ATOMIC_XOR_X2_ADDR64_RTN_si = 3997,
4013 : BUFFER_ATOMIC_XOR_X2_ADDR64_si = 3998,
4014 : BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_si = 3999,
4015 : BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN_vi = 4000,
4016 : BUFFER_ATOMIC_XOR_X2_BOTHEN_si = 4001,
4017 : BUFFER_ATOMIC_XOR_X2_BOTHEN_vi = 4002,
4018 : BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_si = 4003,
4019 : BUFFER_ATOMIC_XOR_X2_IDXEN_RTN_vi = 4004,
4020 : BUFFER_ATOMIC_XOR_X2_IDXEN_si = 4005,
4021 : BUFFER_ATOMIC_XOR_X2_IDXEN_vi = 4006,
4022 : BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_si = 4007,
4023 : BUFFER_ATOMIC_XOR_X2_OFFEN_RTN_vi = 4008,
4024 : BUFFER_ATOMIC_XOR_X2_OFFEN_si = 4009,
4025 : BUFFER_ATOMIC_XOR_X2_OFFEN_vi = 4010,
4026 : BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_si = 4011,
4027 : BUFFER_ATOMIC_XOR_X2_OFFSET_RTN_vi = 4012,
4028 : BUFFER_ATOMIC_XOR_X2_OFFSET_si = 4013,
4029 : BUFFER_ATOMIC_XOR_X2_OFFSET_vi = 4014,
4030 : BUFFER_LOAD_DWORDX2_ADDR64_si = 4015,
4031 : BUFFER_LOAD_DWORDX2_BOTHEN_si = 4016,
4032 : BUFFER_LOAD_DWORDX2_BOTHEN_vi = 4017,
4033 : BUFFER_LOAD_DWORDX2_IDXEN_si = 4018,
4034 : BUFFER_LOAD_DWORDX2_IDXEN_vi = 4019,
4035 : BUFFER_LOAD_DWORDX2_LDS_BOTHEN_vi = 4020,
4036 : BUFFER_LOAD_DWORDX2_LDS_IDXEN_vi = 4021,
4037 : BUFFER_LOAD_DWORDX2_LDS_OFFEN_vi = 4022,
4038 : BUFFER_LOAD_DWORDX2_LDS_OFFSET_vi = 4023,
4039 : BUFFER_LOAD_DWORDX2_OFFEN_si = 4024,
4040 : BUFFER_LOAD_DWORDX2_OFFEN_vi = 4025,
4041 : BUFFER_LOAD_DWORDX2_OFFSET_si = 4026,
4042 : BUFFER_LOAD_DWORDX2_OFFSET_vi = 4027,
4043 : BUFFER_LOAD_DWORDX3_ADDR64_si = 4028,
4044 : BUFFER_LOAD_DWORDX3_BOTHEN_si = 4029,
4045 : BUFFER_LOAD_DWORDX3_BOTHEN_vi = 4030,
4046 : BUFFER_LOAD_DWORDX3_IDXEN_si = 4031,
4047 : BUFFER_LOAD_DWORDX3_IDXEN_vi = 4032,
4048 : BUFFER_LOAD_DWORDX3_LDS_BOTHEN_vi = 4033,
4049 : BUFFER_LOAD_DWORDX3_LDS_IDXEN_vi = 4034,
4050 : BUFFER_LOAD_DWORDX3_LDS_OFFEN_vi = 4035,
4051 : BUFFER_LOAD_DWORDX3_LDS_OFFSET_vi = 4036,
4052 : BUFFER_LOAD_DWORDX3_OFFEN_si = 4037,
4053 : BUFFER_LOAD_DWORDX3_OFFEN_vi = 4038,
4054 : BUFFER_LOAD_DWORDX3_OFFSET_si = 4039,
4055 : BUFFER_LOAD_DWORDX3_OFFSET_vi = 4040,
4056 : BUFFER_LOAD_DWORDX4_ADDR64_si = 4041,
4057 : BUFFER_LOAD_DWORDX4_BOTHEN_si = 4042,
4058 : BUFFER_LOAD_DWORDX4_BOTHEN_vi = 4043,
4059 : BUFFER_LOAD_DWORDX4_IDXEN_si = 4044,
4060 : BUFFER_LOAD_DWORDX4_IDXEN_vi = 4045,
4061 : BUFFER_LOAD_DWORDX4_LDS_BOTHEN_vi = 4046,
4062 : BUFFER_LOAD_DWORDX4_LDS_IDXEN_vi = 4047,
4063 : BUFFER_LOAD_DWORDX4_LDS_OFFEN_vi = 4048,
4064 : BUFFER_LOAD_DWORDX4_LDS_OFFSET_vi = 4049,
4065 : BUFFER_LOAD_DWORDX4_OFFEN_si = 4050,
4066 : BUFFER_LOAD_DWORDX4_OFFEN_vi = 4051,
4067 : BUFFER_LOAD_DWORDX4_OFFSET_si = 4052,
4068 : BUFFER_LOAD_DWORDX4_OFFSET_vi = 4053,
4069 : BUFFER_LOAD_DWORD_ADDR64_si = 4054,
4070 : BUFFER_LOAD_DWORD_BOTHEN_si = 4055,
4071 : BUFFER_LOAD_DWORD_BOTHEN_vi = 4056,
4072 : BUFFER_LOAD_DWORD_IDXEN_si = 4057,
4073 : BUFFER_LOAD_DWORD_IDXEN_vi = 4058,
4074 : BUFFER_LOAD_DWORD_LDS_ADDR64_si = 4059,
4075 : BUFFER_LOAD_DWORD_LDS_BOTHEN_si = 4060,
4076 : BUFFER_LOAD_DWORD_LDS_BOTHEN_vi = 4061,
4077 : BUFFER_LOAD_DWORD_LDS_IDXEN_si = 4062,
4078 : BUFFER_LOAD_DWORD_LDS_IDXEN_vi = 4063,
4079 : BUFFER_LOAD_DWORD_LDS_OFFEN_si = 4064,
4080 : BUFFER_LOAD_DWORD_LDS_OFFEN_vi = 4065,
4081 : BUFFER_LOAD_DWORD_LDS_OFFSET_si = 4066,
4082 : BUFFER_LOAD_DWORD_LDS_OFFSET_vi = 4067,
4083 : BUFFER_LOAD_DWORD_OFFEN_si = 4068,
4084 : BUFFER_LOAD_DWORD_OFFEN_vi = 4069,
4085 : BUFFER_LOAD_DWORD_OFFSET_si = 4070,
4086 : BUFFER_LOAD_DWORD_OFFSET_vi = 4071,
4087 : BUFFER_LOAD_FORMAT_D16_HI_X_BOTHEN_vi = 4072,
4088 : BUFFER_LOAD_FORMAT_D16_HI_X_IDXEN_vi = 4073,
4089 : BUFFER_LOAD_FORMAT_D16_HI_X_OFFEN_vi = 4074,
4090 : BUFFER_LOAD_FORMAT_D16_HI_X_OFFSET_vi = 4075,
4091 : BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi = 4076,
4092 : BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi = 4077,
4093 : BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi = 4078,
4094 : BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi = 4079,
4095 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80 = 4080,
4096 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80 = 4081,
4097 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80 = 4082,
4098 : BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80 = 4083,
4099 : BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi = 4084,
4100 : BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi = 4085,
4101 : BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi = 4086,
4102 : BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi = 4087,
4103 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80 = 4088,
4104 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80 = 4089,
4105 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80 = 4090,
4106 : BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80 = 4091,
4107 : BUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi = 4092,
4108 : BUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi = 4093,
4109 : BUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi = 4094,
4110 : BUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi = 4095,
4111 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80 = 4096,
4112 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80 = 4097,
4113 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80 = 4098,
4114 : BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80 = 4099,
4115 : BUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi = 4100,
4116 : BUFFER_LOAD_FORMAT_D16_X_IDXEN_vi = 4101,
4117 : BUFFER_LOAD_FORMAT_D16_X_OFFEN_vi = 4102,
4118 : BUFFER_LOAD_FORMAT_D16_X_OFFSET_vi = 4103,
4119 : BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80 = 4104,
4120 : BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80 = 4105,
4121 : BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80 = 4106,
4122 : BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80 = 4107,
4123 : BUFFER_LOAD_FORMAT_XYZW_ADDR64_si = 4108,
4124 : BUFFER_LOAD_FORMAT_XYZW_BOTHEN_si = 4109,
4125 : BUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi = 4110,
4126 : BUFFER_LOAD_FORMAT_XYZW_IDXEN_si = 4111,
4127 : BUFFER_LOAD_FORMAT_XYZW_IDXEN_vi = 4112,
4128 : BUFFER_LOAD_FORMAT_XYZW_OFFEN_si = 4113,
4129 : BUFFER_LOAD_FORMAT_XYZW_OFFEN_vi = 4114,
4130 : BUFFER_LOAD_FORMAT_XYZW_OFFSET_si = 4115,
4131 : BUFFER_LOAD_FORMAT_XYZW_OFFSET_vi = 4116,
4132 : BUFFER_LOAD_FORMAT_XYZ_ADDR64_si = 4117,
4133 : BUFFER_LOAD_FORMAT_XYZ_BOTHEN_si = 4118,
4134 : BUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi = 4119,
4135 : BUFFER_LOAD_FORMAT_XYZ_IDXEN_si = 4120,
4136 : BUFFER_LOAD_FORMAT_XYZ_IDXEN_vi = 4121,
4137 : BUFFER_LOAD_FORMAT_XYZ_OFFEN_si = 4122,
4138 : BUFFER_LOAD_FORMAT_XYZ_OFFEN_vi = 4123,
4139 : BUFFER_LOAD_FORMAT_XYZ_OFFSET_si = 4124,
4140 : BUFFER_LOAD_FORMAT_XYZ_OFFSET_vi = 4125,
4141 : BUFFER_LOAD_FORMAT_XY_ADDR64_si = 4126,
4142 : BUFFER_LOAD_FORMAT_XY_BOTHEN_si = 4127,
4143 : BUFFER_LOAD_FORMAT_XY_BOTHEN_vi = 4128,
4144 : BUFFER_LOAD_FORMAT_XY_IDXEN_si = 4129,
4145 : BUFFER_LOAD_FORMAT_XY_IDXEN_vi = 4130,
4146 : BUFFER_LOAD_FORMAT_XY_OFFEN_si = 4131,
4147 : BUFFER_LOAD_FORMAT_XY_OFFEN_vi = 4132,
4148 : BUFFER_LOAD_FORMAT_XY_OFFSET_si = 4133,
4149 : BUFFER_LOAD_FORMAT_XY_OFFSET_vi = 4134,
4150 : BUFFER_LOAD_FORMAT_X_ADDR64_si = 4135,
4151 : BUFFER_LOAD_FORMAT_X_BOTHEN_si = 4136,
4152 : BUFFER_LOAD_FORMAT_X_BOTHEN_vi = 4137,
4153 : BUFFER_LOAD_FORMAT_X_IDXEN_si = 4138,
4154 : BUFFER_LOAD_FORMAT_X_IDXEN_vi = 4139,
4155 : BUFFER_LOAD_FORMAT_X_LDS_ADDR64_si = 4140,
4156 : BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_si = 4141,
4157 : BUFFER_LOAD_FORMAT_X_LDS_BOTHEN_vi = 4142,
4158 : BUFFER_LOAD_FORMAT_X_LDS_IDXEN_si = 4143,
4159 : BUFFER_LOAD_FORMAT_X_LDS_IDXEN_vi = 4144,
4160 : BUFFER_LOAD_FORMAT_X_LDS_OFFEN_si = 4145,
4161 : BUFFER_LOAD_FORMAT_X_LDS_OFFEN_vi = 4146,
4162 : BUFFER_LOAD_FORMAT_X_LDS_OFFSET_si = 4147,
4163 : BUFFER_LOAD_FORMAT_X_LDS_OFFSET_vi = 4148,
4164 : BUFFER_LOAD_FORMAT_X_OFFEN_si = 4149,
4165 : BUFFER_LOAD_FORMAT_X_OFFEN_vi = 4150,
4166 : BUFFER_LOAD_FORMAT_X_OFFSET_si = 4151,
4167 : BUFFER_LOAD_FORMAT_X_OFFSET_vi = 4152,
4168 : BUFFER_LOAD_SBYTE_ADDR64_si = 4153,
4169 : BUFFER_LOAD_SBYTE_BOTHEN_si = 4154,
4170 : BUFFER_LOAD_SBYTE_BOTHEN_vi = 4155,
4171 : BUFFER_LOAD_SBYTE_D16_BOTHEN_vi = 4156,
4172 : BUFFER_LOAD_SBYTE_D16_HI_BOTHEN_vi = 4157,
4173 : BUFFER_LOAD_SBYTE_D16_HI_IDXEN_vi = 4158,
4174 : BUFFER_LOAD_SBYTE_D16_HI_OFFEN_vi = 4159,
4175 : BUFFER_LOAD_SBYTE_D16_HI_OFFSET_vi = 4160,
4176 : BUFFER_LOAD_SBYTE_D16_IDXEN_vi = 4161,
4177 : BUFFER_LOAD_SBYTE_D16_OFFEN_vi = 4162,
4178 : BUFFER_LOAD_SBYTE_D16_OFFSET_vi = 4163,
4179 : BUFFER_LOAD_SBYTE_IDXEN_si = 4164,
4180 : BUFFER_LOAD_SBYTE_IDXEN_vi = 4165,
4181 : BUFFER_LOAD_SBYTE_LDS_ADDR64_si = 4166,
4182 : BUFFER_LOAD_SBYTE_LDS_BOTHEN_si = 4167,
4183 : BUFFER_LOAD_SBYTE_LDS_BOTHEN_vi = 4168,
4184 : BUFFER_LOAD_SBYTE_LDS_IDXEN_si = 4169,
4185 : BUFFER_LOAD_SBYTE_LDS_IDXEN_vi = 4170,
4186 : BUFFER_LOAD_SBYTE_LDS_OFFEN_si = 4171,
4187 : BUFFER_LOAD_SBYTE_LDS_OFFEN_vi = 4172,
4188 : BUFFER_LOAD_SBYTE_LDS_OFFSET_si = 4173,
4189 : BUFFER_LOAD_SBYTE_LDS_OFFSET_vi = 4174,
4190 : BUFFER_LOAD_SBYTE_OFFEN_si = 4175,
4191 : BUFFER_LOAD_SBYTE_OFFEN_vi = 4176,
4192 : BUFFER_LOAD_SBYTE_OFFSET_si = 4177,
4193 : BUFFER_LOAD_SBYTE_OFFSET_vi = 4178,
4194 : BUFFER_LOAD_SHORT_D16_BOTHEN_vi = 4179,
4195 : BUFFER_LOAD_SHORT_D16_HI_BOTHEN_vi = 4180,
4196 : BUFFER_LOAD_SHORT_D16_HI_IDXEN_vi = 4181,
4197 : BUFFER_LOAD_SHORT_D16_HI_OFFEN_vi = 4182,
4198 : BUFFER_LOAD_SHORT_D16_HI_OFFSET_vi = 4183,
4199 : BUFFER_LOAD_SHORT_D16_IDXEN_vi = 4184,
4200 : BUFFER_LOAD_SHORT_D16_OFFEN_vi = 4185,
4201 : BUFFER_LOAD_SHORT_D16_OFFSET_vi = 4186,
4202 : BUFFER_LOAD_SSHORT_ADDR64_si = 4187,
4203 : BUFFER_LOAD_SSHORT_BOTHEN_si = 4188,
4204 : BUFFER_LOAD_SSHORT_BOTHEN_vi = 4189,
4205 : BUFFER_LOAD_SSHORT_IDXEN_si = 4190,
4206 : BUFFER_LOAD_SSHORT_IDXEN_vi = 4191,
4207 : BUFFER_LOAD_SSHORT_LDS_ADDR64_si = 4192,
4208 : BUFFER_LOAD_SSHORT_LDS_BOTHEN_si = 4193,
4209 : BUFFER_LOAD_SSHORT_LDS_BOTHEN_vi = 4194,
4210 : BUFFER_LOAD_SSHORT_LDS_IDXEN_si = 4195,
4211 : BUFFER_LOAD_SSHORT_LDS_IDXEN_vi = 4196,
4212 : BUFFER_LOAD_SSHORT_LDS_OFFEN_si = 4197,
4213 : BUFFER_LOAD_SSHORT_LDS_OFFEN_vi = 4198,
4214 : BUFFER_LOAD_SSHORT_LDS_OFFSET_si = 4199,
4215 : BUFFER_LOAD_SSHORT_LDS_OFFSET_vi = 4200,
4216 : BUFFER_LOAD_SSHORT_OFFEN_si = 4201,
4217 : BUFFER_LOAD_SSHORT_OFFEN_vi = 4202,
4218 : BUFFER_LOAD_SSHORT_OFFSET_si = 4203,
4219 : BUFFER_LOAD_SSHORT_OFFSET_vi = 4204,
4220 : BUFFER_LOAD_UBYTE_ADDR64_si = 4205,
4221 : BUFFER_LOAD_UBYTE_BOTHEN_si = 4206,
4222 : BUFFER_LOAD_UBYTE_BOTHEN_vi = 4207,
4223 : BUFFER_LOAD_UBYTE_D16_BOTHEN_vi = 4208,
4224 : BUFFER_LOAD_UBYTE_D16_HI_BOTHEN_vi = 4209,
4225 : BUFFER_LOAD_UBYTE_D16_HI_IDXEN_vi = 4210,
4226 : BUFFER_LOAD_UBYTE_D16_HI_OFFEN_vi = 4211,
4227 : BUFFER_LOAD_UBYTE_D16_HI_OFFSET_vi = 4212,
4228 : BUFFER_LOAD_UBYTE_D16_IDXEN_vi = 4213,
4229 : BUFFER_LOAD_UBYTE_D16_OFFEN_vi = 4214,
4230 : BUFFER_LOAD_UBYTE_D16_OFFSET_vi = 4215,
4231 : BUFFER_LOAD_UBYTE_IDXEN_si = 4216,
4232 : BUFFER_LOAD_UBYTE_IDXEN_vi = 4217,
4233 : BUFFER_LOAD_UBYTE_LDS_ADDR64_si = 4218,
4234 : BUFFER_LOAD_UBYTE_LDS_BOTHEN_si = 4219,
4235 : BUFFER_LOAD_UBYTE_LDS_BOTHEN_vi = 4220,
4236 : BUFFER_LOAD_UBYTE_LDS_IDXEN_si = 4221,
4237 : BUFFER_LOAD_UBYTE_LDS_IDXEN_vi = 4222,
4238 : BUFFER_LOAD_UBYTE_LDS_OFFEN_si = 4223,
4239 : BUFFER_LOAD_UBYTE_LDS_OFFEN_vi = 4224,
4240 : BUFFER_LOAD_UBYTE_LDS_OFFSET_si = 4225,
4241 : BUFFER_LOAD_UBYTE_LDS_OFFSET_vi = 4226,
4242 : BUFFER_LOAD_UBYTE_OFFEN_si = 4227,
4243 : BUFFER_LOAD_UBYTE_OFFEN_vi = 4228,
4244 : BUFFER_LOAD_UBYTE_OFFSET_si = 4229,
4245 : BUFFER_LOAD_UBYTE_OFFSET_vi = 4230,
4246 : BUFFER_LOAD_USHORT_ADDR64_si = 4231,
4247 : BUFFER_LOAD_USHORT_BOTHEN_si = 4232,
4248 : BUFFER_LOAD_USHORT_BOTHEN_vi = 4233,
4249 : BUFFER_LOAD_USHORT_IDXEN_si = 4234,
4250 : BUFFER_LOAD_USHORT_IDXEN_vi = 4235,
4251 : BUFFER_LOAD_USHORT_LDS_ADDR64_si = 4236,
4252 : BUFFER_LOAD_USHORT_LDS_BOTHEN_si = 4237,
4253 : BUFFER_LOAD_USHORT_LDS_BOTHEN_vi = 4238,
4254 : BUFFER_LOAD_USHORT_LDS_IDXEN_si = 4239,
4255 : BUFFER_LOAD_USHORT_LDS_IDXEN_vi = 4240,
4256 : BUFFER_LOAD_USHORT_LDS_OFFEN_si = 4241,
4257 : BUFFER_LOAD_USHORT_LDS_OFFEN_vi = 4242,
4258 : BUFFER_LOAD_USHORT_LDS_OFFSET_si = 4243,
4259 : BUFFER_LOAD_USHORT_LDS_OFFSET_vi = 4244,
4260 : BUFFER_LOAD_USHORT_OFFEN_si = 4245,
4261 : BUFFER_LOAD_USHORT_OFFEN_vi = 4246,
4262 : BUFFER_LOAD_USHORT_OFFSET_si = 4247,
4263 : BUFFER_LOAD_USHORT_OFFSET_vi = 4248,
4264 : BUFFER_STORE_BYTE_ADDR64_si = 4249,
4265 : BUFFER_STORE_BYTE_BOTHEN_si = 4250,
4266 : BUFFER_STORE_BYTE_BOTHEN_vi = 4251,
4267 : BUFFER_STORE_BYTE_D16_HI_BOTHEN_vi = 4252,
4268 : BUFFER_STORE_BYTE_D16_HI_IDXEN_vi = 4253,
4269 : BUFFER_STORE_BYTE_D16_HI_OFFEN_vi = 4254,
4270 : BUFFER_STORE_BYTE_D16_HI_OFFSET_vi = 4255,
4271 : BUFFER_STORE_BYTE_IDXEN_si = 4256,
4272 : BUFFER_STORE_BYTE_IDXEN_vi = 4257,
4273 : BUFFER_STORE_BYTE_OFFEN_si = 4258,
4274 : BUFFER_STORE_BYTE_OFFEN_vi = 4259,
4275 : BUFFER_STORE_BYTE_OFFSET_si = 4260,
4276 : BUFFER_STORE_BYTE_OFFSET_vi = 4261,
4277 : BUFFER_STORE_DWORDX2_ADDR64_si = 4262,
4278 : BUFFER_STORE_DWORDX2_BOTHEN_si = 4263,
4279 : BUFFER_STORE_DWORDX2_BOTHEN_vi = 4264,
4280 : BUFFER_STORE_DWORDX2_IDXEN_si = 4265,
4281 : BUFFER_STORE_DWORDX2_IDXEN_vi = 4266,
4282 : BUFFER_STORE_DWORDX2_OFFEN_si = 4267,
4283 : BUFFER_STORE_DWORDX2_OFFEN_vi = 4268,
4284 : BUFFER_STORE_DWORDX2_OFFSET_si = 4269,
4285 : BUFFER_STORE_DWORDX2_OFFSET_vi = 4270,
4286 : BUFFER_STORE_DWORDX3_ADDR64_si = 4271,
4287 : BUFFER_STORE_DWORDX3_BOTHEN_si = 4272,
4288 : BUFFER_STORE_DWORDX3_BOTHEN_vi = 4273,
4289 : BUFFER_STORE_DWORDX3_IDXEN_si = 4274,
4290 : BUFFER_STORE_DWORDX3_IDXEN_vi = 4275,
4291 : BUFFER_STORE_DWORDX3_OFFEN_si = 4276,
4292 : BUFFER_STORE_DWORDX3_OFFEN_vi = 4277,
4293 : BUFFER_STORE_DWORDX3_OFFSET_si = 4278,
4294 : BUFFER_STORE_DWORDX3_OFFSET_vi = 4279,
4295 : BUFFER_STORE_DWORDX4_ADDR64_si = 4280,
4296 : BUFFER_STORE_DWORDX4_BOTHEN_si = 4281,
4297 : BUFFER_STORE_DWORDX4_BOTHEN_vi = 4282,
4298 : BUFFER_STORE_DWORDX4_IDXEN_si = 4283,
4299 : BUFFER_STORE_DWORDX4_IDXEN_vi = 4284,
4300 : BUFFER_STORE_DWORDX4_OFFEN_si = 4285,
4301 : BUFFER_STORE_DWORDX4_OFFEN_vi = 4286,
4302 : BUFFER_STORE_DWORDX4_OFFSET_si = 4287,
4303 : BUFFER_STORE_DWORDX4_OFFSET_vi = 4288,
4304 : BUFFER_STORE_DWORD_ADDR64_si = 4289,
4305 : BUFFER_STORE_DWORD_BOTHEN_si = 4290,
4306 : BUFFER_STORE_DWORD_BOTHEN_vi = 4291,
4307 : BUFFER_STORE_DWORD_IDXEN_si = 4292,
4308 : BUFFER_STORE_DWORD_IDXEN_vi = 4293,
4309 : BUFFER_STORE_DWORD_OFFEN_si = 4294,
4310 : BUFFER_STORE_DWORD_OFFEN_vi = 4295,
4311 : BUFFER_STORE_DWORD_OFFSET_si = 4296,
4312 : BUFFER_STORE_DWORD_OFFSET_vi = 4297,
4313 : BUFFER_STORE_FORMAT_D16_HI_X_BOTHEN_vi = 4298,
4314 : BUFFER_STORE_FORMAT_D16_HI_X_IDXEN_vi = 4299,
4315 : BUFFER_STORE_FORMAT_D16_HI_X_OFFEN_vi = 4300,
4316 : BUFFER_STORE_FORMAT_D16_HI_X_OFFSET_vi = 4301,
4317 : BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi = 4302,
4318 : BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi = 4303,
4319 : BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi = 4304,
4320 : BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi = 4305,
4321 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80 = 4306,
4322 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80 = 4307,
4323 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80 = 4308,
4324 : BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80 = 4309,
4325 : BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi = 4310,
4326 : BUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi = 4311,
4327 : BUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi = 4312,
4328 : BUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi = 4313,
4329 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80 = 4314,
4330 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80 = 4315,
4331 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80 = 4316,
4332 : BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80 = 4317,
4333 : BUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi = 4318,
4334 : BUFFER_STORE_FORMAT_D16_XY_IDXEN_vi = 4319,
4335 : BUFFER_STORE_FORMAT_D16_XY_OFFEN_vi = 4320,
4336 : BUFFER_STORE_FORMAT_D16_XY_OFFSET_vi = 4321,
4337 : BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80 = 4322,
4338 : BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80 = 4323,
4339 : BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80 = 4324,
4340 : BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80 = 4325,
4341 : BUFFER_STORE_FORMAT_D16_X_BOTHEN_vi = 4326,
4342 : BUFFER_STORE_FORMAT_D16_X_IDXEN_vi = 4327,
4343 : BUFFER_STORE_FORMAT_D16_X_OFFEN_vi = 4328,
4344 : BUFFER_STORE_FORMAT_D16_X_OFFSET_vi = 4329,
4345 : BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80 = 4330,
4346 : BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80 = 4331,
4347 : BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80 = 4332,
4348 : BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80 = 4333,
4349 : BUFFER_STORE_FORMAT_XYZW_ADDR64_si = 4334,
4350 : BUFFER_STORE_FORMAT_XYZW_BOTHEN_si = 4335,
4351 : BUFFER_STORE_FORMAT_XYZW_BOTHEN_vi = 4336,
4352 : BUFFER_STORE_FORMAT_XYZW_IDXEN_si = 4337,
4353 : BUFFER_STORE_FORMAT_XYZW_IDXEN_vi = 4338,
4354 : BUFFER_STORE_FORMAT_XYZW_OFFEN_si = 4339,
4355 : BUFFER_STORE_FORMAT_XYZW_OFFEN_vi = 4340,
4356 : BUFFER_STORE_FORMAT_XYZW_OFFSET_si = 4341,
4357 : BUFFER_STORE_FORMAT_XYZW_OFFSET_vi = 4342,
4358 : BUFFER_STORE_FORMAT_XYZ_ADDR64_si = 4343,
4359 : BUFFER_STORE_FORMAT_XYZ_BOTHEN_si = 4344,
4360 : BUFFER_STORE_FORMAT_XYZ_BOTHEN_vi = 4345,
4361 : BUFFER_STORE_FORMAT_XYZ_IDXEN_si = 4346,
4362 : BUFFER_STORE_FORMAT_XYZ_IDXEN_vi = 4347,
4363 : BUFFER_STORE_FORMAT_XYZ_OFFEN_si = 4348,
4364 : BUFFER_STORE_FORMAT_XYZ_OFFEN_vi = 4349,
4365 : BUFFER_STORE_FORMAT_XYZ_OFFSET_si = 4350,
4366 : BUFFER_STORE_FORMAT_XYZ_OFFSET_vi = 4351,
4367 : BUFFER_STORE_FORMAT_XY_ADDR64_si = 4352,
4368 : BUFFER_STORE_FORMAT_XY_BOTHEN_si = 4353,
4369 : BUFFER_STORE_FORMAT_XY_BOTHEN_vi = 4354,
4370 : BUFFER_STORE_FORMAT_XY_IDXEN_si = 4355,
4371 : BUFFER_STORE_FORMAT_XY_IDXEN_vi = 4356,
4372 : BUFFER_STORE_FORMAT_XY_OFFEN_si = 4357,
4373 : BUFFER_STORE_FORMAT_XY_OFFEN_vi = 4358,
4374 : BUFFER_STORE_FORMAT_XY_OFFSET_si = 4359,
4375 : BUFFER_STORE_FORMAT_XY_OFFSET_vi = 4360,
4376 : BUFFER_STORE_FORMAT_X_ADDR64_si = 4361,
4377 : BUFFER_STORE_FORMAT_X_BOTHEN_si = 4362,
4378 : BUFFER_STORE_FORMAT_X_BOTHEN_vi = 4363,
4379 : BUFFER_STORE_FORMAT_X_IDXEN_si = 4364,
4380 : BUFFER_STORE_FORMAT_X_IDXEN_vi = 4365,
4381 : BUFFER_STORE_FORMAT_X_OFFEN_si = 4366,
4382 : BUFFER_STORE_FORMAT_X_OFFEN_vi = 4367,
4383 : BUFFER_STORE_FORMAT_X_OFFSET_si = 4368,
4384 : BUFFER_STORE_FORMAT_X_OFFSET_vi = 4369,
4385 : BUFFER_STORE_LDS_DWORD_vi = 4370,
4386 : BUFFER_STORE_SHORT_ADDR64_si = 4371,
4387 : BUFFER_STORE_SHORT_BOTHEN_si = 4372,
4388 : BUFFER_STORE_SHORT_BOTHEN_vi = 4373,
4389 : BUFFER_STORE_SHORT_D16_HI_BOTHEN_vi = 4374,
4390 : BUFFER_STORE_SHORT_D16_HI_IDXEN_vi = 4375,
4391 : BUFFER_STORE_SHORT_D16_HI_OFFEN_vi = 4376,
4392 : BUFFER_STORE_SHORT_D16_HI_OFFSET_vi = 4377,
4393 : BUFFER_STORE_SHORT_IDXEN_si = 4378,
4394 : BUFFER_STORE_SHORT_IDXEN_vi = 4379,
4395 : BUFFER_STORE_SHORT_OFFEN_si = 4380,
4396 : BUFFER_STORE_SHORT_OFFEN_vi = 4381,
4397 : BUFFER_STORE_SHORT_OFFSET_si = 4382,
4398 : BUFFER_STORE_SHORT_OFFSET_vi = 4383,
4399 : BUFFER_WBINVL1_SC_si = 4384,
4400 : BUFFER_WBINVL1_VOL_ci = 4385,
4401 : BUFFER_WBINVL1_VOL_vi = 4386,
4402 : BUFFER_WBINVL1_si = 4387,
4403 : BUFFER_WBINVL1_vi = 4388,
4404 : DS_ADD_F32_vi = 4389,
4405 : DS_ADD_RTN_F32_vi = 4390,
4406 : DS_ADD_RTN_U32_si = 4391,
4407 : DS_ADD_RTN_U32_vi = 4392,
4408 : DS_ADD_RTN_U64_si = 4393,
4409 : DS_ADD_RTN_U64_vi = 4394,
4410 : DS_ADD_SRC2_F32_vi = 4395,
4411 : DS_ADD_SRC2_U32_si = 4396,
4412 : DS_ADD_SRC2_U32_vi = 4397,
4413 : DS_ADD_SRC2_U64_si = 4398,
4414 : DS_ADD_SRC2_U64_vi = 4399,
4415 : DS_ADD_U32_si = 4400,
4416 : DS_ADD_U32_vi = 4401,
4417 : DS_ADD_U64_si = 4402,
4418 : DS_ADD_U64_vi = 4403,
4419 : DS_AND_B32_si = 4404,
4420 : DS_AND_B32_vi = 4405,
4421 : DS_AND_B64_si = 4406,
4422 : DS_AND_B64_vi = 4407,
4423 : DS_AND_RTN_B32_si = 4408,
4424 : DS_AND_RTN_B32_vi = 4409,
4425 : DS_AND_RTN_B64_si = 4410,
4426 : DS_AND_RTN_B64_vi = 4411,
4427 : DS_AND_SRC2_B32_si = 4412,
4428 : DS_AND_SRC2_B32_vi = 4413,
4429 : DS_AND_SRC2_B64_si = 4414,
4430 : DS_AND_SRC2_B64_vi = 4415,
4431 : DS_APPEND_si = 4416,
4432 : DS_APPEND_vi = 4417,
4433 : DS_BPERMUTE_B32_vi = 4418,
4434 : DS_CMPST_B32_si = 4419,
4435 : DS_CMPST_B32_vi = 4420,
4436 : DS_CMPST_B64_si = 4421,
4437 : DS_CMPST_B64_vi = 4422,
4438 : DS_CMPST_F32_si = 4423,
4439 : DS_CMPST_F32_vi = 4424,
4440 : DS_CMPST_F64_si = 4425,
4441 : DS_CMPST_F64_vi = 4426,
4442 : DS_CMPST_RTN_B32_si = 4427,
4443 : DS_CMPST_RTN_B32_vi = 4428,
4444 : DS_CMPST_RTN_B64_si = 4429,
4445 : DS_CMPST_RTN_B64_vi = 4430,
4446 : DS_CMPST_RTN_F32_si = 4431,
4447 : DS_CMPST_RTN_F32_vi = 4432,
4448 : DS_CMPST_RTN_F64_si = 4433,
4449 : DS_CMPST_RTN_F64_vi = 4434,
4450 : DS_CONDXCHG32_RTN_B64_si = 4435,
4451 : DS_CONDXCHG32_RTN_B64_vi = 4436,
4452 : DS_CONSUME_si = 4437,
4453 : DS_CONSUME_vi = 4438,
4454 : DS_DEC_RTN_U32_si = 4439,
4455 : DS_DEC_RTN_U32_vi = 4440,
4456 : DS_DEC_RTN_U64_si = 4441,
4457 : DS_DEC_RTN_U64_vi = 4442,
4458 : DS_DEC_SRC2_U32_si = 4443,
4459 : DS_DEC_SRC2_U32_vi = 4444,
4460 : DS_DEC_SRC2_U64_si = 4445,
4461 : DS_DEC_SRC2_U64_vi = 4446,
4462 : DS_DEC_U32_si = 4447,
4463 : DS_DEC_U32_vi = 4448,
4464 : DS_DEC_U64_si = 4449,
4465 : DS_DEC_U64_vi = 4450,
4466 : DS_GWS_BARRIER_si = 4451,
4467 : DS_GWS_BARRIER_vi = 4452,
4468 : DS_GWS_INIT_si = 4453,
4469 : DS_GWS_INIT_vi = 4454,
4470 : DS_GWS_SEMA_BR_si = 4455,
4471 : DS_GWS_SEMA_BR_vi = 4456,
4472 : DS_GWS_SEMA_P_si = 4457,
4473 : DS_GWS_SEMA_P_vi = 4458,
4474 : DS_GWS_SEMA_RELEASE_ALL_si = 4459,
4475 : DS_GWS_SEMA_RELEASE_ALL_vi = 4460,
4476 : DS_GWS_SEMA_V_si = 4461,
4477 : DS_GWS_SEMA_V_vi = 4462,
4478 : DS_INC_RTN_U32_si = 4463,
4479 : DS_INC_RTN_U32_vi = 4464,
4480 : DS_INC_RTN_U64_si = 4465,
4481 : DS_INC_RTN_U64_vi = 4466,
4482 : DS_INC_SRC2_U32_si = 4467,
4483 : DS_INC_SRC2_U32_vi = 4468,
4484 : DS_INC_SRC2_U64_si = 4469,
4485 : DS_INC_SRC2_U64_vi = 4470,
4486 : DS_INC_U32_si = 4471,
4487 : DS_INC_U32_vi = 4472,
4488 : DS_INC_U64_si = 4473,
4489 : DS_INC_U64_vi = 4474,
4490 : DS_MAX_F32_si = 4475,
4491 : DS_MAX_F32_vi = 4476,
4492 : DS_MAX_F64_si = 4477,
4493 : DS_MAX_F64_vi = 4478,
4494 : DS_MAX_I32_si = 4479,
4495 : DS_MAX_I32_vi = 4480,
4496 : DS_MAX_I64_si = 4481,
4497 : DS_MAX_I64_vi = 4482,
4498 : DS_MAX_RTN_F32_si = 4483,
4499 : DS_MAX_RTN_F32_vi = 4484,
4500 : DS_MAX_RTN_F64_si = 4485,
4501 : DS_MAX_RTN_F64_vi = 4486,
4502 : DS_MAX_RTN_I32_si = 4487,
4503 : DS_MAX_RTN_I32_vi = 4488,
4504 : DS_MAX_RTN_I64_si = 4489,
4505 : DS_MAX_RTN_I64_vi = 4490,
4506 : DS_MAX_RTN_U32_si = 4491,
4507 : DS_MAX_RTN_U32_vi = 4492,
4508 : DS_MAX_RTN_U64_si = 4493,
4509 : DS_MAX_RTN_U64_vi = 4494,
4510 : DS_MAX_SRC2_F32_si = 4495,
4511 : DS_MAX_SRC2_F32_vi = 4496,
4512 : DS_MAX_SRC2_F64_si = 4497,
4513 : DS_MAX_SRC2_F64_vi = 4498,
4514 : DS_MAX_SRC2_I32_si = 4499,
4515 : DS_MAX_SRC2_I32_vi = 4500,
4516 : DS_MAX_SRC2_I64_si = 4501,
4517 : DS_MAX_SRC2_I64_vi = 4502,
4518 : DS_MAX_SRC2_U32_si = 4503,
4519 : DS_MAX_SRC2_U32_vi = 4504,
4520 : DS_MAX_SRC2_U64_si = 4505,
4521 : DS_MAX_SRC2_U64_vi = 4506,
4522 : DS_MAX_U32_si = 4507,
4523 : DS_MAX_U32_vi = 4508,
4524 : DS_MAX_U64_si = 4509,
4525 : DS_MAX_U64_vi = 4510,
4526 : DS_MIN_F32_si = 4511,
4527 : DS_MIN_F32_vi = 4512,
4528 : DS_MIN_F64_si = 4513,
4529 : DS_MIN_F64_vi = 4514,
4530 : DS_MIN_I32_si = 4515,
4531 : DS_MIN_I32_vi = 4516,
4532 : DS_MIN_I64_si = 4517,
4533 : DS_MIN_I64_vi = 4518,
4534 : DS_MIN_RTN_F32_si = 4519,
4535 : DS_MIN_RTN_F32_vi = 4520,
4536 : DS_MIN_RTN_F64_si = 4521,
4537 : DS_MIN_RTN_F64_vi = 4522,
4538 : DS_MIN_RTN_I32_si = 4523,
4539 : DS_MIN_RTN_I32_vi = 4524,
4540 : DS_MIN_RTN_I64_si = 4525,
4541 : DS_MIN_RTN_I64_vi = 4526,
4542 : DS_MIN_RTN_U32_si = 4527,
4543 : DS_MIN_RTN_U32_vi = 4528,
4544 : DS_MIN_RTN_U64_si = 4529,
4545 : DS_MIN_RTN_U64_vi = 4530,
4546 : DS_MIN_SRC2_F32_si = 4531,
4547 : DS_MIN_SRC2_F32_vi = 4532,
4548 : DS_MIN_SRC2_F64_si = 4533,
4549 : DS_MIN_SRC2_F64_vi = 4534,
4550 : DS_MIN_SRC2_I32_si = 4535,
4551 : DS_MIN_SRC2_I32_vi = 4536,
4552 : DS_MIN_SRC2_I64_si = 4537,
4553 : DS_MIN_SRC2_I64_vi = 4538,
4554 : DS_MIN_SRC2_U32_si = 4539,
4555 : DS_MIN_SRC2_U32_vi = 4540,
4556 : DS_MIN_SRC2_U64_si = 4541,
4557 : DS_MIN_SRC2_U64_vi = 4542,
4558 : DS_MIN_U32_si = 4543,
4559 : DS_MIN_U32_vi = 4544,
4560 : DS_MIN_U64_si = 4545,
4561 : DS_MIN_U64_vi = 4546,
4562 : DS_MSKOR_B32_si = 4547,
4563 : DS_MSKOR_B32_vi = 4548,
4564 : DS_MSKOR_B64_si = 4549,
4565 : DS_MSKOR_B64_vi = 4550,
4566 : DS_MSKOR_RTN_B32_si = 4551,
4567 : DS_MSKOR_RTN_B32_vi = 4552,
4568 : DS_MSKOR_RTN_B64_si = 4553,
4569 : DS_MSKOR_RTN_B64_vi = 4554,
4570 : DS_NOP_si = 4555,
4571 : DS_NOP_vi = 4556,
4572 : DS_ORDERED_COUNT_si = 4557,
4573 : DS_ORDERED_COUNT_vi = 4558,
4574 : DS_OR_B32_si = 4559,
4575 : DS_OR_B32_vi = 4560,
4576 : DS_OR_B64_si = 4561,
4577 : DS_OR_B64_vi = 4562,
4578 : DS_OR_RTN_B32_si = 4563,
4579 : DS_OR_RTN_B32_vi = 4564,
4580 : DS_OR_RTN_B64_si = 4565,
4581 : DS_OR_RTN_B64_vi = 4566,
4582 : DS_OR_SRC2_B32_si = 4567,
4583 : DS_OR_SRC2_B32_vi = 4568,
4584 : DS_OR_SRC2_B64_si = 4569,
4585 : DS_OR_SRC2_B64_vi = 4570,
4586 : DS_PERMUTE_B32_vi = 4571,
4587 : DS_READ2ST64_B32_si = 4572,
4588 : DS_READ2ST64_B32_vi = 4573,
4589 : DS_READ2ST64_B64_si = 4574,
4590 : DS_READ2ST64_B64_vi = 4575,
4591 : DS_READ2_B32_si = 4576,
4592 : DS_READ2_B32_vi = 4577,
4593 : DS_READ2_B64_si = 4578,
4594 : DS_READ2_B64_vi = 4579,
4595 : DS_READ_ADDTID_B32_vi = 4580,
4596 : DS_READ_B128_si = 4581,
4597 : DS_READ_B128_vi = 4582,
4598 : DS_READ_B32_si = 4583,
4599 : DS_READ_B32_vi = 4584,
4600 : DS_READ_B64_si = 4585,
4601 : DS_READ_B64_vi = 4586,
4602 : DS_READ_B96_si = 4587,
4603 : DS_READ_B96_vi = 4588,
4604 : DS_READ_I16_si = 4589,
4605 : DS_READ_I16_vi = 4590,
4606 : DS_READ_I8_D16_HI_vi = 4591,
4607 : DS_READ_I8_D16_vi = 4592,
4608 : DS_READ_I8_si = 4593,
4609 : DS_READ_I8_vi = 4594,
4610 : DS_READ_U16_D16_HI_vi = 4595,
4611 : DS_READ_U16_D16_vi = 4596,
4612 : DS_READ_U16_si = 4597,
4613 : DS_READ_U16_vi = 4598,
4614 : DS_READ_U8_D16_HI_vi = 4599,
4615 : DS_READ_U8_D16_vi = 4600,
4616 : DS_READ_U8_si = 4601,
4617 : DS_READ_U8_vi = 4602,
4618 : DS_RSUB_RTN_U32_si = 4603,
4619 : DS_RSUB_RTN_U32_vi = 4604,
4620 : DS_RSUB_RTN_U64_si = 4605,
4621 : DS_RSUB_RTN_U64_vi = 4606,
4622 : DS_RSUB_SRC2_U32_si = 4607,
4623 : DS_RSUB_SRC2_U32_vi = 4608,
4624 : DS_RSUB_SRC2_U64_si = 4609,
4625 : DS_RSUB_SRC2_U64_vi = 4610,
4626 : DS_RSUB_U32_si = 4611,
4627 : DS_RSUB_U32_vi = 4612,
4628 : DS_RSUB_U64_si = 4613,
4629 : DS_RSUB_U64_vi = 4614,
4630 : DS_SUB_RTN_U32_si = 4615,
4631 : DS_SUB_RTN_U32_vi = 4616,
4632 : DS_SUB_RTN_U64_si = 4617,
4633 : DS_SUB_RTN_U64_vi = 4618,
4634 : DS_SUB_SRC2_U32_si = 4619,
4635 : DS_SUB_SRC2_U32_vi = 4620,
4636 : DS_SUB_SRC2_U64_si = 4621,
4637 : DS_SUB_SRC2_U64_vi = 4622,
4638 : DS_SUB_U32_si = 4623,
4639 : DS_SUB_U32_vi = 4624,
4640 : DS_SUB_U64_si = 4625,
4641 : DS_SUB_U64_vi = 4626,
4642 : DS_SWIZZLE_B32_si = 4627,
4643 : DS_SWIZZLE_B32_vi = 4628,
4644 : DS_WRAP_RTN_B32_si = 4629,
4645 : DS_WRAP_RTN_B32_vi = 4630,
4646 : DS_WRITE2ST64_B32_si = 4631,
4647 : DS_WRITE2ST64_B32_vi = 4632,
4648 : DS_WRITE2ST64_B64_si = 4633,
4649 : DS_WRITE2ST64_B64_vi = 4634,
4650 : DS_WRITE2_B32_si = 4635,
4651 : DS_WRITE2_B32_vi = 4636,
4652 : DS_WRITE2_B64_si = 4637,
4653 : DS_WRITE2_B64_vi = 4638,
4654 : DS_WRITE_ADDTID_B32_vi = 4639,
4655 : DS_WRITE_B128_si = 4640,
4656 : DS_WRITE_B128_vi = 4641,
4657 : DS_WRITE_B16_D16_HI_vi = 4642,
4658 : DS_WRITE_B16_si = 4643,
4659 : DS_WRITE_B16_vi = 4644,
4660 : DS_WRITE_B32_si = 4645,
4661 : DS_WRITE_B32_vi = 4646,
4662 : DS_WRITE_B64_si = 4647,
4663 : DS_WRITE_B64_vi = 4648,
4664 : DS_WRITE_B8_D16_HI_vi = 4649,
4665 : DS_WRITE_B8_si = 4650,
4666 : DS_WRITE_B8_vi = 4651,
4667 : DS_WRITE_B96_si = 4652,
4668 : DS_WRITE_B96_vi = 4653,
4669 : DS_WRITE_SRC2_B32_si = 4654,
4670 : DS_WRITE_SRC2_B32_vi = 4655,
4671 : DS_WRITE_SRC2_B64_si = 4656,
4672 : DS_WRITE_SRC2_B64_vi = 4657,
4673 : DS_WRXCHG2ST64_RTN_B32_si = 4658,
4674 : DS_WRXCHG2ST64_RTN_B32_vi = 4659,
4675 : DS_WRXCHG2ST64_RTN_B64_si = 4660,
4676 : DS_WRXCHG2ST64_RTN_B64_vi = 4661,
4677 : DS_WRXCHG2_RTN_B32_si = 4662,
4678 : DS_WRXCHG2_RTN_B32_vi = 4663,
4679 : DS_WRXCHG2_RTN_B64_si = 4664,
4680 : DS_WRXCHG2_RTN_B64_vi = 4665,
4681 : DS_WRXCHG_RTN_B32_si = 4666,
4682 : DS_WRXCHG_RTN_B32_vi = 4667,
4683 : DS_WRXCHG_RTN_B64_si = 4668,
4684 : DS_WRXCHG_RTN_B64_vi = 4669,
4685 : DS_XOR_B32_si = 4670,
4686 : DS_XOR_B32_vi = 4671,
4687 : DS_XOR_B64_si = 4672,
4688 : DS_XOR_B64_vi = 4673,
4689 : DS_XOR_RTN_B32_si = 4674,
4690 : DS_XOR_RTN_B32_vi = 4675,
4691 : DS_XOR_RTN_B64_si = 4676,
4692 : DS_XOR_RTN_B64_vi = 4677,
4693 : DS_XOR_SRC2_B32_si = 4678,
4694 : DS_XOR_SRC2_B32_vi = 4679,
4695 : DS_XOR_SRC2_B64_si = 4680,
4696 : DS_XOR_SRC2_B64_vi = 4681,
4697 : EXP_DONE_si = 4682,
4698 : EXP_DONE_vi = 4683,
4699 : EXP_si = 4684,
4700 : EXP_vi = 4685,
4701 : FLAT_ATOMIC_ADD_RTN_ci = 4686,
4702 : FLAT_ATOMIC_ADD_RTN_vi = 4687,
4703 : FLAT_ATOMIC_ADD_X2_RTN_ci = 4688,
4704 : FLAT_ATOMIC_ADD_X2_RTN_vi = 4689,
4705 : FLAT_ATOMIC_ADD_X2_ci = 4690,
4706 : FLAT_ATOMIC_ADD_X2_vi = 4691,
4707 : FLAT_ATOMIC_ADD_ci = 4692,
4708 : FLAT_ATOMIC_ADD_vi = 4693,
4709 : FLAT_ATOMIC_AND_RTN_ci = 4694,
4710 : FLAT_ATOMIC_AND_RTN_vi = 4695,
4711 : FLAT_ATOMIC_AND_X2_RTN_ci = 4696,
4712 : FLAT_ATOMIC_AND_X2_RTN_vi = 4697,
4713 : FLAT_ATOMIC_AND_X2_ci = 4698,
4714 : FLAT_ATOMIC_AND_X2_vi = 4699,
4715 : FLAT_ATOMIC_AND_ci = 4700,
4716 : FLAT_ATOMIC_AND_vi = 4701,
4717 : FLAT_ATOMIC_CMPSWAP_RTN_ci = 4702,
4718 : FLAT_ATOMIC_CMPSWAP_RTN_vi = 4703,
4719 : FLAT_ATOMIC_CMPSWAP_X2_RTN_ci = 4704,
4720 : FLAT_ATOMIC_CMPSWAP_X2_RTN_vi = 4705,
4721 : FLAT_ATOMIC_CMPSWAP_X2_ci = 4706,
4722 : FLAT_ATOMIC_CMPSWAP_X2_vi = 4707,
4723 : FLAT_ATOMIC_CMPSWAP_ci = 4708,
4724 : FLAT_ATOMIC_CMPSWAP_vi = 4709,
4725 : FLAT_ATOMIC_DEC_RTN_ci = 4710,
4726 : FLAT_ATOMIC_DEC_RTN_vi = 4711,
4727 : FLAT_ATOMIC_DEC_X2_RTN_ci = 4712,
4728 : FLAT_ATOMIC_DEC_X2_RTN_vi = 4713,
4729 : FLAT_ATOMIC_DEC_X2_ci = 4714,
4730 : FLAT_ATOMIC_DEC_X2_vi = 4715,
4731 : FLAT_ATOMIC_DEC_ci = 4716,
4732 : FLAT_ATOMIC_DEC_vi = 4717,
4733 : FLAT_ATOMIC_FCMPSWAP_RTN_ci = 4718,
4734 : FLAT_ATOMIC_FCMPSWAP_X2_RTN_ci = 4719,
4735 : FLAT_ATOMIC_FCMPSWAP_X2_ci = 4720,
4736 : FLAT_ATOMIC_FCMPSWAP_ci = 4721,
4737 : FLAT_ATOMIC_FMAX_RTN_ci = 4722,
4738 : FLAT_ATOMIC_FMAX_X2_RTN_ci = 4723,
4739 : FLAT_ATOMIC_FMAX_X2_ci = 4724,
4740 : FLAT_ATOMIC_FMAX_ci = 4725,
4741 : FLAT_ATOMIC_FMIN_RTN_ci = 4726,
4742 : FLAT_ATOMIC_FMIN_X2_RTN_ci = 4727,
4743 : FLAT_ATOMIC_FMIN_X2_ci = 4728,
4744 : FLAT_ATOMIC_FMIN_ci = 4729,
4745 : FLAT_ATOMIC_INC_RTN_ci = 4730,
4746 : FLAT_ATOMIC_INC_RTN_vi = 4731,
4747 : FLAT_ATOMIC_INC_X2_RTN_ci = 4732,
4748 : FLAT_ATOMIC_INC_X2_RTN_vi = 4733,
4749 : FLAT_ATOMIC_INC_X2_ci = 4734,
4750 : FLAT_ATOMIC_INC_X2_vi = 4735,
4751 : FLAT_ATOMIC_INC_ci = 4736,
4752 : FLAT_ATOMIC_INC_vi = 4737,
4753 : FLAT_ATOMIC_OR_RTN_ci = 4738,
4754 : FLAT_ATOMIC_OR_RTN_vi = 4739,
4755 : FLAT_ATOMIC_OR_X2_RTN_ci = 4740,
4756 : FLAT_ATOMIC_OR_X2_RTN_vi = 4741,
4757 : FLAT_ATOMIC_OR_X2_ci = 4742,
4758 : FLAT_ATOMIC_OR_X2_vi = 4743,
4759 : FLAT_ATOMIC_OR_ci = 4744,
4760 : FLAT_ATOMIC_OR_vi = 4745,
4761 : FLAT_ATOMIC_SMAX_RTN_ci = 4746,
4762 : FLAT_ATOMIC_SMAX_RTN_vi = 4747,
4763 : FLAT_ATOMIC_SMAX_X2_RTN_ci = 4748,
4764 : FLAT_ATOMIC_SMAX_X2_RTN_vi = 4749,
4765 : FLAT_ATOMIC_SMAX_X2_ci = 4750,
4766 : FLAT_ATOMIC_SMAX_X2_vi = 4751,
4767 : FLAT_ATOMIC_SMAX_ci = 4752,
4768 : FLAT_ATOMIC_SMAX_vi = 4753,
4769 : FLAT_ATOMIC_SMIN_RTN_ci = 4754,
4770 : FLAT_ATOMIC_SMIN_RTN_vi = 4755,
4771 : FLAT_ATOMIC_SMIN_X2_RTN_ci = 4756,
4772 : FLAT_ATOMIC_SMIN_X2_RTN_vi = 4757,
4773 : FLAT_ATOMIC_SMIN_X2_ci = 4758,
4774 : FLAT_ATOMIC_SMIN_X2_vi = 4759,
4775 : FLAT_ATOMIC_SMIN_ci = 4760,
4776 : FLAT_ATOMIC_SMIN_vi = 4761,
4777 : FLAT_ATOMIC_SUB_RTN_ci = 4762,
4778 : FLAT_ATOMIC_SUB_RTN_vi = 4763,
4779 : FLAT_ATOMIC_SUB_X2_RTN_ci = 4764,
4780 : FLAT_ATOMIC_SUB_X2_RTN_vi = 4765,
4781 : FLAT_ATOMIC_SUB_X2_ci = 4766,
4782 : FLAT_ATOMIC_SUB_X2_vi = 4767,
4783 : FLAT_ATOMIC_SUB_ci = 4768,
4784 : FLAT_ATOMIC_SUB_vi = 4769,
4785 : FLAT_ATOMIC_SWAP_RTN_ci = 4770,
4786 : FLAT_ATOMIC_SWAP_RTN_vi = 4771,
4787 : FLAT_ATOMIC_SWAP_X2_RTN_ci = 4772,
4788 : FLAT_ATOMIC_SWAP_X2_RTN_vi = 4773,
4789 : FLAT_ATOMIC_SWAP_X2_ci = 4774,
4790 : FLAT_ATOMIC_SWAP_X2_vi = 4775,
4791 : FLAT_ATOMIC_SWAP_ci = 4776,
4792 : FLAT_ATOMIC_SWAP_vi = 4777,
4793 : FLAT_ATOMIC_UMAX_RTN_ci = 4778,
4794 : FLAT_ATOMIC_UMAX_RTN_vi = 4779,
4795 : FLAT_ATOMIC_UMAX_X2_RTN_ci = 4780,
4796 : FLAT_ATOMIC_UMAX_X2_RTN_vi = 4781,
4797 : FLAT_ATOMIC_UMAX_X2_ci = 4782,
4798 : FLAT_ATOMIC_UMAX_X2_vi = 4783,
4799 : FLAT_ATOMIC_UMAX_ci = 4784,
4800 : FLAT_ATOMIC_UMAX_vi = 4785,
4801 : FLAT_ATOMIC_UMIN_RTN_ci = 4786,
4802 : FLAT_ATOMIC_UMIN_RTN_vi = 4787,
4803 : FLAT_ATOMIC_UMIN_X2_RTN_ci = 4788,
4804 : FLAT_ATOMIC_UMIN_X2_RTN_vi = 4789,
4805 : FLAT_ATOMIC_UMIN_X2_ci = 4790,
4806 : FLAT_ATOMIC_UMIN_X2_vi = 4791,
4807 : FLAT_ATOMIC_UMIN_ci = 4792,
4808 : FLAT_ATOMIC_UMIN_vi = 4793,
4809 : FLAT_ATOMIC_XOR_RTN_ci = 4794,
4810 : FLAT_ATOMIC_XOR_RTN_vi = 4795,
4811 : FLAT_ATOMIC_XOR_X2_RTN_ci = 4796,
4812 : FLAT_ATOMIC_XOR_X2_RTN_vi = 4797,
4813 : FLAT_ATOMIC_XOR_X2_ci = 4798,
4814 : FLAT_ATOMIC_XOR_X2_vi = 4799,
4815 : FLAT_ATOMIC_XOR_ci = 4800,
4816 : FLAT_ATOMIC_XOR_vi = 4801,
4817 : FLAT_LOAD_DWORDX2_ci = 4802,
4818 : FLAT_LOAD_DWORDX2_vi = 4803,
4819 : FLAT_LOAD_DWORDX3_ci = 4804,
4820 : FLAT_LOAD_DWORDX3_vi = 4805,
4821 : FLAT_LOAD_DWORDX4_ci = 4806,
4822 : FLAT_LOAD_DWORDX4_vi = 4807,
4823 : FLAT_LOAD_DWORD_ci = 4808,
4824 : FLAT_LOAD_DWORD_vi = 4809,
4825 : FLAT_LOAD_SBYTE_D16_HI_vi = 4810,
4826 : FLAT_LOAD_SBYTE_D16_vi = 4811,
4827 : FLAT_LOAD_SBYTE_ci = 4812,
4828 : FLAT_LOAD_SBYTE_vi = 4813,
4829 : FLAT_LOAD_SHORT_D16_HI_vi = 4814,
4830 : FLAT_LOAD_SHORT_D16_vi = 4815,
4831 : FLAT_LOAD_SSHORT_ci = 4816,
4832 : FLAT_LOAD_SSHORT_vi = 4817,
4833 : FLAT_LOAD_UBYTE_D16_HI_vi = 4818,
4834 : FLAT_LOAD_UBYTE_D16_vi = 4819,
4835 : FLAT_LOAD_UBYTE_ci = 4820,
4836 : FLAT_LOAD_UBYTE_vi = 4821,
4837 : FLAT_LOAD_USHORT_ci = 4822,
4838 : FLAT_LOAD_USHORT_vi = 4823,
4839 : FLAT_STORE_BYTE_D16_HI_vi = 4824,
4840 : FLAT_STORE_BYTE_ci = 4825,
4841 : FLAT_STORE_BYTE_vi = 4826,
4842 : FLAT_STORE_DWORDX2_ci = 4827,
4843 : FLAT_STORE_DWORDX2_vi = 4828,
4844 : FLAT_STORE_DWORDX3_ci = 4829,
4845 : FLAT_STORE_DWORDX3_vi = 4830,
4846 : FLAT_STORE_DWORDX4_ci = 4831,
4847 : FLAT_STORE_DWORDX4_vi = 4832,
4848 : FLAT_STORE_DWORD_ci = 4833,
4849 : FLAT_STORE_DWORD_vi = 4834,
4850 : FLAT_STORE_SHORT_D16_HI_vi = 4835,
4851 : FLAT_STORE_SHORT_ci = 4836,
4852 : FLAT_STORE_SHORT_vi = 4837,
4853 : GLOBAL_ATOMIC_ADD_RTN_vi = 4838,
4854 : GLOBAL_ATOMIC_ADD_SADDR_RTN_vi = 4839,
4855 : GLOBAL_ATOMIC_ADD_SADDR_vi = 4840,
4856 : GLOBAL_ATOMIC_ADD_X2_RTN_vi = 4841,
4857 : GLOBAL_ATOMIC_ADD_X2_SADDR_RTN_vi = 4842,
4858 : GLOBAL_ATOMIC_ADD_X2_SADDR_vi = 4843,
4859 : GLOBAL_ATOMIC_ADD_X2_vi = 4844,
4860 : GLOBAL_ATOMIC_ADD_vi = 4845,
4861 : GLOBAL_ATOMIC_AND_RTN_vi = 4846,
4862 : GLOBAL_ATOMIC_AND_SADDR_RTN_vi = 4847,
4863 : GLOBAL_ATOMIC_AND_SADDR_vi = 4848,
4864 : GLOBAL_ATOMIC_AND_X2_RTN_vi = 4849,
4865 : GLOBAL_ATOMIC_AND_X2_SADDR_RTN_vi = 4850,
4866 : GLOBAL_ATOMIC_AND_X2_SADDR_vi = 4851,
4867 : GLOBAL_ATOMIC_AND_X2_vi = 4852,
4868 : GLOBAL_ATOMIC_AND_vi = 4853,
4869 : GLOBAL_ATOMIC_CMPSWAP_RTN_vi = 4854,
4870 : GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN_vi = 4855,
4871 : GLOBAL_ATOMIC_CMPSWAP_SADDR_vi = 4856,
4872 : GLOBAL_ATOMIC_CMPSWAP_X2_RTN_vi = 4857,
4873 : GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN_vi = 4858,
4874 : GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_vi = 4859,
4875 : GLOBAL_ATOMIC_CMPSWAP_X2_vi = 4860,
4876 : GLOBAL_ATOMIC_CMPSWAP_vi = 4861,
4877 : GLOBAL_ATOMIC_DEC_RTN_vi = 4862,
4878 : GLOBAL_ATOMIC_DEC_SADDR_RTN_vi = 4863,
4879 : GLOBAL_ATOMIC_DEC_SADDR_vi = 4864,
4880 : GLOBAL_ATOMIC_DEC_X2_RTN_vi = 4865,
4881 : GLOBAL_ATOMIC_DEC_X2_SADDR_RTN_vi = 4866,
4882 : GLOBAL_ATOMIC_DEC_X2_SADDR_vi = 4867,
4883 : GLOBAL_ATOMIC_DEC_X2_vi = 4868,
4884 : GLOBAL_ATOMIC_DEC_vi = 4869,
4885 : GLOBAL_ATOMIC_INC_RTN_vi = 4870,
4886 : GLOBAL_ATOMIC_INC_SADDR_RTN_vi = 4871,
4887 : GLOBAL_ATOMIC_INC_SADDR_vi = 4872,
4888 : GLOBAL_ATOMIC_INC_X2_RTN_vi = 4873,
4889 : GLOBAL_ATOMIC_INC_X2_SADDR_RTN_vi = 4874,
4890 : GLOBAL_ATOMIC_INC_X2_SADDR_vi = 4875,
4891 : GLOBAL_ATOMIC_INC_X2_vi = 4876,
4892 : GLOBAL_ATOMIC_INC_vi = 4877,
4893 : GLOBAL_ATOMIC_OR_RTN_vi = 4878,
4894 : GLOBAL_ATOMIC_OR_SADDR_RTN_vi = 4879,
4895 : GLOBAL_ATOMIC_OR_SADDR_vi = 4880,
4896 : GLOBAL_ATOMIC_OR_X2_RTN_vi = 4881,
4897 : GLOBAL_ATOMIC_OR_X2_SADDR_RTN_vi = 4882,
4898 : GLOBAL_ATOMIC_OR_X2_SADDR_vi = 4883,
4899 : GLOBAL_ATOMIC_OR_X2_vi = 4884,
4900 : GLOBAL_ATOMIC_OR_vi = 4885,
4901 : GLOBAL_ATOMIC_SMAX_RTN_vi = 4886,
4902 : GLOBAL_ATOMIC_SMAX_SADDR_RTN_vi = 4887,
4903 : GLOBAL_ATOMIC_SMAX_SADDR_vi = 4888,
4904 : GLOBAL_ATOMIC_SMAX_X2_RTN_vi = 4889,
4905 : GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN_vi = 4890,
4906 : GLOBAL_ATOMIC_SMAX_X2_SADDR_vi = 4891,
4907 : GLOBAL_ATOMIC_SMAX_X2_vi = 4892,
4908 : GLOBAL_ATOMIC_SMAX_vi = 4893,
4909 : GLOBAL_ATOMIC_SMIN_RTN_vi = 4894,
4910 : GLOBAL_ATOMIC_SMIN_SADDR_RTN_vi = 4895,
4911 : GLOBAL_ATOMIC_SMIN_SADDR_vi = 4896,
4912 : GLOBAL_ATOMIC_SMIN_X2_RTN_vi = 4897,
4913 : GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN_vi = 4898,
4914 : GLOBAL_ATOMIC_SMIN_X2_SADDR_vi = 4899,
4915 : GLOBAL_ATOMIC_SMIN_X2_vi = 4900,
4916 : GLOBAL_ATOMIC_SMIN_vi = 4901,
4917 : GLOBAL_ATOMIC_SUB_RTN_vi = 4902,
4918 : GLOBAL_ATOMIC_SUB_SADDR_RTN_vi = 4903,
4919 : GLOBAL_ATOMIC_SUB_SADDR_vi = 4904,
4920 : GLOBAL_ATOMIC_SUB_X2_RTN_vi = 4905,
4921 : GLOBAL_ATOMIC_SUB_X2_SADDR_RTN_vi = 4906,
4922 : GLOBAL_ATOMIC_SUB_X2_SADDR_vi = 4907,
4923 : GLOBAL_ATOMIC_SUB_X2_vi = 4908,
4924 : GLOBAL_ATOMIC_SUB_vi = 4909,
4925 : GLOBAL_ATOMIC_SWAP_RTN_vi = 4910,
4926 : GLOBAL_ATOMIC_SWAP_SADDR_RTN_vi = 4911,
4927 : GLOBAL_ATOMIC_SWAP_SADDR_vi = 4912,
4928 : GLOBAL_ATOMIC_SWAP_X2_RTN_vi = 4913,
4929 : GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN_vi = 4914,
4930 : GLOBAL_ATOMIC_SWAP_X2_SADDR_vi = 4915,
4931 : GLOBAL_ATOMIC_SWAP_X2_vi = 4916,
4932 : GLOBAL_ATOMIC_SWAP_vi = 4917,
4933 : GLOBAL_ATOMIC_UMAX_RTN_vi = 4918,
4934 : GLOBAL_ATOMIC_UMAX_SADDR_RTN_vi = 4919,
4935 : GLOBAL_ATOMIC_UMAX_SADDR_vi = 4920,
4936 : GLOBAL_ATOMIC_UMAX_X2_RTN_vi = 4921,
4937 : GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN_vi = 4922,
4938 : GLOBAL_ATOMIC_UMAX_X2_SADDR_vi = 4923,
4939 : GLOBAL_ATOMIC_UMAX_X2_vi = 4924,
4940 : GLOBAL_ATOMIC_UMAX_vi = 4925,
4941 : GLOBAL_ATOMIC_UMIN_RTN_vi = 4926,
4942 : GLOBAL_ATOMIC_UMIN_SADDR_RTN_vi = 4927,
4943 : GLOBAL_ATOMIC_UMIN_SADDR_vi = 4928,
4944 : GLOBAL_ATOMIC_UMIN_X2_RTN_vi = 4929,
4945 : GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN_vi = 4930,
4946 : GLOBAL_ATOMIC_UMIN_X2_SADDR_vi = 4931,
4947 : GLOBAL_ATOMIC_UMIN_X2_vi = 4932,
4948 : GLOBAL_ATOMIC_UMIN_vi = 4933,
4949 : GLOBAL_ATOMIC_XOR_RTN_vi = 4934,
4950 : GLOBAL_ATOMIC_XOR_SADDR_RTN_vi = 4935,
4951 : GLOBAL_ATOMIC_XOR_SADDR_vi = 4936,
4952 : GLOBAL_ATOMIC_XOR_X2_RTN_vi = 4937,
4953 : GLOBAL_ATOMIC_XOR_X2_SADDR_RTN_vi = 4938,
4954 : GLOBAL_ATOMIC_XOR_X2_SADDR_vi = 4939,
4955 : GLOBAL_ATOMIC_XOR_X2_vi = 4940,
4956 : GLOBAL_ATOMIC_XOR_vi = 4941,
4957 : GLOBAL_LOAD_DWORDX2_SADDR_vi = 4942,
4958 : GLOBAL_LOAD_DWORDX2_vi = 4943,
4959 : GLOBAL_LOAD_DWORDX3_SADDR_vi = 4944,
4960 : GLOBAL_LOAD_DWORDX3_vi = 4945,
4961 : GLOBAL_LOAD_DWORDX4_SADDR_vi = 4946,
4962 : GLOBAL_LOAD_DWORDX4_vi = 4947,
4963 : GLOBAL_LOAD_DWORD_SADDR_vi = 4948,
4964 : GLOBAL_LOAD_DWORD_vi = 4949,
4965 : GLOBAL_LOAD_SBYTE_D16_HI_SADDR_vi = 4950,
4966 : GLOBAL_LOAD_SBYTE_D16_HI_vi = 4951,
4967 : GLOBAL_LOAD_SBYTE_D16_SADDR_vi = 4952,
4968 : GLOBAL_LOAD_SBYTE_D16_vi = 4953,
4969 : GLOBAL_LOAD_SBYTE_SADDR_vi = 4954,
4970 : GLOBAL_LOAD_SBYTE_vi = 4955,
4971 : GLOBAL_LOAD_SHORT_D16_HI_SADDR_vi = 4956,
4972 : GLOBAL_LOAD_SHORT_D16_HI_vi = 4957,
4973 : GLOBAL_LOAD_SHORT_D16_SADDR_vi = 4958,
4974 : GLOBAL_LOAD_SHORT_D16_vi = 4959,
4975 : GLOBAL_LOAD_SSHORT_SADDR_vi = 4960,
4976 : GLOBAL_LOAD_SSHORT_vi = 4961,
4977 : GLOBAL_LOAD_UBYTE_D16_HI_SADDR_vi = 4962,
4978 : GLOBAL_LOAD_UBYTE_D16_HI_vi = 4963,
4979 : GLOBAL_LOAD_UBYTE_D16_SADDR_vi = 4964,
4980 : GLOBAL_LOAD_UBYTE_D16_vi = 4965,
4981 : GLOBAL_LOAD_UBYTE_SADDR_vi = 4966,
4982 : GLOBAL_LOAD_UBYTE_vi = 4967,
4983 : GLOBAL_LOAD_USHORT_SADDR_vi = 4968,
4984 : GLOBAL_LOAD_USHORT_vi = 4969,
4985 : GLOBAL_STORE_BYTE_D16_HI_SADDR_vi = 4970,
4986 : GLOBAL_STORE_BYTE_D16_HI_vi = 4971,
4987 : GLOBAL_STORE_BYTE_SADDR_vi = 4972,
4988 : GLOBAL_STORE_BYTE_vi = 4973,
4989 : GLOBAL_STORE_DWORDX2_SADDR_vi = 4974,
4990 : GLOBAL_STORE_DWORDX2_vi = 4975,
4991 : GLOBAL_STORE_DWORDX3_SADDR_vi = 4976,
4992 : GLOBAL_STORE_DWORDX3_vi = 4977,
4993 : GLOBAL_STORE_DWORDX4_SADDR_vi = 4978,
4994 : GLOBAL_STORE_DWORDX4_vi = 4979,
4995 : GLOBAL_STORE_DWORD_SADDR_vi = 4980,
4996 : GLOBAL_STORE_DWORD_vi = 4981,
4997 : GLOBAL_STORE_SHORT_D16_HI_SADDR_vi = 4982,
4998 : GLOBAL_STORE_SHORT_D16_HI_vi = 4983,
4999 : GLOBAL_STORE_SHORT_SADDR_vi = 4984,
5000 : GLOBAL_STORE_SHORT_vi = 4985,
5001 : IMAGE_ATOMIC_ADD_V1_V1_si = 4986,
5002 : IMAGE_ATOMIC_ADD_V1_V1_vi = 4987,
5003 : IMAGE_ATOMIC_ADD_V1_V2_si = 4988,
5004 : IMAGE_ATOMIC_ADD_V1_V2_vi = 4989,
5005 : IMAGE_ATOMIC_ADD_V1_V3_si = 4990,
5006 : IMAGE_ATOMIC_ADD_V1_V3_vi = 4991,
5007 : IMAGE_ATOMIC_ADD_V1_V4_si = 4992,
5008 : IMAGE_ATOMIC_ADD_V1_V4_vi = 4993,
5009 : IMAGE_ATOMIC_ADD_V2_V1_si = 4994,
5010 : IMAGE_ATOMIC_ADD_V2_V1_vi = 4995,
5011 : IMAGE_ATOMIC_ADD_V2_V2_si = 4996,
5012 : IMAGE_ATOMIC_ADD_V2_V2_vi = 4997,
5013 : IMAGE_ATOMIC_ADD_V2_V3_si = 4998,
5014 : IMAGE_ATOMIC_ADD_V2_V3_vi = 4999,
5015 : IMAGE_ATOMIC_ADD_V2_V4_si = 5000,
5016 : IMAGE_ATOMIC_ADD_V2_V4_vi = 5001,
5017 : IMAGE_ATOMIC_AND_V1_V1_si = 5002,
5018 : IMAGE_ATOMIC_AND_V1_V1_vi = 5003,
5019 : IMAGE_ATOMIC_AND_V1_V2_si = 5004,
5020 : IMAGE_ATOMIC_AND_V1_V2_vi = 5005,
5021 : IMAGE_ATOMIC_AND_V1_V3_si = 5006,
5022 : IMAGE_ATOMIC_AND_V1_V3_vi = 5007,
5023 : IMAGE_ATOMIC_AND_V1_V4_si = 5008,
5024 : IMAGE_ATOMIC_AND_V1_V4_vi = 5009,
5025 : IMAGE_ATOMIC_AND_V2_V1_si = 5010,
5026 : IMAGE_ATOMIC_AND_V2_V1_vi = 5011,
5027 : IMAGE_ATOMIC_AND_V2_V2_si = 5012,
5028 : IMAGE_ATOMIC_AND_V2_V2_vi = 5013,
5029 : IMAGE_ATOMIC_AND_V2_V3_si = 5014,
5030 : IMAGE_ATOMIC_AND_V2_V3_vi = 5015,
5031 : IMAGE_ATOMIC_AND_V2_V4_si = 5016,
5032 : IMAGE_ATOMIC_AND_V2_V4_vi = 5017,
5033 : IMAGE_ATOMIC_CMPSWAP_V1_V1_si = 5018,
5034 : IMAGE_ATOMIC_CMPSWAP_V1_V1_vi = 5019,
5035 : IMAGE_ATOMIC_CMPSWAP_V1_V2_si = 5020,
5036 : IMAGE_ATOMIC_CMPSWAP_V1_V2_vi = 5021,
5037 : IMAGE_ATOMIC_CMPSWAP_V1_V3_si = 5022,
5038 : IMAGE_ATOMIC_CMPSWAP_V1_V3_vi = 5023,
5039 : IMAGE_ATOMIC_CMPSWAP_V1_V4_si = 5024,
5040 : IMAGE_ATOMIC_CMPSWAP_V1_V4_vi = 5025,
5041 : IMAGE_ATOMIC_CMPSWAP_V2_V1_si = 5026,
5042 : IMAGE_ATOMIC_CMPSWAP_V2_V1_vi = 5027,
5043 : IMAGE_ATOMIC_CMPSWAP_V2_V2_si = 5028,
5044 : IMAGE_ATOMIC_CMPSWAP_V2_V2_vi = 5029,
5045 : IMAGE_ATOMIC_CMPSWAP_V2_V3_si = 5030,
5046 : IMAGE_ATOMIC_CMPSWAP_V2_V3_vi = 5031,
5047 : IMAGE_ATOMIC_CMPSWAP_V2_V4_si = 5032,
5048 : IMAGE_ATOMIC_CMPSWAP_V2_V4_vi = 5033,
5049 : IMAGE_ATOMIC_DEC_V1_V1_si = 5034,
5050 : IMAGE_ATOMIC_DEC_V1_V1_vi = 5035,
5051 : IMAGE_ATOMIC_DEC_V1_V2_si = 5036,
5052 : IMAGE_ATOMIC_DEC_V1_V2_vi = 5037,
5053 : IMAGE_ATOMIC_DEC_V1_V3_si = 5038,
5054 : IMAGE_ATOMIC_DEC_V1_V3_vi = 5039,
5055 : IMAGE_ATOMIC_DEC_V1_V4_si = 5040,
5056 : IMAGE_ATOMIC_DEC_V1_V4_vi = 5041,
5057 : IMAGE_ATOMIC_DEC_V2_V1_si = 5042,
5058 : IMAGE_ATOMIC_DEC_V2_V1_vi = 5043,
5059 : IMAGE_ATOMIC_DEC_V2_V2_si = 5044,
5060 : IMAGE_ATOMIC_DEC_V2_V2_vi = 5045,
5061 : IMAGE_ATOMIC_DEC_V2_V3_si = 5046,
5062 : IMAGE_ATOMIC_DEC_V2_V3_vi = 5047,
5063 : IMAGE_ATOMIC_DEC_V2_V4_si = 5048,
5064 : IMAGE_ATOMIC_DEC_V2_V4_vi = 5049,
5065 : IMAGE_ATOMIC_INC_V1_V1_si = 5050,
5066 : IMAGE_ATOMIC_INC_V1_V1_vi = 5051,
5067 : IMAGE_ATOMIC_INC_V1_V2_si = 5052,
5068 : IMAGE_ATOMIC_INC_V1_V2_vi = 5053,
5069 : IMAGE_ATOMIC_INC_V1_V3_si = 5054,
5070 : IMAGE_ATOMIC_INC_V1_V3_vi = 5055,
5071 : IMAGE_ATOMIC_INC_V1_V4_si = 5056,
5072 : IMAGE_ATOMIC_INC_V1_V4_vi = 5057,
5073 : IMAGE_ATOMIC_INC_V2_V1_si = 5058,
5074 : IMAGE_ATOMIC_INC_V2_V1_vi = 5059,
5075 : IMAGE_ATOMIC_INC_V2_V2_si = 5060,
5076 : IMAGE_ATOMIC_INC_V2_V2_vi = 5061,
5077 : IMAGE_ATOMIC_INC_V2_V3_si = 5062,
5078 : IMAGE_ATOMIC_INC_V2_V3_vi = 5063,
5079 : IMAGE_ATOMIC_INC_V2_V4_si = 5064,
5080 : IMAGE_ATOMIC_INC_V2_V4_vi = 5065,
5081 : IMAGE_ATOMIC_OR_V1_V1_si = 5066,
5082 : IMAGE_ATOMIC_OR_V1_V1_vi = 5067,
5083 : IMAGE_ATOMIC_OR_V1_V2_si = 5068,
5084 : IMAGE_ATOMIC_OR_V1_V2_vi = 5069,
5085 : IMAGE_ATOMIC_OR_V1_V3_si = 5070,
5086 : IMAGE_ATOMIC_OR_V1_V3_vi = 5071,
5087 : IMAGE_ATOMIC_OR_V1_V4_si = 5072,
5088 : IMAGE_ATOMIC_OR_V1_V4_vi = 5073,
5089 : IMAGE_ATOMIC_OR_V2_V1_si = 5074,
5090 : IMAGE_ATOMIC_OR_V2_V1_vi = 5075,
5091 : IMAGE_ATOMIC_OR_V2_V2_si = 5076,
5092 : IMAGE_ATOMIC_OR_V2_V2_vi = 5077,
5093 : IMAGE_ATOMIC_OR_V2_V3_si = 5078,
5094 : IMAGE_ATOMIC_OR_V2_V3_vi = 5079,
5095 : IMAGE_ATOMIC_OR_V2_V4_si = 5080,
5096 : IMAGE_ATOMIC_OR_V2_V4_vi = 5081,
5097 : IMAGE_ATOMIC_SMAX_V1_V1_si = 5082,
5098 : IMAGE_ATOMIC_SMAX_V1_V1_vi = 5083,
5099 : IMAGE_ATOMIC_SMAX_V1_V2_si = 5084,
5100 : IMAGE_ATOMIC_SMAX_V1_V2_vi = 5085,
5101 : IMAGE_ATOMIC_SMAX_V1_V3_si = 5086,
5102 : IMAGE_ATOMIC_SMAX_V1_V3_vi = 5087,
5103 : IMAGE_ATOMIC_SMAX_V1_V4_si = 5088,
5104 : IMAGE_ATOMIC_SMAX_V1_V4_vi = 5089,
5105 : IMAGE_ATOMIC_SMAX_V2_V1_si = 5090,
5106 : IMAGE_ATOMIC_SMAX_V2_V1_vi = 5091,
5107 : IMAGE_ATOMIC_SMAX_V2_V2_si = 5092,
5108 : IMAGE_ATOMIC_SMAX_V2_V2_vi = 5093,
5109 : IMAGE_ATOMIC_SMAX_V2_V3_si = 5094,
5110 : IMAGE_ATOMIC_SMAX_V2_V3_vi = 5095,
5111 : IMAGE_ATOMIC_SMAX_V2_V4_si = 5096,
5112 : IMAGE_ATOMIC_SMAX_V2_V4_vi = 5097,
5113 : IMAGE_ATOMIC_SMIN_V1_V1_si = 5098,
5114 : IMAGE_ATOMIC_SMIN_V1_V1_vi = 5099,
5115 : IMAGE_ATOMIC_SMIN_V1_V2_si = 5100,
5116 : IMAGE_ATOMIC_SMIN_V1_V2_vi = 5101,
5117 : IMAGE_ATOMIC_SMIN_V1_V3_si = 5102,
5118 : IMAGE_ATOMIC_SMIN_V1_V3_vi = 5103,
5119 : IMAGE_ATOMIC_SMIN_V1_V4_si = 5104,
5120 : IMAGE_ATOMIC_SMIN_V1_V4_vi = 5105,
5121 : IMAGE_ATOMIC_SMIN_V2_V1_si = 5106,
5122 : IMAGE_ATOMIC_SMIN_V2_V1_vi = 5107,
5123 : IMAGE_ATOMIC_SMIN_V2_V2_si = 5108,
5124 : IMAGE_ATOMIC_SMIN_V2_V2_vi = 5109,
5125 : IMAGE_ATOMIC_SMIN_V2_V3_si = 5110,
5126 : IMAGE_ATOMIC_SMIN_V2_V3_vi = 5111,
5127 : IMAGE_ATOMIC_SMIN_V2_V4_si = 5112,
5128 : IMAGE_ATOMIC_SMIN_V2_V4_vi = 5113,
5129 : IMAGE_ATOMIC_SUB_V1_V1_si = 5114,
5130 : IMAGE_ATOMIC_SUB_V1_V1_vi = 5115,
5131 : IMAGE_ATOMIC_SUB_V1_V2_si = 5116,
5132 : IMAGE_ATOMIC_SUB_V1_V2_vi = 5117,
5133 : IMAGE_ATOMIC_SUB_V1_V3_si = 5118,
5134 : IMAGE_ATOMIC_SUB_V1_V3_vi = 5119,
5135 : IMAGE_ATOMIC_SUB_V1_V4_si = 5120,
5136 : IMAGE_ATOMIC_SUB_V1_V4_vi = 5121,
5137 : IMAGE_ATOMIC_SUB_V2_V1_si = 5122,
5138 : IMAGE_ATOMIC_SUB_V2_V1_vi = 5123,
5139 : IMAGE_ATOMIC_SUB_V2_V2_si = 5124,
5140 : IMAGE_ATOMIC_SUB_V2_V2_vi = 5125,
5141 : IMAGE_ATOMIC_SUB_V2_V3_si = 5126,
5142 : IMAGE_ATOMIC_SUB_V2_V3_vi = 5127,
5143 : IMAGE_ATOMIC_SUB_V2_V4_si = 5128,
5144 : IMAGE_ATOMIC_SUB_V2_V4_vi = 5129,
5145 : IMAGE_ATOMIC_SWAP_V1_V1_si = 5130,
5146 : IMAGE_ATOMIC_SWAP_V1_V1_vi = 5131,
5147 : IMAGE_ATOMIC_SWAP_V1_V2_si = 5132,
5148 : IMAGE_ATOMIC_SWAP_V1_V2_vi = 5133,
5149 : IMAGE_ATOMIC_SWAP_V1_V3_si = 5134,
5150 : IMAGE_ATOMIC_SWAP_V1_V3_vi = 5135,
5151 : IMAGE_ATOMIC_SWAP_V1_V4_si = 5136,
5152 : IMAGE_ATOMIC_SWAP_V1_V4_vi = 5137,
5153 : IMAGE_ATOMIC_SWAP_V2_V1_si = 5138,
5154 : IMAGE_ATOMIC_SWAP_V2_V1_vi = 5139,
5155 : IMAGE_ATOMIC_SWAP_V2_V2_si = 5140,
5156 : IMAGE_ATOMIC_SWAP_V2_V2_vi = 5141,
5157 : IMAGE_ATOMIC_SWAP_V2_V3_si = 5142,
5158 : IMAGE_ATOMIC_SWAP_V2_V3_vi = 5143,
5159 : IMAGE_ATOMIC_SWAP_V2_V4_si = 5144,
5160 : IMAGE_ATOMIC_SWAP_V2_V4_vi = 5145,
5161 : IMAGE_ATOMIC_UMAX_V1_V1_si = 5146,
5162 : IMAGE_ATOMIC_UMAX_V1_V1_vi = 5147,
5163 : IMAGE_ATOMIC_UMAX_V1_V2_si = 5148,
5164 : IMAGE_ATOMIC_UMAX_V1_V2_vi = 5149,
5165 : IMAGE_ATOMIC_UMAX_V1_V3_si = 5150,
5166 : IMAGE_ATOMIC_UMAX_V1_V3_vi = 5151,
5167 : IMAGE_ATOMIC_UMAX_V1_V4_si = 5152,
5168 : IMAGE_ATOMIC_UMAX_V1_V4_vi = 5153,
5169 : IMAGE_ATOMIC_UMAX_V2_V1_si = 5154,
5170 : IMAGE_ATOMIC_UMAX_V2_V1_vi = 5155,
5171 : IMAGE_ATOMIC_UMAX_V2_V2_si = 5156,
5172 : IMAGE_ATOMIC_UMAX_V2_V2_vi = 5157,
5173 : IMAGE_ATOMIC_UMAX_V2_V3_si = 5158,
5174 : IMAGE_ATOMIC_UMAX_V2_V3_vi = 5159,
5175 : IMAGE_ATOMIC_UMAX_V2_V4_si = 5160,
5176 : IMAGE_ATOMIC_UMAX_V2_V4_vi = 5161,
5177 : IMAGE_ATOMIC_UMIN_V1_V1_si = 5162,
5178 : IMAGE_ATOMIC_UMIN_V1_V1_vi = 5163,
5179 : IMAGE_ATOMIC_UMIN_V1_V2_si = 5164,
5180 : IMAGE_ATOMIC_UMIN_V1_V2_vi = 5165,
5181 : IMAGE_ATOMIC_UMIN_V1_V3_si = 5166,
5182 : IMAGE_ATOMIC_UMIN_V1_V3_vi = 5167,
5183 : IMAGE_ATOMIC_UMIN_V1_V4_si = 5168,
5184 : IMAGE_ATOMIC_UMIN_V1_V4_vi = 5169,
5185 : IMAGE_ATOMIC_UMIN_V2_V1_si = 5170,
5186 : IMAGE_ATOMIC_UMIN_V2_V1_vi = 5171,
5187 : IMAGE_ATOMIC_UMIN_V2_V2_si = 5172,
5188 : IMAGE_ATOMIC_UMIN_V2_V2_vi = 5173,
5189 : IMAGE_ATOMIC_UMIN_V2_V3_si = 5174,
5190 : IMAGE_ATOMIC_UMIN_V2_V3_vi = 5175,
5191 : IMAGE_ATOMIC_UMIN_V2_V4_si = 5176,
5192 : IMAGE_ATOMIC_UMIN_V2_V4_vi = 5177,
5193 : IMAGE_ATOMIC_XOR_V1_V1_si = 5178,
5194 : IMAGE_ATOMIC_XOR_V1_V1_vi = 5179,
5195 : IMAGE_ATOMIC_XOR_V1_V2_si = 5180,
5196 : IMAGE_ATOMIC_XOR_V1_V2_vi = 5181,
5197 : IMAGE_ATOMIC_XOR_V1_V3_si = 5182,
5198 : IMAGE_ATOMIC_XOR_V1_V3_vi = 5183,
5199 : IMAGE_ATOMIC_XOR_V1_V4_si = 5184,
5200 : IMAGE_ATOMIC_XOR_V1_V4_vi = 5185,
5201 : IMAGE_ATOMIC_XOR_V2_V1_si = 5186,
5202 : IMAGE_ATOMIC_XOR_V2_V1_vi = 5187,
5203 : IMAGE_ATOMIC_XOR_V2_V2_si = 5188,
5204 : IMAGE_ATOMIC_XOR_V2_V2_vi = 5189,
5205 : IMAGE_ATOMIC_XOR_V2_V3_si = 5190,
5206 : IMAGE_ATOMIC_XOR_V2_V3_vi = 5191,
5207 : IMAGE_ATOMIC_XOR_V2_V4_si = 5192,
5208 : IMAGE_ATOMIC_XOR_V2_V4_vi = 5193,
5209 : IMAGE_GATHER4_B_CL_O_V2_V3 = 5194,
5210 : IMAGE_GATHER4_B_CL_O_V2_V4 = 5195,
5211 : IMAGE_GATHER4_B_CL_O_V2_V8 = 5196,
5212 : IMAGE_GATHER4_B_CL_O_V4_V3 = 5197,
5213 : IMAGE_GATHER4_B_CL_O_V4_V4 = 5198,
5214 : IMAGE_GATHER4_B_CL_O_V4_V8 = 5199,
5215 : IMAGE_GATHER4_B_CL_V2_V2 = 5200,
5216 : IMAGE_GATHER4_B_CL_V2_V3 = 5201,
5217 : IMAGE_GATHER4_B_CL_V2_V4 = 5202,
5218 : IMAGE_GATHER4_B_CL_V2_V8 = 5203,
5219 : IMAGE_GATHER4_B_CL_V4_V2 = 5204,
5220 : IMAGE_GATHER4_B_CL_V4_V3 = 5205,
5221 : IMAGE_GATHER4_B_CL_V4_V4 = 5206,
5222 : IMAGE_GATHER4_B_CL_V4_V8 = 5207,
5223 : IMAGE_GATHER4_B_O_V2_V3 = 5208,
5224 : IMAGE_GATHER4_B_O_V2_V4 = 5209,
5225 : IMAGE_GATHER4_B_O_V2_V8 = 5210,
5226 : IMAGE_GATHER4_B_O_V4_V3 = 5211,
5227 : IMAGE_GATHER4_B_O_V4_V4 = 5212,
5228 : IMAGE_GATHER4_B_O_V4_V8 = 5213,
5229 : IMAGE_GATHER4_B_V2_V2 = 5214,
5230 : IMAGE_GATHER4_B_V2_V3 = 5215,
5231 : IMAGE_GATHER4_B_V2_V4 = 5216,
5232 : IMAGE_GATHER4_B_V4_V2 = 5217,
5233 : IMAGE_GATHER4_B_V4_V3 = 5218,
5234 : IMAGE_GATHER4_B_V4_V4 = 5219,
5235 : IMAGE_GATHER4_CL_O_V2_V2 = 5220,
5236 : IMAGE_GATHER4_CL_O_V2_V3 = 5221,
5237 : IMAGE_GATHER4_CL_O_V2_V4 = 5222,
5238 : IMAGE_GATHER4_CL_O_V2_V8 = 5223,
5239 : IMAGE_GATHER4_CL_O_V4_V2 = 5224,
5240 : IMAGE_GATHER4_CL_O_V4_V3 = 5225,
5241 : IMAGE_GATHER4_CL_O_V4_V4 = 5226,
5242 : IMAGE_GATHER4_CL_O_V4_V8 = 5227,
5243 : IMAGE_GATHER4_CL_V2_V1 = 5228,
5244 : IMAGE_GATHER4_CL_V2_V2 = 5229,
5245 : IMAGE_GATHER4_CL_V2_V3 = 5230,
5246 : IMAGE_GATHER4_CL_V2_V4 = 5231,
5247 : IMAGE_GATHER4_CL_V4_V1 = 5232,
5248 : IMAGE_GATHER4_CL_V4_V2 = 5233,
5249 : IMAGE_GATHER4_CL_V4_V3 = 5234,
5250 : IMAGE_GATHER4_CL_V4_V4 = 5235,
5251 : IMAGE_GATHER4_C_B_CL_O_V2_V4 = 5236,
5252 : IMAGE_GATHER4_C_B_CL_O_V2_V8 = 5237,
5253 : IMAGE_GATHER4_C_B_CL_O_V4_V4 = 5238,
5254 : IMAGE_GATHER4_C_B_CL_O_V4_V8 = 5239,
5255 : IMAGE_GATHER4_C_B_CL_V2_V3 = 5240,
5256 : IMAGE_GATHER4_C_B_CL_V2_V4 = 5241,
5257 : IMAGE_GATHER4_C_B_CL_V2_V8 = 5242,
5258 : IMAGE_GATHER4_C_B_CL_V4_V3 = 5243,
5259 : IMAGE_GATHER4_C_B_CL_V4_V4 = 5244,
5260 : IMAGE_GATHER4_C_B_CL_V4_V8 = 5245,
5261 : IMAGE_GATHER4_C_B_O_V2_V4 = 5246,
5262 : IMAGE_GATHER4_C_B_O_V2_V8 = 5247,
5263 : IMAGE_GATHER4_C_B_O_V4_V4 = 5248,
5264 : IMAGE_GATHER4_C_B_O_V4_V8 = 5249,
5265 : IMAGE_GATHER4_C_B_V2_V3 = 5250,
5266 : IMAGE_GATHER4_C_B_V2_V4 = 5251,
5267 : IMAGE_GATHER4_C_B_V2_V8 = 5252,
5268 : IMAGE_GATHER4_C_B_V4_V3 = 5253,
5269 : IMAGE_GATHER4_C_B_V4_V4 = 5254,
5270 : IMAGE_GATHER4_C_B_V4_V8 = 5255,
5271 : IMAGE_GATHER4_C_CL_O_V2_V3 = 5256,
5272 : IMAGE_GATHER4_C_CL_O_V2_V4 = 5257,
5273 : IMAGE_GATHER4_C_CL_O_V2_V8 = 5258,
5274 : IMAGE_GATHER4_C_CL_O_V4_V3 = 5259,
5275 : IMAGE_GATHER4_C_CL_O_V4_V4 = 5260,
5276 : IMAGE_GATHER4_C_CL_O_V4_V8 = 5261,
5277 : IMAGE_GATHER4_C_CL_V2_V2 = 5262,
5278 : IMAGE_GATHER4_C_CL_V2_V3 = 5263,
5279 : IMAGE_GATHER4_C_CL_V2_V4 = 5264,
5280 : IMAGE_GATHER4_C_CL_V2_V8 = 5265,
5281 : IMAGE_GATHER4_C_CL_V4_V2 = 5266,
5282 : IMAGE_GATHER4_C_CL_V4_V3 = 5267,
5283 : IMAGE_GATHER4_C_CL_V4_V4 = 5268,
5284 : IMAGE_GATHER4_C_CL_V4_V8 = 5269,
5285 : IMAGE_GATHER4_C_LZ_O_V2_V3 = 5270,
5286 : IMAGE_GATHER4_C_LZ_O_V2_V4 = 5271,
5287 : IMAGE_GATHER4_C_LZ_O_V2_V8 = 5272,
5288 : IMAGE_GATHER4_C_LZ_O_V4_V3 = 5273,
5289 : IMAGE_GATHER4_C_LZ_O_V4_V4 = 5274,
5290 : IMAGE_GATHER4_C_LZ_O_V4_V8 = 5275,
5291 : IMAGE_GATHER4_C_LZ_V2_V2 = 5276,
5292 : IMAGE_GATHER4_C_LZ_V2_V3 = 5277,
5293 : IMAGE_GATHER4_C_LZ_V2_V4 = 5278,
5294 : IMAGE_GATHER4_C_LZ_V4_V2 = 5279,
5295 : IMAGE_GATHER4_C_LZ_V4_V3 = 5280,
5296 : IMAGE_GATHER4_C_LZ_V4_V4 = 5281,
5297 : IMAGE_GATHER4_C_L_O_V2_V3 = 5282,
5298 : IMAGE_GATHER4_C_L_O_V2_V4 = 5283,
5299 : IMAGE_GATHER4_C_L_O_V2_V8 = 5284,
5300 : IMAGE_GATHER4_C_L_O_V4_V3 = 5285,
5301 : IMAGE_GATHER4_C_L_O_V4_V4 = 5286,
5302 : IMAGE_GATHER4_C_L_O_V4_V8 = 5287,
5303 : IMAGE_GATHER4_C_L_V2_V2 = 5288,
5304 : IMAGE_GATHER4_C_L_V2_V3 = 5289,
5305 : IMAGE_GATHER4_C_L_V2_V4 = 5290,
5306 : IMAGE_GATHER4_C_L_V2_V8 = 5291,
5307 : IMAGE_GATHER4_C_L_V4_V2 = 5292,
5308 : IMAGE_GATHER4_C_L_V4_V3 = 5293,
5309 : IMAGE_GATHER4_C_L_V4_V4 = 5294,
5310 : IMAGE_GATHER4_C_L_V4_V8 = 5295,
5311 : IMAGE_GATHER4_C_O_V2_V3 = 5296,
5312 : IMAGE_GATHER4_C_O_V2_V4 = 5297,
5313 : IMAGE_GATHER4_C_O_V2_V8 = 5298,
5314 : IMAGE_GATHER4_C_O_V4_V3 = 5299,
5315 : IMAGE_GATHER4_C_O_V4_V4 = 5300,
5316 : IMAGE_GATHER4_C_O_V4_V8 = 5301,
5317 : IMAGE_GATHER4_C_V2_V2 = 5302,
5318 : IMAGE_GATHER4_C_V2_V3 = 5303,
5319 : IMAGE_GATHER4_C_V2_V4 = 5304,
5320 : IMAGE_GATHER4_C_V4_V2 = 5305,
5321 : IMAGE_GATHER4_C_V4_V3 = 5306,
5322 : IMAGE_GATHER4_C_V4_V4 = 5307,
5323 : IMAGE_GATHER4_LZ_O_V2_V2 = 5308,
5324 : IMAGE_GATHER4_LZ_O_V2_V3 = 5309,
5325 : IMAGE_GATHER4_LZ_O_V2_V4 = 5310,
5326 : IMAGE_GATHER4_LZ_O_V4_V2 = 5311,
5327 : IMAGE_GATHER4_LZ_O_V4_V3 = 5312,
5328 : IMAGE_GATHER4_LZ_O_V4_V4 = 5313,
5329 : IMAGE_GATHER4_LZ_V2_V1 = 5314,
5330 : IMAGE_GATHER4_LZ_V2_V2 = 5315,
5331 : IMAGE_GATHER4_LZ_V2_V3 = 5316,
5332 : IMAGE_GATHER4_LZ_V2_V4 = 5317,
5333 : IMAGE_GATHER4_LZ_V4_V1 = 5318,
5334 : IMAGE_GATHER4_LZ_V4_V2 = 5319,
5335 : IMAGE_GATHER4_LZ_V4_V3 = 5320,
5336 : IMAGE_GATHER4_LZ_V4_V4 = 5321,
5337 : IMAGE_GATHER4_L_O_V2_V2 = 5322,
5338 : IMAGE_GATHER4_L_O_V2_V3 = 5323,
5339 : IMAGE_GATHER4_L_O_V2_V4 = 5324,
5340 : IMAGE_GATHER4_L_O_V2_V8 = 5325,
5341 : IMAGE_GATHER4_L_O_V4_V2 = 5326,
5342 : IMAGE_GATHER4_L_O_V4_V3 = 5327,
5343 : IMAGE_GATHER4_L_O_V4_V4 = 5328,
5344 : IMAGE_GATHER4_L_O_V4_V8 = 5329,
5345 : IMAGE_GATHER4_L_V2_V1 = 5330,
5346 : IMAGE_GATHER4_L_V2_V2 = 5331,
5347 : IMAGE_GATHER4_L_V2_V3 = 5332,
5348 : IMAGE_GATHER4_L_V2_V4 = 5333,
5349 : IMAGE_GATHER4_L_V4_V1 = 5334,
5350 : IMAGE_GATHER4_L_V4_V2 = 5335,
5351 : IMAGE_GATHER4_L_V4_V3 = 5336,
5352 : IMAGE_GATHER4_L_V4_V4 = 5337,
5353 : IMAGE_GATHER4_O_V2_V2 = 5338,
5354 : IMAGE_GATHER4_O_V2_V3 = 5339,
5355 : IMAGE_GATHER4_O_V2_V4 = 5340,
5356 : IMAGE_GATHER4_O_V4_V2 = 5341,
5357 : IMAGE_GATHER4_O_V4_V3 = 5342,
5358 : IMAGE_GATHER4_O_V4_V4 = 5343,
5359 : IMAGE_GATHER4_V2_V1 = 5344,
5360 : IMAGE_GATHER4_V2_V2 = 5345,
5361 : IMAGE_GATHER4_V2_V3 = 5346,
5362 : IMAGE_GATHER4_V2_V4 = 5347,
5363 : IMAGE_GATHER4_V4_V1 = 5348,
5364 : IMAGE_GATHER4_V4_V2 = 5349,
5365 : IMAGE_GATHER4_V4_V3 = 5350,
5366 : IMAGE_GATHER4_V4_V4 = 5351,
5367 : IMAGE_GET_LOD_V1_V1 = 5352,
5368 : IMAGE_GET_LOD_V1_V2 = 5353,
5369 : IMAGE_GET_LOD_V1_V3 = 5354,
5370 : IMAGE_GET_LOD_V1_V4 = 5355,
5371 : IMAGE_GET_LOD_V2_V1 = 5356,
5372 : IMAGE_GET_LOD_V2_V2 = 5357,
5373 : IMAGE_GET_LOD_V2_V3 = 5358,
5374 : IMAGE_GET_LOD_V2_V4 = 5359,
5375 : IMAGE_GET_LOD_V3_V1 = 5360,
5376 : IMAGE_GET_LOD_V3_V2 = 5361,
5377 : IMAGE_GET_LOD_V3_V3 = 5362,
5378 : IMAGE_GET_LOD_V3_V4 = 5363,
5379 : IMAGE_GET_LOD_V4_V1 = 5364,
5380 : IMAGE_GET_LOD_V4_V2 = 5365,
5381 : IMAGE_GET_LOD_V4_V3 = 5366,
5382 : IMAGE_GET_LOD_V4_V4 = 5367,
5383 : IMAGE_GET_RESINFO_V1_V1 = 5368,
5384 : IMAGE_GET_RESINFO_V1_V2 = 5369,
5385 : IMAGE_GET_RESINFO_V1_V3 = 5370,
5386 : IMAGE_GET_RESINFO_V1_V4 = 5371,
5387 : IMAGE_GET_RESINFO_V2_V1 = 5372,
5388 : IMAGE_GET_RESINFO_V2_V2 = 5373,
5389 : IMAGE_GET_RESINFO_V2_V3 = 5374,
5390 : IMAGE_GET_RESINFO_V2_V4 = 5375,
5391 : IMAGE_GET_RESINFO_V3_V1 = 5376,
5392 : IMAGE_GET_RESINFO_V3_V2 = 5377,
5393 : IMAGE_GET_RESINFO_V3_V3 = 5378,
5394 : IMAGE_GET_RESINFO_V3_V4 = 5379,
5395 : IMAGE_GET_RESINFO_V4_V1 = 5380,
5396 : IMAGE_GET_RESINFO_V4_V2 = 5381,
5397 : IMAGE_GET_RESINFO_V4_V3 = 5382,
5398 : IMAGE_GET_RESINFO_V4_V4 = 5383,
5399 : IMAGE_LOAD_MIP_PCK_SGN_V1_V1 = 5384,
5400 : IMAGE_LOAD_MIP_PCK_SGN_V1_V2 = 5385,
5401 : IMAGE_LOAD_MIP_PCK_SGN_V1_V3 = 5386,
5402 : IMAGE_LOAD_MIP_PCK_SGN_V1_V4 = 5387,
5403 : IMAGE_LOAD_MIP_PCK_SGN_V2_V1 = 5388,
5404 : IMAGE_LOAD_MIP_PCK_SGN_V2_V2 = 5389,
5405 : IMAGE_LOAD_MIP_PCK_SGN_V2_V3 = 5390,
5406 : IMAGE_LOAD_MIP_PCK_SGN_V2_V4 = 5391,
5407 : IMAGE_LOAD_MIP_PCK_SGN_V3_V1 = 5392,
5408 : IMAGE_LOAD_MIP_PCK_SGN_V3_V2 = 5393,
5409 : IMAGE_LOAD_MIP_PCK_SGN_V3_V3 = 5394,
5410 : IMAGE_LOAD_MIP_PCK_SGN_V3_V4 = 5395,
5411 : IMAGE_LOAD_MIP_PCK_SGN_V4_V1 = 5396,
5412 : IMAGE_LOAD_MIP_PCK_SGN_V4_V2 = 5397,
5413 : IMAGE_LOAD_MIP_PCK_SGN_V4_V3 = 5398,
5414 : IMAGE_LOAD_MIP_PCK_SGN_V4_V4 = 5399,
5415 : IMAGE_LOAD_MIP_PCK_V1_V1 = 5400,
5416 : IMAGE_LOAD_MIP_PCK_V1_V2 = 5401,
5417 : IMAGE_LOAD_MIP_PCK_V1_V3 = 5402,
5418 : IMAGE_LOAD_MIP_PCK_V1_V4 = 5403,
5419 : IMAGE_LOAD_MIP_PCK_V2_V1 = 5404,
5420 : IMAGE_LOAD_MIP_PCK_V2_V2 = 5405,
5421 : IMAGE_LOAD_MIP_PCK_V2_V3 = 5406,
5422 : IMAGE_LOAD_MIP_PCK_V2_V4 = 5407,
5423 : IMAGE_LOAD_MIP_PCK_V3_V1 = 5408,
5424 : IMAGE_LOAD_MIP_PCK_V3_V2 = 5409,
5425 : IMAGE_LOAD_MIP_PCK_V3_V3 = 5410,
5426 : IMAGE_LOAD_MIP_PCK_V3_V4 = 5411,
5427 : IMAGE_LOAD_MIP_PCK_V4_V1 = 5412,
5428 : IMAGE_LOAD_MIP_PCK_V4_V2 = 5413,
5429 : IMAGE_LOAD_MIP_PCK_V4_V3 = 5414,
5430 : IMAGE_LOAD_MIP_PCK_V4_V4 = 5415,
5431 : IMAGE_LOAD_MIP_V1_V1 = 5416,
5432 : IMAGE_LOAD_MIP_V1_V2 = 5417,
5433 : IMAGE_LOAD_MIP_V1_V3 = 5418,
5434 : IMAGE_LOAD_MIP_V1_V4 = 5419,
5435 : IMAGE_LOAD_MIP_V2_V1 = 5420,
5436 : IMAGE_LOAD_MIP_V2_V2 = 5421,
5437 : IMAGE_LOAD_MIP_V2_V3 = 5422,
5438 : IMAGE_LOAD_MIP_V2_V4 = 5423,
5439 : IMAGE_LOAD_MIP_V3_V1 = 5424,
5440 : IMAGE_LOAD_MIP_V3_V2 = 5425,
5441 : IMAGE_LOAD_MIP_V3_V3 = 5426,
5442 : IMAGE_LOAD_MIP_V3_V4 = 5427,
5443 : IMAGE_LOAD_MIP_V4_V1 = 5428,
5444 : IMAGE_LOAD_MIP_V4_V2 = 5429,
5445 : IMAGE_LOAD_MIP_V4_V3 = 5430,
5446 : IMAGE_LOAD_MIP_V4_V4 = 5431,
5447 : IMAGE_LOAD_PCK_SGN_V1_V1 = 5432,
5448 : IMAGE_LOAD_PCK_SGN_V1_V2 = 5433,
5449 : IMAGE_LOAD_PCK_SGN_V1_V3 = 5434,
5450 : IMAGE_LOAD_PCK_SGN_V1_V4 = 5435,
5451 : IMAGE_LOAD_PCK_SGN_V2_V1 = 5436,
5452 : IMAGE_LOAD_PCK_SGN_V2_V2 = 5437,
5453 : IMAGE_LOAD_PCK_SGN_V2_V3 = 5438,
5454 : IMAGE_LOAD_PCK_SGN_V2_V4 = 5439,
5455 : IMAGE_LOAD_PCK_SGN_V3_V1 = 5440,
5456 : IMAGE_LOAD_PCK_SGN_V3_V2 = 5441,
5457 : IMAGE_LOAD_PCK_SGN_V3_V3 = 5442,
5458 : IMAGE_LOAD_PCK_SGN_V3_V4 = 5443,
5459 : IMAGE_LOAD_PCK_SGN_V4_V1 = 5444,
5460 : IMAGE_LOAD_PCK_SGN_V4_V2 = 5445,
5461 : IMAGE_LOAD_PCK_SGN_V4_V3 = 5446,
5462 : IMAGE_LOAD_PCK_SGN_V4_V4 = 5447,
5463 : IMAGE_LOAD_PCK_V1_V1 = 5448,
5464 : IMAGE_LOAD_PCK_V1_V2 = 5449,
5465 : IMAGE_LOAD_PCK_V1_V3 = 5450,
5466 : IMAGE_LOAD_PCK_V1_V4 = 5451,
5467 : IMAGE_LOAD_PCK_V2_V1 = 5452,
5468 : IMAGE_LOAD_PCK_V2_V2 = 5453,
5469 : IMAGE_LOAD_PCK_V2_V3 = 5454,
5470 : IMAGE_LOAD_PCK_V2_V4 = 5455,
5471 : IMAGE_LOAD_PCK_V3_V1 = 5456,
5472 : IMAGE_LOAD_PCK_V3_V2 = 5457,
5473 : IMAGE_LOAD_PCK_V3_V3 = 5458,
5474 : IMAGE_LOAD_PCK_V3_V4 = 5459,
5475 : IMAGE_LOAD_PCK_V4_V1 = 5460,
5476 : IMAGE_LOAD_PCK_V4_V2 = 5461,
5477 : IMAGE_LOAD_PCK_V4_V3 = 5462,
5478 : IMAGE_LOAD_PCK_V4_V4 = 5463,
5479 : IMAGE_LOAD_V1_V1 = 5464,
5480 : IMAGE_LOAD_V1_V2 = 5465,
5481 : IMAGE_LOAD_V1_V3 = 5466,
5482 : IMAGE_LOAD_V1_V4 = 5467,
5483 : IMAGE_LOAD_V2_V1 = 5468,
5484 : IMAGE_LOAD_V2_V2 = 5469,
5485 : IMAGE_LOAD_V2_V3 = 5470,
5486 : IMAGE_LOAD_V2_V4 = 5471,
5487 : IMAGE_LOAD_V3_V1 = 5472,
5488 : IMAGE_LOAD_V3_V2 = 5473,
5489 : IMAGE_LOAD_V3_V3 = 5474,
5490 : IMAGE_LOAD_V3_V4 = 5475,
5491 : IMAGE_LOAD_V4_V1 = 5476,
5492 : IMAGE_LOAD_V4_V2 = 5477,
5493 : IMAGE_LOAD_V4_V3 = 5478,
5494 : IMAGE_LOAD_V4_V4 = 5479,
5495 : IMAGE_SAMPLE_B_CL_O_V1_V3 = 5480,
5496 : IMAGE_SAMPLE_B_CL_O_V1_V4 = 5481,
5497 : IMAGE_SAMPLE_B_CL_O_V1_V8 = 5482,
5498 : IMAGE_SAMPLE_B_CL_O_V2_V3 = 5483,
5499 : IMAGE_SAMPLE_B_CL_O_V2_V4 = 5484,
5500 : IMAGE_SAMPLE_B_CL_O_V2_V8 = 5485,
5501 : IMAGE_SAMPLE_B_CL_O_V3_V3 = 5486,
5502 : IMAGE_SAMPLE_B_CL_O_V3_V4 = 5487,
5503 : IMAGE_SAMPLE_B_CL_O_V3_V8 = 5488,
5504 : IMAGE_SAMPLE_B_CL_O_V4_V3 = 5489,
5505 : IMAGE_SAMPLE_B_CL_O_V4_V4 = 5490,
5506 : IMAGE_SAMPLE_B_CL_O_V4_V8 = 5491,
5507 : IMAGE_SAMPLE_B_CL_V1_V2 = 5492,
5508 : IMAGE_SAMPLE_B_CL_V1_V3 = 5493,
5509 : IMAGE_SAMPLE_B_CL_V1_V4 = 5494,
5510 : IMAGE_SAMPLE_B_CL_V1_V8 = 5495,
5511 : IMAGE_SAMPLE_B_CL_V2_V2 = 5496,
5512 : IMAGE_SAMPLE_B_CL_V2_V3 = 5497,
5513 : IMAGE_SAMPLE_B_CL_V2_V4 = 5498,
5514 : IMAGE_SAMPLE_B_CL_V2_V8 = 5499,
5515 : IMAGE_SAMPLE_B_CL_V3_V2 = 5500,
5516 : IMAGE_SAMPLE_B_CL_V3_V3 = 5501,
5517 : IMAGE_SAMPLE_B_CL_V3_V4 = 5502,
5518 : IMAGE_SAMPLE_B_CL_V3_V8 = 5503,
5519 : IMAGE_SAMPLE_B_CL_V4_V2 = 5504,
5520 : IMAGE_SAMPLE_B_CL_V4_V3 = 5505,
5521 : IMAGE_SAMPLE_B_CL_V4_V4 = 5506,
5522 : IMAGE_SAMPLE_B_CL_V4_V8 = 5507,
5523 : IMAGE_SAMPLE_B_O_V1_V3 = 5508,
5524 : IMAGE_SAMPLE_B_O_V1_V4 = 5509,
5525 : IMAGE_SAMPLE_B_O_V1_V8 = 5510,
5526 : IMAGE_SAMPLE_B_O_V2_V3 = 5511,
5527 : IMAGE_SAMPLE_B_O_V2_V4 = 5512,
5528 : IMAGE_SAMPLE_B_O_V2_V8 = 5513,
5529 : IMAGE_SAMPLE_B_O_V3_V3 = 5514,
5530 : IMAGE_SAMPLE_B_O_V3_V4 = 5515,
5531 : IMAGE_SAMPLE_B_O_V3_V8 = 5516,
5532 : IMAGE_SAMPLE_B_O_V4_V3 = 5517,
5533 : IMAGE_SAMPLE_B_O_V4_V4 = 5518,
5534 : IMAGE_SAMPLE_B_O_V4_V8 = 5519,
5535 : IMAGE_SAMPLE_B_V1_V2 = 5520,
5536 : IMAGE_SAMPLE_B_V1_V3 = 5521,
5537 : IMAGE_SAMPLE_B_V1_V4 = 5522,
5538 : IMAGE_SAMPLE_B_V2_V2 = 5523,
5539 : IMAGE_SAMPLE_B_V2_V3 = 5524,
5540 : IMAGE_SAMPLE_B_V2_V4 = 5525,
5541 : IMAGE_SAMPLE_B_V3_V2 = 5526,
5542 : IMAGE_SAMPLE_B_V3_V3 = 5527,
5543 : IMAGE_SAMPLE_B_V3_V4 = 5528,
5544 : IMAGE_SAMPLE_B_V4_V2 = 5529,
5545 : IMAGE_SAMPLE_B_V4_V3 = 5530,
5546 : IMAGE_SAMPLE_B_V4_V4 = 5531,
5547 : IMAGE_SAMPLE_CD_CL_O_V1_V16 = 5532,
5548 : IMAGE_SAMPLE_CD_CL_O_V1_V3 = 5533,
5549 : IMAGE_SAMPLE_CD_CL_O_V1_V4 = 5534,
5550 : IMAGE_SAMPLE_CD_CL_O_V1_V8 = 5535,
5551 : IMAGE_SAMPLE_CD_CL_O_V2_V16 = 5536,
5552 : IMAGE_SAMPLE_CD_CL_O_V2_V3 = 5537,
5553 : IMAGE_SAMPLE_CD_CL_O_V2_V4 = 5538,
5554 : IMAGE_SAMPLE_CD_CL_O_V2_V8 = 5539,
5555 : IMAGE_SAMPLE_CD_CL_O_V3_V16 = 5540,
5556 : IMAGE_SAMPLE_CD_CL_O_V3_V3 = 5541,
5557 : IMAGE_SAMPLE_CD_CL_O_V3_V4 = 5542,
5558 : IMAGE_SAMPLE_CD_CL_O_V3_V8 = 5543,
5559 : IMAGE_SAMPLE_CD_CL_O_V4_V16 = 5544,
5560 : IMAGE_SAMPLE_CD_CL_O_V4_V3 = 5545,
5561 : IMAGE_SAMPLE_CD_CL_O_V4_V4 = 5546,
5562 : IMAGE_SAMPLE_CD_CL_O_V4_V8 = 5547,
5563 : IMAGE_SAMPLE_CD_CL_V1_V16 = 5548,
5564 : IMAGE_SAMPLE_CD_CL_V1_V2 = 5549,
5565 : IMAGE_SAMPLE_CD_CL_V1_V3 = 5550,
5566 : IMAGE_SAMPLE_CD_CL_V1_V4 = 5551,
5567 : IMAGE_SAMPLE_CD_CL_V1_V8 = 5552,
5568 : IMAGE_SAMPLE_CD_CL_V2_V16 = 5553,
5569 : IMAGE_SAMPLE_CD_CL_V2_V2 = 5554,
5570 : IMAGE_SAMPLE_CD_CL_V2_V3 = 5555,
5571 : IMAGE_SAMPLE_CD_CL_V2_V4 = 5556,
5572 : IMAGE_SAMPLE_CD_CL_V2_V8 = 5557,
5573 : IMAGE_SAMPLE_CD_CL_V3_V16 = 5558,
5574 : IMAGE_SAMPLE_CD_CL_V3_V2 = 5559,
5575 : IMAGE_SAMPLE_CD_CL_V3_V3 = 5560,
5576 : IMAGE_SAMPLE_CD_CL_V3_V4 = 5561,
5577 : IMAGE_SAMPLE_CD_CL_V3_V8 = 5562,
5578 : IMAGE_SAMPLE_CD_CL_V4_V16 = 5563,
5579 : IMAGE_SAMPLE_CD_CL_V4_V2 = 5564,
5580 : IMAGE_SAMPLE_CD_CL_V4_V3 = 5565,
5581 : IMAGE_SAMPLE_CD_CL_V4_V4 = 5566,
5582 : IMAGE_SAMPLE_CD_CL_V4_V8 = 5567,
5583 : IMAGE_SAMPLE_CD_O_V1_V16 = 5568,
5584 : IMAGE_SAMPLE_CD_O_V1_V3 = 5569,
5585 : IMAGE_SAMPLE_CD_O_V1_V4 = 5570,
5586 : IMAGE_SAMPLE_CD_O_V1_V8 = 5571,
5587 : IMAGE_SAMPLE_CD_O_V2_V16 = 5572,
5588 : IMAGE_SAMPLE_CD_O_V2_V3 = 5573,
5589 : IMAGE_SAMPLE_CD_O_V2_V4 = 5574,
5590 : IMAGE_SAMPLE_CD_O_V2_V8 = 5575,
5591 : IMAGE_SAMPLE_CD_O_V3_V16 = 5576,
5592 : IMAGE_SAMPLE_CD_O_V3_V3 = 5577,
5593 : IMAGE_SAMPLE_CD_O_V3_V4 = 5578,
5594 : IMAGE_SAMPLE_CD_O_V3_V8 = 5579,
5595 : IMAGE_SAMPLE_CD_O_V4_V16 = 5580,
5596 : IMAGE_SAMPLE_CD_O_V4_V3 = 5581,
5597 : IMAGE_SAMPLE_CD_O_V4_V4 = 5582,
5598 : IMAGE_SAMPLE_CD_O_V4_V8 = 5583,
5599 : IMAGE_SAMPLE_CD_V1_V16 = 5584,
5600 : IMAGE_SAMPLE_CD_V1_V2 = 5585,
5601 : IMAGE_SAMPLE_CD_V1_V3 = 5586,
5602 : IMAGE_SAMPLE_CD_V1_V4 = 5587,
5603 : IMAGE_SAMPLE_CD_V1_V8 = 5588,
5604 : IMAGE_SAMPLE_CD_V2_V16 = 5589,
5605 : IMAGE_SAMPLE_CD_V2_V2 = 5590,
5606 : IMAGE_SAMPLE_CD_V2_V3 = 5591,
5607 : IMAGE_SAMPLE_CD_V2_V4 = 5592,
5608 : IMAGE_SAMPLE_CD_V2_V8 = 5593,
5609 : IMAGE_SAMPLE_CD_V3_V16 = 5594,
5610 : IMAGE_SAMPLE_CD_V3_V2 = 5595,
5611 : IMAGE_SAMPLE_CD_V3_V3 = 5596,
5612 : IMAGE_SAMPLE_CD_V3_V4 = 5597,
5613 : IMAGE_SAMPLE_CD_V3_V8 = 5598,
5614 : IMAGE_SAMPLE_CD_V4_V16 = 5599,
5615 : IMAGE_SAMPLE_CD_V4_V2 = 5600,
5616 : IMAGE_SAMPLE_CD_V4_V3 = 5601,
5617 : IMAGE_SAMPLE_CD_V4_V4 = 5602,
5618 : IMAGE_SAMPLE_CD_V4_V8 = 5603,
5619 : IMAGE_SAMPLE_CL_O_V1_V2 = 5604,
5620 : IMAGE_SAMPLE_CL_O_V1_V3 = 5605,
5621 : IMAGE_SAMPLE_CL_O_V1_V4 = 5606,
5622 : IMAGE_SAMPLE_CL_O_V1_V8 = 5607,
5623 : IMAGE_SAMPLE_CL_O_V2_V2 = 5608,
5624 : IMAGE_SAMPLE_CL_O_V2_V3 = 5609,
5625 : IMAGE_SAMPLE_CL_O_V2_V4 = 5610,
5626 : IMAGE_SAMPLE_CL_O_V2_V8 = 5611,
5627 : IMAGE_SAMPLE_CL_O_V3_V2 = 5612,
5628 : IMAGE_SAMPLE_CL_O_V3_V3 = 5613,
5629 : IMAGE_SAMPLE_CL_O_V3_V4 = 5614,
5630 : IMAGE_SAMPLE_CL_O_V3_V8 = 5615,
5631 : IMAGE_SAMPLE_CL_O_V4_V2 = 5616,
5632 : IMAGE_SAMPLE_CL_O_V4_V3 = 5617,
5633 : IMAGE_SAMPLE_CL_O_V4_V4 = 5618,
5634 : IMAGE_SAMPLE_CL_O_V4_V8 = 5619,
5635 : IMAGE_SAMPLE_CL_V1_V1 = 5620,
5636 : IMAGE_SAMPLE_CL_V1_V2 = 5621,
5637 : IMAGE_SAMPLE_CL_V1_V3 = 5622,
5638 : IMAGE_SAMPLE_CL_V1_V4 = 5623,
5639 : IMAGE_SAMPLE_CL_V2_V1 = 5624,
5640 : IMAGE_SAMPLE_CL_V2_V2 = 5625,
5641 : IMAGE_SAMPLE_CL_V2_V3 = 5626,
5642 : IMAGE_SAMPLE_CL_V2_V4 = 5627,
5643 : IMAGE_SAMPLE_CL_V3_V1 = 5628,
5644 : IMAGE_SAMPLE_CL_V3_V2 = 5629,
5645 : IMAGE_SAMPLE_CL_V3_V3 = 5630,
5646 : IMAGE_SAMPLE_CL_V3_V4 = 5631,
5647 : IMAGE_SAMPLE_CL_V4_V1 = 5632,
5648 : IMAGE_SAMPLE_CL_V4_V2 = 5633,
5649 : IMAGE_SAMPLE_CL_V4_V3 = 5634,
5650 : IMAGE_SAMPLE_CL_V4_V4 = 5635,
5651 : IMAGE_SAMPLE_C_B_CL_O_V1_V4 = 5636,
5652 : IMAGE_SAMPLE_C_B_CL_O_V1_V8 = 5637,
5653 : IMAGE_SAMPLE_C_B_CL_O_V2_V4 = 5638,
5654 : IMAGE_SAMPLE_C_B_CL_O_V2_V8 = 5639,
5655 : IMAGE_SAMPLE_C_B_CL_O_V3_V4 = 5640,
5656 : IMAGE_SAMPLE_C_B_CL_O_V3_V8 = 5641,
5657 : IMAGE_SAMPLE_C_B_CL_O_V4_V4 = 5642,
5658 : IMAGE_SAMPLE_C_B_CL_O_V4_V8 = 5643,
5659 : IMAGE_SAMPLE_C_B_CL_V1_V3 = 5644,
5660 : IMAGE_SAMPLE_C_B_CL_V1_V4 = 5645,
5661 : IMAGE_SAMPLE_C_B_CL_V1_V8 = 5646,
5662 : IMAGE_SAMPLE_C_B_CL_V2_V3 = 5647,
5663 : IMAGE_SAMPLE_C_B_CL_V2_V4 = 5648,
5664 : IMAGE_SAMPLE_C_B_CL_V2_V8 = 5649,
5665 : IMAGE_SAMPLE_C_B_CL_V3_V3 = 5650,
5666 : IMAGE_SAMPLE_C_B_CL_V3_V4 = 5651,
5667 : IMAGE_SAMPLE_C_B_CL_V3_V8 = 5652,
5668 : IMAGE_SAMPLE_C_B_CL_V4_V3 = 5653,
5669 : IMAGE_SAMPLE_C_B_CL_V4_V4 = 5654,
5670 : IMAGE_SAMPLE_C_B_CL_V4_V8 = 5655,
5671 : IMAGE_SAMPLE_C_B_O_V1_V4 = 5656,
5672 : IMAGE_SAMPLE_C_B_O_V1_V8 = 5657,
5673 : IMAGE_SAMPLE_C_B_O_V2_V4 = 5658,
5674 : IMAGE_SAMPLE_C_B_O_V2_V8 = 5659,
5675 : IMAGE_SAMPLE_C_B_O_V3_V4 = 5660,
5676 : IMAGE_SAMPLE_C_B_O_V3_V8 = 5661,
5677 : IMAGE_SAMPLE_C_B_O_V4_V4 = 5662,
5678 : IMAGE_SAMPLE_C_B_O_V4_V8 = 5663,
5679 : IMAGE_SAMPLE_C_B_V1_V3 = 5664,
5680 : IMAGE_SAMPLE_C_B_V1_V4 = 5665,
5681 : IMAGE_SAMPLE_C_B_V1_V8 = 5666,
5682 : IMAGE_SAMPLE_C_B_V2_V3 = 5667,
5683 : IMAGE_SAMPLE_C_B_V2_V4 = 5668,
5684 : IMAGE_SAMPLE_C_B_V2_V8 = 5669,
5685 : IMAGE_SAMPLE_C_B_V3_V3 = 5670,
5686 : IMAGE_SAMPLE_C_B_V3_V4 = 5671,
5687 : IMAGE_SAMPLE_C_B_V3_V8 = 5672,
5688 : IMAGE_SAMPLE_C_B_V4_V3 = 5673,
5689 : IMAGE_SAMPLE_C_B_V4_V4 = 5674,
5690 : IMAGE_SAMPLE_C_B_V4_V8 = 5675,
5691 : IMAGE_SAMPLE_C_CD_CL_O_V1_V16 = 5676,
5692 : IMAGE_SAMPLE_C_CD_CL_O_V1_V4 = 5677,
5693 : IMAGE_SAMPLE_C_CD_CL_O_V1_V8 = 5678,
5694 : IMAGE_SAMPLE_C_CD_CL_O_V2_V16 = 5679,
5695 : IMAGE_SAMPLE_C_CD_CL_O_V2_V4 = 5680,
5696 : IMAGE_SAMPLE_C_CD_CL_O_V2_V8 = 5681,
5697 : IMAGE_SAMPLE_C_CD_CL_O_V3_V16 = 5682,
5698 : IMAGE_SAMPLE_C_CD_CL_O_V3_V4 = 5683,
5699 : IMAGE_SAMPLE_C_CD_CL_O_V3_V8 = 5684,
5700 : IMAGE_SAMPLE_C_CD_CL_O_V4_V16 = 5685,
5701 : IMAGE_SAMPLE_C_CD_CL_O_V4_V4 = 5686,
5702 : IMAGE_SAMPLE_C_CD_CL_O_V4_V8 = 5687,
5703 : IMAGE_SAMPLE_C_CD_CL_V1_V16 = 5688,
5704 : IMAGE_SAMPLE_C_CD_CL_V1_V3 = 5689,
5705 : IMAGE_SAMPLE_C_CD_CL_V1_V4 = 5690,
5706 : IMAGE_SAMPLE_C_CD_CL_V1_V8 = 5691,
5707 : IMAGE_SAMPLE_C_CD_CL_V2_V16 = 5692,
5708 : IMAGE_SAMPLE_C_CD_CL_V2_V3 = 5693,
5709 : IMAGE_SAMPLE_C_CD_CL_V2_V4 = 5694,
5710 : IMAGE_SAMPLE_C_CD_CL_V2_V8 = 5695,
5711 : IMAGE_SAMPLE_C_CD_CL_V3_V16 = 5696,
5712 : IMAGE_SAMPLE_C_CD_CL_V3_V3 = 5697,
5713 : IMAGE_SAMPLE_C_CD_CL_V3_V4 = 5698,
5714 : IMAGE_SAMPLE_C_CD_CL_V3_V8 = 5699,
5715 : IMAGE_SAMPLE_C_CD_CL_V4_V16 = 5700,
5716 : IMAGE_SAMPLE_C_CD_CL_V4_V3 = 5701,
5717 : IMAGE_SAMPLE_C_CD_CL_V4_V4 = 5702,
5718 : IMAGE_SAMPLE_C_CD_CL_V4_V8 = 5703,
5719 : IMAGE_SAMPLE_C_CD_O_V1_V16 = 5704,
5720 : IMAGE_SAMPLE_C_CD_O_V1_V4 = 5705,
5721 : IMAGE_SAMPLE_C_CD_O_V1_V8 = 5706,
5722 : IMAGE_SAMPLE_C_CD_O_V2_V16 = 5707,
5723 : IMAGE_SAMPLE_C_CD_O_V2_V4 = 5708,
5724 : IMAGE_SAMPLE_C_CD_O_V2_V8 = 5709,
5725 : IMAGE_SAMPLE_C_CD_O_V3_V16 = 5710,
5726 : IMAGE_SAMPLE_C_CD_O_V3_V4 = 5711,
5727 : IMAGE_SAMPLE_C_CD_O_V3_V8 = 5712,
5728 : IMAGE_SAMPLE_C_CD_O_V4_V16 = 5713,
5729 : IMAGE_SAMPLE_C_CD_O_V4_V4 = 5714,
5730 : IMAGE_SAMPLE_C_CD_O_V4_V8 = 5715,
5731 : IMAGE_SAMPLE_C_CD_V1_V16 = 5716,
5732 : IMAGE_SAMPLE_C_CD_V1_V3 = 5717,
5733 : IMAGE_SAMPLE_C_CD_V1_V4 = 5718,
5734 : IMAGE_SAMPLE_C_CD_V1_V8 = 5719,
5735 : IMAGE_SAMPLE_C_CD_V2_V16 = 5720,
5736 : IMAGE_SAMPLE_C_CD_V2_V3 = 5721,
5737 : IMAGE_SAMPLE_C_CD_V2_V4 = 5722,
5738 : IMAGE_SAMPLE_C_CD_V2_V8 = 5723,
5739 : IMAGE_SAMPLE_C_CD_V3_V16 = 5724,
5740 : IMAGE_SAMPLE_C_CD_V3_V3 = 5725,
5741 : IMAGE_SAMPLE_C_CD_V3_V4 = 5726,
5742 : IMAGE_SAMPLE_C_CD_V3_V8 = 5727,
5743 : IMAGE_SAMPLE_C_CD_V4_V16 = 5728,
5744 : IMAGE_SAMPLE_C_CD_V4_V3 = 5729,
5745 : IMAGE_SAMPLE_C_CD_V4_V4 = 5730,
5746 : IMAGE_SAMPLE_C_CD_V4_V8 = 5731,
5747 : IMAGE_SAMPLE_C_CL_O_V1_V3 = 5732,
5748 : IMAGE_SAMPLE_C_CL_O_V1_V4 = 5733,
5749 : IMAGE_SAMPLE_C_CL_O_V1_V8 = 5734,
5750 : IMAGE_SAMPLE_C_CL_O_V2_V3 = 5735,
5751 : IMAGE_SAMPLE_C_CL_O_V2_V4 = 5736,
5752 : IMAGE_SAMPLE_C_CL_O_V2_V8 = 5737,
5753 : IMAGE_SAMPLE_C_CL_O_V3_V3 = 5738,
5754 : IMAGE_SAMPLE_C_CL_O_V3_V4 = 5739,
5755 : IMAGE_SAMPLE_C_CL_O_V3_V8 = 5740,
5756 : IMAGE_SAMPLE_C_CL_O_V4_V3 = 5741,
5757 : IMAGE_SAMPLE_C_CL_O_V4_V4 = 5742,
5758 : IMAGE_SAMPLE_C_CL_O_V4_V8 = 5743,
5759 : IMAGE_SAMPLE_C_CL_V1_V2 = 5744,
5760 : IMAGE_SAMPLE_C_CL_V1_V3 = 5745,
5761 : IMAGE_SAMPLE_C_CL_V1_V4 = 5746,
5762 : IMAGE_SAMPLE_C_CL_V1_V8 = 5747,
5763 : IMAGE_SAMPLE_C_CL_V2_V2 = 5748,
5764 : IMAGE_SAMPLE_C_CL_V2_V3 = 5749,
5765 : IMAGE_SAMPLE_C_CL_V2_V4 = 5750,
5766 : IMAGE_SAMPLE_C_CL_V2_V8 = 5751,
5767 : IMAGE_SAMPLE_C_CL_V3_V2 = 5752,
5768 : IMAGE_SAMPLE_C_CL_V3_V3 = 5753,
5769 : IMAGE_SAMPLE_C_CL_V3_V4 = 5754,
5770 : IMAGE_SAMPLE_C_CL_V3_V8 = 5755,
5771 : IMAGE_SAMPLE_C_CL_V4_V2 = 5756,
5772 : IMAGE_SAMPLE_C_CL_V4_V3 = 5757,
5773 : IMAGE_SAMPLE_C_CL_V4_V4 = 5758,
5774 : IMAGE_SAMPLE_C_CL_V4_V8 = 5759,
5775 : IMAGE_SAMPLE_C_D_CL_O_V1_V16 = 5760,
5776 : IMAGE_SAMPLE_C_D_CL_O_V1_V4 = 5761,
5777 : IMAGE_SAMPLE_C_D_CL_O_V1_V8 = 5762,
5778 : IMAGE_SAMPLE_C_D_CL_O_V2_V16 = 5763,
5779 : IMAGE_SAMPLE_C_D_CL_O_V2_V4 = 5764,
5780 : IMAGE_SAMPLE_C_D_CL_O_V2_V8 = 5765,
5781 : IMAGE_SAMPLE_C_D_CL_O_V3_V16 = 5766,
5782 : IMAGE_SAMPLE_C_D_CL_O_V3_V4 = 5767,
5783 : IMAGE_SAMPLE_C_D_CL_O_V3_V8 = 5768,
5784 : IMAGE_SAMPLE_C_D_CL_O_V4_V16 = 5769,
5785 : IMAGE_SAMPLE_C_D_CL_O_V4_V4 = 5770,
5786 : IMAGE_SAMPLE_C_D_CL_O_V4_V8 = 5771,
5787 : IMAGE_SAMPLE_C_D_CL_V1_V16 = 5772,
5788 : IMAGE_SAMPLE_C_D_CL_V1_V3 = 5773,
5789 : IMAGE_SAMPLE_C_D_CL_V1_V4 = 5774,
5790 : IMAGE_SAMPLE_C_D_CL_V1_V8 = 5775,
5791 : IMAGE_SAMPLE_C_D_CL_V2_V16 = 5776,
5792 : IMAGE_SAMPLE_C_D_CL_V2_V3 = 5777,
5793 : IMAGE_SAMPLE_C_D_CL_V2_V4 = 5778,
5794 : IMAGE_SAMPLE_C_D_CL_V2_V8 = 5779,
5795 : IMAGE_SAMPLE_C_D_CL_V3_V16 = 5780,
5796 : IMAGE_SAMPLE_C_D_CL_V3_V3 = 5781,
5797 : IMAGE_SAMPLE_C_D_CL_V3_V4 = 5782,
5798 : IMAGE_SAMPLE_C_D_CL_V3_V8 = 5783,
5799 : IMAGE_SAMPLE_C_D_CL_V4_V16 = 5784,
5800 : IMAGE_SAMPLE_C_D_CL_V4_V3 = 5785,
5801 : IMAGE_SAMPLE_C_D_CL_V4_V4 = 5786,
5802 : IMAGE_SAMPLE_C_D_CL_V4_V8 = 5787,
5803 : IMAGE_SAMPLE_C_D_O_V1_V16 = 5788,
5804 : IMAGE_SAMPLE_C_D_O_V1_V4 = 5789,
5805 : IMAGE_SAMPLE_C_D_O_V1_V8 = 5790,
5806 : IMAGE_SAMPLE_C_D_O_V2_V16 = 5791,
5807 : IMAGE_SAMPLE_C_D_O_V2_V4 = 5792,
5808 : IMAGE_SAMPLE_C_D_O_V2_V8 = 5793,
5809 : IMAGE_SAMPLE_C_D_O_V3_V16 = 5794,
5810 : IMAGE_SAMPLE_C_D_O_V3_V4 = 5795,
5811 : IMAGE_SAMPLE_C_D_O_V3_V8 = 5796,
5812 : IMAGE_SAMPLE_C_D_O_V4_V16 = 5797,
5813 : IMAGE_SAMPLE_C_D_O_V4_V4 = 5798,
5814 : IMAGE_SAMPLE_C_D_O_V4_V8 = 5799,
5815 : IMAGE_SAMPLE_C_D_V1_V16 = 5800,
5816 : IMAGE_SAMPLE_C_D_V1_V3 = 5801,
5817 : IMAGE_SAMPLE_C_D_V1_V4 = 5802,
5818 : IMAGE_SAMPLE_C_D_V1_V8 = 5803,
5819 : IMAGE_SAMPLE_C_D_V2_V16 = 5804,
5820 : IMAGE_SAMPLE_C_D_V2_V3 = 5805,
5821 : IMAGE_SAMPLE_C_D_V2_V4 = 5806,
5822 : IMAGE_SAMPLE_C_D_V2_V8 = 5807,
5823 : IMAGE_SAMPLE_C_D_V3_V16 = 5808,
5824 : IMAGE_SAMPLE_C_D_V3_V3 = 5809,
5825 : IMAGE_SAMPLE_C_D_V3_V4 = 5810,
5826 : IMAGE_SAMPLE_C_D_V3_V8 = 5811,
5827 : IMAGE_SAMPLE_C_D_V4_V16 = 5812,
5828 : IMAGE_SAMPLE_C_D_V4_V3 = 5813,
5829 : IMAGE_SAMPLE_C_D_V4_V4 = 5814,
5830 : IMAGE_SAMPLE_C_D_V4_V8 = 5815,
5831 : IMAGE_SAMPLE_C_LZ_O_V1_V3 = 5816,
5832 : IMAGE_SAMPLE_C_LZ_O_V1_V4 = 5817,
5833 : IMAGE_SAMPLE_C_LZ_O_V1_V8 = 5818,
5834 : IMAGE_SAMPLE_C_LZ_O_V2_V3 = 5819,
5835 : IMAGE_SAMPLE_C_LZ_O_V2_V4 = 5820,
5836 : IMAGE_SAMPLE_C_LZ_O_V2_V8 = 5821,
5837 : IMAGE_SAMPLE_C_LZ_O_V3_V3 = 5822,
5838 : IMAGE_SAMPLE_C_LZ_O_V3_V4 = 5823,
5839 : IMAGE_SAMPLE_C_LZ_O_V3_V8 = 5824,
5840 : IMAGE_SAMPLE_C_LZ_O_V4_V3 = 5825,
5841 : IMAGE_SAMPLE_C_LZ_O_V4_V4 = 5826,
5842 : IMAGE_SAMPLE_C_LZ_O_V4_V8 = 5827,
5843 : IMAGE_SAMPLE_C_LZ_V1_V2 = 5828,
5844 : IMAGE_SAMPLE_C_LZ_V1_V3 = 5829,
5845 : IMAGE_SAMPLE_C_LZ_V1_V4 = 5830,
5846 : IMAGE_SAMPLE_C_LZ_V2_V2 = 5831,
5847 : IMAGE_SAMPLE_C_LZ_V2_V3 = 5832,
5848 : IMAGE_SAMPLE_C_LZ_V2_V4 = 5833,
5849 : IMAGE_SAMPLE_C_LZ_V3_V2 = 5834,
5850 : IMAGE_SAMPLE_C_LZ_V3_V3 = 5835,
5851 : IMAGE_SAMPLE_C_LZ_V3_V4 = 5836,
5852 : IMAGE_SAMPLE_C_LZ_V4_V2 = 5837,
5853 : IMAGE_SAMPLE_C_LZ_V4_V3 = 5838,
5854 : IMAGE_SAMPLE_C_LZ_V4_V4 = 5839,
5855 : IMAGE_SAMPLE_C_L_O_V1_V3 = 5840,
5856 : IMAGE_SAMPLE_C_L_O_V1_V4 = 5841,
5857 : IMAGE_SAMPLE_C_L_O_V1_V8 = 5842,
5858 : IMAGE_SAMPLE_C_L_O_V2_V3 = 5843,
5859 : IMAGE_SAMPLE_C_L_O_V2_V4 = 5844,
5860 : IMAGE_SAMPLE_C_L_O_V2_V8 = 5845,
5861 : IMAGE_SAMPLE_C_L_O_V3_V3 = 5846,
5862 : IMAGE_SAMPLE_C_L_O_V3_V4 = 5847,
5863 : IMAGE_SAMPLE_C_L_O_V3_V8 = 5848,
5864 : IMAGE_SAMPLE_C_L_O_V4_V3 = 5849,
5865 : IMAGE_SAMPLE_C_L_O_V4_V4 = 5850,
5866 : IMAGE_SAMPLE_C_L_O_V4_V8 = 5851,
5867 : IMAGE_SAMPLE_C_L_V1_V2 = 5852,
5868 : IMAGE_SAMPLE_C_L_V1_V3 = 5853,
5869 : IMAGE_SAMPLE_C_L_V1_V4 = 5854,
5870 : IMAGE_SAMPLE_C_L_V1_V8 = 5855,
5871 : IMAGE_SAMPLE_C_L_V2_V2 = 5856,
5872 : IMAGE_SAMPLE_C_L_V2_V3 = 5857,
5873 : IMAGE_SAMPLE_C_L_V2_V4 = 5858,
5874 : IMAGE_SAMPLE_C_L_V2_V8 = 5859,
5875 : IMAGE_SAMPLE_C_L_V3_V2 = 5860,
5876 : IMAGE_SAMPLE_C_L_V3_V3 = 5861,
5877 : IMAGE_SAMPLE_C_L_V3_V4 = 5862,
5878 : IMAGE_SAMPLE_C_L_V3_V8 = 5863,
5879 : IMAGE_SAMPLE_C_L_V4_V2 = 5864,
5880 : IMAGE_SAMPLE_C_L_V4_V3 = 5865,
5881 : IMAGE_SAMPLE_C_L_V4_V4 = 5866,
5882 : IMAGE_SAMPLE_C_L_V4_V8 = 5867,
5883 : IMAGE_SAMPLE_C_O_V1_V3 = 5868,
5884 : IMAGE_SAMPLE_C_O_V1_V4 = 5869,
5885 : IMAGE_SAMPLE_C_O_V1_V8 = 5870,
5886 : IMAGE_SAMPLE_C_O_V2_V3 = 5871,
5887 : IMAGE_SAMPLE_C_O_V2_V4 = 5872,
5888 : IMAGE_SAMPLE_C_O_V2_V8 = 5873,
5889 : IMAGE_SAMPLE_C_O_V3_V3 = 5874,
5890 : IMAGE_SAMPLE_C_O_V3_V4 = 5875,
5891 : IMAGE_SAMPLE_C_O_V3_V8 = 5876,
5892 : IMAGE_SAMPLE_C_O_V4_V3 = 5877,
5893 : IMAGE_SAMPLE_C_O_V4_V4 = 5878,
5894 : IMAGE_SAMPLE_C_O_V4_V8 = 5879,
5895 : IMAGE_SAMPLE_C_V1_V2 = 5880,
5896 : IMAGE_SAMPLE_C_V1_V3 = 5881,
5897 : IMAGE_SAMPLE_C_V1_V4 = 5882,
5898 : IMAGE_SAMPLE_C_V2_V2 = 5883,
5899 : IMAGE_SAMPLE_C_V2_V3 = 5884,
5900 : IMAGE_SAMPLE_C_V2_V4 = 5885,
5901 : IMAGE_SAMPLE_C_V3_V2 = 5886,
5902 : IMAGE_SAMPLE_C_V3_V3 = 5887,
5903 : IMAGE_SAMPLE_C_V3_V4 = 5888,
5904 : IMAGE_SAMPLE_C_V4_V2 = 5889,
5905 : IMAGE_SAMPLE_C_V4_V3 = 5890,
5906 : IMAGE_SAMPLE_C_V4_V4 = 5891,
5907 : IMAGE_SAMPLE_D_CL_O_V1_V16 = 5892,
5908 : IMAGE_SAMPLE_D_CL_O_V1_V3 = 5893,
5909 : IMAGE_SAMPLE_D_CL_O_V1_V4 = 5894,
5910 : IMAGE_SAMPLE_D_CL_O_V1_V8 = 5895,
5911 : IMAGE_SAMPLE_D_CL_O_V2_V16 = 5896,
5912 : IMAGE_SAMPLE_D_CL_O_V2_V3 = 5897,
5913 : IMAGE_SAMPLE_D_CL_O_V2_V4 = 5898,
5914 : IMAGE_SAMPLE_D_CL_O_V2_V8 = 5899,
5915 : IMAGE_SAMPLE_D_CL_O_V3_V16 = 5900,
5916 : IMAGE_SAMPLE_D_CL_O_V3_V3 = 5901,
5917 : IMAGE_SAMPLE_D_CL_O_V3_V4 = 5902,
5918 : IMAGE_SAMPLE_D_CL_O_V3_V8 = 5903,
5919 : IMAGE_SAMPLE_D_CL_O_V4_V16 = 5904,
5920 : IMAGE_SAMPLE_D_CL_O_V4_V3 = 5905,
5921 : IMAGE_SAMPLE_D_CL_O_V4_V4 = 5906,
5922 : IMAGE_SAMPLE_D_CL_O_V4_V8 = 5907,
5923 : IMAGE_SAMPLE_D_CL_V1_V16 = 5908,
5924 : IMAGE_SAMPLE_D_CL_V1_V2 = 5909,
5925 : IMAGE_SAMPLE_D_CL_V1_V3 = 5910,
5926 : IMAGE_SAMPLE_D_CL_V1_V4 = 5911,
5927 : IMAGE_SAMPLE_D_CL_V1_V8 = 5912,
5928 : IMAGE_SAMPLE_D_CL_V2_V16 = 5913,
5929 : IMAGE_SAMPLE_D_CL_V2_V2 = 5914,
5930 : IMAGE_SAMPLE_D_CL_V2_V3 = 5915,
5931 : IMAGE_SAMPLE_D_CL_V2_V4 = 5916,
5932 : IMAGE_SAMPLE_D_CL_V2_V8 = 5917,
5933 : IMAGE_SAMPLE_D_CL_V3_V16 = 5918,
5934 : IMAGE_SAMPLE_D_CL_V3_V2 = 5919,
5935 : IMAGE_SAMPLE_D_CL_V3_V3 = 5920,
5936 : IMAGE_SAMPLE_D_CL_V3_V4 = 5921,
5937 : IMAGE_SAMPLE_D_CL_V3_V8 = 5922,
5938 : IMAGE_SAMPLE_D_CL_V4_V16 = 5923,
5939 : IMAGE_SAMPLE_D_CL_V4_V2 = 5924,
5940 : IMAGE_SAMPLE_D_CL_V4_V3 = 5925,
5941 : IMAGE_SAMPLE_D_CL_V4_V4 = 5926,
5942 : IMAGE_SAMPLE_D_CL_V4_V8 = 5927,
5943 : IMAGE_SAMPLE_D_O_V1_V16 = 5928,
5944 : IMAGE_SAMPLE_D_O_V1_V3 = 5929,
5945 : IMAGE_SAMPLE_D_O_V1_V4 = 5930,
5946 : IMAGE_SAMPLE_D_O_V1_V8 = 5931,
5947 : IMAGE_SAMPLE_D_O_V2_V16 = 5932,
5948 : IMAGE_SAMPLE_D_O_V2_V3 = 5933,
5949 : IMAGE_SAMPLE_D_O_V2_V4 = 5934,
5950 : IMAGE_SAMPLE_D_O_V2_V8 = 5935,
5951 : IMAGE_SAMPLE_D_O_V3_V16 = 5936,
5952 : IMAGE_SAMPLE_D_O_V3_V3 = 5937,
5953 : IMAGE_SAMPLE_D_O_V3_V4 = 5938,
5954 : IMAGE_SAMPLE_D_O_V3_V8 = 5939,
5955 : IMAGE_SAMPLE_D_O_V4_V16 = 5940,
5956 : IMAGE_SAMPLE_D_O_V4_V3 = 5941,
5957 : IMAGE_SAMPLE_D_O_V4_V4 = 5942,
5958 : IMAGE_SAMPLE_D_O_V4_V8 = 5943,
5959 : IMAGE_SAMPLE_D_V1_V16 = 5944,
5960 : IMAGE_SAMPLE_D_V1_V2 = 5945,
5961 : IMAGE_SAMPLE_D_V1_V3 = 5946,
5962 : IMAGE_SAMPLE_D_V1_V4 = 5947,
5963 : IMAGE_SAMPLE_D_V1_V8 = 5948,
5964 : IMAGE_SAMPLE_D_V2_V16 = 5949,
5965 : IMAGE_SAMPLE_D_V2_V2 = 5950,
5966 : IMAGE_SAMPLE_D_V2_V3 = 5951,
5967 : IMAGE_SAMPLE_D_V2_V4 = 5952,
5968 : IMAGE_SAMPLE_D_V2_V8 = 5953,
5969 : IMAGE_SAMPLE_D_V3_V16 = 5954,
5970 : IMAGE_SAMPLE_D_V3_V2 = 5955,
5971 : IMAGE_SAMPLE_D_V3_V3 = 5956,
5972 : IMAGE_SAMPLE_D_V3_V4 = 5957,
5973 : IMAGE_SAMPLE_D_V3_V8 = 5958,
5974 : IMAGE_SAMPLE_D_V4_V16 = 5959,
5975 : IMAGE_SAMPLE_D_V4_V2 = 5960,
5976 : IMAGE_SAMPLE_D_V4_V3 = 5961,
5977 : IMAGE_SAMPLE_D_V4_V4 = 5962,
5978 : IMAGE_SAMPLE_D_V4_V8 = 5963,
5979 : IMAGE_SAMPLE_LZ_O_V1_V2 = 5964,
5980 : IMAGE_SAMPLE_LZ_O_V1_V3 = 5965,
5981 : IMAGE_SAMPLE_LZ_O_V1_V4 = 5966,
5982 : IMAGE_SAMPLE_LZ_O_V2_V2 = 5967,
5983 : IMAGE_SAMPLE_LZ_O_V2_V3 = 5968,
5984 : IMAGE_SAMPLE_LZ_O_V2_V4 = 5969,
5985 : IMAGE_SAMPLE_LZ_O_V3_V2 = 5970,
5986 : IMAGE_SAMPLE_LZ_O_V3_V3 = 5971,
5987 : IMAGE_SAMPLE_LZ_O_V3_V4 = 5972,
5988 : IMAGE_SAMPLE_LZ_O_V4_V2 = 5973,
5989 : IMAGE_SAMPLE_LZ_O_V4_V3 = 5974,
5990 : IMAGE_SAMPLE_LZ_O_V4_V4 = 5975,
5991 : IMAGE_SAMPLE_LZ_V1_V1 = 5976,
5992 : IMAGE_SAMPLE_LZ_V1_V2 = 5977,
5993 : IMAGE_SAMPLE_LZ_V1_V3 = 5978,
5994 : IMAGE_SAMPLE_LZ_V1_V4 = 5979,
5995 : IMAGE_SAMPLE_LZ_V2_V1 = 5980,
5996 : IMAGE_SAMPLE_LZ_V2_V2 = 5981,
5997 : IMAGE_SAMPLE_LZ_V2_V3 = 5982,
5998 : IMAGE_SAMPLE_LZ_V2_V4 = 5983,
5999 : IMAGE_SAMPLE_LZ_V3_V1 = 5984,
6000 : IMAGE_SAMPLE_LZ_V3_V2 = 5985,
6001 : IMAGE_SAMPLE_LZ_V3_V3 = 5986,
6002 : IMAGE_SAMPLE_LZ_V3_V4 = 5987,
6003 : IMAGE_SAMPLE_LZ_V4_V1 = 5988,
6004 : IMAGE_SAMPLE_LZ_V4_V2 = 5989,
6005 : IMAGE_SAMPLE_LZ_V4_V3 = 5990,
6006 : IMAGE_SAMPLE_LZ_V4_V4 = 5991,
6007 : IMAGE_SAMPLE_L_O_V1_V2 = 5992,
6008 : IMAGE_SAMPLE_L_O_V1_V3 = 5993,
6009 : IMAGE_SAMPLE_L_O_V1_V4 = 5994,
6010 : IMAGE_SAMPLE_L_O_V1_V8 = 5995,
6011 : IMAGE_SAMPLE_L_O_V2_V2 = 5996,
6012 : IMAGE_SAMPLE_L_O_V2_V3 = 5997,
6013 : IMAGE_SAMPLE_L_O_V2_V4 = 5998,
6014 : IMAGE_SAMPLE_L_O_V2_V8 = 5999,
6015 : IMAGE_SAMPLE_L_O_V3_V2 = 6000,
6016 : IMAGE_SAMPLE_L_O_V3_V3 = 6001,
6017 : IMAGE_SAMPLE_L_O_V3_V4 = 6002,
6018 : IMAGE_SAMPLE_L_O_V3_V8 = 6003,
6019 : IMAGE_SAMPLE_L_O_V4_V2 = 6004,
6020 : IMAGE_SAMPLE_L_O_V4_V3 = 6005,
6021 : IMAGE_SAMPLE_L_O_V4_V4 = 6006,
6022 : IMAGE_SAMPLE_L_O_V4_V8 = 6007,
6023 : IMAGE_SAMPLE_L_V1_V1 = 6008,
6024 : IMAGE_SAMPLE_L_V1_V2 = 6009,
6025 : IMAGE_SAMPLE_L_V1_V3 = 6010,
6026 : IMAGE_SAMPLE_L_V1_V4 = 6011,
6027 : IMAGE_SAMPLE_L_V2_V1 = 6012,
6028 : IMAGE_SAMPLE_L_V2_V2 = 6013,
6029 : IMAGE_SAMPLE_L_V2_V3 = 6014,
6030 : IMAGE_SAMPLE_L_V2_V4 = 6015,
6031 : IMAGE_SAMPLE_L_V3_V1 = 6016,
6032 : IMAGE_SAMPLE_L_V3_V2 = 6017,
6033 : IMAGE_SAMPLE_L_V3_V3 = 6018,
6034 : IMAGE_SAMPLE_L_V3_V4 = 6019,
6035 : IMAGE_SAMPLE_L_V4_V1 = 6020,
6036 : IMAGE_SAMPLE_L_V4_V2 = 6021,
6037 : IMAGE_SAMPLE_L_V4_V3 = 6022,
6038 : IMAGE_SAMPLE_L_V4_V4 = 6023,
6039 : IMAGE_SAMPLE_O_V1_V2 = 6024,
6040 : IMAGE_SAMPLE_O_V1_V3 = 6025,
6041 : IMAGE_SAMPLE_O_V1_V4 = 6026,
6042 : IMAGE_SAMPLE_O_V2_V2 = 6027,
6043 : IMAGE_SAMPLE_O_V2_V3 = 6028,
6044 : IMAGE_SAMPLE_O_V2_V4 = 6029,
6045 : IMAGE_SAMPLE_O_V3_V2 = 6030,
6046 : IMAGE_SAMPLE_O_V3_V3 = 6031,
6047 : IMAGE_SAMPLE_O_V3_V4 = 6032,
6048 : IMAGE_SAMPLE_O_V4_V2 = 6033,
6049 : IMAGE_SAMPLE_O_V4_V3 = 6034,
6050 : IMAGE_SAMPLE_O_V4_V4 = 6035,
6051 : IMAGE_SAMPLE_V1_V1 = 6036,
6052 : IMAGE_SAMPLE_V1_V2 = 6037,
6053 : IMAGE_SAMPLE_V1_V3 = 6038,
6054 : IMAGE_SAMPLE_V1_V4 = 6039,
6055 : IMAGE_SAMPLE_V2_V1 = 6040,
6056 : IMAGE_SAMPLE_V2_V2 = 6041,
6057 : IMAGE_SAMPLE_V2_V3 = 6042,
6058 : IMAGE_SAMPLE_V2_V4 = 6043,
6059 : IMAGE_SAMPLE_V3_V1 = 6044,
6060 : IMAGE_SAMPLE_V3_V2 = 6045,
6061 : IMAGE_SAMPLE_V3_V3 = 6046,
6062 : IMAGE_SAMPLE_V3_V4 = 6047,
6063 : IMAGE_SAMPLE_V4_V1 = 6048,
6064 : IMAGE_SAMPLE_V4_V2 = 6049,
6065 : IMAGE_SAMPLE_V4_V3 = 6050,
6066 : IMAGE_SAMPLE_V4_V4 = 6051,
6067 : IMAGE_STORE_MIP_PCK_V1_V1 = 6052,
6068 : IMAGE_STORE_MIP_PCK_V1_V2 = 6053,
6069 : IMAGE_STORE_MIP_PCK_V1_V3 = 6054,
6070 : IMAGE_STORE_MIP_PCK_V1_V4 = 6055,
6071 : IMAGE_STORE_MIP_PCK_V2_V1 = 6056,
6072 : IMAGE_STORE_MIP_PCK_V2_V2 = 6057,
6073 : IMAGE_STORE_MIP_PCK_V2_V3 = 6058,
6074 : IMAGE_STORE_MIP_PCK_V2_V4 = 6059,
6075 : IMAGE_STORE_MIP_PCK_V3_V1 = 6060,
6076 : IMAGE_STORE_MIP_PCK_V3_V2 = 6061,
6077 : IMAGE_STORE_MIP_PCK_V3_V3 = 6062,
6078 : IMAGE_STORE_MIP_PCK_V3_V4 = 6063,
6079 : IMAGE_STORE_MIP_PCK_V4_V1 = 6064,
6080 : IMAGE_STORE_MIP_PCK_V4_V2 = 6065,
6081 : IMAGE_STORE_MIP_PCK_V4_V3 = 6066,
6082 : IMAGE_STORE_MIP_PCK_V4_V4 = 6067,
6083 : IMAGE_STORE_MIP_V1_V1 = 6068,
6084 : IMAGE_STORE_MIP_V1_V2 = 6069,
6085 : IMAGE_STORE_MIP_V1_V3 = 6070,
6086 : IMAGE_STORE_MIP_V1_V4 = 6071,
6087 : IMAGE_STORE_MIP_V2_V1 = 6072,
6088 : IMAGE_STORE_MIP_V2_V2 = 6073,
6089 : IMAGE_STORE_MIP_V2_V3 = 6074,
6090 : IMAGE_STORE_MIP_V2_V4 = 6075,
6091 : IMAGE_STORE_MIP_V3_V1 = 6076,
6092 : IMAGE_STORE_MIP_V3_V2 = 6077,
6093 : IMAGE_STORE_MIP_V3_V3 = 6078,
6094 : IMAGE_STORE_MIP_V3_V4 = 6079,
6095 : IMAGE_STORE_MIP_V4_V1 = 6080,
6096 : IMAGE_STORE_MIP_V4_V2 = 6081,
6097 : IMAGE_STORE_MIP_V4_V3 = 6082,
6098 : IMAGE_STORE_MIP_V4_V4 = 6083,
6099 : IMAGE_STORE_PCK_V1_V1 = 6084,
6100 : IMAGE_STORE_PCK_V1_V2 = 6085,
6101 : IMAGE_STORE_PCK_V1_V3 = 6086,
6102 : IMAGE_STORE_PCK_V1_V4 = 6087,
6103 : IMAGE_STORE_PCK_V2_V1 = 6088,
6104 : IMAGE_STORE_PCK_V2_V2 = 6089,
6105 : IMAGE_STORE_PCK_V2_V3 = 6090,
6106 : IMAGE_STORE_PCK_V2_V4 = 6091,
6107 : IMAGE_STORE_PCK_V3_V1 = 6092,
6108 : IMAGE_STORE_PCK_V3_V2 = 6093,
6109 : IMAGE_STORE_PCK_V3_V3 = 6094,
6110 : IMAGE_STORE_PCK_V3_V4 = 6095,
6111 : IMAGE_STORE_PCK_V4_V1 = 6096,
6112 : IMAGE_STORE_PCK_V4_V2 = 6097,
6113 : IMAGE_STORE_PCK_V4_V3 = 6098,
6114 : IMAGE_STORE_PCK_V4_V4 = 6099,
6115 : IMAGE_STORE_V1_V1 = 6100,
6116 : IMAGE_STORE_V1_V2 = 6101,
6117 : IMAGE_STORE_V1_V3 = 6102,
6118 : IMAGE_STORE_V1_V4 = 6103,
6119 : IMAGE_STORE_V2_V1 = 6104,
6120 : IMAGE_STORE_V2_V2 = 6105,
6121 : IMAGE_STORE_V2_V3 = 6106,
6122 : IMAGE_STORE_V2_V4 = 6107,
6123 : IMAGE_STORE_V3_V1 = 6108,
6124 : IMAGE_STORE_V3_V2 = 6109,
6125 : IMAGE_STORE_V3_V3 = 6110,
6126 : IMAGE_STORE_V3_V4 = 6111,
6127 : IMAGE_STORE_V4_V1 = 6112,
6128 : IMAGE_STORE_V4_V2 = 6113,
6129 : IMAGE_STORE_V4_V3 = 6114,
6130 : IMAGE_STORE_V4_V4 = 6115,
6131 : SCRATCH_LOAD_DWORDX2_SADDR_vi = 6116,
6132 : SCRATCH_LOAD_DWORDX2_vi = 6117,
6133 : SCRATCH_LOAD_DWORDX3_SADDR_vi = 6118,
6134 : SCRATCH_LOAD_DWORDX3_vi = 6119,
6135 : SCRATCH_LOAD_DWORDX4_SADDR_vi = 6120,
6136 : SCRATCH_LOAD_DWORDX4_vi = 6121,
6137 : SCRATCH_LOAD_DWORD_SADDR_vi = 6122,
6138 : SCRATCH_LOAD_DWORD_vi = 6123,
6139 : SCRATCH_LOAD_SBYTE_D16_HI_SADDR_vi = 6124,
6140 : SCRATCH_LOAD_SBYTE_D16_HI_vi = 6125,
6141 : SCRATCH_LOAD_SBYTE_D16_SADDR_vi = 6126,
6142 : SCRATCH_LOAD_SBYTE_D16_vi = 6127,
6143 : SCRATCH_LOAD_SBYTE_SADDR_vi = 6128,
6144 : SCRATCH_LOAD_SBYTE_vi = 6129,
6145 : SCRATCH_LOAD_SHORT_D16_HI_SADDR_vi = 6130,
6146 : SCRATCH_LOAD_SHORT_D16_HI_vi = 6131,
6147 : SCRATCH_LOAD_SHORT_D16_SADDR_vi = 6132,
6148 : SCRATCH_LOAD_SHORT_D16_vi = 6133,
6149 : SCRATCH_LOAD_SSHORT_SADDR_vi = 6134,
6150 : SCRATCH_LOAD_SSHORT_vi = 6135,
6151 : SCRATCH_LOAD_UBYTE_D16_HI_SADDR_vi = 6136,
6152 : SCRATCH_LOAD_UBYTE_D16_HI_vi = 6137,
6153 : SCRATCH_LOAD_UBYTE_D16_SADDR_vi = 6138,
6154 : SCRATCH_LOAD_UBYTE_D16_vi = 6139,
6155 : SCRATCH_LOAD_UBYTE_SADDR_vi = 6140,
6156 : SCRATCH_LOAD_UBYTE_vi = 6141,
6157 : SCRATCH_LOAD_USHORT_SADDR_vi = 6142,
6158 : SCRATCH_LOAD_USHORT_vi = 6143,
6159 : SCRATCH_STORE_BYTE_D16_HI_SADDR_vi = 6144,
6160 : SCRATCH_STORE_BYTE_D16_HI_vi = 6145,
6161 : SCRATCH_STORE_BYTE_SADDR_vi = 6146,
6162 : SCRATCH_STORE_BYTE_vi = 6147,
6163 : SCRATCH_STORE_DWORDX2_SADDR_vi = 6148,
6164 : SCRATCH_STORE_DWORDX2_vi = 6149,
6165 : SCRATCH_STORE_DWORDX3_SADDR_vi = 6150,
6166 : SCRATCH_STORE_DWORDX3_vi = 6151,
6167 : SCRATCH_STORE_DWORDX4_SADDR_vi = 6152,
6168 : SCRATCH_STORE_DWORDX4_vi = 6153,
6169 : SCRATCH_STORE_DWORD_SADDR_vi = 6154,
6170 : SCRATCH_STORE_DWORD_vi = 6155,
6171 : SCRATCH_STORE_SHORT_D16_HI_SADDR_vi = 6156,
6172 : SCRATCH_STORE_SHORT_D16_HI_vi = 6157,
6173 : SCRATCH_STORE_SHORT_SADDR_vi = 6158,
6174 : SCRATCH_STORE_SHORT_vi = 6159,
6175 : S_ABSDIFF_I32_si = 6160,
6176 : S_ABSDIFF_I32_vi = 6161,
6177 : S_ABS_I32_si = 6162,
6178 : S_ABS_I32_vi = 6163,
6179 : S_ADDC_U32_si = 6164,
6180 : S_ADDC_U32_vi = 6165,
6181 : S_ADDK_I32_si = 6166,
6182 : S_ADDK_I32_vi = 6167,
6183 : S_ADD_I32_si = 6168,
6184 : S_ADD_I32_vi = 6169,
6185 : S_ADD_U32_si = 6170,
6186 : S_ADD_U32_vi = 6171,
6187 : S_ANDN1_SAVEEXEC_B64_vi = 6172,
6188 : S_ANDN1_WREXEC_B64_vi = 6173,
6189 : S_ANDN2_B32_si = 6174,
6190 : S_ANDN2_B32_vi = 6175,
6191 : S_ANDN2_B64_si = 6176,
6192 : S_ANDN2_B64_vi = 6177,
6193 : S_ANDN2_SAVEEXEC_B64_si = 6178,
6194 : S_ANDN2_SAVEEXEC_B64_vi = 6179,
6195 : S_ANDN2_WREXEC_B64_vi = 6180,
6196 : S_AND_B32_si = 6181,
6197 : S_AND_B32_vi = 6182,
6198 : S_AND_B64_si = 6183,
6199 : S_AND_B64_vi = 6184,
6200 : S_AND_SAVEEXEC_B64_si = 6185,
6201 : S_AND_SAVEEXEC_B64_vi = 6186,
6202 : S_ASHR_I32_si = 6187,
6203 : S_ASHR_I32_vi = 6188,
6204 : S_ASHR_I64_si = 6189,
6205 : S_ASHR_I64_vi = 6190,
6206 : S_ATC_PROBE_BUFFER_IMM_vi = 6191,
6207 : S_ATC_PROBE_BUFFER_SGPR_vi = 6192,
6208 : S_ATC_PROBE_IMM_vi = 6193,
6209 : S_ATC_PROBE_SGPR_vi = 6194,
6210 : S_ATOMIC_ADD_IMM_RTN_vi = 6195,
6211 : S_ATOMIC_ADD_IMM_vi = 6196,
6212 : S_ATOMIC_ADD_SGPR_RTN_vi = 6197,
6213 : S_ATOMIC_ADD_SGPR_vi = 6198,
6214 : S_ATOMIC_ADD_X2_IMM_RTN_vi = 6199,
6215 : S_ATOMIC_ADD_X2_IMM_vi = 6200,
6216 : S_ATOMIC_ADD_X2_SGPR_RTN_vi = 6201,
6217 : S_ATOMIC_ADD_X2_SGPR_vi = 6202,
6218 : S_ATOMIC_AND_IMM_RTN_vi = 6203,
6219 : S_ATOMIC_AND_IMM_vi = 6204,
6220 : S_ATOMIC_AND_SGPR_RTN_vi = 6205,
6221 : S_ATOMIC_AND_SGPR_vi = 6206,
6222 : S_ATOMIC_AND_X2_IMM_RTN_vi = 6207,
6223 : S_ATOMIC_AND_X2_IMM_vi = 6208,
6224 : S_ATOMIC_AND_X2_SGPR_RTN_vi = 6209,
6225 : S_ATOMIC_AND_X2_SGPR_vi = 6210,
6226 : S_ATOMIC_CMPSWAP_IMM_RTN_vi = 6211,
6227 : S_ATOMIC_CMPSWAP_IMM_vi = 6212,
6228 : S_ATOMIC_CMPSWAP_SGPR_RTN_vi = 6213,
6229 : S_ATOMIC_CMPSWAP_SGPR_vi = 6214,
6230 : S_ATOMIC_CMPSWAP_X2_IMM_RTN_vi = 6215,
6231 : S_ATOMIC_CMPSWAP_X2_IMM_vi = 6216,
6232 : S_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi = 6217,
6233 : S_ATOMIC_CMPSWAP_X2_SGPR_vi = 6218,
6234 : S_ATOMIC_DEC_IMM_RTN_vi = 6219,
6235 : S_ATOMIC_DEC_IMM_vi = 6220,
6236 : S_ATOMIC_DEC_SGPR_RTN_vi = 6221,
6237 : S_ATOMIC_DEC_SGPR_vi = 6222,
6238 : S_ATOMIC_DEC_X2_IMM_RTN_vi = 6223,
6239 : S_ATOMIC_DEC_X2_IMM_vi = 6224,
6240 : S_ATOMIC_DEC_X2_SGPR_RTN_vi = 6225,
6241 : S_ATOMIC_DEC_X2_SGPR_vi = 6226,
6242 : S_ATOMIC_INC_IMM_RTN_vi = 6227,
6243 : S_ATOMIC_INC_IMM_vi = 6228,
6244 : S_ATOMIC_INC_SGPR_RTN_vi = 6229,
6245 : S_ATOMIC_INC_SGPR_vi = 6230,
6246 : S_ATOMIC_INC_X2_IMM_RTN_vi = 6231,
6247 : S_ATOMIC_INC_X2_IMM_vi = 6232,
6248 : S_ATOMIC_INC_X2_SGPR_RTN_vi = 6233,
6249 : S_ATOMIC_INC_X2_SGPR_vi = 6234,
6250 : S_ATOMIC_OR_IMM_RTN_vi = 6235,
6251 : S_ATOMIC_OR_IMM_vi = 6236,
6252 : S_ATOMIC_OR_SGPR_RTN_vi = 6237,
6253 : S_ATOMIC_OR_SGPR_vi = 6238,
6254 : S_ATOMIC_OR_X2_IMM_RTN_vi = 6239,
6255 : S_ATOMIC_OR_X2_IMM_vi = 6240,
6256 : S_ATOMIC_OR_X2_SGPR_RTN_vi = 6241,
6257 : S_ATOMIC_OR_X2_SGPR_vi = 6242,
6258 : S_ATOMIC_SMAX_IMM_RTN_vi = 6243,
6259 : S_ATOMIC_SMAX_IMM_vi = 6244,
6260 : S_ATOMIC_SMAX_SGPR_RTN_vi = 6245,
6261 : S_ATOMIC_SMAX_SGPR_vi = 6246,
6262 : S_ATOMIC_SMAX_X2_IMM_RTN_vi = 6247,
6263 : S_ATOMIC_SMAX_X2_IMM_vi = 6248,
6264 : S_ATOMIC_SMAX_X2_SGPR_RTN_vi = 6249,
6265 : S_ATOMIC_SMAX_X2_SGPR_vi = 6250,
6266 : S_ATOMIC_SMIN_IMM_RTN_vi = 6251,
6267 : S_ATOMIC_SMIN_IMM_vi = 6252,
6268 : S_ATOMIC_SMIN_SGPR_RTN_vi = 6253,
6269 : S_ATOMIC_SMIN_SGPR_vi = 6254,
6270 : S_ATOMIC_SMIN_X2_IMM_RTN_vi = 6255,
6271 : S_ATOMIC_SMIN_X2_IMM_vi = 6256,
6272 : S_ATOMIC_SMIN_X2_SGPR_RTN_vi = 6257,
6273 : S_ATOMIC_SMIN_X2_SGPR_vi = 6258,
6274 : S_ATOMIC_SUB_IMM_RTN_vi = 6259,
6275 : S_ATOMIC_SUB_IMM_vi = 6260,
6276 : S_ATOMIC_SUB_SGPR_RTN_vi = 6261,
6277 : S_ATOMIC_SUB_SGPR_vi = 6262,
6278 : S_ATOMIC_SUB_X2_IMM_RTN_vi = 6263,
6279 : S_ATOMIC_SUB_X2_IMM_vi = 6264,
6280 : S_ATOMIC_SUB_X2_SGPR_RTN_vi = 6265,
6281 : S_ATOMIC_SUB_X2_SGPR_vi = 6266,
6282 : S_ATOMIC_SWAP_IMM_RTN_vi = 6267,
6283 : S_ATOMIC_SWAP_IMM_vi = 6268,
6284 : S_ATOMIC_SWAP_SGPR_RTN_vi = 6269,
6285 : S_ATOMIC_SWAP_SGPR_vi = 6270,
6286 : S_ATOMIC_SWAP_X2_IMM_RTN_vi = 6271,
6287 : S_ATOMIC_SWAP_X2_IMM_vi = 6272,
6288 : S_ATOMIC_SWAP_X2_SGPR_RTN_vi = 6273,
6289 : S_ATOMIC_SWAP_X2_SGPR_vi = 6274,
6290 : S_ATOMIC_UMAX_IMM_RTN_vi = 6275,
6291 : S_ATOMIC_UMAX_IMM_vi = 6276,
6292 : S_ATOMIC_UMAX_SGPR_RTN_vi = 6277,
6293 : S_ATOMIC_UMAX_SGPR_vi = 6278,
6294 : S_ATOMIC_UMAX_X2_IMM_RTN_vi = 6279,
6295 : S_ATOMIC_UMAX_X2_IMM_vi = 6280,
6296 : S_ATOMIC_UMAX_X2_SGPR_RTN_vi = 6281,
6297 : S_ATOMIC_UMAX_X2_SGPR_vi = 6282,
6298 : S_ATOMIC_UMIN_IMM_RTN_vi = 6283,
6299 : S_ATOMIC_UMIN_IMM_vi = 6284,
6300 : S_ATOMIC_UMIN_SGPR_RTN_vi = 6285,
6301 : S_ATOMIC_UMIN_SGPR_vi = 6286,
6302 : S_ATOMIC_UMIN_X2_IMM_RTN_vi = 6287,
6303 : S_ATOMIC_UMIN_X2_IMM_vi = 6288,
6304 : S_ATOMIC_UMIN_X2_SGPR_RTN_vi = 6289,
6305 : S_ATOMIC_UMIN_X2_SGPR_vi = 6290,
6306 : S_ATOMIC_XOR_IMM_RTN_vi = 6291,
6307 : S_ATOMIC_XOR_IMM_vi = 6292,
6308 : S_ATOMIC_XOR_SGPR_RTN_vi = 6293,
6309 : S_ATOMIC_XOR_SGPR_vi = 6294,
6310 : S_ATOMIC_XOR_X2_IMM_RTN_vi = 6295,
6311 : S_ATOMIC_XOR_X2_IMM_vi = 6296,
6312 : S_ATOMIC_XOR_X2_SGPR_RTN_vi = 6297,
6313 : S_ATOMIC_XOR_X2_SGPR_vi = 6298,
6314 : S_BARRIER = 6299,
6315 : S_BCNT0_I32_B32_si = 6300,
6316 : S_BCNT0_I32_B32_vi = 6301,
6317 : S_BCNT0_I32_B64_si = 6302,
6318 : S_BCNT0_I32_B64_vi = 6303,
6319 : S_BCNT1_I32_B32_si = 6304,
6320 : S_BCNT1_I32_B32_vi = 6305,
6321 : S_BCNT1_I32_B64_si = 6306,
6322 : S_BCNT1_I32_B64_vi = 6307,
6323 : S_BFE_I32_si = 6308,
6324 : S_BFE_I32_vi = 6309,
6325 : S_BFE_I64_si = 6310,
6326 : S_BFE_I64_vi = 6311,
6327 : S_BFE_U32_si = 6312,
6328 : S_BFE_U32_vi = 6313,
6329 : S_BFE_U64_si = 6314,
6330 : S_BFE_U64_vi = 6315,
6331 : S_BFM_B32_si = 6316,
6332 : S_BFM_B32_vi = 6317,
6333 : S_BFM_B64_si = 6318,
6334 : S_BFM_B64_vi = 6319,
6335 : S_BITCMP0_B32 = 6320,
6336 : S_BITCMP0_B64 = 6321,
6337 : S_BITCMP1_B32 = 6322,
6338 : S_BITCMP1_B64 = 6323,
6339 : S_BITREPLICATE_B64_B32_vi = 6324,
6340 : S_BITSET0_B32_si = 6325,
6341 : S_BITSET0_B32_vi = 6326,
6342 : S_BITSET0_B64_si = 6327,
6343 : S_BITSET0_B64_vi = 6328,
6344 : S_BITSET1_B32_si = 6329,
6345 : S_BITSET1_B32_vi = 6330,
6346 : S_BITSET1_B64_si = 6331,
6347 : S_BITSET1_B64_vi = 6332,
6348 : S_BRANCH = 6333,
6349 : S_BREV_B32_si = 6334,
6350 : S_BREV_B32_vi = 6335,
6351 : S_BREV_B64_si = 6336,
6352 : S_BREV_B64_vi = 6337,
6353 : S_BUFFER_ATOMIC_ADD_IMM_RTN_vi = 6338,
6354 : S_BUFFER_ATOMIC_ADD_IMM_vi = 6339,
6355 : S_BUFFER_ATOMIC_ADD_SGPR_RTN_vi = 6340,
6356 : S_BUFFER_ATOMIC_ADD_SGPR_vi = 6341,
6357 : S_BUFFER_ATOMIC_ADD_X2_IMM_RTN_vi = 6342,
6358 : S_BUFFER_ATOMIC_ADD_X2_IMM_vi = 6343,
6359 : S_BUFFER_ATOMIC_ADD_X2_SGPR_RTN_vi = 6344,
6360 : S_BUFFER_ATOMIC_ADD_X2_SGPR_vi = 6345,
6361 : S_BUFFER_ATOMIC_AND_IMM_RTN_vi = 6346,
6362 : S_BUFFER_ATOMIC_AND_IMM_vi = 6347,
6363 : S_BUFFER_ATOMIC_AND_SGPR_RTN_vi = 6348,
6364 : S_BUFFER_ATOMIC_AND_SGPR_vi = 6349,
6365 : S_BUFFER_ATOMIC_AND_X2_IMM_RTN_vi = 6350,
6366 : S_BUFFER_ATOMIC_AND_X2_IMM_vi = 6351,
6367 : S_BUFFER_ATOMIC_AND_X2_SGPR_RTN_vi = 6352,
6368 : S_BUFFER_ATOMIC_AND_X2_SGPR_vi = 6353,
6369 : S_BUFFER_ATOMIC_CMPSWAP_IMM_RTN_vi = 6354,
6370 : S_BUFFER_ATOMIC_CMPSWAP_IMM_vi = 6355,
6371 : S_BUFFER_ATOMIC_CMPSWAP_SGPR_RTN_vi = 6356,
6372 : S_BUFFER_ATOMIC_CMPSWAP_SGPR_vi = 6357,
6373 : S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_RTN_vi = 6358,
6374 : S_BUFFER_ATOMIC_CMPSWAP_X2_IMM_vi = 6359,
6375 : S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_RTN_vi = 6360,
6376 : S_BUFFER_ATOMIC_CMPSWAP_X2_SGPR_vi = 6361,
6377 : S_BUFFER_ATOMIC_DEC_IMM_RTN_vi = 6362,
6378 : S_BUFFER_ATOMIC_DEC_IMM_vi = 6363,
6379 : S_BUFFER_ATOMIC_DEC_SGPR_RTN_vi = 6364,
6380 : S_BUFFER_ATOMIC_DEC_SGPR_vi = 6365,
6381 : S_BUFFER_ATOMIC_DEC_X2_IMM_RTN_vi = 6366,
6382 : S_BUFFER_ATOMIC_DEC_X2_IMM_vi = 6367,
6383 : S_BUFFER_ATOMIC_DEC_X2_SGPR_RTN_vi = 6368,
6384 : S_BUFFER_ATOMIC_DEC_X2_SGPR_vi = 6369,
6385 : S_BUFFER_ATOMIC_INC_IMM_RTN_vi = 6370,
6386 : S_BUFFER_ATOMIC_INC_IMM_vi = 6371,
6387 : S_BUFFER_ATOMIC_INC_SGPR_RTN_vi = 6372,
6388 : S_BUFFER_ATOMIC_INC_SGPR_vi = 6373,
6389 : S_BUFFER_ATOMIC_INC_X2_IMM_RTN_vi = 6374,
6390 : S_BUFFER_ATOMIC_INC_X2_IMM_vi = 6375,
6391 : S_BUFFER_ATOMIC_INC_X2_SGPR_RTN_vi = 6376,
6392 : S_BUFFER_ATOMIC_INC_X2_SGPR_vi = 6377,
6393 : S_BUFFER_ATOMIC_OR_IMM_RTN_vi = 6378,
6394 : S_BUFFER_ATOMIC_OR_IMM_vi = 6379,
6395 : S_BUFFER_ATOMIC_OR_SGPR_RTN_vi = 6380,
6396 : S_BUFFER_ATOMIC_OR_SGPR_vi = 6381,
6397 : S_BUFFER_ATOMIC_OR_X2_IMM_RTN_vi = 6382,
6398 : S_BUFFER_ATOMIC_OR_X2_IMM_vi = 6383,
6399 : S_BUFFER_ATOMIC_OR_X2_SGPR_RTN_vi = 6384,
6400 : S_BUFFER_ATOMIC_OR_X2_SGPR_vi = 6385,
6401 : S_BUFFER_ATOMIC_SMAX_IMM_RTN_vi = 6386,
6402 : S_BUFFER_ATOMIC_SMAX_IMM_vi = 6387,
6403 : S_BUFFER_ATOMIC_SMAX_SGPR_RTN_vi = 6388,
6404 : S_BUFFER_ATOMIC_SMAX_SGPR_vi = 6389,
6405 : S_BUFFER_ATOMIC_SMAX_X2_IMM_RTN_vi = 6390,
6406 : S_BUFFER_ATOMIC_SMAX_X2_IMM_vi = 6391,
6407 : S_BUFFER_ATOMIC_SMAX_X2_SGPR_RTN_vi = 6392,
6408 : S_BUFFER_ATOMIC_SMAX_X2_SGPR_vi = 6393,
6409 : S_BUFFER_ATOMIC_SMIN_IMM_RTN_vi = 6394,
6410 : S_BUFFER_ATOMIC_SMIN_IMM_vi = 6395,
6411 : S_BUFFER_ATOMIC_SMIN_SGPR_RTN_vi = 6396,
6412 : S_BUFFER_ATOMIC_SMIN_SGPR_vi = 6397,
6413 : S_BUFFER_ATOMIC_SMIN_X2_IMM_RTN_vi = 6398,
6414 : S_BUFFER_ATOMIC_SMIN_X2_IMM_vi = 6399,
6415 : S_BUFFER_ATOMIC_SMIN_X2_SGPR_RTN_vi = 6400,
6416 : S_BUFFER_ATOMIC_SMIN_X2_SGPR_vi = 6401,
6417 : S_BUFFER_ATOMIC_SUB_IMM_RTN_vi = 6402,
6418 : S_BUFFER_ATOMIC_SUB_IMM_vi = 6403,
6419 : S_BUFFER_ATOMIC_SUB_SGPR_RTN_vi = 6404,
6420 : S_BUFFER_ATOMIC_SUB_SGPR_vi = 6405,
6421 : S_BUFFER_ATOMIC_SUB_X2_IMM_RTN_vi = 6406,
6422 : S_BUFFER_ATOMIC_SUB_X2_IMM_vi = 6407,
6423 : S_BUFFER_ATOMIC_SUB_X2_SGPR_RTN_vi = 6408,
6424 : S_BUFFER_ATOMIC_SUB_X2_SGPR_vi = 6409,
6425 : S_BUFFER_ATOMIC_SWAP_IMM_RTN_vi = 6410,
6426 : S_BUFFER_ATOMIC_SWAP_IMM_vi = 6411,
6427 : S_BUFFER_ATOMIC_SWAP_SGPR_RTN_vi = 6412,
6428 : S_BUFFER_ATOMIC_SWAP_SGPR_vi = 6413,
6429 : S_BUFFER_ATOMIC_SWAP_X2_IMM_RTN_vi = 6414,
6430 : S_BUFFER_ATOMIC_SWAP_X2_IMM_vi = 6415,
6431 : S_BUFFER_ATOMIC_SWAP_X2_SGPR_RTN_vi = 6416,
6432 : S_BUFFER_ATOMIC_SWAP_X2_SGPR_vi = 6417,
6433 : S_BUFFER_ATOMIC_UMAX_IMM_RTN_vi = 6418,
6434 : S_BUFFER_ATOMIC_UMAX_IMM_vi = 6419,
6435 : S_BUFFER_ATOMIC_UMAX_SGPR_RTN_vi = 6420,
6436 : S_BUFFER_ATOMIC_UMAX_SGPR_vi = 6421,
6437 : S_BUFFER_ATOMIC_UMAX_X2_IMM_RTN_vi = 6422,
6438 : S_BUFFER_ATOMIC_UMAX_X2_IMM_vi = 6423,
6439 : S_BUFFER_ATOMIC_UMAX_X2_SGPR_RTN_vi = 6424,
6440 : S_BUFFER_ATOMIC_UMAX_X2_SGPR_vi = 6425,
6441 : S_BUFFER_ATOMIC_UMIN_IMM_RTN_vi = 6426,
6442 : S_BUFFER_ATOMIC_UMIN_IMM_vi = 6427,
6443 : S_BUFFER_ATOMIC_UMIN_SGPR_RTN_vi = 6428,
6444 : S_BUFFER_ATOMIC_UMIN_SGPR_vi = 6429,
6445 : S_BUFFER_ATOMIC_UMIN_X2_IMM_RTN_vi = 6430,
6446 : S_BUFFER_ATOMIC_UMIN_X2_IMM_vi = 6431,
6447 : S_BUFFER_ATOMIC_UMIN_X2_SGPR_RTN_vi = 6432,
6448 : S_BUFFER_ATOMIC_UMIN_X2_SGPR_vi = 6433,
6449 : S_BUFFER_ATOMIC_XOR_IMM_RTN_vi = 6434,
6450 : S_BUFFER_ATOMIC_XOR_IMM_vi = 6435,
6451 : S_BUFFER_ATOMIC_XOR_SGPR_RTN_vi = 6436,
6452 : S_BUFFER_ATOMIC_XOR_SGPR_vi = 6437,
6453 : S_BUFFER_ATOMIC_XOR_X2_IMM_RTN_vi = 6438,
6454 : S_BUFFER_ATOMIC_XOR_X2_IMM_vi = 6439,
6455 : S_BUFFER_ATOMIC_XOR_X2_SGPR_RTN_vi = 6440,
6456 : S_BUFFER_ATOMIC_XOR_X2_SGPR_vi = 6441,
6457 : S_BUFFER_LOAD_DWORDX16_IMM_ci = 6442,
6458 : S_BUFFER_LOAD_DWORDX16_IMM_si = 6443,
6459 : S_BUFFER_LOAD_DWORDX16_IMM_vi = 6444,
6460 : S_BUFFER_LOAD_DWORDX16_SGPR_si = 6445,
6461 : S_BUFFER_LOAD_DWORDX16_SGPR_vi = 6446,
6462 : S_BUFFER_LOAD_DWORDX2_IMM_ci = 6447,
6463 : S_BUFFER_LOAD_DWORDX2_IMM_si = 6448,
6464 : S_BUFFER_LOAD_DWORDX2_IMM_vi = 6449,
6465 : S_BUFFER_LOAD_DWORDX2_SGPR_si = 6450,
6466 : S_BUFFER_LOAD_DWORDX2_SGPR_vi = 6451,
6467 : S_BUFFER_LOAD_DWORDX4_IMM_ci = 6452,
6468 : S_BUFFER_LOAD_DWORDX4_IMM_si = 6453,
6469 : S_BUFFER_LOAD_DWORDX4_IMM_vi = 6454,
6470 : S_BUFFER_LOAD_DWORDX4_SGPR_si = 6455,
6471 : S_BUFFER_LOAD_DWORDX4_SGPR_vi = 6456,
6472 : S_BUFFER_LOAD_DWORDX8_IMM_ci = 6457,
6473 : S_BUFFER_LOAD_DWORDX8_IMM_si = 6458,
6474 : S_BUFFER_LOAD_DWORDX8_IMM_vi = 6459,
6475 : S_BUFFER_LOAD_DWORDX8_SGPR_si = 6460,
6476 : S_BUFFER_LOAD_DWORDX8_SGPR_vi = 6461,
6477 : S_BUFFER_LOAD_DWORD_IMM_ci = 6462,
6478 : S_BUFFER_LOAD_DWORD_IMM_si = 6463,
6479 : S_BUFFER_LOAD_DWORD_IMM_vi = 6464,
6480 : S_BUFFER_LOAD_DWORD_SGPR_si = 6465,
6481 : S_BUFFER_LOAD_DWORD_SGPR_vi = 6466,
6482 : S_BUFFER_STORE_DWORDX2_IMM_vi = 6467,
6483 : S_BUFFER_STORE_DWORDX2_SGPR_vi = 6468,
6484 : S_BUFFER_STORE_DWORDX4_IMM_vi = 6469,
6485 : S_BUFFER_STORE_DWORDX4_SGPR_vi = 6470,
6486 : S_BUFFER_STORE_DWORD_IMM_vi = 6471,
6487 : S_BUFFER_STORE_DWORD_SGPR_vi = 6472,
6488 : S_CALL_B64_vi = 6473,
6489 : S_CBRANCH_CDBGSYS = 6474,
6490 : S_CBRANCH_CDBGSYS_AND_USER = 6475,
6491 : S_CBRANCH_CDBGSYS_OR_USER = 6476,
6492 : S_CBRANCH_CDBGUSER = 6477,
6493 : S_CBRANCH_EXECNZ = 6478,
6494 : S_CBRANCH_EXECZ = 6479,
6495 : S_CBRANCH_G_FORK_si = 6480,
6496 : S_CBRANCH_G_FORK_vi = 6481,
6497 : S_CBRANCH_I_FORK_si = 6482,
6498 : S_CBRANCH_I_FORK_vi = 6483,
6499 : S_CBRANCH_JOIN_si = 6484,
6500 : S_CBRANCH_JOIN_vi = 6485,
6501 : S_CBRANCH_SCC0 = 6486,
6502 : S_CBRANCH_SCC1 = 6487,
6503 : S_CBRANCH_VCCNZ = 6488,
6504 : S_CBRANCH_VCCZ = 6489,
6505 : S_CMOVK_I32_si = 6490,
6506 : S_CMOVK_I32_vi = 6491,
6507 : S_CMOV_B32_si = 6492,
6508 : S_CMOV_B32_vi = 6493,
6509 : S_CMOV_B64_si = 6494,
6510 : S_CMOV_B64_vi = 6495,
6511 : S_CMPK_EQ_I32_si = 6496,
6512 : S_CMPK_EQ_I32_vi = 6497,
6513 : S_CMPK_EQ_U32_si = 6498,
6514 : S_CMPK_EQ_U32_vi = 6499,
6515 : S_CMPK_GE_I32_si = 6500,
6516 : S_CMPK_GE_I32_vi = 6501,
6517 : S_CMPK_GE_U32_si = 6502,
6518 : S_CMPK_GE_U32_vi = 6503,
6519 : S_CMPK_GT_I32_si = 6504,
6520 : S_CMPK_GT_I32_vi = 6505,
6521 : S_CMPK_GT_U32_si = 6506,
6522 : S_CMPK_GT_U32_vi = 6507,
6523 : S_CMPK_LE_I32_si = 6508,
6524 : S_CMPK_LE_I32_vi = 6509,
6525 : S_CMPK_LE_U32_si = 6510,
6526 : S_CMPK_LE_U32_vi = 6511,
6527 : S_CMPK_LG_I32_si = 6512,
6528 : S_CMPK_LG_I32_vi = 6513,
6529 : S_CMPK_LG_U32_si = 6514,
6530 : S_CMPK_LG_U32_vi = 6515,
6531 : S_CMPK_LT_I32_si = 6516,
6532 : S_CMPK_LT_I32_vi = 6517,
6533 : S_CMPK_LT_U32_si = 6518,
6534 : S_CMPK_LT_U32_vi = 6519,
6535 : S_CMP_EQ_I32 = 6520,
6536 : S_CMP_EQ_U32 = 6521,
6537 : S_CMP_EQ_U64 = 6522,
6538 : S_CMP_GE_I32 = 6523,
6539 : S_CMP_GE_U32 = 6524,
6540 : S_CMP_GT_I32 = 6525,
6541 : S_CMP_GT_U32 = 6526,
6542 : S_CMP_LE_I32 = 6527,
6543 : S_CMP_LE_U32 = 6528,
6544 : S_CMP_LG_I32 = 6529,
6545 : S_CMP_LG_U32 = 6530,
6546 : S_CMP_LG_U64 = 6531,
6547 : S_CMP_LT_I32 = 6532,
6548 : S_CMP_LT_U32 = 6533,
6549 : S_CSELECT_B32_si = 6534,
6550 : S_CSELECT_B32_vi = 6535,
6551 : S_CSELECT_B64_si = 6536,
6552 : S_CSELECT_B64_vi = 6537,
6553 : S_DCACHE_DISCARD_IMM_vi = 6538,
6554 : S_DCACHE_DISCARD_SGPR_vi = 6539,
6555 : S_DCACHE_DISCARD_X2_IMM_vi = 6540,
6556 : S_DCACHE_DISCARD_X2_SGPR_vi = 6541,
6557 : S_DCACHE_INV_VOL_ci = 6542,
6558 : S_DCACHE_INV_VOL_vi = 6543,
6559 : S_DCACHE_INV_si = 6544,
6560 : S_DCACHE_INV_vi = 6545,
6561 : S_DCACHE_WB_VOL_vi = 6546,
6562 : S_DCACHE_WB_vi = 6547,
6563 : S_DECPERFLEVEL = 6548,
6564 : S_ENDPGM = 6549,
6565 : S_ENDPGM_ORDERED_PS_DONE = 6550,
6566 : S_ENDPGM_SAVED = 6551,
6567 : S_FF0_I32_B32_si = 6552,
6568 : S_FF0_I32_B32_vi = 6553,
6569 : S_FF0_I32_B64_si = 6554,
6570 : S_FF0_I32_B64_vi = 6555,
6571 : S_FF1_I32_B32_si = 6556,
6572 : S_FF1_I32_B32_vi = 6557,
6573 : S_FF1_I32_B64_si = 6558,
6574 : S_FF1_I32_B64_vi = 6559,
6575 : S_FLBIT_I32_B32_si = 6560,
6576 : S_FLBIT_I32_B32_vi = 6561,
6577 : S_FLBIT_I32_B64_si = 6562,
6578 : S_FLBIT_I32_B64_vi = 6563,
6579 : S_FLBIT_I32_I64_si = 6564,
6580 : S_FLBIT_I32_I64_vi = 6565,
6581 : S_FLBIT_I32_si = 6566,
6582 : S_FLBIT_I32_vi = 6567,
6583 : S_GETPC_B64_si = 6568,
6584 : S_GETPC_B64_vi = 6569,
6585 : S_GETREG_B32_si = 6570,
6586 : S_GETREG_B32_vi = 6571,
6587 : S_ICACHE_INV = 6572,
6588 : S_INCPERFLEVEL = 6573,
6589 : S_LOAD_DWORDX16_IMM_ci = 6574,
6590 : S_LOAD_DWORDX16_IMM_si = 6575,
6591 : S_LOAD_DWORDX16_IMM_vi = 6576,
6592 : S_LOAD_DWORDX16_SGPR_si = 6577,
6593 : S_LOAD_DWORDX16_SGPR_vi = 6578,
6594 : S_LOAD_DWORDX2_IMM_ci = 6579,
6595 : S_LOAD_DWORDX2_IMM_si = 6580,
6596 : S_LOAD_DWORDX2_IMM_vi = 6581,
6597 : S_LOAD_DWORDX2_SGPR_si = 6582,
6598 : S_LOAD_DWORDX2_SGPR_vi = 6583,
6599 : S_LOAD_DWORDX4_IMM_ci = 6584,
6600 : S_LOAD_DWORDX4_IMM_si = 6585,
6601 : S_LOAD_DWORDX4_IMM_vi = 6586,
6602 : S_LOAD_DWORDX4_SGPR_si = 6587,
6603 : S_LOAD_DWORDX4_SGPR_vi = 6588,
6604 : S_LOAD_DWORDX8_IMM_ci = 6589,
6605 : S_LOAD_DWORDX8_IMM_si = 6590,
6606 : S_LOAD_DWORDX8_IMM_vi = 6591,
6607 : S_LOAD_DWORDX8_SGPR_si = 6592,
6608 : S_LOAD_DWORDX8_SGPR_vi = 6593,
6609 : S_LOAD_DWORD_IMM_ci = 6594,
6610 : S_LOAD_DWORD_IMM_si = 6595,
6611 : S_LOAD_DWORD_IMM_vi = 6596,
6612 : S_LOAD_DWORD_SGPR_si = 6597,
6613 : S_LOAD_DWORD_SGPR_vi = 6598,
6614 : S_LSHL1_ADD_U32_vi = 6599,
6615 : S_LSHL2_ADD_U32_vi = 6600,
6616 : S_LSHL3_ADD_U32_vi = 6601,
6617 : S_LSHL4_ADD_U32_vi = 6602,
6618 : S_LSHL_B32_si = 6603,
6619 : S_LSHL_B32_vi = 6604,
6620 : S_LSHL_B64_si = 6605,
6621 : S_LSHL_B64_vi = 6606,
6622 : S_LSHR_B32_si = 6607,
6623 : S_LSHR_B32_vi = 6608,
6624 : S_LSHR_B64_si = 6609,
6625 : S_LSHR_B64_vi = 6610,
6626 : S_MAX_I32_si = 6611,
6627 : S_MAX_I32_vi = 6612,
6628 : S_MAX_U32_si = 6613,
6629 : S_MAX_U32_vi = 6614,
6630 : S_MEMREALTIME_vi = 6615,
6631 : S_MEMTIME_si = 6616,
6632 : S_MEMTIME_vi = 6617,
6633 : S_MIN_I32_si = 6618,
6634 : S_MIN_I32_vi = 6619,
6635 : S_MIN_U32_si = 6620,
6636 : S_MIN_U32_vi = 6621,
6637 : S_MOVK_I32_si = 6622,
6638 : S_MOVK_I32_vi = 6623,
6639 : S_MOVRELD_B32_si = 6624,
6640 : S_MOVRELD_B32_vi = 6625,
6641 : S_MOVRELD_B64_si = 6626,
6642 : S_MOVRELD_B64_vi = 6627,
6643 : S_MOVRELS_B32_si = 6628,
6644 : S_MOVRELS_B32_vi = 6629,
6645 : S_MOVRELS_B64_si = 6630,
6646 : S_MOVRELS_B64_vi = 6631,
6647 : S_MOV_B32_si = 6632,
6648 : S_MOV_B32_vi = 6633,
6649 : S_MOV_B64_si = 6634,
6650 : S_MOV_B64_vi = 6635,
6651 : S_MOV_FED_B32_si = 6636,
6652 : S_MOV_FED_B32_vi = 6637,
6653 : S_MOV_REGRD_B32_si = 6638,
6654 : S_MOV_REGRD_B32_vi = 6639,
6655 : S_MULK_I32_si = 6640,
6656 : S_MULK_I32_vi = 6641,
6657 : S_MUL_HI_I32_vi = 6642,
6658 : S_MUL_HI_U32_vi = 6643,
6659 : S_MUL_I32_si = 6644,
6660 : S_MUL_I32_vi = 6645,
6661 : S_NAND_B32_si = 6646,
6662 : S_NAND_B32_vi = 6647,
6663 : S_NAND_B64_si = 6648,
6664 : S_NAND_B64_vi = 6649,
6665 : S_NAND_SAVEEXEC_B64_si = 6650,
6666 : S_NAND_SAVEEXEC_B64_vi = 6651,
6667 : S_NOP = 6652,
6668 : S_NOR_B32_si = 6653,
6669 : S_NOR_B32_vi = 6654,
6670 : S_NOR_B64_si = 6655,
6671 : S_NOR_B64_vi = 6656,
6672 : S_NOR_SAVEEXEC_B64_si = 6657,
6673 : S_NOR_SAVEEXEC_B64_vi = 6658,
6674 : S_NOT_B32_si = 6659,
6675 : S_NOT_B32_vi = 6660,
6676 : S_NOT_B64_si = 6661,
6677 : S_NOT_B64_vi = 6662,
6678 : S_ORN1_SAVEEXEC_B64_vi = 6663,
6679 : S_ORN2_B32_si = 6664,
6680 : S_ORN2_B32_vi = 6665,
6681 : S_ORN2_B64_si = 6666,
6682 : S_ORN2_B64_vi = 6667,
6683 : S_ORN2_SAVEEXEC_B64_si = 6668,
6684 : S_ORN2_SAVEEXEC_B64_vi = 6669,
6685 : S_OR_B32_si = 6670,
6686 : S_OR_B32_vi = 6671,
6687 : S_OR_B64_si = 6672,
6688 : S_OR_B64_vi = 6673,
6689 : S_OR_SAVEEXEC_B64_si = 6674,
6690 : S_OR_SAVEEXEC_B64_vi = 6675,
6691 : S_PACK_HH_B32_B16_vi = 6676,
6692 : S_PACK_LH_B32_B16_vi = 6677,
6693 : S_PACK_LL_B32_B16_vi = 6678,
6694 : S_QUADMASK_B32_si = 6679,
6695 : S_QUADMASK_B32_vi = 6680,
6696 : S_QUADMASK_B64_si = 6681,
6697 : S_QUADMASK_B64_vi = 6682,
6698 : S_RFE_B64_si = 6683,
6699 : S_RFE_B64_vi = 6684,
6700 : S_RFE_RESTORE_B64_vi = 6685,
6701 : S_SCRATCH_LOAD_DWORDX2_IMM_vi = 6686,
6702 : S_SCRATCH_LOAD_DWORDX2_SGPR_vi = 6687,
6703 : S_SCRATCH_LOAD_DWORDX4_IMM_vi = 6688,
6704 : S_SCRATCH_LOAD_DWORDX4_SGPR_vi = 6689,
6705 : S_SCRATCH_LOAD_DWORD_IMM_vi = 6690,
6706 : S_SCRATCH_LOAD_DWORD_SGPR_vi = 6691,
6707 : S_SCRATCH_STORE_DWORDX2_IMM_vi = 6692,
6708 : S_SCRATCH_STORE_DWORDX2_SGPR_vi = 6693,
6709 : S_SCRATCH_STORE_DWORDX4_IMM_vi = 6694,
6710 : S_SCRATCH_STORE_DWORDX4_SGPR_vi = 6695,
6711 : S_SCRATCH_STORE_DWORD_IMM_vi = 6696,
6712 : S_SCRATCH_STORE_DWORD_SGPR_vi = 6697,
6713 : S_SENDMSG = 6698,
6714 : S_SENDMSGHALT = 6699,
6715 : S_SETHALT = 6700,
6716 : S_SETKILL = 6701,
6717 : S_SETPC_B64_si = 6702,
6718 : S_SETPC_B64_vi = 6703,
6719 : S_SETPRIO = 6704,
6720 : S_SETREG_B32_si = 6705,
6721 : S_SETREG_B32_vi = 6706,
6722 : S_SETREG_IMM32_B32_si = 6707,
6723 : S_SETREG_IMM32_B32_vi = 6708,
6724 : S_SETVSKIP = 6709,
6725 : S_SET_GPR_IDX_IDX_vi = 6710,
6726 : S_SET_GPR_IDX_MODE = 6711,
6727 : S_SET_GPR_IDX_OFF = 6712,
6728 : S_SET_GPR_IDX_ON = 6713,
6729 : S_SEXT_I32_I16_si = 6714,
6730 : S_SEXT_I32_I16_vi = 6715,
6731 : S_SEXT_I32_I8_si = 6716,
6732 : S_SEXT_I32_I8_vi = 6717,
6733 : S_SLEEP = 6718,
6734 : S_STORE_DWORDX2_IMM_vi = 6719,
6735 : S_STORE_DWORDX2_SGPR_vi = 6720,
6736 : S_STORE_DWORDX4_IMM_vi = 6721,
6737 : S_STORE_DWORDX4_SGPR_vi = 6722,
6738 : S_STORE_DWORD_IMM_vi = 6723,
6739 : S_STORE_DWORD_SGPR_vi = 6724,
6740 : S_SUBB_U32_si = 6725,
6741 : S_SUBB_U32_vi = 6726,
6742 : S_SUB_I32_si = 6727,
6743 : S_SUB_I32_vi = 6728,
6744 : S_SUB_U32_si = 6729,
6745 : S_SUB_U32_vi = 6730,
6746 : S_SWAPPC_B64_si = 6731,
6747 : S_SWAPPC_B64_vi = 6732,
6748 : S_TRAP = 6733,
6749 : S_TTRACEDATA = 6734,
6750 : S_WAITCNT = 6735,
6751 : S_WAKEUP = 6736,
6752 : S_WQM_B32_si = 6737,
6753 : S_WQM_B32_vi = 6738,
6754 : S_WQM_B64_si = 6739,
6755 : S_WQM_B64_vi = 6740,
6756 : S_XNOR_B32_si = 6741,
6757 : S_XNOR_B32_vi = 6742,
6758 : S_XNOR_B64_si = 6743,
6759 : S_XNOR_B64_vi = 6744,
6760 : S_XNOR_SAVEEXEC_B64_si = 6745,
6761 : S_XNOR_SAVEEXEC_B64_vi = 6746,
6762 : S_XOR_B32_si = 6747,
6763 : S_XOR_B32_vi = 6748,
6764 : S_XOR_B64_si = 6749,
6765 : S_XOR_B64_vi = 6750,
6766 : S_XOR_SAVEEXEC_B64_si = 6751,
6767 : S_XOR_SAVEEXEC_B64_vi = 6752,
6768 : TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN_vi = 6753,
6769 : TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN_vi = 6754,
6770 : TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN_vi = 6755,
6771 : TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET_vi = 6756,
6772 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80 = 6757,
6773 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80 = 6758,
6774 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80 = 6759,
6775 : TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80 = 6760,
6776 : TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN_vi = 6761,
6777 : TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN_vi = 6762,
6778 : TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN_vi = 6763,
6779 : TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET_vi = 6764,
6780 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80 = 6765,
6781 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80 = 6766,
6782 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80 = 6767,
6783 : TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80 = 6768,
6784 : TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN_vi = 6769,
6785 : TBUFFER_LOAD_FORMAT_D16_XY_IDXEN_vi = 6770,
6786 : TBUFFER_LOAD_FORMAT_D16_XY_OFFEN_vi = 6771,
6787 : TBUFFER_LOAD_FORMAT_D16_XY_OFFSET_vi = 6772,
6788 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN_gfx80 = 6773,
6789 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN_gfx80 = 6774,
6790 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN_gfx80 = 6775,
6791 : TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET_gfx80 = 6776,
6792 : TBUFFER_LOAD_FORMAT_D16_X_BOTHEN_vi = 6777,
6793 : TBUFFER_LOAD_FORMAT_D16_X_IDXEN_vi = 6778,
6794 : TBUFFER_LOAD_FORMAT_D16_X_OFFEN_vi = 6779,
6795 : TBUFFER_LOAD_FORMAT_D16_X_OFFSET_vi = 6780,
6796 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN_gfx80 = 6781,
6797 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN_gfx80 = 6782,
6798 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN_gfx80 = 6783,
6799 : TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET_gfx80 = 6784,
6800 : TBUFFER_LOAD_FORMAT_XYZW_ADDR64_si = 6785,
6801 : TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_si = 6786,
6802 : TBUFFER_LOAD_FORMAT_XYZW_BOTHEN_vi = 6787,
6803 : TBUFFER_LOAD_FORMAT_XYZW_IDXEN_si = 6788,
6804 : TBUFFER_LOAD_FORMAT_XYZW_IDXEN_vi = 6789,
6805 : TBUFFER_LOAD_FORMAT_XYZW_OFFEN_si = 6790,
6806 : TBUFFER_LOAD_FORMAT_XYZW_OFFEN_vi = 6791,
6807 : TBUFFER_LOAD_FORMAT_XYZW_OFFSET_si = 6792,
6808 : TBUFFER_LOAD_FORMAT_XYZW_OFFSET_vi = 6793,
6809 : TBUFFER_LOAD_FORMAT_XYZ_ADDR64_si = 6794,
6810 : TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_si = 6795,
6811 : TBUFFER_LOAD_FORMAT_XYZ_BOTHEN_vi = 6796,
6812 : TBUFFER_LOAD_FORMAT_XYZ_IDXEN_si = 6797,
6813 : TBUFFER_LOAD_FORMAT_XYZ_IDXEN_vi = 6798,
6814 : TBUFFER_LOAD_FORMAT_XYZ_OFFEN_si = 6799,
6815 : TBUFFER_LOAD_FORMAT_XYZ_OFFEN_vi = 6800,
6816 : TBUFFER_LOAD_FORMAT_XYZ_OFFSET_si = 6801,
6817 : TBUFFER_LOAD_FORMAT_XYZ_OFFSET_vi = 6802,
6818 : TBUFFER_LOAD_FORMAT_XY_ADDR64_si = 6803,
6819 : TBUFFER_LOAD_FORMAT_XY_BOTHEN_si = 6804,
6820 : TBUFFER_LOAD_FORMAT_XY_BOTHEN_vi = 6805,
6821 : TBUFFER_LOAD_FORMAT_XY_IDXEN_si = 6806,
6822 : TBUFFER_LOAD_FORMAT_XY_IDXEN_vi = 6807,
6823 : TBUFFER_LOAD_FORMAT_XY_OFFEN_si = 6808,
6824 : TBUFFER_LOAD_FORMAT_XY_OFFEN_vi = 6809,
6825 : TBUFFER_LOAD_FORMAT_XY_OFFSET_si = 6810,
6826 : TBUFFER_LOAD_FORMAT_XY_OFFSET_vi = 6811,
6827 : TBUFFER_LOAD_FORMAT_X_ADDR64_si = 6812,
6828 : TBUFFER_LOAD_FORMAT_X_BOTHEN_si = 6813,
6829 : TBUFFER_LOAD_FORMAT_X_BOTHEN_vi = 6814,
6830 : TBUFFER_LOAD_FORMAT_X_IDXEN_si = 6815,
6831 : TBUFFER_LOAD_FORMAT_X_IDXEN_vi = 6816,
6832 : TBUFFER_LOAD_FORMAT_X_OFFEN_si = 6817,
6833 : TBUFFER_LOAD_FORMAT_X_OFFEN_vi = 6818,
6834 : TBUFFER_LOAD_FORMAT_X_OFFSET_si = 6819,
6835 : TBUFFER_LOAD_FORMAT_X_OFFSET_vi = 6820,
6836 : TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_vi = 6821,
6837 : TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_vi = 6822,
6838 : TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_vi = 6823,
6839 : TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_vi = 6824,
6840 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_gfx80 = 6825,
6841 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_gfx80 = 6826,
6842 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_gfx80 = 6827,
6843 : TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_gfx80 = 6828,
6844 : TBUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_vi = 6829,
6845 : TBUFFER_STORE_FORMAT_D16_XYZ_IDXEN_vi = 6830,
6846 : TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_vi = 6831,
6847 : TBUFFER_STORE_FORMAT_D16_XYZ_OFFSET_vi = 6832,
6848 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_gfx80 = 6833,
6849 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_gfx80 = 6834,
6850 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_gfx80 = 6835,
6851 : TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_gfx80 = 6836,
6852 : TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_vi = 6837,
6853 : TBUFFER_STORE_FORMAT_D16_XY_IDXEN_vi = 6838,
6854 : TBUFFER_STORE_FORMAT_D16_XY_OFFEN_vi = 6839,
6855 : TBUFFER_STORE_FORMAT_D16_XY_OFFSET_vi = 6840,
6856 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_gfx80 = 6841,
6857 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_gfx80 = 6842,
6858 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_gfx80 = 6843,
6859 : TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_gfx80 = 6844,
6860 : TBUFFER_STORE_FORMAT_D16_X_BOTHEN_vi = 6845,
6861 : TBUFFER_STORE_FORMAT_D16_X_IDXEN_vi = 6846,
6862 : TBUFFER_STORE_FORMAT_D16_X_OFFEN_vi = 6847,
6863 : TBUFFER_STORE_FORMAT_D16_X_OFFSET_vi = 6848,
6864 : TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_gfx80 = 6849,
6865 : TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_gfx80 = 6850,
6866 : TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_gfx80 = 6851,
6867 : TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_gfx80 = 6852,
6868 : TBUFFER_STORE_FORMAT_XYZW_ADDR64_si = 6853,
6869 : TBUFFER_STORE_FORMAT_XYZW_BOTHEN_si = 6854,
6870 : TBUFFER_STORE_FORMAT_XYZW_BOTHEN_vi = 6855,
6871 : TBUFFER_STORE_FORMAT_XYZW_IDXEN_si = 6856,
6872 : TBUFFER_STORE_FORMAT_XYZW_IDXEN_vi = 6857,
6873 : TBUFFER_STORE_FORMAT_XYZW_OFFEN_si = 6858,
6874 : TBUFFER_STORE_FORMAT_XYZW_OFFEN_vi = 6859,
6875 : TBUFFER_STORE_FORMAT_XYZW_OFFSET_si = 6860,
6876 : TBUFFER_STORE_FORMAT_XYZW_OFFSET_vi = 6861,
6877 : TBUFFER_STORE_FORMAT_XYZ_ADDR64_si = 6862,
6878 : TBUFFER_STORE_FORMAT_XYZ_BOTHEN_si = 6863,
6879 : TBUFFER_STORE_FORMAT_XYZ_BOTHEN_vi = 6864,
6880 : TBUFFER_STORE_FORMAT_XYZ_IDXEN_si = 6865,
6881 : TBUFFER_STORE_FORMAT_XYZ_IDXEN_vi = 6866,
6882 : TBUFFER_STORE_FORMAT_XYZ_OFFEN_si = 6867,
6883 : TBUFFER_STORE_FORMAT_XYZ_OFFEN_vi = 6868,
6884 : TBUFFER_STORE_FORMAT_XYZ_OFFSET_si = 6869,
6885 : TBUFFER_STORE_FORMAT_XYZ_OFFSET_vi = 6870,
6886 : TBUFFER_STORE_FORMAT_XY_ADDR64_si = 6871,
6887 : TBUFFER_STORE_FORMAT_XY_BOTHEN_si = 6872,
6888 : TBUFFER_STORE_FORMAT_XY_BOTHEN_vi = 6873,
6889 : TBUFFER_STORE_FORMAT_XY_IDXEN_si = 6874,
6890 : TBUFFER_STORE_FORMAT_XY_IDXEN_vi = 6875,
6891 : TBUFFER_STORE_FORMAT_XY_OFFEN_si = 6876,
6892 : TBUFFER_STORE_FORMAT_XY_OFFEN_vi = 6877,
6893 : TBUFFER_STORE_FORMAT_XY_OFFSET_si = 6878,
6894 : TBUFFER_STORE_FORMAT_XY_OFFSET_vi = 6879,
6895 : TBUFFER_STORE_FORMAT_X_ADDR64_si = 6880,
6896 : TBUFFER_STORE_FORMAT_X_BOTHEN_si = 6881,
6897 : TBUFFER_STORE_FORMAT_X_BOTHEN_vi = 6882,
6898 : TBUFFER_STORE_FORMAT_X_IDXEN_si = 6883,
6899 : TBUFFER_STORE_FORMAT_X_IDXEN_vi = 6884,
6900 : TBUFFER_STORE_FORMAT_X_OFFEN_si = 6885,
6901 : TBUFFER_STORE_FORMAT_X_OFFEN_vi = 6886,
6902 : TBUFFER_STORE_FORMAT_X_OFFSET_si = 6887,
6903 : TBUFFER_STORE_FORMAT_X_OFFSET_vi = 6888,
6904 : V_ADD3_U32_vi = 6889,
6905 : V_ADDC_CO_U32_dpp_gfx9 = 6890,
6906 : V_ADDC_CO_U32_e32_gfx9 = 6891,
6907 : V_ADDC_CO_U32_e64_gfx9 = 6892,
6908 : V_ADDC_CO_U32_sdwa_gfx9 = 6893,
6909 : V_ADDC_U32_dpp = 6894,
6910 : V_ADDC_U32_e32_si = 6895,
6911 : V_ADDC_U32_e32_vi = 6896,
6912 : V_ADDC_U32_e64_si = 6897,
6913 : V_ADDC_U32_e64_vi = 6898,
6914 : V_ADDC_U32_sdwa_vi = 6899,
6915 : V_ADD_CO_U32_dpp_gfx9 = 6900,
6916 : V_ADD_CO_U32_e32_gfx9 = 6901,
6917 : V_ADD_CO_U32_e64_gfx9 = 6902,
6918 : V_ADD_CO_U32_sdwa_gfx9 = 6903,
6919 : V_ADD_F16_dpp = 6904,
6920 : V_ADD_F16_e32_vi = 6905,
6921 : V_ADD_F16_e64_vi = 6906,
6922 : V_ADD_F16_sdwa_gfx9 = 6907,
6923 : V_ADD_F16_sdwa_vi = 6908,
6924 : V_ADD_F32_dpp = 6909,
6925 : V_ADD_F32_e32_si = 6910,
6926 : V_ADD_F32_e32_vi = 6911,
6927 : V_ADD_F32_e64_si = 6912,
6928 : V_ADD_F32_e64_vi = 6913,
6929 : V_ADD_F32_sdwa_gfx9 = 6914,
6930 : V_ADD_F32_sdwa_vi = 6915,
6931 : V_ADD_F64_si = 6916,
6932 : V_ADD_F64_vi = 6917,
6933 : V_ADD_I16_vi = 6918,
6934 : V_ADD_I32_e32_si = 6919,
6935 : V_ADD_I32_e64_si = 6920,
6936 : V_ADD_I32_gfx9_gfx9 = 6921,
6937 : V_ADD_LSHL_U32_vi = 6922,
6938 : V_ADD_U16_dpp = 6923,
6939 : V_ADD_U16_e32_vi = 6924,
6940 : V_ADD_U16_e64_vi = 6925,
6941 : V_ADD_U16_sdwa_gfx9 = 6926,
6942 : V_ADD_U16_sdwa_vi = 6927,
6943 : V_ADD_U32_dpp = 6928,
6944 : V_ADD_U32_dpp_gfx9 = 6929,
6945 : V_ADD_U32_e32_gfx9 = 6930,
6946 : V_ADD_U32_e32_vi = 6931,
6947 : V_ADD_U32_e64_gfx9 = 6932,
6948 : V_ADD_U32_e64_vi = 6933,
6949 : V_ADD_U32_sdwa_gfx9 = 6934,
6950 : V_ADD_U32_sdwa_vi = 6935,
6951 : V_ALIGNBIT_B32_si = 6936,
6952 : V_ALIGNBIT_B32_vi = 6937,
6953 : V_ALIGNBYTE_B32_si = 6938,
6954 : V_ALIGNBYTE_B32_vi = 6939,
6955 : V_AND_B32_dpp = 6940,
6956 : V_AND_B32_e32_si = 6941,
6957 : V_AND_B32_e32_vi = 6942,
6958 : V_AND_B32_e64_si = 6943,
6959 : V_AND_B32_e64_vi = 6944,
6960 : V_AND_B32_sdwa_gfx9 = 6945,
6961 : V_AND_B32_sdwa_vi = 6946,
6962 : V_AND_OR_B32_vi = 6947,
6963 : V_ASHRREV_I16_dpp = 6948,
6964 : V_ASHRREV_I16_e32_vi = 6949,
6965 : V_ASHRREV_I16_e64_vi = 6950,
6966 : V_ASHRREV_I16_sdwa_gfx9 = 6951,
6967 : V_ASHRREV_I16_sdwa_vi = 6952,
6968 : V_ASHRREV_I32_dpp = 6953,
6969 : V_ASHRREV_I32_e32_si = 6954,
6970 : V_ASHRREV_I32_e32_vi = 6955,
6971 : V_ASHRREV_I32_e64_si = 6956,
6972 : V_ASHRREV_I32_e64_vi = 6957,
6973 : V_ASHRREV_I32_sdwa_gfx9 = 6958,
6974 : V_ASHRREV_I32_sdwa_vi = 6959,
6975 : V_ASHRREV_I64_vi = 6960,
6976 : V_ASHR_I32_e32_si = 6961,
6977 : V_ASHR_I32_e64_si = 6962,
6978 : V_ASHR_I64_si = 6963,
6979 : V_BCNT_U32_B32_e32_si = 6964,
6980 : V_BCNT_U32_B32_e64_si = 6965,
6981 : V_BCNT_U32_B32_e64_vi = 6966,
6982 : V_BFE_I32_si = 6967,
6983 : V_BFE_I32_vi = 6968,
6984 : V_BFE_U32_si = 6969,
6985 : V_BFE_U32_vi = 6970,
6986 : V_BFI_B32_si = 6971,
6987 : V_BFI_B32_vi = 6972,
6988 : V_BFM_B32_e32_si = 6973,
6989 : V_BFM_B32_e64_si = 6974,
6990 : V_BFM_B32_e64_vi = 6975,
6991 : V_BFREV_B32_dpp = 6976,
6992 : V_BFREV_B32_e32_si = 6977,
6993 : V_BFREV_B32_e32_vi = 6978,
6994 : V_BFREV_B32_e64_si = 6979,
6995 : V_BFREV_B32_e64_vi = 6980,
6996 : V_BFREV_B32_sdwa_gfx9 = 6981,
6997 : V_BFREV_B32_sdwa_vi = 6982,
6998 : V_CEIL_F16_dpp = 6983,
6999 : V_CEIL_F16_e32_vi = 6984,
7000 : V_CEIL_F16_e64_vi = 6985,
7001 : V_CEIL_F16_sdwa_gfx9 = 6986,
7002 : V_CEIL_F16_sdwa_vi = 6987,
7003 : V_CEIL_F32_dpp = 6988,
7004 : V_CEIL_F32_e32_si = 6989,
7005 : V_CEIL_F32_e32_vi = 6990,
7006 : V_CEIL_F32_e64_si = 6991,
7007 : V_CEIL_F32_e64_vi = 6992,
7008 : V_CEIL_F32_sdwa_gfx9 = 6993,
7009 : V_CEIL_F32_sdwa_vi = 6994,
7010 : V_CEIL_F64_dpp = 6995,
7011 : V_CEIL_F64_e32_ci = 6996,
7012 : V_CEIL_F64_e32_vi = 6997,
7013 : V_CEIL_F64_e64_ci = 6998,
7014 : V_CEIL_F64_e64_vi = 6999,
7015 : V_CEIL_F64_sdwa_gfx9 = 7000,
7016 : V_CEIL_F64_sdwa_vi = 7001,
7017 : V_CLREXCP_dpp = 7002,
7018 : V_CLREXCP_e32_si = 7003,
7019 : V_CLREXCP_e32_vi = 7004,
7020 : V_CLREXCP_e64_si = 7005,
7021 : V_CLREXCP_e64_vi = 7006,
7022 : V_CLREXCP_sdwa_gfx9 = 7007,
7023 : V_CLREXCP_sdwa_vi = 7008,
7024 : V_CMPSX_EQ_F32_e32_si = 7009,
7025 : V_CMPSX_EQ_F32_e64_si = 7010,
7026 : V_CMPSX_EQ_F64_e32_si = 7011,
7027 : V_CMPSX_EQ_F64_e64_si = 7012,
7028 : V_CMPSX_F_F32_e32_si = 7013,
7029 : V_CMPSX_F_F32_e64_si = 7014,
7030 : V_CMPSX_F_F64_e32_si = 7015,
7031 : V_CMPSX_F_F64_e64_si = 7016,
7032 : V_CMPSX_GE_F32_e32_si = 7017,
7033 : V_CMPSX_GE_F32_e64_si = 7018,
7034 : V_CMPSX_GE_F64_e32_si = 7019,
7035 : V_CMPSX_GE_F64_e64_si = 7020,
7036 : V_CMPSX_GT_F32_e32_si = 7021,
7037 : V_CMPSX_GT_F32_e64_si = 7022,
7038 : V_CMPSX_GT_F64_e32_si = 7023,
7039 : V_CMPSX_GT_F64_e64_si = 7024,
7040 : V_CMPSX_LE_F32_e32_si = 7025,
7041 : V_CMPSX_LE_F32_e64_si = 7026,
7042 : V_CMPSX_LE_F64_e32_si = 7027,
7043 : V_CMPSX_LE_F64_e64_si = 7028,
7044 : V_CMPSX_LG_F32_e32_si = 7029,
7045 : V_CMPSX_LG_F32_e64_si = 7030,
7046 : V_CMPSX_LG_F64_e32_si = 7031,
7047 : V_CMPSX_LG_F64_e64_si = 7032,
7048 : V_CMPSX_LT_F32_e32_si = 7033,
7049 : V_CMPSX_LT_F32_e64_si = 7034,
7050 : V_CMPSX_LT_F64_e32_si = 7035,
7051 : V_CMPSX_LT_F64_e64_si = 7036,
7052 : V_CMPSX_NEQ_F32_e32_si = 7037,
7053 : V_CMPSX_NEQ_F32_e64_si = 7038,
7054 : V_CMPSX_NEQ_F64_e32_si = 7039,
7055 : V_CMPSX_NEQ_F64_e64_si = 7040,
7056 : V_CMPSX_NGE_F32_e32_si = 7041,
7057 : V_CMPSX_NGE_F32_e64_si = 7042,
7058 : V_CMPSX_NGE_F64_e32_si = 7043,
7059 : V_CMPSX_NGE_F64_e64_si = 7044,
7060 : V_CMPSX_NGT_F32_e32_si = 7045,
7061 : V_CMPSX_NGT_F32_e64_si = 7046,
7062 : V_CMPSX_NGT_F64_e32_si = 7047,
7063 : V_CMPSX_NGT_F64_e64_si = 7048,
7064 : V_CMPSX_NLE_F32_e32_si = 7049,
7065 : V_CMPSX_NLE_F32_e64_si = 7050,
7066 : V_CMPSX_NLE_F64_e32_si = 7051,
7067 : V_CMPSX_NLE_F64_e64_si = 7052,
7068 : V_CMPSX_NLG_F32_e32_si = 7053,
7069 : V_CMPSX_NLG_F32_e64_si = 7054,
7070 : V_CMPSX_NLG_F64_e32_si = 7055,
7071 : V_CMPSX_NLG_F64_e64_si = 7056,
7072 : V_CMPSX_NLT_F32_e32_si = 7057,
7073 : V_CMPSX_NLT_F32_e64_si = 7058,
7074 : V_CMPSX_NLT_F64_e32_si = 7059,
7075 : V_CMPSX_NLT_F64_e64_si = 7060,
7076 : V_CMPSX_O_F32_e32_si = 7061,
7077 : V_CMPSX_O_F32_e64_si = 7062,
7078 : V_CMPSX_O_F64_e32_si = 7063,
7079 : V_CMPSX_O_F64_e64_si = 7064,
7080 : V_CMPSX_TRU_F32_e32_si = 7065,
7081 : V_CMPSX_TRU_F32_e64_si = 7066,
7082 : V_CMPSX_TRU_F64_e32_si = 7067,
7083 : V_CMPSX_TRU_F64_e64_si = 7068,
7084 : V_CMPSX_U_F32_e32_si = 7069,
7085 : V_CMPSX_U_F32_e64_si = 7070,
7086 : V_CMPSX_U_F64_e32_si = 7071,
7087 : V_CMPSX_U_F64_e64_si = 7072,
7088 : V_CMPS_EQ_F32_e32_si = 7073,
7089 : V_CMPS_EQ_F32_e64_si = 7074,
7090 : V_CMPS_EQ_F64_e32_si = 7075,
7091 : V_CMPS_EQ_F64_e64_si = 7076,
7092 : V_CMPS_F_F32_e32_si = 7077,
7093 : V_CMPS_F_F32_e64_si = 7078,
7094 : V_CMPS_F_F64_e32_si = 7079,
7095 : V_CMPS_F_F64_e64_si = 7080,
7096 : V_CMPS_GE_F32_e32_si = 7081,
7097 : V_CMPS_GE_F32_e64_si = 7082,
7098 : V_CMPS_GE_F64_e32_si = 7083,
7099 : V_CMPS_GE_F64_e64_si = 7084,
7100 : V_CMPS_GT_F32_e32_si = 7085,
7101 : V_CMPS_GT_F32_e64_si = 7086,
7102 : V_CMPS_GT_F64_e32_si = 7087,
7103 : V_CMPS_GT_F64_e64_si = 7088,
7104 : V_CMPS_LE_F32_e32_si = 7089,
7105 : V_CMPS_LE_F32_e64_si = 7090,
7106 : V_CMPS_LE_F64_e32_si = 7091,
7107 : V_CMPS_LE_F64_e64_si = 7092,
7108 : V_CMPS_LG_F32_e32_si = 7093,
7109 : V_CMPS_LG_F32_e64_si = 7094,
7110 : V_CMPS_LG_F64_e32_si = 7095,
7111 : V_CMPS_LG_F64_e64_si = 7096,
7112 : V_CMPS_LT_F32_e32_si = 7097,
7113 : V_CMPS_LT_F32_e64_si = 7098,
7114 : V_CMPS_LT_F64_e32_si = 7099,
7115 : V_CMPS_LT_F64_e64_si = 7100,
7116 : V_CMPS_NEQ_F32_e32_si = 7101,
7117 : V_CMPS_NEQ_F32_e64_si = 7102,
7118 : V_CMPS_NEQ_F64_e32_si = 7103,
7119 : V_CMPS_NEQ_F64_e64_si = 7104,
7120 : V_CMPS_NGE_F32_e32_si = 7105,
7121 : V_CMPS_NGE_F32_e64_si = 7106,
7122 : V_CMPS_NGE_F64_e32_si = 7107,
7123 : V_CMPS_NGE_F64_e64_si = 7108,
7124 : V_CMPS_NGT_F32_e32_si = 7109,
7125 : V_CMPS_NGT_F32_e64_si = 7110,
7126 : V_CMPS_NGT_F64_e32_si = 7111,
7127 : V_CMPS_NGT_F64_e64_si = 7112,
7128 : V_CMPS_NLE_F32_e32_si = 7113,
7129 : V_CMPS_NLE_F32_e64_si = 7114,
7130 : V_CMPS_NLE_F64_e32_si = 7115,
7131 : V_CMPS_NLE_F64_e64_si = 7116,
7132 : V_CMPS_NLG_F32_e32_si = 7117,
7133 : V_CMPS_NLG_F32_e64_si = 7118,
7134 : V_CMPS_NLG_F64_e32_si = 7119,
7135 : V_CMPS_NLG_F64_e64_si = 7120,
7136 : V_CMPS_NLT_F32_e32_si = 7121,
7137 : V_CMPS_NLT_F32_e64_si = 7122,
7138 : V_CMPS_NLT_F64_e32_si = 7123,
7139 : V_CMPS_NLT_F64_e64_si = 7124,
7140 : V_CMPS_O_F32_e32_si = 7125,
7141 : V_CMPS_O_F32_e64_si = 7126,
7142 : V_CMPS_O_F64_e32_si = 7127,
7143 : V_CMPS_O_F64_e64_si = 7128,
7144 : V_CMPS_TRU_F32_e32_si = 7129,
7145 : V_CMPS_TRU_F32_e64_si = 7130,
7146 : V_CMPS_TRU_F64_e32_si = 7131,
7147 : V_CMPS_TRU_F64_e64_si = 7132,
7148 : V_CMPS_U_F32_e32_si = 7133,
7149 : V_CMPS_U_F32_e64_si = 7134,
7150 : V_CMPS_U_F64_e32_si = 7135,
7151 : V_CMPS_U_F64_e64_si = 7136,
7152 : V_CMPX_CLASS_F16_e32_vi = 7137,
7153 : V_CMPX_CLASS_F16_e64_vi = 7138,
7154 : V_CMPX_CLASS_F16_sdwa_gfx9 = 7139,
7155 : V_CMPX_CLASS_F16_sdwa_vi = 7140,
7156 : V_CMPX_CLASS_F32_e32_si = 7141,
7157 : V_CMPX_CLASS_F32_e32_vi = 7142,
7158 : V_CMPX_CLASS_F32_e64_si = 7143,
7159 : V_CMPX_CLASS_F32_e64_vi = 7144,
7160 : V_CMPX_CLASS_F32_sdwa_gfx9 = 7145,
7161 : V_CMPX_CLASS_F32_sdwa_vi = 7146,
7162 : V_CMPX_CLASS_F64_e32_si = 7147,
7163 : V_CMPX_CLASS_F64_e32_vi = 7148,
7164 : V_CMPX_CLASS_F64_e64_si = 7149,
7165 : V_CMPX_CLASS_F64_e64_vi = 7150,
7166 : V_CMPX_CLASS_F64_sdwa_gfx9 = 7151,
7167 : V_CMPX_CLASS_F64_sdwa_vi = 7152,
7168 : V_CMPX_EQ_F16_e32_vi = 7153,
7169 : V_CMPX_EQ_F16_e64_vi = 7154,
7170 : V_CMPX_EQ_F16_sdwa_gfx9 = 7155,
7171 : V_CMPX_EQ_F16_sdwa_vi = 7156,
7172 : V_CMPX_EQ_F32_e32_si = 7157,
7173 : V_CMPX_EQ_F32_e32_vi = 7158,
7174 : V_CMPX_EQ_F32_e64_si = 7159,
7175 : V_CMPX_EQ_F32_e64_vi = 7160,
7176 : V_CMPX_EQ_F32_sdwa_gfx9 = 7161,
7177 : V_CMPX_EQ_F32_sdwa_vi = 7162,
7178 : V_CMPX_EQ_F64_e32_si = 7163,
7179 : V_CMPX_EQ_F64_e32_vi = 7164,
7180 : V_CMPX_EQ_F64_e64_si = 7165,
7181 : V_CMPX_EQ_F64_e64_vi = 7166,
7182 : V_CMPX_EQ_F64_sdwa_gfx9 = 7167,
7183 : V_CMPX_EQ_F64_sdwa_vi = 7168,
7184 : V_CMPX_EQ_I16_e32_vi = 7169,
7185 : V_CMPX_EQ_I16_e64_vi = 7170,
7186 : V_CMPX_EQ_I16_sdwa_gfx9 = 7171,
7187 : V_CMPX_EQ_I16_sdwa_vi = 7172,
7188 : V_CMPX_EQ_I32_e32_si = 7173,
7189 : V_CMPX_EQ_I32_e32_vi = 7174,
7190 : V_CMPX_EQ_I32_e64_si = 7175,
7191 : V_CMPX_EQ_I32_e64_vi = 7176,
7192 : V_CMPX_EQ_I32_sdwa_gfx9 = 7177,
7193 : V_CMPX_EQ_I32_sdwa_vi = 7178,
7194 : V_CMPX_EQ_I64_e32_si = 7179,
7195 : V_CMPX_EQ_I64_e32_vi = 7180,
7196 : V_CMPX_EQ_I64_e64_si = 7181,
7197 : V_CMPX_EQ_I64_e64_vi = 7182,
7198 : V_CMPX_EQ_I64_sdwa_gfx9 = 7183,
7199 : V_CMPX_EQ_I64_sdwa_vi = 7184,
7200 : V_CMPX_EQ_U16_e32_vi = 7185,
7201 : V_CMPX_EQ_U16_e64_vi = 7186,
7202 : V_CMPX_EQ_U16_sdwa_gfx9 = 7187,
7203 : V_CMPX_EQ_U16_sdwa_vi = 7188,
7204 : V_CMPX_EQ_U32_e32_si = 7189,
7205 : V_CMPX_EQ_U32_e32_vi = 7190,
7206 : V_CMPX_EQ_U32_e64_si = 7191,
7207 : V_CMPX_EQ_U32_e64_vi = 7192,
7208 : V_CMPX_EQ_U32_sdwa_gfx9 = 7193,
7209 : V_CMPX_EQ_U32_sdwa_vi = 7194,
7210 : V_CMPX_EQ_U64_e32_si = 7195,
7211 : V_CMPX_EQ_U64_e32_vi = 7196,
7212 : V_CMPX_EQ_U64_e64_si = 7197,
7213 : V_CMPX_EQ_U64_e64_vi = 7198,
7214 : V_CMPX_EQ_U64_sdwa_gfx9 = 7199,
7215 : V_CMPX_EQ_U64_sdwa_vi = 7200,
7216 : V_CMPX_F_F16_e32_vi = 7201,
7217 : V_CMPX_F_F16_e64_vi = 7202,
7218 : V_CMPX_F_F16_sdwa_gfx9 = 7203,
7219 : V_CMPX_F_F16_sdwa_vi = 7204,
7220 : V_CMPX_F_F32_e32_si = 7205,
7221 : V_CMPX_F_F32_e32_vi = 7206,
7222 : V_CMPX_F_F32_e64_si = 7207,
7223 : V_CMPX_F_F32_e64_vi = 7208,
7224 : V_CMPX_F_F32_sdwa_gfx9 = 7209,
7225 : V_CMPX_F_F32_sdwa_vi = 7210,
7226 : V_CMPX_F_F64_e32_si = 7211,
7227 : V_CMPX_F_F64_e32_vi = 7212,
7228 : V_CMPX_F_F64_e64_si = 7213,
7229 : V_CMPX_F_F64_e64_vi = 7214,
7230 : V_CMPX_F_F64_sdwa_gfx9 = 7215,
7231 : V_CMPX_F_F64_sdwa_vi = 7216,
7232 : V_CMPX_F_I16_e32_vi = 7217,
7233 : V_CMPX_F_I16_e64_vi = 7218,
7234 : V_CMPX_F_I16_sdwa_gfx9 = 7219,
7235 : V_CMPX_F_I16_sdwa_vi = 7220,
7236 : V_CMPX_F_I32_e32_si = 7221,
7237 : V_CMPX_F_I32_e32_vi = 7222,
7238 : V_CMPX_F_I32_e64_si = 7223,
7239 : V_CMPX_F_I32_e64_vi = 7224,
7240 : V_CMPX_F_I32_sdwa_gfx9 = 7225,
7241 : V_CMPX_F_I32_sdwa_vi = 7226,
7242 : V_CMPX_F_I64_e32_si = 7227,
7243 : V_CMPX_F_I64_e32_vi = 7228,
7244 : V_CMPX_F_I64_e64_si = 7229,
7245 : V_CMPX_F_I64_e64_vi = 7230,
7246 : V_CMPX_F_I64_sdwa_gfx9 = 7231,
7247 : V_CMPX_F_I64_sdwa_vi = 7232,
7248 : V_CMPX_F_U16_e32_vi = 7233,
7249 : V_CMPX_F_U16_e64_vi = 7234,
7250 : V_CMPX_F_U16_sdwa_gfx9 = 7235,
7251 : V_CMPX_F_U16_sdwa_vi = 7236,
7252 : V_CMPX_F_U32_e32_si = 7237,
7253 : V_CMPX_F_U32_e32_vi = 7238,
7254 : V_CMPX_F_U32_e64_si = 7239,
7255 : V_CMPX_F_U32_e64_vi = 7240,
7256 : V_CMPX_F_U32_sdwa_gfx9 = 7241,
7257 : V_CMPX_F_U32_sdwa_vi = 7242,
7258 : V_CMPX_F_U64_e32_si = 7243,
7259 : V_CMPX_F_U64_e32_vi = 7244,
7260 : V_CMPX_F_U64_e64_si = 7245,
7261 : V_CMPX_F_U64_e64_vi = 7246,
7262 : V_CMPX_F_U64_sdwa_gfx9 = 7247,
7263 : V_CMPX_F_U64_sdwa_vi = 7248,
7264 : V_CMPX_GE_F16_e32_vi = 7249,
7265 : V_CMPX_GE_F16_e64_vi = 7250,
7266 : V_CMPX_GE_F16_sdwa_gfx9 = 7251,
7267 : V_CMPX_GE_F16_sdwa_vi = 7252,
7268 : V_CMPX_GE_F32_e32_si = 7253,
7269 : V_CMPX_GE_F32_e32_vi = 7254,
7270 : V_CMPX_GE_F32_e64_si = 7255,
7271 : V_CMPX_GE_F32_e64_vi = 7256,
7272 : V_CMPX_GE_F32_sdwa_gfx9 = 7257,
7273 : V_CMPX_GE_F32_sdwa_vi = 7258,
7274 : V_CMPX_GE_F64_e32_si = 7259,
7275 : V_CMPX_GE_F64_e32_vi = 7260,
7276 : V_CMPX_GE_F64_e64_si = 7261,
7277 : V_CMPX_GE_F64_e64_vi = 7262,
7278 : V_CMPX_GE_F64_sdwa_gfx9 = 7263,
7279 : V_CMPX_GE_F64_sdwa_vi = 7264,
7280 : V_CMPX_GE_I16_e32_vi = 7265,
7281 : V_CMPX_GE_I16_e64_vi = 7266,
7282 : V_CMPX_GE_I16_sdwa_gfx9 = 7267,
7283 : V_CMPX_GE_I16_sdwa_vi = 7268,
7284 : V_CMPX_GE_I32_e32_si = 7269,
7285 : V_CMPX_GE_I32_e32_vi = 7270,
7286 : V_CMPX_GE_I32_e64_si = 7271,
7287 : V_CMPX_GE_I32_e64_vi = 7272,
7288 : V_CMPX_GE_I32_sdwa_gfx9 = 7273,
7289 : V_CMPX_GE_I32_sdwa_vi = 7274,
7290 : V_CMPX_GE_I64_e32_si = 7275,
7291 : V_CMPX_GE_I64_e32_vi = 7276,
7292 : V_CMPX_GE_I64_e64_si = 7277,
7293 : V_CMPX_GE_I64_e64_vi = 7278,
7294 : V_CMPX_GE_I64_sdwa_gfx9 = 7279,
7295 : V_CMPX_GE_I64_sdwa_vi = 7280,
7296 : V_CMPX_GE_U16_e32_vi = 7281,
7297 : V_CMPX_GE_U16_e64_vi = 7282,
7298 : V_CMPX_GE_U16_sdwa_gfx9 = 7283,
7299 : V_CMPX_GE_U16_sdwa_vi = 7284,
7300 : V_CMPX_GE_U32_e32_si = 7285,
7301 : V_CMPX_GE_U32_e32_vi = 7286,
7302 : V_CMPX_GE_U32_e64_si = 7287,
7303 : V_CMPX_GE_U32_e64_vi = 7288,
7304 : V_CMPX_GE_U32_sdwa_gfx9 = 7289,
7305 : V_CMPX_GE_U32_sdwa_vi = 7290,
7306 : V_CMPX_GE_U64_e32_si = 7291,
7307 : V_CMPX_GE_U64_e32_vi = 7292,
7308 : V_CMPX_GE_U64_e64_si = 7293,
7309 : V_CMPX_GE_U64_e64_vi = 7294,
7310 : V_CMPX_GE_U64_sdwa_gfx9 = 7295,
7311 : V_CMPX_GE_U64_sdwa_vi = 7296,
7312 : V_CMPX_GT_F16_e32_vi = 7297,
7313 : V_CMPX_GT_F16_e64_vi = 7298,
7314 : V_CMPX_GT_F16_sdwa_gfx9 = 7299,
7315 : V_CMPX_GT_F16_sdwa_vi = 7300,
7316 : V_CMPX_GT_F32_e32_si = 7301,
7317 : V_CMPX_GT_F32_e32_vi = 7302,
7318 : V_CMPX_GT_F32_e64_si = 7303,
7319 : V_CMPX_GT_F32_e64_vi = 7304,
7320 : V_CMPX_GT_F32_sdwa_gfx9 = 7305,
7321 : V_CMPX_GT_F32_sdwa_vi = 7306,
7322 : V_CMPX_GT_F64_e32_si = 7307,
7323 : V_CMPX_GT_F64_e32_vi = 7308,
7324 : V_CMPX_GT_F64_e64_si = 7309,
7325 : V_CMPX_GT_F64_e64_vi = 7310,
7326 : V_CMPX_GT_F64_sdwa_gfx9 = 7311,
7327 : V_CMPX_GT_F64_sdwa_vi = 7312,
7328 : V_CMPX_GT_I16_e32_vi = 7313,
7329 : V_CMPX_GT_I16_e64_vi = 7314,
7330 : V_CMPX_GT_I16_sdwa_gfx9 = 7315,
7331 : V_CMPX_GT_I16_sdwa_vi = 7316,
7332 : V_CMPX_GT_I32_e32_si = 7317,
7333 : V_CMPX_GT_I32_e32_vi = 7318,
7334 : V_CMPX_GT_I32_e64_si = 7319,
7335 : V_CMPX_GT_I32_e64_vi = 7320,
7336 : V_CMPX_GT_I32_sdwa_gfx9 = 7321,
7337 : V_CMPX_GT_I32_sdwa_vi = 7322,
7338 : V_CMPX_GT_I64_e32_si = 7323,
7339 : V_CMPX_GT_I64_e32_vi = 7324,
7340 : V_CMPX_GT_I64_e64_si = 7325,
7341 : V_CMPX_GT_I64_e64_vi = 7326,
7342 : V_CMPX_GT_I64_sdwa_gfx9 = 7327,
7343 : V_CMPX_GT_I64_sdwa_vi = 7328,
7344 : V_CMPX_GT_U16_e32_vi = 7329,
7345 : V_CMPX_GT_U16_e64_vi = 7330,
7346 : V_CMPX_GT_U16_sdwa_gfx9 = 7331,
7347 : V_CMPX_GT_U16_sdwa_vi = 7332,
7348 : V_CMPX_GT_U32_e32_si = 7333,
7349 : V_CMPX_GT_U32_e32_vi = 7334,
7350 : V_CMPX_GT_U32_e64_si = 7335,
7351 : V_CMPX_GT_U32_e64_vi = 7336,
7352 : V_CMPX_GT_U32_sdwa_gfx9 = 7337,
7353 : V_CMPX_GT_U32_sdwa_vi = 7338,
7354 : V_CMPX_GT_U64_e32_si = 7339,
7355 : V_CMPX_GT_U64_e32_vi = 7340,
7356 : V_CMPX_GT_U64_e64_si = 7341,
7357 : V_CMPX_GT_U64_e64_vi = 7342,
7358 : V_CMPX_GT_U64_sdwa_gfx9 = 7343,
7359 : V_CMPX_GT_U64_sdwa_vi = 7344,
7360 : V_CMPX_LE_F16_e32_vi = 7345,
7361 : V_CMPX_LE_F16_e64_vi = 7346,
7362 : V_CMPX_LE_F16_sdwa_gfx9 = 7347,
7363 : V_CMPX_LE_F16_sdwa_vi = 7348,
7364 : V_CMPX_LE_F32_e32_si = 7349,
7365 : V_CMPX_LE_F32_e32_vi = 7350,
7366 : V_CMPX_LE_F32_e64_si = 7351,
7367 : V_CMPX_LE_F32_e64_vi = 7352,
7368 : V_CMPX_LE_F32_sdwa_gfx9 = 7353,
7369 : V_CMPX_LE_F32_sdwa_vi = 7354,
7370 : V_CMPX_LE_F64_e32_si = 7355,
7371 : V_CMPX_LE_F64_e32_vi = 7356,
7372 : V_CMPX_LE_F64_e64_si = 7357,
7373 : V_CMPX_LE_F64_e64_vi = 7358,
7374 : V_CMPX_LE_F64_sdwa_gfx9 = 7359,
7375 : V_CMPX_LE_F64_sdwa_vi = 7360,
7376 : V_CMPX_LE_I16_e32_vi = 7361,
7377 : V_CMPX_LE_I16_e64_vi = 7362,
7378 : V_CMPX_LE_I16_sdwa_gfx9 = 7363,
7379 : V_CMPX_LE_I16_sdwa_vi = 7364,
7380 : V_CMPX_LE_I32_e32_si = 7365,
7381 : V_CMPX_LE_I32_e32_vi = 7366,
7382 : V_CMPX_LE_I32_e64_si = 7367,
7383 : V_CMPX_LE_I32_e64_vi = 7368,
7384 : V_CMPX_LE_I32_sdwa_gfx9 = 7369,
7385 : V_CMPX_LE_I32_sdwa_vi = 7370,
7386 : V_CMPX_LE_I64_e32_si = 7371,
7387 : V_CMPX_LE_I64_e32_vi = 7372,
7388 : V_CMPX_LE_I64_e64_si = 7373,
7389 : V_CMPX_LE_I64_e64_vi = 7374,
7390 : V_CMPX_LE_I64_sdwa_gfx9 = 7375,
7391 : V_CMPX_LE_I64_sdwa_vi = 7376,
7392 : V_CMPX_LE_U16_e32_vi = 7377,
7393 : V_CMPX_LE_U16_e64_vi = 7378,
7394 : V_CMPX_LE_U16_sdwa_gfx9 = 7379,
7395 : V_CMPX_LE_U16_sdwa_vi = 7380,
7396 : V_CMPX_LE_U32_e32_si = 7381,
7397 : V_CMPX_LE_U32_e32_vi = 7382,
7398 : V_CMPX_LE_U32_e64_si = 7383,
7399 : V_CMPX_LE_U32_e64_vi = 7384,
7400 : V_CMPX_LE_U32_sdwa_gfx9 = 7385,
7401 : V_CMPX_LE_U32_sdwa_vi = 7386,
7402 : V_CMPX_LE_U64_e32_si = 7387,
7403 : V_CMPX_LE_U64_e32_vi = 7388,
7404 : V_CMPX_LE_U64_e64_si = 7389,
7405 : V_CMPX_LE_U64_e64_vi = 7390,
7406 : V_CMPX_LE_U64_sdwa_gfx9 = 7391,
7407 : V_CMPX_LE_U64_sdwa_vi = 7392,
7408 : V_CMPX_LG_F16_e32_vi = 7393,
7409 : V_CMPX_LG_F16_e64_vi = 7394,
7410 : V_CMPX_LG_F16_sdwa_gfx9 = 7395,
7411 : V_CMPX_LG_F16_sdwa_vi = 7396,
7412 : V_CMPX_LG_F32_e32_si = 7397,
7413 : V_CMPX_LG_F32_e32_vi = 7398,
7414 : V_CMPX_LG_F32_e64_si = 7399,
7415 : V_CMPX_LG_F32_e64_vi = 7400,
7416 : V_CMPX_LG_F32_sdwa_gfx9 = 7401,
7417 : V_CMPX_LG_F32_sdwa_vi = 7402,
7418 : V_CMPX_LG_F64_e32_si = 7403,
7419 : V_CMPX_LG_F64_e32_vi = 7404,
7420 : V_CMPX_LG_F64_e64_si = 7405,
7421 : V_CMPX_LG_F64_e64_vi = 7406,
7422 : V_CMPX_LG_F64_sdwa_gfx9 = 7407,
7423 : V_CMPX_LG_F64_sdwa_vi = 7408,
7424 : V_CMPX_LT_F16_e32_vi = 7409,
7425 : V_CMPX_LT_F16_e64_vi = 7410,
7426 : V_CMPX_LT_F16_sdwa_gfx9 = 7411,
7427 : V_CMPX_LT_F16_sdwa_vi = 7412,
7428 : V_CMPX_LT_F32_e32_si = 7413,
7429 : V_CMPX_LT_F32_e32_vi = 7414,
7430 : V_CMPX_LT_F32_e64_si = 7415,
7431 : V_CMPX_LT_F32_e64_vi = 7416,
7432 : V_CMPX_LT_F32_sdwa_gfx9 = 7417,
7433 : V_CMPX_LT_F32_sdwa_vi = 7418,
7434 : V_CMPX_LT_F64_e32_si = 7419,
7435 : V_CMPX_LT_F64_e32_vi = 7420,
7436 : V_CMPX_LT_F64_e64_si = 7421,
7437 : V_CMPX_LT_F64_e64_vi = 7422,
7438 : V_CMPX_LT_F64_sdwa_gfx9 = 7423,
7439 : V_CMPX_LT_F64_sdwa_vi = 7424,
7440 : V_CMPX_LT_I16_e32_vi = 7425,
7441 : V_CMPX_LT_I16_e64_vi = 7426,
7442 : V_CMPX_LT_I16_sdwa_gfx9 = 7427,
7443 : V_CMPX_LT_I16_sdwa_vi = 7428,
7444 : V_CMPX_LT_I32_e32_si = 7429,
7445 : V_CMPX_LT_I32_e32_vi = 7430,
7446 : V_CMPX_LT_I32_e64_si = 7431,
7447 : V_CMPX_LT_I32_e64_vi = 7432,
7448 : V_CMPX_LT_I32_sdwa_gfx9 = 7433,
7449 : V_CMPX_LT_I32_sdwa_vi = 7434,
7450 : V_CMPX_LT_I64_e32_si = 7435,
7451 : V_CMPX_LT_I64_e32_vi = 7436,
7452 : V_CMPX_LT_I64_e64_si = 7437,
7453 : V_CMPX_LT_I64_e64_vi = 7438,
7454 : V_CMPX_LT_I64_sdwa_gfx9 = 7439,
7455 : V_CMPX_LT_I64_sdwa_vi = 7440,
7456 : V_CMPX_LT_U16_e32_vi = 7441,
7457 : V_CMPX_LT_U16_e64_vi = 7442,
7458 : V_CMPX_LT_U16_sdwa_gfx9 = 7443,
7459 : V_CMPX_LT_U16_sdwa_vi = 7444,
7460 : V_CMPX_LT_U32_e32_si = 7445,
7461 : V_CMPX_LT_U32_e32_vi = 7446,
7462 : V_CMPX_LT_U32_e64_si = 7447,
7463 : V_CMPX_LT_U32_e64_vi = 7448,
7464 : V_CMPX_LT_U32_sdwa_gfx9 = 7449,
7465 : V_CMPX_LT_U32_sdwa_vi = 7450,
7466 : V_CMPX_LT_U64_e32_si = 7451,
7467 : V_CMPX_LT_U64_e32_vi = 7452,
7468 : V_CMPX_LT_U64_e64_si = 7453,
7469 : V_CMPX_LT_U64_e64_vi = 7454,
7470 : V_CMPX_LT_U64_sdwa_gfx9 = 7455,
7471 : V_CMPX_LT_U64_sdwa_vi = 7456,
7472 : V_CMPX_NEQ_F16_e32_vi = 7457,
7473 : V_CMPX_NEQ_F16_e64_vi = 7458,
7474 : V_CMPX_NEQ_F16_sdwa_gfx9 = 7459,
7475 : V_CMPX_NEQ_F16_sdwa_vi = 7460,
7476 : V_CMPX_NEQ_F32_e32_si = 7461,
7477 : V_CMPX_NEQ_F32_e32_vi = 7462,
7478 : V_CMPX_NEQ_F32_e64_si = 7463,
7479 : V_CMPX_NEQ_F32_e64_vi = 7464,
7480 : V_CMPX_NEQ_F32_sdwa_gfx9 = 7465,
7481 : V_CMPX_NEQ_F32_sdwa_vi = 7466,
7482 : V_CMPX_NEQ_F64_e32_si = 7467,
7483 : V_CMPX_NEQ_F64_e32_vi = 7468,
7484 : V_CMPX_NEQ_F64_e64_si = 7469,
7485 : V_CMPX_NEQ_F64_e64_vi = 7470,
7486 : V_CMPX_NEQ_F64_sdwa_gfx9 = 7471,
7487 : V_CMPX_NEQ_F64_sdwa_vi = 7472,
7488 : V_CMPX_NE_I16_e32_vi = 7473,
7489 : V_CMPX_NE_I16_e64_vi = 7474,
7490 : V_CMPX_NE_I16_sdwa_gfx9 = 7475,
7491 : V_CMPX_NE_I16_sdwa_vi = 7476,
7492 : V_CMPX_NE_I32_e32_si = 7477,
7493 : V_CMPX_NE_I32_e32_vi = 7478,
7494 : V_CMPX_NE_I32_e64_si = 7479,
7495 : V_CMPX_NE_I32_e64_vi = 7480,
7496 : V_CMPX_NE_I32_sdwa_gfx9 = 7481,
7497 : V_CMPX_NE_I32_sdwa_vi = 7482,
7498 : V_CMPX_NE_I64_e32_si = 7483,
7499 : V_CMPX_NE_I64_e32_vi = 7484,
7500 : V_CMPX_NE_I64_e64_si = 7485,
7501 : V_CMPX_NE_I64_e64_vi = 7486,
7502 : V_CMPX_NE_I64_sdwa_gfx9 = 7487,
7503 : V_CMPX_NE_I64_sdwa_vi = 7488,
7504 : V_CMPX_NE_U16_e32_vi = 7489,
7505 : V_CMPX_NE_U16_e64_vi = 7490,
7506 : V_CMPX_NE_U16_sdwa_gfx9 = 7491,
7507 : V_CMPX_NE_U16_sdwa_vi = 7492,
7508 : V_CMPX_NE_U32_e32_si = 7493,
7509 : V_CMPX_NE_U32_e32_vi = 7494,
7510 : V_CMPX_NE_U32_e64_si = 7495,
7511 : V_CMPX_NE_U32_e64_vi = 7496,
7512 : V_CMPX_NE_U32_sdwa_gfx9 = 7497,
7513 : V_CMPX_NE_U32_sdwa_vi = 7498,
7514 : V_CMPX_NE_U64_e32_si = 7499,
7515 : V_CMPX_NE_U64_e32_vi = 7500,
7516 : V_CMPX_NE_U64_e64_si = 7501,
7517 : V_CMPX_NE_U64_e64_vi = 7502,
7518 : V_CMPX_NE_U64_sdwa_gfx9 = 7503,
7519 : V_CMPX_NE_U64_sdwa_vi = 7504,
7520 : V_CMPX_NGE_F16_e32_vi = 7505,
7521 : V_CMPX_NGE_F16_e64_vi = 7506,
7522 : V_CMPX_NGE_F16_sdwa_gfx9 = 7507,
7523 : V_CMPX_NGE_F16_sdwa_vi = 7508,
7524 : V_CMPX_NGE_F32_e32_si = 7509,
7525 : V_CMPX_NGE_F32_e32_vi = 7510,
7526 : V_CMPX_NGE_F32_e64_si = 7511,
7527 : V_CMPX_NGE_F32_e64_vi = 7512,
7528 : V_CMPX_NGE_F32_sdwa_gfx9 = 7513,
7529 : V_CMPX_NGE_F32_sdwa_vi = 7514,
7530 : V_CMPX_NGE_F64_e32_si = 7515,
7531 : V_CMPX_NGE_F64_e32_vi = 7516,
7532 : V_CMPX_NGE_F64_e64_si = 7517,
7533 : V_CMPX_NGE_F64_e64_vi = 7518,
7534 : V_CMPX_NGE_F64_sdwa_gfx9 = 7519,
7535 : V_CMPX_NGE_F64_sdwa_vi = 7520,
7536 : V_CMPX_NGT_F16_e32_vi = 7521,
7537 : V_CMPX_NGT_F16_e64_vi = 7522,
7538 : V_CMPX_NGT_F16_sdwa_gfx9 = 7523,
7539 : V_CMPX_NGT_F16_sdwa_vi = 7524,
7540 : V_CMPX_NGT_F32_e32_si = 7525,
7541 : V_CMPX_NGT_F32_e32_vi = 7526,
7542 : V_CMPX_NGT_F32_e64_si = 7527,
7543 : V_CMPX_NGT_F32_e64_vi = 7528,
7544 : V_CMPX_NGT_F32_sdwa_gfx9 = 7529,
7545 : V_CMPX_NGT_F32_sdwa_vi = 7530,
7546 : V_CMPX_NGT_F64_e32_si = 7531,
7547 : V_CMPX_NGT_F64_e32_vi = 7532,
7548 : V_CMPX_NGT_F64_e64_si = 7533,
7549 : V_CMPX_NGT_F64_e64_vi = 7534,
7550 : V_CMPX_NGT_F64_sdwa_gfx9 = 7535,
7551 : V_CMPX_NGT_F64_sdwa_vi = 7536,
7552 : V_CMPX_NLE_F16_e32_vi = 7537,
7553 : V_CMPX_NLE_F16_e64_vi = 7538,
7554 : V_CMPX_NLE_F16_sdwa_gfx9 = 7539,
7555 : V_CMPX_NLE_F16_sdwa_vi = 7540,
7556 : V_CMPX_NLE_F32_e32_si = 7541,
7557 : V_CMPX_NLE_F32_e32_vi = 7542,
7558 : V_CMPX_NLE_F32_e64_si = 7543,
7559 : V_CMPX_NLE_F32_e64_vi = 7544,
7560 : V_CMPX_NLE_F32_sdwa_gfx9 = 7545,
7561 : V_CMPX_NLE_F32_sdwa_vi = 7546,
7562 : V_CMPX_NLE_F64_e32_si = 7547,
7563 : V_CMPX_NLE_F64_e32_vi = 7548,
7564 : V_CMPX_NLE_F64_e64_si = 7549,
7565 : V_CMPX_NLE_F64_e64_vi = 7550,
7566 : V_CMPX_NLE_F64_sdwa_gfx9 = 7551,
7567 : V_CMPX_NLE_F64_sdwa_vi = 7552,
7568 : V_CMPX_NLG_F16_e32_vi = 7553,
7569 : V_CMPX_NLG_F16_e64_vi = 7554,
7570 : V_CMPX_NLG_F16_sdwa_gfx9 = 7555,
7571 : V_CMPX_NLG_F16_sdwa_vi = 7556,
7572 : V_CMPX_NLG_F32_e32_si = 7557,
7573 : V_CMPX_NLG_F32_e32_vi = 7558,
7574 : V_CMPX_NLG_F32_e64_si = 7559,
7575 : V_CMPX_NLG_F32_e64_vi = 7560,
7576 : V_CMPX_NLG_F32_sdwa_gfx9 = 7561,
7577 : V_CMPX_NLG_F32_sdwa_vi = 7562,
7578 : V_CMPX_NLG_F64_e32_si = 7563,
7579 : V_CMPX_NLG_F64_e32_vi = 7564,
7580 : V_CMPX_NLG_F64_e64_si = 7565,
7581 : V_CMPX_NLG_F64_e64_vi = 7566,
7582 : V_CMPX_NLG_F64_sdwa_gfx9 = 7567,
7583 : V_CMPX_NLG_F64_sdwa_vi = 7568,
7584 : V_CMPX_NLT_F16_e32_vi = 7569,
7585 : V_CMPX_NLT_F16_e64_vi = 7570,
7586 : V_CMPX_NLT_F16_sdwa_gfx9 = 7571,
7587 : V_CMPX_NLT_F16_sdwa_vi = 7572,
7588 : V_CMPX_NLT_F32_e32_si = 7573,
7589 : V_CMPX_NLT_F32_e32_vi = 7574,
7590 : V_CMPX_NLT_F32_e64_si = 7575,
7591 : V_CMPX_NLT_F32_e64_vi = 7576,
7592 : V_CMPX_NLT_F32_sdwa_gfx9 = 7577,
7593 : V_CMPX_NLT_F32_sdwa_vi = 7578,
7594 : V_CMPX_NLT_F64_e32_si = 7579,
7595 : V_CMPX_NLT_F64_e32_vi = 7580,
7596 : V_CMPX_NLT_F64_e64_si = 7581,
7597 : V_CMPX_NLT_F64_e64_vi = 7582,
7598 : V_CMPX_NLT_F64_sdwa_gfx9 = 7583,
7599 : V_CMPX_NLT_F64_sdwa_vi = 7584,
7600 : V_CMPX_O_F16_e32_vi = 7585,
7601 : V_CMPX_O_F16_e64_vi = 7586,
7602 : V_CMPX_O_F16_sdwa_gfx9 = 7587,
7603 : V_CMPX_O_F16_sdwa_vi = 7588,
7604 : V_CMPX_O_F32_e32_si = 7589,
7605 : V_CMPX_O_F32_e32_vi = 7590,
7606 : V_CMPX_O_F32_e64_si = 7591,
7607 : V_CMPX_O_F32_e64_vi = 7592,
7608 : V_CMPX_O_F32_sdwa_gfx9 = 7593,
7609 : V_CMPX_O_F32_sdwa_vi = 7594,
7610 : V_CMPX_O_F64_e32_si = 7595,
7611 : V_CMPX_O_F64_e32_vi = 7596,
7612 : V_CMPX_O_F64_e64_si = 7597,
7613 : V_CMPX_O_F64_e64_vi = 7598,
7614 : V_CMPX_O_F64_sdwa_gfx9 = 7599,
7615 : V_CMPX_O_F64_sdwa_vi = 7600,
7616 : V_CMPX_TRU_F16_e32_vi = 7601,
7617 : V_CMPX_TRU_F16_e64_vi = 7602,
7618 : V_CMPX_TRU_F16_sdwa_gfx9 = 7603,
7619 : V_CMPX_TRU_F16_sdwa_vi = 7604,
7620 : V_CMPX_TRU_F32_e32_si = 7605,
7621 : V_CMPX_TRU_F32_e32_vi = 7606,
7622 : V_CMPX_TRU_F32_e64_si = 7607,
7623 : V_CMPX_TRU_F32_e64_vi = 7608,
7624 : V_CMPX_TRU_F32_sdwa_gfx9 = 7609,
7625 : V_CMPX_TRU_F32_sdwa_vi = 7610,
7626 : V_CMPX_TRU_F64_e32_si = 7611,
7627 : V_CMPX_TRU_F64_e32_vi = 7612,
7628 : V_CMPX_TRU_F64_e64_si = 7613,
7629 : V_CMPX_TRU_F64_e64_vi = 7614,
7630 : V_CMPX_TRU_F64_sdwa_gfx9 = 7615,
7631 : V_CMPX_TRU_F64_sdwa_vi = 7616,
7632 : V_CMPX_T_I16_e32_vi = 7617,
7633 : V_CMPX_T_I16_e64_vi = 7618,
7634 : V_CMPX_T_I16_sdwa_gfx9 = 7619,
7635 : V_CMPX_T_I16_sdwa_vi = 7620,
7636 : V_CMPX_T_I32_e32_si = 7621,
7637 : V_CMPX_T_I32_e32_vi = 7622,
7638 : V_CMPX_T_I32_e64_si = 7623,
7639 : V_CMPX_T_I32_e64_vi = 7624,
7640 : V_CMPX_T_I32_sdwa_gfx9 = 7625,
7641 : V_CMPX_T_I32_sdwa_vi = 7626,
7642 : V_CMPX_T_I64_e32_si = 7627,
7643 : V_CMPX_T_I64_e32_vi = 7628,
7644 : V_CMPX_T_I64_e64_si = 7629,
7645 : V_CMPX_T_I64_e64_vi = 7630,
7646 : V_CMPX_T_I64_sdwa_gfx9 = 7631,
7647 : V_CMPX_T_I64_sdwa_vi = 7632,
7648 : V_CMPX_T_U16_e32_vi = 7633,
7649 : V_CMPX_T_U16_e64_vi = 7634,
7650 : V_CMPX_T_U16_sdwa_gfx9 = 7635,
7651 : V_CMPX_T_U16_sdwa_vi = 7636,
7652 : V_CMPX_T_U32_e32_si = 7637,
7653 : V_CMPX_T_U32_e32_vi = 7638,
7654 : V_CMPX_T_U32_e64_si = 7639,
7655 : V_CMPX_T_U32_e64_vi = 7640,
7656 : V_CMPX_T_U32_sdwa_gfx9 = 7641,
7657 : V_CMPX_T_U32_sdwa_vi = 7642,
7658 : V_CMPX_T_U64_e32_si = 7643,
7659 : V_CMPX_T_U64_e32_vi = 7644,
7660 : V_CMPX_T_U64_e64_si = 7645,
7661 : V_CMPX_T_U64_e64_vi = 7646,
7662 : V_CMPX_T_U64_sdwa_gfx9 = 7647,
7663 : V_CMPX_T_U64_sdwa_vi = 7648,
7664 : V_CMPX_U_F16_e32_vi = 7649,
7665 : V_CMPX_U_F16_e64_vi = 7650,
7666 : V_CMPX_U_F16_sdwa_gfx9 = 7651,
7667 : V_CMPX_U_F16_sdwa_vi = 7652,
7668 : V_CMPX_U_F32_e32_si = 7653,
7669 : V_CMPX_U_F32_e32_vi = 7654,
7670 : V_CMPX_U_F32_e64_si = 7655,
7671 : V_CMPX_U_F32_e64_vi = 7656,
7672 : V_CMPX_U_F32_sdwa_gfx9 = 7657,
7673 : V_CMPX_U_F32_sdwa_vi = 7658,
7674 : V_CMPX_U_F64_e32_si = 7659,
7675 : V_CMPX_U_F64_e32_vi = 7660,
7676 : V_CMPX_U_F64_e64_si = 7661,
7677 : V_CMPX_U_F64_e64_vi = 7662,
7678 : V_CMPX_U_F64_sdwa_gfx9 = 7663,
7679 : V_CMPX_U_F64_sdwa_vi = 7664,
7680 : V_CMP_CLASS_F16_e32_vi = 7665,
7681 : V_CMP_CLASS_F16_e64_vi = 7666,
7682 : V_CMP_CLASS_F16_sdwa_gfx9 = 7667,
7683 : V_CMP_CLASS_F16_sdwa_vi = 7668,
7684 : V_CMP_CLASS_F32_e32_si = 7669,
7685 : V_CMP_CLASS_F32_e32_vi = 7670,
7686 : V_CMP_CLASS_F32_e64_si = 7671,
7687 : V_CMP_CLASS_F32_e64_vi = 7672,
7688 : V_CMP_CLASS_F32_sdwa_gfx9 = 7673,
7689 : V_CMP_CLASS_F32_sdwa_vi = 7674,
7690 : V_CMP_CLASS_F64_e32_si = 7675,
7691 : V_CMP_CLASS_F64_e32_vi = 7676,
7692 : V_CMP_CLASS_F64_e64_si = 7677,
7693 : V_CMP_CLASS_F64_e64_vi = 7678,
7694 : V_CMP_CLASS_F64_sdwa_gfx9 = 7679,
7695 : V_CMP_CLASS_F64_sdwa_vi = 7680,
7696 : V_CMP_EQ_F16_e32_vi = 7681,
7697 : V_CMP_EQ_F16_e64_vi = 7682,
7698 : V_CMP_EQ_F16_sdwa_gfx9 = 7683,
7699 : V_CMP_EQ_F16_sdwa_vi = 7684,
7700 : V_CMP_EQ_F32_e32_si = 7685,
7701 : V_CMP_EQ_F32_e32_vi = 7686,
7702 : V_CMP_EQ_F32_e64_si = 7687,
7703 : V_CMP_EQ_F32_e64_vi = 7688,
7704 : V_CMP_EQ_F32_sdwa_gfx9 = 7689,
7705 : V_CMP_EQ_F32_sdwa_vi = 7690,
7706 : V_CMP_EQ_F64_e32_si = 7691,
7707 : V_CMP_EQ_F64_e32_vi = 7692,
7708 : V_CMP_EQ_F64_e64_si = 7693,
7709 : V_CMP_EQ_F64_e64_vi = 7694,
7710 : V_CMP_EQ_F64_sdwa_gfx9 = 7695,
7711 : V_CMP_EQ_F64_sdwa_vi = 7696,
7712 : V_CMP_EQ_I16_e32_vi = 7697,
7713 : V_CMP_EQ_I16_e64_vi = 7698,
7714 : V_CMP_EQ_I16_sdwa_gfx9 = 7699,
7715 : V_CMP_EQ_I16_sdwa_vi = 7700,
7716 : V_CMP_EQ_I32_e32_si = 7701,
7717 : V_CMP_EQ_I32_e32_vi = 7702,
7718 : V_CMP_EQ_I32_e64_si = 7703,
7719 : V_CMP_EQ_I32_e64_vi = 7704,
7720 : V_CMP_EQ_I32_sdwa_gfx9 = 7705,
7721 : V_CMP_EQ_I32_sdwa_vi = 7706,
7722 : V_CMP_EQ_I64_e32_si = 7707,
7723 : V_CMP_EQ_I64_e32_vi = 7708,
7724 : V_CMP_EQ_I64_e64_si = 7709,
7725 : V_CMP_EQ_I64_e64_vi = 7710,
7726 : V_CMP_EQ_I64_sdwa_gfx9 = 7711,
7727 : V_CMP_EQ_I64_sdwa_vi = 7712,
7728 : V_CMP_EQ_U16_e32_vi = 7713,
7729 : V_CMP_EQ_U16_e64_vi = 7714,
7730 : V_CMP_EQ_U16_sdwa_gfx9 = 7715,
7731 : V_CMP_EQ_U16_sdwa_vi = 7716,
7732 : V_CMP_EQ_U32_e32_si = 7717,
7733 : V_CMP_EQ_U32_e32_vi = 7718,
7734 : V_CMP_EQ_U32_e64_si = 7719,
7735 : V_CMP_EQ_U32_e64_vi = 7720,
7736 : V_CMP_EQ_U32_sdwa_gfx9 = 7721,
7737 : V_CMP_EQ_U32_sdwa_vi = 7722,
7738 : V_CMP_EQ_U64_e32_si = 7723,
7739 : V_CMP_EQ_U64_e32_vi = 7724,
7740 : V_CMP_EQ_U64_e64_si = 7725,
7741 : V_CMP_EQ_U64_e64_vi = 7726,
7742 : V_CMP_EQ_U64_sdwa_gfx9 = 7727,
7743 : V_CMP_EQ_U64_sdwa_vi = 7728,
7744 : V_CMP_F_F16_e32_vi = 7729,
7745 : V_CMP_F_F16_e64_vi = 7730,
7746 : V_CMP_F_F16_sdwa_gfx9 = 7731,
7747 : V_CMP_F_F16_sdwa_vi = 7732,
7748 : V_CMP_F_F32_e32_si = 7733,
7749 : V_CMP_F_F32_e32_vi = 7734,
7750 : V_CMP_F_F32_e64_si = 7735,
7751 : V_CMP_F_F32_e64_vi = 7736,
7752 : V_CMP_F_F32_sdwa_gfx9 = 7737,
7753 : V_CMP_F_F32_sdwa_vi = 7738,
7754 : V_CMP_F_F64_e32_si = 7739,
7755 : V_CMP_F_F64_e32_vi = 7740,
7756 : V_CMP_F_F64_e64_si = 7741,
7757 : V_CMP_F_F64_e64_vi = 7742,
7758 : V_CMP_F_F64_sdwa_gfx9 = 7743,
7759 : V_CMP_F_F64_sdwa_vi = 7744,
7760 : V_CMP_F_I16_e32_vi = 7745,
7761 : V_CMP_F_I16_e64_vi = 7746,
7762 : V_CMP_F_I16_sdwa_gfx9 = 7747,
7763 : V_CMP_F_I16_sdwa_vi = 7748,
7764 : V_CMP_F_I32_e32_si = 7749,
7765 : V_CMP_F_I32_e32_vi = 7750,
7766 : V_CMP_F_I32_e64_si = 7751,
7767 : V_CMP_F_I32_e64_vi = 7752,
7768 : V_CMP_F_I32_sdwa_gfx9 = 7753,
7769 : V_CMP_F_I32_sdwa_vi = 7754,
7770 : V_CMP_F_I64_e32_si = 7755,
7771 : V_CMP_F_I64_e32_vi = 7756,
7772 : V_CMP_F_I64_e64_si = 7757,
7773 : V_CMP_F_I64_e64_vi = 7758,
7774 : V_CMP_F_I64_sdwa_gfx9 = 7759,
7775 : V_CMP_F_I64_sdwa_vi = 7760,
7776 : V_CMP_F_U16_e32_vi = 7761,
7777 : V_CMP_F_U16_e64_vi = 7762,
7778 : V_CMP_F_U16_sdwa_gfx9 = 7763,
7779 : V_CMP_F_U16_sdwa_vi = 7764,
7780 : V_CMP_F_U32_e32_si = 7765,
7781 : V_CMP_F_U32_e32_vi = 7766,
7782 : V_CMP_F_U32_e64_si = 7767,
7783 : V_CMP_F_U32_e64_vi = 7768,
7784 : V_CMP_F_U32_sdwa_gfx9 = 7769,
7785 : V_CMP_F_U32_sdwa_vi = 7770,
7786 : V_CMP_F_U64_e32_si = 7771,
7787 : V_CMP_F_U64_e32_vi = 7772,
7788 : V_CMP_F_U64_e64_si = 7773,
7789 : V_CMP_F_U64_e64_vi = 7774,
7790 : V_CMP_F_U64_sdwa_gfx9 = 7775,
7791 : V_CMP_F_U64_sdwa_vi = 7776,
7792 : V_CMP_GE_F16_e32_vi = 7777,
7793 : V_CMP_GE_F16_e64_vi = 7778,
7794 : V_CMP_GE_F16_sdwa_gfx9 = 7779,
7795 : V_CMP_GE_F16_sdwa_vi = 7780,
7796 : V_CMP_GE_F32_e32_si = 7781,
7797 : V_CMP_GE_F32_e32_vi = 7782,
7798 : V_CMP_GE_F32_e64_si = 7783,
7799 : V_CMP_GE_F32_e64_vi = 7784,
7800 : V_CMP_GE_F32_sdwa_gfx9 = 7785,
7801 : V_CMP_GE_F32_sdwa_vi = 7786,
7802 : V_CMP_GE_F64_e32_si = 7787,
7803 : V_CMP_GE_F64_e32_vi = 7788,
7804 : V_CMP_GE_F64_e64_si = 7789,
7805 : V_CMP_GE_F64_e64_vi = 7790,
7806 : V_CMP_GE_F64_sdwa_gfx9 = 7791,
7807 : V_CMP_GE_F64_sdwa_vi = 7792,
7808 : V_CMP_GE_I16_e32_vi = 7793,
7809 : V_CMP_GE_I16_e64_vi = 7794,
7810 : V_CMP_GE_I16_sdwa_gfx9 = 7795,
7811 : V_CMP_GE_I16_sdwa_vi = 7796,
7812 : V_CMP_GE_I32_e32_si = 7797,
7813 : V_CMP_GE_I32_e32_vi = 7798,
7814 : V_CMP_GE_I32_e64_si = 7799,
7815 : V_CMP_GE_I32_e64_vi = 7800,
7816 : V_CMP_GE_I32_sdwa_gfx9 = 7801,
7817 : V_CMP_GE_I32_sdwa_vi = 7802,
7818 : V_CMP_GE_I64_e32_si = 7803,
7819 : V_CMP_GE_I64_e32_vi = 7804,
7820 : V_CMP_GE_I64_e64_si = 7805,
7821 : V_CMP_GE_I64_e64_vi = 7806,
7822 : V_CMP_GE_I64_sdwa_gfx9 = 7807,
7823 : V_CMP_GE_I64_sdwa_vi = 7808,
7824 : V_CMP_GE_U16_e32_vi = 7809,
7825 : V_CMP_GE_U16_e64_vi = 7810,
7826 : V_CMP_GE_U16_sdwa_gfx9 = 7811,
7827 : V_CMP_GE_U16_sdwa_vi = 7812,
7828 : V_CMP_GE_U32_e32_si = 7813,
7829 : V_CMP_GE_U32_e32_vi = 7814,
7830 : V_CMP_GE_U32_e64_si = 7815,
7831 : V_CMP_GE_U32_e64_vi = 7816,
7832 : V_CMP_GE_U32_sdwa_gfx9 = 7817,
7833 : V_CMP_GE_U32_sdwa_vi = 7818,
7834 : V_CMP_GE_U64_e32_si = 7819,
7835 : V_CMP_GE_U64_e32_vi = 7820,
7836 : V_CMP_GE_U64_e64_si = 7821,
7837 : V_CMP_GE_U64_e64_vi = 7822,
7838 : V_CMP_GE_U64_sdwa_gfx9 = 7823,
7839 : V_CMP_GE_U64_sdwa_vi = 7824,
7840 : V_CMP_GT_F16_e32_vi = 7825,
7841 : V_CMP_GT_F16_e64_vi = 7826,
7842 : V_CMP_GT_F16_sdwa_gfx9 = 7827,
7843 : V_CMP_GT_F16_sdwa_vi = 7828,
7844 : V_CMP_GT_F32_e32_si = 7829,
7845 : V_CMP_GT_F32_e32_vi = 7830,
7846 : V_CMP_GT_F32_e64_si = 7831,
7847 : V_CMP_GT_F32_e64_vi = 7832,
7848 : V_CMP_GT_F32_sdwa_gfx9 = 7833,
7849 : V_CMP_GT_F32_sdwa_vi = 7834,
7850 : V_CMP_GT_F64_e32_si = 7835,
7851 : V_CMP_GT_F64_e32_vi = 7836,
7852 : V_CMP_GT_F64_e64_si = 7837,
7853 : V_CMP_GT_F64_e64_vi = 7838,
7854 : V_CMP_GT_F64_sdwa_gfx9 = 7839,
7855 : V_CMP_GT_F64_sdwa_vi = 7840,
7856 : V_CMP_GT_I16_e32_vi = 7841,
7857 : V_CMP_GT_I16_e64_vi = 7842,
7858 : V_CMP_GT_I16_sdwa_gfx9 = 7843,
7859 : V_CMP_GT_I16_sdwa_vi = 7844,
7860 : V_CMP_GT_I32_e32_si = 7845,
7861 : V_CMP_GT_I32_e32_vi = 7846,
7862 : V_CMP_GT_I32_e64_si = 7847,
7863 : V_CMP_GT_I32_e64_vi = 7848,
7864 : V_CMP_GT_I32_sdwa_gfx9 = 7849,
7865 : V_CMP_GT_I32_sdwa_vi = 7850,
7866 : V_CMP_GT_I64_e32_si = 7851,
7867 : V_CMP_GT_I64_e32_vi = 7852,
7868 : V_CMP_GT_I64_e64_si = 7853,
7869 : V_CMP_GT_I64_e64_vi = 7854,
7870 : V_CMP_GT_I64_sdwa_gfx9 = 7855,
7871 : V_CMP_GT_I64_sdwa_vi = 7856,
7872 : V_CMP_GT_U16_e32_vi = 7857,
7873 : V_CMP_GT_U16_e64_vi = 7858,
7874 : V_CMP_GT_U16_sdwa_gfx9 = 7859,
7875 : V_CMP_GT_U16_sdwa_vi = 7860,
7876 : V_CMP_GT_U32_e32_si = 7861,
7877 : V_CMP_GT_U32_e32_vi = 7862,
7878 : V_CMP_GT_U32_e64_si = 7863,
7879 : V_CMP_GT_U32_e64_vi = 7864,
7880 : V_CMP_GT_U32_sdwa_gfx9 = 7865,
7881 : V_CMP_GT_U32_sdwa_vi = 7866,
7882 : V_CMP_GT_U64_e32_si = 7867,
7883 : V_CMP_GT_U64_e32_vi = 7868,
7884 : V_CMP_GT_U64_e64_si = 7869,
7885 : V_CMP_GT_U64_e64_vi = 7870,
7886 : V_CMP_GT_U64_sdwa_gfx9 = 7871,
7887 : V_CMP_GT_U64_sdwa_vi = 7872,
7888 : V_CMP_LE_F16_e32_vi = 7873,
7889 : V_CMP_LE_F16_e64_vi = 7874,
7890 : V_CMP_LE_F16_sdwa_gfx9 = 7875,
7891 : V_CMP_LE_F16_sdwa_vi = 7876,
7892 : V_CMP_LE_F32_e32_si = 7877,
7893 : V_CMP_LE_F32_e32_vi = 7878,
7894 : V_CMP_LE_F32_e64_si = 7879,
7895 : V_CMP_LE_F32_e64_vi = 7880,
7896 : V_CMP_LE_F32_sdwa_gfx9 = 7881,
7897 : V_CMP_LE_F32_sdwa_vi = 7882,
7898 : V_CMP_LE_F64_e32_si = 7883,
7899 : V_CMP_LE_F64_e32_vi = 7884,
7900 : V_CMP_LE_F64_e64_si = 7885,
7901 : V_CMP_LE_F64_e64_vi = 7886,
7902 : V_CMP_LE_F64_sdwa_gfx9 = 7887,
7903 : V_CMP_LE_F64_sdwa_vi = 7888,
7904 : V_CMP_LE_I16_e32_vi = 7889,
7905 : V_CMP_LE_I16_e64_vi = 7890,
7906 : V_CMP_LE_I16_sdwa_gfx9 = 7891,
7907 : V_CMP_LE_I16_sdwa_vi = 7892,
7908 : V_CMP_LE_I32_e32_si = 7893,
7909 : V_CMP_LE_I32_e32_vi = 7894,
7910 : V_CMP_LE_I32_e64_si = 7895,
7911 : V_CMP_LE_I32_e64_vi = 7896,
7912 : V_CMP_LE_I32_sdwa_gfx9 = 7897,
7913 : V_CMP_LE_I32_sdwa_vi = 7898,
7914 : V_CMP_LE_I64_e32_si = 7899,
7915 : V_CMP_LE_I64_e32_vi = 7900,
7916 : V_CMP_LE_I64_e64_si = 7901,
7917 : V_CMP_LE_I64_e64_vi = 7902,
7918 : V_CMP_LE_I64_sdwa_gfx9 = 7903,
7919 : V_CMP_LE_I64_sdwa_vi = 7904,
7920 : V_CMP_LE_U16_e32_vi = 7905,
7921 : V_CMP_LE_U16_e64_vi = 7906,
7922 : V_CMP_LE_U16_sdwa_gfx9 = 7907,
7923 : V_CMP_LE_U16_sdwa_vi = 7908,
7924 : V_CMP_LE_U32_e32_si = 7909,
7925 : V_CMP_LE_U32_e32_vi = 7910,
7926 : V_CMP_LE_U32_e64_si = 7911,
7927 : V_CMP_LE_U32_e64_vi = 7912,
7928 : V_CMP_LE_U32_sdwa_gfx9 = 7913,
7929 : V_CMP_LE_U32_sdwa_vi = 7914,
7930 : V_CMP_LE_U64_e32_si = 7915,
7931 : V_CMP_LE_U64_e32_vi = 7916,
7932 : V_CMP_LE_U64_e64_si = 7917,
7933 : V_CMP_LE_U64_e64_vi = 7918,
7934 : V_CMP_LE_U64_sdwa_gfx9 = 7919,
7935 : V_CMP_LE_U64_sdwa_vi = 7920,
7936 : V_CMP_LG_F16_e32_vi = 7921,
7937 : V_CMP_LG_F16_e64_vi = 7922,
7938 : V_CMP_LG_F16_sdwa_gfx9 = 7923,
7939 : V_CMP_LG_F16_sdwa_vi = 7924,
7940 : V_CMP_LG_F32_e32_si = 7925,
7941 : V_CMP_LG_F32_e32_vi = 7926,
7942 : V_CMP_LG_F32_e64_si = 7927,
7943 : V_CMP_LG_F32_e64_vi = 7928,
7944 : V_CMP_LG_F32_sdwa_gfx9 = 7929,
7945 : V_CMP_LG_F32_sdwa_vi = 7930,
7946 : V_CMP_LG_F64_e32_si = 7931,
7947 : V_CMP_LG_F64_e32_vi = 7932,
7948 : V_CMP_LG_F64_e64_si = 7933,
7949 : V_CMP_LG_F64_e64_vi = 7934,
7950 : V_CMP_LG_F64_sdwa_gfx9 = 7935,
7951 : V_CMP_LG_F64_sdwa_vi = 7936,
7952 : V_CMP_LT_F16_e32_vi = 7937,
7953 : V_CMP_LT_F16_e64_vi = 7938,
7954 : V_CMP_LT_F16_sdwa_gfx9 = 7939,
7955 : V_CMP_LT_F16_sdwa_vi = 7940,
7956 : V_CMP_LT_F32_e32_si = 7941,
7957 : V_CMP_LT_F32_e32_vi = 7942,
7958 : V_CMP_LT_F32_e64_si = 7943,
7959 : V_CMP_LT_F32_e64_vi = 7944,
7960 : V_CMP_LT_F32_sdwa_gfx9 = 7945,
7961 : V_CMP_LT_F32_sdwa_vi = 7946,
7962 : V_CMP_LT_F64_e32_si = 7947,
7963 : V_CMP_LT_F64_e32_vi = 7948,
7964 : V_CMP_LT_F64_e64_si = 7949,
7965 : V_CMP_LT_F64_e64_vi = 7950,
7966 : V_CMP_LT_F64_sdwa_gfx9 = 7951,
7967 : V_CMP_LT_F64_sdwa_vi = 7952,
7968 : V_CMP_LT_I16_e32_vi = 7953,
7969 : V_CMP_LT_I16_e64_vi = 7954,
7970 : V_CMP_LT_I16_sdwa_gfx9 = 7955,
7971 : V_CMP_LT_I16_sdwa_vi = 7956,
7972 : V_CMP_LT_I32_e32_si = 7957,
7973 : V_CMP_LT_I32_e32_vi = 7958,
7974 : V_CMP_LT_I32_e64_si = 7959,
7975 : V_CMP_LT_I32_e64_vi = 7960,
7976 : V_CMP_LT_I32_sdwa_gfx9 = 7961,
7977 : V_CMP_LT_I32_sdwa_vi = 7962,
7978 : V_CMP_LT_I64_e32_si = 7963,
7979 : V_CMP_LT_I64_e32_vi = 7964,
7980 : V_CMP_LT_I64_e64_si = 7965,
7981 : V_CMP_LT_I64_e64_vi = 7966,
7982 : V_CMP_LT_I64_sdwa_gfx9 = 7967,
7983 : V_CMP_LT_I64_sdwa_vi = 7968,
7984 : V_CMP_LT_U16_e32_vi = 7969,
7985 : V_CMP_LT_U16_e64_vi = 7970,
7986 : V_CMP_LT_U16_sdwa_gfx9 = 7971,
7987 : V_CMP_LT_U16_sdwa_vi = 7972,
7988 : V_CMP_LT_U32_e32_si = 7973,
7989 : V_CMP_LT_U32_e32_vi = 7974,
7990 : V_CMP_LT_U32_e64_si = 7975,
7991 : V_CMP_LT_U32_e64_vi = 7976,
7992 : V_CMP_LT_U32_sdwa_gfx9 = 7977,
7993 : V_CMP_LT_U32_sdwa_vi = 7978,
7994 : V_CMP_LT_U64_e32_si = 7979,
7995 : V_CMP_LT_U64_e32_vi = 7980,
7996 : V_CMP_LT_U64_e64_si = 7981,
7997 : V_CMP_LT_U64_e64_vi = 7982,
7998 : V_CMP_LT_U64_sdwa_gfx9 = 7983,
7999 : V_CMP_LT_U64_sdwa_vi = 7984,
8000 : V_CMP_NEQ_F16_e32_vi = 7985,
8001 : V_CMP_NEQ_F16_e64_vi = 7986,
8002 : V_CMP_NEQ_F16_sdwa_gfx9 = 7987,
8003 : V_CMP_NEQ_F16_sdwa_vi = 7988,
8004 : V_CMP_NEQ_F32_e32_si = 7989,
8005 : V_CMP_NEQ_F32_e32_vi = 7990,
8006 : V_CMP_NEQ_F32_e64_si = 7991,
8007 : V_CMP_NEQ_F32_e64_vi = 7992,
8008 : V_CMP_NEQ_F32_sdwa_gfx9 = 7993,
8009 : V_CMP_NEQ_F32_sdwa_vi = 7994,
8010 : V_CMP_NEQ_F64_e32_si = 7995,
8011 : V_CMP_NEQ_F64_e32_vi = 7996,
8012 : V_CMP_NEQ_F64_e64_si = 7997,
8013 : V_CMP_NEQ_F64_e64_vi = 7998,
8014 : V_CMP_NEQ_F64_sdwa_gfx9 = 7999,
8015 : V_CMP_NEQ_F64_sdwa_vi = 8000,
8016 : V_CMP_NE_I16_e32_vi = 8001,
8017 : V_CMP_NE_I16_e64_vi = 8002,
8018 : V_CMP_NE_I16_sdwa_gfx9 = 8003,
8019 : V_CMP_NE_I16_sdwa_vi = 8004,
8020 : V_CMP_NE_I32_e32_si = 8005,
8021 : V_CMP_NE_I32_e32_vi = 8006,
8022 : V_CMP_NE_I32_e64_si = 8007,
8023 : V_CMP_NE_I32_e64_vi = 8008,
8024 : V_CMP_NE_I32_sdwa_gfx9 = 8009,
8025 : V_CMP_NE_I32_sdwa_vi = 8010,
8026 : V_CMP_NE_I64_e32_si = 8011,
8027 : V_CMP_NE_I64_e32_vi = 8012,
8028 : V_CMP_NE_I64_e64_si = 8013,
8029 : V_CMP_NE_I64_e64_vi = 8014,
8030 : V_CMP_NE_I64_sdwa_gfx9 = 8015,
8031 : V_CMP_NE_I64_sdwa_vi = 8016,
8032 : V_CMP_NE_U16_e32_vi = 8017,
8033 : V_CMP_NE_U16_e64_vi = 8018,
8034 : V_CMP_NE_U16_sdwa_gfx9 = 8019,
8035 : V_CMP_NE_U16_sdwa_vi = 8020,
8036 : V_CMP_NE_U32_e32_si = 8021,
8037 : V_CMP_NE_U32_e32_vi = 8022,
8038 : V_CMP_NE_U32_e64_si = 8023,
8039 : V_CMP_NE_U32_e64_vi = 8024,
8040 : V_CMP_NE_U32_sdwa_gfx9 = 8025,
8041 : V_CMP_NE_U32_sdwa_vi = 8026,
8042 : V_CMP_NE_U64_e32_si = 8027,
8043 : V_CMP_NE_U64_e32_vi = 8028,
8044 : V_CMP_NE_U64_e64_si = 8029,
8045 : V_CMP_NE_U64_e64_vi = 8030,
8046 : V_CMP_NE_U64_sdwa_gfx9 = 8031,
8047 : V_CMP_NE_U64_sdwa_vi = 8032,
8048 : V_CMP_NGE_F16_e32_vi = 8033,
8049 : V_CMP_NGE_F16_e64_vi = 8034,
8050 : V_CMP_NGE_F16_sdwa_gfx9 = 8035,
8051 : V_CMP_NGE_F16_sdwa_vi = 8036,
8052 : V_CMP_NGE_F32_e32_si = 8037,
8053 : V_CMP_NGE_F32_e32_vi = 8038,
8054 : V_CMP_NGE_F32_e64_si = 8039,
8055 : V_CMP_NGE_F32_e64_vi = 8040,
8056 : V_CMP_NGE_F32_sdwa_gfx9 = 8041,
8057 : V_CMP_NGE_F32_sdwa_vi = 8042,
8058 : V_CMP_NGE_F64_e32_si = 8043,
8059 : V_CMP_NGE_F64_e32_vi = 8044,
8060 : V_CMP_NGE_F64_e64_si = 8045,
8061 : V_CMP_NGE_F64_e64_vi = 8046,
8062 : V_CMP_NGE_F64_sdwa_gfx9 = 8047,
8063 : V_CMP_NGE_F64_sdwa_vi = 8048,
8064 : V_CMP_NGT_F16_e32_vi = 8049,
8065 : V_CMP_NGT_F16_e64_vi = 8050,
8066 : V_CMP_NGT_F16_sdwa_gfx9 = 8051,
8067 : V_CMP_NGT_F16_sdwa_vi = 8052,
8068 : V_CMP_NGT_F32_e32_si = 8053,
8069 : V_CMP_NGT_F32_e32_vi = 8054,
8070 : V_CMP_NGT_F32_e64_si = 8055,
8071 : V_CMP_NGT_F32_e64_vi = 8056,
8072 : V_CMP_NGT_F32_sdwa_gfx9 = 8057,
8073 : V_CMP_NGT_F32_sdwa_vi = 8058,
8074 : V_CMP_NGT_F64_e32_si = 8059,
8075 : V_CMP_NGT_F64_e32_vi = 8060,
8076 : V_CMP_NGT_F64_e64_si = 8061,
8077 : V_CMP_NGT_F64_e64_vi = 8062,
8078 : V_CMP_NGT_F64_sdwa_gfx9 = 8063,
8079 : V_CMP_NGT_F64_sdwa_vi = 8064,
8080 : V_CMP_NLE_F16_e32_vi = 8065,
8081 : V_CMP_NLE_F16_e64_vi = 8066,
8082 : V_CMP_NLE_F16_sdwa_gfx9 = 8067,
8083 : V_CMP_NLE_F16_sdwa_vi = 8068,
8084 : V_CMP_NLE_F32_e32_si = 8069,
8085 : V_CMP_NLE_F32_e32_vi = 8070,
8086 : V_CMP_NLE_F32_e64_si = 8071,
8087 : V_CMP_NLE_F32_e64_vi = 8072,
8088 : V_CMP_NLE_F32_sdwa_gfx9 = 8073,
8089 : V_CMP_NLE_F32_sdwa_vi = 8074,
8090 : V_CMP_NLE_F64_e32_si = 8075,
8091 : V_CMP_NLE_F64_e32_vi = 8076,
8092 : V_CMP_NLE_F64_e64_si = 8077,
8093 : V_CMP_NLE_F64_e64_vi = 8078,
8094 : V_CMP_NLE_F64_sdwa_gfx9 = 8079,
8095 : V_CMP_NLE_F64_sdwa_vi = 8080,
8096 : V_CMP_NLG_F16_e32_vi = 8081,
8097 : V_CMP_NLG_F16_e64_vi = 8082,
8098 : V_CMP_NLG_F16_sdwa_gfx9 = 8083,
8099 : V_CMP_NLG_F16_sdwa_vi = 8084,
8100 : V_CMP_NLG_F32_e32_si = 8085,
8101 : V_CMP_NLG_F32_e32_vi = 8086,
8102 : V_CMP_NLG_F32_e64_si = 8087,
8103 : V_CMP_NLG_F32_e64_vi = 8088,
8104 : V_CMP_NLG_F32_sdwa_gfx9 = 8089,
8105 : V_CMP_NLG_F32_sdwa_vi = 8090,
8106 : V_CMP_NLG_F64_e32_si = 8091,
8107 : V_CMP_NLG_F64_e32_vi = 8092,
8108 : V_CMP_NLG_F64_e64_si = 8093,
8109 : V_CMP_NLG_F64_e64_vi = 8094,
8110 : V_CMP_NLG_F64_sdwa_gfx9 = 8095,
8111 : V_CMP_NLG_F64_sdwa_vi = 8096,
8112 : V_CMP_NLT_F16_e32_vi = 8097,
8113 : V_CMP_NLT_F16_e64_vi = 8098,
8114 : V_CMP_NLT_F16_sdwa_gfx9 = 8099,
8115 : V_CMP_NLT_F16_sdwa_vi = 8100,
8116 : V_CMP_NLT_F32_e32_si = 8101,
8117 : V_CMP_NLT_F32_e32_vi = 8102,
8118 : V_CMP_NLT_F32_e64_si = 8103,
8119 : V_CMP_NLT_F32_e64_vi = 8104,
8120 : V_CMP_NLT_F32_sdwa_gfx9 = 8105,
8121 : V_CMP_NLT_F32_sdwa_vi = 8106,
8122 : V_CMP_NLT_F64_e32_si = 8107,
8123 : V_CMP_NLT_F64_e32_vi = 8108,
8124 : V_CMP_NLT_F64_e64_si = 8109,
8125 : V_CMP_NLT_F64_e64_vi = 8110,
8126 : V_CMP_NLT_F64_sdwa_gfx9 = 8111,
8127 : V_CMP_NLT_F64_sdwa_vi = 8112,
8128 : V_CMP_O_F16_e32_vi = 8113,
8129 : V_CMP_O_F16_e64_vi = 8114,
8130 : V_CMP_O_F16_sdwa_gfx9 = 8115,
8131 : V_CMP_O_F16_sdwa_vi = 8116,
8132 : V_CMP_O_F32_e32_si = 8117,
8133 : V_CMP_O_F32_e32_vi = 8118,
8134 : V_CMP_O_F32_e64_si = 8119,
8135 : V_CMP_O_F32_e64_vi = 8120,
8136 : V_CMP_O_F32_sdwa_gfx9 = 8121,
8137 : V_CMP_O_F32_sdwa_vi = 8122,
8138 : V_CMP_O_F64_e32_si = 8123,
8139 : V_CMP_O_F64_e32_vi = 8124,
8140 : V_CMP_O_F64_e64_si = 8125,
8141 : V_CMP_O_F64_e64_vi = 8126,
8142 : V_CMP_O_F64_sdwa_gfx9 = 8127,
8143 : V_CMP_O_F64_sdwa_vi = 8128,
8144 : V_CMP_TRU_F16_e32_vi = 8129,
8145 : V_CMP_TRU_F16_e64_vi = 8130,
8146 : V_CMP_TRU_F16_sdwa_gfx9 = 8131,
8147 : V_CMP_TRU_F16_sdwa_vi = 8132,
8148 : V_CMP_TRU_F32_e32_si = 8133,
8149 : V_CMP_TRU_F32_e32_vi = 8134,
8150 : V_CMP_TRU_F32_e64_si = 8135,
8151 : V_CMP_TRU_F32_e64_vi = 8136,
8152 : V_CMP_TRU_F32_sdwa_gfx9 = 8137,
8153 : V_CMP_TRU_F32_sdwa_vi = 8138,
8154 : V_CMP_TRU_F64_e32_si = 8139,
8155 : V_CMP_TRU_F64_e32_vi = 8140,
8156 : V_CMP_TRU_F64_e64_si = 8141,
8157 : V_CMP_TRU_F64_e64_vi = 8142,
8158 : V_CMP_TRU_F64_sdwa_gfx9 = 8143,
8159 : V_CMP_TRU_F64_sdwa_vi = 8144,
8160 : V_CMP_T_I16_e32_vi = 8145,
8161 : V_CMP_T_I16_e64_vi = 8146,
8162 : V_CMP_T_I16_sdwa_gfx9 = 8147,
8163 : V_CMP_T_I16_sdwa_vi = 8148,
8164 : V_CMP_T_I32_e32_si = 8149,
8165 : V_CMP_T_I32_e32_vi = 8150,
8166 : V_CMP_T_I32_e64_si = 8151,
8167 : V_CMP_T_I32_e64_vi = 8152,
8168 : V_CMP_T_I32_sdwa_gfx9 = 8153,
8169 : V_CMP_T_I32_sdwa_vi = 8154,
8170 : V_CMP_T_I64_e32_si = 8155,
8171 : V_CMP_T_I64_e32_vi = 8156,
8172 : V_CMP_T_I64_e64_si = 8157,
8173 : V_CMP_T_I64_e64_vi = 8158,
8174 : V_CMP_T_I64_sdwa_gfx9 = 8159,
8175 : V_CMP_T_I64_sdwa_vi = 8160,
8176 : V_CMP_T_U16_e32_vi = 8161,
8177 : V_CMP_T_U16_e64_vi = 8162,
8178 : V_CMP_T_U16_sdwa_gfx9 = 8163,
8179 : V_CMP_T_U16_sdwa_vi = 8164,
8180 : V_CMP_T_U32_e32_si = 8165,
8181 : V_CMP_T_U32_e32_vi = 8166,
8182 : V_CMP_T_U32_e64_si = 8167,
8183 : V_CMP_T_U32_e64_vi = 8168,
8184 : V_CMP_T_U32_sdwa_gfx9 = 8169,
8185 : V_CMP_T_U32_sdwa_vi = 8170,
8186 : V_CMP_T_U64_e32_si = 8171,
8187 : V_CMP_T_U64_e32_vi = 8172,
8188 : V_CMP_T_U64_e64_si = 8173,
8189 : V_CMP_T_U64_e64_vi = 8174,
8190 : V_CMP_T_U64_sdwa_gfx9 = 8175,
8191 : V_CMP_T_U64_sdwa_vi = 8176,
8192 : V_CMP_U_F16_e32_vi = 8177,
8193 : V_CMP_U_F16_e64_vi = 8178,
8194 : V_CMP_U_F16_sdwa_gfx9 = 8179,
8195 : V_CMP_U_F16_sdwa_vi = 8180,
8196 : V_CMP_U_F32_e32_si = 8181,
8197 : V_CMP_U_F32_e32_vi = 8182,
8198 : V_CMP_U_F32_e64_si = 8183,
8199 : V_CMP_U_F32_e64_vi = 8184,
8200 : V_CMP_U_F32_sdwa_gfx9 = 8185,
8201 : V_CMP_U_F32_sdwa_vi = 8186,
8202 : V_CMP_U_F64_e32_si = 8187,
8203 : V_CMP_U_F64_e32_vi = 8188,
8204 : V_CMP_U_F64_e64_si = 8189,
8205 : V_CMP_U_F64_e64_vi = 8190,
8206 : V_CMP_U_F64_sdwa_gfx9 = 8191,
8207 : V_CMP_U_F64_sdwa_vi = 8192,
8208 : V_CNDMASK_B32_dpp = 8193,
8209 : V_CNDMASK_B32_e32_si = 8194,
8210 : V_CNDMASK_B32_e32_vi = 8195,
8211 : V_CNDMASK_B32_e64_si = 8196,
8212 : V_CNDMASK_B32_e64_vi = 8197,
8213 : V_CNDMASK_B32_sdwa_gfx9 = 8198,
8214 : V_CNDMASK_B32_sdwa_vi = 8199,
8215 : V_COS_F16_dpp = 8200,
8216 : V_COS_F16_e32_vi = 8201,
8217 : V_COS_F16_e64_vi = 8202,
8218 : V_COS_F16_sdwa_gfx9 = 8203,
8219 : V_COS_F16_sdwa_vi = 8204,
8220 : V_COS_F32_dpp = 8205,
8221 : V_COS_F32_e32_si = 8206,
8222 : V_COS_F32_e32_vi = 8207,
8223 : V_COS_F32_e64_si = 8208,
8224 : V_COS_F32_e64_vi = 8209,
8225 : V_COS_F32_sdwa_gfx9 = 8210,
8226 : V_COS_F32_sdwa_vi = 8211,
8227 : V_CUBEID_F32_si = 8212,
8228 : V_CUBEID_F32_vi = 8213,
8229 : V_CUBEMA_F32_si = 8214,
8230 : V_CUBEMA_F32_vi = 8215,
8231 : V_CUBESC_F32_si = 8216,
8232 : V_CUBESC_F32_vi = 8217,
8233 : V_CUBETC_F32_si = 8218,
8234 : V_CUBETC_F32_vi = 8219,
8235 : V_CVT_F16_F32_dpp = 8220,
8236 : V_CVT_F16_F32_e32_si = 8221,
8237 : V_CVT_F16_F32_e32_vi = 8222,
8238 : V_CVT_F16_F32_e64_si = 8223,
8239 : V_CVT_F16_F32_e64_vi = 8224,
8240 : V_CVT_F16_F32_sdwa_gfx9 = 8225,
8241 : V_CVT_F16_F32_sdwa_vi = 8226,
8242 : V_CVT_F16_I16_dpp = 8227,
8243 : V_CVT_F16_I16_e32_vi = 8228,
8244 : V_CVT_F16_I16_e64_vi = 8229,
8245 : V_CVT_F16_I16_sdwa_gfx9 = 8230,
8246 : V_CVT_F16_I16_sdwa_vi = 8231,
8247 : V_CVT_F16_U16_dpp = 8232,
8248 : V_CVT_F16_U16_e32_vi = 8233,
8249 : V_CVT_F16_U16_e64_vi = 8234,
8250 : V_CVT_F16_U16_sdwa_gfx9 = 8235,
8251 : V_CVT_F16_U16_sdwa_vi = 8236,
8252 : V_CVT_F32_F16_dpp = 8237,
8253 : V_CVT_F32_F16_e32_si = 8238,
8254 : V_CVT_F32_F16_e32_vi = 8239,
8255 : V_CVT_F32_F16_e64_si = 8240,
8256 : V_CVT_F32_F16_e64_vi = 8241,
8257 : V_CVT_F32_F16_sdwa_gfx9 = 8242,
8258 : V_CVT_F32_F16_sdwa_vi = 8243,
8259 : V_CVT_F32_F64_dpp = 8244,
8260 : V_CVT_F32_F64_e32_si = 8245,
8261 : V_CVT_F32_F64_e32_vi = 8246,
8262 : V_CVT_F32_F64_e64_si = 8247,
8263 : V_CVT_F32_F64_e64_vi = 8248,
8264 : V_CVT_F32_F64_sdwa_gfx9 = 8249,
8265 : V_CVT_F32_F64_sdwa_vi = 8250,
8266 : V_CVT_F32_I32_dpp = 8251,
8267 : V_CVT_F32_I32_e32_si = 8252,
8268 : V_CVT_F32_I32_e32_vi = 8253,
8269 : V_CVT_F32_I32_e64_si = 8254,
8270 : V_CVT_F32_I32_e64_vi = 8255,
8271 : V_CVT_F32_I32_sdwa_gfx9 = 8256,
8272 : V_CVT_F32_I32_sdwa_vi = 8257,
8273 : V_CVT_F32_U32_dpp = 8258,
8274 : V_CVT_F32_U32_e32_si = 8259,
8275 : V_CVT_F32_U32_e32_vi = 8260,
8276 : V_CVT_F32_U32_e64_si = 8261,
8277 : V_CVT_F32_U32_e64_vi = 8262,
8278 : V_CVT_F32_U32_sdwa_gfx9 = 8263,
8279 : V_CVT_F32_U32_sdwa_vi = 8264,
8280 : V_CVT_F32_UBYTE0_dpp = 8265,
8281 : V_CVT_F32_UBYTE0_e32_si = 8266,
8282 : V_CVT_F32_UBYTE0_e32_vi = 8267,
8283 : V_CVT_F32_UBYTE0_e64_si = 8268,
8284 : V_CVT_F32_UBYTE0_e64_vi = 8269,
8285 : V_CVT_F32_UBYTE0_sdwa_gfx9 = 8270,
8286 : V_CVT_F32_UBYTE0_sdwa_vi = 8271,
8287 : V_CVT_F32_UBYTE1_dpp = 8272,
8288 : V_CVT_F32_UBYTE1_e32_si = 8273,
8289 : V_CVT_F32_UBYTE1_e32_vi = 8274,
8290 : V_CVT_F32_UBYTE1_e64_si = 8275,
8291 : V_CVT_F32_UBYTE1_e64_vi = 8276,
8292 : V_CVT_F32_UBYTE1_sdwa_gfx9 = 8277,
8293 : V_CVT_F32_UBYTE1_sdwa_vi = 8278,
8294 : V_CVT_F32_UBYTE2_dpp = 8279,
8295 : V_CVT_F32_UBYTE2_e32_si = 8280,
8296 : V_CVT_F32_UBYTE2_e32_vi = 8281,
8297 : V_CVT_F32_UBYTE2_e64_si = 8282,
8298 : V_CVT_F32_UBYTE2_e64_vi = 8283,
8299 : V_CVT_F32_UBYTE2_sdwa_gfx9 = 8284,
8300 : V_CVT_F32_UBYTE2_sdwa_vi = 8285,
8301 : V_CVT_F32_UBYTE3_dpp = 8286,
8302 : V_CVT_F32_UBYTE3_e32_si = 8287,
8303 : V_CVT_F32_UBYTE3_e32_vi = 8288,
8304 : V_CVT_F32_UBYTE3_e64_si = 8289,
8305 : V_CVT_F32_UBYTE3_e64_vi = 8290,
8306 : V_CVT_F32_UBYTE3_sdwa_gfx9 = 8291,
8307 : V_CVT_F32_UBYTE3_sdwa_vi = 8292,
8308 : V_CVT_F64_F32_dpp = 8293,
8309 : V_CVT_F64_F32_e32_si = 8294,
8310 : V_CVT_F64_F32_e32_vi = 8295,
8311 : V_CVT_F64_F32_e64_si = 8296,
8312 : V_CVT_F64_F32_e64_vi = 8297,
8313 : V_CVT_F64_F32_sdwa_gfx9 = 8298,
8314 : V_CVT_F64_F32_sdwa_vi = 8299,
8315 : V_CVT_F64_I32_dpp = 8300,
8316 : V_CVT_F64_I32_e32_si = 8301,
8317 : V_CVT_F64_I32_e32_vi = 8302,
8318 : V_CVT_F64_I32_e64_si = 8303,
8319 : V_CVT_F64_I32_e64_vi = 8304,
8320 : V_CVT_F64_I32_sdwa_gfx9 = 8305,
8321 : V_CVT_F64_I32_sdwa_vi = 8306,
8322 : V_CVT_F64_U32_dpp = 8307,
8323 : V_CVT_F64_U32_e32_si = 8308,
8324 : V_CVT_F64_U32_e32_vi = 8309,
8325 : V_CVT_F64_U32_e64_si = 8310,
8326 : V_CVT_F64_U32_e64_vi = 8311,
8327 : V_CVT_F64_U32_sdwa_gfx9 = 8312,
8328 : V_CVT_F64_U32_sdwa_vi = 8313,
8329 : V_CVT_FLR_I32_F32_dpp = 8314,
8330 : V_CVT_FLR_I32_F32_e32_si = 8315,
8331 : V_CVT_FLR_I32_F32_e32_vi = 8316,
8332 : V_CVT_FLR_I32_F32_e64_si = 8317,
8333 : V_CVT_FLR_I32_F32_e64_vi = 8318,
8334 : V_CVT_FLR_I32_F32_sdwa_gfx9 = 8319,
8335 : V_CVT_FLR_I32_F32_sdwa_vi = 8320,
8336 : V_CVT_I16_F16_dpp = 8321,
8337 : V_CVT_I16_F16_e32_vi = 8322,
8338 : V_CVT_I16_F16_e64_vi = 8323,
8339 : V_CVT_I16_F16_sdwa_gfx9 = 8324,
8340 : V_CVT_I16_F16_sdwa_vi = 8325,
8341 : V_CVT_I32_F32_dpp = 8326,
8342 : V_CVT_I32_F32_e32_si = 8327,
8343 : V_CVT_I32_F32_e32_vi = 8328,
8344 : V_CVT_I32_F32_e64_si = 8329,
8345 : V_CVT_I32_F32_e64_vi = 8330,
8346 : V_CVT_I32_F32_sdwa_gfx9 = 8331,
8347 : V_CVT_I32_F32_sdwa_vi = 8332,
8348 : V_CVT_I32_F64_dpp = 8333,
8349 : V_CVT_I32_F64_e32_si = 8334,
8350 : V_CVT_I32_F64_e32_vi = 8335,
8351 : V_CVT_I32_F64_e64_si = 8336,
8352 : V_CVT_I32_F64_e64_vi = 8337,
8353 : V_CVT_I32_F64_sdwa_gfx9 = 8338,
8354 : V_CVT_I32_F64_sdwa_vi = 8339,
8355 : V_CVT_NORM_I16_F16_dpp = 8340,
8356 : V_CVT_NORM_I16_F16_e32_vi = 8341,
8357 : V_CVT_NORM_I16_F16_e64_vi = 8342,
8358 : V_CVT_NORM_I16_F16_sdwa_gfx9 = 8343,
8359 : V_CVT_NORM_I16_F16_sdwa_vi = 8344,
8360 : V_CVT_NORM_U16_F16_dpp = 8345,
8361 : V_CVT_NORM_U16_F16_e32_vi = 8346,
8362 : V_CVT_NORM_U16_F16_e64_vi = 8347,
8363 : V_CVT_NORM_U16_F16_sdwa_gfx9 = 8348,
8364 : V_CVT_NORM_U16_F16_sdwa_vi = 8349,
8365 : V_CVT_OFF_F32_I4_dpp = 8350,
8366 : V_CVT_OFF_F32_I4_e32_si = 8351,
8367 : V_CVT_OFF_F32_I4_e32_vi = 8352,
8368 : V_CVT_OFF_F32_I4_e64_si = 8353,
8369 : V_CVT_OFF_F32_I4_e64_vi = 8354,
8370 : V_CVT_OFF_F32_I4_sdwa_gfx9 = 8355,
8371 : V_CVT_OFF_F32_I4_sdwa_vi = 8356,
8372 : V_CVT_PKACCUM_U8_F32_e32_si = 8357,
8373 : V_CVT_PKACCUM_U8_F32_e64_si = 8358,
8374 : V_CVT_PKACCUM_U8_F32_e64_vi = 8359,
8375 : V_CVT_PKNORM_I16_F16_vi = 8360,
8376 : V_CVT_PKNORM_I16_F32_e32_si = 8361,
8377 : V_CVT_PKNORM_I16_F32_e64_si = 8362,
8378 : V_CVT_PKNORM_I16_F32_e64_vi = 8363,
8379 : V_CVT_PKNORM_U16_F16_vi = 8364,
8380 : V_CVT_PKNORM_U16_F32_e32_si = 8365,
8381 : V_CVT_PKNORM_U16_F32_e64_si = 8366,
8382 : V_CVT_PKNORM_U16_F32_e64_vi = 8367,
8383 : V_CVT_PKRTZ_F16_F32_e32_si = 8368,
8384 : V_CVT_PKRTZ_F16_F32_e64_si = 8369,
8385 : V_CVT_PKRTZ_F16_F32_e64_vi = 8370,
8386 : V_CVT_PK_I16_I32_e32_si = 8371,
8387 : V_CVT_PK_I16_I32_e64_si = 8372,
8388 : V_CVT_PK_I16_I32_e64_vi = 8373,
8389 : V_CVT_PK_U16_U32_e32_si = 8374,
8390 : V_CVT_PK_U16_U32_e64_si = 8375,
8391 : V_CVT_PK_U16_U32_e64_vi = 8376,
8392 : V_CVT_PK_U8_F32_si = 8377,
8393 : V_CVT_PK_U8_F32_vi = 8378,
8394 : V_CVT_RPI_I32_F32_dpp = 8379,
8395 : V_CVT_RPI_I32_F32_e32_si = 8380,
8396 : V_CVT_RPI_I32_F32_e32_vi = 8381,
8397 : V_CVT_RPI_I32_F32_e64_si = 8382,
8398 : V_CVT_RPI_I32_F32_e64_vi = 8383,
8399 : V_CVT_RPI_I32_F32_sdwa_gfx9 = 8384,
8400 : V_CVT_RPI_I32_F32_sdwa_vi = 8385,
8401 : V_CVT_U16_F16_dpp = 8386,
8402 : V_CVT_U16_F16_e32_vi = 8387,
8403 : V_CVT_U16_F16_e64_vi = 8388,
8404 : V_CVT_U16_F16_sdwa_gfx9 = 8389,
8405 : V_CVT_U16_F16_sdwa_vi = 8390,
8406 : V_CVT_U32_F32_dpp = 8391,
8407 : V_CVT_U32_F32_e32_si = 8392,
8408 : V_CVT_U32_F32_e32_vi = 8393,
8409 : V_CVT_U32_F32_e64_si = 8394,
8410 : V_CVT_U32_F32_e64_vi = 8395,
8411 : V_CVT_U32_F32_sdwa_gfx9 = 8396,
8412 : V_CVT_U32_F32_sdwa_vi = 8397,
8413 : V_CVT_U32_F64_dpp = 8398,
8414 : V_CVT_U32_F64_e32_si = 8399,
8415 : V_CVT_U32_F64_e32_vi = 8400,
8416 : V_CVT_U32_F64_e64_si = 8401,
8417 : V_CVT_U32_F64_e64_vi = 8402,
8418 : V_CVT_U32_F64_sdwa_gfx9 = 8403,
8419 : V_CVT_U32_F64_sdwa_vi = 8404,
8420 : V_DIV_FIXUP_F16_gfx9_gfx9 = 8405,
8421 : V_DIV_FIXUP_F16_vi = 8406,
8422 : V_DIV_FIXUP_F32_si = 8407,
8423 : V_DIV_FIXUP_F32_vi = 8408,
8424 : V_DIV_FIXUP_F64_si = 8409,
8425 : V_DIV_FIXUP_F64_vi = 8410,
8426 : V_DIV_FIXUP_LEGACY_F16_gfx9 = 8411,
8427 : V_DIV_FMAS_F32_si = 8412,
8428 : V_DIV_FMAS_F32_vi = 8413,
8429 : V_DIV_FMAS_F64_si = 8414,
8430 : V_DIV_FMAS_F64_vi = 8415,
8431 : V_DIV_SCALE_F32_si = 8416,
8432 : V_DIV_SCALE_F32_vi = 8417,
8433 : V_DIV_SCALE_F64_si = 8418,
8434 : V_DIV_SCALE_F64_vi = 8419,
8435 : V_DOT2_F32_F16_vi = 8420,
8436 : V_DOT2_I32_I16_vi = 8421,
8437 : V_DOT2_U32_U16_vi = 8422,
8438 : V_DOT4_I32_I8_vi = 8423,
8439 : V_DOT4_U32_U8_vi = 8424,
8440 : V_DOT8_I32_I4_vi = 8425,
8441 : V_DOT8_U32_U4_vi = 8426,
8442 : V_EXP_F16_dpp = 8427,
8443 : V_EXP_F16_e32_vi = 8428,
8444 : V_EXP_F16_e64_vi = 8429,
8445 : V_EXP_F16_sdwa_gfx9 = 8430,
8446 : V_EXP_F16_sdwa_vi = 8431,
8447 : V_EXP_F32_dpp = 8432,
8448 : V_EXP_F32_e32_si = 8433,
8449 : V_EXP_F32_e32_vi = 8434,
8450 : V_EXP_F32_e64_si = 8435,
8451 : V_EXP_F32_e64_vi = 8436,
8452 : V_EXP_F32_sdwa_gfx9 = 8437,
8453 : V_EXP_F32_sdwa_vi = 8438,
8454 : V_EXP_LEGACY_F32_dpp = 8439,
8455 : V_EXP_LEGACY_F32_e32_ci = 8440,
8456 : V_EXP_LEGACY_F32_e32_vi = 8441,
8457 : V_EXP_LEGACY_F32_e64_ci = 8442,
8458 : V_EXP_LEGACY_F32_e64_vi = 8443,
8459 : V_EXP_LEGACY_F32_sdwa_gfx9 = 8444,
8460 : V_EXP_LEGACY_F32_sdwa_vi = 8445,
8461 : V_FFBH_I32_dpp = 8446,
8462 : V_FFBH_I32_e32_si = 8447,
8463 : V_FFBH_I32_e32_vi = 8448,
8464 : V_FFBH_I32_e64_si = 8449,
8465 : V_FFBH_I32_e64_vi = 8450,
8466 : V_FFBH_I32_sdwa_gfx9 = 8451,
8467 : V_FFBH_I32_sdwa_vi = 8452,
8468 : V_FFBH_U32_dpp = 8453,
8469 : V_FFBH_U32_e32_si = 8454,
8470 : V_FFBH_U32_e32_vi = 8455,
8471 : V_FFBH_U32_e64_si = 8456,
8472 : V_FFBH_U32_e64_vi = 8457,
8473 : V_FFBH_U32_sdwa_gfx9 = 8458,
8474 : V_FFBH_U32_sdwa_vi = 8459,
8475 : V_FFBL_B32_dpp = 8460,
8476 : V_FFBL_B32_e32_si = 8461,
8477 : V_FFBL_B32_e32_vi = 8462,
8478 : V_FFBL_B32_e64_si = 8463,
8479 : V_FFBL_B32_e64_vi = 8464,
8480 : V_FFBL_B32_sdwa_gfx9 = 8465,
8481 : V_FFBL_B32_sdwa_vi = 8466,
8482 : V_FLOOR_F16_dpp = 8467,
8483 : V_FLOOR_F16_e32_vi = 8468,
8484 : V_FLOOR_F16_e64_vi = 8469,
8485 : V_FLOOR_F16_sdwa_gfx9 = 8470,
8486 : V_FLOOR_F16_sdwa_vi = 8471,
8487 : V_FLOOR_F32_dpp = 8472,
8488 : V_FLOOR_F32_e32_si = 8473,
8489 : V_FLOOR_F32_e32_vi = 8474,
8490 : V_FLOOR_F32_e64_si = 8475,
8491 : V_FLOOR_F32_e64_vi = 8476,
8492 : V_FLOOR_F32_sdwa_gfx9 = 8477,
8493 : V_FLOOR_F32_sdwa_vi = 8478,
8494 : V_FLOOR_F64_dpp = 8479,
8495 : V_FLOOR_F64_e32_ci = 8480,
8496 : V_FLOOR_F64_e32_vi = 8481,
8497 : V_FLOOR_F64_e64_ci = 8482,
8498 : V_FLOOR_F64_e64_vi = 8483,
8499 : V_FLOOR_F64_sdwa_gfx9 = 8484,
8500 : V_FLOOR_F64_sdwa_vi = 8485,
8501 : V_FMAC_F32_dpp = 8486,
8502 : V_FMAC_F32_e32_vi = 8487,
8503 : V_FMAC_F32_e64_vi = 8488,
8504 : V_FMAC_F32_sdwa_gfx9 = 8489,
8505 : V_FMAC_F32_sdwa_vi = 8490,
8506 : V_FMA_F16_gfx9_gfx9 = 8491,
8507 : V_FMA_F16_vi = 8492,
8508 : V_FMA_F32_si = 8493,
8509 : V_FMA_F32_vi = 8494,
8510 : V_FMA_F64_si = 8495,
8511 : V_FMA_F64_vi = 8496,
8512 : V_FMA_LEGACY_F16_gfx9 = 8497,
8513 : V_FMA_MIXHI_F16_vi = 8498,
8514 : V_FMA_MIXLO_F16_vi = 8499,
8515 : V_FMA_MIX_F32_vi = 8500,
8516 : V_FRACT_F16_dpp = 8501,
8517 : V_FRACT_F16_e32_vi = 8502,
8518 : V_FRACT_F16_e64_vi = 8503,
8519 : V_FRACT_F16_sdwa_gfx9 = 8504,
8520 : V_FRACT_F16_sdwa_vi = 8505,
8521 : V_FRACT_F32_dpp = 8506,
8522 : V_FRACT_F32_e32_si = 8507,
8523 : V_FRACT_F32_e32_vi = 8508,
8524 : V_FRACT_F32_e64_si = 8509,
8525 : V_FRACT_F32_e64_vi = 8510,
8526 : V_FRACT_F32_sdwa_gfx9 = 8511,
8527 : V_FRACT_F32_sdwa_vi = 8512,
8528 : V_FRACT_F64_dpp = 8513,
8529 : V_FRACT_F64_e32_si = 8514,
8530 : V_FRACT_F64_e32_vi = 8515,
8531 : V_FRACT_F64_e64_si = 8516,
8532 : V_FRACT_F64_e64_vi = 8517,
8533 : V_FRACT_F64_sdwa_gfx9 = 8518,
8534 : V_FRACT_F64_sdwa_vi = 8519,
8535 : V_FREXP_EXP_I16_F16_dpp = 8520,
8536 : V_FREXP_EXP_I16_F16_e32_vi = 8521,
8537 : V_FREXP_EXP_I16_F16_e64_vi = 8522,
8538 : V_FREXP_EXP_I16_F16_sdwa_gfx9 = 8523,
8539 : V_FREXP_EXP_I16_F16_sdwa_vi = 8524,
8540 : V_FREXP_EXP_I32_F32_dpp = 8525,
8541 : V_FREXP_EXP_I32_F32_e32_si = 8526,
8542 : V_FREXP_EXP_I32_F32_e32_vi = 8527,
8543 : V_FREXP_EXP_I32_F32_e64_si = 8528,
8544 : V_FREXP_EXP_I32_F32_e64_vi = 8529,
8545 : V_FREXP_EXP_I32_F32_sdwa_gfx9 = 8530,
8546 : V_FREXP_EXP_I32_F32_sdwa_vi = 8531,
8547 : V_FREXP_EXP_I32_F64_dpp = 8532,
8548 : V_FREXP_EXP_I32_F64_e32_si = 8533,
8549 : V_FREXP_EXP_I32_F64_e32_vi = 8534,
8550 : V_FREXP_EXP_I32_F64_e64_si = 8535,
8551 : V_FREXP_EXP_I32_F64_e64_vi = 8536,
8552 : V_FREXP_EXP_I32_F64_sdwa_gfx9 = 8537,
8553 : V_FREXP_EXP_I32_F64_sdwa_vi = 8538,
8554 : V_FREXP_MANT_F16_dpp = 8539,
8555 : V_FREXP_MANT_F16_e32_vi = 8540,
8556 : V_FREXP_MANT_F16_e64_vi = 8541,
8557 : V_FREXP_MANT_F16_sdwa_gfx9 = 8542,
8558 : V_FREXP_MANT_F16_sdwa_vi = 8543,
8559 : V_FREXP_MANT_F32_dpp = 8544,
8560 : V_FREXP_MANT_F32_e32_si = 8545,
8561 : V_FREXP_MANT_F32_e32_vi = 8546,
8562 : V_FREXP_MANT_F32_e64_si = 8547,
8563 : V_FREXP_MANT_F32_e64_vi = 8548,
8564 : V_FREXP_MANT_F32_sdwa_gfx9 = 8549,
8565 : V_FREXP_MANT_F32_sdwa_vi = 8550,
8566 : V_FREXP_MANT_F64_dpp = 8551,
8567 : V_FREXP_MANT_F64_e32_si = 8552,
8568 : V_FREXP_MANT_F64_e32_vi = 8553,
8569 : V_FREXP_MANT_F64_e64_si = 8554,
8570 : V_FREXP_MANT_F64_e64_vi = 8555,
8571 : V_FREXP_MANT_F64_sdwa_gfx9 = 8556,
8572 : V_FREXP_MANT_F64_sdwa_vi = 8557,
8573 : V_INTERP_MOV_F32_e64_vi = 8558,
8574 : V_INTERP_MOV_F32_si = 8559,
8575 : V_INTERP_MOV_F32_vi = 8560,
8576 : V_INTERP_P1LL_F16_vi = 8561,
8577 : V_INTERP_P1LV_F16_vi = 8562,
8578 : V_INTERP_P1_F32_16bank_si = 8563,
8579 : V_INTERP_P1_F32_16bank_vi = 8564,
8580 : V_INTERP_P1_F32_e64_vi = 8565,
8581 : V_INTERP_P1_F32_si = 8566,
8582 : V_INTERP_P1_F32_vi = 8567,
8583 : V_INTERP_P2_F16_gfx9_gfx9 = 8568,
8584 : V_INTERP_P2_F16_vi = 8569,
8585 : V_INTERP_P2_F32_e64_vi = 8570,
8586 : V_INTERP_P2_F32_si = 8571,
8587 : V_INTERP_P2_F32_vi = 8572,
8588 : V_INTERP_P2_LEGACY_F16_gfx9 = 8573,
8589 : V_LDEXP_F16_dpp = 8574,
8590 : V_LDEXP_F16_e32_vi = 8575,
8591 : V_LDEXP_F16_e64_vi = 8576,
8592 : V_LDEXP_F16_sdwa_gfx9 = 8577,
8593 : V_LDEXP_F16_sdwa_vi = 8578,
8594 : V_LDEXP_F32_e32_si = 8579,
8595 : V_LDEXP_F32_e64_si = 8580,
8596 : V_LDEXP_F32_e64_vi = 8581,
8597 : V_LDEXP_F64_si = 8582,
8598 : V_LDEXP_F64_vi = 8583,
8599 : V_LERP_U8_si = 8584,
8600 : V_LERP_U8_vi = 8585,
8601 : V_LOG_CLAMP_F32_e32_si = 8586,
8602 : V_LOG_CLAMP_F32_e64_si = 8587,
8603 : V_LOG_F16_dpp = 8588,
8604 : V_LOG_F16_e32_vi = 8589,
8605 : V_LOG_F16_e64_vi = 8590,
8606 : V_LOG_F16_sdwa_gfx9 = 8591,
8607 : V_LOG_F16_sdwa_vi = 8592,
8608 : V_LOG_F32_dpp = 8593,
8609 : V_LOG_F32_e32_si = 8594,
8610 : V_LOG_F32_e32_vi = 8595,
8611 : V_LOG_F32_e64_si = 8596,
8612 : V_LOG_F32_e64_vi = 8597,
8613 : V_LOG_F32_sdwa_gfx9 = 8598,
8614 : V_LOG_F32_sdwa_vi = 8599,
8615 : V_LOG_LEGACY_F32_dpp = 8600,
8616 : V_LOG_LEGACY_F32_e32_ci = 8601,
8617 : V_LOG_LEGACY_F32_e32_vi = 8602,
8618 : V_LOG_LEGACY_F32_e64_ci = 8603,
8619 : V_LOG_LEGACY_F32_e64_vi = 8604,
8620 : V_LOG_LEGACY_F32_sdwa_gfx9 = 8605,
8621 : V_LOG_LEGACY_F32_sdwa_vi = 8606,
8622 : V_LSHLREV_B16_dpp = 8607,
8623 : V_LSHLREV_B16_e32_vi = 8608,
8624 : V_LSHLREV_B16_e64_vi = 8609,
8625 : V_LSHLREV_B16_sdwa_gfx9 = 8610,
8626 : V_LSHLREV_B16_sdwa_vi = 8611,
8627 : V_LSHLREV_B32_dpp = 8612,
8628 : V_LSHLREV_B32_e32_si = 8613,
8629 : V_LSHLREV_B32_e32_vi = 8614,
8630 : V_LSHLREV_B32_e64_si = 8615,
8631 : V_LSHLREV_B32_e64_vi = 8616,
8632 : V_LSHLREV_B32_sdwa_gfx9 = 8617,
8633 : V_LSHLREV_B32_sdwa_vi = 8618,
8634 : V_LSHLREV_B64_vi = 8619,
8635 : V_LSHL_ADD_U32_vi = 8620,
8636 : V_LSHL_B32_e32_si = 8621,
8637 : V_LSHL_B32_e64_si = 8622,
8638 : V_LSHL_B64_si = 8623,
8639 : V_LSHL_OR_B32_vi = 8624,
8640 : V_LSHRREV_B16_dpp = 8625,
8641 : V_LSHRREV_B16_e32_vi = 8626,
8642 : V_LSHRREV_B16_e64_vi = 8627,
8643 : V_LSHRREV_B16_sdwa_gfx9 = 8628,
8644 : V_LSHRREV_B16_sdwa_vi = 8629,
8645 : V_LSHRREV_B32_dpp = 8630,
8646 : V_LSHRREV_B32_e32_si = 8631,
8647 : V_LSHRREV_B32_e32_vi = 8632,
8648 : V_LSHRREV_B32_e64_si = 8633,
8649 : V_LSHRREV_B32_e64_vi = 8634,
8650 : V_LSHRREV_B32_sdwa_gfx9 = 8635,
8651 : V_LSHRREV_B32_sdwa_vi = 8636,
8652 : V_LSHRREV_B64_vi = 8637,
8653 : V_LSHR_B32_e32_si = 8638,
8654 : V_LSHR_B32_e64_si = 8639,
8655 : V_LSHR_B64_si = 8640,
8656 : V_MAC_F16_dpp = 8641,
8657 : V_MAC_F16_e32_vi = 8642,
8658 : V_MAC_F16_e64_vi = 8643,
8659 : V_MAC_F16_sdwa_gfx9 = 8644,
8660 : V_MAC_F16_sdwa_vi = 8645,
8661 : V_MAC_F32_dpp = 8646,
8662 : V_MAC_F32_e32_si = 8647,
8663 : V_MAC_F32_e32_vi = 8648,
8664 : V_MAC_F32_e64_si = 8649,
8665 : V_MAC_F32_e64_vi = 8650,
8666 : V_MAC_F32_sdwa_gfx9 = 8651,
8667 : V_MAC_F32_sdwa_vi = 8652,
8668 : V_MAC_LEGACY_F32_e32_si = 8653,
8669 : V_MAC_LEGACY_F32_e64_si = 8654,
8670 : V_MADAK_F16_vi = 8655,
8671 : V_MADAK_F32_si = 8656,
8672 : V_MADAK_F32_vi = 8657,
8673 : V_MADMK_F16_vi = 8658,
8674 : V_MADMK_F32_si = 8659,
8675 : V_MADMK_F32_vi = 8660,
8676 : V_MAD_F16_gfx9_gfx9 = 8661,
8677 : V_MAD_F16_vi = 8662,
8678 : V_MAD_F32_si = 8663,
8679 : V_MAD_F32_vi = 8664,
8680 : V_MAD_I16_gfx9_gfx9 = 8665,
8681 : V_MAD_I16_vi = 8666,
8682 : V_MAD_I32_I16_vi = 8667,
8683 : V_MAD_I32_I24_si = 8668,
8684 : V_MAD_I32_I24_vi = 8669,
8685 : V_MAD_I64_I32_ci = 8670,
8686 : V_MAD_I64_I32_vi = 8671,
8687 : V_MAD_LEGACY_F16_gfx9 = 8672,
8688 : V_MAD_LEGACY_F32_si = 8673,
8689 : V_MAD_LEGACY_F32_vi = 8674,
8690 : V_MAD_LEGACY_I16_gfx9 = 8675,
8691 : V_MAD_LEGACY_U16_gfx9 = 8676,
8692 : V_MAD_MIXHI_F16_vi = 8677,
8693 : V_MAD_MIXLO_F16_vi = 8678,
8694 : V_MAD_MIX_F32_vi = 8679,
8695 : V_MAD_U16_gfx9_gfx9 = 8680,
8696 : V_MAD_U16_vi = 8681,
8697 : V_MAD_U32_U16_vi = 8682,
8698 : V_MAD_U32_U24_si = 8683,
8699 : V_MAD_U32_U24_vi = 8684,
8700 : V_MAD_U64_U32_ci = 8685,
8701 : V_MAD_U64_U32_vi = 8686,
8702 : V_MAX3_F16_vi = 8687,
8703 : V_MAX3_F32_si = 8688,
8704 : V_MAX3_F32_vi = 8689,
8705 : V_MAX3_I16_vi = 8690,
8706 : V_MAX3_I32_si = 8691,
8707 : V_MAX3_I32_vi = 8692,
8708 : V_MAX3_U16_vi = 8693,
8709 : V_MAX3_U32_si = 8694,
8710 : V_MAX3_U32_vi = 8695,
8711 : V_MAX_F16_dpp = 8696,
8712 : V_MAX_F16_e32_vi = 8697,
8713 : V_MAX_F16_e64_vi = 8698,
8714 : V_MAX_F16_sdwa_gfx9 = 8699,
8715 : V_MAX_F16_sdwa_vi = 8700,
8716 : V_MAX_F32_dpp = 8701,
8717 : V_MAX_F32_e32_si = 8702,
8718 : V_MAX_F32_e32_vi = 8703,
8719 : V_MAX_F32_e64_si = 8704,
8720 : V_MAX_F32_e64_vi = 8705,
8721 : V_MAX_F32_sdwa_gfx9 = 8706,
8722 : V_MAX_F32_sdwa_vi = 8707,
8723 : V_MAX_F64_si = 8708,
8724 : V_MAX_F64_vi = 8709,
8725 : V_MAX_I16_dpp = 8710,
8726 : V_MAX_I16_e32_vi = 8711,
8727 : V_MAX_I16_e64_vi = 8712,
8728 : V_MAX_I16_sdwa_gfx9 = 8713,
8729 : V_MAX_I16_sdwa_vi = 8714,
8730 : V_MAX_I32_dpp = 8715,
8731 : V_MAX_I32_e32_si = 8716,
8732 : V_MAX_I32_e32_vi = 8717,
8733 : V_MAX_I32_e64_si = 8718,
8734 : V_MAX_I32_e64_vi = 8719,
8735 : V_MAX_I32_sdwa_gfx9 = 8720,
8736 : V_MAX_I32_sdwa_vi = 8721,
8737 : V_MAX_LEGACY_F32_e32_si = 8722,
8738 : V_MAX_LEGACY_F32_e64_si = 8723,
8739 : V_MAX_U16_dpp = 8724,
8740 : V_MAX_U16_e32_vi = 8725,
8741 : V_MAX_U16_e64_vi = 8726,
8742 : V_MAX_U16_sdwa_gfx9 = 8727,
8743 : V_MAX_U16_sdwa_vi = 8728,
8744 : V_MAX_U32_dpp = 8729,
8745 : V_MAX_U32_e32_si = 8730,
8746 : V_MAX_U32_e32_vi = 8731,
8747 : V_MAX_U32_e64_si = 8732,
8748 : V_MAX_U32_e64_vi = 8733,
8749 : V_MAX_U32_sdwa_gfx9 = 8734,
8750 : V_MAX_U32_sdwa_vi = 8735,
8751 : V_MBCNT_HI_U32_B32_e32_si = 8736,
8752 : V_MBCNT_HI_U32_B32_e64_si = 8737,
8753 : V_MBCNT_HI_U32_B32_e64_vi = 8738,
8754 : V_MBCNT_LO_U32_B32_e32_si = 8739,
8755 : V_MBCNT_LO_U32_B32_e64_si = 8740,
8756 : V_MBCNT_LO_U32_B32_e64_vi = 8741,
8757 : V_MED3_F16_vi = 8742,
8758 : V_MED3_F32_si = 8743,
8759 : V_MED3_F32_vi = 8744,
8760 : V_MED3_I16_vi = 8745,
8761 : V_MED3_I32_si = 8746,
8762 : V_MED3_I32_vi = 8747,
8763 : V_MED3_U16_vi = 8748,
8764 : V_MED3_U32_si = 8749,
8765 : V_MED3_U32_vi = 8750,
8766 : V_MIN3_F16_vi = 8751,
8767 : V_MIN3_F32_si = 8752,
8768 : V_MIN3_F32_vi = 8753,
8769 : V_MIN3_I16_vi = 8754,
8770 : V_MIN3_I32_si = 8755,
8771 : V_MIN3_I32_vi = 8756,
8772 : V_MIN3_U16_vi = 8757,
8773 : V_MIN3_U32_si = 8758,
8774 : V_MIN3_U32_vi = 8759,
8775 : V_MIN_F16_dpp = 8760,
8776 : V_MIN_F16_e32_vi = 8761,
8777 : V_MIN_F16_e64_vi = 8762,
8778 : V_MIN_F16_sdwa_gfx9 = 8763,
8779 : V_MIN_F16_sdwa_vi = 8764,
8780 : V_MIN_F32_dpp = 8765,
8781 : V_MIN_F32_e32_si = 8766,
8782 : V_MIN_F32_e32_vi = 8767,
8783 : V_MIN_F32_e64_si = 8768,
8784 : V_MIN_F32_e64_vi = 8769,
8785 : V_MIN_F32_sdwa_gfx9 = 8770,
8786 : V_MIN_F32_sdwa_vi = 8771,
8787 : V_MIN_F64_si = 8772,
8788 : V_MIN_F64_vi = 8773,
8789 : V_MIN_I16_dpp = 8774,
8790 : V_MIN_I16_e32_vi = 8775,
8791 : V_MIN_I16_e64_vi = 8776,
8792 : V_MIN_I16_sdwa_gfx9 = 8777,
8793 : V_MIN_I16_sdwa_vi = 8778,
8794 : V_MIN_I32_dpp = 8779,
8795 : V_MIN_I32_e32_si = 8780,
8796 : V_MIN_I32_e32_vi = 8781,
8797 : V_MIN_I32_e64_si = 8782,
8798 : V_MIN_I32_e64_vi = 8783,
8799 : V_MIN_I32_sdwa_gfx9 = 8784,
8800 : V_MIN_I32_sdwa_vi = 8785,
8801 : V_MIN_LEGACY_F32_e32_si = 8786,
8802 : V_MIN_LEGACY_F32_e64_si = 8787,
8803 : V_MIN_U16_dpp = 8788,
8804 : V_MIN_U16_e32_vi = 8789,
8805 : V_MIN_U16_e64_vi = 8790,
8806 : V_MIN_U16_sdwa_gfx9 = 8791,
8807 : V_MIN_U16_sdwa_vi = 8792,
8808 : V_MIN_U32_dpp = 8793,
8809 : V_MIN_U32_e32_si = 8794,
8810 : V_MIN_U32_e32_vi = 8795,
8811 : V_MIN_U32_e64_si = 8796,
8812 : V_MIN_U32_e64_vi = 8797,
8813 : V_MIN_U32_sdwa_gfx9 = 8798,
8814 : V_MIN_U32_sdwa_vi = 8799,
8815 : V_MOVRELD_B32_e32_si = 8800,
8816 : V_MOVRELD_B32_e32_vi = 8801,
8817 : V_MOVRELD_B32_e64_si = 8802,
8818 : V_MOVRELD_B32_e64_vi = 8803,
8819 : V_MOVRELSD_B32_e32_si = 8804,
8820 : V_MOVRELSD_B32_e32_vi = 8805,
8821 : V_MOVRELSD_B32_e64_si = 8806,
8822 : V_MOVRELSD_B32_e64_vi = 8807,
8823 : V_MOVRELS_B32_e32_si = 8808,
8824 : V_MOVRELS_B32_e32_vi = 8809,
8825 : V_MOVRELS_B32_e64_si = 8810,
8826 : V_MOVRELS_B32_e64_vi = 8811,
8827 : V_MOV_B32_dpp = 8812,
8828 : V_MOV_B32_e32_si = 8813,
8829 : V_MOV_B32_e32_vi = 8814,
8830 : V_MOV_B32_e64_si = 8815,
8831 : V_MOV_B32_e64_vi = 8816,
8832 : V_MOV_B32_sdwa_gfx9 = 8817,
8833 : V_MOV_B32_sdwa_vi = 8818,
8834 : V_MOV_FED_B32_dpp = 8819,
8835 : V_MOV_FED_B32_e32_si = 8820,
8836 : V_MOV_FED_B32_e32_vi = 8821,
8837 : V_MOV_FED_B32_e64_si = 8822,
8838 : V_MOV_FED_B32_e64_vi = 8823,
8839 : V_MOV_FED_B32_sdwa_gfx9 = 8824,
8840 : V_MOV_FED_B32_sdwa_vi = 8825,
8841 : V_MQSAD_PK_U16_U8_si = 8826,
8842 : V_MQSAD_PK_U16_U8_vi = 8827,
8843 : V_MQSAD_U32_U8_ci = 8828,
8844 : V_MQSAD_U32_U8_vi = 8829,
8845 : V_MSAD_U8_si = 8830,
8846 : V_MSAD_U8_vi = 8831,
8847 : V_MULLIT_F32_si = 8832,
8848 : V_MUL_F16_dpp = 8833,
8849 : V_MUL_F16_e32_vi = 8834,
8850 : V_MUL_F16_e64_vi = 8835,
8851 : V_MUL_F16_sdwa_gfx9 = 8836,
8852 : V_MUL_F16_sdwa_vi = 8837,
8853 : V_MUL_F32_dpp = 8838,
8854 : V_MUL_F32_e32_si = 8839,
8855 : V_MUL_F32_e32_vi = 8840,
8856 : V_MUL_F32_e64_si = 8841,
8857 : V_MUL_F32_e64_vi = 8842,
8858 : V_MUL_F32_sdwa_gfx9 = 8843,
8859 : V_MUL_F32_sdwa_vi = 8844,
8860 : V_MUL_F64_si = 8845,
8861 : V_MUL_F64_vi = 8846,
8862 : V_MUL_HI_I32_I24_dpp = 8847,
8863 : V_MUL_HI_I32_I24_e32_si = 8848,
8864 : V_MUL_HI_I32_I24_e32_vi = 8849,
8865 : V_MUL_HI_I32_I24_e64_si = 8850,
8866 : V_MUL_HI_I32_I24_e64_vi = 8851,
8867 : V_MUL_HI_I32_I24_sdwa_gfx9 = 8852,
8868 : V_MUL_HI_I32_I24_sdwa_vi = 8853,
8869 : V_MUL_HI_I32_si = 8854,
8870 : V_MUL_HI_I32_vi = 8855,
8871 : V_MUL_HI_U32_U24_dpp = 8856,
8872 : V_MUL_HI_U32_U24_e32_si = 8857,
8873 : V_MUL_HI_U32_U24_e32_vi = 8858,
8874 : V_MUL_HI_U32_U24_e64_si = 8859,
8875 : V_MUL_HI_U32_U24_e64_vi = 8860,
8876 : V_MUL_HI_U32_U24_sdwa_gfx9 = 8861,
8877 : V_MUL_HI_U32_U24_sdwa_vi = 8862,
8878 : V_MUL_HI_U32_si = 8863,
8879 : V_MUL_HI_U32_vi = 8864,
8880 : V_MUL_I32_I24_dpp = 8865,
8881 : V_MUL_I32_I24_e32_si = 8866,
8882 : V_MUL_I32_I24_e32_vi = 8867,
8883 : V_MUL_I32_I24_e64_si = 8868,
8884 : V_MUL_I32_I24_e64_vi = 8869,
8885 : V_MUL_I32_I24_sdwa_gfx9 = 8870,
8886 : V_MUL_I32_I24_sdwa_vi = 8871,
8887 : V_MUL_LEGACY_F32_dpp = 8872,
8888 : V_MUL_LEGACY_F32_e32_si = 8873,
8889 : V_MUL_LEGACY_F32_e32_vi = 8874,
8890 : V_MUL_LEGACY_F32_e64_si = 8875,
8891 : V_MUL_LEGACY_F32_e64_vi = 8876,
8892 : V_MUL_LEGACY_F32_sdwa_gfx9 = 8877,
8893 : V_MUL_LEGACY_F32_sdwa_vi = 8878,
8894 : V_MUL_LO_I32_si = 8879,
8895 : V_MUL_LO_I32_vi = 8880,
8896 : V_MUL_LO_U16_dpp = 8881,
8897 : V_MUL_LO_U16_e32_vi = 8882,
8898 : V_MUL_LO_U16_e64_vi = 8883,
8899 : V_MUL_LO_U16_sdwa_gfx9 = 8884,
8900 : V_MUL_LO_U16_sdwa_vi = 8885,
8901 : V_MUL_LO_U32_si = 8886,
8902 : V_MUL_LO_U32_vi = 8887,
8903 : V_MUL_U32_U24_dpp = 8888,
8904 : V_MUL_U32_U24_e32_si = 8889,
8905 : V_MUL_U32_U24_e32_vi = 8890,
8906 : V_MUL_U32_U24_e64_si = 8891,
8907 : V_MUL_U32_U24_e64_vi = 8892,
8908 : V_MUL_U32_U24_sdwa_gfx9 = 8893,
8909 : V_MUL_U32_U24_sdwa_vi = 8894,
8910 : V_NOP_dpp = 8895,
8911 : V_NOP_e32_si = 8896,
8912 : V_NOP_e32_vi = 8897,
8913 : V_NOP_e64_si = 8898,
8914 : V_NOP_e64_vi = 8899,
8915 : V_NOP_sdwa_gfx9 = 8900,
8916 : V_NOP_sdwa_vi = 8901,
8917 : V_NOT_B32_dpp = 8902,
8918 : V_NOT_B32_e32_si = 8903,
8919 : V_NOT_B32_e32_vi = 8904,
8920 : V_NOT_B32_e64_si = 8905,
8921 : V_NOT_B32_e64_vi = 8906,
8922 : V_NOT_B32_sdwa_gfx9 = 8907,
8923 : V_NOT_B32_sdwa_vi = 8908,
8924 : V_OR3_B32_vi = 8909,
8925 : V_OR_B32_dpp = 8910,
8926 : V_OR_B32_e32_si = 8911,
8927 : V_OR_B32_e32_vi = 8912,
8928 : V_OR_B32_e64_si = 8913,
8929 : V_OR_B32_e64_vi = 8914,
8930 : V_OR_B32_sdwa_gfx9 = 8915,
8931 : V_OR_B32_sdwa_vi = 8916,
8932 : V_PACK_B32_F16_vi = 8917,
8933 : V_PERM_B32_vi = 8918,
8934 : V_PK_ADD_F16_vi = 8919,
8935 : V_PK_ADD_I16_vi = 8920,
8936 : V_PK_ADD_U16_vi = 8921,
8937 : V_PK_ASHRREV_I16_vi = 8922,
8938 : V_PK_FMA_F16_vi = 8923,
8939 : V_PK_LSHLREV_B16_vi = 8924,
8940 : V_PK_LSHRREV_B16_vi = 8925,
8941 : V_PK_MAD_I16_vi = 8926,
8942 : V_PK_MAD_U16_vi = 8927,
8943 : V_PK_MAX_F16_vi = 8928,
8944 : V_PK_MAX_I16_vi = 8929,
8945 : V_PK_MAX_U16_vi = 8930,
8946 : V_PK_MIN_F16_vi = 8931,
8947 : V_PK_MIN_I16_vi = 8932,
8948 : V_PK_MIN_U16_vi = 8933,
8949 : V_PK_MUL_F16_vi = 8934,
8950 : V_PK_MUL_LO_U16_vi = 8935,
8951 : V_PK_SUB_I16_vi = 8936,
8952 : V_PK_SUB_U16_vi = 8937,
8953 : V_QSAD_PK_U16_U8_ci = 8938,
8954 : V_QSAD_PK_U16_U8_vi = 8939,
8955 : V_RCP_CLAMP_F32_e32_si = 8940,
8956 : V_RCP_CLAMP_F32_e64_si = 8941,
8957 : V_RCP_CLAMP_F64_e32_si = 8942,
8958 : V_RCP_CLAMP_F64_e64_si = 8943,
8959 : V_RCP_F16_dpp = 8944,
8960 : V_RCP_F16_e32_vi = 8945,
8961 : V_RCP_F16_e64_vi = 8946,
8962 : V_RCP_F16_sdwa_gfx9 = 8947,
8963 : V_RCP_F16_sdwa_vi = 8948,
8964 : V_RCP_F32_dpp = 8949,
8965 : V_RCP_F32_e32_si = 8950,
8966 : V_RCP_F32_e32_vi = 8951,
8967 : V_RCP_F32_e64_si = 8952,
8968 : V_RCP_F32_e64_vi = 8953,
8969 : V_RCP_F32_sdwa_gfx9 = 8954,
8970 : V_RCP_F32_sdwa_vi = 8955,
8971 : V_RCP_F64_dpp = 8956,
8972 : V_RCP_F64_e32_si = 8957,
8973 : V_RCP_F64_e32_vi = 8958,
8974 : V_RCP_F64_e64_si = 8959,
8975 : V_RCP_F64_e64_vi = 8960,
8976 : V_RCP_F64_sdwa_gfx9 = 8961,
8977 : V_RCP_F64_sdwa_vi = 8962,
8978 : V_RCP_IFLAG_F32_dpp = 8963,
8979 : V_RCP_IFLAG_F32_e32_si = 8964,
8980 : V_RCP_IFLAG_F32_e32_vi = 8965,
8981 : V_RCP_IFLAG_F32_e64_si = 8966,
8982 : V_RCP_IFLAG_F32_e64_vi = 8967,
8983 : V_RCP_IFLAG_F32_sdwa_gfx9 = 8968,
8984 : V_RCP_IFLAG_F32_sdwa_vi = 8969,
8985 : V_RCP_LEGACY_F32_e32_si = 8970,
8986 : V_RCP_LEGACY_F32_e64_si = 8971,
8987 : V_READFIRSTLANE_B32 = 8972,
8988 : V_READLANE_B32_si = 8973,
8989 : V_READLANE_B32_vi = 8974,
8990 : V_RNDNE_F16_dpp = 8975,
8991 : V_RNDNE_F16_e32_vi = 8976,
8992 : V_RNDNE_F16_e64_vi = 8977,
8993 : V_RNDNE_F16_sdwa_gfx9 = 8978,
8994 : V_RNDNE_F16_sdwa_vi = 8979,
8995 : V_RNDNE_F32_dpp = 8980,
8996 : V_RNDNE_F32_e32_si = 8981,
8997 : V_RNDNE_F32_e32_vi = 8982,
8998 : V_RNDNE_F32_e64_si = 8983,
8999 : V_RNDNE_F32_e64_vi = 8984,
9000 : V_RNDNE_F32_sdwa_gfx9 = 8985,
9001 : V_RNDNE_F32_sdwa_vi = 8986,
9002 : V_RNDNE_F64_dpp = 8987,
9003 : V_RNDNE_F64_e32_ci = 8988,
9004 : V_RNDNE_F64_e32_vi = 8989,
9005 : V_RNDNE_F64_e64_ci = 8990,
9006 : V_RNDNE_F64_e64_vi = 8991,
9007 : V_RNDNE_F64_sdwa_gfx9 = 8992,
9008 : V_RNDNE_F64_sdwa_vi = 8993,
9009 : V_RSQ_CLAMP_F32_e32_si = 8994,
9010 : V_RSQ_CLAMP_F32_e64_si = 8995,
9011 : V_RSQ_CLAMP_F64_e32_si = 8996,
9012 : V_RSQ_CLAMP_F64_e64_si = 8997,
9013 : V_RSQ_F16_dpp = 8998,
9014 : V_RSQ_F16_e32_vi = 8999,
9015 : V_RSQ_F16_e64_vi = 9000,
9016 : V_RSQ_F16_sdwa_gfx9 = 9001,
9017 : V_RSQ_F16_sdwa_vi = 9002,
9018 : V_RSQ_F32_dpp = 9003,
9019 : V_RSQ_F32_e32_si = 9004,
9020 : V_RSQ_F32_e32_vi = 9005,
9021 : V_RSQ_F32_e64_si = 9006,
9022 : V_RSQ_F32_e64_vi = 9007,
9023 : V_RSQ_F32_sdwa_gfx9 = 9008,
9024 : V_RSQ_F32_sdwa_vi = 9009,
9025 : V_RSQ_F64_dpp = 9010,
9026 : V_RSQ_F64_e32_si = 9011,
9027 : V_RSQ_F64_e32_vi = 9012,
9028 : V_RSQ_F64_e64_si = 9013,
9029 : V_RSQ_F64_e64_vi = 9014,
9030 : V_RSQ_F64_sdwa_gfx9 = 9015,
9031 : V_RSQ_F64_sdwa_vi = 9016,
9032 : V_RSQ_LEGACY_F32_e32_si = 9017,
9033 : V_RSQ_LEGACY_F32_e64_si = 9018,
9034 : V_SAD_HI_U8_si = 9019,
9035 : V_SAD_HI_U8_vi = 9020,
9036 : V_SAD_U16_si = 9021,
9037 : V_SAD_U16_vi = 9022,
9038 : V_SAD_U32_si = 9023,
9039 : V_SAD_U32_vi = 9024,
9040 : V_SAD_U8_si = 9025,
9041 : V_SAD_U8_vi = 9026,
9042 : V_SAT_PK_U8_I16_dpp = 9027,
9043 : V_SAT_PK_U8_I16_e32_vi = 9028,
9044 : V_SAT_PK_U8_I16_e64_vi = 9029,
9045 : V_SAT_PK_U8_I16_sdwa_gfx9 = 9030,
9046 : V_SAT_PK_U8_I16_sdwa_vi = 9031,
9047 : V_SCREEN_PARTITION_4SE_B32_dpp = 9032,
9048 : V_SCREEN_PARTITION_4SE_B32_e32_vi = 9033,
9049 : V_SCREEN_PARTITION_4SE_B32_e64_vi = 9034,
9050 : V_SCREEN_PARTITION_4SE_B32_sdwa_gfx9 = 9035,
9051 : V_SIN_F16_dpp = 9036,
9052 : V_SIN_F16_e32_vi = 9037,
9053 : V_SIN_F16_e64_vi = 9038,
9054 : V_SIN_F16_sdwa_gfx9 = 9039,
9055 : V_SIN_F16_sdwa_vi = 9040,
9056 : V_SIN_F32_dpp = 9041,
9057 : V_SIN_F32_e32_si = 9042,
9058 : V_SIN_F32_e32_vi = 9043,
9059 : V_SIN_F32_e64_si = 9044,
9060 : V_SIN_F32_e64_vi = 9045,
9061 : V_SIN_F32_sdwa_gfx9 = 9046,
9062 : V_SIN_F32_sdwa_vi = 9047,
9063 : V_SQRT_F16_dpp = 9048,
9064 : V_SQRT_F16_e32_vi = 9049,
9065 : V_SQRT_F16_e64_vi = 9050,
9066 : V_SQRT_F16_sdwa_gfx9 = 9051,
9067 : V_SQRT_F16_sdwa_vi = 9052,
9068 : V_SQRT_F32_dpp = 9053,
9069 : V_SQRT_F32_e32_si = 9054,
9070 : V_SQRT_F32_e32_vi = 9055,
9071 : V_SQRT_F32_e64_si = 9056,
9072 : V_SQRT_F32_e64_vi = 9057,
9073 : V_SQRT_F32_sdwa_gfx9 = 9058,
9074 : V_SQRT_F32_sdwa_vi = 9059,
9075 : V_SQRT_F64_dpp = 9060,
9076 : V_SQRT_F64_e32_si = 9061,
9077 : V_SQRT_F64_e32_vi = 9062,
9078 : V_SQRT_F64_e64_si = 9063,
9079 : V_SQRT_F64_e64_vi = 9064,
9080 : V_SQRT_F64_sdwa_gfx9 = 9065,
9081 : V_SQRT_F64_sdwa_vi = 9066,
9082 : V_SUBBREV_CO_U32_dpp_gfx9 = 9067,
9083 : V_SUBBREV_CO_U32_e32_gfx9 = 9068,
9084 : V_SUBBREV_CO_U32_e64_gfx9 = 9069,
9085 : V_SUBBREV_CO_U32_sdwa_gfx9 = 9070,
9086 : V_SUBBREV_U32_dpp = 9071,
9087 : V_SUBBREV_U32_e32_si = 9072,
9088 : V_SUBBREV_U32_e32_vi = 9073,
9089 : V_SUBBREV_U32_e64_si = 9074,
9090 : V_SUBBREV_U32_e64_vi = 9075,
9091 : V_SUBBREV_U32_sdwa_vi = 9076,
9092 : V_SUBB_CO_U32_dpp_gfx9 = 9077,
9093 : V_SUBB_CO_U32_e32_gfx9 = 9078,
9094 : V_SUBB_CO_U32_e64_gfx9 = 9079,
9095 : V_SUBB_CO_U32_sdwa_gfx9 = 9080,
9096 : V_SUBB_U32_dpp = 9081,
9097 : V_SUBB_U32_e32_si = 9082,
9098 : V_SUBB_U32_e32_vi = 9083,
9099 : V_SUBB_U32_e64_si = 9084,
9100 : V_SUBB_U32_e64_vi = 9085,
9101 : V_SUBB_U32_sdwa_vi = 9086,
9102 : V_SUBREV_CO_U32_dpp_gfx9 = 9087,
9103 : V_SUBREV_CO_U32_e32_gfx9 = 9088,
9104 : V_SUBREV_CO_U32_e64_gfx9 = 9089,
9105 : V_SUBREV_CO_U32_sdwa_gfx9 = 9090,
9106 : V_SUBREV_F16_dpp = 9091,
9107 : V_SUBREV_F16_e32_vi = 9092,
9108 : V_SUBREV_F16_e64_vi = 9093,
9109 : V_SUBREV_F16_sdwa_gfx9 = 9094,
9110 : V_SUBREV_F16_sdwa_vi = 9095,
9111 : V_SUBREV_F32_dpp = 9096,
9112 : V_SUBREV_F32_e32_si = 9097,
9113 : V_SUBREV_F32_e32_vi = 9098,
9114 : V_SUBREV_F32_e64_si = 9099,
9115 : V_SUBREV_F32_e64_vi = 9100,
9116 : V_SUBREV_F32_sdwa_gfx9 = 9101,
9117 : V_SUBREV_F32_sdwa_vi = 9102,
9118 : V_SUBREV_I32_e32_si = 9103,
9119 : V_SUBREV_I32_e64_si = 9104,
9120 : V_SUBREV_U16_dpp = 9105,
9121 : V_SUBREV_U16_e32_vi = 9106,
9122 : V_SUBREV_U16_e64_vi = 9107,
9123 : V_SUBREV_U16_sdwa_gfx9 = 9108,
9124 : V_SUBREV_U16_sdwa_vi = 9109,
9125 : V_SUBREV_U32_dpp = 9110,
9126 : V_SUBREV_U32_dpp_gfx9 = 9111,
9127 : V_SUBREV_U32_e32_gfx9 = 9112,
9128 : V_SUBREV_U32_e32_vi = 9113,
9129 : V_SUBREV_U32_e64_gfx9 = 9114,
9130 : V_SUBREV_U32_e64_vi = 9115,
9131 : V_SUBREV_U32_sdwa_gfx9 = 9116,
9132 : V_SUBREV_U32_sdwa_vi = 9117,
9133 : V_SUB_CO_U32_dpp_gfx9 = 9118,
9134 : V_SUB_CO_U32_e32_gfx9 = 9119,
9135 : V_SUB_CO_U32_e64_gfx9 = 9120,
9136 : V_SUB_CO_U32_sdwa_gfx9 = 9121,
9137 : V_SUB_F16_dpp = 9122,
9138 : V_SUB_F16_e32_vi = 9123,
9139 : V_SUB_F16_e64_vi = 9124,
9140 : V_SUB_F16_sdwa_gfx9 = 9125,
9141 : V_SUB_F16_sdwa_vi = 9126,
9142 : V_SUB_F32_dpp = 9127,
9143 : V_SUB_F32_e32_si = 9128,
9144 : V_SUB_F32_e32_vi = 9129,
9145 : V_SUB_F32_e64_si = 9130,
9146 : V_SUB_F32_e64_vi = 9131,
9147 : V_SUB_F32_sdwa_gfx9 = 9132,
9148 : V_SUB_F32_sdwa_vi = 9133,
9149 : V_SUB_I16_vi = 9134,
9150 : V_SUB_I32_e32_si = 9135,
9151 : V_SUB_I32_e64_si = 9136,
9152 : V_SUB_I32_gfx9_gfx9 = 9137,
9153 : V_SUB_U16_dpp = 9138,
9154 : V_SUB_U16_e32_vi = 9139,
9155 : V_SUB_U16_e64_vi = 9140,
9156 : V_SUB_U16_sdwa_gfx9 = 9141,
9157 : V_SUB_U16_sdwa_vi = 9142,
9158 : V_SUB_U32_dpp = 9143,
9159 : V_SUB_U32_dpp_gfx9 = 9144,
9160 : V_SUB_U32_e32_gfx9 = 9145,
9161 : V_SUB_U32_e32_vi = 9146,
9162 : V_SUB_U32_e64_gfx9 = 9147,
9163 : V_SUB_U32_e64_vi = 9148,
9164 : V_SUB_U32_sdwa_gfx9 = 9149,
9165 : V_SUB_U32_sdwa_vi = 9150,
9166 : V_SWAP_B32_vi = 9151,
9167 : V_TRIG_PREOP_F64_si = 9152,
9168 : V_TRIG_PREOP_F64_vi = 9153,
9169 : V_TRUNC_F16_dpp = 9154,
9170 : V_TRUNC_F16_e32_vi = 9155,
9171 : V_TRUNC_F16_e64_vi = 9156,
9172 : V_TRUNC_F16_sdwa_gfx9 = 9157,
9173 : V_TRUNC_F16_sdwa_vi = 9158,
9174 : V_TRUNC_F32_dpp = 9159,
9175 : V_TRUNC_F32_e32_si = 9160,
9176 : V_TRUNC_F32_e32_vi = 9161,
9177 : V_TRUNC_F32_e64_si = 9162,
9178 : V_TRUNC_F32_e64_vi = 9163,
9179 : V_TRUNC_F32_sdwa_gfx9 = 9164,
9180 : V_TRUNC_F32_sdwa_vi = 9165,
9181 : V_TRUNC_F64_dpp = 9166,
9182 : V_TRUNC_F64_e32_ci = 9167,
9183 : V_TRUNC_F64_e32_vi = 9168,
9184 : V_TRUNC_F64_e64_ci = 9169,
9185 : V_TRUNC_F64_e64_vi = 9170,
9186 : V_TRUNC_F64_sdwa_gfx9 = 9171,
9187 : V_TRUNC_F64_sdwa_vi = 9172,
9188 : V_WRITELANE_B32_si = 9173,
9189 : V_WRITELANE_B32_vi = 9174,
9190 : V_XAD_U32_vi = 9175,
9191 : V_XNOR_B32_dpp = 9176,
9192 : V_XNOR_B32_e32_vi = 9177,
9193 : V_XNOR_B32_e64_vi = 9178,
9194 : V_XNOR_B32_sdwa_gfx9 = 9179,
9195 : V_XNOR_B32_sdwa_vi = 9180,
9196 : V_XOR_B32_dpp = 9181,
9197 : V_XOR_B32_e32_si = 9182,
9198 : V_XOR_B32_e32_vi = 9183,
9199 : V_XOR_B32_e64_si = 9184,
9200 : V_XOR_B32_e64_vi = 9185,
9201 : V_XOR_B32_sdwa_gfx9 = 9186,
9202 : V_XOR_B32_sdwa_vi = 9187,
9203 : INSTRUCTION_LIST_END = 9188
9204 : };
9205 :
9206 : } // end AMDGPU namespace
9207 : } // end llvm namespace
9208 : #endif // GET_INSTRINFO_ENUM
9209 :
9210 : #ifdef GET_INSTRINFO_SCHED_ENUM
9211 : #undef GET_INSTRINFO_SCHED_ENUM
9212 : namespace llvm {
9213 :
9214 : namespace AMDGPU {
9215 : namespace Sched {
9216 : enum {
9217 : NoInstrModel = 0,
9218 : NullALU_Write32Bit = 1,
9219 : NullALU_WriteVMEM = 2,
9220 : NullALU_WriteLDS = 3,
9221 : NullALU_WriteExport = 4,
9222 : NullALU_WriteBranch = 5,
9223 : NullALU = 6,
9224 : NullALU_WriteSALU = 7,
9225 : NullALU_WriteSMEM = 8,
9226 : NullALU_Write32Bit_WriteSALU = 9,
9227 : NullALU_WriteDoubleAdd = 10,
9228 : NullALU_Write64Bit = 11,
9229 : NullALU_WriteQuarterRate32 = 12,
9230 : NullALU_WriteFloatFMA = 13,
9231 : NullALU_WriteDouble = 14,
9232 : NullALU_WriteFloatFMA_WriteSALU = 15,
9233 : NullALU_WriteDouble_WriteSALU = 16,
9234 : NullALU_WriteQuarterRate32_WriteSALU = 17,
9235 : NullALU_Write64Bit_Write64Bit = 18,
9236 : NullALU_WriteBarrier = 19,
9237 : COPY = 20,
9238 : SCHED_LIST_END = 21
9239 : };
9240 : } // end Sched namespace
9241 : } // end AMDGPU namespace
9242 : } // end llvm namespace
9243 : #endif // GET_INSTRINFO_SCHED_ENUM
9244 :
9245 : #ifdef GET_INSTRINFO_MC_DESC
9246 : #undef GET_INSTRINFO_MC_DESC
9247 : namespace llvm {
9248 :
9249 : static const MCPhysReg ImplicitList1[] = { AMDGPU::EXEC, 0 };
9250 : static const MCPhysReg ImplicitList2[] = { AMDGPU::EXEC, AMDGPU::M0, 0 };
9251 : static const MCPhysReg ImplicitList3[] = { AMDGPU::M0, AMDGPU::EXEC, 0 };
9252 : static const MCPhysReg ImplicitList4[] = { AMDGPU::EXEC, AMDGPU::FLAT_SCR, 0 };
9253 : static const MCPhysReg ImplicitList5[] = { AMDGPU::SCC, 0 };
9254 : static const MCPhysReg ImplicitList6[] = { AMDGPU::EXEC, AMDGPU::SCC, 0 };
9255 : static const MCPhysReg ImplicitList7[] = { AMDGPU::EXEC, AMDGPU::VCC, 0 };
9256 : static const MCPhysReg ImplicitList8[] = { AMDGPU::M0, AMDGPU::EXEC, AMDGPU::SCC, 0 };
9257 : static const MCPhysReg ImplicitList9[] = { AMDGPU::M0, 0 };
9258 : static const MCPhysReg ImplicitList10[] = { AMDGPU::EXEC, AMDGPU::VCC, AMDGPU::SCC, 0 };
9259 : static const MCPhysReg ImplicitList11[] = { AMDGPU::FLAT_SCR, 0 };
9260 : static const MCPhysReg ImplicitList12[] = { AMDGPU::VCC, AMDGPU::EXEC, 0 };
9261 : static const MCPhysReg ImplicitList13[] = { AMDGPU::VCC, 0 };
9262 :
9263 : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9264 : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9265 : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9266 : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9267 : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9268 : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9269 : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9270 : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9271 : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
9272 : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9273 : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9274 : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
9275 : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
9276 : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9277 : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9278 : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
9279 : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9280 : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
9281 : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
9282 : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
9283 : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
9284 : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
9285 : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
9286 : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
9287 : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
9288 : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9289 : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
9290 : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
9291 : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
9292 : static const MCOperandInfo OperandInfo31[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9293 : static const MCOperandInfo OperandInfo32[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9294 : static const MCOperandInfo OperandInfo33[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9295 : static const MCOperandInfo OperandInfo34[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9296 : static const MCOperandInfo OperandInfo35[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9297 : static const MCOperandInfo OperandInfo36[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9298 : static const MCOperandInfo OperandInfo37[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9299 : static const MCOperandInfo OperandInfo38[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9300 : static const MCOperandInfo OperandInfo39[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9301 : static const MCOperandInfo OperandInfo40[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9302 : static const MCOperandInfo OperandInfo41[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9303 : static const MCOperandInfo OperandInfo42[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9304 : static const MCOperandInfo OperandInfo43[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9305 : static const MCOperandInfo OperandInfo44[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9306 : static const MCOperandInfo OperandInfo45[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9307 : static const MCOperandInfo OperandInfo46[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9308 : static const MCOperandInfo OperandInfo47[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9309 : static const MCOperandInfo OperandInfo48[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9310 : static const MCOperandInfo OperandInfo49[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9311 : static const MCOperandInfo OperandInfo50[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9312 : static const MCOperandInfo OperandInfo51[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9313 : static const MCOperandInfo OperandInfo52[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9314 : static const MCOperandInfo OperandInfo53[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9315 : static const MCOperandInfo OperandInfo54[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9316 : static const MCOperandInfo OperandInfo55[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9317 : static const MCOperandInfo OperandInfo56[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9318 : static const MCOperandInfo OperandInfo57[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9319 : static const MCOperandInfo OperandInfo58[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9320 : static const MCOperandInfo OperandInfo59[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9321 : static const MCOperandInfo OperandInfo60[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9322 : static const MCOperandInfo OperandInfo61[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9323 : static const MCOperandInfo OperandInfo62[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9324 : static const MCOperandInfo OperandInfo63[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9325 : static const MCOperandInfo OperandInfo64[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9326 : static const MCOperandInfo OperandInfo65[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9327 : static const MCOperandInfo OperandInfo66[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9328 : static const MCOperandInfo OperandInfo67[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9329 : static const MCOperandInfo OperandInfo68[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9330 : static const MCOperandInfo OperandInfo69[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9331 : static const MCOperandInfo OperandInfo70[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9332 : static const MCOperandInfo OperandInfo71[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9333 : static const MCOperandInfo OperandInfo72[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9334 : static const MCOperandInfo OperandInfo73[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9335 : static const MCOperandInfo OperandInfo74[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9336 : static const MCOperandInfo OperandInfo75[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9337 : static const MCOperandInfo OperandInfo76[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9338 : static const MCOperandInfo OperandInfo77[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9339 : static const MCOperandInfo OperandInfo78[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9340 : static const MCOperandInfo OperandInfo79[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9341 : static const MCOperandInfo OperandInfo80[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9342 : static const MCOperandInfo OperandInfo81[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9343 : static const MCOperandInfo OperandInfo82[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9344 : static const MCOperandInfo OperandInfo83[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9345 : static const MCOperandInfo OperandInfo84[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9346 : static const MCOperandInfo OperandInfo85[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9347 : static const MCOperandInfo OperandInfo86[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9348 : static const MCOperandInfo OperandInfo87[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9349 : static const MCOperandInfo OperandInfo88[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9350 : static const MCOperandInfo OperandInfo89[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9351 : static const MCOperandInfo OperandInfo90[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9352 : static const MCOperandInfo OperandInfo91[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9353 : static const MCOperandInfo OperandInfo92[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9354 : static const MCOperandInfo OperandInfo93[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9355 : static const MCOperandInfo OperandInfo94[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9356 : static const MCOperandInfo OperandInfo95[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9357 : static const MCOperandInfo OperandInfo96[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9358 : static const MCOperandInfo OperandInfo97[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9359 : static const MCOperandInfo OperandInfo98[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9360 : static const MCOperandInfo OperandInfo99[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9361 : static const MCOperandInfo OperandInfo100[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9362 : static const MCOperandInfo OperandInfo101[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9363 : static const MCOperandInfo OperandInfo102[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9364 : static const MCOperandInfo OperandInfo103[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9365 : static const MCOperandInfo OperandInfo104[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9366 : static const MCOperandInfo OperandInfo105[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9367 : static const MCOperandInfo OperandInfo106[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9368 : static const MCOperandInfo OperandInfo107[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9369 : static const MCOperandInfo OperandInfo108[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9370 : static const MCOperandInfo OperandInfo109[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9371 : static const MCOperandInfo OperandInfo110[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9372 : static const MCOperandInfo OperandInfo111[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9373 : static const MCOperandInfo OperandInfo112[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9374 : static const MCOperandInfo OperandInfo113[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9375 : static const MCOperandInfo OperandInfo114[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9376 : static const MCOperandInfo OperandInfo115[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9377 : static const MCOperandInfo OperandInfo116[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9378 : static const MCOperandInfo OperandInfo117[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9379 : static const MCOperandInfo OperandInfo118[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9380 : static const MCOperandInfo OperandInfo119[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9381 : static const MCOperandInfo OperandInfo120[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9382 : static const MCOperandInfo OperandInfo121[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9383 : static const MCOperandInfo OperandInfo122[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9384 : static const MCOperandInfo OperandInfo123[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9385 : static const MCOperandInfo OperandInfo124[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9386 : static const MCOperandInfo OperandInfo125[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9387 : static const MCOperandInfo OperandInfo126[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9388 : static const MCOperandInfo OperandInfo127[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9389 : static const MCOperandInfo OperandInfo128[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9390 : static const MCOperandInfo OperandInfo129[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9391 : static const MCOperandInfo OperandInfo130[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9392 : static const MCOperandInfo OperandInfo131[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9393 : static const MCOperandInfo OperandInfo132[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9394 : static const MCOperandInfo OperandInfo133[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9395 : static const MCOperandInfo OperandInfo134[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9396 : static const MCOperandInfo OperandInfo135[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XEXEC_HIRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9397 : static const MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
9398 : static const MCOperandInfo OperandInfo137[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9399 : static const MCOperandInfo OperandInfo138[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9400 : static const MCOperandInfo OperandInfo139[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9401 : static const MCOperandInfo OperandInfo140[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9402 : static const MCOperandInfo OperandInfo141[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9403 : static const MCOperandInfo OperandInfo142[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9404 : static const MCOperandInfo OperandInfo143[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9405 : static const MCOperandInfo OperandInfo144[] = { { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9406 : static const MCOperandInfo OperandInfo145[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9407 : static const MCOperandInfo OperandInfo146[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9408 : static const MCOperandInfo OperandInfo147[] = { { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9409 : static const MCOperandInfo OperandInfo148[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9410 : static const MCOperandInfo OperandInfo149[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9411 : static const MCOperandInfo OperandInfo150[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9412 : static const MCOperandInfo OperandInfo151[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9413 : static const MCOperandInfo OperandInfo152[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9414 : static const MCOperandInfo OperandInfo153[] = { { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9415 : static const MCOperandInfo OperandInfo154[] = { { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9416 : static const MCOperandInfo OperandInfo155[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9417 : static const MCOperandInfo OperandInfo156[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9418 : static const MCOperandInfo OperandInfo157[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9419 : static const MCOperandInfo OperandInfo158[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9420 : static const MCOperandInfo OperandInfo159[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9421 : static const MCOperandInfo OperandInfo160[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9422 : static const MCOperandInfo OperandInfo161[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9423 : static const MCOperandInfo OperandInfo162[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9424 : static const MCOperandInfo OperandInfo163[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9425 : static const MCOperandInfo OperandInfo164[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9426 : static const MCOperandInfo OperandInfo165[] = { { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9427 : static const MCOperandInfo OperandInfo166[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9428 : static const MCOperandInfo OperandInfo167[] = { { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9429 : static const MCOperandInfo OperandInfo168[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9430 : static const MCOperandInfo OperandInfo169[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9431 : static const MCOperandInfo OperandInfo170[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9432 : static const MCOperandInfo OperandInfo171[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9433 : static const MCOperandInfo OperandInfo172[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9434 : static const MCOperandInfo OperandInfo173[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9435 : static const MCOperandInfo OperandInfo174[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9436 : static const MCOperandInfo OperandInfo175[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9437 : static const MCOperandInfo OperandInfo176[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9438 : static const MCOperandInfo OperandInfo177[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9439 : static const MCOperandInfo OperandInfo178[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9440 : static const MCOperandInfo OperandInfo179[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9441 : static const MCOperandInfo OperandInfo180[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9442 : static const MCOperandInfo OperandInfo181[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9443 : static const MCOperandInfo OperandInfo182[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9444 : static const MCOperandInfo OperandInfo183[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9445 : static const MCOperandInfo OperandInfo184[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9446 : static const MCOperandInfo OperandInfo185[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9447 : static const MCOperandInfo OperandInfo186[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9448 : static const MCOperandInfo OperandInfo187[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9449 : static const MCOperandInfo OperandInfo188[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9450 : static const MCOperandInfo OperandInfo189[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9451 : static const MCOperandInfo OperandInfo190[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9452 : static const MCOperandInfo OperandInfo191[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9453 : static const MCOperandInfo OperandInfo192[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9454 : static const MCOperandInfo OperandInfo193[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9455 : static const MCOperandInfo OperandInfo194[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9456 : static const MCOperandInfo OperandInfo195[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9457 : static const MCOperandInfo OperandInfo196[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9458 : static const MCOperandInfo OperandInfo197[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9459 : static const MCOperandInfo OperandInfo198[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9460 : static const MCOperandInfo OperandInfo199[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9461 : static const MCOperandInfo OperandInfo200[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9462 : static const MCOperandInfo OperandInfo201[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9463 : static const MCOperandInfo OperandInfo202[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9464 : static const MCOperandInfo OperandInfo203[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9465 : static const MCOperandInfo OperandInfo204[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9466 : static const MCOperandInfo OperandInfo205[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9467 : static const MCOperandInfo OperandInfo206[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9468 : static const MCOperandInfo OperandInfo207[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9469 : static const MCOperandInfo OperandInfo208[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9470 : static const MCOperandInfo OperandInfo209[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9471 : static const MCOperandInfo OperandInfo210[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9472 : static const MCOperandInfo OperandInfo211[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9473 : static const MCOperandInfo OperandInfo212[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9474 : static const MCOperandInfo OperandInfo213[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9475 : static const MCOperandInfo OperandInfo214[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9476 : static const MCOperandInfo OperandInfo215[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9477 : static const MCOperandInfo OperandInfo216[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9478 : static const MCOperandInfo OperandInfo217[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9479 : static const MCOperandInfo OperandInfo218[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9480 : static const MCOperandInfo OperandInfo219[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
9481 : static const MCOperandInfo OperandInfo220[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9482 : static const MCOperandInfo OperandInfo221[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9483 : static const MCOperandInfo OperandInfo222[] = { { AMDGPU::SReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9484 : static const MCOperandInfo OperandInfo223[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9485 : static const MCOperandInfo OperandInfo224[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9486 : static const MCOperandInfo OperandInfo225[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9487 : static const MCOperandInfo OperandInfo226[] = { { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9488 : static const MCOperandInfo OperandInfo227[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9489 : static const MCOperandInfo OperandInfo228[] = { { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9490 : static const MCOperandInfo OperandInfo229[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9491 : static const MCOperandInfo OperandInfo230[] = { { AMDGPU::SReg_32_XM0_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9492 : static const MCOperandInfo OperandInfo231[] = { { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9493 : static const MCOperandInfo OperandInfo232[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9494 : static const MCOperandInfo OperandInfo233[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9495 : static const MCOperandInfo OperandInfo234[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9496 : static const MCOperandInfo OperandInfo235[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9497 : static const MCOperandInfo OperandInfo236[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9498 : static const MCOperandInfo OperandInfo237[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9499 : static const MCOperandInfo OperandInfo238[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9500 : static const MCOperandInfo OperandInfo239[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9501 : static const MCOperandInfo OperandInfo240[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9502 : static const MCOperandInfo OperandInfo241[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9503 : static const MCOperandInfo OperandInfo242[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9504 : static const MCOperandInfo OperandInfo243[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9505 : static const MCOperandInfo OperandInfo244[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9506 : static const MCOperandInfo OperandInfo245[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9507 : static const MCOperandInfo OperandInfo246[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9508 : static const MCOperandInfo OperandInfo247[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9509 : static const MCOperandInfo OperandInfo248[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9510 : static const MCOperandInfo OperandInfo249[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9511 : static const MCOperandInfo OperandInfo250[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9512 : static const MCOperandInfo OperandInfo251[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9513 : static const MCOperandInfo OperandInfo252[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9514 : static const MCOperandInfo OperandInfo253[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9515 : static const MCOperandInfo OperandInfo254[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9516 : static const MCOperandInfo OperandInfo255[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9517 : static const MCOperandInfo OperandInfo256[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9518 : static const MCOperandInfo OperandInfo257[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9519 : static const MCOperandInfo OperandInfo258[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9520 : static const MCOperandInfo OperandInfo259[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9521 : static const MCOperandInfo OperandInfo260[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9522 : static const MCOperandInfo OperandInfo261[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, };
9523 : static const MCOperandInfo OperandInfo262[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9524 : static const MCOperandInfo OperandInfo263[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
9525 : static const MCOperandInfo OperandInfo264[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9526 : static const MCOperandInfo OperandInfo265[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9527 : static const MCOperandInfo OperandInfo266[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9528 : static const MCOperandInfo OperandInfo267[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9529 : static const MCOperandInfo OperandInfo268[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, };
9530 : static const MCOperandInfo OperandInfo269[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9531 : static const MCOperandInfo OperandInfo270[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9532 : static const MCOperandInfo OperandInfo271[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, };
9533 : static const MCOperandInfo OperandInfo272[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9534 : static const MCOperandInfo OperandInfo273[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9535 : static const MCOperandInfo OperandInfo274[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
9536 : static const MCOperandInfo OperandInfo275[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9537 : static const MCOperandInfo OperandInfo276[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9538 : static const MCOperandInfo OperandInfo277[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9539 : static const MCOperandInfo OperandInfo278[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9540 : static const MCOperandInfo OperandInfo279[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9541 : static const MCOperandInfo OperandInfo280[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9542 : static const MCOperandInfo OperandInfo281[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9543 : static const MCOperandInfo OperandInfo282[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9544 : static const MCOperandInfo OperandInfo283[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9545 : static const MCOperandInfo OperandInfo284[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9546 : static const MCOperandInfo OperandInfo285[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9547 : static const MCOperandInfo OperandInfo286[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9548 : static const MCOperandInfo OperandInfo287[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9549 : static const MCOperandInfo OperandInfo288[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9550 : static const MCOperandInfo OperandInfo289[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9551 : static const MCOperandInfo OperandInfo290[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9552 : static const MCOperandInfo OperandInfo291[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, };
9553 : static const MCOperandInfo OperandInfo292[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_SDWA_VOPC_DST, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9554 : static const MCOperandInfo OperandInfo293[] = { { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9555 : static const MCOperandInfo OperandInfo294[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9556 : static const MCOperandInfo OperandInfo295[] = { { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9557 : static const MCOperandInfo OperandInfo296[] = { { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, };
9558 : static const MCOperandInfo OperandInfo297[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::SReg_64_XEXECRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9559 : static const MCOperandInfo OperandInfo298[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9560 : static const MCOperandInfo OperandInfo299[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9561 : static const MCOperandInfo OperandInfo300[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT16, 0 }, };
9562 : static const MCOperandInfo OperandInfo301[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9563 : static const MCOperandInfo OperandInfo302[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9564 : static const MCOperandInfo OperandInfo303[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP64, 0 }, };
9565 : static const MCOperandInfo OperandInfo304[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9566 : static const MCOperandInfo OperandInfo305[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9567 : static const MCOperandInfo OperandInfo306[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, };
9568 : static const MCOperandInfo OperandInfo307[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9569 : static const MCOperandInfo OperandInfo308[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9570 : static const MCOperandInfo OperandInfo309[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9571 : static const MCOperandInfo OperandInfo310[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9572 : static const MCOperandInfo OperandInfo311[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9573 : static const MCOperandInfo OperandInfo312[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9574 : static const MCOperandInfo OperandInfo313[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9575 : static const MCOperandInfo OperandInfo314[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9576 : static const MCOperandInfo OperandInfo315[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9577 : static const MCOperandInfo OperandInfo316[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9578 : static const MCOperandInfo OperandInfo317[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9579 : static const MCOperandInfo OperandInfo318[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, };
9580 : static const MCOperandInfo OperandInfo319[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, };
9581 : static const MCOperandInfo OperandInfo320[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9582 : static const MCOperandInfo OperandInfo321[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9583 : static const MCOperandInfo OperandInfo322[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9584 : static const MCOperandInfo OperandInfo323[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9585 : static const MCOperandInfo OperandInfo324[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9586 : static const MCOperandInfo OperandInfo325[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9587 : static const MCOperandInfo OperandInfo326[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9588 : static const MCOperandInfo OperandInfo327[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9589 : static const MCOperandInfo OperandInfo328[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9590 : static const MCOperandInfo OperandInfo329[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9591 : static const MCOperandInfo OperandInfo330[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9592 : static const MCOperandInfo OperandInfo331[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9593 : static const MCOperandInfo OperandInfo332[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9594 : static const MCOperandInfo OperandInfo333[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9595 : static const MCOperandInfo OperandInfo334[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9596 : static const MCOperandInfo OperandInfo335[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9597 : static const MCOperandInfo OperandInfo336[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9598 : static const MCOperandInfo OperandInfo337[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9599 : static const MCOperandInfo OperandInfo338[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP64, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9600 : static const MCOperandInfo OperandInfo339[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_FP16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9601 : static const MCOperandInfo OperandInfo340[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9602 : static const MCOperandInfo OperandInfo341[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9603 : static const MCOperandInfo OperandInfo342[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM16, 0 }, };
9604 : static const MCOperandInfo OperandInfo343[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM32, 0 }, };
9605 : static const MCOperandInfo OperandInfo344[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM16, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9606 : static const MCOperandInfo OperandInfo345[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_FP32, 0 }, { -1, 0, AMDGPU::OPERAND_KIMM32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9607 : static const MCOperandInfo OperandInfo346[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9608 : static const MCOperandInfo OperandInfo347[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9609 : static const MCOperandInfo OperandInfo348[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9610 : static const MCOperandInfo OperandInfo349[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9611 : static const MCOperandInfo OperandInfo350[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9612 : static const MCOperandInfo OperandInfo351[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9613 : static const MCOperandInfo OperandInfo352[] = { { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9614 : static const MCOperandInfo OperandInfo353[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9615 : static const MCOperandInfo OperandInfo354[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9616 : static const MCOperandInfo OperandInfo355[] = { { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9617 : static const MCOperandInfo OperandInfo356[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9618 : static const MCOperandInfo OperandInfo357[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9619 : static const MCOperandInfo OperandInfo358[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9620 : static const MCOperandInfo OperandInfo359[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT64, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9621 : static const MCOperandInfo OperandInfo360[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9622 : static const MCOperandInfo OperandInfo361[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9623 : static const MCOperandInfo OperandInfo362[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2FP16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9624 : static const MCOperandInfo OperandInfo363[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_V2INT16, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9625 : static const MCOperandInfo OperandInfo364[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, };
9626 : static const MCOperandInfo OperandInfo365[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9627 : static const MCOperandInfo OperandInfo366[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VS_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9628 : static const MCOperandInfo OperandInfo367[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9629 : static const MCOperandInfo OperandInfo368[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9630 : static const MCOperandInfo OperandInfo369[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, (1 << MCOI::EARLY_CLOBBER) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
9631 : static const MCOperandInfo OperandInfo370[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9632 : static const MCOperandInfo OperandInfo371[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9633 : static const MCOperandInfo OperandInfo372[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9634 : static const MCOperandInfo OperandInfo373[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9635 : static const MCOperandInfo OperandInfo374[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9636 : static const MCOperandInfo OperandInfo375[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9637 : static const MCOperandInfo OperandInfo376[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9638 : static const MCOperandInfo OperandInfo377[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9639 : static const MCOperandInfo OperandInfo378[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9640 : static const MCOperandInfo OperandInfo379[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9641 : static const MCOperandInfo OperandInfo380[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9642 : static const MCOperandInfo OperandInfo381[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9643 : static const MCOperandInfo OperandInfo382[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9644 : static const MCOperandInfo OperandInfo383[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9645 : static const MCOperandInfo OperandInfo384[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9646 : static const MCOperandInfo OperandInfo385[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9647 : static const MCOperandInfo OperandInfo386[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9648 : static const MCOperandInfo OperandInfo387[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9649 : static const MCOperandInfo OperandInfo388[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9650 : static const MCOperandInfo OperandInfo389[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9651 : static const MCOperandInfo OperandInfo390[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9652 : static const MCOperandInfo OperandInfo391[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9653 : static const MCOperandInfo OperandInfo392[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9654 : static const MCOperandInfo OperandInfo393[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9655 : static const MCOperandInfo OperandInfo394[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9656 : static const MCOperandInfo OperandInfo395[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9657 : static const MCOperandInfo OperandInfo396[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9658 : static const MCOperandInfo OperandInfo397[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9659 : static const MCOperandInfo OperandInfo398[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9660 : static const MCOperandInfo OperandInfo399[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9661 : static const MCOperandInfo OperandInfo400[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9662 : static const MCOperandInfo OperandInfo401[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9663 : static const MCOperandInfo OperandInfo402[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9664 : static const MCOperandInfo OperandInfo403[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9665 : static const MCOperandInfo OperandInfo404[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9666 : static const MCOperandInfo OperandInfo405[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9667 : static const MCOperandInfo OperandInfo406[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9668 : static const MCOperandInfo OperandInfo407[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9669 : static const MCOperandInfo OperandInfo408[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9670 : static const MCOperandInfo OperandInfo409[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9671 : static const MCOperandInfo OperandInfo410[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9672 : static const MCOperandInfo OperandInfo411[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9673 : static const MCOperandInfo OperandInfo412[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9674 : static const MCOperandInfo OperandInfo413[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9675 : static const MCOperandInfo OperandInfo414[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9676 : static const MCOperandInfo OperandInfo415[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9677 : static const MCOperandInfo OperandInfo416[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9678 : static const MCOperandInfo OperandInfo417[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9679 : static const MCOperandInfo OperandInfo418[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9680 : static const MCOperandInfo OperandInfo419[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9681 : static const MCOperandInfo OperandInfo420[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9682 : static const MCOperandInfo OperandInfo421[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9683 : static const MCOperandInfo OperandInfo422[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9684 : static const MCOperandInfo OperandInfo423[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9685 : static const MCOperandInfo OperandInfo424[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9686 : static const MCOperandInfo OperandInfo425[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9687 : static const MCOperandInfo OperandInfo426[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9688 : static const MCOperandInfo OperandInfo427[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9689 : static const MCOperandInfo OperandInfo428[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9690 : static const MCOperandInfo OperandInfo429[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9691 : static const MCOperandInfo OperandInfo430[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9692 : static const MCOperandInfo OperandInfo431[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9693 : static const MCOperandInfo OperandInfo432[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9694 : static const MCOperandInfo OperandInfo433[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9695 : static const MCOperandInfo OperandInfo434[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9696 : static const MCOperandInfo OperandInfo435[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9697 : static const MCOperandInfo OperandInfo436[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9698 : static const MCOperandInfo OperandInfo437[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9699 : static const MCOperandInfo OperandInfo438[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9700 : static const MCOperandInfo OperandInfo439[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9701 : static const MCOperandInfo OperandInfo440[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9702 : static const MCOperandInfo OperandInfo441[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9703 : static const MCOperandInfo OperandInfo442[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9704 : static const MCOperandInfo OperandInfo443[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9705 : static const MCOperandInfo OperandInfo444[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9706 : static const MCOperandInfo OperandInfo445[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9707 : static const MCOperandInfo OperandInfo446[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9708 : static const MCOperandInfo OperandInfo447[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9709 : static const MCOperandInfo OperandInfo448[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9710 : static const MCOperandInfo OperandInfo449[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9711 : static const MCOperandInfo OperandInfo450[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9712 : static const MCOperandInfo OperandInfo451[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9713 : static const MCOperandInfo OperandInfo452[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9714 : static const MCOperandInfo OperandInfo453[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9715 : static const MCOperandInfo OperandInfo454[] = { { AMDGPU::VReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_512RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9716 : static const MCOperandInfo OperandInfo455[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9717 : static const MCOperandInfo OperandInfo456[] = { { AMDGPU::VReg_96RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9718 : static const MCOperandInfo OperandInfo457[] = { { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, };
9719 : static const MCOperandInfo OperandInfo458[] = { { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, { AMDGPU::SReg_64RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT64, 0 }, };
9720 : static const MCOperandInfo OperandInfo459[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9721 : static const MCOperandInfo OperandInfo460[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9722 : static const MCOperandInfo OperandInfo461[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9723 : static const MCOperandInfo OperandInfo462[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9724 : static const MCOperandInfo OperandInfo463[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9725 : static const MCOperandInfo OperandInfo464[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9726 : static const MCOperandInfo OperandInfo465[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9727 : static const MCOperandInfo OperandInfo466[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, AMDGPU::OPERAND_INPUT_MODS, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9728 : static const MCOperandInfo OperandInfo467[] = { { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VReg_64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
9729 : static const MCOperandInfo OperandInfo468[] = { { AMDGPU::SReg_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
9730 : static const MCOperandInfo OperandInfo469[] = { { AMDGPU::VGPR_32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, 0 }, { AMDGPU::SReg_32RegClassID, 0, AMDGPU::OPERAND_REG_INLINE_C_INT32, 0 }, { AMDGPU::VS_32RegClassID, 0, AMDGPU::OPERAND_REG_IMM_INT32, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
9731 :
9732 : extern const MCInstrDesc AMDGPUInsts[] = {
9733 : { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
9734 : { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
9735 : { 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2 = CFI_INSTRUCTION
9736 : { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = EH_LABEL
9737 : { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = GC_LABEL
9738 : { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = ANNOTATION_LABEL
9739 : { 6, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #6 = KILL
9740 : { 7, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #7 = EXTRACT_SUBREG
9741 : { 8, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #8 = INSERT_SUBREG
9742 : { 9, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #9 = IMPLICIT_DEF
9743 : { 10, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #10 = SUBREG_TO_REG
9744 : { 11, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #11 = COPY_TO_REGCLASS
9745 : { 12, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #12 = DBG_VALUE
9746 : { 13, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #13 = DBG_LABEL
9747 : { 14, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #14 = REG_SEQUENCE
9748 : { 15, 2, 1, 0, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = COPY
9749 : { 16, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #16 = BUNDLE
9750 : { 17, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #17 = LIFETIME_START
9751 : { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_END
9752 : { 19, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #19 = STACKMAP
9753 : { 20, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #20 = FENTRY_CALL
9754 : { 21, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #21 = PATCHPOINT
9755 : { 22, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #22 = LOAD_STACK_GUARD
9756 : { 23, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #23 = STATEPOINT
9757 : { 24, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #24 = LOCAL_ESCAPE
9758 : { 25, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #25 = FAULTING_OP
9759 : { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1UL |
