LCOV - code coverage report
Current view: top level - build-llvm/lib/Target/AMDGPU - R600GenCallingConv.inc (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 6 6 100.0 %
Date: 2018-10-20 13:21:21 Functions: 1 1 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
       2             : |*                                                                            *|
       3             : |* Calling Convention Implementation Fragment                                 *|
       4             : |*                                                                            *|
       5             : |* Automatically generated file, do not edit!                                 *|
       6             : |*                                                                            *|
       7             : \*===----------------------------------------------------------------------===*/
       8             : 
       9             : static bool CC_R600(unsigned ValNo, MVT ValVT,
      10             :                     MVT LocVT, CCValAssign::LocInfo LocInfo,
      11             :                     ISD::ArgFlagsTy ArgFlags, CCState &State);
      12             : 
      13             : 
      14          65 : static bool CC_R600(unsigned ValNo, MVT ValVT,
      15             :                     MVT LocVT, CCValAssign::LocInfo LocInfo,
      16             :                     ISD::ArgFlagsTy ArgFlags, CCState &State) {
      17             : 
      18          65 :   if (ArgFlags.isInReg()) {
      19          65 :     if (LocVT == MVT::v4f32 ||
      20             :         LocVT == MVT::v4i32) {
      21             :       static const MCPhysReg RegList1[] = {
      22             :         R600::T0_XYZW, R600::T1_XYZW, R600::T2_XYZW, R600::T3_XYZW, R600::T4_XYZW, R600::T5_XYZW, R600::T6_XYZW, R600::T7_XYZW, R600::T8_XYZW, R600::T9_XYZW, R600::T10_XYZW, R600::T11_XYZW, R600::T12_XYZW, R600::T13_XYZW, R600::T14_XYZW, R600::T15_XYZW, R600::T16_XYZW, R600::T17_XYZW, R600::T18_XYZW, R600::T19_XYZW, R600::T20_XYZW, R600::T21_XYZW, R600::T22_XYZW, R600::T23_XYZW, R600::T24_XYZW, R600::T25_XYZW, R600::T26_XYZW, R600::T27_XYZW, R600::T28_XYZW, R600::T29_XYZW, R600::T30_XYZW, R600::T31_XYZW, R600::T32_XYZW
      23             :       };
      24          65 :       if (unsigned Reg = State.AllocateReg(RegList1)) {
      25          65 :         State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      26          65 :         return false;
      27             :       }
      28             :     }
      29             :   }
      30             : 
      31             :   return true;  // CC didn't match.
      32             : }

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