Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Subtarget Enumeration Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_SUBTARGETINFO_ENUM
11 : #undef GET_SUBTARGETINFO_ENUM
12 :
13 : namespace llvm {
14 : namespace R600 {
15 : enum {
16 : FeatureCFALUBug = 0,
17 : FeatureCaymanISA = 1,
18 : FeatureDX10Clamp = 2,
19 : FeatureEvergreen = 3,
20 : FeatureFMA = 4,
21 : FeatureFP32Denormals = 5,
22 : FeatureFP64 = 6,
23 : FeatureFetchLimit8 = 7,
24 : FeatureFetchLimit16 = 8,
25 : FeatureLocalMemorySize0 = 9,
26 : FeatureLocalMemorySize32768 = 10,
27 : FeatureLocalMemorySize65536 = 11,
28 : FeatureNorthernIslands = 12,
29 : FeaturePromoteAlloca = 13,
30 : FeatureR600 = 14,
31 : FeatureR600ALUInst = 15,
32 : FeatureR700 = 16,
33 : FeatureVertexCache = 17,
34 : FeatureWavefrontSize16 = 18,
35 : FeatureWavefrontSize32 = 19,
36 : FeatureWavefrontSize64 = 20,
37 : };
38 : } // end namespace R600
39 : } // end namespace llvm
40 :
41 : #endif // GET_SUBTARGETINFO_ENUM
42 :
43 :
44 : #ifdef GET_SUBTARGETINFO_MC_DESC
45 : #undef GET_SUBTARGETINFO_MC_DESC
46 :
47 : namespace llvm {
48 : // Sorted (by key) array of values for CPU features.
49 : extern const llvm::SubtargetFeatureKV R600FeatureKV[] = {
50 : { "EVERGREEN", "EVERGREEN GPU generation", { R600::FeatureEvergreen }, { R600::FeatureFetchLimit16, R600::FeatureLocalMemorySize32768 } },
51 : { "HasVertexCache", "Specify use of dedicated vertex cache", { R600::FeatureVertexCache }, { } },
52 : { "NORTHERN_ISLANDS", "NORTHERN_ISLANDS GPU generation", { R600::FeatureNorthernIslands }, { R600::FeatureFetchLimit16, R600::FeatureWavefrontSize64, R600::FeatureLocalMemorySize32768 } },
53 : { "R600", "R600 GPU generation", { R600::FeatureR600 }, { R600::FeatureR600ALUInst, R600::FeatureFetchLimit8, R600::FeatureLocalMemorySize0 } },
54 : { "R600ALUInst", "Older version of ALU instructions encoding", { R600::FeatureR600ALUInst }, { } },
55 : { "R700", "R700 GPU generation", { R600::FeatureR700 }, { R600::FeatureFetchLimit16, R600::FeatureLocalMemorySize0 } },
56 : { "caymanISA", "Use Cayman ISA", { R600::FeatureCaymanISA }, { } },
57 : { "cfalubug", "GPU has CF_ALU bug", { R600::FeatureCFALUBug }, { } },
58 : { "dx10-clamp", "clamp modifier clamps NaNs to 0.0", { R600::FeatureDX10Clamp }, { } },
59 : { "fetch16", "Limit the maximum number of fetches in a clause to 16", { R600::FeatureFetchLimit16 }, { } },
60 : { "fetch8", "Limit the maximum number of fetches in a clause to 8", { R600::FeatureFetchLimit8 }, { } },
61 : { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", { R600::FeatureFMA }, { } },
62 : { "fp32-denormals", "Enable single precision denormal handling", { R600::FeatureFP32Denormals }, { } },
63 : { "fp64", "Enable double precision operations", { R600::FeatureFP64 }, { } },
64 : { "localmemorysize0", "The size of local memory in bytes", { R600::FeatureLocalMemorySize0 }, { } },
65 : { "localmemorysize32768", "The size of local memory in bytes", { R600::FeatureLocalMemorySize32768 }, { } },
66 : { "localmemorysize65536", "The size of local memory in bytes", { R600::FeatureLocalMemorySize65536 }, { } },
67 : { "promote-alloca", "Enable promote alloca pass", { R600::FeaturePromoteAlloca }, { } },
68 : { "wavefrontsize16", "The number of threads per wavefront", { R600::FeatureWavefrontSize16 }, { } },
69 : { "wavefrontsize32", "The number of threads per wavefront", { R600::FeatureWavefrontSize32 }, { } },
70 : { "wavefrontsize64", "The number of threads per wavefront", { R600::FeatureWavefrontSize64 }, { } },
71 : };
72 :
73 : // Sorted (by key) array of values for CPU subtype.
74 : extern const llvm::SubtargetFeatureKV R600SubTypeKV[] = {
75 : { "barts", "Select the barts processor", { R600::FeatureNorthernIslands, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
76 : { "caicos", "Select the caicos processor", { R600::FeatureNorthernIslands, R600::FeatureCFALUBug }, { } },
77 : { "cayman", "Select the cayman processor", { R600::FeatureNorthernIslands, R600::FeatureCaymanISA, R600::FeatureFMA }, { } },
78 : { "cedar", "Select the cedar processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize32, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
79 : { "cypress", "Select the cypress processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureVertexCache, R600::FeatureFMA }, { } },
80 : { "juniper", "Select the juniper processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
81 : { "r600", "Select the r600 processor", { R600::FeatureR600, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
82 : { "r630", "Select the r630 processor", { R600::FeatureR600, R600::FeatureWavefrontSize32, R600::FeatureVertexCache }, { } },
83 : { "redwood", "Select the redwood processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
84 : { "rs880", "Select the rs880 processor", { R600::FeatureR600, R600::FeatureWavefrontSize16 }, { } },
85 : { "rv670", "Select the rv670 processor", { R600::FeatureR600, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
86 : { "rv710", "Select the rv710 processor", { R600::FeatureR700, R600::FeatureWavefrontSize32, R600::FeatureVertexCache }, { } },
87 : { "rv730", "Select the rv730 processor", { R600::FeatureR700, R600::FeatureWavefrontSize32, R600::FeatureVertexCache }, { } },
88 : { "rv770", "Select the rv770 processor", { R600::FeatureR700, R600::FeatureWavefrontSize64, R600::FeatureVertexCache }, { } },
89 : { "sumo", "Select the sumo processor", { R600::FeatureEvergreen, R600::FeatureWavefrontSize64, R600::FeatureCFALUBug }, { } },
90 : { "turks", "Select the turks processor", { R600::FeatureNorthernIslands, R600::FeatureVertexCache, R600::FeatureCFALUBug }, { } },
91 : };
92 :
93 : #ifdef DBGFIELD
94 : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
95 : #endif
96 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
97 : #define DBGFIELD(x) x,
98 : #else
99 : #define DBGFIELD(x)
100 : #endif
101 :
102 : // Functional units for "R600_VLIW5_Itin"
103 : namespace R600_VLIW5_ItinFU {
104 : const unsigned ALU_X = 1 << 0;
105 : const unsigned ALU_Y = 1 << 1;
106 : const unsigned ALU_Z = 1 << 2;
107 : const unsigned ALU_W = 1 << 3;
108 : const unsigned TRANS = 1 << 4;
109 : const unsigned ALU_NULL = 1 << 5;
110 : } // end namespace R600_VLIW5_ItinFU
111 :
112 : // Functional units for "R600_VLIW4_Itin"
113 : namespace R600_VLIW4_ItinFU {
114 : const unsigned ALU_X = 1 << 0;
115 : const unsigned ALU_Y = 1 << 1;
116 : const unsigned ALU_Z = 1 << 2;
117 : const unsigned ALU_W = 1 << 3;
118 : const unsigned ALU_NULL = 1 << 4;
119 : } // end namespace R600_VLIW4_ItinFU
120 :
121 : extern const llvm::InstrStage R600Stages[] = {
122 : { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
123 : { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
124 : { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
125 : { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
126 : { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
127 : { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
128 : { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
129 : { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
130 : { 0, 0, 0, llvm::InstrStage::Required } // End stages
131 : };
132 : extern const unsigned R600OperandCycles[] = {
133 : 0, // No itinerary
134 : 0 // End operand cycles
135 : };
136 : extern const unsigned R600ForwardingPaths[] = {
137 : 0, // No itinerary
138 : 0 // End bypass tables
139 : };
140 :
141 : static const llvm::InstrItinerary R600_VLIW5_Itin[] = {
142 : { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
143 : { 1, 1, 2, 0, 0 }, // 1 NullALU
144 : { 1, 2, 3, 0, 0 }, // 2 VecALU
145 : { 1, 3, 4, 0, 0 }, // 3 AnyALU
146 : { 1, 4, 5, 0, 0 }, // 4 TransALU
147 : { 1, 5, 6, 0, 0 }, // 5 XALU
148 : { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
149 : };
150 :
151 : static const llvm::InstrItinerary R600_VLIW4_Itin[] = {
152 : { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
153 : { 1, 6, 7, 0, 0 }, // 1 NullALU
154 : { 1, 7, 8, 0, 0 }, // 2 VecALU
155 : { 1, 7, 8, 0, 0 }, // 3 AnyALU
156 : { 1, 6, 7, 0, 0 }, // 4 TransALU
157 : { 0, 0, 0, 0, 0 }, // 5 XALU
158 : { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
159 : };
160 :
161 : // ===============================================================
162 : // Data tables for the new per-operand machine model.
163 :
164 : // {ProcResourceIdx, Cycles}
165 : extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
166 : { 0, 0}, // Invalid
167 : }; // R600WriteProcResTable
168 :
169 : // {Cycles, WriteResourceID}
170 : extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
171 : { 0, 0}, // Invalid
172 : }; // R600WriteLatencyTable
173 :
174 : // {UseIdx, WriteResourceID, Cycles}
175 : extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
176 : {0, 0, 0}, // Invalid
177 : }; // R600ReadAdvanceTable
178 :
179 : static const llvm::MCSchedModel NoSchedModel = {
180 : MCSchedModel::DefaultIssueWidth,
181 : MCSchedModel::DefaultMicroOpBufferSize,
182 : MCSchedModel::DefaultLoopMicroOpBufferSize,
183 : MCSchedModel::DefaultLoadLatency,
184 : MCSchedModel::DefaultHighLatency,
185 : MCSchedModel::DefaultMispredictPenalty,
186 : false, // PostRAScheduler
187 : false, // CompleteModel
188 : 0, // Processor ID
189 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
190 : nullptr, // No Itinerary
191 : nullptr // No extra processor descriptor
192 : };
193 :
194 : static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
195 : MCSchedModel::DefaultIssueWidth,
196 : MCSchedModel::DefaultMicroOpBufferSize,
197 : MCSchedModel::DefaultLoopMicroOpBufferSize,
198 : MCSchedModel::DefaultLoadLatency,
199 : MCSchedModel::DefaultHighLatency,
200 : MCSchedModel::DefaultMispredictPenalty,
201 : false, // PostRAScheduler
202 : false, // CompleteModel
203 : 1, // Processor ID
204 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
205 : R600_VLIW5_Itin,
206 : nullptr // No extra processor descriptor
207 : };
208 :
209 : static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
210 : MCSchedModel::DefaultIssueWidth,
211 : MCSchedModel::DefaultMicroOpBufferSize,
212 : MCSchedModel::DefaultLoopMicroOpBufferSize,
213 : MCSchedModel::DefaultLoadLatency,
214 : MCSchedModel::DefaultHighLatency,
215 : MCSchedModel::DefaultMispredictPenalty,
216 : false, // PostRAScheduler
217 : false, // CompleteModel
218 : 2, // Processor ID
219 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
220 : R600_VLIW4_Itin,
221 : nullptr // No extra processor descriptor
222 : };
223 :
224 : // Sorted (by key) array of itineraries for CPU subtype.
225 : extern const llvm::SubtargetInfoKV R600ProcSchedKV[] = {
226 : { "barts", (const void *)&R600_VLIW5_ItinModel },
227 : { "caicos", (const void *)&R600_VLIW5_ItinModel },
228 : { "cayman", (const void *)&R600_VLIW4_ItinModel },
229 : { "cedar", (const void *)&R600_VLIW5_ItinModel },
230 : { "cypress", (const void *)&R600_VLIW5_ItinModel },
231 : { "juniper", (const void *)&R600_VLIW5_ItinModel },
232 : { "r600", (const void *)&R600_VLIW5_ItinModel },
233 : { "r630", (const void *)&R600_VLIW5_ItinModel },
234 : { "redwood", (const void *)&R600_VLIW5_ItinModel },
235 : { "rs880", (const void *)&R600_VLIW5_ItinModel },
236 : { "rv670", (const void *)&R600_VLIW5_ItinModel },
237 : { "rv710", (const void *)&R600_VLIW5_ItinModel },
238 : { "rv730", (const void *)&R600_VLIW5_ItinModel },
239 : { "rv770", (const void *)&R600_VLIW5_ItinModel },
240 : { "sumo", (const void *)&R600_VLIW5_ItinModel },
241 : { "turks", (const void *)&R600_VLIW5_ItinModel },
242 : };
243 :
244 : #undef DBGFIELD
245 : namespace R600_MC {
246 0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
247 : const MCInst *MI, unsigned CPUID) {
248 : // Don't know how to resolve this scheduling class.
249 0 : return 0;
250 : }
251 : } // end of namespace R600_MC
252 :
253 : struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
254 : R600GenMCSubtargetInfo(const Triple &TT,
255 : StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
256 : ArrayRef<SubtargetFeatureKV> PD,
257 : const SubtargetInfoKV *ProcSched,
258 : const MCWriteProcResEntry *WPR,
259 : const MCWriteLatencyEntry *WL,
260 : const MCReadAdvanceEntry *RA, const InstrStage *IS,
261 296 : const unsigned *OC, const unsigned *FP) :
262 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
263 296 : WPR, WL, RA, IS, OC, FP) { }
264 :
265 0 : unsigned resolveVariantSchedClass(unsigned SchedClass,
266 : const MCInst *MI, unsigned CPUID) const override {
267 0 : return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
268 : }
269 : };
270 :
271 296 : static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
272 : return new R600GenMCSubtargetInfo(TT, CPU, FS, R600FeatureKV, R600SubTypeKV,
273 : R600ProcSchedKV, R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
274 296 : R600Stages, R600OperandCycles, R600ForwardingPaths);
275 : }
276 :
277 : } // end namespace llvm
278 :
279 : #endif // GET_SUBTARGETINFO_MC_DESC
280 :
281 :
282 : #ifdef GET_SUBTARGETINFO_TARGET_DESC
283 : #undef GET_SUBTARGETINFO_TARGET_DESC
284 :
285 : #include "llvm/Support/Debug.h"
286 : #include "llvm/Support/raw_ostream.h"
287 :
288 : // ParseSubtargetFeatures - Parses features string setting specified
289 : // subtarget options.
290 291 : void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
291 : LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
292 : LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
293 291 : InitMCProcessorInfo(CPU, FS);
294 : const FeatureBitset& Bits = getFeatureBits();
295 291 : if (Bits[R600::FeatureCFALUBug]) CFALUBug = true;
296 291 : if (Bits[R600::FeatureCaymanISA]) CaymanISA = true;
297 291 : if (Bits[R600::FeatureDX10Clamp]) DX10Clamp = true;
298 291 : if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
299 291 : if (Bits[R600::FeatureFMA]) FMA = true;
300 291 : if (Bits[R600::FeatureFP32Denormals]) FP32Denormals = true;
301 291 : if (Bits[R600::FeatureFP64]) FP64 = true;
302 291 : if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
303 291 : if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
304 291 : if (Bits[R600::FeatureLocalMemorySize0] && LocalMemorySize < 0) LocalMemorySize = 0;
305 291 : if (Bits[R600::FeatureLocalMemorySize32768] && LocalMemorySize < 32768) LocalMemorySize = 32768;
306 291 : if (Bits[R600::FeatureLocalMemorySize65536] && LocalMemorySize < 65536) LocalMemorySize = 65536;
307 291 : if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
308 291 : if (Bits[R600::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
309 291 : if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
310 291 : if (Bits[R600::FeatureR600ALUInst]) R600ALUInst = false;
311 291 : if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
312 291 : if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
313 291 : if (Bits[R600::FeatureWavefrontSize16] && WavefrontSize < 16) WavefrontSize = 16;
314 291 : if (Bits[R600::FeatureWavefrontSize32] && WavefrontSize < 32) WavefrontSize = 32;
315 291 : if (Bits[R600::FeatureWavefrontSize64] && WavefrontSize < 64) WavefrontSize = 64;
316 291 : }
317 : #endif // GET_SUBTARGETINFO_TARGET_DESC
318 :
319 :
320 : #ifdef GET_SUBTARGETINFO_HEADER
321 : #undef GET_SUBTARGETINFO_HEADER
322 :
323 : namespace llvm {
324 : class DFAPacketizer;
325 : namespace R600_MC {
326 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
327 : }
328 :
329 : struct R600GenSubtargetInfo : public TargetSubtargetInfo {
330 : explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
331 : public:
332 : unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
333 : unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
334 : DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
335 : };
336 : } // end namespace llvm
337 :
338 : #endif // GET_SUBTARGETINFO_HEADER
339 :
340 :
341 : #ifdef GET_SUBTARGETINFO_CTOR
342 : #undef GET_SUBTARGETINFO_CTOR
343 :
344 : #include "llvm/CodeGen/TargetSchedule.h"
345 :
346 : namespace llvm {
347 : extern const llvm::SubtargetFeatureKV R600FeatureKV[];
348 : extern const llvm::SubtargetFeatureKV R600SubTypeKV[];
349 : extern const llvm::SubtargetInfoKV R600ProcSchedKV[];
350 : extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
351 : extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
352 : extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
353 : extern const llvm::InstrStage R600Stages[];
354 : extern const unsigned R600OperandCycles[];
355 : extern const unsigned R600ForwardingPaths[];
356 291 : R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
357 : : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(R600FeatureKV, 21), makeArrayRef(R600SubTypeKV, 16),
358 : R600ProcSchedKV, R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
359 291 : R600Stages, R600OperandCycles, R600ForwardingPaths) {}
360 :
361 0 : unsigned R600GenSubtargetInfo
362 : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
363 0 : report_fatal_error("Expected a variant SchedClass");
364 : } // R600GenSubtargetInfo::resolveSchedClass
365 :
366 0 : unsigned R600GenSubtargetInfo
367 : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
368 0 : return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
369 : } // R600GenSubtargetInfo::resolveVariantSchedClass
370 :
371 : } // end namespace llvm
372 :
373 : #endif // GET_SUBTARGETINFO_CTOR
374 :
375 :
376 : #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
377 : #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
378 :
379 : #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
380 :
381 :
382 : #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
383 : #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
384 :
385 : #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
386 :
|
