Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Assembly Matcher Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_ASSEMBLER_HEADER
11 : #undef GET_ASSEMBLER_HEADER
12 : // This should be included into the middle of the declaration of
13 : // your subclasses implementation of MCTargetAsmParser.
14 : uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15 : void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16 : const OperandVector &Operands);
17 : void convertToMapAndConstraints(unsigned Kind,
18 : const OperandVector &Operands) override;
19 : unsigned MatchInstructionImpl(const OperandVector &Operands,
20 : MCInst &Inst,
21 : SmallVectorImpl<NearMissInfo> *NearMisses,
22 : bool matchingInlineAsm,
23 : unsigned VariantID = 0);
24 : OperandMatchResultTy MatchOperandParserImpl(
25 : OperandVector &Operands,
26 : StringRef Mnemonic,
27 : bool ParseForAllFeatures = false);
28 : OperandMatchResultTy tryCustomParseOperand(
29 : OperandVector &Operands,
30 : unsigned MCK);
31 :
32 : #endif // GET_ASSEMBLER_HEADER_INFO
33 :
34 :
35 : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
36 : #undef GET_OPERAND_DIAGNOSTIC_TYPES
37 :
38 : Match_AlignedMemory16,
39 : Match_AlignedMemory32,
40 : Match_AlignedMemory64,
41 : Match_AlignedMemory64or128,
42 : Match_AlignedMemory64or128or256,
43 : Match_AlignedMemoryNone,
44 : Match_ComplexRotationEven,
45 : Match_ComplexRotationOdd,
46 : Match_DPR,
47 : Match_DPR_8,
48 : Match_DPR_RegList,
49 : Match_DPR_VFP2,
50 : Match_DupAlignedMemory16,
51 : Match_DupAlignedMemory32,
52 : Match_DupAlignedMemory64,
53 : Match_DupAlignedMemory64or128,
54 : Match_DupAlignedMemoryNone,
55 : Match_GPR,
56 : Match_GPRnopc,
57 : Match_GPRsp,
58 : Match_GPRwithAPSR,
59 : Match_Imm0_1,
60 : Match_Imm0_15,
61 : Match_Imm0_239,
62 : Match_Imm0_255,
63 : Match_Imm0_3,
64 : Match_Imm0_31,
65 : Match_Imm0_32,
66 : Match_Imm0_4095,
67 : Match_Imm0_63,
68 : Match_Imm0_65535,
69 : Match_Imm0_65535Expr,
70 : Match_Imm0_7,
71 : Match_Imm16,
72 : Match_Imm1_15,
73 : Match_Imm1_31,
74 : Match_Imm1_7,
75 : Match_Imm24bit,
76 : Match_Imm256_65535Expr,
77 : Match_Imm32,
78 : Match_Imm8,
79 : Match_Imm8_255,
80 : Match_ImmRange1_16,
81 : Match_ImmRange1_32,
82 : Match_ImmThumbSR,
83 : Match_PKHLSLImm,
84 : Match_QPR,
85 : Match_QPR_8,
86 : Match_QPR_VFP2,
87 : Match_SPR,
88 : Match_SPRRegList,
89 : Match_SPR_8,
90 : Match_SetEndImm,
91 : Match_ShrImm16,
92 : Match_ShrImm32,
93 : Match_ShrImm64,
94 : Match_ShrImm8,
95 : Match_hGPR,
96 : Match_rGPR,
97 : Match_tGPR,
98 : END_OPERAND_DIAGNOSTIC_TYPES
99 : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
100 :
101 :
102 : #ifdef GET_REGISTER_MATCHER
103 : #undef GET_REGISTER_MATCHER
104 :
105 : // Flags for subtarget features that participate in instruction matching.
106 : enum SubtargetFeatureFlag : uint64_t {
107 : Feature_HasV4T = (1ULL << 22),
108 : Feature_HasV5T = (1ULL << 23),
109 : Feature_HasV5TE = (1ULL << 24),
110 : Feature_HasV6 = (1ULL << 25),
111 : Feature_HasV6M = (1ULL << 27),
112 : Feature_HasV8MBaseline = (1ULL << 32),
113 : Feature_HasV8MMainline = (1ULL << 33),
114 : Feature_HasV6T2 = (1ULL << 28),
115 : Feature_HasV6K = (1ULL << 26),
116 : Feature_HasV7 = (1ULL << 29),
117 : Feature_HasV8 = (1ULL << 31),
118 : Feature_PreV8 = (1ULL << 48),
119 : Feature_HasV8_1a = (1ULL << 34),
120 : Feature_HasV8_2a = (1ULL << 35),
121 : Feature_HasV8_3a = (1ULL << 36),
122 : Feature_HasV8_4a = (1ULL << 37),
123 : Feature_HasV8_5a = (1ULL << 38),
124 : Feature_HasVFP2 = (1ULL << 39),
125 : Feature_HasVFP3 = (1ULL << 40),
126 : Feature_HasVFP4 = (1ULL << 41),
127 : Feature_HasDPVFP = (1ULL << 7),
128 : Feature_HasFPARMv8 = (1ULL << 14),
129 : Feature_HasNEON = (1ULL << 17),
130 : Feature_HasSHA2 = (1ULL << 19),
131 : Feature_HasAES = (1ULL << 1),
132 : Feature_HasCrypto = (1ULL << 4),
133 : Feature_HasDotProd = (1ULL << 11),
134 : Feature_HasCRC = (1ULL << 3),
135 : Feature_HasRAS = (1ULL << 18),
136 : Feature_HasFP16 = (1ULL << 12),
137 : Feature_HasFullFP16 = (1ULL << 15),
138 : Feature_HasFP16FML = (1ULL << 13),
139 : Feature_HasDivideInThumb = (1ULL << 10),
140 : Feature_HasDivideInARM = (1ULL << 9),
141 : Feature_HasDSP = (1ULL << 8),
142 : Feature_HasDB = (1ULL << 5),
143 : Feature_HasDFB = (1ULL << 6),
144 : Feature_HasV7Clrex = (1ULL << 30),
145 : Feature_HasAcquireRelease = (1ULL << 2),
146 : Feature_HasMP = (1ULL << 16),
147 : Feature_HasVirtualization = (1ULL << 42),
148 : Feature_HasTrustZone = (1ULL << 21),
149 : Feature_Has8MSecExt = (1ULL << 0),
150 : Feature_IsThumb = (1ULL << 46),
151 : Feature_IsThumb2 = (1ULL << 47),
152 : Feature_IsMClass = (1ULL << 44),
153 : Feature_IsNotMClass = (1ULL << 45),
154 : Feature_IsARM = (1ULL << 43),
155 : Feature_UseNaClTrap = (1ULL << 49),
156 : Feature_UseNegativeImmediates = (1ULL << 50),
157 : Feature_HasSpecCtrl = (1ULL << 20),
158 : Feature_None = 0
159 : };
160 :
161 52044 : static unsigned MatchRegisterName(StringRef Name) {
162 52044 : switch (Name.size()) {
163 : default: break;
164 45695 : case 2: // 43 strings to match.
165 : switch (Name[0]) {
166 : default: break;
167 10730 : case 'd': // 10 strings to match.
168 : switch (Name[1]) {
169 : default: break;
170 : case '0': // 1 string to match.
171 : return 14; // "d0"
172 : case '1': // 1 string to match.
173 : return 15; // "d1"
174 : case '2': // 1 string to match.
175 : return 16; // "d2"
176 : case '3': // 1 string to match.
177 : return 17; // "d3"
178 : case '4': // 1 string to match.
179 : return 18; // "d4"
180 : case '5': // 1 string to match.
181 : return 19; // "d5"
182 : case '6': // 1 string to match.
183 : return 20; // "d6"
184 : case '7': // 1 string to match.
185 : return 21; // "d7"
186 : case '8': // 1 string to match.
187 : return 22; // "d8"
188 : case '9': // 1 string to match.
189 : return 23; // "d9"
190 : }
191 : break;
192 944 : case 'l': // 1 string to match.
193 944 : if (Name[1] != 'r')
194 : break;
195 : return 10; // "lr"
196 649 : case 'p': // 1 string to match.
197 649 : if (Name[1] != 'c')
198 : break;
199 : return 11; // "pc"
200 3974 : case 'q': // 10 strings to match.
201 : switch (Name[1]) {
202 : default: break;
203 : case '0': // 1 string to match.
204 : return 50; // "q0"
205 : case '1': // 1 string to match.
206 : return 51; // "q1"
207 : case '2': // 1 string to match.
208 : return 52; // "q2"
209 : case '3': // 1 string to match.
210 : return 53; // "q3"
211 : case '4': // 1 string to match.
212 : return 54; // "q4"
213 : case '5': // 1 string to match.
214 : return 55; // "q5"
215 : case '6': // 1 string to match.
216 : return 56; // "q6"
217 : case '7': // 1 string to match.
218 : return 57; // "q7"
219 : case '8': // 1 string to match.
220 : return 58; // "q8"
221 : case '9': // 1 string to match.
222 : return 59; // "q9"
223 : }
224 : break;
225 26142 : case 'r': // 10 strings to match.
226 : switch (Name[1]) {
227 : default: break;
228 : case '0': // 1 string to match.
229 : return 66; // "r0"
230 : case '1': // 1 string to match.
231 : return 67; // "r1"
232 : case '2': // 1 string to match.
233 : return 68; // "r2"
234 : case '3': // 1 string to match.
235 : return 69; // "r3"
236 : case '4': // 1 string to match.
237 : return 70; // "r4"
238 : case '5': // 1 string to match.
239 : return 71; // "r5"
240 : case '6': // 1 string to match.
241 : return 72; // "r6"
242 : case '7': // 1 string to match.
243 : return 73; // "r7"
244 : case '8': // 1 string to match.
245 : return 74; // "r8"
246 : case '9': // 1 string to match.
247 : return 75; // "r9"
248 : }
249 : break;
250 3128 : case 's': // 11 strings to match.
251 : switch (Name[1]) {
252 : default: break;
253 : case '0': // 1 string to match.
254 : return 79; // "s0"
255 : case '1': // 1 string to match.
256 : return 80; // "s1"
257 : case '2': // 1 string to match.
258 : return 81; // "s2"
259 : case '3': // 1 string to match.
260 : return 82; // "s3"
261 : case '4': // 1 string to match.
262 : return 83; // "s4"
263 : case '5': // 1 string to match.
264 : return 84; // "s5"
265 : case '6': // 1 string to match.
266 : return 85; // "s6"
267 : case '7': // 1 string to match.
268 : return 86; // "s7"
269 : case '8': // 1 string to match.
270 : return 87; // "s8"
271 : case '9': // 1 string to match.
272 : return 88; // "s9"
273 : case 'p': // 1 string to match.
274 : return 12; // "sp"
275 : }
276 : break;
277 : }
278 : break;
279 5939 : case 3: // 53 strings to match.
280 : switch (Name[0]) {
281 : default: break;
282 3529 : case 'd': // 22 strings to match.
283 : switch (Name[1]) {
284 : default: break;
285 3143 : case '1': // 10 strings to match.
286 : switch (Name[2]) {
287 : default: break;
288 : case '0': // 1 string to match.
289 : return 24; // "d10"
290 : case '1': // 1 string to match.
291 : return 25; // "d11"
292 : case '2': // 1 string to match.
293 : return 26; // "d12"
294 : case '3': // 1 string to match.
295 : return 27; // "d13"
296 : case '4': // 1 string to match.
297 : return 28; // "d14"
298 : case '5': // 1 string to match.
299 : return 29; // "d15"
300 : case '6': // 1 string to match.
301 : return 30; // "d16"
302 : case '7': // 1 string to match.
303 : return 31; // "d17"
304 : case '8': // 1 string to match.
305 : return 32; // "d18"
306 : case '9': // 1 string to match.
307 : return 33; // "d19"
308 : }
309 : break;
310 347 : case '2': // 10 strings to match.
311 : switch (Name[2]) {
312 : default: break;
313 : case '0': // 1 string to match.
314 : return 34; // "d20"
315 : case '1': // 1 string to match.
316 : return 35; // "d21"
317 : case '2': // 1 string to match.
318 : return 36; // "d22"
319 : case '3': // 1 string to match.
320 : return 37; // "d23"
321 : case '4': // 1 string to match.
322 : return 38; // "d24"
323 : case '5': // 1 string to match.
324 : return 39; // "d25"
325 : case '6': // 1 string to match.
326 : return 40; // "d26"
327 : case '7': // 1 string to match.
328 : return 41; // "d27"
329 : case '8': // 1 string to match.
330 : return 42; // "d28"
331 : case '9': // 1 string to match.
332 : return 43; // "d29"
333 : }
334 : break;
335 39 : case '3': // 2 strings to match.
336 : switch (Name[2]) {
337 : default: break;
338 : case '0': // 1 string to match.
339 : return 44; // "d30"
340 20 : case '1': // 1 string to match.
341 20 : return 45; // "d31"
342 : }
343 : break;
344 : }
345 : break;
346 151 : case 'q': // 6 strings to match.
347 151 : if (Name[1] != '1')
348 : break;
349 : switch (Name[2]) {
350 : default: break;
351 : case '0': // 1 string to match.
352 : return 60; // "q10"
353 : case '1': // 1 string to match.
354 : return 61; // "q11"
355 : case '2': // 1 string to match.
356 : return 62; // "q12"
357 : case '3': // 1 string to match.
358 : return 63; // "q13"
359 : case '4': // 1 string to match.
360 : return 64; // "q14"
361 : case '5': // 1 string to match.
362 : return 65; // "q15"
363 : }
364 : break;
365 1346 : case 'r': // 3 strings to match.
366 1346 : if (Name[1] != '1')
367 : break;
368 : switch (Name[2]) {
369 : default: break;
370 : case '0': // 1 string to match.
371 : return 76; // "r10"
372 : case '1': // 1 string to match.
373 : return 77; // "r11"
374 : case '2': // 1 string to match.
375 : return 78; // "r12"
376 : }
377 : break;
378 207 : case 's': // 22 strings to match.
379 : switch (Name[1]) {
380 : default: break;
381 142 : case '1': // 10 strings to match.
382 : switch (Name[2]) {
383 : default: break;
384 : case '0': // 1 string to match.
385 : return 89; // "s10"
386 : case '1': // 1 string to match.
387 : return 90; // "s11"
388 : case '2': // 1 string to match.
389 : return 91; // "s12"
390 : case '3': // 1 string to match.
391 : return 92; // "s13"
392 : case '4': // 1 string to match.
393 : return 93; // "s14"
394 : case '5': // 1 string to match.
395 : return 94; // "s15"
396 : case '6': // 1 string to match.
397 : return 95; // "s16"
398 : case '7': // 1 string to match.
399 : return 96; // "s17"
400 : case '8': // 1 string to match.
401 : return 97; // "s18"
402 : case '9': // 1 string to match.
403 : return 98; // "s19"
404 : }
405 : break;
406 57 : case '2': // 10 strings to match.
407 : switch (Name[2]) {
408 : default: break;
409 : case '0': // 1 string to match.
410 : return 99; // "s20"
411 : case '1': // 1 string to match.
412 : return 100; // "s21"
413 : case '2': // 1 string to match.
414 : return 101; // "s22"
415 : case '3': // 1 string to match.
416 : return 102; // "s23"
417 : case '4': // 1 string to match.
418 : return 103; // "s24"
419 : case '5': // 1 string to match.
420 : return 104; // "s25"
421 : case '6': // 1 string to match.
422 : return 105; // "s26"
423 : case '7': // 1 string to match.
424 : return 106; // "s27"
425 : case '8': // 1 string to match.
426 : return 107; // "s28"
427 : case '9': // 1 string to match.
428 : return 108; // "s29"
429 : }
430 : break;
431 8 : case '3': // 2 strings to match.
432 : switch (Name[2]) {
433 : default: break;
434 : case '0': // 1 string to match.
435 : return 109; // "s30"
436 2 : case '1': // 1 string to match.
437 2 : return 110; // "s31"
438 : }
439 : break;
440 : }
441 : break;
442 : }
443 : break;
444 70 : case 4: // 3 strings to match.
445 : switch (Name[0]) {
446 : default: break;
447 : case 'a': // 1 string to match.
448 4 : if (memcmp(Name.data()+1, "psr", 3) != 0)
449 : break;
450 : return 1; // "apsr"
451 : case 'c': // 1 string to match.
452 9 : if (memcmp(Name.data()+1, "psr", 3) != 0)
453 : break;
454 : return 3; // "cpsr"
455 : case 's': // 1 string to match.
456 15 : if (memcmp(Name.data()+1, "psr", 3) != 0)
457 : break;
458 : return 13; // "spsr"
459 : }
460 : break;
461 169 : case 5: // 6 strings to match.
462 : switch (Name[0]) {
463 : default: break;
464 111 : case 'f': // 3 strings to match.
465 111 : if (Name[1] != 'p')
466 : break;
467 : switch (Name[2]) {
468 : default: break;
469 : case 'e': // 1 string to match.
470 9 : if (memcmp(Name.data()+3, "xc", 2) != 0)
471 : break;
472 : return 4; // "fpexc"
473 102 : case 's': // 2 strings to match.
474 : switch (Name[3]) {
475 : default: break;
476 77 : case 'c': // 1 string to match.
477 77 : if (Name[4] != 'r')
478 : break;
479 : return 6; // "fpscr"
480 25 : case 'i': // 1 string to match.
481 25 : if (Name[4] != 'd')
482 : break;
483 : return 8; // "fpsid"
484 : }
485 : break;
486 : }
487 : break;
488 : case 'm': // 3 strings to match.
489 32 : if (memcmp(Name.data()+1, "vfr", 3) != 0)
490 : break;
491 : switch (Name[4]) {
492 : default: break;
493 : case '0': // 1 string to match.
494 : return 47; // "mvfr0"
495 : case '1': // 1 string to match.
496 : return 48; // "mvfr1"
497 : case '2': // 1 string to match.
498 : return 49; // "mvfr2"
499 : }
500 : break;
501 : }
502 : break;
503 : case 6: // 1 string to match.
504 45 : if (memcmp(Name.data()+0, "fpinst", 6) != 0)
505 : break;
506 : return 5; // "fpinst"
507 11 : case 7: // 2 strings to match.
508 : switch (Name[0]) {
509 : default: break;
510 : case 'f': // 1 string to match.
511 2 : if (memcmp(Name.data()+1, "pinst2", 6) != 0)
512 : break;
513 : return 46; // "fpinst2"
514 : case 'i': // 1 string to match.
515 2 : if (memcmp(Name.data()+1, "tstate", 6) != 0)
516 : break;
517 : return 9; // "itstate"
518 : }
519 : break;
520 : case 9: // 1 string to match.
521 36 : if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0)
522 : break;
523 : return 2; // "apsr_nzcv"
524 : case 10: // 1 string to match.
525 9 : if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0)
526 : break;
527 : return 7; // "fpscr_nzcv"
528 : }
529 : return 0;
530 : }
531 :
532 : #endif // GET_REGISTER_MATCHER
533 :
534 :
535 : #ifdef GET_SUBTARGET_FEATURE_NAME
536 : #undef GET_SUBTARGET_FEATURE_NAME
537 :
538 : // User-level names for subtarget features that participate in
539 : // instruction matching.
540 2332 : static const char *getSubtargetFeatureName(uint64_t Val) {
541 2332 : switch(Val) {
542 : case Feature_HasV4T: return "armv4t";
543 1 : case Feature_HasV5T: return "armv5t";
544 0 : case Feature_HasV5TE: return "armv5te";
545 0 : case Feature_HasV6: return "armv6";
546 12 : case Feature_HasV6M: return "armv6m or armv6t2";
547 12 : case Feature_HasV8MBaseline: return "armv8m.base";
548 2 : case Feature_HasV8MMainline: return "armv8m.main";
549 4 : case Feature_HasV6T2: return "armv6t2";
550 5 : case Feature_HasV6K: return "armv6k";
551 6 : case Feature_HasV7: return "armv7";
552 113 : case Feature_HasV8: return "armv8";
553 2 : case Feature_PreV8: return "armv7 or earlier";
554 36 : case Feature_HasV8_1a: return "armv8.1a";
555 0 : case Feature_HasV8_2a: return "armv8.2a";
556 42 : case Feature_HasV8_3a: return "armv8.3a";
557 0 : case Feature_HasV8_4a: return "armv8.4a";
558 0 : case Feature_HasV8_5a: return "armv8.5a";
559 12 : case Feature_HasVFP2: return "VFP2";
560 0 : case Feature_HasVFP3: return "VFP3";
561 0 : case Feature_HasVFP4: return "VFP4";
562 52 : case Feature_HasDPVFP: return "double precision VFP";
563 669 : case Feature_HasFPARMv8: return "FPARMv8";
564 319 : case Feature_HasNEON: return "NEON";
565 0 : case Feature_HasSHA2: return "sha2";
566 0 : case Feature_HasAES: return "aes";
567 105 : case Feature_HasCrypto: return "crypto";
568 64 : case Feature_HasDotProd: return "dotprod";
569 42 : case Feature_HasCRC: return "crc";
570 0 : case Feature_HasRAS: return "ras";
571 4 : case Feature_HasFP16: return "half-float conversions";
572 384 : case Feature_HasFullFP16: return "full half-float";
573 80 : case Feature_HasFP16FML: return "full half-float fml";
574 11 : case Feature_HasDivideInThumb: return "divide in THUMB";
575 11 : case Feature_HasDivideInARM: return "divide in ARM";
576 12 : case Feature_HasDSP: return "dsp";
577 5 : case Feature_HasDB: return "data-barriers";
578 2 : case Feature_HasDFB: return "full-data-barrier";
579 2 : case Feature_HasV7Clrex: return "v7 clrex";
580 28 : case Feature_HasAcquireRelease: return "acquire/release";
581 13 : case Feature_HasMP: return "mp-extensions";
582 0 : case Feature_HasVirtualization: return "virtualization-extensions";
583 11 : case Feature_HasTrustZone: return "TrustZone";
584 0 : case Feature_Has8MSecExt: return "ARMv8-M Security Extensions";
585 5 : case Feature_IsThumb: return "thumb";
586 93 : case Feature_IsThumb2: return "thumb2";
587 0 : case Feature_IsMClass: return "armv*m";
588 22 : case Feature_IsNotMClass: return "!armv*m";
589 96 : case Feature_IsARM: return "arm-mode";
590 0 : case Feature_UseNaClTrap: return "NaCl";
591 53 : case Feature_UseNegativeImmediates: return "NegativeImmediates";
592 2 : case Feature_HasSpecCtrl: return "specctrl";
593 0 : default: return "(unknown)";
594 : }
595 : }
596 :
597 : #endif // GET_SUBTARGET_FEATURE_NAME
598 :
599 :
600 : #ifdef GET_MATCHER_IMPLEMENTATION
601 : #undef GET_MATCHER_IMPLEMENTATION
602 :
603 0 : static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
604 : switch (VariantID) {
605 : case 0:
606 : break;
607 : }
608 0 : switch (Mnemonic.size()) {
609 : default: break;
610 0 : case 3: // 4 strings to match.
611 0 : switch (Mnemonic[0]) {
612 : default: break;
613 : case 'r': // 1 string to match.
614 0 : if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
615 : break;
616 0 : Mnemonic = "rfeia"; // "rfe"
617 0 : return;
618 0 : case 's': // 3 strings to match.
619 : switch (Mnemonic[1]) {
620 : default: break;
621 0 : case 'm': // 1 string to match.
622 0 : if (Mnemonic[2] != 'i')
623 : break;
624 0 : Mnemonic = "smc"; // "smi"
625 0 : return;
626 0 : case 'r': // 1 string to match.
627 0 : if (Mnemonic[2] != 's')
628 : break;
629 0 : Mnemonic = "srsia"; // "srs"
630 0 : return;
631 0 : case 'w': // 1 string to match.
632 0 : if (Mnemonic[2] != 'i')
633 : break;
634 0 : Mnemonic = "svc"; // "swi"
635 0 : return;
636 : }
637 : break;
638 : }
639 : break;
640 0 : case 4: // 10 strings to match.
641 0 : switch (Mnemonic[0]) {
642 : default: break;
643 0 : case 'f': // 8 strings to match.
644 : switch (Mnemonic[1]) {
645 : default: break;
646 0 : case 'l': // 2 strings to match.
647 0 : if (Mnemonic[2] != 'd')
648 : break;
649 : switch (Mnemonic[3]) {
650 : default: break;
651 0 : case 'd': // 1 string to match.
652 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldd"
653 0 : Mnemonic = "vldr";
654 : return;
655 0 : case 's': // 1 string to match.
656 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "flds"
657 0 : Mnemonic = "vldr";
658 : return;
659 : }
660 : break;
661 0 : case 'm': // 4 strings to match.
662 : switch (Mnemonic[2]) {
663 : default: break;
664 0 : case 'r': // 2 strings to match.
665 : switch (Mnemonic[3]) {
666 : default: break;
667 0 : case 's': // 1 string to match.
668 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrs"
669 0 : Mnemonic = "vmov";
670 : return;
671 0 : case 'x': // 1 string to match.
672 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrx"
673 0 : Mnemonic = "vmrs";
674 : return;
675 : }
676 : break;
677 0 : case 's': // 1 string to match.
678 0 : if (Mnemonic[3] != 'r')
679 : break;
680 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmsr"
681 0 : Mnemonic = "vmov";
682 : return;
683 0 : case 'x': // 1 string to match.
684 0 : if (Mnemonic[3] != 'r')
685 : break;
686 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmxr"
687 0 : Mnemonic = "vmsr";
688 : return;
689 : }
690 : break;
691 0 : case 's': // 2 strings to match.
692 0 : if (Mnemonic[2] != 't')
693 : break;
694 : switch (Mnemonic[3]) {
695 : default: break;
696 0 : case 'd': // 1 string to match.
697 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstd"
698 0 : Mnemonic = "vstr";
699 : return;
700 0 : case 's': // 1 string to match.
701 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsts"
702 0 : Mnemonic = "vstr";
703 : return;
704 : }
705 : break;
706 : }
707 : break;
708 0 : case 'v': // 2 strings to match.
709 : switch (Mnemonic[1]) {
710 : default: break;
711 : case 'l': // 1 string to match.
712 0 : if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
713 : break;
714 0 : Mnemonic = "vldmia"; // "vldm"
715 0 : return;
716 : case 's': // 1 string to match.
717 0 : if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
718 : break;
719 0 : Mnemonic = "vstmia"; // "vstm"
720 0 : return;
721 : }
722 : break;
723 : }
724 : break;
725 0 : case 5: // 51 strings to match.
726 0 : switch (Mnemonic[0]) {
727 : default: break;
728 0 : case 'f': // 18 strings to match.
729 : switch (Mnemonic[1]) {
730 : default: break;
731 : case 'a': // 2 strings to match.
732 0 : if (memcmp(Mnemonic.data()+2, "dd", 2) != 0)
733 : break;
734 : switch (Mnemonic[4]) {
735 : default: break;
736 0 : case 'd': // 1 string to match.
737 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "faddd"
738 0 : Mnemonic = "vadd.f64";
739 : return;
740 0 : case 's': // 1 string to match.
741 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fadds"
742 0 : Mnemonic = "vadd.f32";
743 : return;
744 : }
745 : break;
746 0 : case 'c': // 4 strings to match.
747 : switch (Mnemonic[2]) {
748 : default: break;
749 0 : case 'm': // 2 strings to match.
750 0 : if (Mnemonic[3] != 'p')
751 : break;
752 : switch (Mnemonic[4]) {
753 : default: break;
754 0 : case 'd': // 1 string to match.
755 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcmpd"
756 0 : Mnemonic = "vcmp.f64";
757 : return;
758 0 : case 's': // 1 string to match.
759 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcmps"
760 0 : Mnemonic = "vcmp.f32";
761 : return;
762 : }
763 : break;
764 0 : case 'p': // 2 strings to match.
765 0 : if (Mnemonic[3] != 'y')
766 : break;
767 : switch (Mnemonic[4]) {
768 : default: break;
769 0 : case 'd': // 1 string to match.
770 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcpyd"
771 0 : Mnemonic = "vmov.f64";
772 : return;
773 0 : case 's': // 1 string to match.
774 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcpys"
775 0 : Mnemonic = "vmov.f32";
776 : return;
777 : }
778 : break;
779 : }
780 : break;
781 : case 'd': // 2 strings to match.
782 0 : if (memcmp(Mnemonic.data()+2, "iv", 2) != 0)
783 : break;
784 : switch (Mnemonic[4]) {
785 : default: break;
786 0 : case 'd': // 1 string to match.
787 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fdivd"
788 0 : Mnemonic = "vdiv.f64";
789 : return;
790 0 : case 's': // 1 string to match.
791 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fdivs"
792 0 : Mnemonic = "vdiv.f32";
793 : return;
794 : }
795 : break;
796 0 : case 'm': // 8 strings to match.
797 : switch (Mnemonic[2]) {
798 : default: break;
799 0 : case 'a': // 2 strings to match.
800 0 : if (Mnemonic[3] != 'c')
801 : break;
802 : switch (Mnemonic[4]) {
803 : default: break;
804 0 : case 'd': // 1 string to match.
805 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmacd"
806 0 : Mnemonic = "vmla.f64";
807 : return;
808 0 : case 's': // 1 string to match.
809 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmacs"
810 0 : Mnemonic = "vmla.f32";
811 : return;
812 : }
813 : break;
814 : case 'd': // 1 string to match.
815 0 : if (memcmp(Mnemonic.data()+3, "rr", 2) != 0)
816 : break;
817 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmdrr"
818 0 : Mnemonic = "vmov";
819 : return;
820 0 : case 'r': // 3 strings to match.
821 : switch (Mnemonic[3]) {
822 : default: break;
823 0 : case 'd': // 2 strings to match.
824 : switch (Mnemonic[4]) {
825 : default: break;
826 0 : case 'd': // 1 string to match.
827 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrdd"
828 0 : Mnemonic = "vmov";
829 : return;
830 0 : case 's': // 1 string to match.
831 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrds"
832 0 : Mnemonic = "vmov";
833 : return;
834 : }
835 : break;
836 0 : case 'r': // 1 string to match.
837 0 : if (Mnemonic[4] != 'd')
838 : break;
839 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrrd"
840 0 : Mnemonic = "vmov";
841 : return;
842 : }
843 : break;
844 0 : case 'u': // 2 strings to match.
845 0 : if (Mnemonic[3] != 'l')
846 : break;
847 : switch (Mnemonic[4]) {
848 : default: break;
849 0 : case 'd': // 1 string to match.
850 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmuld"
851 0 : Mnemonic = "vmul.f64";
852 : return;
853 0 : case 's': // 1 string to match.
854 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmuls"
855 0 : Mnemonic = "vmul.f32";
856 : return;
857 : }
858 : break;
859 : }
860 : break;
861 : case 'n': // 2 strings to match.
862 0 : if (memcmp(Mnemonic.data()+2, "eg", 2) != 0)
863 : break;
864 : switch (Mnemonic[4]) {
865 : default: break;
866 0 : case 'd': // 1 string to match.
867 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fnegd"
868 0 : Mnemonic = "vneg.f64";
869 : return;
870 0 : case 's': // 1 string to match.
871 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fnegs"
872 0 : Mnemonic = "vneg.f32";
873 : return;
874 : }
875 : break;
876 : }
877 : break;
878 : case 'l': // 3 strings to match.
879 0 : if (memcmp(Mnemonic.data()+1, "dm", 2) != 0)
880 : break;
881 : switch (Mnemonic[3]) {
882 : default: break;
883 0 : case 'e': // 1 string to match.
884 0 : if (Mnemonic[4] != 'a')
885 : break;
886 0 : Mnemonic = "ldmdb"; // "ldmea"
887 0 : return;
888 0 : case 'f': // 1 string to match.
889 0 : if (Mnemonic[4] != 'd')
890 : break;
891 0 : Mnemonic = "ldm"; // "ldmfd"
892 0 : return;
893 0 : case 'i': // 1 string to match.
894 0 : if (Mnemonic[4] != 'a')
895 : break;
896 0 : Mnemonic = "ldm"; // "ldmia"
897 0 : return;
898 : }
899 : break;
900 : case 'r': // 4 strings to match.
901 0 : if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
902 : break;
903 : switch (Mnemonic[3]) {
904 : default: break;
905 0 : case 'e': // 2 strings to match.
906 : switch (Mnemonic[4]) {
907 : default: break;
908 : case 'a': // 1 string to match.
909 0 : Mnemonic = "rfedb"; // "rfeea"
910 0 : return;
911 : case 'd': // 1 string to match.
912 0 : Mnemonic = "rfeib"; // "rfeed"
913 0 : return;
914 : }
915 : break;
916 0 : case 'f': // 2 strings to match.
917 : switch (Mnemonic[4]) {
918 : default: break;
919 : case 'a': // 1 string to match.
920 0 : Mnemonic = "rfeda"; // "rfefa"
921 0 : return;
922 : case 'd': // 1 string to match.
923 0 : Mnemonic = "rfeia"; // "rfefd"
924 0 : return;
925 : }
926 : break;
927 : }
928 : break;
929 0 : case 's': // 7 strings to match.
930 : switch (Mnemonic[1]) {
931 : default: break;
932 0 : case 'r': // 4 strings to match.
933 0 : if (Mnemonic[2] != 's')
934 : break;
935 : switch (Mnemonic[3]) {
936 : default: break;
937 0 : case 'e': // 2 strings to match.
938 : switch (Mnemonic[4]) {
939 : default: break;
940 : case 'a': // 1 string to match.
941 0 : Mnemonic = "srsia"; // "srsea"
942 0 : return;
943 : case 'd': // 1 string to match.
944 0 : Mnemonic = "srsda"; // "srsed"
945 0 : return;
946 : }
947 : break;
948 0 : case 'f': // 2 strings to match.
949 : switch (Mnemonic[4]) {
950 : default: break;
951 : case 'a': // 1 string to match.
952 0 : Mnemonic = "srsib"; // "srsfa"
953 0 : return;
954 : case 'd': // 1 string to match.
955 0 : Mnemonic = "srsdb"; // "srsfd"
956 0 : return;
957 : }
958 : break;
959 : }
960 : break;
961 0 : case 't': // 3 strings to match.
962 0 : if (Mnemonic[2] != 'm')
963 : break;
964 : switch (Mnemonic[3]) {
965 : default: break;
966 0 : case 'e': // 1 string to match.
967 0 : if (Mnemonic[4] != 'a')
968 : break;
969 0 : Mnemonic = "stm"; // "stmea"
970 0 : return;
971 0 : case 'f': // 1 string to match.
972 0 : if (Mnemonic[4] != 'd')
973 : break;
974 0 : Mnemonic = "stmdb"; // "stmfd"
975 0 : return;
976 0 : case 'i': // 1 string to match.
977 0 : if (Mnemonic[4] != 'a')
978 : break;
979 0 : Mnemonic = "stm"; // "stmia"
980 0 : return;
981 : }
982 : break;
983 : }
984 : break;
985 0 : case 'v': // 19 strings to match.
986 : switch (Mnemonic[1]) {
987 : default: break;
988 0 : case 'a': // 3 strings to match.
989 : switch (Mnemonic[2]) {
990 : default: break;
991 : case 'b': // 1 string to match.
992 0 : if (memcmp(Mnemonic.data()+3, "sq", 2) != 0)
993 : break;
994 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vabsq"
995 0 : Mnemonic = "vabs";
996 : return;
997 : case 'd': // 1 string to match.
998 0 : if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
999 : break;
1000 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vaddq"
1001 0 : Mnemonic = "vadd";
1002 : return;
1003 : case 'n': // 1 string to match.
1004 0 : if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1005 : break;
1006 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vandq"
1007 0 : Mnemonic = "vand";
1008 : return;
1009 : }
1010 : break;
1011 : case 'b': // 1 string to match.
1012 0 : if (memcmp(Mnemonic.data()+2, "icq", 3) != 0)
1013 : break;
1014 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vbicq"
1015 0 : Mnemonic = "vbic";
1016 : return;
1017 0 : case 'c': // 3 strings to match.
1018 : switch (Mnemonic[2]) {
1019 : default: break;
1020 : case 'e': // 1 string to match.
1021 0 : if (memcmp(Mnemonic.data()+3, "qq", 2) != 0)
1022 : break;
1023 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vceqq"
1024 0 : Mnemonic = "vceq";
1025 : return;
1026 : case 'l': // 1 string to match.
1027 0 : if (memcmp(Mnemonic.data()+3, "eq", 2) != 0)
1028 : break;
1029 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vcleq"
1030 0 : Mnemonic = "vcle";
1031 : return;
1032 : case 'v': // 1 string to match.
1033 0 : if (memcmp(Mnemonic.data()+3, "tq", 2) != 0)
1034 : break;
1035 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vcvtq"
1036 0 : Mnemonic = "vcvt";
1037 : return;
1038 : }
1039 : break;
1040 : case 'e': // 1 string to match.
1041 0 : if (memcmp(Mnemonic.data()+2, "orq", 3) != 0)
1042 : break;
1043 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "veorq"
1044 0 : Mnemonic = "veor";
1045 : return;
1046 0 : case 'm': // 5 strings to match.
1047 : switch (Mnemonic[2]) {
1048 : default: break;
1049 : case 'a': // 1 string to match.
1050 0 : if (memcmp(Mnemonic.data()+3, "xq", 2) != 0)
1051 : break;
1052 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmaxq"
1053 0 : Mnemonic = "vmax";
1054 : return;
1055 : case 'i': // 1 string to match.
1056 0 : if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1057 : break;
1058 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vminq"
1059 0 : Mnemonic = "vmin";
1060 : return;
1061 : case 'o': // 1 string to match.
1062 0 : if (memcmp(Mnemonic.data()+3, "vq", 2) != 0)
1063 : break;
1064 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq"
1065 0 : Mnemonic = "vmov";
1066 : return;
1067 : case 'u': // 1 string to match.
1068 0 : if (memcmp(Mnemonic.data()+3, "lq", 2) != 0)
1069 : break;
1070 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmulq"
1071 0 : Mnemonic = "vmul";
1072 : return;
1073 : case 'v': // 1 string to match.
1074 0 : if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1075 : break;
1076 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmvnq"
1077 0 : Mnemonic = "vmvn";
1078 : return;
1079 : }
1080 : break;
1081 : case 'o': // 1 string to match.
1082 0 : if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0)
1083 : break;
1084 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vorrq"
1085 0 : Mnemonic = "vorr";
1086 : return;
1087 0 : case 's': // 4 strings to match.
1088 : switch (Mnemonic[2]) {
1089 : default: break;
1090 0 : case 'h': // 2 strings to match.
1091 : switch (Mnemonic[3]) {
1092 : default: break;
1093 0 : case 'l': // 1 string to match.
1094 0 : if (Mnemonic[4] != 'q')
1095 : break;
1096 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vshlq"
1097 0 : Mnemonic = "vshl";
1098 : return;
1099 0 : case 'r': // 1 string to match.
1100 0 : if (Mnemonic[4] != 'q')
1101 : break;
1102 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vshrq"
1103 0 : Mnemonic = "vshr";
1104 : return;
1105 : }
1106 : break;
1107 : case 'u': // 1 string to match.
1108 0 : if (memcmp(Mnemonic.data()+3, "bq", 2) != 0)
1109 : break;
1110 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vsubq"
1111 0 : Mnemonic = "vsub";
1112 : return;
1113 : case 'w': // 1 string to match.
1114 0 : if (memcmp(Mnemonic.data()+3, "pq", 2) != 0)
1115 : break;
1116 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vswpq"
1117 0 : Mnemonic = "vswp";
1118 : return;
1119 : }
1120 : break;
1121 : case 'z': // 1 string to match.
1122 0 : if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0)
1123 : break;
1124 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vzipq"
1125 0 : Mnemonic = "vzip";
1126 : return;
1127 : }
1128 : break;
1129 : }
1130 : break;
1131 0 : case 6: // 10 strings to match.
1132 0 : if (Mnemonic[0] != 'f')
1133 : break;
1134 : switch (Mnemonic[1]) {
1135 : default: break;
1136 0 : case 's': // 4 strings to match.
1137 : switch (Mnemonic[2]) {
1138 : default: break;
1139 : case 'i': // 2 strings to match.
1140 0 : if (memcmp(Mnemonic.data()+3, "to", 2) != 0)
1141 : break;
1142 : switch (Mnemonic[5]) {
1143 : default: break;
1144 0 : case 'd': // 1 string to match.
1145 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsitod"
1146 0 : Mnemonic = "vcvt.f64.s32";
1147 : return;
1148 0 : case 's': // 1 string to match.
1149 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsitos"
1150 0 : Mnemonic = "vcvt.f32.s32";
1151 : return;
1152 : }
1153 : break;
1154 : case 'q': // 2 strings to match.
1155 0 : if (memcmp(Mnemonic.data()+3, "rt", 2) != 0)
1156 : break;
1157 : switch (Mnemonic[5]) {
1158 : default: break;
1159 0 : case 'd': // 1 string to match.
1160 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsqrtd"
1161 0 : Mnemonic = "vsqrt";
1162 : return;
1163 0 : case 's': // 1 string to match.
1164 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsqrts"
1165 0 : Mnemonic = "vsqrt";
1166 : return;
1167 : }
1168 : break;
1169 : }
1170 : break;
1171 0 : case 't': // 4 strings to match.
1172 0 : if (Mnemonic[2] != 'o')
1173 : break;
1174 : switch (Mnemonic[3]) {
1175 : default: break;
1176 0 : case 's': // 2 strings to match.
1177 0 : if (Mnemonic[4] != 'i')
1178 : break;
1179 : switch (Mnemonic[5]) {
1180 : default: break;
1181 0 : case 'd': // 1 string to match.
1182 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosid"
1183 0 : Mnemonic = "vcvtr.s32.f64";
1184 : return;
1185 0 : case 's': // 1 string to match.
1186 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosis"
1187 0 : Mnemonic = "vcvtr.s32.f32";
1188 : return;
1189 : }
1190 : break;
1191 0 : case 'u': // 2 strings to match.
1192 0 : if (Mnemonic[4] != 'i')
1193 : break;
1194 : switch (Mnemonic[5]) {
1195 : default: break;
1196 0 : case 'd': // 1 string to match.
1197 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouid"
1198 0 : Mnemonic = "vcvtr.u32.f64";
1199 : return;
1200 0 : case 's': // 1 string to match.
1201 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouis"
1202 0 : Mnemonic = "vcvtr.u32.f32";
1203 : return;
1204 : }
1205 : break;
1206 : }
1207 : break;
1208 : case 'u': // 2 strings to match.
1209 0 : if (memcmp(Mnemonic.data()+2, "ito", 3) != 0)
1210 : break;
1211 : switch (Mnemonic[5]) {
1212 : default: break;
1213 0 : case 'd': // 1 string to match.
1214 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fuitod"
1215 0 : Mnemonic = "vcvt.f64.u32";
1216 : return;
1217 0 : case 's': // 1 string to match.
1218 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fuitos"
1219 0 : Mnemonic = "vcvt.f32.u32";
1220 : return;
1221 : }
1222 : break;
1223 : }
1224 : break;
1225 0 : case 7: // 8 strings to match.
1226 0 : if (Mnemonic[0] != 'f')
1227 : break;
1228 : switch (Mnemonic[1]) {
1229 : default: break;
1230 : case 'l': // 2 strings to match.
1231 0 : if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
1232 : break;
1233 : switch (Mnemonic[4]) {
1234 : default: break;
1235 : case 'e': // 1 string to match.
1236 0 : if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1237 : break;
1238 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmeax"
1239 0 : Mnemonic = "fldmdbx";
1240 : return;
1241 : case 'f': // 1 string to match.
1242 0 : if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1243 : break;
1244 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmfdx"
1245 0 : Mnemonic = "fldmiax";
1246 : return;
1247 : }
1248 : break;
1249 : case 's': // 2 strings to match.
1250 0 : if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
1251 : break;
1252 : switch (Mnemonic[4]) {
1253 : default: break;
1254 : case 'e': // 1 string to match.
1255 0 : if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1256 : break;
1257 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmeax"
1258 0 : Mnemonic = "fstmiax";
1259 : return;
1260 : case 'f': // 1 string to match.
1261 0 : if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1262 : break;
1263 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmfdx"
1264 0 : Mnemonic = "fstmdbx";
1265 : return;
1266 : }
1267 : break;
1268 0 : case 't': // 4 strings to match.
1269 0 : if (Mnemonic[2] != 'o')
1270 : break;
1271 : switch (Mnemonic[3]) {
1272 : default: break;
1273 : case 's': // 2 strings to match.
1274 0 : if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1275 : break;
1276 : switch (Mnemonic[6]) {
1277 : default: break;
1278 0 : case 'd': // 1 string to match.
1279 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosizd"
1280 0 : Mnemonic = "vcvt.s32.f64";
1281 : return;
1282 0 : case 's': // 1 string to match.
1283 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosizs"
1284 0 : Mnemonic = "vcvt.s32.f32";
1285 : return;
1286 : }
1287 : break;
1288 : case 'u': // 2 strings to match.
1289 0 : if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1290 : break;
1291 : switch (Mnemonic[6]) {
1292 : default: break;
1293 0 : case 'd': // 1 string to match.
1294 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouizd"
1295 0 : Mnemonic = "vcvt.u32.f64";
1296 : return;
1297 0 : case 's': // 1 string to match.
1298 0 : if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouizs"
1299 0 : Mnemonic = "vcvt.u32.f32";
1300 : return;
1301 : }
1302 : break;
1303 : }
1304 : break;
1305 : }
1306 : break;
1307 0 : case 8: // 5 strings to match.
1308 0 : switch (Mnemonic[0]) {
1309 : default: break;
1310 : case 'q': // 1 string to match.
1311 0 : if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0)
1312 : break;
1313 0 : Mnemonic = "qsax"; // "qsubaddx"
1314 0 : return;
1315 0 : case 's': // 2 strings to match.
1316 : switch (Mnemonic[1]) {
1317 : default: break;
1318 : case 'a': // 1 string to match.
1319 0 : if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1320 : break;
1321 0 : Mnemonic = "sasx"; // "saddsubx"
1322 0 : return;
1323 : case 's': // 1 string to match.
1324 0 : if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1325 : break;
1326 0 : Mnemonic = "ssax"; // "ssubaddx"
1327 0 : return;
1328 : }
1329 : break;
1330 0 : case 'u': // 2 strings to match.
1331 : switch (Mnemonic[1]) {
1332 : default: break;
1333 : case 'a': // 1 string to match.
1334 0 : if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1335 : break;
1336 0 : Mnemonic = "uasx"; // "uaddsubx"
1337 0 : return;
1338 : case 's': // 1 string to match.
1339 0 : if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1340 : break;
1341 0 : Mnemonic = "usax"; // "usubaddx"
1342 0 : return;
1343 : }
1344 : break;
1345 : }
1346 : break;
1347 0 : case 9: // 8 strings to match.
1348 0 : switch (Mnemonic[0]) {
1349 : default: break;
1350 0 : case 's': // 2 strings to match.
1351 0 : if (Mnemonic[1] != 'h')
1352 : break;
1353 : switch (Mnemonic[2]) {
1354 : default: break;
1355 : case 'a': // 1 string to match.
1356 0 : if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1357 : break;
1358 0 : Mnemonic = "shasx"; // "shaddsubx"
1359 0 : return;
1360 : case 's': // 1 string to match.
1361 0 : if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1362 : break;
1363 0 : Mnemonic = "shsax"; // "shsubaddx"
1364 0 : return;
1365 : }
1366 : break;
1367 0 : case 'u': // 4 strings to match.
1368 : switch (Mnemonic[1]) {
1369 : default: break;
1370 0 : case 'h': // 2 strings to match.
1371 : switch (Mnemonic[2]) {
1372 : default: break;
1373 : case 'a': // 1 string to match.
1374 0 : if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1375 : break;
1376 0 : Mnemonic = "uhasx"; // "uhaddsubx"
1377 0 : return;
1378 : case 's': // 1 string to match.
1379 0 : if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1380 : break;
1381 0 : Mnemonic = "uhsax"; // "uhsubaddx"
1382 0 : return;
1383 : }
1384 : break;
1385 0 : case 'q': // 2 strings to match.
1386 : switch (Mnemonic[2]) {
1387 : default: break;
1388 : case 'a': // 1 string to match.
1389 0 : if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1390 : break;
1391 0 : Mnemonic = "uqasx"; // "uqaddsubx"
1392 0 : return;
1393 : case 's': // 1 string to match.
1394 0 : if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1395 : break;
1396 0 : Mnemonic = "uqsax"; // "uqsubaddx"
1397 0 : return;
1398 : }
1399 : break;
1400 : }
1401 : break;
1402 : case 'v': // 2 strings to match.
1403 0 : if (memcmp(Mnemonic.data()+1, "movq.f", 6) != 0)
1404 : break;
1405 : switch (Mnemonic[7]) {
1406 : default: break;
1407 0 : case '3': // 1 string to match.
1408 0 : if (Mnemonic[8] != '2')
1409 : break;
1410 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq.f32"
1411 0 : Mnemonic = "vmov.f32";
1412 : return;
1413 0 : case '6': // 1 string to match.
1414 0 : if (Mnemonic[8] != '4')
1415 : break;
1416 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq.f64"
1417 0 : Mnemonic = "vmov.f64";
1418 : return;
1419 : }
1420 : break;
1421 : }
1422 : break;
1423 : case 11: // 2 strings to match.
1424 0 : if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0)
1425 : break;
1426 : switch (Mnemonic[8]) {
1427 : default: break;
1428 : case 'f': // 1 string to match.
1429 0 : if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
1430 : break;
1431 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vrecpeq.f32"
1432 0 : Mnemonic = "vrecpe.f32";
1433 : return;
1434 : case 'u': // 1 string to match.
1435 0 : if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
1436 : break;
1437 0 : if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vrecpeq.u32"
1438 0 : Mnemonic = "vrecpe.u32";
1439 : return;
1440 : }
1441 : break;
1442 : }
1443 : }
1444 :
1445 : enum {
1446 : Tie0_1_1,
1447 : Tie0_2_2,
1448 : Tie0_3_3,
1449 : Tie0_4_4,
1450 : Tie0_4_5,
1451 : Tie1_1_1,
1452 : Tie1_3_3,
1453 : Tie1_4_4,
1454 : Tie2_4_4,
1455 : };
1456 :
1457 : static const uint8_t TiedAsmOperandTable[][3] = {
1458 : /* Tie0_1_1 */ { 0, 1, 1 },
1459 : /* Tie0_2_2 */ { 0, 2, 2 },
1460 : /* Tie0_3_3 */ { 0, 3, 3 },
1461 : /* Tie0_4_4 */ { 0, 4, 4 },
1462 : /* Tie0_4_5 */ { 0, 4, 5 },
1463 : /* Tie1_1_1 */ { 1, 1, 1 },
1464 : /* Tie1_3_3 */ { 1, 3, 3 },
1465 : /* Tie1_4_4 */ { 1, 4, 4 },
1466 : /* Tie2_4_4 */ { 2, 4, 4 },
1467 : };
1468 :
1469 : namespace {
1470 : enum OperatorConversionKind {
1471 : CVT_Done,
1472 : CVT_Reg,
1473 : CVT_Tied,
1474 : CVT_95_Reg,
1475 : CVT_95_addCCOutOperands,
1476 : CVT_95_addCondCodeOperands,
1477 : CVT_95_addRegShiftedRegOperands,
1478 : CVT_95_addModImmOperands,
1479 : CVT_95_addModImmNotOperands,
1480 : CVT_95_addRegShiftedImmOperands,
1481 : CVT_95_addImmOperands,
1482 : CVT_95_addT2SOImmNotOperands,
1483 : CVT_95_addImm0_95_508s4Operands,
1484 : CVT_regSP,
1485 : CVT_95_addImm0_95_508s4NegOperands,
1486 : CVT_95_addImm0_95_4095NegOperands,
1487 : CVT_95_addThumbModImmNeg8_95_255Operands,
1488 : CVT_95_addT2SOImmNegOperands,
1489 : CVT_95_addModImmNegOperands,
1490 : CVT_95_addImm0_95_1020s4Operands,
1491 : CVT_95_addThumbModImmNeg1_95_7Operands,
1492 : CVT_95_addUnsignedOffset_95_b8s2Operands,
1493 : CVT_95_addAdrLabelOperands,
1494 : CVT_95_addARMBranchTargetOperands,
1495 : CVT_cvtThumbBranches,
1496 : CVT_95_addBitfieldOperands,
1497 : CVT_imm_95_0,
1498 : CVT_95_addThumbBranchTargetOperands,
1499 : CVT_95_addCoprocNumOperands,
1500 : CVT_95_addCoprocRegOperands,
1501 : CVT_95_addProcIFlagsOperands,
1502 : CVT_imm_95_20,
1503 : CVT_imm_95_12,
1504 : CVT_imm_95_15,
1505 : CVT_95_addMemBarrierOptOperands,
1506 : CVT_imm_95_16,
1507 : CVT_95_addFPImmOperands,
1508 : CVT_95_addDPRRegListOperands,
1509 : CVT_imm_95_1,
1510 : CVT_95_addInstSyncBarrierOptOperands,
1511 : CVT_95_addITCondCodeOperands,
1512 : CVT_95_addITMaskOperands,
1513 : CVT_95_addMemNoOffsetOperands,
1514 : CVT_95_addAddrMode5Operands,
1515 : CVT_95_addCoprocOptionOperands,
1516 : CVT_95_addPostIdxImm8s4Operands,
1517 : CVT_95_addRegListOperands,
1518 : CVT_95_addThumbMemPCOperands,
1519 : CVT_95_addConstPoolAsmImmOperands,
1520 : CVT_95_addMemThumbRIs4Operands,
1521 : CVT_95_addMemThumbRROperands,
1522 : CVT_95_addMemThumbSPIOperands,
1523 : CVT_95_addMemImm12OffsetOperands,
1524 : CVT_95_addMemNegImm8OffsetOperands,
1525 : CVT_95_addMemRegOffsetOperands,
1526 : CVT_95_addMemUImm12OffsetOperands,
1527 : CVT_95_addT2MemRegOffsetOperands,
1528 : CVT_95_addMemPCRelImm12Operands,
1529 : CVT_95_addMemImm8OffsetOperands,
1530 : CVT_95_addAM2OffsetImmOperands,
1531 : CVT_95_addPostIdxRegShiftedOperands,
1532 : CVT_95_addMemThumbRIs1Operands,
1533 : CVT_95_addMemPosImm8OffsetOperands,
1534 : CVT_95_addMemImm8s4OffsetOperands,
1535 : CVT_95_addAddrMode3Operands,
1536 : CVT_95_addAM3OffsetOperands,
1537 : CVT_95_addMemImm0_95_1020s4OffsetOperands,
1538 : CVT_95_addMemThumbRIs2Operands,
1539 : CVT_95_addPostIdxRegOperands,
1540 : CVT_95_addPostIdxImm8Operands,
1541 : CVT_reg0,
1542 : CVT_regCPSR,
1543 : CVT_imm_95_14,
1544 : CVT_95_addBankedRegOperands,
1545 : CVT_95_addMSRMaskOperands,
1546 : CVT_cvtThumbMultiply,
1547 : CVT_regR8,
1548 : CVT_regR0,
1549 : CVT_95_addPKHASRImmOperands,
1550 : CVT_imm_95_4,
1551 : CVT_95_addImm1_95_32Operands,
1552 : CVT_imm_95_5,
1553 : CVT_95_addShifterImmOperands,
1554 : CVT_95_addImm1_95_16Operands,
1555 : CVT_95_addRotImmOperands,
1556 : CVT_95_addMemTBBOperands,
1557 : CVT_95_addMemTBHOperands,
1558 : CVT_95_addTraceSyncBarrierOptOperands,
1559 : CVT_95_addNEONi16splatNotOperands,
1560 : CVT_95_addNEONi32splatNotOperands,
1561 : CVT_95_addNEONi16splatOperands,
1562 : CVT_95_addNEONi32splatOperands,
1563 : CVT_95_addComplexRotationOddOperands,
1564 : CVT_95_addComplexRotationEvenOperands,
1565 : CVT_95_addVectorIndex64Operands,
1566 : CVT_95_addVectorIndex32Operands,
1567 : CVT_95_addFBits16Operands,
1568 : CVT_95_addFBits32Operands,
1569 : CVT_95_addVectorIndex16Operands,
1570 : CVT_95_addVectorIndex8Operands,
1571 : CVT_95_addVecListOperands,
1572 : CVT_95_addDupAlignedMemory16Operands,
1573 : CVT_95_addAlignedMemory64or128Operands,
1574 : CVT_95_addAlignedMemory64or128or256Operands,
1575 : CVT_95_addAlignedMemory64Operands,
1576 : CVT_95_addVecListIndexedOperands,
1577 : CVT_95_addAlignedMemory16Operands,
1578 : CVT_95_addDupAlignedMemory32Operands,
1579 : CVT_95_addAlignedMemory32Operands,
1580 : CVT_95_addDupAlignedMemoryNoneOperands,
1581 : CVT_95_addAlignedMemoryNoneOperands,
1582 : CVT_95_addAlignedMemoryOperands,
1583 : CVT_95_addDupAlignedMemory64Operands,
1584 : CVT_95_addDupAlignedMemory64or128Operands,
1585 : CVT_95_addSPRRegListOperands,
1586 : CVT_95_addAddrMode5FP16Operands,
1587 : CVT_95_addNEONi32vmovOperands,
1588 : CVT_95_addNEONvmovi8ReplicateOperands,
1589 : CVT_95_addNEONvmovi16ReplicateOperands,
1590 : CVT_95_addNEONi32vmovNegOperands,
1591 : CVT_95_addNEONvmovi32ReplicateOperands,
1592 : CVT_95_addNEONi64splatOperands,
1593 : CVT_95_addNEONi8splatOperands,
1594 : CVT_95_addNEONinvi8ReplicateOperands,
1595 : CVT_imm_95_2,
1596 : CVT_imm_95_3,
1597 : CVT_NUM_CONVERTERS
1598 : };
1599 :
1600 : enum InstructionConversionKind {
1601 : Convert_NoOperands,
1602 : Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1,
1603 : Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
1604 : Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
1605 : Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
1606 : Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
1607 : Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
1608 : Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1609 : Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1610 : Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1611 : Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
1612 : Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0,
1613 : Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0,
1614 : Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0,
1615 : Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
1616 : Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0,
1617 : Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0,
1618 : Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0,
1619 : Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0,
1620 : Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0,
1621 : Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0,
1622 : Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1,
1623 : Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1,
1624 : Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1,
1625 : Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
1626 : Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0,
1627 : Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0,
1628 : Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0,
1629 : Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0,
1630 : Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0,
1631 : Convert__Reg1_1__Imm0_40951_3__CondCode2_0,
1632 : Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0,
1633 : Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0,
1634 : Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0,
1635 : Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
1636 : Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1,
1637 : Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1,
1638 : Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1,
1639 : Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
1640 : Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0,
1641 : Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0,
1642 : Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0,
1643 : Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0,
1644 : Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0,
1645 : Convert__Reg1_1__Imm1_2__CondCode2_0,
1646 : Convert__Reg1_1__AdrLabel1_2__CondCode2_0,
1647 : Convert__Reg1_2__Imm1_3__CondCode2_0,
1648 : Convert__Reg1_1__Tie0_1_1__Reg1_2,
1649 : Convert__Reg1_1__Reg1_2,
1650 : Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
1651 : Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1652 : Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1653 : Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1654 : Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
1655 : Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0,
1656 : Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1,
1657 : Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0,
1658 : Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0,
1659 : Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
1660 : Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1,
1661 : Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
1662 : Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0,
1663 : Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0,
1664 : Convert__ARMBranchTarget1_1__CondCode2_0,
1665 : ConvertCustom_cvtThumbBranches,
1666 : Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0,
1667 : Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0,
1668 : Convert__imm_95_0,
1669 : Convert__Imm0_2551_0,
1670 : Convert__Imm0_655351_0,
1671 : Convert__ARMBranchTarget1_0,
1672 : Convert__CondCode2_0__ThumbBranchTarget1_1,
1673 : Convert__Reg1_0,
1674 : Convert__ThumbBranchTarget1_0,
1675 : Convert__Reg1_1__CondCode2_0,
1676 : Convert__CondCode2_0__Reg1_1,
1677 : Convert__CondCode2_0__ARMBranchTarget1_1,
1678 : Convert__CondCode2_0,
1679 : Convert__Reg1_0__ThumbBranchTarget1_1,
1680 : Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1681 : Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1682 : Convert__Reg1_1__Reg1_2__CondCode2_0,
1683 : Convert__Reg1_1__ModImmNeg1_2__CondCode2_0,
1684 : Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0,
1685 : Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0,
1686 : Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0,
1687 : Convert__Reg1_1__T2SOImm1_2__CondCode2_0,
1688 : Convert__Reg1_1__ModImm1_2__CondCode2_0,
1689 : Convert__Reg1_2__Reg1_3__CondCode2_0,
1690 : Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0,
1691 : Convert__Reg1_2__T2SOImm1_3__CondCode2_0,
1692 : Convert__Reg1_1__Imm0_2551_2__CondCode2_0,
1693 : Convert__Imm0_311_0,
1694 : Convert__Imm0_311_1,
1695 : Convert__Imm1_0__ProcIFlags1_1,
1696 : Convert__Imm1_0__ProcIFlags1_2,
1697 : Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2,
1698 : Convert__Imm1_0__ProcIFlags1_1__Imm1_2,
1699 : Convert__Imm1_0__ProcIFlags1_2__Imm1_3,
1700 : Convert__Reg1_0__Reg1_1__Reg1_2,
1701 : Convert__imm_95_20__CondCode2_0,
1702 : Convert__Imm0_151_1__CondCode2_0,
1703 : Convert__imm_95_12,
1704 : Convert__imm_95_12__CondCode2_0,
1705 : Convert__imm_95_15,
1706 : Convert__imm_95_15__CondCode2_0,
1707 : Convert__MemBarrierOpt1_0,
1708 : Convert__MemBarrierOpt1_1__CondCode2_0,
1709 : Convert__imm_95_0__CondCode2_0,
1710 : Convert__imm_95_16__CondCode2_0,
1711 : Convert__Reg1_1__FPImm1_2__CondCode2_0,
1712 : Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3,
1713 : Convert__Reg1_1__CondCode2_0__DPRRegList1_2,
1714 : Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0,
1715 : Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0,
1716 : Convert__Imm0_2391_1__CondCode2_0,
1717 : Convert__Imm0_2391_2__CondCode2_0,
1718 : Convert__Imm0_631_0,
1719 : Convert__Imm0_655351_1,
1720 : Convert__InstSyncBarrierOpt1_0,
1721 : Convert__InstSyncBarrierOpt1_1__CondCode2_0,
1722 : Convert__ITCondCode1_1__ITMask1_0,
1723 : Convert__Reg1_1__MemNoOffset1_2__CondCode2_0,
1724 : Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0,
1725 : Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,
1726 : Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0,
1727 : Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0,
1728 : Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2,
1729 : Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3,
1730 : Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3,
1731 : Convert__Reg1_1__CondCode2_0__RegList1_2,
1732 : Convert__Reg1_2__CondCode2_0__RegList1_3,
1733 : Convert__Reg1_1__CondCode2_0__RegList1_3,
1734 : Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3,
1735 : Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4,
1736 : Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0,
1737 : Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0,
1738 : Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0,
1739 : Convert__Reg1_1__MemThumbRR2_2__CondCode2_0,
1740 : Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0,
1741 : Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0,
1742 : Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0,
1743 : Convert__Reg1_1__MemRegOffset3_2__CondCode2_0,
1744 : Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0,
1745 : Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0,
1746 : Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0,
1747 : Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0,
1748 : Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0,
1749 : Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0,
1750 : Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0,
1751 : Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0,
1752 : Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0,
1753 : Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0,
1754 : Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0,
1755 : Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0,
1756 : Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0,
1757 : Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0,
1758 : Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0,
1759 : Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
1760 : Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
1761 : Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0,
1762 : Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0,
1763 : Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0,
1764 : Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0,
1765 : Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0,
1766 : Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0,
1767 : Convert__Reg1_1__AddrMode33_2__CondCode2_0,
1768 : Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0,
1769 : Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0,
1770 : Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0,
1771 : Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0,
1772 : Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1,
1773 : Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0,
1774 : Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0,
1775 : Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
1776 : Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1,
1777 : Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
1778 : Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
1779 : Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
1780 : Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0,
1781 : Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
1782 : Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
1783 : Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1784 : Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0,
1785 : Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1786 : Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0,
1787 : Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4,
1788 : Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
1789 : Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
1790 : Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0,
1791 : Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0,
1792 : Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0,
1793 : Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0,
1794 : Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1,
1795 : Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
1796 : Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
1797 : Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
1798 : Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
1799 : Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0,
1800 : Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0,
1801 : Convert__Reg1_2__Reg1_3__CondCode2_0__reg0,
1802 : Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
1803 : Convert__Reg1_0__Reg1_1,
1804 : Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0,
1805 : Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR,
1806 : Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR,
1807 : Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR,
1808 : Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR,
1809 : Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0,
1810 : Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
1811 : Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
1812 : Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0,
1813 : Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
1814 : Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0,
1815 : Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4,
1816 : Convert__Reg1_1__BankedReg1_2__CondCode2_0,
1817 : Convert__Reg1_1__MSRMask1_2__CondCode2_0,
1818 : Convert__BankedReg1_1__Reg1_2__CondCode2_0,
1819 : Convert__MSRMask1_1__Reg1_2__CondCode2_0,
1820 : Convert__MSRMask1_1__ModImm1_2__CondCode2_0,
1821 : Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0,
1822 : ConvertCustom_cvtThumbMultiply,
1823 : Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1,
1824 : Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
1825 : Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
1826 : Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
1827 : Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0,
1828 : Convert__regR8__regR8__imm_95_14__imm_95_0,
1829 : Convert__regR0__regR0__CondCode2_0__reg0,
1830 : Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
1831 : Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0,
1832 : Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0,
1833 : Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0,
1834 : Convert__MemImm12Offset2_0,
1835 : Convert__MemRegOffset3_0,
1836 : Convert__Imm1_1__CondCode2_0,
1837 : Convert__MemNegImm8Offset2_1__CondCode2_0,
1838 : Convert__MemUImm12Offset2_1__CondCode2_0,
1839 : Convert__T2MemRegOffset3_1__CondCode2_0,
1840 : Convert__MemPCRelImm121_1__CondCode2_0,
1841 : Convert__CondCode2_0__RegList1_1,
1842 : Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1,
1843 : Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2,
1844 : Convert__imm_95_4__imm_95_14__imm_95_0,
1845 : Convert__imm_95_4,
1846 : Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
1847 : Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0,
1848 : Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0,
1849 : Convert__SetEndImm1_0,
1850 : Convert__Imm0_11_0,
1851 : Convert__imm_95_4__CondCode2_0,
1852 : Convert__imm_95_5__CondCode2_0,
1853 : Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3,
1854 : Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0,
1855 : Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0,
1856 : Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0,
1857 : Convert__Imm0_311_2,
1858 : Convert__Imm0_311_1__CondCode2_0,
1859 : Convert__Imm0_311_2__CondCode2_0,
1860 : Convert__Imm0_311_3__CondCode2_0,
1861 : Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0,
1862 : Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0,
1863 : Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0,
1864 : Convert__imm_95_0__imm_95_14__imm_95_0,
1865 : Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0,
1866 : Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0,
1867 : Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0,
1868 : Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0,
1869 : Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0,
1870 : Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0,
1871 : Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0,
1872 : Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0,
1873 : Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
1874 : Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0,
1875 : Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
1876 : Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0,
1877 : Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0,
1878 : Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0,
1879 : Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0,
1880 : Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0,
1881 : Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0,
1882 : Convert__Imm0_2551_3__CondCode2_0,
1883 : Convert__Imm0_2551_1__CondCode2_0,
1884 : Convert__Imm24bit1_1__CondCode2_0,
1885 : Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
1886 : Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0,
1887 : Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
1888 : Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0,
1889 : Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
1890 : Convert__MemTBB2_1__CondCode2_0,
1891 : Convert__MemTBH2_1__CondCode2_0,
1892 : Convert__TraceSyncBarrierOpt1_0,
1893 : Convert__TraceSyncBarrierOpt1_1__CondCode2_0,
1894 : Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0,
1895 : Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0,
1896 : Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0,
1897 : Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0,
1898 : Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0,
1899 : Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
1900 : Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0,
1901 : Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0,
1902 : Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0,
1903 : Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0,
1904 : Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0,
1905 : Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0,
1906 : Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0,
1907 : Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0,
1908 : Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0,
1909 : Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4,
1910 : Convert__Reg1_2__Reg1_2__CondCode2_0,
1911 : Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4,
1912 : Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5,
1913 : Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5,
1914 : Convert__Reg1_2__CondCode2_0,
1915 : Convert__Reg1_3__Reg1_4__CondCode2_0,
1916 : Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0,
1917 : Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0,
1918 : Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0,
1919 : Convert__Reg1_2__Reg1_3,
1920 : Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
1921 : Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
1922 : Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0,
1923 : Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0,
1924 : Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0,
1925 : Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0,
1926 : Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0,
1927 : Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0,
1928 : Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0,
1929 : Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0,
1930 : Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0,
1931 : Convert__Reg1_1__Reg1_2__Reg1_3,
1932 : Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4,
1933 : Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4,
1934 : Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1935 : Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0,
1936 : Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0,
1937 : Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1938 : Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0,
1939 : Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0,
1940 : Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0,
1941 : Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1942 : Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1943 : Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1944 : Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1945 : Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1946 : Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
1947 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1948 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1949 : Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
1950 : Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
1951 : Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0,
1952 : Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
1953 : Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1954 : Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1955 : Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
1956 : Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
1957 : Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
1958 : Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
1959 : Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
1960 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1961 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1962 : Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1963 : Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1964 : Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1965 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
1966 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1967 : Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
1968 : Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1969 : Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
1970 : Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0,
1971 : Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
1972 : Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
1973 : Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
1974 : Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0,
1975 : Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1976 : Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
1977 : Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
1978 : Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
1979 : Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
1980 : Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
1981 : Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
1982 : Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0,
1983 : Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
1984 : Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
1985 : Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
1986 : Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
1987 : Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1988 : Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
1989 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
1990 : Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
1991 : Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
1992 : Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
1993 : Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
1994 : Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
1995 : Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
1996 : Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
1997 : Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
1998 : Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
1999 : Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2000 : Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2001 : Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0,
2002 : Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2003 : Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2004 : Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2005 : Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2006 : Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2007 : Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2008 : Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2009 : Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2010 : Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2011 : Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2012 : Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2013 : Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2014 : Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2015 : Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0,
2016 : Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0,
2017 : Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0,
2018 : Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0,
2019 : Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2020 : Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2021 : Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2022 : Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2023 : Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2024 : Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2025 : Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2026 : Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2027 : Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2028 : Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2029 : Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0,
2030 : Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2031 : Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2032 : Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2033 : Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2034 : Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2035 : Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2036 : Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2037 : Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2038 : Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2039 : Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2040 : Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2041 : Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2042 : Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2043 : Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2044 : Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0,
2045 : Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0,
2046 : Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0,
2047 : Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0,
2048 : Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3,
2049 : Convert__Reg1_1__CondCode2_0__SPRRegList1_2,
2050 : Convert__Reg1_1__AddrMode52_2__CondCode2_0,
2051 : Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0,
2052 : Convert__Reg1_2__AddrMode52_3__CondCode2_0,
2053 : Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2054 : Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2055 : Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0,
2056 : Convert__Reg1_2__FPImm1_3__CondCode2_0,
2057 : Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0,
2058 : Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0,
2059 : Convert__Reg1_2__NEONi16splat1_3__CondCode2_0,
2060 : Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0,
2061 : Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0,
2062 : Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0,
2063 : Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0,
2064 : Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0,
2065 : Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0,
2066 : Convert__Reg1_2__NEONi64splat1_3__CondCode2_0,
2067 : Convert__Reg1_2__NEONi8splat1_3__CondCode2_0,
2068 : Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0,
2069 : Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0,
2070 : Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0,
2071 : Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0,
2072 : Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2073 : Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2074 : Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2075 : Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2076 : Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0,
2077 : Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0,
2078 : Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0,
2079 : Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0,
2080 : Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1,
2081 : Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1,
2082 : Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2,
2083 : Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2,
2084 : Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0,
2085 : Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0,
2086 : Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0,
2087 : Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0,
2088 : Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0,
2089 : Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0,
2090 : Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0,
2091 : Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0,
2092 : Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0,
2093 : Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0,
2094 : Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,
2095 : Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,
2096 : Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,
2097 : Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0,
2098 : Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0,
2099 : Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0,
2100 : Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0,
2101 : Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0,
2102 : Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3,
2103 : Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4,
2104 : Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0,
2105 : Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0,
2106 : Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0,
2107 : Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0,
2108 : Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0,
2109 : Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0,
2110 : Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0,
2111 : Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0,
2112 : Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2113 : Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2114 : Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
2115 : Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
2116 : Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
2117 : Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0,
2118 : Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
2119 : Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0,
2120 : Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
2121 : Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0,
2122 : Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
2123 : Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0,
2124 : Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0,
2125 : Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
2126 : Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
2127 : Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0,
2128 : Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
2129 : Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
2130 : Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0,
2131 : Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
2132 : Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
2133 : Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
2134 : Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
2135 : Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0,
2136 : Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0,
2137 : Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0,
2138 : Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0,
2139 : Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0,
2140 : Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0,
2141 : Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0,
2142 : Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0,
2143 : Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0,
2144 : Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0,
2145 : Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0,
2146 : Convert__imm_95_2__CondCode2_0,
2147 : Convert__imm_95_3__CondCode2_0,
2148 : Convert__imm_95_1__CondCode2_0,
2149 : CVT_NUM_SIGNATURES
2150 : };
2151 :
2152 : } // end anonymous namespace
2153 :
2154 : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
2155 : // Convert_NoOperands
2156 : { CVT_Done },
2157 : // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1
2158 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2159 : // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
2160 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2161 : // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
2162 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2163 : // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
2164 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2165 : // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
2166 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2167 : // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
2168 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2169 : // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2170 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2171 : // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2172 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2173 : // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2174 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2175 : // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
2176 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2177 : // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0
2178 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2179 : // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0
2180 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2181 : // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0
2182 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2183 : // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
2184 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2185 : // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0
2186 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2187 : // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0
2188 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2189 : // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0
2190 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2191 : // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0
2192 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2193 : // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0
2194 : { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2195 : // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0
2196 : { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2197 : // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1
2198 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2199 : // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1
2200 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2201 : // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1
2202 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2203 : // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
2204 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2205 : // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0
2206 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2207 : // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0
2208 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2209 : // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0
2210 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2211 : // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0
2212 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2213 : // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0
2214 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2215 : // Convert__Reg1_1__Imm0_40951_3__CondCode2_0
2216 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2217 : // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0
2218 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2219 : // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0
2220 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2221 : // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0
2222 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2223 : // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
2224 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2225 : // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1
2226 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2227 : // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1
2228 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2229 : // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1
2230 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2231 : // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
2232 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2233 : // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0
2234 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2235 : // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0
2236 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2237 : // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0
2238 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2239 : // Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0
2240 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2241 : // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0
2242 : { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2243 : // Convert__Reg1_1__Imm1_2__CondCode2_0
2244 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2245 : // Convert__Reg1_1__AdrLabel1_2__CondCode2_0
2246 : { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2247 : // Convert__Reg1_2__Imm1_3__CondCode2_0
2248 : { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2249 : // Convert__Reg1_1__Tie0_1_1__Reg1_2
2250 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done },
2251 : // Convert__Reg1_1__Reg1_2
2252 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2253 : // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
2254 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2255 : // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2256 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2257 : // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2258 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2259 : // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2260 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2261 : // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
2262 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2263 : // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0
2264 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2265 : // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1
2266 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2267 : // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0
2268 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2269 : // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0
2270 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2271 : // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
2272 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2273 : // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1
2274 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2275 : // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
2276 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2277 : // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0
2278 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2279 : // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0
2280 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2281 : // Convert__ARMBranchTarget1_1__CondCode2_0
2282 : { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2283 : // ConvertCustom_cvtThumbBranches
2284 : { CVT_cvtThumbBranches, 0, CVT_Done },
2285 : // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0
2286 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2287 : // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0
2288 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2289 : // Convert__imm_95_0
2290 : { CVT_imm_95_0, 0, CVT_Done },
2291 : // Convert__Imm0_2551_0
2292 : { CVT_95_addImmOperands, 1, CVT_Done },
2293 : // Convert__Imm0_655351_0
2294 : { CVT_95_addImmOperands, 1, CVT_Done },
2295 : // Convert__ARMBranchTarget1_0
2296 : { CVT_95_addARMBranchTargetOperands, 1, CVT_Done },
2297 : // Convert__CondCode2_0__ThumbBranchTarget1_1
2298 : { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
2299 : // Convert__Reg1_0
2300 : { CVT_95_Reg, 1, CVT_Done },
2301 : // Convert__ThumbBranchTarget1_0
2302 : { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done },
2303 : // Convert__Reg1_1__CondCode2_0
2304 : { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2305 : // Convert__CondCode2_0__Reg1_1
2306 : { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_Done },
2307 : // Convert__CondCode2_0__ARMBranchTarget1_1
2308 : { CVT_95_addCondCodeOperands, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done },
2309 : // Convert__CondCode2_0
2310 : { CVT_95_addCondCodeOperands, 1, CVT_Done },
2311 : // Convert__Reg1_0__ThumbBranchTarget1_1
2312 : { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
2313 : // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2314 : { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2315 : // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2316 : { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2317 : // Convert__Reg1_1__Reg1_2__CondCode2_0
2318 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2319 : // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0
2320 : { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2321 : // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0
2322 : { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2323 : // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0
2324 : { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2325 : // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0
2326 : { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2327 : // Convert__Reg1_1__T2SOImm1_2__CondCode2_0
2328 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2329 : // Convert__Reg1_1__ModImm1_2__CondCode2_0
2330 : { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2331 : // Convert__Reg1_2__Reg1_3__CondCode2_0
2332 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2333 : // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0
2334 : { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2335 : // Convert__Reg1_2__T2SOImm1_3__CondCode2_0
2336 : { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2337 : // Convert__Reg1_1__Imm0_2551_2__CondCode2_0
2338 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2339 : // Convert__Imm0_311_0
2340 : { CVT_95_addImmOperands, 1, CVT_Done },
2341 : // Convert__Imm0_311_1
2342 : { CVT_95_addImmOperands, 2, CVT_Done },
2343 : // Convert__Imm1_0__ProcIFlags1_1
2344 : { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done },
2345 : // Convert__Imm1_0__ProcIFlags1_2
2346 : { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done },
2347 : // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2
2348 : { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2349 : // Convert__Imm1_0__ProcIFlags1_1__Imm1_2
2350 : { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
2351 : // Convert__Imm1_0__ProcIFlags1_2__Imm1_3
2352 : { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
2353 : // Convert__Reg1_0__Reg1_1__Reg1_2
2354 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
2355 : // Convert__imm_95_20__CondCode2_0
2356 : { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2357 : // Convert__Imm0_151_1__CondCode2_0
2358 : { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2359 : // Convert__imm_95_12
2360 : { CVT_imm_95_12, 0, CVT_Done },
2361 : // Convert__imm_95_12__CondCode2_0
2362 : { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2363 : // Convert__imm_95_15
2364 : { CVT_imm_95_15, 0, CVT_Done },
2365 : // Convert__imm_95_15__CondCode2_0
2366 : { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2367 : // Convert__MemBarrierOpt1_0
2368 : { CVT_95_addMemBarrierOptOperands, 1, CVT_Done },
2369 : // Convert__MemBarrierOpt1_1__CondCode2_0
2370 : { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2371 : // Convert__imm_95_0__CondCode2_0
2372 : { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2373 : // Convert__imm_95_16__CondCode2_0
2374 : { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2375 : // Convert__Reg1_1__FPImm1_2__CondCode2_0
2376 : { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2377 : // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3
2378 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done },
2379 : // Convert__Reg1_1__CondCode2_0__DPRRegList1_2
2380 : { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
2381 : // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0
2382 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2383 : // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0
2384 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2385 : // Convert__Imm0_2391_1__CondCode2_0
2386 : { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2387 : // Convert__Imm0_2391_2__CondCode2_0
2388 : { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2389 : // Convert__Imm0_631_0
2390 : { CVT_95_addImmOperands, 1, CVT_Done },
2391 : // Convert__Imm0_655351_1
2392 : { CVT_95_addImmOperands, 2, CVT_Done },
2393 : // Convert__InstSyncBarrierOpt1_0
2394 : { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done },
2395 : // Convert__InstSyncBarrierOpt1_1__CondCode2_0
2396 : { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2397 : // Convert__ITCondCode1_1__ITMask1_0
2398 : { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done },
2399 : // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0
2400 : { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2401 : // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0
2402 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2403 : // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0
2404 : { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2405 : // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0
2406 : { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2407 : // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0
2408 : { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2409 : // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2
2410 : { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done },
2411 : // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3
2412 : { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done },
2413 : // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3
2414 : { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done },
2415 : // Convert__Reg1_1__CondCode2_0__RegList1_2
2416 : { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
2417 : // Convert__Reg1_2__CondCode2_0__RegList1_3
2418 : { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2419 : // Convert__Reg1_1__CondCode2_0__RegList1_3
2420 : { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2421 : // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3
2422 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done },
2423 : // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4
2424 : { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 5, CVT_Done },
2425 : // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0
2426 : { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2427 : // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0
2428 : { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2429 : // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0
2430 : { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2431 : // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0
2432 : { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2433 : // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0
2434 : { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2435 : // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0
2436 : { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2437 : // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0
2438 : { CVT_95_Reg, 2, CVT_95_addMemNegImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2439 : // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0
2440 : { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2441 : // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0
2442 : { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2443 : // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0
2444 : { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2445 : // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0
2446 : { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2447 : // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0
2448 : { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2449 : // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0
2450 : { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2451 : // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0
2452 : { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2453 : // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0
2454 : { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2455 : // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0
2456 : { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2457 : // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0
2458 : { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2459 : // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0
2460 : { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2461 : // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0
2462 : { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2463 : // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0
2464 : { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2465 : // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0
2466 : { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2467 : // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0
2468 : { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2469 : // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0
2470 : { CVT_95_Reg, 2, CVT_95_addMemPosImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2471 : // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
2472 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2473 : // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
2474 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2475 : // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0
2476 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2477 : // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0
2478 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2479 : // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0
2480 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2481 : // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0
2482 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2483 : // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0
2484 : { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2485 : // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0
2486 : { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2487 : // Convert__Reg1_1__AddrMode33_2__CondCode2_0
2488 : { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2489 : // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0
2490 : { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2491 : // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0
2492 : { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2493 : // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0
2494 : { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2495 : // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0
2496 : { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2497 : // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1
2498 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2499 : // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0
2500 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2501 : // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0
2502 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2503 : // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
2504 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2505 : // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1
2506 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done },
2507 : // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
2508 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2509 : // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
2510 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2511 : // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
2512 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2513 : // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0
2514 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2515 : // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
2516 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2517 : // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
2518 : { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2519 : // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2520 : { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2521 : // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0
2522 : { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
2523 : // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2524 : { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2525 : // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0
2526 : { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2527 : // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4
2528 : { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done },
2529 : // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
2530 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2531 : // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
2532 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2533 : // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0
2534 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2535 : // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0
2536 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2537 : // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0
2538 : { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2539 : // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0
2540 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2541 : // Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1
2542 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2543 : // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
2544 : { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2545 : // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
2546 : { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2547 : // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
2548 : { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2549 : // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
2550 : { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2551 : // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0
2552 : { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2553 : // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0
2554 : { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2555 : // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0
2556 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2557 : // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
2558 : { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2559 : // Convert__Reg1_0__Reg1_1
2560 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
2561 : // Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0
2562 : { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2563 : // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR
2564 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2565 : // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR
2566 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2567 : // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR
2568 : { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2569 : // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR
2570 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done },
2571 : // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0
2572 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2573 : // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
2574 : { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2575 : // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
2576 : { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
2577 : // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0
2578 : { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
2579 : // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
2580 : { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
2581 : // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0
2582 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2583 : // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4
2584 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done },
2585 : // Convert__Reg1_1__BankedReg1_2__CondCode2_0
2586 : { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2587 : // Convert__Reg1_1__MSRMask1_2__CondCode2_0
2588 : { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2589 : // Convert__BankedReg1_1__Reg1_2__CondCode2_0
2590 : { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2591 : // Convert__MSRMask1_1__Reg1_2__CondCode2_0
2592 : { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2593 : // Convert__MSRMask1_1__ModImm1_2__CondCode2_0
2594 : { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2595 : // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0
2596 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2597 : // ConvertCustom_cvtThumbMultiply
2598 : { CVT_cvtThumbMultiply, 0, CVT_Done },
2599 : // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1
2600 : { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done },
2601 : // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
2602 : { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2603 : // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
2604 : { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2605 : // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
2606 : { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2607 : // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0
2608 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2609 : // Convert__regR8__regR8__imm_95_14__imm_95_0
2610 : { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2611 : // Convert__regR0__regR0__CondCode2_0__reg0
2612 : { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done },
2613 : // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
2614 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2615 : // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0
2616 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2617 : // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0
2618 : { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2619 : // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0
2620 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2621 : // Convert__MemImm12Offset2_0
2622 : { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done },
2623 : // Convert__MemRegOffset3_0
2624 : { CVT_95_addMemRegOffsetOperands, 1, CVT_Done },
2625 : // Convert__Imm1_1__CondCode2_0
2626 : { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2627 : // Convert__MemNegImm8Offset2_1__CondCode2_0
2628 : { CVT_95_addMemNegImm8OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2629 : // Convert__MemUImm12Offset2_1__CondCode2_0
2630 : { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2631 : // Convert__T2MemRegOffset3_1__CondCode2_0
2632 : { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2633 : // Convert__MemPCRelImm121_1__CondCode2_0
2634 : { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2635 : // Convert__CondCode2_0__RegList1_1
2636 : { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
2637 : // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1
2638 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done },
2639 : // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2
2640 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done },
2641 : // Convert__imm_95_4__imm_95_14__imm_95_0
2642 : { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2643 : // Convert__imm_95_4
2644 : { CVT_imm_95_4, 0, CVT_Done },
2645 : // Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
2646 : { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2647 : // Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0
2648 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2649 : // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0
2650 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2651 : // Convert__SetEndImm1_0
2652 : { CVT_95_addImmOperands, 1, CVT_Done },
2653 : // Convert__Imm0_11_0
2654 : { CVT_95_addImmOperands, 1, CVT_Done },
2655 : // Convert__imm_95_4__CondCode2_0
2656 : { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2657 : // Convert__imm_95_5__CondCode2_0
2658 : { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2659 : // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3
2660 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2661 : // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0
2662 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2663 : // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0
2664 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2665 : // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0
2666 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done },
2667 : // Convert__Imm0_311_2
2668 : { CVT_95_addImmOperands, 3, CVT_Done },
2669 : // Convert__Imm0_311_1__CondCode2_0
2670 : { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2671 : // Convert__Imm0_311_2__CondCode2_0
2672 : { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2673 : // Convert__Imm0_311_3__CondCode2_0
2674 : { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2675 : // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0
2676 : { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2677 : // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0
2678 : { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2679 : // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0
2680 : { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2681 : // Convert__imm_95_0__imm_95_14__imm_95_0
2682 : { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done },
2683 : // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0
2684 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2685 : // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0
2686 : { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2687 : // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0
2688 : { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2689 : // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0
2690 : { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2691 : // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0
2692 : { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2693 : // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0
2694 : { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2695 : // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0
2696 : { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2697 : // Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0
2698 : { CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2699 : // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
2700 : { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2701 : // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0
2702 : { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2703 : // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
2704 : { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2705 : // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0
2706 : { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2707 : // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0
2708 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2709 : // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0
2710 : { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2711 : // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0
2712 : { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2713 : // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0
2714 : { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2715 : // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0
2716 : { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2717 : // Convert__Imm0_2551_3__CondCode2_0
2718 : { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2719 : // Convert__Imm0_2551_1__CondCode2_0
2720 : { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2721 : // Convert__Imm24bit1_1__CondCode2_0
2722 : { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2723 : // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
2724 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2725 : // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0
2726 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2727 : // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
2728 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2729 : // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0
2730 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2731 : // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
2732 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2733 : // Convert__MemTBB2_1__CondCode2_0
2734 : { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2735 : // Convert__MemTBH2_1__CondCode2_0
2736 : { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2737 : // Convert__TraceSyncBarrierOpt1_0
2738 : { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done },
2739 : // Convert__TraceSyncBarrierOpt1_1__CondCode2_0
2740 : { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done },
2741 : // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0
2742 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
2743 : // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0
2744 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2745 : // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0
2746 : { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2747 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0
2748 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2749 : // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0
2750 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2751 : // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
2752 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2753 : // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0
2754 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2755 : // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0
2756 : { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2757 : // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0
2758 : { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2759 : // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0
2760 : { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2761 : // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0
2762 : { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2763 : // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0
2764 : { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2765 : // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0
2766 : { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
2767 : // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0
2768 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2769 : // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0
2770 : { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2771 : // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4
2772 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
2773 : // Convert__Reg1_2__Reg1_2__CondCode2_0
2774 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2775 : // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4
2776 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
2777 : // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5
2778 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
2779 : // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5
2780 : { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
2781 : // Convert__Reg1_2__CondCode2_0
2782 : { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
2783 : // Convert__Reg1_3__Reg1_4__CondCode2_0
2784 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2785 : // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0
2786 : { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2787 : // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0
2788 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2789 : // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0
2790 : { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2791 : // Convert__Reg1_2__Reg1_3
2792 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2793 : // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
2794 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2795 : // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
2796 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2797 : // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0
2798 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2799 : // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0
2800 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2801 : // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0
2802 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2803 : // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0
2804 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2805 : // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0
2806 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2807 : // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0
2808 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2809 : // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0
2810 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2811 : // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0
2812 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2813 : // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0
2814 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2815 : // Convert__Reg1_1__Reg1_2__Reg1_3
2816 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
2817 : // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4
2818 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
2819 : // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4
2820 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
2821 : // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2822 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2823 : // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0
2824 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2825 : // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0
2826 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2827 : // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2828 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2829 : // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0
2830 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2831 : // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0
2832 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2833 : // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0
2834 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2835 : // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2836 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2837 : // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2838 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2839 : // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2840 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2841 : // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2842 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2843 : // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2844 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2845 : // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2846 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2847 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2848 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2849 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2850 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2851 : // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
2852 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2853 : // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
2854 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2855 : // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0
2856 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2857 : // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
2858 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2859 : // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2860 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2861 : // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2862 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2863 : // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
2864 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2865 : // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
2866 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2867 : // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
2868 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2869 : // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
2870 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2871 : // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
2872 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2873 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2874 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2875 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2876 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2877 : // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2878 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2879 : // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2880 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2881 : // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2882 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2883 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
2884 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2885 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2886 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2887 : // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
2888 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2889 : // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2890 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2891 : // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2892 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2893 : // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0
2894 : { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2895 : // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
2896 : { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2897 : // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
2898 : { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
2899 : // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
2900 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2901 : // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0
2902 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2903 : // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2904 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2905 : // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
2906 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2907 : // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2908 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2909 : // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2910 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2911 : // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2912 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2913 : // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2914 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2915 : // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
2916 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2917 : // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0
2918 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2919 : // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
2920 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2921 : // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
2922 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2923 : // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
2924 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2925 : // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
2926 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2927 : // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2928 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2929 : // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
2930 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2931 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
2932 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2933 : // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
2934 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2935 : // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
2936 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2937 : // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
2938 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2939 : // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2940 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2941 : // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2942 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2943 : // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
2944 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2945 : // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
2946 : { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2947 : // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
2948 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2949 : // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2950 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2951 : // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2952 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2953 : // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
2954 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2955 : // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0
2956 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2957 : // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2958 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2959 : // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2960 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2961 : // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2962 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2963 : // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
2964 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2965 : // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2966 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2967 : // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2968 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2969 : // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2970 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2971 : // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
2972 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2973 : // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
2974 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2975 : // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2976 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2977 : // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2978 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2979 : // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2980 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2981 : // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
2982 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
2983 : // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0
2984 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands, 1, CVT_Done },
2985 : // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0
2986 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
2987 : // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0
2988 : { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands, 1, CVT_Done },
2989 : // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0
2990 : { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands, 1, CVT_Done },
2991 : // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2992 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2993 : // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
2994 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2995 : // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
2996 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2997 : // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0
2998 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
2999 : // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3000 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3001 : // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
3002 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3003 : // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
3004 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3005 : // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
3006 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3007 : // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
3008 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3009 : // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3010 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3011 : // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0
3012 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3013 : // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3014 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3015 : // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3016 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3017 : // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3018 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3019 : // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3020 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3021 : // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3022 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3023 : // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3024 : { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3025 : // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3026 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3027 : // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
3028 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3029 : // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3030 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3031 : // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
3032 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3033 : // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3034 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3035 : // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3036 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3037 : // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3038 : { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3039 : // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3040 : { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3041 : // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0
3042 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done },
3043 : // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0
3044 : { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands, 1, CVT_Done },
3045 : // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0
3046 : { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands, 1, CVT_Done },
3047 : // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0
3048 : { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands, 1, CVT_Done },
3049 : // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3
3050 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done },
3051 : // Convert__Reg1_1__CondCode2_0__SPRRegList1_2
3052 : { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
3053 : // Convert__Reg1_1__AddrMode52_2__CondCode2_0
3054 : { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3055 : // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0
3056 : { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3057 : // Convert__Reg1_2__AddrMode52_3__CondCode2_0
3058 : { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3059 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
3060 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3061 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
3062 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3063 : // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0
3064 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3065 : // Convert__Reg1_2__FPImm1_3__CondCode2_0
3066 : { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3067 : // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0
3068 : { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3069 : // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0
3070 : { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3071 : // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0
3072 : { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3073 : // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0
3074 : { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3075 : // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0
3076 : { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3077 : // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0
3078 : { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3079 : // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0
3080 : { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3081 : // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0
3082 : { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3083 : // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0
3084 : { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3085 : // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0
3086 : { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3087 : // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0
3088 : { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3089 : // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0
3090 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3091 : // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0
3092 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3093 : // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0
3094 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3095 : // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0
3096 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3097 : // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
3098 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3099 : // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
3100 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3101 : // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
3102 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3103 : // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
3104 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3105 : // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0
3106 : { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3107 : // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0
3108 : { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3109 : // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0
3110 : { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3111 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0
3112 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3113 : // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1
3114 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done },
3115 : // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1
3116 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done },
3117 : // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2
3118 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
3119 : // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2
3120 : { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
3121 : // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0
3122 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3123 : // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0
3124 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3125 : // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0
3126 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3127 : // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0
3128 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3129 : // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0
3130 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3131 : // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0
3132 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3133 : // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0
3134 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3135 : // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0
3136 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3137 : // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0
3138 : { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3139 : // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0
3140 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3141 : // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0
3142 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3143 : // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0
3144 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3145 : // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0
3146 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3147 : // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0
3148 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3149 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0
3150 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3151 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0
3152 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3153 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0
3154 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3155 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0
3156 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3157 : // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3
3158 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3159 : // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4
3160 : { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3161 : // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0
3162 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3163 : // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0
3164 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3165 : // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0
3166 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3167 : // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0
3168 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3169 : // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0
3170 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3171 : // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0
3172 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3173 : // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0
3174 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3175 : // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0
3176 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3177 : // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
3178 : { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3179 : // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
3180 : { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3181 : // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
3182 : { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3183 : // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
3184 : { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3185 : // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
3186 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3187 : // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0
3188 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3189 : // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
3190 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3191 : // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0
3192 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3193 : // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
3194 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3195 : // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0
3196 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3197 : // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
3198 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3199 : // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0
3200 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3201 : // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0
3202 : { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3203 : // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
3204 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3205 : // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
3206 : { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3207 : // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0
3208 : { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3209 : // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
3210 : { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3211 : // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
3212 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3213 : // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0
3214 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
3215 : // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
3216 : { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3217 : // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
3218 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done },
3219 : // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
3220 : { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
3221 : // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
3222 : { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done },
3223 : // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0
3224 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
3225 : // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0
3226 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 1, CVT_Done },
3227 : // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0
3228 : { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3229 : // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0
3230 : { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3231 : // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0
3232 : { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3233 : // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0
3234 : { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3235 : // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0
3236 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3237 : // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0
3238 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3239 : // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0
3240 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3241 : // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0
3242 : { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done },
3243 : // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0
3244 : { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done },
3245 : // Convert__imm_95_2__CondCode2_0
3246 : { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3247 : // Convert__imm_95_3__CondCode2_0
3248 : { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3249 : // Convert__imm_95_1__CondCode2_0
3250 : { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done },
3251 : };
3252 :
3253 31027 : void ARMAsmParser::
3254 : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
3255 : const OperandVector &Operands) {
3256 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3257 31027 : const uint8_t *Converter = ConversionTable[Kind];
3258 : unsigned OpIdx;
3259 : Inst.setOpcode(Opcode);
3260 134370 : for (const uint8_t *p = Converter; *p; p+= 2) {
3261 103343 : OpIdx = *(p + 1);
3262 103343 : switch (*p) {
3263 0 : default: llvm_unreachable("invalid conversion entry!");
3264 0 : case CVT_Reg:
3265 0 : static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
3266 : break;
3267 3087 : case CVT_Tied: {
3268 : assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
3269 : std::begin(TiedAsmOperandTable)) &&
3270 : "Tied operand not found");
3271 3087 : unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
3272 3087 : if (TiedResOpnd != (uint8_t) -1)
3273 : Inst.addOperand(Inst.getOperand(TiedResOpnd));
3274 : break;
3275 : }
3276 37697 : case CVT_95_Reg:
3277 75394 : static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
3278 : break;
3279 5169 : case CVT_95_addCCOutOperands:
3280 10338 : static_cast<ARMOperand&>(*Operands[OpIdx]).addCCOutOperands(Inst, 1);
3281 : break;
3282 22585 : case CVT_95_addCondCodeOperands:
3283 45170 : static_cast<ARMOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2);
3284 22585 : break;
3285 241 : case CVT_95_addRegShiftedRegOperands:
3286 482 : static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3);
3287 241 : break;
3288 1096 : case CVT_95_addModImmOperands:
3289 2192 : static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmOperands(Inst, 1);
3290 1096 : break;
3291 49 : case CVT_95_addModImmNotOperands:
3292 98 : static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1);
3293 49 : break;
3294 926 : case CVT_95_addRegShiftedImmOperands:
3295 1852 : static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2);
3296 926 : break;
3297 4117 : case CVT_95_addImmOperands:
3298 4117 : static_cast<ARMOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
3299 : break;
3300 69 : case CVT_95_addT2SOImmNotOperands:
3301 138 : static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1);
3302 69 : break;
3303 35 : case CVT_95_addImm0_95_508s4Operands:
3304 70 : static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1);
3305 35 : break;
3306 : case CVT_regSP:
3307 303 : Inst.addOperand(MCOperand::createReg(ARM::SP));
3308 303 : break;
3309 6 : case CVT_95_addImm0_95_508s4NegOperands:
3310 12 : static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1);
3311 6 : break;
3312 18 : case CVT_95_addImm0_95_4095NegOperands:
3313 36 : static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1);
3314 18 : break;
3315 4 : case CVT_95_addThumbModImmNeg8_95_255Operands:
3316 8 : static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1);
3317 4 : break;
3318 67 : case CVT_95_addT2SOImmNegOperands:
3319 134 : static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1);
3320 67 : break;
3321 36 : case CVT_95_addModImmNegOperands:
3322 72 : static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1);
3323 36 : break;
3324 14 : case CVT_95_addImm0_95_1020s4Operands:
3325 28 : static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1);
3326 14 : break;
3327 4 : case CVT_95_addThumbModImmNeg1_95_7Operands:
3328 8 : static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1);
3329 4 : break;
3330 29 : case CVT_95_addUnsignedOffset_95_b8s2Operands:
3331 58 : static_cast<ARMOperand&>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1);
3332 29 : break;
3333 26 : case CVT_95_addAdrLabelOperands:
3334 52 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
3335 26 : break;
3336 563 : case CVT_95_addARMBranchTargetOperands:
3337 563 : static_cast<ARMOperand&>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1);
3338 : break;
3339 383 : case CVT_cvtThumbBranches:
3340 383 : cvtThumbBranches(Inst, Operands);
3341 383 : break;
3342 45 : case CVT_95_addBitfieldOperands:
3343 90 : static_cast<ARMOperand&>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1);
3344 45 : break;
3345 : case CVT_imm_95_0:
3346 1383 : Inst.addOperand(MCOperand::createImm(0));
3347 1383 : break;
3348 253 : case CVT_95_addThumbBranchTargetOperands:
3349 253 : static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1);
3350 : break;
3351 1400 : case CVT_95_addCoprocNumOperands:
3352 1400 : static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1);
3353 : break;
3354 1521 : case CVT_95_addCoprocRegOperands:
3355 1521 : static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1);
3356 : break;
3357 71 : case CVT_95_addProcIFlagsOperands:
3358 71 : static_cast<ARMOperand&>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1);
3359 : break;
3360 : case CVT_imm_95_20:
3361 8 : Inst.addOperand(MCOperand::createImm(20));
3362 8 : break;
3363 : case CVT_imm_95_12:
3364 4 : Inst.addOperand(MCOperand::createImm(12));
3365 4 : break;
3366 : case CVT_imm_95_15:
3367 29 : Inst.addOperand(MCOperand::createImm(15));
3368 29 : break;
3369 256 : case CVT_95_addMemBarrierOptOperands:
3370 256 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1);
3371 : break;
3372 : case CVT_imm_95_16:
3373 3 : Inst.addOperand(MCOperand::createImm(16));
3374 3 : break;
3375 37 : case CVT_95_addFPImmOperands:
3376 74 : static_cast<ARMOperand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
3377 37 : break;
3378 67 : case CVT_95_addDPRRegListOperands:
3379 67 : static_cast<ARMOperand&>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1);
3380 : break;
3381 : case CVT_imm_95_1:
3382 34 : Inst.addOperand(MCOperand::createImm(1));
3383 34 : break;
3384 18 : case CVT_95_addInstSyncBarrierOptOperands:
3385 18 : static_cast<ARMOperand&>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1);
3386 : break;
3387 5514 : case CVT_95_addITCondCodeOperands:
3388 5514 : static_cast<ARMOperand&>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1);
3389 : break;
3390 5514 : case CVT_95_addITMaskOperands:
3391 5514 : static_cast<ARMOperand&>(*Operands[OpIdx]).addITMaskOperands(Inst, 1);
3392 : break;
3393 1066 : case CVT_95_addMemNoOffsetOperands:
3394 2132 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1);
3395 : break;
3396 745 : case CVT_95_addAddrMode5Operands:
3397 1490 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2);
3398 745 : break;
3399 142 : case CVT_95_addCoprocOptionOperands:
3400 284 : static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1);
3401 : break;
3402 352 : case CVT_95_addPostIdxImm8s4Operands:
3403 704 : static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1);
3404 352 : break;
3405 941 : case CVT_95_addRegListOperands:
3406 1882 : static_cast<ARMOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
3407 941 : break;
3408 50 : case CVT_95_addThumbMemPCOperands:
3409 100 : static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1);
3410 50 : break;
3411 549 : case CVT_95_addConstPoolAsmImmOperands:
3412 549 : static_cast<ARMOperand&>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1);
3413 : break;
3414 41 : case CVT_95_addMemThumbRIs4Operands:
3415 82 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2);
3416 41 : break;
3417 39 : case CVT_95_addMemThumbRROperands:
3418 78 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2);
3419 39 : break;
3420 31 : case CVT_95_addMemThumbSPIOperands:
3421 62 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2);
3422 31 : break;
3423 150 : case CVT_95_addMemImm12OffsetOperands:
3424 300 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2);
3425 150 : break;
3426 38 : case CVT_95_addMemNegImm8OffsetOperands:
3427 38 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNegImm8OffsetOperands(Inst, 2);
3428 : break;
3429 90 : case CVT_95_addMemRegOffsetOperands:
3430 180 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3);
3431 90 : break;
3432 276 : case CVT_95_addMemUImm12OffsetOperands:
3433 552 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2);
3434 276 : break;
3435 257 : case CVT_95_addT2MemRegOffsetOperands:
3436 514 : static_cast<ARMOperand&>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3);
3437 257 : break;
3438 53 : case CVT_95_addMemPCRelImm12Operands:
3439 106 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1);
3440 : break;
3441 103 : case CVT_95_addMemImm8OffsetOperands:
3442 206 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8OffsetOperands(Inst, 2);
3443 103 : break;
3444 43 : case CVT_95_addAM2OffsetImmOperands:
3445 86 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2);
3446 43 : break;
3447 36 : case CVT_95_addPostIdxRegShiftedOperands:
3448 72 : static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2);
3449 36 : break;
3450 23 : case CVT_95_addMemThumbRIs1Operands:
3451 46 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2);
3452 23 : break;
3453 42 : case CVT_95_addMemPosImm8OffsetOperands:
3454 42 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPosImm8OffsetOperands(Inst, 2);
3455 : break;
3456 145 : case CVT_95_addMemImm8s4OffsetOperands:
3457 290 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2);
3458 145 : break;
3459 147 : case CVT_95_addAddrMode3Operands:
3460 294 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3);
3461 147 : break;
3462 78 : case CVT_95_addAM3OffsetOperands:
3463 156 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2);
3464 78 : break;
3465 44 : case CVT_95_addMemImm0_95_1020s4OffsetOperands:
3466 88 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2);
3467 44 : break;
3468 30 : case CVT_95_addMemThumbRIs2Operands:
3469 60 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2);
3470 30 : break;
3471 12 : case CVT_95_addPostIdxRegOperands:
3472 24 : static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2);
3473 12 : break;
3474 16 : case CVT_95_addPostIdxImm8Operands:
3475 32 : static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1);
3476 16 : break;
3477 : case CVT_reg0:
3478 61 : Inst.addOperand(MCOperand::createReg(0));
3479 61 : break;
3480 : case CVT_regCPSR:
3481 119 : Inst.addOperand(MCOperand::createReg(ARM::CPSR));
3482 119 : break;
3483 : case CVT_imm_95_14:
3484 67 : Inst.addOperand(MCOperand::createImm(14));
3485 67 : break;
3486 198 : case CVT_95_addBankedRegOperands:
3487 198 : static_cast<ARMOperand&>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1);
3488 : break;
3489 334 : case CVT_95_addMSRMaskOperands:
3490 334 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1);
3491 : break;
3492 30 : case CVT_cvtThumbMultiply:
3493 30 : cvtThumbMultiply(Inst, Operands);
3494 30 : break;
3495 : case CVT_regR8:
3496 68 : Inst.addOperand(MCOperand::createReg(ARM::R8));
3497 68 : break;
3498 : case CVT_regR0:
3499 4 : Inst.addOperand(MCOperand::createReg(ARM::R0));
3500 4 : break;
3501 12 : case CVT_95_addPKHASRImmOperands:
3502 24 : static_cast<ARMOperand&>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1);
3503 12 : break;
3504 : case CVT_imm_95_4:
3505 35 : Inst.addOperand(MCOperand::createImm(4));
3506 35 : break;
3507 156 : case CVT_95_addImm1_95_32Operands:
3508 312 : static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
3509 156 : break;
3510 : case CVT_imm_95_5:
3511 13 : Inst.addOperand(MCOperand::createImm(5));
3512 13 : break;
3513 44 : case CVT_95_addShifterImmOperands:
3514 88 : static_cast<ARMOperand&>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1);
3515 : break;
3516 18 : case CVT_95_addImm1_95_16Operands:
3517 36 : static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
3518 18 : break;
3519 330 : case CVT_95_addRotImmOperands:
3520 660 : static_cast<ARMOperand&>(*Operands[OpIdx]).addRotImmOperands(Inst, 1);
3521 : break;
3522 7 : case CVT_95_addMemTBBOperands:
3523 14 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2);
3524 7 : break;
3525 7 : case CVT_95_addMemTBHOperands:
3526 14 : static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2);
3527 7 : break;
3528 2 : case CVT_95_addTraceSyncBarrierOptOperands:
3529 2 : static_cast<ARMOperand&>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1);
3530 : break;
3531 4 : case CVT_95_addNEONi16splatNotOperands:
3532 8 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1);
3533 4 : break;
3534 8 : case CVT_95_addNEONi32splatNotOperands:
3535 16 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1);
3536 8 : break;
3537 16 : case CVT_95_addNEONi16splatOperands:
3538 32 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1);
3539 16 : break;
3540 11 : case CVT_95_addNEONi32splatOperands:
3541 22 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1);
3542 11 : break;
3543 40 : case CVT_95_addComplexRotationOddOperands:
3544 80 : static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
3545 40 : break;
3546 120 : case CVT_95_addComplexRotationEvenOperands:
3547 240 : static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
3548 120 : break;
3549 40 : case CVT_95_addVectorIndex64Operands:
3550 40 : static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1);
3551 : break;
3552 175 : case CVT_95_addVectorIndex32Operands:
3553 175 : static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1);
3554 : break;
3555 28 : case CVT_95_addFBits16Operands:
3556 56 : static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits16Operands(Inst, 1);
3557 28 : break;
3558 28 : case CVT_95_addFBits32Operands:
3559 56 : static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits32Operands(Inst, 1);
3560 28 : break;
3561 134 : case CVT_95_addVectorIndex16Operands:
3562 134 : static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1);
3563 : break;
3564 22 : case CVT_95_addVectorIndex8Operands:
3565 22 : static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1);
3566 : break;
3567 1075 : case CVT_95_addVecListOperands:
3568 2150 : static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListOperands(Inst, 1);
3569 : break;
3570 24 : case CVT_95_addDupAlignedMemory16Operands:
3571 24 : static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2);
3572 : break;
3573 289 : case CVT_95_addAlignedMemory64or128Operands:
3574 289 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2);
3575 : break;
3576 393 : case CVT_95_addAlignedMemory64or128or256Operands:
3577 393 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2);
3578 : break;
3579 346 : case CVT_95_addAlignedMemory64Operands:
3580 346 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2);
3581 : break;
3582 327 : case CVT_95_addVecListIndexedOperands:
3583 654 : static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2);
3584 327 : break;
3585 38 : case CVT_95_addAlignedMemory16Operands:
3586 38 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2);
3587 : break;
3588 42 : case CVT_95_addDupAlignedMemory32Operands:
3589 42 : static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2);
3590 : break;
3591 66 : case CVT_95_addAlignedMemory32Operands:
3592 66 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2);
3593 : break;
3594 48 : case CVT_95_addDupAlignedMemoryNoneOperands:
3595 48 : static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2);
3596 : break;
3597 80 : case CVT_95_addAlignedMemoryNoneOperands:
3598 80 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2);
3599 : break;
3600 0 : case CVT_95_addAlignedMemoryOperands:
3601 0 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2);
3602 0 : break;
3603 36 : case CVT_95_addDupAlignedMemory64Operands:
3604 36 : static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2);
3605 : break;
3606 24 : case CVT_95_addDupAlignedMemory64or128Operands:
3607 24 : static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2);
3608 : break;
3609 12 : case CVT_95_addSPRRegListOperands:
3610 12 : static_cast<ARMOperand&>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1);
3611 : break;
3612 32 : case CVT_95_addAddrMode5FP16Operands:
3613 64 : static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2);
3614 32 : break;
3615 38 : case CVT_95_addNEONi32vmovOperands:
3616 76 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1);
3617 38 : break;
3618 8 : case CVT_95_addNEONvmovi8ReplicateOperands:
3619 8 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1);
3620 : break;
3621 16 : case CVT_95_addNEONvmovi16ReplicateOperands:
3622 32 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1);
3623 16 : break;
3624 0 : case CVT_95_addNEONi32vmovNegOperands:
3625 0 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1);
3626 0 : break;
3627 8 : case CVT_95_addNEONvmovi32ReplicateOperands:
3628 16 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1);
3629 8 : break;
3630 8 : case CVT_95_addNEONi64splatOperands:
3631 16 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1);
3632 8 : break;
3633 4 : case CVT_95_addNEONi8splatOperands:
3634 8 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1);
3635 4 : break;
3636 10 : case CVT_95_addNEONinvi8ReplicateOperands:
3637 10 : static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1);
3638 : break;
3639 : case CVT_imm_95_2:
3640 34 : Inst.addOperand(MCOperand::createImm(2));
3641 34 : break;
3642 : case CVT_imm_95_3:
3643 34 : Inst.addOperand(MCOperand::createImm(3));
3644 34 : break;
3645 : }
3646 : }
3647 31027 : }
3648 :
3649 0 : void ARMAsmParser::
3650 : convertToMapAndConstraints(unsigned Kind,
3651 : const OperandVector &Operands) {
3652 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
3653 : unsigned NumMCOperands = 0;
3654 0 : const uint8_t *Converter = ConversionTable[Kind];
3655 0 : for (const uint8_t *p = Converter; *p; p+= 2) {
3656 0 : switch (*p) {
3657 0 : default: llvm_unreachable("invalid conversion entry!");
3658 0 : case CVT_Reg:
3659 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3660 0 : Operands[*(p + 1)]->setConstraint("r");
3661 0 : ++NumMCOperands;
3662 0 : break;
3663 0 : case CVT_Tied:
3664 0 : ++NumMCOperands;
3665 0 : break;
3666 0 : case CVT_95_Reg:
3667 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3668 0 : Operands[*(p + 1)]->setConstraint("r");
3669 0 : NumMCOperands += 1;
3670 0 : break;
3671 0 : case CVT_95_addCCOutOperands:
3672 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3673 0 : Operands[*(p + 1)]->setConstraint("m");
3674 0 : NumMCOperands += 1;
3675 0 : break;
3676 0 : case CVT_95_addCondCodeOperands:
3677 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3678 0 : Operands[*(p + 1)]->setConstraint("m");
3679 0 : NumMCOperands += 2;
3680 0 : break;
3681 0 : case CVT_95_addRegShiftedRegOperands:
3682 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3683 0 : Operands[*(p + 1)]->setConstraint("m");
3684 0 : NumMCOperands += 3;
3685 0 : break;
3686 0 : case CVT_95_addModImmOperands:
3687 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3688 0 : Operands[*(p + 1)]->setConstraint("m");
3689 0 : NumMCOperands += 1;
3690 0 : break;
3691 0 : case CVT_95_addModImmNotOperands:
3692 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3693 0 : Operands[*(p + 1)]->setConstraint("m");
3694 0 : NumMCOperands += 1;
3695 0 : break;
3696 0 : case CVT_95_addRegShiftedImmOperands:
3697 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3698 0 : Operands[*(p + 1)]->setConstraint("m");
3699 0 : NumMCOperands += 2;
3700 0 : break;
3701 0 : case CVT_95_addImmOperands:
3702 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3703 0 : Operands[*(p + 1)]->setConstraint("m");
3704 0 : NumMCOperands += 1;
3705 0 : break;
3706 0 : case CVT_95_addT2SOImmNotOperands:
3707 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3708 0 : Operands[*(p + 1)]->setConstraint("m");
3709 0 : NumMCOperands += 1;
3710 0 : break;
3711 0 : case CVT_95_addImm0_95_508s4Operands:
3712 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3713 0 : Operands[*(p + 1)]->setConstraint("m");
3714 0 : NumMCOperands += 1;
3715 0 : break;
3716 0 : case CVT_regSP:
3717 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3718 0 : Operands[*(p + 1)]->setConstraint("m");
3719 0 : ++NumMCOperands;
3720 0 : break;
3721 0 : case CVT_95_addImm0_95_508s4NegOperands:
3722 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3723 0 : Operands[*(p + 1)]->setConstraint("m");
3724 0 : NumMCOperands += 1;
3725 0 : break;
3726 0 : case CVT_95_addImm0_95_4095NegOperands:
3727 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3728 0 : Operands[*(p + 1)]->setConstraint("m");
3729 0 : NumMCOperands += 1;
3730 0 : break;
3731 0 : case CVT_95_addThumbModImmNeg8_95_255Operands:
3732 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3733 0 : Operands[*(p + 1)]->setConstraint("m");
3734 0 : NumMCOperands += 1;
3735 0 : break;
3736 0 : case CVT_95_addT2SOImmNegOperands:
3737 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3738 0 : Operands[*(p + 1)]->setConstraint("m");
3739 0 : NumMCOperands += 1;
3740 0 : break;
3741 0 : case CVT_95_addModImmNegOperands:
3742 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3743 0 : Operands[*(p + 1)]->setConstraint("m");
3744 0 : NumMCOperands += 1;
3745 0 : break;
3746 0 : case CVT_95_addImm0_95_1020s4Operands:
3747 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3748 0 : Operands[*(p + 1)]->setConstraint("m");
3749 0 : NumMCOperands += 1;
3750 0 : break;
3751 0 : case CVT_95_addThumbModImmNeg1_95_7Operands:
3752 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3753 0 : Operands[*(p + 1)]->setConstraint("m");
3754 0 : NumMCOperands += 1;
3755 0 : break;
3756 0 : case CVT_95_addUnsignedOffset_95_b8s2Operands:
3757 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3758 0 : Operands[*(p + 1)]->setConstraint("m");
3759 0 : NumMCOperands += 1;
3760 0 : break;
3761 0 : case CVT_95_addAdrLabelOperands:
3762 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3763 0 : Operands[*(p + 1)]->setConstraint("m");
3764 0 : NumMCOperands += 1;
3765 0 : break;
3766 0 : case CVT_95_addARMBranchTargetOperands:
3767 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3768 0 : Operands[*(p + 1)]->setConstraint("m");
3769 0 : NumMCOperands += 1;
3770 0 : break;
3771 0 : case CVT_95_addBitfieldOperands:
3772 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3773 0 : Operands[*(p + 1)]->setConstraint("m");
3774 0 : NumMCOperands += 1;
3775 0 : break;
3776 0 : case CVT_imm_95_0:
3777 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3778 0 : Operands[*(p + 1)]->setConstraint("");
3779 0 : ++NumMCOperands;
3780 0 : break;
3781 0 : case CVT_95_addThumbBranchTargetOperands:
3782 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3783 0 : Operands[*(p + 1)]->setConstraint("m");
3784 0 : NumMCOperands += 1;
3785 0 : break;
3786 0 : case CVT_95_addCoprocNumOperands:
3787 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3788 0 : Operands[*(p + 1)]->setConstraint("m");
3789 0 : NumMCOperands += 1;
3790 0 : break;
3791 0 : case CVT_95_addCoprocRegOperands:
3792 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3793 0 : Operands[*(p + 1)]->setConstraint("m");
3794 0 : NumMCOperands += 1;
3795 0 : break;
3796 0 : case CVT_95_addProcIFlagsOperands:
3797 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3798 0 : Operands[*(p + 1)]->setConstraint("m");
3799 0 : NumMCOperands += 1;
3800 0 : break;
3801 0 : case CVT_imm_95_20:
3802 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3803 0 : Operands[*(p + 1)]->setConstraint("");
3804 0 : ++NumMCOperands;
3805 0 : break;
3806 0 : case CVT_imm_95_12:
3807 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3808 0 : Operands[*(p + 1)]->setConstraint("");
3809 0 : ++NumMCOperands;
3810 0 : break;
3811 0 : case CVT_imm_95_15:
3812 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3813 0 : Operands[*(p + 1)]->setConstraint("");
3814 0 : ++NumMCOperands;
3815 0 : break;
3816 0 : case CVT_95_addMemBarrierOptOperands:
3817 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3818 0 : Operands[*(p + 1)]->setConstraint("m");
3819 0 : NumMCOperands += 1;
3820 0 : break;
3821 0 : case CVT_imm_95_16:
3822 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3823 0 : Operands[*(p + 1)]->setConstraint("");
3824 0 : ++NumMCOperands;
3825 0 : break;
3826 0 : case CVT_95_addFPImmOperands:
3827 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3828 0 : Operands[*(p + 1)]->setConstraint("m");
3829 0 : NumMCOperands += 1;
3830 0 : break;
3831 0 : case CVT_95_addDPRRegListOperands:
3832 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3833 0 : Operands[*(p + 1)]->setConstraint("m");
3834 0 : NumMCOperands += 1;
3835 0 : break;
3836 0 : case CVT_imm_95_1:
3837 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3838 0 : Operands[*(p + 1)]->setConstraint("");
3839 0 : ++NumMCOperands;
3840 0 : break;
3841 0 : case CVT_95_addInstSyncBarrierOptOperands:
3842 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3843 0 : Operands[*(p + 1)]->setConstraint("m");
3844 0 : NumMCOperands += 1;
3845 0 : break;
3846 0 : case CVT_95_addITCondCodeOperands:
3847 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3848 0 : Operands[*(p + 1)]->setConstraint("m");
3849 0 : NumMCOperands += 1;
3850 0 : break;
3851 0 : case CVT_95_addITMaskOperands:
3852 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3853 0 : Operands[*(p + 1)]->setConstraint("m");
3854 0 : NumMCOperands += 1;
3855 0 : break;
3856 0 : case CVT_95_addMemNoOffsetOperands:
3857 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3858 0 : Operands[*(p + 1)]->setConstraint("m");
3859 0 : NumMCOperands += 1;
3860 0 : break;
3861 0 : case CVT_95_addAddrMode5Operands:
3862 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3863 0 : Operands[*(p + 1)]->setConstraint("m");
3864 0 : NumMCOperands += 2;
3865 0 : break;
3866 0 : case CVT_95_addCoprocOptionOperands:
3867 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3868 0 : Operands[*(p + 1)]->setConstraint("m");
3869 0 : NumMCOperands += 1;
3870 0 : break;
3871 0 : case CVT_95_addPostIdxImm8s4Operands:
3872 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3873 0 : Operands[*(p + 1)]->setConstraint("m");
3874 0 : NumMCOperands += 1;
3875 0 : break;
3876 0 : case CVT_95_addRegListOperands:
3877 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3878 0 : Operands[*(p + 1)]->setConstraint("m");
3879 0 : NumMCOperands += 1;
3880 0 : break;
3881 0 : case CVT_95_addThumbMemPCOperands:
3882 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3883 0 : Operands[*(p + 1)]->setConstraint("m");
3884 0 : NumMCOperands += 1;
3885 0 : break;
3886 0 : case CVT_95_addConstPoolAsmImmOperands:
3887 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3888 0 : Operands[*(p + 1)]->setConstraint("m");
3889 0 : NumMCOperands += 1;
3890 0 : break;
3891 0 : case CVT_95_addMemThumbRIs4Operands:
3892 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3893 0 : Operands[*(p + 1)]->setConstraint("m");
3894 0 : NumMCOperands += 2;
3895 0 : break;
3896 0 : case CVT_95_addMemThumbRROperands:
3897 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3898 0 : Operands[*(p + 1)]->setConstraint("m");
3899 0 : NumMCOperands += 2;
3900 0 : break;
3901 0 : case CVT_95_addMemThumbSPIOperands:
3902 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3903 0 : Operands[*(p + 1)]->setConstraint("m");
3904 0 : NumMCOperands += 2;
3905 0 : break;
3906 0 : case CVT_95_addMemImm12OffsetOperands:
3907 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3908 0 : Operands[*(p + 1)]->setConstraint("m");
3909 0 : NumMCOperands += 2;
3910 0 : break;
3911 0 : case CVT_95_addMemNegImm8OffsetOperands:
3912 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3913 0 : Operands[*(p + 1)]->setConstraint("m");
3914 0 : NumMCOperands += 2;
3915 0 : break;
3916 0 : case CVT_95_addMemRegOffsetOperands:
3917 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3918 0 : Operands[*(p + 1)]->setConstraint("m");
3919 0 : NumMCOperands += 3;
3920 0 : break;
3921 0 : case CVT_95_addMemUImm12OffsetOperands:
3922 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3923 0 : Operands[*(p + 1)]->setConstraint("m");
3924 0 : NumMCOperands += 2;
3925 0 : break;
3926 0 : case CVT_95_addT2MemRegOffsetOperands:
3927 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3928 0 : Operands[*(p + 1)]->setConstraint("m");
3929 0 : NumMCOperands += 3;
3930 0 : break;
3931 0 : case CVT_95_addMemPCRelImm12Operands:
3932 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3933 0 : Operands[*(p + 1)]->setConstraint("m");
3934 0 : NumMCOperands += 1;
3935 0 : break;
3936 0 : case CVT_95_addMemImm8OffsetOperands:
3937 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3938 0 : Operands[*(p + 1)]->setConstraint("m");
3939 0 : NumMCOperands += 2;
3940 0 : break;
3941 0 : case CVT_95_addAM2OffsetImmOperands:
3942 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3943 0 : Operands[*(p + 1)]->setConstraint("m");
3944 0 : NumMCOperands += 2;
3945 0 : break;
3946 0 : case CVT_95_addPostIdxRegShiftedOperands:
3947 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3948 0 : Operands[*(p + 1)]->setConstraint("m");
3949 0 : NumMCOperands += 2;
3950 0 : break;
3951 0 : case CVT_95_addMemThumbRIs1Operands:
3952 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3953 0 : Operands[*(p + 1)]->setConstraint("m");
3954 0 : NumMCOperands += 2;
3955 0 : break;
3956 0 : case CVT_95_addMemPosImm8OffsetOperands:
3957 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3958 0 : Operands[*(p + 1)]->setConstraint("m");
3959 0 : NumMCOperands += 2;
3960 0 : break;
3961 0 : case CVT_95_addMemImm8s4OffsetOperands:
3962 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3963 0 : Operands[*(p + 1)]->setConstraint("m");
3964 0 : NumMCOperands += 2;
3965 0 : break;
3966 0 : case CVT_95_addAddrMode3Operands:
3967 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3968 0 : Operands[*(p + 1)]->setConstraint("m");
3969 0 : NumMCOperands += 3;
3970 0 : break;
3971 0 : case CVT_95_addAM3OffsetOperands:
3972 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3973 0 : Operands[*(p + 1)]->setConstraint("m");
3974 0 : NumMCOperands += 2;
3975 0 : break;
3976 0 : case CVT_95_addMemImm0_95_1020s4OffsetOperands:
3977 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3978 0 : Operands[*(p + 1)]->setConstraint("m");
3979 0 : NumMCOperands += 2;
3980 0 : break;
3981 0 : case CVT_95_addMemThumbRIs2Operands:
3982 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3983 0 : Operands[*(p + 1)]->setConstraint("m");
3984 0 : NumMCOperands += 2;
3985 0 : break;
3986 0 : case CVT_95_addPostIdxRegOperands:
3987 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3988 0 : Operands[*(p + 1)]->setConstraint("m");
3989 0 : NumMCOperands += 2;
3990 0 : break;
3991 0 : case CVT_95_addPostIdxImm8Operands:
3992 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3993 0 : Operands[*(p + 1)]->setConstraint("m");
3994 0 : NumMCOperands += 1;
3995 0 : break;
3996 0 : case CVT_reg0:
3997 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
3998 0 : Operands[*(p + 1)]->setConstraint("m");
3999 0 : ++NumMCOperands;
4000 0 : break;
4001 0 : case CVT_regCPSR:
4002 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4003 0 : Operands[*(p + 1)]->setConstraint("m");
4004 0 : ++NumMCOperands;
4005 0 : break;
4006 0 : case CVT_imm_95_14:
4007 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4008 0 : Operands[*(p + 1)]->setConstraint("");
4009 0 : ++NumMCOperands;
4010 0 : break;
4011 0 : case CVT_95_addBankedRegOperands:
4012 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4013 0 : Operands[*(p + 1)]->setConstraint("m");
4014 0 : NumMCOperands += 1;
4015 0 : break;
4016 0 : case CVT_95_addMSRMaskOperands:
4017 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4018 0 : Operands[*(p + 1)]->setConstraint("m");
4019 0 : NumMCOperands += 1;
4020 0 : break;
4021 0 : case CVT_regR8:
4022 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4023 0 : Operands[*(p + 1)]->setConstraint("m");
4024 0 : ++NumMCOperands;
4025 0 : break;
4026 0 : case CVT_regR0:
4027 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4028 0 : Operands[*(p + 1)]->setConstraint("m");
4029 0 : ++NumMCOperands;
4030 0 : break;
4031 0 : case CVT_95_addPKHASRImmOperands:
4032 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4033 0 : Operands[*(p + 1)]->setConstraint("m");
4034 0 : NumMCOperands += 1;
4035 0 : break;
4036 0 : case CVT_imm_95_4:
4037 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4038 0 : Operands[*(p + 1)]->setConstraint("");
4039 0 : ++NumMCOperands;
4040 0 : break;
4041 0 : case CVT_95_addImm1_95_32Operands:
4042 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4043 0 : Operands[*(p + 1)]->setConstraint("m");
4044 0 : NumMCOperands += 1;
4045 0 : break;
4046 0 : case CVT_imm_95_5:
4047 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4048 0 : Operands[*(p + 1)]->setConstraint("");
4049 0 : ++NumMCOperands;
4050 0 : break;
4051 0 : case CVT_95_addShifterImmOperands:
4052 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4053 0 : Operands[*(p + 1)]->setConstraint("m");
4054 0 : NumMCOperands += 1;
4055 0 : break;
4056 0 : case CVT_95_addImm1_95_16Operands:
4057 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4058 0 : Operands[*(p + 1)]->setConstraint("m");
4059 0 : NumMCOperands += 1;
4060 0 : break;
4061 0 : case CVT_95_addRotImmOperands:
4062 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4063 0 : Operands[*(p + 1)]->setConstraint("m");
4064 0 : NumMCOperands += 1;
4065 0 : break;
4066 0 : case CVT_95_addMemTBBOperands:
4067 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4068 0 : Operands[*(p + 1)]->setConstraint("m");
4069 0 : NumMCOperands += 2;
4070 0 : break;
4071 0 : case CVT_95_addMemTBHOperands:
4072 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4073 0 : Operands[*(p + 1)]->setConstraint("m");
4074 0 : NumMCOperands += 2;
4075 0 : break;
4076 0 : case CVT_95_addTraceSyncBarrierOptOperands:
4077 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4078 0 : Operands[*(p + 1)]->setConstraint("m");
4079 0 : NumMCOperands += 1;
4080 0 : break;
4081 0 : case CVT_95_addNEONi16splatNotOperands:
4082 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4083 0 : Operands[*(p + 1)]->setConstraint("m");
4084 0 : NumMCOperands += 1;
4085 0 : break;
4086 0 : case CVT_95_addNEONi32splatNotOperands:
4087 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4088 0 : Operands[*(p + 1)]->setConstraint("m");
4089 0 : NumMCOperands += 1;
4090 0 : break;
4091 0 : case CVT_95_addNEONi16splatOperands:
4092 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4093 0 : Operands[*(p + 1)]->setConstraint("m");
4094 0 : NumMCOperands += 1;
4095 0 : break;
4096 0 : case CVT_95_addNEONi32splatOperands:
4097 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4098 0 : Operands[*(p + 1)]->setConstraint("m");
4099 0 : NumMCOperands += 1;
4100 0 : break;
4101 0 : case CVT_95_addComplexRotationOddOperands:
4102 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4103 0 : Operands[*(p + 1)]->setConstraint("m");
4104 0 : NumMCOperands += 1;
4105 0 : break;
4106 0 : case CVT_95_addComplexRotationEvenOperands:
4107 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4108 0 : Operands[*(p + 1)]->setConstraint("m");
4109 0 : NumMCOperands += 1;
4110 0 : break;
4111 0 : case CVT_95_addVectorIndex64Operands:
4112 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4113 0 : Operands[*(p + 1)]->setConstraint("m");
4114 0 : NumMCOperands += 1;
4115 0 : break;
4116 0 : case CVT_95_addVectorIndex32Operands:
4117 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4118 0 : Operands[*(p + 1)]->setConstraint("m");
4119 0 : NumMCOperands += 1;
4120 0 : break;
4121 0 : case CVT_95_addFBits16Operands:
4122 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4123 0 : Operands[*(p + 1)]->setConstraint("m");
4124 0 : NumMCOperands += 1;
4125 0 : break;
4126 0 : case CVT_95_addFBits32Operands:
4127 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4128 0 : Operands[*(p + 1)]->setConstraint("m");
4129 0 : NumMCOperands += 1;
4130 0 : break;
4131 0 : case CVT_95_addVectorIndex16Operands:
4132 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4133 0 : Operands[*(p + 1)]->setConstraint("m");
4134 0 : NumMCOperands += 1;
4135 0 : break;
4136 0 : case CVT_95_addVectorIndex8Operands:
4137 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4138 0 : Operands[*(p + 1)]->setConstraint("m");
4139 0 : NumMCOperands += 1;
4140 0 : break;
4141 0 : case CVT_95_addVecListOperands:
4142 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4143 0 : Operands[*(p + 1)]->setConstraint("m");
4144 0 : NumMCOperands += 1;
4145 0 : break;
4146 0 : case CVT_95_addDupAlignedMemory16Operands:
4147 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4148 0 : Operands[*(p + 1)]->setConstraint("m");
4149 0 : NumMCOperands += 2;
4150 0 : break;
4151 0 : case CVT_95_addAlignedMemory64or128Operands:
4152 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4153 0 : Operands[*(p + 1)]->setConstraint("m");
4154 0 : NumMCOperands += 2;
4155 0 : break;
4156 0 : case CVT_95_addAlignedMemory64or128or256Operands:
4157 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4158 0 : Operands[*(p + 1)]->setConstraint("m");
4159 0 : NumMCOperands += 2;
4160 0 : break;
4161 0 : case CVT_95_addAlignedMemory64Operands:
4162 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4163 0 : Operands[*(p + 1)]->setConstraint("m");
4164 0 : NumMCOperands += 2;
4165 0 : break;
4166 0 : case CVT_95_addVecListIndexedOperands:
4167 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4168 0 : Operands[*(p + 1)]->setConstraint("m");
4169 0 : NumMCOperands += 2;
4170 0 : break;
4171 0 : case CVT_95_addAlignedMemory16Operands:
4172 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4173 0 : Operands[*(p + 1)]->setConstraint("m");
4174 0 : NumMCOperands += 2;
4175 0 : break;
4176 0 : case CVT_95_addDupAlignedMemory32Operands:
4177 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4178 0 : Operands[*(p + 1)]->setConstraint("m");
4179 0 : NumMCOperands += 2;
4180 0 : break;
4181 0 : case CVT_95_addAlignedMemory32Operands:
4182 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4183 0 : Operands[*(p + 1)]->setConstraint("m");
4184 0 : NumMCOperands += 2;
4185 0 : break;
4186 0 : case CVT_95_addDupAlignedMemoryNoneOperands:
4187 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4188 0 : Operands[*(p + 1)]->setConstraint("m");
4189 0 : NumMCOperands += 2;
4190 0 : break;
4191 0 : case CVT_95_addAlignedMemoryNoneOperands:
4192 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4193 0 : Operands[*(p + 1)]->setConstraint("m");
4194 0 : NumMCOperands += 2;
4195 0 : break;
4196 0 : case CVT_95_addAlignedMemoryOperands:
4197 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4198 0 : Operands[*(p + 1)]->setConstraint("m");
4199 0 : NumMCOperands += 2;
4200 0 : break;
4201 0 : case CVT_95_addDupAlignedMemory64Operands:
4202 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4203 0 : Operands[*(p + 1)]->setConstraint("m");
4204 0 : NumMCOperands += 2;
4205 0 : break;
4206 0 : case CVT_95_addDupAlignedMemory64or128Operands:
4207 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4208 0 : Operands[*(p + 1)]->setConstraint("m");
4209 0 : NumMCOperands += 2;
4210 0 : break;
4211 0 : case CVT_95_addSPRRegListOperands:
4212 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4213 0 : Operands[*(p + 1)]->setConstraint("m");
4214 0 : NumMCOperands += 1;
4215 0 : break;
4216 0 : case CVT_95_addAddrMode5FP16Operands:
4217 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4218 0 : Operands[*(p + 1)]->setConstraint("m");
4219 0 : NumMCOperands += 2;
4220 0 : break;
4221 0 : case CVT_95_addNEONi32vmovOperands:
4222 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4223 0 : Operands[*(p + 1)]->setConstraint("m");
4224 0 : NumMCOperands += 1;
4225 0 : break;
4226 0 : case CVT_95_addNEONvmovi8ReplicateOperands:
4227 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4228 0 : Operands[*(p + 1)]->setConstraint("m");
4229 0 : NumMCOperands += 1;
4230 0 : break;
4231 0 : case CVT_95_addNEONvmovi16ReplicateOperands:
4232 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4233 0 : Operands[*(p + 1)]->setConstraint("m");
4234 0 : NumMCOperands += 1;
4235 0 : break;
4236 0 : case CVT_95_addNEONi32vmovNegOperands:
4237 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4238 0 : Operands[*(p + 1)]->setConstraint("m");
4239 0 : NumMCOperands += 1;
4240 0 : break;
4241 0 : case CVT_95_addNEONvmovi32ReplicateOperands:
4242 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4243 0 : Operands[*(p + 1)]->setConstraint("m");
4244 0 : NumMCOperands += 1;
4245 0 : break;
4246 0 : case CVT_95_addNEONi64splatOperands:
4247 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4248 0 : Operands[*(p + 1)]->setConstraint("m");
4249 0 : NumMCOperands += 1;
4250 0 : break;
4251 0 : case CVT_95_addNEONi8splatOperands:
4252 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4253 0 : Operands[*(p + 1)]->setConstraint("m");
4254 0 : NumMCOperands += 1;
4255 0 : break;
4256 0 : case CVT_95_addNEONinvi8ReplicateOperands:
4257 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4258 0 : Operands[*(p + 1)]->setConstraint("m");
4259 0 : NumMCOperands += 1;
4260 0 : break;
4261 0 : case CVT_imm_95_2:
4262 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4263 0 : Operands[*(p + 1)]->setConstraint("");
4264 0 : ++NumMCOperands;
4265 0 : break;
4266 0 : case CVT_imm_95_3:
4267 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4268 0 : Operands[*(p + 1)]->setConstraint("");
4269 0 : ++NumMCOperands;
4270 0 : break;
4271 : }
4272 : }
4273 0 : }
4274 :
4275 : namespace {
4276 :
4277 : /// MatchClassKind - The kinds of classes which participate in
4278 : /// instruction matching.
4279 : enum MatchClassKind {
4280 : InvalidMatchClass = 0,
4281 : OptionalMatchClass = 1,
4282 : MCK__DOT_d, // '.d'
4283 : MCK__DOT_f, // '.f'
4284 : MCK__DOT_s16, // '.s16'
4285 : MCK__DOT_s32, // '.s32'
4286 : MCK__DOT_s64, // '.s64'
4287 : MCK__DOT_s8, // '.s8'
4288 : MCK__DOT_u16, // '.u16'
4289 : MCK__DOT_u32, // '.u32'
4290 : MCK__DOT_u64, // '.u64'
4291 : MCK__DOT_u8, // '.u8'
4292 : MCK__DOT_f32, // '.f32'
4293 : MCK__DOT_f64, // '.f64'
4294 : MCK__DOT_i16, // '.i16'
4295 : MCK__DOT_i32, // '.i32'
4296 : MCK__DOT_i64, // '.i64'
4297 : MCK__DOT_i8, // '.i8'
4298 : MCK__DOT_p16, // '.p16'
4299 : MCK__DOT_p8, // '.p8'
4300 : MCK__EXCLAIM_, // '!'
4301 : MCK__35_0, // '#0'
4302 : MCK__DOT_16, // '.16'
4303 : MCK__DOT_32, // '.32'
4304 : MCK__DOT_64, // '.64'
4305 : MCK__DOT_8, // '.8'
4306 : MCK__DOT_f16, // '.f16'
4307 : MCK__DOT_p64, // '.p64'
4308 : MCK__DOT_w, // '.w'
4309 : MCK__91_, // '['
4310 : MCK__93_, // ']'
4311 : MCK__94_, // '^'
4312 : MCK__123_, // '{'
4313 : MCK__125_, // '}'
4314 : MCK_LAST_TOKEN = MCK__125_,
4315 : MCK_Reg11, // derived register class
4316 : MCK_Reg59, // derived register class
4317 : MCK_Reg75, // derived register class
4318 : MCK_APSR, // register class 'APSR'
4319 : MCK_APSR_NZCV, // register class 'APSR_NZCV'
4320 : MCK_CCR, // register class 'CCR,CPSR'
4321 : MCK_FPEXC, // register class 'FPEXC'
4322 : MCK_FPINST, // register class 'FPINST'
4323 : MCK_FPINST2, // register class 'FPINST2'
4324 : MCK_FPSCR, // register class 'FPSCR'
4325 : MCK_FPSID, // register class 'FPSID'
4326 : MCK_GPRsp, // register class 'GPRsp,SP'
4327 : MCK_LR, // register class 'LR'
4328 : MCK_MVFR0, // register class 'MVFR0'
4329 : MCK_MVFR1, // register class 'MVFR1'
4330 : MCK_MVFR2, // register class 'MVFR2'
4331 : MCK_PC, // register class 'PC'
4332 : MCK_SPSR, // register class 'SPSR'
4333 : MCK_Reg60, // derived register class
4334 : MCK_Reg68, // derived register class
4335 : MCK_Reg73, // derived register class
4336 : MCK_Reg100, // derived register class
4337 : MCK_Reg45, // derived register class
4338 : MCK_Reg61, // derived register class
4339 : MCK_Reg72, // derived register class
4340 : MCK_Reg74, // derived register class
4341 : MCK_Reg83, // derived register class
4342 : MCK_Reg88, // derived register class
4343 : MCK_Reg101, // derived register class
4344 : MCK_Reg0, // derived register class
4345 : MCK_Reg46, // derived register class
4346 : MCK_Reg62, // derived register class
4347 : MCK_Reg69, // derived register class
4348 : MCK_Reg84, // derived register class
4349 : MCK_Reg89, // derived register class
4350 : MCK_Reg93, // derived register class
4351 : MCK_Reg102, // derived register class
4352 : MCK_QPR_8, // register class 'QPR_8'
4353 : MCK_Reg57, // derived register class
4354 : MCK_Reg63, // derived register class
4355 : MCK_tcGPR, // register class 'tcGPR'
4356 : MCK_Reg10, // derived register class
4357 : MCK_Reg40, // derived register class
4358 : MCK_Reg58, // derived register class
4359 : MCK_Reg64, // derived register class
4360 : MCK_Reg70, // derived register class
4361 : MCK_Reg76, // derived register class
4362 : MCK_Reg94, // derived register class
4363 : MCK_Reg103, // derived register class
4364 : MCK_Reg8, // derived register class
4365 : MCK_Reg26, // derived register class
4366 : MCK_Reg47, // derived register class
4367 : MCK_Reg55, // derived register class
4368 : MCK_Reg65, // derived register class
4369 : MCK_Reg77, // derived register class
4370 : MCK_Reg85, // derived register class
4371 : MCK_Reg90, // derived register class
4372 : MCK_Reg104, // derived register class
4373 : MCK_GPRPair, // register class 'GPRPair'
4374 : MCK_Reg27, // derived register class
4375 : MCK_Reg41, // derived register class
4376 : MCK_Reg48, // derived register class
4377 : MCK_Reg56, // derived register class
4378 : MCK_Reg66, // derived register class
4379 : MCK_Reg78, // derived register class
4380 : MCK_Reg86, // derived register class
4381 : MCK_Reg91, // derived register class
4382 : MCK_Reg95, // derived register class
4383 : MCK_Reg105, // derived register class
4384 : MCK_DPR_8, // register class 'DPR_8'
4385 : MCK_QPR_VFP2, // register class 'QPR_VFP2'
4386 : MCK_hGPR, // register class 'hGPR'
4387 : MCK_tGPR, // register class 'tGPR'
4388 : MCK_tGPRwithpc, // register class 'tGPRwithpc'
4389 : MCK_Reg96, // derived register class
4390 : MCK_Reg53, // derived register class
4391 : MCK_QQQQPR, // register class 'QQQQPR'
4392 : MCK_Reg42, // derived register class
4393 : MCK_Reg54, // derived register class
4394 : MCK_Reg79, // derived register class
4395 : MCK_Reg97, // derived register class
4396 : MCK_Reg106, // derived register class
4397 : MCK_rGPR, // register class 'rGPR'
4398 : MCK_Reg24, // derived register class
4399 : MCK_Reg51, // derived register class
4400 : MCK_Reg80, // derived register class
4401 : MCK_Reg87, // derived register class
4402 : MCK_Reg92, // derived register class
4403 : MCK_GPRnopc, // register class 'GPRnopc'
4404 : MCK_QQPR, // register class 'QQPR'
4405 : MCK_Reg25, // derived register class
4406 : MCK_Reg43, // derived register class
4407 : MCK_Reg52, // derived register class
4408 : MCK_Reg81, // derived register class
4409 : MCK_Reg98, // derived register class
4410 : MCK_DPR_VFP2, // register class 'DPR_VFP2'
4411 : MCK_GPR, // register class 'GPR'
4412 : MCK_GPRwithAPSR, // register class 'GPRwithAPSR'
4413 : MCK_QPR, // register class 'QPR'
4414 : MCK_SPR_8, // register class 'SPR_8'
4415 : MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc'
4416 : MCK_DQuad, // register class 'DQuad'
4417 : MCK_DPairSpc, // register class 'DPairSpc'
4418 : MCK_DTriple, // register class 'DTriple'
4419 : MCK_DPair, // register class 'DPair'
4420 : MCK_DPR, // register class 'DPR'
4421 : MCK_HPR, // register class 'HPR,SPR'
4422 : MCK_LAST_REGISTER = MCK_HPR,
4423 : MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand'
4424 : MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand'
4425 : MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget'
4426 : MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand'
4427 : MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand'
4428 : MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand'
4429 : MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand'
4430 : MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand'
4431 : MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand'
4432 : MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand'
4433 : MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand'
4434 : MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand'
4435 : MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand'
4436 : MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand'
4437 : MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand'
4438 : MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand'
4439 : MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand'
4440 : MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand'
4441 : MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand'
4442 : MCK_BankedReg, // user defined class 'BankedRegOperand'
4443 : MCK_Bitfield, // user defined class 'BitfieldAsmOperand'
4444 : MCK_CCOut, // user defined class 'CCOutOperand'
4445 : MCK_CondCode, // user defined class 'CondCodeOperand'
4446 : MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand'
4447 : MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand'
4448 : MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand'
4449 : MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand'
4450 : MCK_FPImm, // user defined class 'FPImmOperand'
4451 : MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand'
4452 : MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand'
4453 : MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand'
4454 : MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand'
4455 : MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand'
4456 : MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand'
4457 : MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand'
4458 : MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand'
4459 : MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand'
4460 : MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand'
4461 : MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand'
4462 : MCK_Imm16, // user defined class 'Imm16AsmOperand'
4463 : MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand'
4464 : MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand'
4465 : MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand'
4466 : MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand'
4467 : MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand'
4468 : MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand'
4469 : MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand'
4470 : MCK_Imm32, // user defined class 'Imm32AsmOperand'
4471 : MCK_Imm8, // user defined class 'Imm8AsmOperand'
4472 : MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand'
4473 : MCK_Imm, // user defined class 'ImmAsmOperand'
4474 : MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand'
4475 : MCK_MSRMask, // user defined class 'MSRMaskOperand'
4476 : MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand'
4477 : MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand'
4478 : MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand'
4479 : MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand'
4480 : MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand'
4481 : MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand'
4482 : MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand'
4483 : MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand'
4484 : MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand'
4485 : MCK_ModImm, // user defined class 'ModImmAsmOperand'
4486 : MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand'
4487 : MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand'
4488 : MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand'
4489 : MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand'
4490 : MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand'
4491 : MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand'
4492 : MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand'
4493 : MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand'
4494 : MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand'
4495 : MCK_RegList, // user defined class 'RegListAsmOperand'
4496 : MCK_RotImm, // user defined class 'RotImmAsmOperand'
4497 : MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand'
4498 : MCK_SetEndImm, // user defined class 'SetEndAsmOperand'
4499 : MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand'
4500 : MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand'
4501 : MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand'
4502 : MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget'
4503 : MCK_ThumbMemPC, // user defined class 'ThumbMemPC'
4504 : MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand'
4505 : MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand'
4506 : MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand'
4507 : MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand'
4508 : MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2'
4509 : MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand'
4510 : MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand'
4511 : MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand'
4512 : MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand'
4513 : MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand'
4514 : MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand'
4515 : MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand'
4516 : MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand'
4517 : MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand'
4518 : MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand'
4519 : MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand'
4520 : MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand'
4521 : MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand'
4522 : MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand'
4523 : MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand'
4524 : MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand'
4525 : MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand'
4526 : MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand'
4527 : MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand'
4528 : MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand'
4529 : MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand'
4530 : MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand'
4531 : MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand'
4532 : MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand'
4533 : MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand'
4534 : MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand'
4535 : MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand'
4536 : MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand'
4537 : MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand'
4538 : MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand'
4539 : MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand'
4540 : MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand'
4541 : MCK_VectorIndex16, // user defined class 'VectorIndex16Operand'
4542 : MCK_VectorIndex32, // user defined class 'VectorIndex32Operand'
4543 : MCK_VectorIndex64, // user defined class 'VectorIndex64Operand'
4544 : MCK_VectorIndex8, // user defined class 'VectorIndex8Operand'
4545 : MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand'
4546 : MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand'
4547 : MCK_ComplexRotationEven, // user defined class 'anonymous_3115'
4548 : MCK_ComplexRotationOdd, // user defined class 'anonymous_3116'
4549 : MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_4160'
4550 : MCK_NEONi16invi8Replicate, // user defined class 'anonymous_4162'
4551 : MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_4165'
4552 : MCK_NEONi32invi8Replicate, // user defined class 'anonymous_4167'
4553 : MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_4174'
4554 : MCK_NEONi64invi8Replicate, // user defined class 'anonymous_4176'
4555 : MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_4187'
4556 : MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_4190'
4557 : MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_4197'
4558 : MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand'
4559 : MCK_FBits16, // user defined class 'fbits16_asm_operand'
4560 : MCK_FBits32, // user defined class 'fbits32_asm_operand'
4561 : MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand'
4562 : MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand'
4563 : MCK_ITMask, // user defined class 'it_mask_asmoperand'
4564 : MCK_ITCondCode, // user defined class 'it_pred_asmoperand'
4565 : MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand'
4566 : MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand'
4567 : MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand'
4568 : MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand'
4569 : MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand'
4570 : MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand'
4571 : MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand'
4572 : MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand'
4573 : MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand'
4574 : MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand'
4575 : MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand'
4576 : MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand'
4577 : MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand'
4578 : MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand'
4579 : MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand'
4580 : MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand'
4581 : MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand'
4582 : MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand'
4583 : MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand'
4584 : MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand'
4585 : MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand'
4586 : MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand'
4587 : MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand'
4588 : MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand'
4589 : MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand'
4590 : MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand'
4591 : MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand'
4592 : NumMatchClassKinds
4593 : };
4594 :
4595 : }
4596 :
4597 4821 : static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) {
4598 4821 : switch (MatchResult) {
4599 : case ARMAsmParser::Match_GPRsp:
4600 : return "operand must be a register sp";
4601 0 : case ARMAsmParser::Match_QPR_8:
4602 0 : return "operand must be a register in range [q0, q3]";
4603 0 : case ARMAsmParser::Match_DPR_8:
4604 0 : return "operand must be a register in range [d0, d7]";
4605 0 : case ARMAsmParser::Match_QPR_VFP2:
4606 0 : return "operand must be a register in range [q0, q7]";
4607 0 : case ARMAsmParser::Match_hGPR:
4608 0 : return "operand must be a register in range [r8, r15]";
4609 39 : case ARMAsmParser::Match_tGPR:
4610 39 : return "operand must be a register in range [r0, r7]";
4611 118 : case ARMAsmParser::Match_GPRnopc:
4612 118 : return "operand must be a register in range [r0, r14]";
4613 4 : case ARMAsmParser::Match_DPR_VFP2:
4614 4 : return "operand must be a register in range [d0, d15]";
4615 59 : case ARMAsmParser::Match_GPR:
4616 59 : return "operand must be a register in range [r0, r15]";
4617 0 : case ARMAsmParser::Match_GPRwithAPSR:
4618 0 : return "operand must be a register in range [r0, r14] or apsr_nzcv";
4619 26 : case ARMAsmParser::Match_QPR:
4620 26 : return "operand must be a register in range [q0, q15]";
4621 0 : case ARMAsmParser::Match_SPR_8:
4622 0 : return "operand must be a register in range [s0, s15]";
4623 4 : case ARMAsmParser::Match_SPR:
4624 4 : return "operand must be a register in range [s0, s31]";
4625 48 : case ARMAsmParser::Match_AlignedMemory16:
4626 48 : return "alignment must be 16 or omitted";
4627 84 : case ARMAsmParser::Match_AlignedMemory32:
4628 84 : return "alignment must be 32 or omitted";
4629 432 : case ARMAsmParser::Match_AlignedMemory64:
4630 432 : return "alignment must be 64 or omitted";
4631 213 : case ARMAsmParser::Match_AlignedMemory64or128:
4632 213 : return "alignment must be 64, 128 or omitted";
4633 150 : case ARMAsmParser::Match_AlignedMemory64or128or256:
4634 150 : return "alignment must be 64, 128, 256 or omitted";
4635 180 : case ARMAsmParser::Match_AlignedMemoryNone:
4636 180 : return "alignment must be omitted";
4637 48 : case ARMAsmParser::Match_DupAlignedMemory16:
4638 48 : return "alignment must be 16 or omitted";
4639 72 : case ARMAsmParser::Match_DupAlignedMemory32:
4640 72 : return "alignment must be 32 or omitted";
4641 48 : case ARMAsmParser::Match_DupAlignedMemory64:
4642 48 : return "alignment must be 64 or omitted";
4643 18 : case ARMAsmParser::Match_DupAlignedMemory64or128:
4644 18 : return "alignment must be 64, 128 or omitted";
4645 120 : case ARMAsmParser::Match_DupAlignedMemoryNone:
4646 120 : return "alignment must be omitted";
4647 15 : case ARMAsmParser::Match_Imm0_15:
4648 15 : return "operand must be an immediate in the range [0,15]";
4649 4 : case ARMAsmParser::Match_Imm0_1:
4650 4 : return "operand must be an immediate in the range [0,1]";
4651 4 : case ARMAsmParser::Match_Imm0_239:
4652 4 : return "operand must be an immediate in the range [0,239]";
4653 23 : case ARMAsmParser::Match_Imm0_255:
4654 23 : return "operand must be an immediate in the range [0,255]";
4655 8 : case ARMAsmParser::Match_Imm0_31:
4656 8 : return "operand must be an immediate in the range [0,31]";
4657 0 : case ARMAsmParser::Match_Imm0_32:
4658 0 : return "operand must be an immediate in the range [0,32]";
4659 0 : case ARMAsmParser::Match_Imm0_3:
4660 0 : return "operand must be an immediate in the range [0,3]";
4661 2 : case ARMAsmParser::Match_Imm0_63:
4662 2 : return "operand must be an immediate in the range [0,63]";
4663 6 : case ARMAsmParser::Match_Imm0_65535:
4664 6 : return "operand must be an immediate in the range [0,65535]";
4665 8 : case ARMAsmParser::Match_Imm0_65535Expr:
4666 8 : return "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
4667 30 : case ARMAsmParser::Match_Imm0_7:
4668 30 : return "operand must be an immediate in the range [0,7]";
4669 0 : case ARMAsmParser::Match_Imm16:
4670 0 : return "operand must be an immediate in the range [16,16]";
4671 0 : case ARMAsmParser::Match_Imm1_15:
4672 0 : return "operand must be an immediate in the range [1,15]";
4673 4 : case ARMAsmParser::Match_ImmRange1_16:
4674 4 : return "operand must be an immediate in the range [1,16]";
4675 4 : case ARMAsmParser::Match_Imm1_31:
4676 4 : return "operand must be an immediate in the range [1,31]";
4677 4 : case ARMAsmParser::Match_ImmRange1_32:
4678 4 : return "operand must be an immediate in the range [1,32]";
4679 0 : case ARMAsmParser::Match_Imm1_7:
4680 0 : return "operand must be an immediate in the range [1,7]";
4681 2 : case ARMAsmParser::Match_Imm24bit:
4682 2 : return "operand must be an immediate in the range [0,0xffffff]";
4683 5 : case ARMAsmParser::Match_Imm256_65535Expr:
4684 5 : return "operand must be an immediate in the range [256,65535]";
4685 0 : case ARMAsmParser::Match_Imm32:
4686 0 : return "operand must be an immediate in the range [32,32]";
4687 0 : case ARMAsmParser::Match_Imm8:
4688 0 : return "operand must be an immediate in the range [8,8]";
4689 0 : case ARMAsmParser::Match_Imm8_255:
4690 0 : return "operand must be an immediate in the range [8,255]";
4691 0 : case ARMAsmParser::Match_PKHLSLImm:
4692 0 : return "operand must be an immediate in the range [0,31]";
4693 8 : case ARMAsmParser::Match_SPRRegList:
4694 8 : return "operand must be a list of registers in range [s0, s31]";
4695 0 : case ARMAsmParser::Match_SetEndImm:
4696 0 : return "operand must be an immediate in the range [0,1]";
4697 6 : case ARMAsmParser::Match_ImmThumbSR:
4698 6 : return "operand must be an immediate in the range [1,32]";
4699 24 : case ARMAsmParser::Match_ComplexRotationEven:
4700 24 : return "complex rotation must be 0, 90, 180 or 270";
4701 20 : case ARMAsmParser::Match_ComplexRotationOdd:
4702 20 : return "complex rotation must be 90 or 270";
4703 5 : case ARMAsmParser::Match_Imm0_4095:
4704 5 : return "operand must be an immediate in the range [0,4095]";
4705 0 : case ARMAsmParser::Match_ShrImm16:
4706 0 : return "operand must be an immediate in the range [1,16]";
4707 0 : case ARMAsmParser::Match_ShrImm32:
4708 0 : return "operand must be an immediate in the range [1,32]";
4709 0 : case ARMAsmParser::Match_ShrImm64:
4710 0 : return "operand must be an immediate in the range [1,64]";
4711 0 : case ARMAsmParser::Match_ShrImm8:
4712 0 : return "operand must be an immediate in the range [1,8]";
4713 2973 : default:
4714 2973 : return nullptr;
4715 : }
4716 : }
4717 :
4718 : static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
4719 : switch (RegisterClass) {
4720 : case MCK_GPRsp:
4721 : return ARMAsmParser::Match_GPRsp;
4722 : case MCK_QPR_8:
4723 : return ARMAsmParser::Match_QPR_8;
4724 : case MCK_DPR_8:
4725 : return ARMAsmParser::Match_DPR_8;
4726 : case MCK_QPR_VFP2:
4727 : return ARMAsmParser::Match_QPR_VFP2;
4728 : case MCK_hGPR:
4729 : return ARMAsmParser::Match_hGPR;
4730 : case MCK_tGPR:
4731 : return ARMAsmParser::Match_tGPR;
4732 : case MCK_rGPR:
4733 : return ARMAsmParser::Match_rGPR;
4734 : case MCK_GPRnopc:
4735 : return ARMAsmParser::Match_GPRnopc;
4736 : case MCK_DPR_VFP2:
4737 : return ARMAsmParser::Match_DPR_VFP2;
4738 : case MCK_GPR:
4739 : return ARMAsmParser::Match_GPR;
4740 : case MCK_GPRwithAPSR:
4741 : return ARMAsmParser::Match_GPRwithAPSR;
4742 : case MCK_QPR:
4743 : return ARMAsmParser::Match_QPR;
4744 : case MCK_SPR_8:
4745 : return ARMAsmParser::Match_SPR_8;
4746 : case MCK_DPR:
4747 : return ARMAsmParser::Match_DPR;
4748 : case MCK_HPR:
4749 : return ARMAsmParser::Match_SPR;
4750 : default:
4751 : return MCTargetAsmParser::Match_InvalidOperand;
4752 : }
4753 : }
4754 :
4755 234240 : static MatchClassKind matchTokenString(StringRef Name) {
4756 234240 : switch (Name.size()) {
4757 : default: break;
4758 3693 : case 1: // 6 strings to match.
4759 : switch (Name[0]) {
4760 : default: break;
4761 : case '!': // 1 string to match.
4762 : return MCK__EXCLAIM_; // "!"
4763 0 : case '[': // 1 string to match.
4764 0 : return MCK__91_; // "["
4765 0 : case ']': // 1 string to match.
4766 0 : return MCK__93_; // "]"
4767 8 : case '^': // 1 string to match.
4768 8 : return MCK__94_; // "^"
4769 0 : case '{': // 1 string to match.
4770 0 : return MCK__123_; // "{"
4771 0 : case '}': // 1 string to match.
4772 0 : return MCK__125_; // "}"
4773 : }
4774 : break;
4775 44505 : case 2: // 5 strings to match.
4776 : switch (Name[0]) {
4777 : default: break;
4778 0 : case '#': // 1 string to match.
4779 0 : if (Name[1] != '0')
4780 : break;
4781 : return MCK__35_0; // "#0"
4782 44505 : case '.': // 4 strings to match.
4783 : switch (Name[1]) {
4784 : default: break;
4785 : case '8': // 1 string to match.
4786 : return MCK__DOT_8; // ".8"
4787 56 : case 'd': // 1 string to match.
4788 56 : return MCK__DOT_d; // ".d"
4789 52 : case 'f': // 1 string to match.
4790 52 : return MCK__DOT_f; // ".f"
4791 3042 : case 'w': // 1 string to match.
4792 3042 : return MCK__DOT_w; // ".w"
4793 : }
4794 : break;
4795 : }
4796 : break;
4797 97654 : case 3: // 7 strings to match.
4798 97654 : if (Name[0] != '.')
4799 : break;
4800 : switch (Name[1]) {
4801 : default: break;
4802 34939 : case '1': // 1 string to match.
4803 34939 : if (Name[2] != '6')
4804 : break;
4805 : return MCK__DOT_16; // ".16"
4806 43816 : case '3': // 1 string to match.
4807 43816 : if (Name[2] != '2')
4808 : break;
4809 : return MCK__DOT_32; // ".32"
4810 9138 : case '6': // 1 string to match.
4811 9138 : if (Name[2] != '4')
4812 : break;
4813 : return MCK__DOT_64; // ".64"
4814 1415 : case 'i': // 1 string to match.
4815 1415 : if (Name[2] != '8')
4816 : break;
4817 : return MCK__DOT_i8; // ".i8"
4818 864 : case 'p': // 1 string to match.
4819 864 : if (Name[2] != '8')
4820 : break;
4821 : return MCK__DOT_p8; // ".p8"
4822 3420 : case 's': // 1 string to match.
4823 3420 : if (Name[2] != '8')
4824 : break;
4825 : return MCK__DOT_s8; // ".s8"
4826 4062 : case 'u': // 1 string to match.
4827 4062 : if (Name[2] != '8')
4828 : break;
4829 : return MCK__DOT_u8; // ".u8"
4830 : }
4831 : break;
4832 88388 : case 4: // 14 strings to match.
4833 88388 : if (Name[0] != '.')
4834 : break;
4835 : switch (Name[1]) {
4836 : default: break;
4837 47609 : case 'f': // 3 strings to match.
4838 : switch (Name[2]) {
4839 : default: break;
4840 26734 : case '1': // 1 string to match.
4841 26734 : if (Name[3] != '6')
4842 : break;
4843 : return MCK__DOT_f16; // ".f16"
4844 12339 : case '3': // 1 string to match.
4845 12339 : if (Name[3] != '2')
4846 : break;
4847 : return MCK__DOT_f32; // ".f32"
4848 8536 : case '6': // 1 string to match.
4849 8536 : if (Name[3] != '4')
4850 : break;
4851 : return MCK__DOT_f64; // ".f64"
4852 : }
4853 : break;
4854 5078 : case 'i': // 3 strings to match.
4855 : switch (Name[2]) {
4856 : default: break;
4857 1470 : case '1': // 1 string to match.
4858 1470 : if (Name[3] != '6')
4859 : break;
4860 : return MCK__DOT_i16; // ".i16"
4861 2482 : case '3': // 1 string to match.
4862 2482 : if (Name[3] != '2')
4863 : break;
4864 : return MCK__DOT_i32; // ".i32"
4865 1126 : case '6': // 1 string to match.
4866 1126 : if (Name[3] != '4')
4867 : break;
4868 : return MCK__DOT_i64; // ".i64"
4869 : }
4870 : break;
4871 255 : case 'p': // 2 strings to match.
4872 : switch (Name[2]) {
4873 : default: break;
4874 242 : case '1': // 1 string to match.
4875 242 : if (Name[3] != '6')
4876 : break;
4877 : return MCK__DOT_p16; // ".p16"
4878 13 : case '6': // 1 string to match.
4879 13 : if (Name[3] != '4')
4880 : break;
4881 : return MCK__DOT_p64; // ".p64"
4882 : }
4883 : break;
4884 15808 : case 's': // 3 strings to match.
4885 : switch (Name[2]) {
4886 : default: break;
4887 7220 : case '1': // 1 string to match.
4888 7220 : if (Name[3] != '6')
4889 : break;
4890 : return MCK__DOT_s16; // ".s16"
4891 7253 : case '3': // 1 string to match.
4892 7253 : if (Name[3] != '2')
4893 : break;
4894 : return MCK__DOT_s32; // ".s32"
4895 1335 : case '6': // 1 string to match.
4896 1335 : if (Name[3] != '4')
4897 : break;
4898 : return MCK__DOT_s64; // ".s64"
4899 : }
4900 : break;
4901 19638 : case 'u': // 3 strings to match.
4902 : switch (Name[2]) {
4903 : default: break;
4904 8671 : case '1': // 1 string to match.
4905 8671 : if (Name[3] != '6')
4906 : break;
4907 : return MCK__DOT_u16; // ".u16"
4908 8972 : case '3': // 1 string to match.
4909 8972 : if (Name[3] != '2')
4910 : break;
4911 : return MCK__DOT_u32; // ".u32"
4912 1995 : case '6': // 1 string to match.
4913 1995 : if (Name[3] != '4')
4914 : break;
4915 : return MCK__DOT_u64; // ".u64"
4916 : }
4917 : break;
4918 : }
4919 : break;
4920 : }
4921 : return InvalidMatchClass;
4922 : }
4923 :
4924 : /// isSubclass - Compute whether \p A is a subclass of \p B.
4925 917886 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
4926 917886 : if (A == B)
4927 : return true;
4928 :
4929 821606 : switch (A) {
4930 : default:
4931 : return false;
4932 :
4933 56 : case MCK__DOT_d:
4934 56 : switch (B) {
4935 : default: return false;
4936 0 : case MCK__DOT_f64: return true;
4937 12 : case MCK__DOT_64: return true;
4938 : }
4939 :
4940 52 : case MCK__DOT_f:
4941 52 : switch (B) {
4942 : default: return false;
4943 0 : case MCK__DOT_f32: return true;
4944 14 : case MCK__DOT_32: return true;
4945 : }
4946 :
4947 13970 : case MCK__DOT_s16:
4948 13970 : switch (B) {
4949 : default: return false;
4950 60 : case MCK__DOT_i16: return true;
4951 73 : case MCK__DOT_16: return true;
4952 : }
4953 :
4954 14795 : case MCK__DOT_s32:
4955 14795 : switch (B) {
4956 : default: return false;
4957 40 : case MCK__DOT_i32: return true;
4958 61 : case MCK__DOT_32: return true;
4959 : }
4960 :
4961 2676 : case MCK__DOT_s64:
4962 2676 : switch (B) {
4963 : default: return false;
4964 7 : case MCK__DOT_i64: return true;
4965 12 : case MCK__DOT_64: return true;
4966 : }
4967 :
4968 6112 : case MCK__DOT_s8:
4969 6112 : switch (B) {
4970 : default: return false;
4971 15 : case MCK__DOT_i8: return true;
4972 82 : case MCK__DOT_8: return true;
4973 : }
4974 :
4975 13112 : case MCK__DOT_u16:
4976 13112 : switch (B) {
4977 : default: return false;
4978 65 : case MCK__DOT_i16: return true;
4979 216 : case MCK__DOT_16: return true;
4980 : }
4981 :
4982 14049 : case MCK__DOT_u32:
4983 14049 : switch (B) {
4984 : default: return false;
4985 59 : case MCK__DOT_i32: return true;
4986 150 : case MCK__DOT_32: return true;
4987 : }
4988 :
4989 2697 : case MCK__DOT_u64:
4990 2697 : switch (B) {
4991 : default: return false;
4992 16 : case MCK__DOT_i64: return true;
4993 12 : case MCK__DOT_64: return true;
4994 : }
4995 :
4996 5183 : case MCK__DOT_u8:
4997 5183 : switch (B) {
4998 : default: return false;
4999 12 : case MCK__DOT_i8: return true;
5000 98 : case MCK__DOT_8: return true;
5001 : }
5002 :
5003 23715 : case MCK__DOT_f32:
5004 23715 : return B == MCK__DOT_32;
5005 :
5006 11987 : case MCK__DOT_f64:
5007 11987 : return B == MCK__DOT_64;
5008 :
5009 3552 : case MCK__DOT_i16:
5010 3552 : return B == MCK__DOT_16;
5011 :
5012 4567 : case MCK__DOT_i32:
5013 4567 : return B == MCK__DOT_32;
5014 :
5015 2275 : case MCK__DOT_i64:
5016 2275 : return B == MCK__DOT_64;
5017 :
5018 2425 : case MCK__DOT_i8:
5019 2425 : return B == MCK__DOT_8;
5020 :
5021 242 : case MCK__DOT_p16:
5022 242 : return B == MCK__DOT_16;
5023 :
5024 1098 : case MCK__DOT_p8:
5025 1098 : return B == MCK__DOT_8;
5026 :
5027 1565 : case MCK_Reg11:
5028 : switch (B) {
5029 : default: return false;
5030 : case MCK_tcGPR: return true;
5031 : case MCK_Reg10: return true;
5032 : case MCK_Reg8: return true;
5033 : case MCK_hGPR: return true;
5034 : case MCK_rGPR: return true;
5035 : case MCK_GPRnopc: return true;
5036 : case MCK_GPR: return true;
5037 : case MCK_GPRwithAPSR: return true;
5038 : }
5039 :
5040 0 : case MCK_Reg59:
5041 : switch (B) {
5042 : default: return false;
5043 : case MCK_Reg60: return true;
5044 : case MCK_Reg61: return true;
5045 : case MCK_Reg62: return true;
5046 : case MCK_Reg63: return true;
5047 : case MCK_Reg64: return true;
5048 : case MCK_Reg65: return true;
5049 : case MCK_Reg66: return true;
5050 : case MCK_QQQQPR: return true;
5051 : }
5052 :
5053 0 : case MCK_Reg75:
5054 0 : switch (B) {
5055 : default: return false;
5056 0 : case MCK_Reg72: return true;
5057 0 : case MCK_Reg74: return true;
5058 0 : case MCK_GPRPair: return true;
5059 : }
5060 :
5061 153 : case MCK_APSR_NZCV:
5062 153 : return B == MCK_GPRwithAPSR;
5063 :
5064 5840 : case MCK_GPRsp:
5065 5840 : switch (B) {
5066 : default: return false;
5067 0 : case MCK_Reg8: return true;
5068 0 : case MCK_hGPR: return true;
5069 1275 : case MCK_GPRnopc: return true;
5070 1245 : case MCK_GPR: return true;
5071 0 : case MCK_GPRwithAPSR: return true;
5072 : }
5073 :
5074 2399 : case MCK_LR:
5075 : switch (B) {
5076 : default: return false;
5077 : case MCK_Reg10: return true;
5078 : case MCK_Reg8: return true;
5079 : case MCK_hGPR: return true;
5080 : case MCK_rGPR: return true;
5081 : case MCK_GPRnopc: return true;
5082 : case MCK_GPR: return true;
5083 : case MCK_GPRwithAPSR: return true;
5084 : }
5085 :
5086 3209 : case MCK_PC:
5087 3209 : switch (B) {
5088 : default: return false;
5089 0 : case MCK_hGPR: return true;
5090 0 : case MCK_tGPRwithpc: return true;
5091 573 : case MCK_GPR: return true;
5092 : }
5093 :
5094 0 : case MCK_Reg60:
5095 : switch (B) {
5096 : default: return false;
5097 : case MCK_Reg61: return true;
5098 : case MCK_Reg62: return true;
5099 : case MCK_Reg63: return true;
5100 : case MCK_Reg64: return true;
5101 : case MCK_Reg65: return true;
5102 : case MCK_Reg66: return true;
5103 : case MCK_QQQQPR: return true;
5104 : }
5105 :
5106 7 : case MCK_Reg68:
5107 7 : switch (B) {
5108 : default: return false;
5109 0 : case MCK_Reg72: return true;
5110 0 : case MCK_Reg69: return true;
5111 0 : case MCK_Reg70: return true;
5112 6 : case MCK_GPRPair: return true;
5113 : }
5114 :
5115 4 : case MCK_Reg73:
5116 4 : switch (B) {
5117 : default: return false;
5118 0 : case MCK_Reg74: return true;
5119 0 : case MCK_Reg70: return true;
5120 4 : case MCK_GPRPair: return true;
5121 : }
5122 :
5123 0 : case MCK_Reg100:
5124 : switch (B) {
5125 : default: return false;
5126 : case MCK_Reg101: return true;
5127 : case MCK_Reg102: return true;
5128 : case MCK_Reg57: return true;
5129 : case MCK_Reg58: return true;
5130 : case MCK_Reg103: return true;
5131 : case MCK_Reg55: return true;
5132 : case MCK_Reg104: return true;
5133 : case MCK_Reg56: return true;
5134 : case MCK_Reg105: return true;
5135 : case MCK_Reg53: return true;
5136 : case MCK_Reg54: return true;
5137 : case MCK_Reg106: return true;
5138 : case MCK_Reg51: return true;
5139 : case MCK_Reg52: return true;
5140 : case MCK_DQuad: return true;
5141 : }
5142 :
5143 0 : case MCK_Reg45:
5144 : switch (B) {
5145 : default: return false;
5146 : case MCK_Reg46: return true;
5147 : case MCK_Reg57: return true;
5148 : case MCK_Reg58: return true;
5149 : case MCK_Reg47: return true;
5150 : case MCK_Reg55: return true;
5151 : case MCK_Reg48: return true;
5152 : case MCK_Reg56: return true;
5153 : case MCK_Reg53: return true;
5154 : case MCK_Reg54: return true;
5155 : case MCK_Reg51: return true;
5156 : case MCK_QQPR: return true;
5157 : case MCK_Reg52: return true;
5158 : case MCK_DQuad: return true;
5159 : }
5160 :
5161 0 : case MCK_Reg61:
5162 : switch (B) {
5163 : default: return false;
5164 : case MCK_Reg62: return true;
5165 : case MCK_Reg63: return true;
5166 : case MCK_Reg64: return true;
5167 : case MCK_Reg65: return true;
5168 : case MCK_Reg66: return true;
5169 : case MCK_QQQQPR: return true;
5170 : }
5171 :
5172 0 : case MCK_Reg72:
5173 0 : return B == MCK_GPRPair;
5174 :
5175 0 : case MCK_Reg74:
5176 0 : return B == MCK_GPRPair;
5177 :
5178 0 : case MCK_Reg83:
5179 : switch (B) {
5180 : default: return false;
5181 : case MCK_Reg84: return true;
5182 : case MCK_Reg76: return true;
5183 : case MCK_Reg77: return true;
5184 : case MCK_Reg85: return true;
5185 : case MCK_Reg78: return true;
5186 : case MCK_Reg86: return true;
5187 : case MCK_Reg79: return true;
5188 : case MCK_Reg80: return true;
5189 : case MCK_Reg87: return true;
5190 : case MCK_Reg81: return true;
5191 : case MCK_DTriple: return true;
5192 : }
5193 :
5194 0 : case MCK_Reg88:
5195 : switch (B) {
5196 : default: return false;
5197 : case MCK_Reg89: return true;
5198 : case MCK_Reg76: return true;
5199 : case MCK_Reg77: return true;
5200 : case MCK_Reg90: return true;
5201 : case MCK_Reg78: return true;
5202 : case MCK_Reg91: return true;
5203 : case MCK_Reg79: return true;
5204 : case MCK_Reg80: return true;
5205 : case MCK_Reg92: return true;
5206 : case MCK_Reg81: return true;
5207 : case MCK_DTriple: return true;
5208 : }
5209 :
5210 0 : case MCK_Reg101:
5211 : switch (B) {
5212 : default: return false;
5213 : case MCK_Reg102: return true;
5214 : case MCK_Reg58: return true;
5215 : case MCK_Reg103: return true;
5216 : case MCK_Reg55: return true;
5217 : case MCK_Reg104: return true;
5218 : case MCK_Reg56: return true;
5219 : case MCK_Reg105: return true;
5220 : case MCK_Reg53: return true;
5221 : case MCK_Reg54: return true;
5222 : case MCK_Reg106: return true;
5223 : case MCK_Reg51: return true;
5224 : case MCK_Reg52: return true;
5225 : case MCK_DQuad: return true;
5226 : }
5227 :
5228 94546 : case MCK_Reg0:
5229 94546 : switch (B) {
5230 : default: return false;
5231 175 : case MCK_tcGPR: return true;
5232 14441 : case MCK_tGPR: return true;
5233 0 : case MCK_tGPRwithpc: return true;
5234 19564 : case MCK_rGPR: return true;
5235 15244 : case MCK_GPRnopc: return true;
5236 19411 : case MCK_GPR: return true;
5237 79 : case MCK_GPRwithAPSR: return true;
5238 : }
5239 :
5240 0 : case MCK_Reg46:
5241 : switch (B) {
5242 : default: return false;
5243 : case MCK_Reg47: return true;
5244 : case MCK_Reg55: return true;
5245 : case MCK_Reg48: return true;
5246 : case MCK_Reg56: return true;
5247 : case MCK_Reg53: return true;
5248 : case MCK_Reg54: return true;
5249 : case MCK_Reg51: return true;
5250 : case MCK_QQPR: return true;
5251 : case MCK_Reg52: return true;
5252 : case MCK_DQuad: return true;
5253 : }
5254 :
5255 0 : case MCK_Reg62:
5256 : switch (B) {
5257 : default: return false;
5258 : case MCK_Reg63: return true;
5259 : case MCK_Reg64: return true;
5260 : case MCK_Reg65: return true;
5261 : case MCK_Reg66: return true;
5262 : case MCK_QQQQPR: return true;
5263 : }
5264 :
5265 13 : case MCK_Reg69:
5266 13 : switch (B) {
5267 : default: return false;
5268 0 : case MCK_Reg70: return true;
5269 12 : case MCK_GPRPair: return true;
5270 : }
5271 :
5272 0 : case MCK_Reg84:
5273 : switch (B) {
5274 : default: return false;
5275 : case MCK_Reg77: return true;
5276 : case MCK_Reg85: return true;
5277 : case MCK_Reg78: return true;
5278 : case MCK_Reg86: return true;
5279 : case MCK_Reg79: return true;
5280 : case MCK_Reg80: return true;
5281 : case MCK_Reg87: return true;
5282 : case MCK_Reg81: return true;
5283 : case MCK_DTriple: return true;
5284 : }
5285 :
5286 0 : case MCK_Reg89:
5287 : switch (B) {
5288 : default: return false;
5289 : case MCK_Reg90: return true;
5290 : case MCK_Reg78: return true;
5291 : case MCK_Reg91: return true;
5292 : case MCK_Reg79: return true;
5293 : case MCK_Reg80: return true;
5294 : case MCK_Reg92: return true;
5295 : case MCK_Reg81: return true;
5296 : case MCK_DTriple: return true;
5297 : }
5298 :
5299 0 : case MCK_Reg93:
5300 0 : switch (B) {
5301 : default: return false;
5302 0 : case MCK_Reg94: return true;
5303 0 : case MCK_Reg95: return true;
5304 0 : case MCK_Reg96: return true;
5305 0 : case MCK_Reg97: return true;
5306 0 : case MCK_Reg98: return true;
5307 0 : case MCK_DTripleSpc: return true;
5308 : }
5309 :
5310 0 : case MCK_Reg102:
5311 : switch (B) {
5312 : default: return false;
5313 : case MCK_Reg103: return true;
5314 : case MCK_Reg104: return true;
5315 : case MCK_Reg56: return true;
5316 : case MCK_Reg105: return true;
5317 : case MCK_Reg53: return true;
5318 : case MCK_Reg54: return true;
5319 : case MCK_Reg106: return true;
5320 : case MCK_Reg51: return true;
5321 : case MCK_Reg52: return true;
5322 : case MCK_DQuad: return true;
5323 : }
5324 :
5325 14488 : case MCK_QPR_8:
5326 : switch (B) {
5327 : default: return false;
5328 : case MCK_Reg26: return true;
5329 : case MCK_Reg27: return true;
5330 : case MCK_QPR_VFP2: return true;
5331 : case MCK_Reg24: return true;
5332 : case MCK_Reg25: return true;
5333 : case MCK_QPR: return true;
5334 : case MCK_DPair: return true;
5335 : }
5336 :
5337 0 : case MCK_Reg57:
5338 : switch (B) {
5339 : default: return false;
5340 : case MCK_Reg58: return true;
5341 : case MCK_Reg55: return true;
5342 : case MCK_Reg56: return true;
5343 : case MCK_Reg53: return true;
5344 : case MCK_Reg54: return true;
5345 : case MCK_Reg51: return true;
5346 : case MCK_Reg52: return true;
5347 : case MCK_DQuad: return true;
5348 : }
5349 :
5350 0 : case MCK_Reg63:
5351 : switch (B) {
5352 : default: return false;
5353 : case MCK_Reg64: return true;
5354 : case MCK_Reg65: return true;
5355 : case MCK_Reg66: return true;
5356 : case MCK_QQQQPR: return true;
5357 : }
5358 :
5359 223 : case MCK_tcGPR:
5360 : switch (B) {
5361 : default: return false;
5362 : case MCK_rGPR: return true;
5363 : case MCK_GPRnopc: return true;
5364 : case MCK_GPR: return true;
5365 : case MCK_GPRwithAPSR: return true;
5366 : }
5367 :
5368 14485 : case MCK_Reg10:
5369 : switch (B) {
5370 : default: return false;
5371 : case MCK_Reg8: return true;
5372 : case MCK_hGPR: return true;
5373 : case MCK_rGPR: return true;
5374 : case MCK_GPRnopc: return true;
5375 : case MCK_GPR: return true;
5376 : case MCK_GPRwithAPSR: return true;
5377 : }
5378 :
5379 0 : case MCK_Reg40:
5380 0 : switch (B) {
5381 : default: return false;
5382 0 : case MCK_Reg41: return true;
5383 0 : case MCK_Reg42: return true;
5384 0 : case MCK_Reg43: return true;
5385 0 : case MCK_DPairSpc: return true;
5386 : }
5387 :
5388 0 : case MCK_Reg58:
5389 : switch (B) {
5390 : default: return false;
5391 : case MCK_Reg55: return true;
5392 : case MCK_Reg56: return true;
5393 : case MCK_Reg53: return true;
5394 : case MCK_Reg54: return true;
5395 : case MCK_Reg51: return true;
5396 : case MCK_Reg52: return true;
5397 : case MCK_DQuad: return true;
5398 : }
5399 :
5400 0 : case MCK_Reg64:
5401 : switch (B) {
5402 : default: return false;
5403 : case MCK_Reg65: return true;
5404 : case MCK_Reg66: return true;
5405 : case MCK_QQQQPR: return true;
5406 : }
5407 :
5408 0 : case MCK_Reg70:
5409 0 : return B == MCK_GPRPair;
5410 :
5411 0 : case MCK_Reg76:
5412 0 : switch (B) {
5413 : default: return false;
5414 0 : case MCK_Reg77: return true;
5415 0 : case MCK_Reg78: return true;
5416 0 : case MCK_Reg79: return true;
5417 0 : case MCK_Reg80: return true;
5418 0 : case MCK_Reg81: return true;
5419 0 : case MCK_DTriple: return true;
5420 : }
5421 :
5422 0 : case MCK_Reg94:
5423 : switch (B) {
5424 : default: return false;
5425 : case MCK_Reg95: return true;
5426 : case MCK_Reg96: return true;
5427 : case MCK_Reg97: return true;
5428 : case MCK_Reg98: return true;
5429 : case MCK_DTripleSpc: return true;
5430 : }
5431 :
5432 0 : case MCK_Reg103:
5433 : switch (B) {
5434 : default: return false;
5435 : case MCK_Reg104: return true;
5436 : case MCK_Reg105: return true;
5437 : case MCK_Reg53: return true;
5438 : case MCK_Reg54: return true;
5439 : case MCK_Reg106: return true;
5440 : case MCK_Reg51: return true;
5441 : case MCK_Reg52: return true;
5442 : case MCK_DQuad: return true;
5443 : }
5444 :
5445 0 : case MCK_Reg8:
5446 : switch (B) {
5447 : default: return false;
5448 : case MCK_hGPR: return true;
5449 : case MCK_GPRnopc: return true;
5450 : case MCK_GPR: return true;
5451 : case MCK_GPRwithAPSR: return true;
5452 : }
5453 :
5454 0 : case MCK_Reg26:
5455 0 : switch (B) {
5456 : default: return false;
5457 0 : case MCK_Reg27: return true;
5458 0 : case MCK_Reg24: return true;
5459 0 : case MCK_Reg25: return true;
5460 0 : case MCK_DPair: return true;
5461 : }
5462 :
5463 0 : case MCK_Reg47:
5464 : switch (B) {
5465 : default: return false;
5466 : case MCK_Reg48: return true;
5467 : case MCK_Reg53: return true;
5468 : case MCK_Reg54: return true;
5469 : case MCK_Reg51: return true;
5470 : case MCK_QQPR: return true;
5471 : case MCK_Reg52: return true;
5472 : case MCK_DQuad: return true;
5473 : }
5474 :
5475 0 : case MCK_Reg55:
5476 : switch (B) {
5477 : default: return false;
5478 : case MCK_Reg56: return true;
5479 : case MCK_Reg53: return true;
5480 : case MCK_Reg54: return true;
5481 : case MCK_Reg51: return true;
5482 : case MCK_Reg52: return true;
5483 : case MCK_DQuad: return true;
5484 : }
5485 :
5486 0 : case MCK_Reg65:
5487 0 : switch (B) {
5488 : default: return false;
5489 0 : case MCK_Reg66: return true;
5490 0 : case MCK_QQQQPR: return true;
5491 : }
5492 :
5493 0 : case MCK_Reg77:
5494 : switch (B) {
5495 : default: return false;
5496 : case MCK_Reg78: return true;
5497 : case MCK_Reg79: return true;
5498 : case MCK_Reg80: return true;
5499 : case MCK_Reg81: return true;
5500 : case MCK_DTriple: return true;
5501 : }
5502 :
5503 0 : case MCK_Reg85:
5504 : switch (B) {
5505 : default: return false;
5506 : case MCK_Reg86: return true;
5507 : case MCK_Reg79: return true;
5508 : case MCK_Reg80: return true;
5509 : case MCK_Reg87: return true;
5510 : case MCK_Reg81: return true;
5511 : case MCK_DTriple: return true;
5512 : }
5513 :
5514 0 : case MCK_Reg90:
5515 : switch (B) {
5516 : default: return false;
5517 : case MCK_Reg91: return true;
5518 : case MCK_Reg79: return true;
5519 : case MCK_Reg80: return true;
5520 : case MCK_Reg92: return true;
5521 : case MCK_Reg81: return true;
5522 : case MCK_DTriple: return true;
5523 : }
5524 :
5525 0 : case MCK_Reg104:
5526 : switch (B) {
5527 : default: return false;
5528 : case MCK_Reg105: return true;
5529 : case MCK_Reg54: return true;
5530 : case MCK_Reg106: return true;
5531 : case MCK_Reg51: return true;
5532 : case MCK_Reg52: return true;
5533 : case MCK_DQuad: return true;
5534 : }
5535 :
5536 0 : case MCK_Reg27:
5537 : switch (B) {
5538 : default: return false;
5539 : case MCK_Reg24: return true;
5540 : case MCK_Reg25: return true;
5541 : case MCK_DPair: return true;
5542 : }
5543 :
5544 0 : case MCK_Reg41:
5545 0 : switch (B) {
5546 : default: return false;
5547 0 : case MCK_Reg42: return true;
5548 0 : case MCK_Reg43: return true;
5549 0 : case MCK_DPairSpc: return true;
5550 : }
5551 :
5552 0 : case MCK_Reg48:
5553 : switch (B) {
5554 : default: return false;
5555 : case MCK_Reg51: return true;
5556 : case MCK_QQPR: return true;
5557 : case MCK_Reg52: return true;
5558 : case MCK_DQuad: return true;
5559 : }
5560 :
5561 0 : case MCK_Reg56:
5562 : switch (B) {
5563 : default: return false;
5564 : case MCK_Reg53: return true;
5565 : case MCK_Reg54: return true;
5566 : case MCK_Reg51: return true;
5567 : case MCK_Reg52: return true;
5568 : case MCK_DQuad: return true;
5569 : }
5570 :
5571 0 : case MCK_Reg66:
5572 0 : return B == MCK_QQQQPR;
5573 :
5574 0 : case MCK_Reg78:
5575 : switch (B) {
5576 : default: return false;
5577 : case MCK_Reg79: return true;
5578 : case MCK_Reg80: return true;
5579 : case MCK_Reg81: return true;
5580 : case MCK_DTriple: return true;
5581 : }
5582 :
5583 0 : case MCK_Reg86:
5584 : switch (B) {
5585 : default: return false;
5586 : case MCK_Reg80: return true;
5587 : case MCK_Reg87: return true;
5588 : case MCK_Reg81: return true;
5589 : case MCK_DTriple: return true;
5590 : }
5591 :
5592 0 : case MCK_Reg91:
5593 : switch (B) {
5594 : default: return false;
5595 : case MCK_Reg92: return true;
5596 : case MCK_Reg81: return true;
5597 : case MCK_DTriple: return true;
5598 : }
5599 :
5600 0 : case MCK_Reg95:
5601 : switch (B) {
5602 : default: return false;
5603 : case MCK_Reg96: return true;
5604 : case MCK_Reg97: return true;
5605 : case MCK_Reg98: return true;
5606 : case MCK_DTripleSpc: return true;
5607 : }
5608 :
5609 0 : case MCK_Reg105:
5610 : switch (B) {
5611 : default: return false;
5612 : case MCK_Reg106: return true;
5613 : case MCK_Reg52: return true;
5614 : case MCK_DQuad: return true;
5615 : }
5616 :
5617 26547 : case MCK_DPR_8:
5618 26547 : switch (B) {
5619 : default: return false;
5620 457 : case MCK_DPR_VFP2: return true;
5621 14940 : case MCK_DPR: return true;
5622 : }
5623 :
5624 4889 : case MCK_QPR_VFP2:
5625 : switch (B) {
5626 : default: return false;
5627 : case MCK_Reg24: return true;
5628 : case MCK_Reg25: return true;
5629 : case MCK_QPR: return true;
5630 : case MCK_DPair: return true;
5631 : }
5632 :
5633 0 : case MCK_hGPR:
5634 0 : return B == MCK_GPR;
5635 :
5636 33927 : case MCK_tGPR:
5637 : switch (B) {
5638 : default: return false;
5639 : case MCK_tGPRwithpc: return true;
5640 : case MCK_rGPR: return true;
5641 : case MCK_GPRnopc: return true;
5642 : case MCK_GPR: return true;
5643 : case MCK_GPRwithAPSR: return true;
5644 : }
5645 :
5646 0 : case MCK_tGPRwithpc:
5647 0 : return B == MCK_GPR;
5648 :
5649 0 : case MCK_Reg96:
5650 : switch (B) {
5651 : default: return false;
5652 : case MCK_Reg97: return true;
5653 : case MCK_Reg98: return true;
5654 : case MCK_DTripleSpc: return true;
5655 : }
5656 :
5657 0 : case MCK_Reg53:
5658 : switch (B) {
5659 : default: return false;
5660 : case MCK_Reg54: return true;
5661 : case MCK_Reg51: return true;
5662 : case MCK_Reg52: return true;
5663 : case MCK_DQuad: return true;
5664 : }
5665 :
5666 0 : case MCK_Reg42:
5667 0 : switch (B) {
5668 : default: return false;
5669 0 : case MCK_Reg43: return true;
5670 0 : case MCK_DPairSpc: return true;
5671 : }
5672 :
5673 0 : case MCK_Reg54:
5674 : switch (B) {
5675 : default: return false;
5676 : case MCK_Reg51: return true;
5677 : case MCK_Reg52: return true;
5678 : case MCK_DQuad: return true;
5679 : }
5680 :
5681 0 : case MCK_Reg79:
5682 : switch (B) {
5683 : default: return false;
5684 : case MCK_Reg80: return true;
5685 : case MCK_Reg81: return true;
5686 : case MCK_DTriple: return true;
5687 : }
5688 :
5689 0 : case MCK_Reg97:
5690 0 : switch (B) {
5691 : default: return false;
5692 0 : case MCK_Reg98: return true;
5693 0 : case MCK_DTripleSpc: return true;
5694 : }
5695 :
5696 0 : case MCK_Reg106:
5697 0 : return B == MCK_DQuad;
5698 :
5699 1024 : case MCK_rGPR:
5700 : switch (B) {
5701 : default: return false;
5702 : case MCK_GPRnopc: return true;
5703 : case MCK_GPR: return true;
5704 : case MCK_GPRwithAPSR: return true;
5705 : }
5706 :
5707 0 : case MCK_Reg24:
5708 0 : switch (B) {
5709 : default: return false;
5710 0 : case MCK_Reg25: return true;
5711 0 : case MCK_DPair: return true;
5712 : }
5713 :
5714 0 : case MCK_Reg51:
5715 0 : switch (B) {
5716 : default: return false;
5717 0 : case MCK_Reg52: return true;
5718 0 : case MCK_DQuad: return true;
5719 : }
5720 :
5721 0 : case MCK_Reg80:
5722 0 : switch (B) {
5723 : default: return false;
5724 0 : case MCK_Reg81: return true;
5725 0 : case MCK_DTriple: return true;
5726 : }
5727 :
5728 0 : case MCK_Reg87:
5729 0 : return B == MCK_DTriple;
5730 :
5731 0 : case MCK_Reg92:
5732 0 : return B == MCK_DTriple;
5733 :
5734 302 : case MCK_GPRnopc:
5735 302 : switch (B) {
5736 : default: return false;
5737 0 : case MCK_GPR: return true;
5738 0 : case MCK_GPRwithAPSR: return true;
5739 : }
5740 :
5741 0 : case MCK_QQPR:
5742 0 : return B == MCK_DQuad;
5743 :
5744 0 : case MCK_Reg25:
5745 0 : return B == MCK_DPair;
5746 :
5747 0 : case MCK_Reg43:
5748 0 : return B == MCK_DPairSpc;
5749 :
5750 0 : case MCK_Reg52:
5751 0 : return B == MCK_DQuad;
5752 :
5753 0 : case MCK_Reg81:
5754 0 : return B == MCK_DTriple;
5755 :
5756 0 : case MCK_Reg98:
5757 0 : return B == MCK_DTripleSpc;
5758 :
5759 3722 : case MCK_DPR_VFP2:
5760 3722 : return B == MCK_DPR;
5761 :
5762 5810 : case MCK_QPR:
5763 5810 : return B == MCK_DPair;
5764 :
5765 11933 : case MCK_SPR_8:
5766 11933 : return B == MCK_HPR;
5767 : }
5768 : }
5769 :
5770 1228808 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
5771 : ARMOperand &Operand = (ARMOperand&)GOp;
5772 1228808 : if (Kind == InvalidMatchClass)
5773 : return MCTargetAsmParser::Match_InvalidOperand;
5774 :
5775 1176357 : if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
5776 468480 : return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
5777 : MCTargetAsmParser::Match_Success :
5778 : MCTargetAsmParser::Match_InvalidOperand;
5779 :
5780 942117 : switch (Kind) {
5781 : default: break;
5782 : // 'AM2OffsetImm' class
5783 : case MCK_AM2OffsetImm: {
5784 : DiagnosticPredicate DP(Operand.isAM2OffsetImm());
5785 106 : if (DP.isMatch())
5786 : return MCTargetAsmParser::Match_Success;
5787 : break;
5788 : }
5789 : // 'AM3Offset' class
5790 83 : case MCK_AM3Offset: {
5791 83 : DiagnosticPredicate DP(Operand.isAM3Offset());
5792 83 : if (DP.isMatch())
5793 : return MCTargetAsmParser::Match_Success;
5794 : break;
5795 : }
5796 : // 'ARMBranchTarget' class
5797 : case MCK_ARMBranchTarget: {
5798 : DiagnosticPredicate DP(Operand.isARMBranchTarget());
5799 1029 : if (DP.isMatch())
5800 : return MCTargetAsmParser::Match_Success;
5801 : break;
5802 : }
5803 : // 'AddrMode3' class
5804 711 : case MCK_AddrMode3: {
5805 711 : DiagnosticPredicate DP(Operand.isAddrMode3());
5806 711 : if (DP.isMatch())
5807 : return MCTargetAsmParser::Match_Success;
5808 : break;
5809 : }
5810 : // 'AddrMode5' class
5811 2250 : case MCK_AddrMode5: {
5812 2250 : DiagnosticPredicate DP(Operand.isAddrMode5());
5813 2250 : if (DP.isMatch())
5814 : return MCTargetAsmParser::Match_Success;
5815 : break;
5816 : }
5817 : // 'AddrMode5FP16' class
5818 43 : case MCK_AddrMode5FP16: {
5819 43 : DiagnosticPredicate DP(Operand.isAddrMode5FP16());
5820 43 : if (DP.isMatch())
5821 : return MCTargetAsmParser::Match_Success;
5822 : break;
5823 : }
5824 : // 'AlignedMemory16' class
5825 1262 : case MCK_AlignedMemory16: {
5826 1262 : DiagnosticPredicate DP(Operand.isAlignedMemory16());
5827 1262 : if (DP.isMatch())
5828 : return MCTargetAsmParser::Match_Success;
5829 : if (DP.isNearMatch())
5830 894 : return ARMAsmParser::Match_AlignedMemory16;
5831 : break;
5832 : }
5833 : // 'AlignedMemory32' class
5834 1994 : case MCK_AlignedMemory32: {
5835 1994 : DiagnosticPredicate DP(Operand.isAlignedMemory32());
5836 1994 : if (DP.isMatch())
5837 : return MCTargetAsmParser::Match_Success;
5838 : if (DP.isNearMatch())
5839 1408 : return ARMAsmParser::Match_AlignedMemory32;
5840 : break;
5841 : }
5842 : // 'AlignedMemory64' class
5843 12694 : case MCK_AlignedMemory64: {
5844 12694 : DiagnosticPredicate DP(Operand.isAlignedMemory64());
5845 12694 : if (DP.isMatch())
5846 : return MCTargetAsmParser::Match_Success;
5847 : if (DP.isNearMatch())
5848 9110 : return ARMAsmParser::Match_AlignedMemory64;
5849 : break;
5850 : }
5851 : // 'AlignedMemory64or128' class
5852 8472 : case MCK_AlignedMemory64or128: {
5853 8472 : DiagnosticPredicate DP(Operand.isAlignedMemory64or128());
5854 8472 : if (DP.isMatch())
5855 : return MCTargetAsmParser::Match_Success;
5856 : if (DP.isNearMatch())
5857 4656 : return ARMAsmParser::Match_AlignedMemory64or128;
5858 : break;
5859 : }
5860 : // 'AlignedMemory64or128or256' class
5861 8721 : case MCK_AlignedMemory64or128or256: {
5862 8721 : DiagnosticPredicate DP(Operand.isAlignedMemory64or128or256());
5863 8721 : if (DP.isMatch())
5864 : return MCTargetAsmParser::Match_Success;
5865 : if (DP.isNearMatch())
5866 3376 : return ARMAsmParser::Match_AlignedMemory64or128or256;
5867 : break;
5868 : }
5869 : // 'AlignedMemoryNone' class
5870 : case MCK_AlignedMemoryNone: {
5871 : DiagnosticPredicate DP(Operand.isAlignedMemoryNone());
5872 4099 : if (DP.isMatch())
5873 : return MCTargetAsmParser::Match_Success;
5874 : if (DP.isNearMatch())
5875 3442 : return ARMAsmParser::Match_AlignedMemoryNone;
5876 : break;
5877 : }
5878 : // 'AlignedMemory' class
5879 : case MCK_AlignedMemory: {
5880 : DiagnosticPredicate DP(Operand.isAlignedMemory());
5881 0 : if (DP.isMatch())
5882 : return MCTargetAsmParser::Match_Success;
5883 : break;
5884 : }
5885 : // 'DupAlignedMemory16' class
5886 1686 : case MCK_DupAlignedMemory16: {
5887 1686 : DiagnosticPredicate DP(Operand.isDupAlignedMemory16());
5888 1686 : if (DP.isMatch())
5889 : return MCTargetAsmParser::Match_Success;
5890 : if (DP.isNearMatch())
5891 1161 : return ARMAsmParser::Match_DupAlignedMemory16;
5892 : break;
5893 : }
5894 : // 'DupAlignedMemory32' class
5895 2558 : case MCK_DupAlignedMemory32: {
5896 2558 : DiagnosticPredicate DP(Operand.isDupAlignedMemory32());
5897 2558 : if (DP.isMatch())
5898 : return MCTargetAsmParser::Match_Success;
5899 : if (DP.isNearMatch())
5900 1741 : return ARMAsmParser::Match_DupAlignedMemory32;
5901 : break;
5902 : }
5903 : // 'DupAlignedMemory64' class
5904 1743 : case MCK_DupAlignedMemory64: {
5905 1743 : DiagnosticPredicate DP(Operand.isDupAlignedMemory64());
5906 1743 : if (DP.isMatch())
5907 : return MCTargetAsmParser::Match_Success;
5908 : if (DP.isNearMatch())
5909 1173 : return ARMAsmParser::Match_DupAlignedMemory64;
5910 : break;
5911 : }
5912 : // 'DupAlignedMemory64or128' class
5913 793 : case MCK_DupAlignedMemory64or128: {
5914 793 : DiagnosticPredicate DP(Operand.isDupAlignedMemory64or128());
5915 793 : if (DP.isMatch())
5916 : return MCTargetAsmParser::Match_Success;
5917 : if (DP.isNearMatch())
5918 421 : return ARMAsmParser::Match_DupAlignedMemory64or128;
5919 : break;
5920 : }
5921 : // 'DupAlignedMemoryNone' class
5922 : case MCK_DupAlignedMemoryNone: {
5923 : DiagnosticPredicate DP(Operand.isDupAlignedMemoryNone());
5924 3476 : if (DP.isMatch())
5925 : return MCTargetAsmParser::Match_Success;
5926 : if (DP.isNearMatch())
5927 2807 : return ARMAsmParser::Match_DupAlignedMemoryNone;
5928 : break;
5929 : }
5930 : // 'AdrLabel' class
5931 33 : case MCK_AdrLabel: {
5932 33 : DiagnosticPredicate DP(Operand.isAdrLabel());
5933 33 : if (DP.isMatch())
5934 : return MCTargetAsmParser::Match_Success;
5935 : break;
5936 : }
5937 : // 'BankedReg' class
5938 654 : case MCK_BankedReg: {
5939 : DiagnosticPredicate DP(Operand.isBankedReg());
5940 654 : if (DP.isMatch())
5941 : return MCTargetAsmParser::Match_Success;
5942 : break;
5943 : }
5944 : // 'Bitfield' class
5945 45 : case MCK_Bitfield: {
5946 : DiagnosticPredicate DP(Operand.isBitfield());
5947 45 : if (DP.isMatch())
5948 : return MCTargetAsmParser::Match_Success;
5949 : break;
5950 : }
5951 : // 'CCOut' class
5952 63866 : case MCK_CCOut: {
5953 : DiagnosticPredicate DP(Operand.isCCOut());
5954 63866 : if (DP.isMatch())
5955 : return MCTargetAsmParser::Match_Success;
5956 : break;
5957 : }
5958 : // 'CondCode' class
5959 313375 : case MCK_CondCode: {
5960 : DiagnosticPredicate DP(Operand.isCondCode());
5961 313375 : if (DP.isMatch())
5962 : return MCTargetAsmParser::Match_Success;
5963 : break;
5964 : }
5965 : // 'CoprocNum' class
5966 3695 : case MCK_CoprocNum: {
5967 : DiagnosticPredicate DP(Operand.isCoprocNum());
5968 3695 : if (DP.isMatch())
5969 : return MCTargetAsmParser::Match_Success;
5970 : break;
5971 : }
5972 : // 'CoprocOption' class
5973 526 : case MCK_CoprocOption: {
5974 : DiagnosticPredicate DP(Operand.isCoprocOption());
5975 526 : if (DP.isMatch())
5976 : return MCTargetAsmParser::Match_Success;
5977 : break;
5978 : }
5979 : // 'CoprocReg' class
5980 3888 : case MCK_CoprocReg: {
5981 : DiagnosticPredicate DP(Operand.isCoprocReg());
5982 3888 : if (DP.isMatch())
5983 : return MCTargetAsmParser::Match_Success;
5984 : break;
5985 : }
5986 : // 'DPRRegList' class
5987 125 : case MCK_DPRRegList: {
5988 : DiagnosticPredicate DP(Operand.isDPRRegList());
5989 125 : if (DP.isMatch())
5990 : return MCTargetAsmParser::Match_Success;
5991 : if (DP.isNearMatch())
5992 50 : return ARMAsmParser::Match_DPR_RegList;
5993 : break;
5994 : }
5995 : // 'FPImm' class
5996 279 : case MCK_FPImm: {
5997 279 : DiagnosticPredicate DP(Operand.isFPImm());
5998 279 : if (DP.isMatch())
5999 : return MCTargetAsmParser::Match_Success;
6000 : break;
6001 : }
6002 : // 'Imm0_15' class
6003 : case MCK_Imm0_15: {
6004 : DiagnosticPredicate DP(Operand.isImmediate<0,15>());
6005 374 : if (DP.isMatch())
6006 : return MCTargetAsmParser::Match_Success;
6007 : if (DP.isNearMatch())
6008 101 : return ARMAsmParser::Match_Imm0_15;
6009 : break;
6010 : }
6011 : // 'Imm0_1' class
6012 : case MCK_Imm0_1: {
6013 : DiagnosticPredicate DP(Operand.isImmediate<0,1>());
6014 47 : if (DP.isMatch())
6015 : return MCTargetAsmParser::Match_Success;
6016 : if (DP.isNearMatch())
6017 33 : return ARMAsmParser::Match_Imm0_1;
6018 : break;
6019 : }
6020 : // 'Imm0_239' class
6021 : case MCK_Imm0_239: {
6022 : DiagnosticPredicate DP(Operand.isImmediate<0,239>());
6023 67 : if (DP.isMatch())
6024 : return MCTargetAsmParser::Match_Success;
6025 : if (DP.isNearMatch())
6026 32 : return ARMAsmParser::Match_Imm0_239;
6027 : break;
6028 : }
6029 : // 'Imm0_255' class
6030 : case MCK_Imm0_255: {
6031 : DiagnosticPredicate DP(Operand.isImmediate<0,255>());
6032 2088 : if (DP.isMatch())
6033 : return MCTargetAsmParser::Match_Success;
6034 : if (DP.isNearMatch())
6035 1882 : return ARMAsmParser::Match_Imm0_255;
6036 : break;
6037 : }
6038 : // 'Imm0_31' class
6039 : case MCK_Imm0_31: {
6040 : DiagnosticPredicate DP(Operand.isImmediate<0,31>());
6041 1417 : if (DP.isMatch())
6042 : return MCTargetAsmParser::Match_Success;
6043 : if (DP.isNearMatch())
6044 758 : return ARMAsmParser::Match_Imm0_31;
6045 : break;
6046 : }
6047 : // 'Imm0_32' class
6048 : case MCK_Imm0_32: {
6049 : DiagnosticPredicate DP(Operand.isImmediate<0,32>());
6050 183 : if (DP.isMatch())
6051 : return MCTargetAsmParser::Match_Success;
6052 : if (DP.isNearMatch())
6053 163 : return ARMAsmParser::Match_Imm0_32;
6054 : break;
6055 : }
6056 : // 'Imm0_3' class
6057 : case MCK_Imm0_3: {
6058 : DiagnosticPredicate DP(Operand.isImmediate<0,3>());
6059 21 : if (DP.isMatch())
6060 : return MCTargetAsmParser::Match_Success;
6061 : if (DP.isNearMatch())
6062 13 : return ARMAsmParser::Match_Imm0_3;
6063 : break;
6064 : }
6065 : // 'Imm0_63' class
6066 : case MCK_Imm0_63: {
6067 : DiagnosticPredicate DP(Operand.isImmediate<0,63>());
6068 26 : if (DP.isMatch())
6069 : return MCTargetAsmParser::Match_Success;
6070 : if (DP.isNearMatch())
6071 14 : return ARMAsmParser::Match_Imm0_63;
6072 : break;
6073 : }
6074 : // 'Imm0_65535' class
6075 : case MCK_Imm0_65535: {
6076 : DiagnosticPredicate DP(Operand.isImmediate<0,65535>());
6077 75 : if (DP.isMatch())
6078 : return MCTargetAsmParser::Match_Success;
6079 : if (DP.isNearMatch())
6080 26 : return ARMAsmParser::Match_Imm0_65535;
6081 : break;
6082 : }
6083 : // 'Imm0_65535Expr' class
6084 : case MCK_Imm0_65535Expr: {
6085 : DiagnosticPredicate DP(Operand.isImm0_65535Expr());
6086 491 : if (DP.isMatch())
6087 : return MCTargetAsmParser::Match_Success;
6088 : if (DP.isNearMatch())
6089 59 : return ARMAsmParser::Match_Imm0_65535Expr;
6090 : break;
6091 : }
6092 : // 'Imm0_7' class
6093 : case MCK_Imm0_7: {
6094 : DiagnosticPredicate DP(Operand.isImmediate<0,7>());
6095 1605 : if (DP.isMatch())
6096 : return MCTargetAsmParser::Match_Success;
6097 : if (DP.isNearMatch())
6098 890 : return ARMAsmParser::Match_Imm0_7;
6099 : break;
6100 : }
6101 : // 'Imm16' class
6102 : case MCK_Imm16: {
6103 : DiagnosticPredicate DP(Operand.isImmediate<16,16>());
6104 6 : if (DP.isMatch())
6105 : return MCTargetAsmParser::Match_Success;
6106 : if (DP.isNearMatch())
6107 4 : return ARMAsmParser::Match_Imm16;
6108 : break;
6109 : }
6110 : // 'Imm1_15' class
6111 : case MCK_Imm1_15: {
6112 : DiagnosticPredicate DP(Operand.isImmediate<1,15>());
6113 30 : if (DP.isMatch())
6114 : return MCTargetAsmParser::Match_Success;
6115 : if (DP.isNearMatch())
6116 14 : return ARMAsmParser::Match_Imm1_15;
6117 : break;
6118 : }
6119 : // 'Imm1_16' class
6120 : case MCK_Imm1_16: {
6121 : DiagnosticPredicate DP(Operand.isImmediate<1,16>());
6122 26 : if (DP.isMatch())
6123 : return MCTargetAsmParser::Match_Success;
6124 : if (DP.isNearMatch())
6125 8 : return ARMAsmParser::Match_ImmRange1_16;
6126 : break;
6127 : }
6128 : // 'Imm1_31' class
6129 : case MCK_Imm1_31: {
6130 : DiagnosticPredicate DP(Operand.isImmediate<1,31>());
6131 335 : if (DP.isMatch())
6132 : return MCTargetAsmParser::Match_Success;
6133 : if (DP.isNearMatch())
6134 258 : return ARMAsmParser::Match_Imm1_31;
6135 : break;
6136 : }
6137 : // 'Imm1_32' class
6138 : case MCK_Imm1_32: {
6139 : DiagnosticPredicate DP(Operand.isImmediate<1,32>());
6140 215 : if (DP.isMatch())
6141 : return MCTargetAsmParser::Match_Success;
6142 : if (DP.isNearMatch())
6143 16 : return ARMAsmParser::Match_ImmRange1_32;
6144 : break;
6145 : }
6146 : // 'Imm1_7' class
6147 : case MCK_Imm1_7: {
6148 : DiagnosticPredicate DP(Operand.isImmediate<1,7>());
6149 22 : if (DP.isMatch())
6150 : return MCTargetAsmParser::Match_Success;
6151 : if (DP.isNearMatch())
6152 16 : return ARMAsmParser::Match_Imm1_7;
6153 : break;
6154 : }
6155 : // 'Imm24bit' class
6156 : case MCK_Imm24bit: {
6157 : DiagnosticPredicate DP(Operand.isImmediate<0,16777215>());
6158 22 : if (DP.isMatch())
6159 : return MCTargetAsmParser::Match_Success;
6160 : if (DP.isNearMatch())
6161 6 : return ARMAsmParser::Match_Imm24bit;
6162 : break;
6163 : }
6164 : // 'Imm256_65535Expr' class
6165 : case MCK_Imm256_65535Expr: {
6166 : DiagnosticPredicate DP(Operand.isImmediate<256,65535>());
6167 168 : if (DP.isMatch())
6168 : return MCTargetAsmParser::Match_Success;
6169 : if (DP.isNearMatch())
6170 158 : return ARMAsmParser::Match_Imm256_65535Expr;
6171 : break;
6172 : }
6173 : // 'Imm32' class
6174 : case MCK_Imm32: {
6175 : DiagnosticPredicate DP(Operand.isImmediate<32,32>());
6176 4 : if (DP.isMatch())
6177 : return MCTargetAsmParser::Match_Success;
6178 : if (DP.isNearMatch())
6179 2 : return ARMAsmParser::Match_Imm32;
6180 : break;
6181 : }
6182 : // 'Imm8' class
6183 : case MCK_Imm8: {
6184 : DiagnosticPredicate DP(Operand.isImmediate<8,8>());
6185 2 : if (DP.isMatch())
6186 : return MCTargetAsmParser::Match_Success;
6187 : if (DP.isNearMatch())
6188 0 : return ARMAsmParser::Match_Imm8;
6189 : break;
6190 : }
6191 : // 'Imm8_255' class
6192 : case MCK_Imm8_255: {
6193 : DiagnosticPredicate DP(Operand.isImmediate<8,255>());
6194 0 : if (DP.isMatch())
6195 : return MCTargetAsmParser::Match_Success;
6196 : if (DP.isNearMatch())
6197 0 : return ARMAsmParser::Match_Imm8_255;
6198 : break;
6199 : }
6200 : // 'Imm' class
6201 3655 : case MCK_Imm: {
6202 : DiagnosticPredicate DP(Operand.isImm());
6203 3655 : if (DP.isMatch())
6204 : return MCTargetAsmParser::Match_Success;
6205 : break;
6206 : }
6207 : // 'InstSyncBarrierOpt' class
6208 36 : case MCK_InstSyncBarrierOpt: {
6209 : DiagnosticPredicate DP(Operand.isInstSyncBarrierOpt());
6210 36 : if (DP.isMatch())
6211 : return MCTargetAsmParser::Match_Success;
6212 : break;
6213 : }
6214 : // 'MSRMask' class
6215 617 : case MCK_MSRMask: {
6216 : DiagnosticPredicate DP(Operand.isMSRMask());
6217 617 : if (DP.isMatch())
6218 : return MCTargetAsmParser::Match_Success;
6219 : break;
6220 : }
6221 : // 'MemBarrierOpt' class
6222 420 : case MCK_MemBarrierOpt: {
6223 : DiagnosticPredicate DP(Operand.isMemBarrierOpt());
6224 420 : if (DP.isMatch())
6225 : return MCTargetAsmParser::Match_Success;
6226 : break;
6227 : }
6228 : // 'MemImm0_1020s4Offset' class
6229 44 : case MCK_MemImm0_1020s4Offset: {
6230 44 : DiagnosticPredicate DP(Operand.isMemImm0_1020s4Offset());
6231 44 : if (DP.isMatch())
6232 : return MCTargetAsmParser::Match_Success;
6233 : break;
6234 : }
6235 : // 'MemImm12Offset' class
6236 913 : case MCK_MemImm12Offset: {
6237 913 : DiagnosticPredicate DP(Operand.isMemImm12Offset());
6238 913 : if (DP.isMatch())
6239 : return MCTargetAsmParser::Match_Success;
6240 : break;
6241 : }
6242 : // 'MemImm8Offset' class
6243 356 : case MCK_MemImm8Offset: {
6244 356 : DiagnosticPredicate DP(Operand.isMemImm8Offset());
6245 356 : if (DP.isMatch())
6246 : return MCTargetAsmParser::Match_Success;
6247 : break;
6248 : }
6249 : // 'MemImm8s4Offset' class
6250 421 : case MCK_MemImm8s4Offset: {
6251 421 : DiagnosticPredicate DP(Operand.isMemImm8s4Offset());
6252 421 : if (DP.isMatch())
6253 : return MCTargetAsmParser::Match_Success;
6254 : break;
6255 : }
6256 : // 'MemNegImm8Offset' class
6257 1078 : case MCK_MemNegImm8Offset: {
6258 1078 : DiagnosticPredicate DP(Operand.isMemNegImm8Offset());
6259 1078 : if (DP.isMatch())
6260 : return MCTargetAsmParser::Match_Success;
6261 : break;
6262 : }
6263 : // 'MemNoOffset' class
6264 1942 : case MCK_MemNoOffset: {
6265 1942 : DiagnosticPredicate DP(Operand.isMemNoOffset());
6266 1942 : if (DP.isMatch())
6267 : return MCTargetAsmParser::Match_Success;
6268 : break;
6269 : }
6270 : // 'MemPosImm8Offset' class
6271 74 : case MCK_MemPosImm8Offset: {
6272 74 : DiagnosticPredicate DP(Operand.isMemPosImm8Offset());
6273 74 : if (DP.isMatch())
6274 : return MCTargetAsmParser::Match_Success;
6275 : break;
6276 : }
6277 : // 'MemRegOffset' class
6278 : case MCK_MemRegOffset: {
6279 : DiagnosticPredicate DP(Operand.isMemRegOffset());
6280 773 : if (DP.isMatch())
6281 : return MCTargetAsmParser::Match_Success;
6282 : break;
6283 : }
6284 : // 'ModImm' class
6285 5105 : case MCK_ModImm: {
6286 : DiagnosticPredicate DP(Operand.isModImm());
6287 5105 : if (DP.isMatch())
6288 : return MCTargetAsmParser::Match_Success;
6289 : break;
6290 : }
6291 : // 'ModImmNeg' class
6292 1847 : case MCK_ModImmNeg: {
6293 1847 : DiagnosticPredicate DP(Operand.isModImmNeg());
6294 1847 : if (DP.isMatch())
6295 : return MCTargetAsmParser::Match_Success;
6296 : break;
6297 : }
6298 : // 'ModImmNot' class
6299 1552 : case MCK_ModImmNot: {
6300 1552 : DiagnosticPredicate DP(Operand.isModImmNot());
6301 1552 : if (DP.isMatch())
6302 : return MCTargetAsmParser::Match_Success;
6303 : break;
6304 : }
6305 : // 'PKHASRImm' class
6306 : case MCK_PKHASRImm: {
6307 : DiagnosticPredicate DP(Operand.isPKHASRImm());
6308 12 : if (DP.isMatch())
6309 : return MCTargetAsmParser::Match_Success;
6310 : break;
6311 : }
6312 : // 'PKHLSLImm' class
6313 : case MCK_PKHLSLImm: {
6314 : DiagnosticPredicate DP(Operand.isImmediate<0,31>());
6315 22 : if (DP.isMatch())
6316 : return MCTargetAsmParser::Match_Success;
6317 : if (DP.isNearMatch())
6318 0 : return ARMAsmParser::Match_PKHLSLImm;
6319 : break;
6320 : }
6321 : // 'PostIdxImm8' class
6322 : case MCK_PostIdxImm8: {
6323 : DiagnosticPredicate DP(Operand.isPostIdxImm8());
6324 19 : if (DP.isMatch())
6325 : return MCTargetAsmParser::Match_Success;
6326 : break;
6327 : }
6328 : // 'PostIdxImm8s4' class
6329 : case MCK_PostIdxImm8s4: {
6330 : DiagnosticPredicate DP(Operand.isPostIdxImm8s4());
6331 352 : if (DP.isMatch())
6332 : return MCTargetAsmParser::Match_Success;
6333 : break;
6334 : }
6335 : // 'PostIdxReg' class
6336 25 : case MCK_PostIdxReg: {
6337 25 : DiagnosticPredicate DP(Operand.isPostIdxReg());
6338 25 : if (DP.isMatch())
6339 : return MCTargetAsmParser::Match_Success;
6340 : break;
6341 : }
6342 : // 'PostIdxRegShifted' class
6343 67 : case MCK_PostIdxRegShifted: {
6344 : DiagnosticPredicate DP(Operand.isPostIdxRegShifted());
6345 67 : if (DP.isMatch())
6346 : return MCTargetAsmParser::Match_Success;
6347 : break;
6348 : }
6349 : // 'ProcIFlags' class
6350 154 : case MCK_ProcIFlags: {
6351 : DiagnosticPredicate DP(Operand.isProcIFlags());
6352 154 : if (DP.isMatch())
6353 : return MCTargetAsmParser::Match_Success;
6354 : break;
6355 : }
6356 : // 'RegList' class
6357 1749 : case MCK_RegList: {
6358 : DiagnosticPredicate DP(Operand.isRegList());
6359 1749 : if (DP.isMatch())
6360 : return MCTargetAsmParser::Match_Success;
6361 : break;
6362 : }
6363 : // 'RotImm' class
6364 342 : case MCK_RotImm: {
6365 : DiagnosticPredicate DP(Operand.isRotImm());
6366 342 : if (DP.isMatch())
6367 : return MCTargetAsmParser::Match_Success;
6368 : break;
6369 : }
6370 : // 'SPRRegList' class
6371 44 : case MCK_SPRRegList: {
6372 : DiagnosticPredicate DP(Operand.isSPRRegList());
6373 44 : if (DP.isMatch())
6374 : return MCTargetAsmParser::Match_Success;
6375 : if (DP.isNearMatch())
6376 24 : return ARMAsmParser::Match_SPRRegList;
6377 : break;
6378 : }
6379 : // 'SetEndImm' class
6380 : case MCK_SetEndImm: {
6381 : DiagnosticPredicate DP(Operand.isImmediate<0,1>());
6382 44 : if (DP.isMatch())
6383 : return MCTargetAsmParser::Match_Success;
6384 : if (DP.isNearMatch())
6385 8 : return ARMAsmParser::Match_SetEndImm;
6386 : break;
6387 : }
6388 : // 'RegShiftedImm' class
6389 10720 : case MCK_RegShiftedImm: {
6390 : DiagnosticPredicate DP(Operand.isRegShiftedImm());
6391 10720 : if (DP.isMatch())
6392 : return MCTargetAsmParser::Match_Success;
6393 : break;
6394 : }
6395 : // 'RegShiftedReg' class
6396 4524 : case MCK_RegShiftedReg: {
6397 4524 : DiagnosticPredicate DP(Operand.isRegShiftedReg());
6398 4524 : if (DP.isMatch())
6399 : return MCTargetAsmParser::Match_Success;
6400 : break;
6401 : }
6402 : // 'ShifterImm' class
6403 52 : case MCK_ShifterImm: {
6404 : DiagnosticPredicate DP(Operand.isShifterImm());
6405 52 : if (DP.isMatch())
6406 : return MCTargetAsmParser::Match_Success;
6407 : break;
6408 : }
6409 : // 'ThumbBranchTarget' class
6410 : case MCK_ThumbBranchTarget: {
6411 : DiagnosticPredicate DP(Operand.isThumbBranchTarget());
6412 445 : if (DP.isMatch())
6413 : return MCTargetAsmParser::Match_Success;
6414 : break;
6415 : }
6416 : // 'ThumbMemPC' class
6417 655 : case MCK_ThumbMemPC: {
6418 655 : DiagnosticPredicate DP(Operand.isThumbMemPC());
6419 655 : if (DP.isMatch())
6420 : return MCTargetAsmParser::Match_Success;
6421 : break;
6422 : }
6423 : // 'ThumbModImmNeg1_7' class
6424 : case MCK_ThumbModImmNeg1_7: {
6425 : DiagnosticPredicate DP(Operand.isThumbModImmNeg1_7());
6426 802 : if (DP.isMatch())
6427 : return MCTargetAsmParser::Match_Success;
6428 : break;
6429 : }
6430 : // 'ThumbModImmNeg8_255' class
6431 : case MCK_ThumbModImmNeg8_255: {
6432 : DiagnosticPredicate DP(Operand.isThumbModImmNeg8_255());
6433 1504 : if (DP.isMatch())
6434 : return MCTargetAsmParser::Match_Success;
6435 : break;
6436 : }
6437 : // 'ImmThumbSR' class
6438 : case MCK_ImmThumbSR: {
6439 : DiagnosticPredicate DP(Operand.isImmediate<1,32>());
6440 660 : if (DP.isMatch())
6441 : return MCTargetAsmParser::Match_Success;
6442 : if (DP.isNearMatch())
6443 456 : return ARMAsmParser::Match_ImmThumbSR;
6444 : break;
6445 : }
6446 : // 'TraceSyncBarrierOpt' class
6447 14 : case MCK_TraceSyncBarrierOpt: {
6448 : DiagnosticPredicate DP(Operand.isTraceSyncBarrierOpt());
6449 14 : if (DP.isMatch())
6450 : return MCTargetAsmParser::Match_Success;
6451 : break;
6452 : }
6453 : // 'UnsignedOffset_b8s2' class
6454 : case MCK_UnsignedOffset_b8s2: {
6455 : DiagnosticPredicate DP(Operand.isUnsignedOffset<8, 2>());
6456 61 : if (DP.isMatch())
6457 : return MCTargetAsmParser::Match_Success;
6458 : break;
6459 : }
6460 : // 'VecListDPairAllLanes' class
6461 : case MCK_VecListDPairAllLanes: {
6462 : DiagnosticPredicate DP(Operand.isVecListDPairAllLanes());
6463 6762 : if (DP.isMatch())
6464 : return MCTargetAsmParser::Match_Success;
6465 : break;
6466 : }
6467 : // 'VecListDPair' class
6468 : case MCK_VecListDPair: {
6469 : DiagnosticPredicate DP(Operand.isVecListDPair());
6470 12735 : if (DP.isMatch())
6471 : return MCTargetAsmParser::Match_Success;
6472 : break;
6473 : }
6474 : // 'VecListDPairSpacedAllLanes' class
6475 : case MCK_VecListDPairSpacedAllLanes: {
6476 : DiagnosticPredicate DP(Operand.isVecListDPairSpacedAllLanes());
6477 2741 : if (DP.isMatch())
6478 : return MCTargetAsmParser::Match_Success;
6479 : break;
6480 : }
6481 : // 'VecListDPairSpaced' class
6482 : case MCK_VecListDPairSpaced: {
6483 : DiagnosticPredicate DP(Operand.isVecListDPairSpaced());
6484 4028 : if (DP.isMatch())
6485 : return MCTargetAsmParser::Match_Success;
6486 : break;
6487 : }
6488 : // 'VecListFourDAllLanes' class
6489 : case MCK_VecListFourDAllLanes: {
6490 : DiagnosticPredicate DP(Operand.isVecListFourDAllLanes());
6491 2508 : if (DP.isMatch())
6492 : return MCTargetAsmParser::Match_Success;
6493 : break;
6494 : }
6495 : // 'VecListFourD' class
6496 : case MCK_VecListFourD: {
6497 : DiagnosticPredicate DP(Operand.isVecListFourD());
6498 16598 : if (DP.isMatch())
6499 : return MCTargetAsmParser::Match_Success;
6500 : break;
6501 : }
6502 : // 'VecListFourDByteIndexed' class
6503 : case MCK_VecListFourDByteIndexed: {
6504 : DiagnosticPredicate DP(Operand.isVecListFourDByteIndexed());
6505 1134 : if (DP.isMatch())
6506 : return MCTargetAsmParser::Match_Success;
6507 : break;
6508 : }
6509 : // 'VecListFourDHWordIndexed' class
6510 : case MCK_VecListFourDHWordIndexed: {
6511 : DiagnosticPredicate DP(Operand.isVecListFourDHWordIndexed());
6512 1598 : if (DP.isMatch())
6513 : return MCTargetAsmParser::Match_Success;
6514 : break;
6515 : }
6516 : // 'VecListFourDWordIndexed' class
6517 : case MCK_VecListFourDWordIndexed: {
6518 : DiagnosticPredicate DP(Operand.isVecListFourDWordIndexed());
6519 1385 : if (DP.isMatch())
6520 : return MCTargetAsmParser::Match_Success;
6521 : break;
6522 : }
6523 : // 'VecListFourQAllLanes' class
6524 : case MCK_VecListFourQAllLanes: {
6525 : DiagnosticPredicate DP(Operand.isVecListFourQAllLanes());
6526 2327 : if (DP.isMatch())
6527 : return MCTargetAsmParser::Match_Success;
6528 : break;
6529 : }
6530 : // 'VecListFourQ' class
6531 : case MCK_VecListFourQ: {
6532 : DiagnosticPredicate DP(Operand.isVecListFourQ());
6533 3930 : if (DP.isMatch())
6534 : return MCTargetAsmParser::Match_Success;
6535 : break;
6536 : }
6537 : // 'VecListFourQHWordIndexed' class
6538 : case MCK_VecListFourQHWordIndexed: {
6539 : DiagnosticPredicate DP(Operand.isVecListFourQHWordIndexed());
6540 1493 : if (DP.isMatch())
6541 : return MCTargetAsmParser::Match_Success;
6542 : break;
6543 : }
6544 : // 'VecListFourQWordIndexed' class
6545 : case MCK_VecListFourQWordIndexed: {
6546 : DiagnosticPredicate DP(Operand.isVecListFourQWordIndexed());
6547 1253 : if (DP.isMatch())
6548 : return MCTargetAsmParser::Match_Success;
6549 : break;
6550 : }
6551 : // 'VecListOneDAllLanes' class
6552 : case MCK_VecListOneDAllLanes: {
6553 : DiagnosticPredicate DP(Operand.isVecListOneDAllLanes());
6554 3747 : if (DP.isMatch())
6555 : return MCTargetAsmParser::Match_Success;
6556 : break;
6557 : }
6558 : // 'VecListOneD' class
6559 : case MCK_VecListOneD: {
6560 : DiagnosticPredicate DP(Operand.isVecListOneD());
6561 8187 : if (DP.isMatch())
6562 : return MCTargetAsmParser::Match_Success;
6563 : break;
6564 : }
6565 : // 'VecListOneDByteIndexed' class
6566 : case MCK_VecListOneDByteIndexed: {
6567 : DiagnosticPredicate DP(Operand.isVecListOneDByteIndexed());
6568 1752 : if (DP.isMatch())
6569 : return MCTargetAsmParser::Match_Success;
6570 : break;
6571 : }
6572 : // 'VecListOneDHWordIndexed' class
6573 : case MCK_VecListOneDHWordIndexed: {
6574 : DiagnosticPredicate DP(Operand.isVecListOneDHWordIndexed());
6575 2287 : if (DP.isMatch())
6576 : return MCTargetAsmParser::Match_Success;
6577 : break;
6578 : }
6579 : // 'VecListOneDWordIndexed' class
6580 : case MCK_VecListOneDWordIndexed: {
6581 : DiagnosticPredicate DP(Operand.isVecListOneDWordIndexed());
6582 2100 : if (DP.isMatch())
6583 : return MCTargetAsmParser::Match_Success;
6584 : break;
6585 : }
6586 : // 'VecListThreeDAllLanes' class
6587 : case MCK_VecListThreeDAllLanes: {
6588 : DiagnosticPredicate DP(Operand.isVecListThreeDAllLanes());
6589 2814 : if (DP.isMatch())
6590 : return MCTargetAsmParser::Match_Success;
6591 : break;
6592 : }
6593 : // 'VecListThreeD' class
6594 : case MCK_VecListThreeD: {
6595 : DiagnosticPredicate DP(Operand.isVecListThreeD());
6596 12575 : if (DP.isMatch())
6597 : return MCTargetAsmParser::Match_Success;
6598 : break;
6599 : }
6600 : // 'VecListThreeDByteIndexed' class
6601 : case MCK_VecListThreeDByteIndexed: {
6602 : DiagnosticPredicate DP(Operand.isVecListThreeDByteIndexed());
6603 1366 : if (DP.isMatch())
6604 : return MCTargetAsmParser::Match_Success;
6605 : break;
6606 : }
6607 : // 'VecListThreeDHWordIndexed' class
6608 : case MCK_VecListThreeDHWordIndexed: {
6609 : DiagnosticPredicate DP(Operand.isVecListThreeDHWordIndexed());
6610 1634 : if (DP.isMatch())
6611 : return MCTargetAsmParser::Match_Success;
6612 : break;
6613 : }
6614 : // 'VecListThreeDWordIndexed' class
6615 : case MCK_VecListThreeDWordIndexed: {
6616 : DiagnosticPredicate DP(Operand.isVecListThreeDWordIndexed());
6617 1500 : if (DP.isMatch())
6618 : return MCTargetAsmParser::Match_Success;
6619 : break;
6620 : }
6621 : // 'VecListThreeQAllLanes' class
6622 : case MCK_VecListThreeQAllLanes: {
6623 : DiagnosticPredicate DP(Operand.isVecListThreeQAllLanes());
6624 2703 : if (DP.isMatch())
6625 : return MCTargetAsmParser::Match_Success;
6626 : break;
6627 : }
6628 : // 'VecListThreeQ' class
6629 : case MCK_VecListThreeQ: {
6630 : DiagnosticPredicate DP(Operand.isVecListThreeQ());
6631 4386 : if (DP.isMatch())
6632 : return MCTargetAsmParser::Match_Success;
6633 : break;
6634 : }
6635 : // 'VecListThreeQHWordIndexed' class
6636 : case MCK_VecListThreeQHWordIndexed: {
6637 : DiagnosticPredicate DP(Operand.isVecListThreeQHWordIndexed());
6638 1564 : if (DP.isMatch())
6639 : return MCTargetAsmParser::Match_Success;
6640 : break;
6641 : }
6642 : // 'VecListThreeQWordIndexed' class
6643 : case MCK_VecListThreeQWordIndexed: {
6644 : DiagnosticPredicate DP(Operand.isVecListThreeQWordIndexed());
6645 1430 : if (DP.isMatch())
6646 : return MCTargetAsmParser::Match_Success;
6647 : break;
6648 : }
6649 : // 'VecListTwoDByteIndexed' class
6650 : case MCK_VecListTwoDByteIndexed: {
6651 : DiagnosticPredicate DP(Operand.isVecListTwoDByteIndexed());
6652 1079 : if (DP.isMatch())
6653 : return MCTargetAsmParser::Match_Success;
6654 : break;
6655 : }
6656 : // 'VecListTwoDHWordIndexed' class
6657 : case MCK_VecListTwoDHWordIndexed: {
6658 : DiagnosticPredicate DP(Operand.isVecListTwoDHWordIndexed());
6659 1465 : if (DP.isMatch())
6660 : return MCTargetAsmParser::Match_Success;
6661 : break;
6662 : }
6663 : // 'VecListTwoDWordIndexed' class
6664 : case MCK_VecListTwoDWordIndexed: {
6665 : DiagnosticPredicate DP(Operand.isVecListTwoDWordIndexed());
6666 1280 : if (DP.isMatch())
6667 : return MCTargetAsmParser::Match_Success;
6668 : break;
6669 : }
6670 : // 'VecListTwoQHWordIndexed' class
6671 : case MCK_VecListTwoQHWordIndexed: {
6672 : DiagnosticPredicate DP(Operand.isVecListTwoQHWordIndexed());
6673 1450 : if (DP.isMatch())
6674 : return MCTargetAsmParser::Match_Success;
6675 : break;
6676 : }
6677 : // 'VecListTwoQWordIndexed' class
6678 : case MCK_VecListTwoQWordIndexed: {
6679 : DiagnosticPredicate DP(Operand.isVecListTwoQWordIndexed());
6680 1254 : if (DP.isMatch())
6681 : return MCTargetAsmParser::Match_Success;
6682 : break;
6683 : }
6684 : // 'VectorIndex16' class
6685 377 : case MCK_VectorIndex16: {
6686 : DiagnosticPredicate DP(Operand.isVectorIndex16());
6687 377 : if (DP.isMatch())
6688 : return MCTargetAsmParser::Match_Success;
6689 : break;
6690 : }
6691 : // 'VectorIndex32' class
6692 527 : case MCK_VectorIndex32: {
6693 : DiagnosticPredicate DP(Operand.isVectorIndex32());
6694 527 : if (DP.isMatch())
6695 : return MCTargetAsmParser::Match_Success;
6696 : break;
6697 : }
6698 : // 'VectorIndex64' class
6699 154 : case MCK_VectorIndex64: {
6700 : DiagnosticPredicate DP(Operand.isVectorIndex64());
6701 154 : if (DP.isMatch())
6702 : return MCTargetAsmParser::Match_Success;
6703 : break;
6704 : }
6705 : // 'VectorIndex8' class
6706 66 : case MCK_VectorIndex8: {
6707 : DiagnosticPredicate DP(Operand.isVectorIndex8());
6708 66 : if (DP.isMatch())
6709 : return MCTargetAsmParser::Match_Success;
6710 : break;
6711 : }
6712 : // 'MemTBB' class
6713 7 : case MCK_MemTBB: {
6714 7 : DiagnosticPredicate DP(Operand.isMemTBB());
6715 7 : if (DP.isMatch())
6716 : return MCTargetAsmParser::Match_Success;
6717 : break;
6718 : }
6719 : // 'MemTBH' class
6720 7 : case MCK_MemTBH: {
6721 7 : DiagnosticPredicate DP(Operand.isMemTBH());
6722 7 : if (DP.isMatch())
6723 : return MCTargetAsmParser::Match_Success;
6724 : break;
6725 : }
6726 : // 'ComplexRotationEven' class
6727 : case MCK_ComplexRotationEven: {
6728 : DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>());
6729 504 : if (DP.isMatch())
6730 : return MCTargetAsmParser::Match_Success;
6731 : if (DP.isNearMatch())
6732 288 : return ARMAsmParser::Match_ComplexRotationEven;
6733 : break;
6734 : }
6735 : // 'ComplexRotationOdd' class
6736 : case MCK_ComplexRotationOdd: {
6737 : DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>());
6738 148 : if (DP.isMatch())
6739 : return MCTargetAsmParser::Match_Success;
6740 : if (DP.isNearMatch())
6741 80 : return ARMAsmParser::Match_ComplexRotationOdd;
6742 : break;
6743 : }
6744 : // 'NEONi16vmovi8Replicate' class
6745 : case MCK_NEONi16vmovi8Replicate: {
6746 : DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 16>());
6747 128 : if (DP.isMatch())
6748 : return MCTargetAsmParser::Match_Success;
6749 : break;
6750 : }
6751 : // 'NEONi16invi8Replicate' class
6752 : case MCK_NEONi16invi8Replicate: {
6753 : DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 16>());
6754 71 : if (DP.isMatch())
6755 : return MCTargetAsmParser::Match_Success;
6756 : break;
6757 : }
6758 : // 'NEONi32vmovi8Replicate' class
6759 : case MCK_NEONi32vmovi8Replicate: {
6760 : DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 32>());
6761 115 : if (DP.isMatch())
6762 : return MCTargetAsmParser::Match_Success;
6763 : break;
6764 : }
6765 : // 'NEONi32invi8Replicate' class
6766 77 : case MCK_NEONi32invi8Replicate: {
6767 77 : DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 32>());
6768 77 : if (DP.isMatch())
6769 : return MCTargetAsmParser::Match_Success;
6770 : break;
6771 : }
6772 : // 'NEONi64vmovi8Replicate' class
6773 70 : case MCK_NEONi64vmovi8Replicate: {
6774 70 : DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 64>());
6775 70 : if (DP.isMatch())
6776 : return MCTargetAsmParser::Match_Success;
6777 : break;
6778 : }
6779 : // 'NEONi64invi8Replicate' class
6780 44 : case MCK_NEONi64invi8Replicate: {
6781 44 : DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 64>());
6782 44 : if (DP.isMatch())
6783 : return MCTargetAsmParser::Match_Success;
6784 : break;
6785 : }
6786 : // 'NEONi32vmovi16Replicate' class
6787 : case MCK_NEONi32vmovi16Replicate: {
6788 : DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 32>());
6789 184 : if (DP.isMatch())
6790 : return MCTargetAsmParser::Match_Success;
6791 : break;
6792 : }
6793 : // 'NEONi64vmovi16Replicate' class
6794 108 : case MCK_NEONi64vmovi16Replicate: {
6795 108 : DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 64>());
6796 108 : if (DP.isMatch())
6797 : return MCTargetAsmParser::Match_Success;
6798 : break;
6799 : }
6800 : // 'NEONi64vmovi32Replicate' class
6801 100 : case MCK_NEONi64vmovi32Replicate: {
6802 100 : DiagnosticPredicate DP(Operand.isNEONmovReplicate<32, 64>());
6803 100 : if (DP.isMatch())
6804 : return MCTargetAsmParser::Match_Success;
6805 : break;
6806 : }
6807 : // 'ConstPoolAsmImm' class
6808 : case MCK_ConstPoolAsmImm: {
6809 : DiagnosticPredicate DP(Operand.isConstPoolAsmImm());
6810 1164 : if (DP.isMatch())
6811 : return MCTargetAsmParser::Match_Success;
6812 : break;
6813 : }
6814 : // 'FBits16' class
6815 : case MCK_FBits16: {
6816 : DiagnosticPredicate DP(Operand.isFBits16());
6817 136 : if (DP.isMatch())
6818 : return MCTargetAsmParser::Match_Success;
6819 : break;
6820 : }
6821 : // 'FBits32' class
6822 : case MCK_FBits32: {
6823 : DiagnosticPredicate DP(Operand.isFBits32());
6824 96 : if (DP.isMatch())
6825 : return MCTargetAsmParser::Match_Success;
6826 : break;
6827 : }
6828 : // 'Imm0_4095' class
6829 : case MCK_Imm0_4095: {
6830 : DiagnosticPredicate DP(Operand.isImmediate<0,4095>());
6831 327 : if (DP.isMatch())
6832 : return MCTargetAsmParser::Match_Success;
6833 : if (DP.isNearMatch())
6834 208 : return ARMAsmParser::Match_Imm0_4095;
6835 : break;
6836 : }
6837 : // 'Imm0_4095Neg' class
6838 : case MCK_Imm0_4095Neg: {
6839 : DiagnosticPredicate DP(Operand.isImm0_4095Neg());
6840 225 : if (DP.isMatch())
6841 : return MCTargetAsmParser::Match_Success;
6842 : break;
6843 : }
6844 : // 'ITMask' class
6845 5520 : case MCK_ITMask: {
6846 : DiagnosticPredicate DP(Operand.isITMask());
6847 5520 : if (DP.isMatch())
6848 : return MCTargetAsmParser::Match_Success;
6849 : break;
6850 : }
6851 : // 'ITCondCode' class
6852 5520 : case MCK_ITCondCode: {
6853 : DiagnosticPredicate DP(Operand.isITCondCode());
6854 5520 : if (DP.isMatch())
6855 : return MCTargetAsmParser::Match_Success;
6856 : break;
6857 : }
6858 : // 'NEONi16splat' class
6859 272 : case MCK_NEONi16splat: {
6860 272 : DiagnosticPredicate DP(Operand.isNEONi16splat());
6861 272 : if (DP.isMatch())
6862 : return MCTargetAsmParser::Match_Success;
6863 : break;
6864 : }
6865 : // 'NEONi32splat' class
6866 81 : case MCK_NEONi32splat: {
6867 81 : DiagnosticPredicate DP(Operand.isNEONi32splat());
6868 81 : if (DP.isMatch())
6869 : return MCTargetAsmParser::Match_Success;
6870 : break;
6871 : }
6872 : // 'NEONi64splat' class
6873 : case MCK_NEONi64splat: {
6874 : DiagnosticPredicate DP(Operand.isNEONi64splat());
6875 60 : if (DP.isMatch())
6876 : return MCTargetAsmParser::Match_Success;
6877 : break;
6878 : }
6879 : // 'NEONi8splat' class
6880 : case MCK_NEONi8splat: {
6881 : DiagnosticPredicate DP(Operand.isNEONi8splat());
6882 60 : if (DP.isMatch())
6883 : return MCTargetAsmParser::Match_Success;
6884 : break;
6885 : }
6886 : // 'NEONi16splatNot' class
6887 50 : case MCK_NEONi16splatNot: {
6888 50 : DiagnosticPredicate DP(Operand.isNEONi16splatNot());
6889 50 : if (DP.isMatch())
6890 : return MCTargetAsmParser::Match_Success;
6891 : break;
6892 : }
6893 : // 'NEONi32splatNot' class
6894 48 : case MCK_NEONi32splatNot: {
6895 48 : DiagnosticPredicate DP(Operand.isNEONi32splatNot());
6896 48 : if (DP.isMatch())
6897 : return MCTargetAsmParser::Match_Success;
6898 : break;
6899 : }
6900 : // 'NEONi32vmov' class
6901 320 : case MCK_NEONi32vmov: {
6902 320 : DiagnosticPredicate DP(Operand.isNEONi32vmov());
6903 320 : if (DP.isMatch())
6904 : return MCTargetAsmParser::Match_Success;
6905 : break;
6906 : }
6907 : // 'NEONi32vmovNeg' class
6908 140 : case MCK_NEONi32vmovNeg: {
6909 140 : DiagnosticPredicate DP(Operand.isNEONi32vmovNeg());
6910 140 : if (DP.isMatch())
6911 : return MCTargetAsmParser::Match_Success;
6912 : break;
6913 : }
6914 : // 'ShrImm16' class
6915 : case MCK_ShrImm16: {
6916 : DiagnosticPredicate DP(Operand.isImmediate<1,16>());
6917 880 : if (DP.isMatch())
6918 : return MCTargetAsmParser::Match_Success;
6919 : if (DP.isNearMatch())
6920 602 : return ARMAsmParser::Match_ShrImm16;
6921 : break;
6922 : }
6923 : // 'ShrImm32' class
6924 : case MCK_ShrImm32: {
6925 : DiagnosticPredicate DP(Operand.isImmediate<1,32>());
6926 782 : if (DP.isMatch())
6927 : return MCTargetAsmParser::Match_Success;
6928 : if (DP.isNearMatch())
6929 460 : return ARMAsmParser::Match_ShrImm32;
6930 : break;
6931 : }
6932 : // 'ShrImm64' class
6933 : case MCK_ShrImm64: {
6934 : DiagnosticPredicate DP(Operand.isImmediate<1,64>());
6935 669 : if (DP.isMatch())
6936 : return MCTargetAsmParser::Match_Success;
6937 : if (DP.isNearMatch())
6938 354 : return ARMAsmParser::Match_ShrImm64;
6939 : break;
6940 : }
6941 : // 'ShrImm8' class
6942 : case MCK_ShrImm8: {
6943 : DiagnosticPredicate DP(Operand.isImmediate<1,8>());
6944 658 : if (DP.isMatch())
6945 : return MCTargetAsmParser::Match_Success;
6946 : if (DP.isNearMatch())
6947 498 : return ARMAsmParser::Match_ShrImm8;
6948 : break;
6949 : }
6950 : // 'T2SOImm' class
6951 6540 : case MCK_T2SOImm: {
6952 6540 : DiagnosticPredicate DP(Operand.isT2SOImm());
6953 6540 : if (DP.isMatch())
6954 : return MCTargetAsmParser::Match_Success;
6955 : break;
6956 : }
6957 : // 'T2SOImmNeg' class
6958 4802 : case MCK_T2SOImmNeg: {
6959 4802 : DiagnosticPredicate DP(Operand.isT2SOImmNeg());
6960 4802 : if (DP.isMatch())
6961 : return MCTargetAsmParser::Match_Success;
6962 : break;
6963 : }
6964 : // 'T2SOImmNot' class
6965 2120 : case MCK_T2SOImmNot: {
6966 2120 : DiagnosticPredicate DP(Operand.isT2SOImmNot());
6967 2120 : if (DP.isMatch())
6968 : return MCTargetAsmParser::Match_Success;
6969 : break;
6970 : }
6971 : // 'MemUImm12Offset' class
6972 1273 : case MCK_MemUImm12Offset: {
6973 1273 : DiagnosticPredicate DP(Operand.isMemUImm12Offset());
6974 1273 : if (DP.isMatch())
6975 : return MCTargetAsmParser::Match_Success;
6976 : break;
6977 : }
6978 : // 'T2MemRegOffset' class
6979 1023 : case MCK_T2MemRegOffset: {
6980 1023 : DiagnosticPredicate DP(Operand.isT2MemRegOffset());
6981 1023 : if (DP.isMatch())
6982 : return MCTargetAsmParser::Match_Success;
6983 : break;
6984 : }
6985 : // 'Imm8s4' class
6986 : case MCK_Imm8s4: {
6987 : DiagnosticPredicate DP(Operand.isImm8s4());
6988 0 : if (DP.isMatch())
6989 : return MCTargetAsmParser::Match_Success;
6990 : break;
6991 : }
6992 : // 'MemPCRelImm12' class
6993 506 : case MCK_MemPCRelImm12: {
6994 506 : DiagnosticPredicate DP(Operand.isMemPCRelImm12());
6995 506 : if (DP.isMatch())
6996 : return MCTargetAsmParser::Match_Success;
6997 : break;
6998 : }
6999 : // 'MemThumbRIs1' class
7000 243 : case MCK_MemThumbRIs1: {
7001 243 : DiagnosticPredicate DP(Operand.isMemThumbRIs1());
7002 243 : if (DP.isMatch())
7003 : return MCTargetAsmParser::Match_Success;
7004 : break;
7005 : }
7006 : // 'MemThumbRIs2' class
7007 237 : case MCK_MemThumbRIs2: {
7008 237 : DiagnosticPredicate DP(Operand.isMemThumbRIs2());
7009 237 : if (DP.isMatch())
7010 : return MCTargetAsmParser::Match_Success;
7011 : break;
7012 : }
7013 : // 'MemThumbRIs4' class
7014 575 : case MCK_MemThumbRIs4: {
7015 575 : DiagnosticPredicate DP(Operand.isMemThumbRIs4());
7016 575 : if (DP.isMatch())
7017 : return MCTargetAsmParser::Match_Success;
7018 : break;
7019 : }
7020 : // 'MemThumbRR' class
7021 1195 : case MCK_MemThumbRR: {
7022 1195 : DiagnosticPredicate DP(Operand.isMemThumbRR());
7023 1195 : if (DP.isMatch())
7024 : return MCTargetAsmParser::Match_Success;
7025 : break;
7026 : }
7027 : // 'MemThumbSPI' class
7028 534 : case MCK_MemThumbSPI: {
7029 534 : DiagnosticPredicate DP(Operand.isMemThumbSPI());
7030 534 : if (DP.isMatch())
7031 : return MCTargetAsmParser::Match_Success;
7032 : break;
7033 : }
7034 : // 'Imm0_1020s4' class
7035 : case MCK_Imm0_1020s4: {
7036 : DiagnosticPredicate DP(Operand.isImm0_1020s4());
7037 51 : if (DP.isMatch())
7038 : return MCTargetAsmParser::Match_Success;
7039 : break;
7040 : }
7041 : // 'Imm0_508s4' class
7042 : case MCK_Imm0_508s4: {
7043 : DiagnosticPredicate DP(Operand.isImm0_508s4());
7044 248 : if (DP.isMatch())
7045 : return MCTargetAsmParser::Match_Success;
7046 : break;
7047 : }
7048 : // 'Imm0_508s4Neg' class
7049 : case MCK_Imm0_508s4Neg: {
7050 : DiagnosticPredicate DP(Operand.isImm0_508s4Neg());
7051 198 : if (DP.isMatch())
7052 : return MCTargetAsmParser::Match_Success;
7053 : break;
7054 : }
7055 : } // end switch (Kind)
7056 :
7057 471426 : if (Operand.isReg()) {
7058 : MatchClassKind OpKind;
7059 : switch (Operand.getReg()) {
7060 : default: OpKind = InvalidMatchClass; break;
7061 : case ARM::R0: OpKind = MCK_Reg0; break;
7062 : case ARM::R1: OpKind = MCK_Reg0; break;
7063 : case ARM::R2: OpKind = MCK_Reg0; break;
7064 : case ARM::R3: OpKind = MCK_Reg0; break;
7065 : case ARM::R4: OpKind = MCK_tGPR; break;
7066 : case ARM::R5: OpKind = MCK_tGPR; break;
7067 : case ARM::R6: OpKind = MCK_tGPR; break;
7068 : case ARM::R7: OpKind = MCK_tGPR; break;
7069 : case ARM::R8: OpKind = MCK_Reg10; break;
7070 : case ARM::R9: OpKind = MCK_Reg10; break;
7071 : case ARM::R10: OpKind = MCK_Reg10; break;
7072 : case ARM::R11: OpKind = MCK_Reg10; break;
7073 : case ARM::R12: OpKind = MCK_Reg11; break;
7074 : case ARM::SP: OpKind = MCK_GPRsp; break;
7075 : case ARM::LR: OpKind = MCK_LR; break;
7076 : case ARM::PC: OpKind = MCK_PC; break;
7077 : case ARM::S0: OpKind = MCK_SPR_8; break;
7078 : case ARM::S1: OpKind = MCK_SPR_8; break;
7079 : case ARM::S2: OpKind = MCK_SPR_8; break;
7080 : case ARM::S3: OpKind = MCK_SPR_8; break;
7081 : case ARM::S4: OpKind = MCK_SPR_8; break;
7082 : case ARM::S5: OpKind = MCK_SPR_8; break;
7083 : case ARM::S6: OpKind = MCK_SPR_8; break;
7084 : case ARM::S7: OpKind = MCK_SPR_8; break;
7085 : case ARM::S8: OpKind = MCK_SPR_8; break;
7086 : case ARM::S9: OpKind = MCK_SPR_8; break;
7087 : case ARM::S10: OpKind = MCK_SPR_8; break;
7088 : case ARM::S11: OpKind = MCK_SPR_8; break;
7089 : case ARM::S12: OpKind = MCK_SPR_8; break;
7090 : case ARM::S13: OpKind = MCK_SPR_8; break;
7091 : case ARM::S14: OpKind = MCK_SPR_8; break;
7092 : case ARM::S15: OpKind = MCK_SPR_8; break;
7093 : case ARM::S16: OpKind = MCK_HPR; break;
7094 : case ARM::S17: OpKind = MCK_HPR; break;
7095 : case ARM::S18: OpKind = MCK_HPR; break;
7096 : case ARM::S19: OpKind = MCK_HPR; break;
7097 : case ARM::S20: OpKind = MCK_HPR; break;
7098 : case ARM::S21: OpKind = MCK_HPR; break;
7099 : case ARM::S22: OpKind = MCK_HPR; break;
7100 : case ARM::S23: OpKind = MCK_HPR; break;
7101 : case ARM::S24: OpKind = MCK_HPR; break;
7102 : case ARM::S25: OpKind = MCK_HPR; break;
7103 : case ARM::S26: OpKind = MCK_HPR; break;
7104 : case ARM::S27: OpKind = MCK_HPR; break;
7105 : case ARM::S28: OpKind = MCK_HPR; break;
7106 : case ARM::S29: OpKind = MCK_HPR; break;
7107 : case ARM::S30: OpKind = MCK_HPR; break;
7108 : case ARM::S31: OpKind = MCK_HPR; break;
7109 : case ARM::D0: OpKind = MCK_DPR_8; break;
7110 : case ARM::D1: OpKind = MCK_DPR_8; break;
7111 : case ARM::D2: OpKind = MCK_DPR_8; break;
7112 : case ARM::D3: OpKind = MCK_DPR_8; break;
7113 : case ARM::D4: OpKind = MCK_DPR_8; break;
7114 : case ARM::D5: OpKind = MCK_DPR_8; break;
7115 : case ARM::D6: OpKind = MCK_DPR_8; break;
7116 : case ARM::D7: OpKind = MCK_DPR_8; break;
7117 : case ARM::D8: OpKind = MCK_DPR_VFP2; break;
7118 : case ARM::D9: OpKind = MCK_DPR_VFP2; break;
7119 : case ARM::D10: OpKind = MCK_DPR_VFP2; break;
7120 : case ARM::D11: OpKind = MCK_DPR_VFP2; break;
7121 : case ARM::D12: OpKind = MCK_DPR_VFP2; break;
7122 : case ARM::D13: OpKind = MCK_DPR_VFP2; break;
7123 : case ARM::D14: OpKind = MCK_DPR_VFP2; break;
7124 : case ARM::D15: OpKind = MCK_DPR_VFP2; break;
7125 : case ARM::D16: OpKind = MCK_DPR; break;
7126 : case ARM::D17: OpKind = MCK_DPR; break;
7127 : case ARM::D18: OpKind = MCK_DPR; break;
7128 : case ARM::D19: OpKind = MCK_DPR; break;
7129 : case ARM::D20: OpKind = MCK_DPR; break;
7130 : case ARM::D21: OpKind = MCK_DPR; break;
7131 : case ARM::D22: OpKind = MCK_DPR; break;
7132 : case ARM::D23: OpKind = MCK_DPR; break;
7133 : case ARM::D24: OpKind = MCK_DPR; break;
7134 : case ARM::D25: OpKind = MCK_DPR; break;
7135 : case ARM::D26: OpKind = MCK_DPR; break;
7136 : case ARM::D27: OpKind = MCK_DPR; break;
7137 : case ARM::D28: OpKind = MCK_DPR; break;
7138 : case ARM::D29: OpKind = MCK_DPR; break;
7139 : case ARM::D30: OpKind = MCK_DPR; break;
7140 : case ARM::D31: OpKind = MCK_DPR; break;
7141 : case ARM::Q0: OpKind = MCK_QPR_8; break;
7142 : case ARM::Q1: OpKind = MCK_QPR_8; break;
7143 : case ARM::Q2: OpKind = MCK_QPR_8; break;
7144 : case ARM::Q3: OpKind = MCK_QPR_8; break;
7145 : case ARM::Q4: OpKind = MCK_QPR_VFP2; break;
7146 : case ARM::Q5: OpKind = MCK_QPR_VFP2; break;
7147 : case ARM::Q6: OpKind = MCK_QPR_VFP2; break;
7148 : case ARM::Q7: OpKind = MCK_QPR_VFP2; break;
7149 : case ARM::Q8: OpKind = MCK_QPR; break;
7150 : case ARM::Q9: OpKind = MCK_QPR; break;
7151 : case ARM::Q10: OpKind = MCK_QPR; break;
7152 : case ARM::Q11: OpKind = MCK_QPR; break;
7153 : case ARM::Q12: OpKind = MCK_QPR; break;
7154 : case ARM::Q13: OpKind = MCK_QPR; break;
7155 : case ARM::Q14: OpKind = MCK_QPR; break;
7156 : case ARM::Q15: OpKind = MCK_QPR; break;
7157 : case ARM::CPSR: OpKind = MCK_CCR; break;
7158 : case ARM::APSR: OpKind = MCK_APSR; break;
7159 : case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break;
7160 : case ARM::SPSR: OpKind = MCK_SPSR; break;
7161 : case ARM::FPSCR: OpKind = MCK_FPSCR; break;
7162 : case ARM::FPSID: OpKind = MCK_FPSID; break;
7163 : case ARM::MVFR2: OpKind = MCK_MVFR2; break;
7164 : case ARM::MVFR1: OpKind = MCK_MVFR1; break;
7165 : case ARM::MVFR0: OpKind = MCK_MVFR0; break;
7166 : case ARM::FPEXC: OpKind = MCK_FPEXC; break;
7167 : case ARM::FPINST: OpKind = MCK_FPINST; break;
7168 : case ARM::FPINST2: OpKind = MCK_FPINST2; break;
7169 : case ARM::D0_D2: OpKind = MCK_Reg40; break;
7170 : case ARM::D1_D3: OpKind = MCK_Reg40; break;
7171 : case ARM::D2_D4: OpKind = MCK_Reg40; break;
7172 : case ARM::D3_D5: OpKind = MCK_Reg40; break;
7173 : case ARM::D4_D6: OpKind = MCK_Reg40; break;
7174 : case ARM::D5_D7: OpKind = MCK_Reg40; break;
7175 : case ARM::D6_D8: OpKind = MCK_Reg41; break;
7176 : case ARM::D7_D9: OpKind = MCK_Reg41; break;
7177 : case ARM::D8_D10: OpKind = MCK_Reg42; break;
7178 : case ARM::D9_D11: OpKind = MCK_Reg42; break;
7179 : case ARM::D10_D12: OpKind = MCK_Reg42; break;
7180 : case ARM::D11_D13: OpKind = MCK_Reg42; break;
7181 : case ARM::D12_D14: OpKind = MCK_Reg42; break;
7182 : case ARM::D13_D15: OpKind = MCK_Reg42; break;
7183 : case ARM::D14_D16: OpKind = MCK_Reg43; break;
7184 : case ARM::D15_D17: OpKind = MCK_Reg43; break;
7185 : case ARM::D16_D18: OpKind = MCK_DPairSpc; break;
7186 : case ARM::D17_D19: OpKind = MCK_DPairSpc; break;
7187 : case ARM::D18_D20: OpKind = MCK_DPairSpc; break;
7188 : case ARM::D19_D21: OpKind = MCK_DPairSpc; break;
7189 : case ARM::D20_D22: OpKind = MCK_DPairSpc; break;
7190 : case ARM::D21_D23: OpKind = MCK_DPairSpc; break;
7191 : case ARM::D22_D24: OpKind = MCK_DPairSpc; break;
7192 : case ARM::D23_D25: OpKind = MCK_DPairSpc; break;
7193 : case ARM::D24_D26: OpKind = MCK_DPairSpc; break;
7194 : case ARM::D25_D27: OpKind = MCK_DPairSpc; break;
7195 : case ARM::D26_D28: OpKind = MCK_DPairSpc; break;
7196 : case ARM::D27_D29: OpKind = MCK_DPairSpc; break;
7197 : case ARM::D28_D30: OpKind = MCK_DPairSpc; break;
7198 : case ARM::D29_D31: OpKind = MCK_DPairSpc; break;
7199 : case ARM::Q0_Q1: OpKind = MCK_Reg45; break;
7200 : case ARM::Q1_Q2: OpKind = MCK_Reg45; break;
7201 : case ARM::Q2_Q3: OpKind = MCK_Reg45; break;
7202 : case ARM::Q3_Q4: OpKind = MCK_Reg46; break;
7203 : case ARM::Q4_Q5: OpKind = MCK_Reg47; break;
7204 : case ARM::Q5_Q6: OpKind = MCK_Reg47; break;
7205 : case ARM::Q6_Q7: OpKind = MCK_Reg47; break;
7206 : case ARM::Q7_Q8: OpKind = MCK_Reg48; break;
7207 : case ARM::Q8_Q9: OpKind = MCK_QQPR; break;
7208 : case ARM::Q9_Q10: OpKind = MCK_QQPR; break;
7209 : case ARM::Q10_Q11: OpKind = MCK_QQPR; break;
7210 : case ARM::Q11_Q12: OpKind = MCK_QQPR; break;
7211 : case ARM::Q12_Q13: OpKind = MCK_QQPR; break;
7212 : case ARM::Q13_Q14: OpKind = MCK_QQPR; break;
7213 : case ARM::Q14_Q15: OpKind = MCK_QQPR; break;
7214 : case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg59; break;
7215 : case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg60; break;
7216 : case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg61; break;
7217 : case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg62; break;
7218 : case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_Reg63; break;
7219 : case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg64; break;
7220 : case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg65; break;
7221 : case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg66; break;
7222 : case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break;
7223 : case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break;
7224 : case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break;
7225 : case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break;
7226 : case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break;
7227 : case ARM::R0_R1: OpKind = MCK_Reg68; break;
7228 : case ARM::R2_R3: OpKind = MCK_Reg68; break;
7229 : case ARM::R4_R5: OpKind = MCK_Reg69; break;
7230 : case ARM::R6_R7: OpKind = MCK_Reg69; break;
7231 : case ARM::R8_R9: OpKind = MCK_Reg73; break;
7232 : case ARM::R10_R11: OpKind = MCK_Reg73; break;
7233 : case ARM::R12_SP: OpKind = MCK_Reg75; break;
7234 : case ARM::D0_D1_D2: OpKind = MCK_Reg83; break;
7235 : case ARM::D1_D2_D3: OpKind = MCK_Reg88; break;
7236 : case ARM::D2_D3_D4: OpKind = MCK_Reg83; break;
7237 : case ARM::D3_D4_D5: OpKind = MCK_Reg88; break;
7238 : case ARM::D4_D5_D6: OpKind = MCK_Reg83; break;
7239 : case ARM::D5_D6_D7: OpKind = MCK_Reg88; break;
7240 : case ARM::D6_D7_D8: OpKind = MCK_Reg84; break;
7241 : case ARM::D7_D8_D9: OpKind = MCK_Reg89; break;
7242 : case ARM::D8_D9_D10: OpKind = MCK_Reg85; break;
7243 : case ARM::D9_D10_D11: OpKind = MCK_Reg90; break;
7244 : case ARM::D10_D11_D12: OpKind = MCK_Reg85; break;
7245 : case ARM::D11_D12_D13: OpKind = MCK_Reg90; break;
7246 : case ARM::D12_D13_D14: OpKind = MCK_Reg85; break;
7247 : case ARM::D13_D14_D15: OpKind = MCK_Reg90; break;
7248 : case ARM::D14_D15_D16: OpKind = MCK_Reg86; break;
7249 : case ARM::D15_D16_D17: OpKind = MCK_Reg91; break;
7250 : case ARM::D16_D17_D18: OpKind = MCK_Reg87; break;
7251 : case ARM::D17_D18_D19: OpKind = MCK_Reg92; break;
7252 : case ARM::D18_D19_D20: OpKind = MCK_Reg87; break;
7253 : case ARM::D19_D20_D21: OpKind = MCK_Reg92; break;
7254 : case ARM::D20_D21_D22: OpKind = MCK_Reg87; break;
7255 : case ARM::D21_D22_D23: OpKind = MCK_Reg92; break;
7256 : case ARM::D22_D23_D24: OpKind = MCK_Reg87; break;
7257 : case ARM::D23_D24_D25: OpKind = MCK_Reg92; break;
7258 : case ARM::D24_D25_D26: OpKind = MCK_Reg87; break;
7259 : case ARM::D25_D26_D27: OpKind = MCK_Reg92; break;
7260 : case ARM::D26_D27_D28: OpKind = MCK_Reg87; break;
7261 : case ARM::D27_D28_D29: OpKind = MCK_Reg92; break;
7262 : case ARM::D28_D29_D30: OpKind = MCK_Reg87; break;
7263 : case ARM::D29_D30_D31: OpKind = MCK_Reg92; break;
7264 : case ARM::D0_D2_D4: OpKind = MCK_Reg93; break;
7265 : case ARM::D1_D3_D5: OpKind = MCK_Reg93; break;
7266 : case ARM::D2_D4_D6: OpKind = MCK_Reg93; break;
7267 : case ARM::D3_D5_D7: OpKind = MCK_Reg93; break;
7268 : case ARM::D4_D6_D8: OpKind = MCK_Reg94; break;
7269 : case ARM::D5_D7_D9: OpKind = MCK_Reg94; break;
7270 : case ARM::D6_D8_D10: OpKind = MCK_Reg95; break;
7271 : case ARM::D7_D9_D11: OpKind = MCK_Reg95; break;
7272 : case ARM::D8_D10_D12: OpKind = MCK_Reg96; break;
7273 : case ARM::D9_D11_D13: OpKind = MCK_Reg96; break;
7274 : case ARM::D10_D12_D14: OpKind = MCK_Reg96; break;
7275 : case ARM::D11_D13_D15: OpKind = MCK_Reg96; break;
7276 : case ARM::D12_D14_D16: OpKind = MCK_Reg97; break;
7277 : case ARM::D13_D15_D17: OpKind = MCK_Reg97; break;
7278 : case ARM::D14_D16_D18: OpKind = MCK_Reg98; break;
7279 : case ARM::D15_D17_D19: OpKind = MCK_Reg98; break;
7280 : case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break;
7281 : case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break;
7282 : case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break;
7283 : case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break;
7284 : case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break;
7285 : case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break;
7286 : case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break;
7287 : case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break;
7288 : case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break;
7289 : case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break;
7290 : case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break;
7291 : case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break;
7292 : case ARM::D1_D2: OpKind = MCK_Reg26; break;
7293 : case ARM::D3_D4: OpKind = MCK_Reg26; break;
7294 : case ARM::D5_D6: OpKind = MCK_Reg26; break;
7295 : case ARM::D7_D8: OpKind = MCK_Reg27; break;
7296 : case ARM::D9_D10: OpKind = MCK_Reg24; break;
7297 : case ARM::D11_D12: OpKind = MCK_Reg24; break;
7298 : case ARM::D13_D14: OpKind = MCK_Reg24; break;
7299 : case ARM::D15_D16: OpKind = MCK_Reg25; break;
7300 : case ARM::D17_D18: OpKind = MCK_DPair; break;
7301 : case ARM::D19_D20: OpKind = MCK_DPair; break;
7302 : case ARM::D21_D22: OpKind = MCK_DPair; break;
7303 : case ARM::D23_D24: OpKind = MCK_DPair; break;
7304 : case ARM::D25_D26: OpKind = MCK_DPair; break;
7305 : case ARM::D27_D28: OpKind = MCK_DPair; break;
7306 : case ARM::D29_D30: OpKind = MCK_DPair; break;
7307 : case ARM::D1_D2_D3_D4: OpKind = MCK_Reg100; break;
7308 : case ARM::D3_D4_D5_D6: OpKind = MCK_Reg100; break;
7309 : case ARM::D5_D6_D7_D8: OpKind = MCK_Reg101; break;
7310 : case ARM::D7_D8_D9_D10: OpKind = MCK_Reg102; break;
7311 : case ARM::D9_D10_D11_D12: OpKind = MCK_Reg103; break;
7312 : case ARM::D11_D12_D13_D14: OpKind = MCK_Reg103; break;
7313 : case ARM::D13_D14_D15_D16: OpKind = MCK_Reg104; break;
7314 : case ARM::D15_D16_D17_D18: OpKind = MCK_Reg105; break;
7315 : case ARM::D17_D18_D19_D20: OpKind = MCK_Reg106; break;
7316 : case ARM::D19_D20_D21_D22: OpKind = MCK_Reg106; break;
7317 : case ARM::D21_D22_D23_D24: OpKind = MCK_Reg106; break;
7318 : case ARM::D23_D24_D25_D26: OpKind = MCK_Reg106; break;
7319 : case ARM::D25_D26_D27_D28: OpKind = MCK_Reg106; break;
7320 : case ARM::D27_D28_D29_D30: OpKind = MCK_Reg106; break;
7321 : }
7322 261476 : return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
7323 : getDiagKindFromRegisterClass(Kind);
7324 : }
7325 :
7326 209950 : if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
7327 : return getDiagKindFromRegisterClass(Kind);
7328 :
7329 : return MCTargetAsmParser::Match_InvalidOperand;
7330 : }
7331 :
7332 : #ifndef NDEBUG
7333 : const char *getMatchClassName(MatchClassKind Kind) {
7334 : switch (Kind) {
7335 : case InvalidMatchClass: return "InvalidMatchClass";
7336 : case OptionalMatchClass: return "OptionalMatchClass";
7337 : case MCK__DOT_d: return "MCK__DOT_d";
7338 : case MCK__DOT_f: return "MCK__DOT_f";
7339 : case MCK__DOT_s16: return "MCK__DOT_s16";
7340 : case MCK__DOT_s32: return "MCK__DOT_s32";
7341 : case MCK__DOT_s64: return "MCK__DOT_s64";
7342 : case MCK__DOT_s8: return "MCK__DOT_s8";
7343 : case MCK__DOT_u16: return "MCK__DOT_u16";
7344 : case MCK__DOT_u32: return "MCK__DOT_u32";
7345 : case MCK__DOT_u64: return "MCK__DOT_u64";
7346 : case MCK__DOT_u8: return "MCK__DOT_u8";
7347 : case MCK__DOT_f32: return "MCK__DOT_f32";
7348 : case MCK__DOT_f64: return "MCK__DOT_f64";
7349 : case MCK__DOT_i16: return "MCK__DOT_i16";
7350 : case MCK__DOT_i32: return "MCK__DOT_i32";
7351 : case MCK__DOT_i64: return "MCK__DOT_i64";
7352 : case MCK__DOT_i8: return "MCK__DOT_i8";
7353 : case MCK__DOT_p16: return "MCK__DOT_p16";
7354 : case MCK__DOT_p8: return "MCK__DOT_p8";
7355 : case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
7356 : case MCK__35_0: return "MCK__35_0";
7357 : case MCK__DOT_16: return "MCK__DOT_16";
7358 : case MCK__DOT_32: return "MCK__DOT_32";
7359 : case MCK__DOT_64: return "MCK__DOT_64";
7360 : case MCK__DOT_8: return "MCK__DOT_8";
7361 : case MCK__DOT_f16: return "MCK__DOT_f16";
7362 : case MCK__DOT_p64: return "MCK__DOT_p64";
7363 : case MCK__DOT_w: return "MCK__DOT_w";
7364 : case MCK__91_: return "MCK__91_";
7365 : case MCK__93_: return "MCK__93_";
7366 : case MCK__94_: return "MCK__94_";
7367 : case MCK__123_: return "MCK__123_";
7368 : case MCK__125_: return "MCK__125_";
7369 : case MCK_Reg11: return "MCK_Reg11";
7370 : case MCK_Reg59: return "MCK_Reg59";
7371 : case MCK_Reg75: return "MCK_Reg75";
7372 : case MCK_APSR: return "MCK_APSR";
7373 : case MCK_APSR_NZCV: return "MCK_APSR_NZCV";
7374 : case MCK_CCR: return "MCK_CCR";
7375 : case MCK_FPEXC: return "MCK_FPEXC";
7376 : case MCK_FPINST: return "MCK_FPINST";
7377 : case MCK_FPINST2: return "MCK_FPINST2";
7378 : case MCK_FPSCR: return "MCK_FPSCR";
7379 : case MCK_FPSID: return "MCK_FPSID";
7380 : case MCK_GPRsp: return "MCK_GPRsp";
7381 : case MCK_LR: return "MCK_LR";
7382 : case MCK_MVFR0: return "MCK_MVFR0";
7383 : case MCK_MVFR1: return "MCK_MVFR1";
7384 : case MCK_MVFR2: return "MCK_MVFR2";
7385 : case MCK_PC: return "MCK_PC";
7386 : case MCK_SPSR: return "MCK_SPSR";
7387 : case MCK_Reg60: return "MCK_Reg60";
7388 : case MCK_Reg68: return "MCK_Reg68";
7389 : case MCK_Reg73: return "MCK_Reg73";
7390 : case MCK_Reg100: return "MCK_Reg100";
7391 : case MCK_Reg45: return "MCK_Reg45";
7392 : case MCK_Reg61: return "MCK_Reg61";
7393 : case MCK_Reg72: return "MCK_Reg72";
7394 : case MCK_Reg74: return "MCK_Reg74";
7395 : case MCK_Reg83: return "MCK_Reg83";
7396 : case MCK_Reg88: return "MCK_Reg88";
7397 : case MCK_Reg101: return "MCK_Reg101";
7398 : case MCK_Reg0: return "MCK_Reg0";
7399 : case MCK_Reg46: return "MCK_Reg46";
7400 : case MCK_Reg62: return "MCK_Reg62";
7401 : case MCK_Reg69: return "MCK_Reg69";
7402 : case MCK_Reg84: return "MCK_Reg84";
7403 : case MCK_Reg89: return "MCK_Reg89";
7404 : case MCK_Reg93: return "MCK_Reg93";
7405 : case MCK_Reg102: return "MCK_Reg102";
7406 : case MCK_QPR_8: return "MCK_QPR_8";
7407 : case MCK_Reg57: return "MCK_Reg57";
7408 : case MCK_Reg63: return "MCK_Reg63";
7409 : case MCK_tcGPR: return "MCK_tcGPR";
7410 : case MCK_Reg10: return "MCK_Reg10";
7411 : case MCK_Reg40: return "MCK_Reg40";
7412 : case MCK_Reg58: return "MCK_Reg58";
7413 : case MCK_Reg64: return "MCK_Reg64";
7414 : case MCK_Reg70: return "MCK_Reg70";
7415 : case MCK_Reg76: return "MCK_Reg76";
7416 : case MCK_Reg94: return "MCK_Reg94";
7417 : case MCK_Reg103: return "MCK_Reg103";
7418 : case MCK_Reg8: return "MCK_Reg8";
7419 : case MCK_Reg26: return "MCK_Reg26";
7420 : case MCK_Reg47: return "MCK_Reg47";
7421 : case MCK_Reg55: return "MCK_Reg55";
7422 : case MCK_Reg65: return "MCK_Reg65";
7423 : case MCK_Reg77: return "MCK_Reg77";
7424 : case MCK_Reg85: return "MCK_Reg85";
7425 : case MCK_Reg90: return "MCK_Reg90";
7426 : case MCK_Reg104: return "MCK_Reg104";
7427 : case MCK_GPRPair: return "MCK_GPRPair";
7428 : case MCK_Reg27: return "MCK_Reg27";
7429 : case MCK_Reg41: return "MCK_Reg41";
7430 : case MCK_Reg48: return "MCK_Reg48";
7431 : case MCK_Reg56: return "MCK_Reg56";
7432 : case MCK_Reg66: return "MCK_Reg66";
7433 : case MCK_Reg78: return "MCK_Reg78";
7434 : case MCK_Reg86: return "MCK_Reg86";
7435 : case MCK_Reg91: return "MCK_Reg91";
7436 : case MCK_Reg95: return "MCK_Reg95";
7437 : case MCK_Reg105: return "MCK_Reg105";
7438 : case MCK_DPR_8: return "MCK_DPR_8";
7439 : case MCK_QPR_VFP2: return "MCK_QPR_VFP2";
7440 : case MCK_hGPR: return "MCK_hGPR";
7441 : case MCK_tGPR: return "MCK_tGPR";
7442 : case MCK_tGPRwithpc: return "MCK_tGPRwithpc";
7443 : case MCK_Reg96: return "MCK_Reg96";
7444 : case MCK_Reg53: return "MCK_Reg53";
7445 : case MCK_QQQQPR: return "MCK_QQQQPR";
7446 : case MCK_Reg42: return "MCK_Reg42";
7447 : case MCK_Reg54: return "MCK_Reg54";
7448 : case MCK_Reg79: return "MCK_Reg79";
7449 : case MCK_Reg97: return "MCK_Reg97";
7450 : case MCK_Reg106: return "MCK_Reg106";
7451 : case MCK_rGPR: return "MCK_rGPR";
7452 : case MCK_Reg24: return "MCK_Reg24";
7453 : case MCK_Reg51: return "MCK_Reg51";
7454 : case MCK_Reg80: return "MCK_Reg80";
7455 : case MCK_Reg87: return "MCK_Reg87";
7456 : case MCK_Reg92: return "MCK_Reg92";
7457 : case MCK_GPRnopc: return "MCK_GPRnopc";
7458 : case MCK_QQPR: return "MCK_QQPR";
7459 : case MCK_Reg25: return "MCK_Reg25";
7460 : case MCK_Reg43: return "MCK_Reg43";
7461 : case MCK_Reg52: return "MCK_Reg52";
7462 : case MCK_Reg81: return "MCK_Reg81";
7463 : case MCK_Reg98: return "MCK_Reg98";
7464 : case MCK_DPR_VFP2: return "MCK_DPR_VFP2";
7465 : case MCK_GPR: return "MCK_GPR";
7466 : case MCK_GPRwithAPSR: return "MCK_GPRwithAPSR";
7467 : case MCK_QPR: return "MCK_QPR";
7468 : case MCK_SPR_8: return "MCK_SPR_8";
7469 : case MCK_DTripleSpc: return "MCK_DTripleSpc";
7470 : case MCK_DQuad: return "MCK_DQuad";
7471 : case MCK_DPairSpc: return "MCK_DPairSpc";
7472 : case MCK_DTriple: return "MCK_DTriple";
7473 : case MCK_DPair: return "MCK_DPair";
7474 : case MCK_DPR: return "MCK_DPR";
7475 : case MCK_HPR: return "MCK_HPR";
7476 : case MCK_AM2OffsetImm: return "MCK_AM2OffsetImm";
7477 : case MCK_AM3Offset: return "MCK_AM3Offset";
7478 : case MCK_ARMBranchTarget: return "MCK_ARMBranchTarget";
7479 : case MCK_AddrMode3: return "MCK_AddrMode3";
7480 : case MCK_AddrMode5: return "MCK_AddrMode5";
7481 : case MCK_AddrMode5FP16: return "MCK_AddrMode5FP16";
7482 : case MCK_AlignedMemory16: return "MCK_AlignedMemory16";
7483 : case MCK_AlignedMemory32: return "MCK_AlignedMemory32";
7484 : case MCK_AlignedMemory64: return "MCK_AlignedMemory64";
7485 : case MCK_AlignedMemory64or128: return "MCK_AlignedMemory64or128";
7486 : case MCK_AlignedMemory64or128or256: return "MCK_AlignedMemory64or128or256";
7487 : case MCK_AlignedMemoryNone: return "MCK_AlignedMemoryNone";
7488 : case MCK_AlignedMemory: return "MCK_AlignedMemory";
7489 : case MCK_DupAlignedMemory16: return "MCK_DupAlignedMemory16";
7490 : case MCK_DupAlignedMemory32: return "MCK_DupAlignedMemory32";
7491 : case MCK_DupAlignedMemory64: return "MCK_DupAlignedMemory64";
7492 : case MCK_DupAlignedMemory64or128: return "MCK_DupAlignedMemory64or128";
7493 : case MCK_DupAlignedMemoryNone: return "MCK_DupAlignedMemoryNone";
7494 : case MCK_AdrLabel: return "MCK_AdrLabel";
7495 : case MCK_BankedReg: return "MCK_BankedReg";
7496 : case MCK_Bitfield: return "MCK_Bitfield";
7497 : case MCK_CCOut: return "MCK_CCOut";
7498 : case MCK_CondCode: return "MCK_CondCode";
7499 : case MCK_CoprocNum: return "MCK_CoprocNum";
7500 : case MCK_CoprocOption: return "MCK_CoprocOption";
7501 : case MCK_CoprocReg: return "MCK_CoprocReg";
7502 : case MCK_DPRRegList: return "MCK_DPRRegList";
7503 : case MCK_FPImm: return "MCK_FPImm";
7504 : case MCK_Imm0_15: return "MCK_Imm0_15";
7505 : case MCK_Imm0_1: return "MCK_Imm0_1";
7506 : case MCK_Imm0_239: return "MCK_Imm0_239";
7507 : case MCK_Imm0_255: return "MCK_Imm0_255";
7508 : case MCK_Imm0_31: return "MCK_Imm0_31";
7509 : case MCK_Imm0_32: return "MCK_Imm0_32";
7510 : case MCK_Imm0_3: return "MCK_Imm0_3";
7511 : case MCK_Imm0_63: return "MCK_Imm0_63";
7512 : case MCK_Imm0_65535: return "MCK_Imm0_65535";
7513 : case MCK_Imm0_65535Expr: return "MCK_Imm0_65535Expr";
7514 : case MCK_Imm0_7: return "MCK_Imm0_7";
7515 : case MCK_Imm16: return "MCK_Imm16";
7516 : case MCK_Imm1_15: return "MCK_Imm1_15";
7517 : case MCK_Imm1_16: return "MCK_Imm1_16";
7518 : case MCK_Imm1_31: return "MCK_Imm1_31";
7519 : case MCK_Imm1_32: return "MCK_Imm1_32";
7520 : case MCK_Imm1_7: return "MCK_Imm1_7";
7521 : case MCK_Imm24bit: return "MCK_Imm24bit";
7522 : case MCK_Imm256_65535Expr: return "MCK_Imm256_65535Expr";
7523 : case MCK_Imm32: return "MCK_Imm32";
7524 : case MCK_Imm8: return "MCK_Imm8";
7525 : case MCK_Imm8_255: return "MCK_Imm8_255";
7526 : case MCK_Imm: return "MCK_Imm";
7527 : case MCK_InstSyncBarrierOpt: return "MCK_InstSyncBarrierOpt";
7528 : case MCK_MSRMask: return "MCK_MSRMask";
7529 : case MCK_MemBarrierOpt: return "MCK_MemBarrierOpt";
7530 : case MCK_MemImm0_1020s4Offset: return "MCK_MemImm0_1020s4Offset";
7531 : case MCK_MemImm12Offset: return "MCK_MemImm12Offset";
7532 : case MCK_MemImm8Offset: return "MCK_MemImm8Offset";
7533 : case MCK_MemImm8s4Offset: return "MCK_MemImm8s4Offset";
7534 : case MCK_MemNegImm8Offset: return "MCK_MemNegImm8Offset";
7535 : case MCK_MemNoOffset: return "MCK_MemNoOffset";
7536 : case MCK_MemPosImm8Offset: return "MCK_MemPosImm8Offset";
7537 : case MCK_MemRegOffset: return "MCK_MemRegOffset";
7538 : case MCK_ModImm: return "MCK_ModImm";
7539 : case MCK_ModImmNeg: return "MCK_ModImmNeg";
7540 : case MCK_ModImmNot: return "MCK_ModImmNot";
7541 : case MCK_PKHASRImm: return "MCK_PKHASRImm";
7542 : case MCK_PKHLSLImm: return "MCK_PKHLSLImm";
7543 : case MCK_PostIdxImm8: return "MCK_PostIdxImm8";
7544 : case MCK_PostIdxImm8s4: return "MCK_PostIdxImm8s4";
7545 : case MCK_PostIdxReg: return "MCK_PostIdxReg";
7546 : case MCK_PostIdxRegShifted: return "MCK_PostIdxRegShifted";
7547 : case MCK_ProcIFlags: return "MCK_ProcIFlags";
7548 : case MCK_RegList: return "MCK_RegList";
7549 : case MCK_RotImm: return "MCK_RotImm";
7550 : case MCK_SPRRegList: return "MCK_SPRRegList";
7551 : case MCK_SetEndImm: return "MCK_SetEndImm";
7552 : case MCK_RegShiftedImm: return "MCK_RegShiftedImm";
7553 : case MCK_RegShiftedReg: return "MCK_RegShiftedReg";
7554 : case MCK_ShifterImm: return "MCK_ShifterImm";
7555 : case MCK_ThumbBranchTarget: return "MCK_ThumbBranchTarget";
7556 : case MCK_ThumbMemPC: return "MCK_ThumbMemPC";
7557 : case MCK_ThumbModImmNeg1_7: return "MCK_ThumbModImmNeg1_7";
7558 : case MCK_ThumbModImmNeg8_255: return "MCK_ThumbModImmNeg8_255";
7559 : case MCK_ImmThumbSR: return "MCK_ImmThumbSR";
7560 : case MCK_TraceSyncBarrierOpt: return "MCK_TraceSyncBarrierOpt";
7561 : case MCK_UnsignedOffset_b8s2: return "MCK_UnsignedOffset_b8s2";
7562 : case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes";
7563 : case MCK_VecListDPair: return "MCK_VecListDPair";
7564 : case MCK_VecListDPairSpacedAllLanes: return "MCK_VecListDPairSpacedAllLanes";
7565 : case MCK_VecListDPairSpaced: return "MCK_VecListDPairSpaced";
7566 : case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes";
7567 : case MCK_VecListFourD: return "MCK_VecListFourD";
7568 : case MCK_VecListFourDByteIndexed: return "MCK_VecListFourDByteIndexed";
7569 : case MCK_VecListFourDHWordIndexed: return "MCK_VecListFourDHWordIndexed";
7570 : case MCK_VecListFourDWordIndexed: return "MCK_VecListFourDWordIndexed";
7571 : case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes";
7572 : case MCK_VecListFourQ: return "MCK_VecListFourQ";
7573 : case MCK_VecListFourQHWordIndexed: return "MCK_VecListFourQHWordIndexed";
7574 : case MCK_VecListFourQWordIndexed: return "MCK_VecListFourQWordIndexed";
7575 : case MCK_VecListOneDAllLanes: return "MCK_VecListOneDAllLanes";
7576 : case MCK_VecListOneD: return "MCK_VecListOneD";
7577 : case MCK_VecListOneDByteIndexed: return "MCK_VecListOneDByteIndexed";
7578 : case MCK_VecListOneDHWordIndexed: return "MCK_VecListOneDHWordIndexed";
7579 : case MCK_VecListOneDWordIndexed: return "MCK_VecListOneDWordIndexed";
7580 : case MCK_VecListThreeDAllLanes: return "MCK_VecListThreeDAllLanes";
7581 : case MCK_VecListThreeD: return "MCK_VecListThreeD";
7582 : case MCK_VecListThreeDByteIndexed: return "MCK_VecListThreeDByteIndexed";
7583 : case MCK_VecListThreeDHWordIndexed: return "MCK_VecListThreeDHWordIndexed";
7584 : case MCK_VecListThreeDWordIndexed: return "MCK_VecListThreeDWordIndexed";
7585 : case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes";
7586 : case MCK_VecListThreeQ: return "MCK_VecListThreeQ";
7587 : case MCK_VecListThreeQHWordIndexed: return "MCK_VecListThreeQHWordIndexed";
7588 : case MCK_VecListThreeQWordIndexed: return "MCK_VecListThreeQWordIndexed";
7589 : case MCK_VecListTwoDByteIndexed: return "MCK_VecListTwoDByteIndexed";
7590 : case MCK_VecListTwoDHWordIndexed: return "MCK_VecListTwoDHWordIndexed";
7591 : case MCK_VecListTwoDWordIndexed: return "MCK_VecListTwoDWordIndexed";
7592 : case MCK_VecListTwoQHWordIndexed: return "MCK_VecListTwoQHWordIndexed";
7593 : case MCK_VecListTwoQWordIndexed: return "MCK_VecListTwoQWordIndexed";
7594 : case MCK_VectorIndex16: return "MCK_VectorIndex16";
7595 : case MCK_VectorIndex32: return "MCK_VectorIndex32";
7596 : case MCK_VectorIndex64: return "MCK_VectorIndex64";
7597 : case MCK_VectorIndex8: return "MCK_VectorIndex8";
7598 : case MCK_MemTBB: return "MCK_MemTBB";
7599 : case MCK_MemTBH: return "MCK_MemTBH";
7600 : case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven";
7601 : case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd";
7602 : case MCK_NEONi16vmovi8Replicate: return "MCK_NEONi16vmovi8Replicate";
7603 : case MCK_NEONi16invi8Replicate: return "MCK_NEONi16invi8Replicate";
7604 : case MCK_NEONi32vmovi8Replicate: return "MCK_NEONi32vmovi8Replicate";
7605 : case MCK_NEONi32invi8Replicate: return "MCK_NEONi32invi8Replicate";
7606 : case MCK_NEONi64vmovi8Replicate: return "MCK_NEONi64vmovi8Replicate";
7607 : case MCK_NEONi64invi8Replicate: return "MCK_NEONi64invi8Replicate";
7608 : case MCK_NEONi32vmovi16Replicate: return "MCK_NEONi32vmovi16Replicate";
7609 : case MCK_NEONi64vmovi16Replicate: return "MCK_NEONi64vmovi16Replicate";
7610 : case MCK_NEONi64vmovi32Replicate: return "MCK_NEONi64vmovi32Replicate";
7611 : case MCK_ConstPoolAsmImm: return "MCK_ConstPoolAsmImm";
7612 : case MCK_FBits16: return "MCK_FBits16";
7613 : case MCK_FBits32: return "MCK_FBits32";
7614 : case MCK_Imm0_4095: return "MCK_Imm0_4095";
7615 : case MCK_Imm0_4095Neg: return "MCK_Imm0_4095Neg";
7616 : case MCK_ITMask: return "MCK_ITMask";
7617 : case MCK_ITCondCode: return "MCK_ITCondCode";
7618 : case MCK_NEONi16splat: return "MCK_NEONi16splat";
7619 : case MCK_NEONi32splat: return "MCK_NEONi32splat";
7620 : case MCK_NEONi64splat: return "MCK_NEONi64splat";
7621 : case MCK_NEONi8splat: return "MCK_NEONi8splat";
7622 : case MCK_NEONi16splatNot: return "MCK_NEONi16splatNot";
7623 : case MCK_NEONi32splatNot: return "MCK_NEONi32splatNot";
7624 : case MCK_NEONi32vmov: return "MCK_NEONi32vmov";
7625 : case MCK_NEONi32vmovNeg: return "MCK_NEONi32vmovNeg";
7626 : case MCK_ShrImm16: return "MCK_ShrImm16";
7627 : case MCK_ShrImm32: return "MCK_ShrImm32";
7628 : case MCK_ShrImm64: return "MCK_ShrImm64";
7629 : case MCK_ShrImm8: return "MCK_ShrImm8";
7630 : case MCK_T2SOImm: return "MCK_T2SOImm";
7631 : case MCK_T2SOImmNeg: return "MCK_T2SOImmNeg";
7632 : case MCK_T2SOImmNot: return "MCK_T2SOImmNot";
7633 : case MCK_MemUImm12Offset: return "MCK_MemUImm12Offset";
7634 : case MCK_T2MemRegOffset: return "MCK_T2MemRegOffset";
7635 : case MCK_Imm8s4: return "MCK_Imm8s4";
7636 : case MCK_MemPCRelImm12: return "MCK_MemPCRelImm12";
7637 : case MCK_MemThumbRIs1: return "MCK_MemThumbRIs1";
7638 : case MCK_MemThumbRIs2: return "MCK_MemThumbRIs2";
7639 : case MCK_MemThumbRIs4: return "MCK_MemThumbRIs4";
7640 : case MCK_MemThumbRR: return "MCK_MemThumbRR";
7641 : case MCK_MemThumbSPI: return "MCK_MemThumbSPI";
7642 : case MCK_Imm0_1020s4: return "MCK_Imm0_1020s4";
7643 : case MCK_Imm0_508s4: return "MCK_Imm0_508s4";
7644 : case MCK_Imm0_508s4Neg: return "MCK_Imm0_508s4Neg";
7645 : case NumMatchClassKinds: return "NumMatchClassKinds";
7646 : }
7647 : llvm_unreachable("unhandled MatchClassKind!");
7648 : }
7649 :
7650 : #endif // NDEBUG
7651 0 : uint64_t ARMAsmParser::
7652 : ComputeAvailableFeatures(const FeatureBitset& FB) const {
7653 : uint64_t Features = 0;
7654 0 : if ((FB[ARM::HasV4TOps]))
7655 : Features |= Feature_HasV4T;
7656 0 : if ((FB[ARM::HasV5TOps]))
7657 0 : Features |= Feature_HasV5T;
7658 0 : if ((FB[ARM::HasV5TEOps]))
7659 0 : Features |= Feature_HasV5TE;
7660 0 : if ((FB[ARM::HasV6Ops]))
7661 0 : Features |= Feature_HasV6;
7662 0 : if ((FB[ARM::HasV6MOps]))
7663 0 : Features |= Feature_HasV6M;
7664 0 : if ((FB[ARM::HasV8MBaselineOps]))
7665 0 : Features |= Feature_HasV8MBaseline;
7666 0 : if ((FB[ARM::HasV8MMainlineOps]))
7667 0 : Features |= Feature_HasV8MMainline;
7668 0 : if ((FB[ARM::HasV6T2Ops]))
7669 0 : Features |= Feature_HasV6T2;
7670 0 : if ((FB[ARM::HasV6KOps]))
7671 0 : Features |= Feature_HasV6K;
7672 0 : if ((FB[ARM::HasV7Ops]))
7673 0 : Features |= Feature_HasV7;
7674 0 : if ((FB[ARM::HasV8Ops]))
7675 0 : Features |= Feature_HasV8;
7676 0 : if ((!FB[ARM::HasV8Ops]))
7677 0 : Features |= Feature_PreV8;
7678 0 : if ((FB[ARM::HasV8_1aOps]))
7679 0 : Features |= Feature_HasV8_1a;
7680 0 : if ((FB[ARM::HasV8_2aOps]))
7681 0 : Features |= Feature_HasV8_2a;
7682 0 : if ((FB[ARM::HasV8_3aOps]))
7683 0 : Features |= Feature_HasV8_3a;
7684 0 : if ((FB[ARM::HasV8_4aOps]))
7685 0 : Features |= Feature_HasV8_4a;
7686 0 : if ((FB[ARM::HasV8_5aOps]))
7687 0 : Features |= Feature_HasV8_5a;
7688 0 : if ((FB[ARM::FeatureVFP2]))
7689 0 : Features |= Feature_HasVFP2;
7690 0 : if ((FB[ARM::FeatureVFP3]))
7691 0 : Features |= Feature_HasVFP3;
7692 0 : if ((FB[ARM::FeatureVFP4]))
7693 0 : Features |= Feature_HasVFP4;
7694 0 : if ((!FB[ARM::FeatureVFPOnlySP]))
7695 0 : Features |= Feature_HasDPVFP;
7696 0 : if ((FB[ARM::FeatureFPARMv8]))
7697 0 : Features |= Feature_HasFPARMv8;
7698 0 : if ((FB[ARM::FeatureNEON]))
7699 0 : Features |= Feature_HasNEON;
7700 0 : if ((FB[ARM::FeatureSHA2]))
7701 0 : Features |= Feature_HasSHA2;
7702 0 : if ((FB[ARM::FeatureAES]))
7703 0 : Features |= Feature_HasAES;
7704 0 : if ((FB[ARM::FeatureCrypto]))
7705 0 : Features |= Feature_HasCrypto;
7706 0 : if ((FB[ARM::FeatureDotProd]))
7707 0 : Features |= Feature_HasDotProd;
7708 0 : if ((FB[ARM::FeatureCRC]))
7709 0 : Features |= Feature_HasCRC;
7710 0 : if ((FB[ARM::FeatureRAS]))
7711 0 : Features |= Feature_HasRAS;
7712 0 : if ((FB[ARM::FeatureFP16]))
7713 0 : Features |= Feature_HasFP16;
7714 0 : if ((FB[ARM::FeatureFullFP16]))
7715 0 : Features |= Feature_HasFullFP16;
7716 0 : if ((FB[ARM::FeatureFP16FML]))
7717 0 : Features |= Feature_HasFP16FML;
7718 0 : if ((FB[ARM::FeatureHWDivThumb]))
7719 0 : Features |= Feature_HasDivideInThumb;
7720 0 : if ((FB[ARM::FeatureHWDivARM]))
7721 0 : Features |= Feature_HasDivideInARM;
7722 0 : if ((FB[ARM::FeatureDSP]))
7723 0 : Features |= Feature_HasDSP;
7724 0 : if ((FB[ARM::FeatureDB]))
7725 0 : Features |= Feature_HasDB;
7726 0 : if ((FB[ARM::FeatureDFB]))
7727 0 : Features |= Feature_HasDFB;
7728 0 : if ((FB[ARM::FeatureV7Clrex]))
7729 0 : Features |= Feature_HasV7Clrex;
7730 0 : if ((FB[ARM::FeatureAcquireRelease]))
7731 0 : Features |= Feature_HasAcquireRelease;
7732 0 : if ((FB[ARM::FeatureMP]))
7733 0 : Features |= Feature_HasMP;
7734 0 : if ((FB[ARM::FeatureVirtualization]))
7735 0 : Features |= Feature_HasVirtualization;
7736 0 : if ((FB[ARM::FeatureTrustZone]))
7737 0 : Features |= Feature_HasTrustZone;
7738 0 : if ((FB[ARM::Feature8MSecExt]))
7739 0 : Features |= Feature_Has8MSecExt;
7740 0 : if ((FB[ARM::ModeThumb]))
7741 0 : Features |= Feature_IsThumb;
7742 0 : if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2]))
7743 0 : Features |= Feature_IsThumb2;
7744 0 : if ((FB[ARM::FeatureMClass]))
7745 0 : Features |= Feature_IsMClass;
7746 0 : if ((!FB[ARM::FeatureMClass]))
7747 0 : Features |= Feature_IsNotMClass;
7748 0 : if ((!FB[ARM::ModeThumb]))
7749 0 : Features |= Feature_IsARM;
7750 0 : if ((FB[ARM::FeatureNaClTrap]))
7751 0 : Features |= Feature_UseNaClTrap;
7752 0 : if ((!FB[ARM::FeatureNoNegativeImmediates]))
7753 0 : Features |= Feature_UseNegativeImmediates;
7754 0 : if ((FB[ARM::FeatureSpecCtrl]))
7755 0 : Features |= Feature_HasSpecCtrl;
7756 0 : return Features;
7757 : }
7758 :
7759 : static const char *const MnemonicTable =
7760 : "\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005a"
7761 : "esmc\003and\003asr\001b\003bfc\003bfi\003bic\004bkpt\002bl\003blx\005bl"
7762 : "xns\002bx\003bxj\004bxns\004cbnz\003cbz\003cdp\004cdp2\005clrex\003clz\003"
7763 : "cmn\003cmp\003cps\006crc32b\007crc32cb\007crc32ch\007crc32cw\006crc32h\006"
7764 : "crc32w\004csdb\003dbg\005dcps1\005dcps2\005dcps3\003dfb\003dmb\003dsb\003"
7765 : "eor\004eret\003esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fconstd\007"
7766 : "fconsts\007fldmdbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fstmdbx\007"
7767 : "fstmiax\005fsubd\005fsubs\004hint\003hlt\003hvc\003isb\002it\003lda\004"
7768 : "ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ldc2\005l"
7769 : "dc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005ldrbt\004"
7770 : "ldrd\005ldrex\006ldrexb\006ldrexd\006ldrexh\004ldrh\005ldrht\005ldrsb\006"
7771 : "ldrsbt\005ldrsh\006ldrsht\004ldrt\003lsl\003lsr\003mcr\004mcr2\004mcrr\005"
7772 : "mcrr2\003mla\003mls\003mov\004movs\004movt\004movw\003mrc\004mrc2\004mr"
7773 : "rc\005mrrc2\003mrs\003msr\003mul\003mvn\003neg\003nop\003orn\003orr\005"
7774 : "pkhbt\005pkhtb\003pld\004pldw\003pli\003pop\005pssbb\004push\004qadd\006"
7775 : "qadd16\005qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005"
7776 : "qsub8\004rbit\003rev\005rev16\005revsh\005rfeda\005rfedb\005rfeia\005rf"
7777 : "eib\003ror\003rrx\003rsb\003rsc\006sadd16\005sadd8\004sasx\002sb\003sbc"
7778 : "\004sbfx\004sdiv\003sel\006setend\006setpan\003sev\004sevl\002sg\005sha"
7779 : "1c\005sha1h\005sha1m\005sha1p\007sha1su0\007sha1su1\007sha256h\010sha25"
7780 : "6h2\tsha256su0\tsha256su1\007shadd16\006shadd8\005shasx\005shsax\007shs"
7781 : "ub16\006shsub8\003smc\006smlabb\006smlabt\005smlad\006smladx\005smlal\007"
7782 : "smlalbb\007smlalbt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb"
7783 : "\006smlatt\006smlawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005"
7784 : "smmla\006smmlar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuad"
7785 : "x\006smulbb\006smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005"
7786 : "smusd\006smusdx\005srsda\005srsdb\005srsia\005srsib\004ssat\006ssat16\004"
7787 : "ssax\004ssbb\006ssub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004"
7788 : "stlb\005stlex\006stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005"
7789 : "stmdb\005stmib\003str\004strb\005strbt\004strd\005strex\006strexb\006st"
7790 : "rexd\006strexh\004strh\005strht\004strt\003sub\004subs\004subw\003svc\003"
7791 : "swp\004swpb\005sxtab\007sxtab16\005sxtah\004sxtb\006sxtb16\004sxth\003t"
7792 : "bb\003tbh\003teq\004trap\003tsb\003tst\002tt\003tta\004ttat\003ttt\006u"
7793 : "add16\005uadd8\004uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005u"
7794 : "hasx\005uhsax\007uhsub16\006uhsub8\005umaal\005umlal\005umull\007uqadd1"
7795 : "6\006uqadd8\005uqasx\005uqsax\007uqsub16\006uqsub8\005usad8\006usada8\004"
7796 : "usat\006usat16\004usax\006usub16\005usub8\005uxtab\007uxtab16\005uxtah\004"
7797 : "uxtb\006uxtb16\004uxth\004vaba\005vabal\004vabd\005vabdl\004vabs\005vac"
7798 : "ge\005vacgt\005vacle\005vaclt\004vadd\006vaddhn\005vaddl\005vaddw\004va"
7799 : "nd\004vbic\004vbif\004vbit\004vbsl\005vcadd\004vceq\004vcge\004vcgt\004"
7800 : "vcle\004vcls\004vclt\004vclz\005vcmla\004vcmp\005vcmpe\004vcnt\004vcvt\005"
7801 : "vcvta\005vcvtb\005vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vdiv\004"
7802 : "vdup\004veor\004vext\004vfma\005vfmal\004vfms\005vfmsl\005vfnma\005vfnm"
7803 : "s\005vhadd\005vhsub\004vins\005vjcvt\004vld1\004vld2\004vld3\004vld4\006"
7804 : "vldmdb\006vldmia\004vldr\005vlldm\005vlstm\004vmax\006vmaxnm\004vmin\006"
7805 : "vminnm\004vmla\005vmlal\004vmls\005vmlsl\004vmov\005vmovl\005vmovn\005v"
7806 : "movx\004vmrs\004vmsr\004vmul\005vmull\004vmvn\004vneg\005vnmla\005vnmls"
7807 : "\005vnmul\004vorn\004vorr\006vpadal\005vpadd\006vpaddl\005vpmax\005vpmi"
7808 : "n\004vpop\005vpush\005vqabs\005vqadd\007vqdmlal\007vqdmlsl\007vqdmulh\007"
7809 : "vqdmull\006vqmovn\007vqmovun\005vqneg\010vqrdmlah\010vqrdmlsh\010vqrdmu"
7810 : "lh\006vqrshl\007vqrshrn\010vqrshrun\005vqshl\006vqshlu\006vqshrn\007vqs"
7811 : "hrun\005vqsub\007vraddhn\006vrecpe\006vrecps\006vrev16\006vrev32\006vre"
7812 : "v64\006vrhadd\006vrinta\006vrintm\006vrintn\006vrintp\006vrintr\006vrin"
7813 : "tx\006vrintz\005vrshl\005vrshr\006vrshrn\007vrsqrte\007vrsqrts\005vrsra"
7814 : "\007vrsubhn\005vsdot\006vseleq\006vselge\006vselgt\006vselvs\004vshl\005"
7815 : "vshll\004vshr\005vshrn\004vsli\005vsqrt\004vsra\004vsri\004vst1\004vst2"
7816 : "\004vst3\004vst4\006vstmdb\006vstmia\004vstr\004vsub\006vsubhn\005vsubl"
7817 : "\005vsubw\004vswp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\004vuzp\004v"
7818 : "zip\003wfe\003wfi\005yield";
7819 :
7820 : namespace {
7821 : struct MatchEntry {
7822 : uint16_t Mnemonic;
7823 : uint16_t Opcode;
7824 : uint16_t ConvertFn;
7825 : uint64_t RequiredFeatures;
7826 : uint16_t Classes[18];
7827 0 : StringRef getMnemonic() const {
7828 15307 : return StringRef(MnemonicTable + Mnemonic + 1,
7829 15307 : MnemonicTable[Mnemonic]);
7830 : }
7831 : };
7832 :
7833 : // Predicate for searching for an opcode.
7834 : struct LessOpcode {
7835 0 : bool operator()(const MatchEntry &LHS, StringRef RHS) {
7836 0 : return LHS.getMnemonic() < RHS;
7837 : }
7838 0 : bool operator()(StringRef LHS, const MatchEntry &RHS) {
7839 0 : return LHS < RHS.getMnemonic();
7840 : }
7841 : bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
7842 : return LHS.getMnemonic() < RHS.getMnemonic();
7843 : }
7844 : };
7845 : } // end anonymous namespace.
7846 :
7847 : static const MatchEntry MatchTable0[] = {
7848 : { 0 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, Feature_IsThumb, { }, },
7849 : { 10 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
7850 : { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
7851 : { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
7852 : { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
7853 : { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
7854 : { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
7855 : { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7856 : { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
7857 : { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
7858 : { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
7859 : { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
7860 : { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
7861 : { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
7862 : { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
7863 : { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
7864 : { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7865 : { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
7866 : { 14 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, },
7867 : { 14 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
7868 : { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
7869 : { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095 }, },
7870 : { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, },
7871 : { 14 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
7872 : { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
7873 : { 14 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
7874 : { 14 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
7875 : { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
7876 : { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
7877 : { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
7878 : { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, },
7879 : { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, },
7880 : { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
7881 : { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
7882 : { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
7883 : { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
7884 : { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
7885 : { 14 /* add */, ARM::tADDspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
7886 : { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
7887 : { 14 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, },
7888 : { 14 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, },
7889 : { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
7890 : { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, },
7891 : { 14 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, },
7892 : { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImmNeg }, },
7893 : { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
7894 : { 14 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
7895 : { 14 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
7896 : { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
7897 : { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
7898 : { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
7899 : { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
7900 : { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
7901 : { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
7902 : { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
7903 : { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
7904 : { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
7905 : { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
7906 : { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
7907 : { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
7908 : { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
7909 : { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
7910 : { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
7911 : { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, },
7912 : { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
7913 : { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, },
7914 : { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, },
7915 : { 23 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, },
7916 : { 23 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
7917 : { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, },
7918 : { 23 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, },
7919 : { 27 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
7920 : { 32 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
7921 : { 37 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
7922 : { 44 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
7923 : { 50 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
7924 : { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
7925 : { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
7926 : { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
7927 : { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
7928 : { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
7929 : { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
7930 : { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
7931 : { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
7932 : { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
7933 : { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
7934 : { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
7935 : { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
7936 : { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
7937 : { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7938 : { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
7939 : { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
7940 : { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
7941 : { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
7942 : { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
7943 : { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
7944 : { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
7945 : { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
7946 : { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7947 : { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
7948 : { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
7949 : { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
7950 : { 54 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
7951 : { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
7952 : { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
7953 : { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
7954 : { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
7955 : { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
7956 : { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
7957 : { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
7958 : { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
7959 : { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7960 : { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
7961 : { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
7962 : { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
7963 : { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7964 : { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
7965 : { 58 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
7966 : { 58 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, Feature_IsThumb, { MCK_CondCode, MCK_Imm }, },
7967 : { 58 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, Feature_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
7968 : { 58 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
7969 : { 58 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
7970 : { 60 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, },
7971 : { 60 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, },
7972 : { 64 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, },
7973 : { 64 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, },
7974 : { 68 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
7975 : { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
7976 : { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
7977 : { 68 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
7978 : { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
7979 : { 68 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
7980 : { 68 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
7981 : { 68 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
7982 : { 68 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
7983 : { 68 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
7984 : { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
7985 : { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
7986 : { 68 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
7987 : { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
7988 : { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7989 : { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
7990 : { 68 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
7991 : { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
7992 : { 68 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
7993 : { 68 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
7994 : { 68 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
7995 : { 68 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
7996 : { 68 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
7997 : { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
7998 : { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
7999 : { 68 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8000 : { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
8001 : { 72 /* bkpt */, ARM::BKPT, Convert__imm_95_0, Feature_IsARM, { }, },
8002 : { 72 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, Feature_IsThumb, { }, },
8003 : { 72 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, Feature_IsThumb, { MCK_Imm0_255 }, },
8004 : { 72 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, Feature_IsARM, { MCK_Imm0_65535 }, },
8005 : { 77 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, Feature_IsARM, { MCK_ARMBranchTarget }, },
8006 : { 77 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
8007 : { 77 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, Feature_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
8008 : { 80 /* blx */, ARM::BLX, Convert__Reg1_0, Feature_IsARM|Feature_HasV5T, { MCK_GPR }, },
8009 : { 80 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, Feature_IsARM|Feature_HasV5T, { MCK_ThumbBranchTarget }, },
8010 : { 80 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, Feature_IsARM|Feature_HasV5T, { MCK_CondCode, MCK_GPR }, },
8011 : { 80 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, Feature_IsThumb|Feature_HasV5T, { MCK_CondCode, MCK_GPR }, },
8012 : { 80 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, Feature_IsThumb|Feature_HasV5T|Feature_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, },
8013 : { 84 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
8014 : { 90 /* bx */, ARM::BX, Convert__Reg1_0, Feature_IsARM|Feature_HasV4T, { MCK_GPR }, },
8015 : { 90 /* bx */, ARM::BX_RET, Convert__CondCode2_0, Feature_IsARM|Feature_HasV4T, { MCK_CondCode, MCK_LR }, },
8016 : { 90 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, Feature_IsARM|Feature_HasV4T, { MCK_CondCode, MCK_GPR }, },
8017 : { 90 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR }, },
8018 : { 93 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, },
8019 : { 93 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR }, },
8020 : { 97 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPR }, },
8021 : { 102 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
8022 : { 107 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
8023 : { 111 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8024 : { 111 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8025 : { 115 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8026 : { 115 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8027 : { 120 /* clrex */, ARM::CLREX, Convert_NoOperands, Feature_IsARM|Feature_HasV6K, { }, },
8028 : { 120 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, Feature_IsThumb|Feature_HasV7Clrex, { MCK_CondCode }, },
8029 : { 126 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8030 : { 126 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8031 : { 130 /* cmn */, ARM::tCMNz, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8032 : { 130 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
8033 : { 130 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
8034 : { 130 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
8035 : { 130 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
8036 : { 130 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
8037 : { 130 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
8038 : { 130 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8039 : { 130 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8040 : { 130 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8041 : { 130 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
8042 : { 130 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
8043 : { 130 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
8044 : { 134 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8045 : { 134 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
8046 : { 134 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
8047 : { 134 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
8048 : { 134 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
8049 : { 134 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
8050 : { 134 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
8051 : { 134 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8052 : { 134 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8053 : { 134 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8054 : { 134 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8055 : { 134 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
8056 : { 134 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
8057 : { 134 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
8058 : { 138 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm0_31 }, },
8059 : { 138 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
8060 : { 138 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, Feature_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, },
8061 : { 138 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, Feature_IsARM, { MCK_Imm, MCK_ProcIFlags }, },
8062 : { 138 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, Feature_IsThumb, { MCK_Imm, MCK_ProcIFlags }, },
8063 : { 138 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, },
8064 : { 138 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, Feature_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, },
8065 : { 138 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, },
8066 : { 138 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, Feature_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, },
8067 : { 142 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8068 : { 142 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8069 : { 149 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8070 : { 149 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8071 : { 157 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8072 : { 157 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8073 : { 165 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8074 : { 165 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8075 : { 173 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8076 : { 173 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8077 : { 180 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8078 : { 180 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8079 : { 187 /* csdb */, ARM::HINT, Convert__imm_95_20__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
8080 : { 187 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, Feature_IsThumb2, { MCK_CondCode }, },
8081 : { 187 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
8082 : { 192 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, Feature_IsARM|Feature_HasV7, { MCK_CondCode, MCK_Imm0_15 }, },
8083 : { 192 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, },
8084 : { 196 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
8085 : { 202 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
8086 : { 208 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
8087 : { 214 /* dfb */, ARM::DSB, Convert__imm_95_12, Feature_IsARM|Feature_HasDFB, { }, },
8088 : { 214 /* dfb */, ARM::t2DSB, Convert__imm_95_12__CondCode2_0, Feature_HasDFB, { MCK_CondCode }, },
8089 : { 218 /* dmb */, ARM::DMB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, { }, },
8090 : { 218 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, },
8091 : { 218 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_MemBarrierOpt }, },
8092 : { 218 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
8093 : { 222 /* dsb */, ARM::DSB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, { }, },
8094 : { 222 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, },
8095 : { 222 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_MemBarrierOpt }, },
8096 : { 222 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
8097 : { 226 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8098 : { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8099 : { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
8100 : { 226 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
8101 : { 226 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8102 : { 226 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8103 : { 226 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8104 : { 226 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
8105 : { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8106 : { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
8107 : { 226 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
8108 : { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8109 : { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8110 : { 226 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8111 : { 226 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8112 : { 226 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
8113 : { 226 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
8114 : { 226 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
8115 : { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8116 : { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8117 : { 226 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8118 : { 230 /* eret */, ARM::ERET, Convert__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode }, },
8119 : { 230 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, Feature_IsThumb2|Feature_HasVirtualization, { MCK_CondCode }, },
8120 : { 235 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, Feature_IsARM|Feature_HasRAS, { MCK_CondCode }, },
8121 : { 235 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, Feature_IsThumb2|Feature_HasRAS, { MCK_CondCode }, },
8122 : { 235 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, Feature_IsThumb2|Feature_HasRAS, { MCK_CondCode, MCK__DOT_w }, },
8123 : { 239 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
8124 : { 245 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
8125 : { 251 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR }, },
8126 : { 258 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR }, },
8127 : { 265 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, },
8128 : { 273 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, },
8129 : { 281 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
8130 : { 289 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
8131 : { 289 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
8132 : { 297 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
8133 : { 303 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
8134 : { 309 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, Feature_HasVFP2, { MCK_CondCode }, },
8135 : { 316 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
8136 : { 324 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
8137 : { 324 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
8138 : { 332 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
8139 : { 338 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
8140 : { 344 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, },
8141 : { 344 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_Imm0_239 }, },
8142 : { 344 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, },
8143 : { 344 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, },
8144 : { 349 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, Feature_IsThumb|Feature_HasV8, { MCK_Imm0_63 }, },
8145 : { 349 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, Feature_IsARM|Feature_HasV8, { MCK_Imm0_65535 }, },
8146 : { 353 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, Feature_IsARM|Feature_HasVirtualization, { MCK_Imm0_65535 }, },
8147 : { 353 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, Feature_IsThumb2, { MCK_Imm0_65535 }, },
8148 : { 353 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, Feature_IsThumb2|Feature_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, },
8149 : { 357 /* isb */, ARM::ISB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, { }, },
8150 : { 357 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, },
8151 : { 357 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_InstSyncBarrierOpt }, },
8152 : { 357 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, },
8153 : { 361 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, Feature_IsARM, { MCK_ITMask, MCK_ITCondCode }, },
8154 : { 361 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, Feature_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, },
8155 : { 364 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8156 : { 364 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8157 : { 368 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8158 : { 368 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8159 : { 373 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8160 : { 373 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8161 : { 379 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8162 : { 379 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8163 : { 386 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
8164 : { 386 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8165 : { 393 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8166 : { 393 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8167 : { 400 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8168 : { 400 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8169 : { 405 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8170 : { 405 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8171 : { 405 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8172 : { 405 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8173 : { 405 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8174 : { 405 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8175 : { 405 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8176 : { 405 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8177 : { 409 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8178 : { 409 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8179 : { 409 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8180 : { 409 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8181 : { 409 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8182 : { 409 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8183 : { 409 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8184 : { 409 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8185 : { 414 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8186 : { 414 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8187 : { 414 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8188 : { 414 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8189 : { 414 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8190 : { 414 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8191 : { 414 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8192 : { 414 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8193 : { 420 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8194 : { 420 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8195 : { 420 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8196 : { 420 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8197 : { 420 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8198 : { 420 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8199 : { 420 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8200 : { 420 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8201 : { 425 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, },
8202 : { 425 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8203 : { 425 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8204 : { 425 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
8205 : { 425 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
8206 : { 425 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8207 : { 425 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8208 : { 425 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8209 : { 425 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8210 : { 425 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8211 : { 429 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8212 : { 429 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8213 : { 429 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8214 : { 429 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8215 : { 435 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8216 : { 435 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8217 : { 435 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
8218 : { 435 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8219 : { 435 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8220 : { 435 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8221 : { 435 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8222 : { 435 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8223 : { 441 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8224 : { 441 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8225 : { 441 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8226 : { 441 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8227 : { 447 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, },
8228 : { 447 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, },
8229 : { 447 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
8230 : { 447 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8231 : { 447 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
8232 : { 447 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, },
8233 : { 447 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
8234 : { 447 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
8235 : { 447 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
8236 : { 447 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
8237 : { 447 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
8238 : { 447 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
8239 : { 447 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
8240 : { 447 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, },
8241 : { 447 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, },
8242 : { 447 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, },
8243 : { 447 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
8244 : { 447 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
8245 : { 447 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, },
8246 : { 447 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
8247 : { 447 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8248 : { 447 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8249 : { 447 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
8250 : { 447 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8251 : { 447 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
8252 : { 451 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
8253 : { 451 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8254 : { 451 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
8255 : { 451 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
8256 : { 451 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
8257 : { 451 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
8258 : { 451 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
8259 : { 451 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
8260 : { 451 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8261 : { 451 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
8262 : { 451 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
8263 : { 451 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
8264 : { 451 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8265 : { 451 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
8266 : { 451 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8267 : { 451 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8268 : { 451 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
8269 : { 451 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8270 : { 451 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
8271 : { 456 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
8272 : { 456 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8273 : { 456 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8274 : { 456 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8275 : { 462 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
8276 : { 462 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
8277 : { 462 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
8278 : { 462 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
8279 : { 462 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
8280 : { 462 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
8281 : { 467 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
8282 : { 467 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8283 : { 473 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8284 : { 473 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8285 : { 480 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
8286 : { 480 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8287 : { 487 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8288 : { 487 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8289 : { 494 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
8290 : { 494 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8291 : { 494 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
8292 : { 494 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
8293 : { 494 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
8294 : { 494 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
8295 : { 494 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8296 : { 494 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
8297 : { 494 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
8298 : { 494 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
8299 : { 494 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
8300 : { 494 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8301 : { 494 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
8302 : { 494 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8303 : { 494 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
8304 : { 494 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
8305 : { 499 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
8306 : { 499 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
8307 : { 499 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
8308 : { 505 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8309 : { 505 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
8310 : { 505 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
8311 : { 505 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
8312 : { 505 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
8313 : { 505 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8314 : { 505 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
8315 : { 505 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
8316 : { 505 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
8317 : { 505 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
8318 : { 505 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8319 : { 505 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
8320 : { 505 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8321 : { 505 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
8322 : { 505 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
8323 : { 511 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
8324 : { 511 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
8325 : { 511 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
8326 : { 518 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8327 : { 518 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
8328 : { 518 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
8329 : { 518 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
8330 : { 518 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
8331 : { 518 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8332 : { 518 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
8333 : { 518 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
8334 : { 518 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
8335 : { 518 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
8336 : { 518 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
8337 : { 518 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
8338 : { 518 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8339 : { 518 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
8340 : { 518 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
8341 : { 524 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
8342 : { 524 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
8343 : { 524 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
8344 : { 531 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
8345 : { 531 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8346 : { 531 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8347 : { 531 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8348 : { 536 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8349 : { 536 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, },
8350 : { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8351 : { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
8352 : { 536 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
8353 : { 536 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
8354 : { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8355 : { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
8356 : { 536 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, },
8357 : { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8358 : { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
8359 : { 536 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__35_0 }, },
8360 : { 536 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8361 : { 536 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
8362 : { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8363 : { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
8364 : { 536 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__35_0 }, },
8365 : { 540 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8366 : { 540 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
8367 : { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8368 : { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
8369 : { 540 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
8370 : { 540 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
8371 : { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8372 : { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
8373 : { 540 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
8374 : { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8375 : { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
8376 : { 540 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8377 : { 540 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
8378 : { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8379 : { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
8380 : { 544 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
8381 : { 544 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
8382 : { 544 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8383 : { 544 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8384 : { 548 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, Feature_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
8385 : { 548 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
8386 : { 548 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8387 : { 548 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8388 : { 553 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
8389 : { 553 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
8390 : { 558 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
8391 : { 558 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
8392 : { 564 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8393 : { 564 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8394 : { 564 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8395 : { 568 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8396 : { 568 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8397 : { 572 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_PC, MCK_LR }, },
8398 : { 572 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, },
8399 : { 572 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
8400 : { 572 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
8401 : { 572 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
8402 : { 572 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
8403 : { 572 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8404 : { 572 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
8405 : { 572 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, },
8406 : { 572 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
8407 : { 572 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
8408 : { 572 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
8409 : { 572 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8410 : { 572 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8411 : { 572 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8412 : { 572 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
8413 : { 572 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
8414 : { 572 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
8415 : { 572 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
8416 : { 572 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
8417 : { 572 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
8418 : { 576 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, Feature_IsThumb, { MCK_tGPR, MCK_tGPR }, },
8419 : { 576 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, Feature_IsThumb, { MCK_tGPR, MCK_Imm0_255 }, },
8420 : { 576 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
8421 : { 576 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
8422 : { 576 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
8423 : { 576 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
8424 : { 576 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
8425 : { 576 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
8426 : { 576 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
8427 : { 576 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
8428 : { 581 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
8429 : { 581 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, },
8430 : { 586 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
8431 : { 586 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
8432 : { 591 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
8433 : { 591 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
8434 : { 591 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8435 : { 591 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8436 : { 595 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, Feature_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
8437 : { 595 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
8438 : { 595 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8439 : { 595 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
8440 : { 600 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
8441 : { 600 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
8442 : { 605 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
8443 : { 605 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
8444 : { 611 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, Feature_IsThumb|Feature_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, },
8445 : { 611 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, Feature_IsThumb|Feature_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, },
8446 : { 611 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, },
8447 : { 611 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, },
8448 : { 611 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, },
8449 : { 611 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, },
8450 : { 611 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, },
8451 : { 611 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, },
8452 : { 611 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, },
8453 : { 615 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, },
8454 : { 615 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, },
8455 : { 615 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
8456 : { 615 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
8457 : { 615 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, },
8458 : { 615 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, },
8459 : { 619 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8460 : { 619 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8461 : { 619 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
8462 : { 619 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8463 : { 619 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
8464 : { 619 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8465 : { 619 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8466 : { 623 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8467 : { 623 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8468 : { 623 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
8469 : { 623 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
8470 : { 623 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
8471 : { 623 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
8472 : { 623 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
8473 : { 623 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8474 : { 623 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8475 : { 623 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8476 : { 623 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8477 : { 623 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
8478 : { 623 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
8479 : { 627 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8480 : { 627 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8481 : { 627 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8482 : { 631 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__imm_95_0, Feature_IsThumb, { }, },
8483 : { 631 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
8484 : { 631 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, },
8485 : { 631 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, Feature_IsARM, { MCK_CondCode }, },
8486 : { 631 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
8487 : { 635 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8488 : { 635 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
8489 : { 635 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
8490 : { 635 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
8491 : { 635 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8492 : { 635 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8493 : { 635 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8494 : { 635 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
8495 : { 639 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8496 : { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8497 : { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
8498 : { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
8499 : { 639 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
8500 : { 639 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8501 : { 639 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8502 : { 639 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8503 : { 639 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
8504 : { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8505 : { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
8506 : { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
8507 : { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8508 : { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8509 : { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8510 : { 639 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
8511 : { 639 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8512 : { 639 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
8513 : { 639 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
8514 : { 639 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
8515 : { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8516 : { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8517 : { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8518 : { 643 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8519 : { 643 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8520 : { 643 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, },
8521 : { 643 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, },
8522 : { 649 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8523 : { 649 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8524 : { 649 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, },
8525 : { 649 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, },
8526 : { 655 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, Feature_IsARM, { MCK_MemImm12Offset }, },
8527 : { 655 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, Feature_IsARM, { MCK_MemRegOffset }, },
8528 : { 655 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm }, },
8529 : { 655 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, },
8530 : { 655 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, },
8531 : { 655 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, },
8532 : { 655 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, },
8533 : { 659 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, Feature_IsARM|Feature_HasV7|Feature_HasMP, { MCK_MemImm12Offset }, },
8534 : { 659 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, Feature_IsARM|Feature_HasV7|Feature_HasMP, { MCK_MemRegOffset }, },
8535 : { 659 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, },
8536 : { 659 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, },
8537 : { 659 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, },
8538 : { 664 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, Feature_IsARM|Feature_HasV7, { MCK_MemImm12Offset }, },
8539 : { 664 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, Feature_IsARM|Feature_HasV7, { MCK_MemRegOffset }, },
8540 : { 664 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_Imm }, },
8541 : { 664 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, },
8542 : { 664 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, },
8543 : { 664 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, },
8544 : { 664 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, },
8545 : { 668 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, Feature_IsThumb, { MCK_CondCode, MCK_RegList }, },
8546 : { 668 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsThumb2, { MCK_CondCode, MCK_RegList }, },
8547 : { 668 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsARM, { MCK_CondCode, MCK_RegList }, },
8548 : { 668 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
8549 : { 672 /* pssbb */, ARM::t2DSB, Convert__imm_95_4__imm_95_14__imm_95_0, Feature_HasDB|Feature_IsThumb2, { }, },
8550 : { 672 /* pssbb */, ARM::DSB, Convert__imm_95_4, Feature_IsARM|Feature_HasDB, { }, },
8551 : { 678 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, Feature_IsThumb, { MCK_CondCode, MCK_RegList }, },
8552 : { 678 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsThumb2, { MCK_CondCode, MCK_RegList }, },
8553 : { 678 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsARM, { MCK_CondCode, MCK_RegList }, },
8554 : { 678 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
8555 : { 683 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8556 : { 683 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8557 : { 688 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8558 : { 688 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8559 : { 695 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8560 : { 695 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8561 : { 701 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8562 : { 701 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8563 : { 706 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8564 : { 706 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8565 : { 712 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8566 : { 712 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8567 : { 718 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8568 : { 718 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8569 : { 723 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8570 : { 723 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8571 : { 728 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8572 : { 728 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8573 : { 735 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8574 : { 735 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8575 : { 741 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8576 : { 741 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8577 : { 746 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8578 : { 746 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8579 : { 746 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8580 : { 746 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8581 : { 750 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8582 : { 750 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8583 : { 750 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8584 : { 750 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8585 : { 756 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8586 : { 756 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8587 : { 756 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
8588 : { 756 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8589 : { 762 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
8590 : { 762 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
8591 : { 768 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
8592 : { 768 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
8593 : { 768 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
8594 : { 768 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
8595 : { 774 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
8596 : { 774 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
8597 : { 774 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
8598 : { 774 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
8599 : { 780 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, },
8600 : { 780 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
8601 : { 786 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8602 : { 786 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8603 : { 786 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm0_31 }, },
8604 : { 786 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
8605 : { 786 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
8606 : { 786 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
8607 : { 786 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm0_31 }, },
8608 : { 786 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8609 : { 786 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, },
8610 : { 786 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8611 : { 786 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
8612 : { 786 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8613 : { 786 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, },
8614 : { 790 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8615 : { 790 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8616 : { 794 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
8617 : { 794 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
8618 : { 794 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
8619 : { 794 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8620 : { 794 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8621 : { 794 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8622 : { 794 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
8623 : { 794 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__35_0 }, },
8624 : { 794 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8625 : { 794 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8626 : { 794 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8627 : { 794 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8628 : { 794 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
8629 : { 794 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
8630 : { 794 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
8631 : { 794 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8632 : { 798 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8633 : { 798 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8634 : { 798 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8635 : { 798 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
8636 : { 798 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8637 : { 798 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
8638 : { 798 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
8639 : { 798 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
8640 : { 802 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8641 : { 802 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8642 : { 809 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8643 : { 809 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8644 : { 815 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8645 : { 815 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8646 : { 820 /* sb */, ARM::SB, Convert_NoOperands, Feature_IsARM|Feature_HasSpecCtrl, { }, },
8647 : { 820 /* sb */, ARM::t2SB, Convert_NoOperands, Feature_IsThumb2|Feature_HasSpecCtrl, { }, },
8648 : { 823 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8649 : { 823 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
8650 : { 823 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8651 : { 823 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8652 : { 823 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
8653 : { 823 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8654 : { 823 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8655 : { 823 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8656 : { 823 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
8657 : { 823 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
8658 : { 823 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
8659 : { 823 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8660 : { 823 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
8661 : { 823 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
8662 : { 823 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
8663 : { 823 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8664 : { 823 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
8665 : { 827 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
8666 : { 827 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
8667 : { 832 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasDivideInThumb|Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8668 : { 832 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8669 : { 837 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8670 : { 837 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8671 : { 841 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, Feature_IsThumb|Feature_IsNotMClass, { MCK_SetEndImm }, },
8672 : { 841 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, Feature_IsARM, { MCK_SetEndImm }, },
8673 : { 848 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, Feature_IsARM|Feature_HasV8|Feature_HasV8_1a, { MCK_Imm0_1 }, },
8674 : { 848 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, Feature_IsThumb2|Feature_HasV8|Feature_HasV8_1a, { MCK_Imm0_1 }, },
8675 : { 855 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
8676 : { 855 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, },
8677 : { 855 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
8678 : { 859 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, Feature_IsARM|Feature_HasV8, { MCK_CondCode }, },
8679 : { 859 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, },
8680 : { 859 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode, MCK__DOT_w }, },
8681 : { 864 /* sg */, ARM::t2SG, Convert__CondCode2_0, Feature_Has8MSecExt, { MCK_CondCode }, },
8682 : { 867 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
8683 : { 873 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
8684 : { 879 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
8685 : { 885 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
8686 : { 891 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
8687 : { 899 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
8688 : { 907 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
8689 : { 915 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
8690 : { 924 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
8691 : { 934 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
8692 : { 944 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8693 : { 944 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8694 : { 952 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8695 : { 952 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8696 : { 959 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8697 : { 959 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8698 : { 965 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8699 : { 965 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8700 : { 971 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8701 : { 971 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8702 : { 979 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8703 : { 979 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8704 : { 986 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, Feature_IsARM|Feature_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
8705 : { 986 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb2|Feature_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
8706 : { 990 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8707 : { 990 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8708 : { 997 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8709 : { 997 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8710 : { 1004 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8711 : { 1004 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8712 : { 1010 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8713 : { 1010 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8714 : { 1017 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8715 : { 1017 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8716 : { 1017 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8717 : { 1023 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8718 : { 1023 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8719 : { 1031 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8720 : { 1031 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8721 : { 1039 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8722 : { 1039 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8723 : { 1046 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8724 : { 1046 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8725 : { 1054 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8726 : { 1054 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8727 : { 1062 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8728 : { 1062 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8729 : { 1070 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8730 : { 1070 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8731 : { 1077 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8732 : { 1077 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8733 : { 1084 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8734 : { 1084 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8735 : { 1091 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8736 : { 1091 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8737 : { 1098 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8738 : { 1098 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8739 : { 1104 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8740 : { 1104 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
8741 : { 1111 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8742 : { 1111 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8743 : { 1118 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8744 : { 1118 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8745 : { 1126 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8746 : { 1126 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8747 : { 1132 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8748 : { 1132 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8749 : { 1139 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8750 : { 1139 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8751 : { 1145 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8752 : { 1145 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8753 : { 1152 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8754 : { 1152 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8755 : { 1158 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8756 : { 1158 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8757 : { 1165 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8758 : { 1165 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8759 : { 1171 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8760 : { 1171 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8761 : { 1178 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8762 : { 1178 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8763 : { 1185 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8764 : { 1185 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8765 : { 1192 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8766 : { 1192 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8767 : { 1192 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
8768 : { 1198 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8769 : { 1198 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8770 : { 1205 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8771 : { 1205 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8772 : { 1212 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8773 : { 1212 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8774 : { 1219 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8775 : { 1219 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8776 : { 1226 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8777 : { 1226 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8778 : { 1232 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8779 : { 1232 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8780 : { 1239 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
8781 : { 1239 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
8782 : { 1239 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
8783 : { 1239 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
8784 : { 1245 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
8785 : { 1245 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
8786 : { 1245 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
8787 : { 1245 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
8788 : { 1245 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
8789 : { 1245 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
8790 : { 1245 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
8791 : { 1245 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
8792 : { 1251 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
8793 : { 1251 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
8794 : { 1251 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
8795 : { 1251 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
8796 : { 1251 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
8797 : { 1251 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
8798 : { 1251 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
8799 : { 1251 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
8800 : { 1257 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, },
8801 : { 1257 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
8802 : { 1257 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
8803 : { 1257 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
8804 : { 1263 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, },
8805 : { 1263 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, },
8806 : { 1263 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, },
8807 : { 1263 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, },
8808 : { 1268 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, },
8809 : { 1268 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, },
8810 : { 1275 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8811 : { 1275 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8812 : { 1280 /* ssbb */, ARM::t2DSB, Convert__imm_95_0__imm_95_14__imm_95_0, Feature_HasDB|Feature_IsThumb2, { }, },
8813 : { 1280 /* ssbb */, ARM::DSB, Convert__imm_95_0, Feature_IsARM|Feature_HasDB, { }, },
8814 : { 1285 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8815 : { 1285 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8816 : { 1292 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
8817 : { 1292 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
8818 : { 1298 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8819 : { 1298 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8820 : { 1298 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8821 : { 1298 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8822 : { 1298 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8823 : { 1298 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8824 : { 1298 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8825 : { 1298 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8826 : { 1302 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8827 : { 1302 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8828 : { 1302 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8829 : { 1302 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8830 : { 1302 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8831 : { 1302 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8832 : { 1302 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8833 : { 1302 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8834 : { 1307 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8835 : { 1307 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8836 : { 1307 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8837 : { 1307 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8838 : { 1307 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8839 : { 1307 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8840 : { 1307 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8841 : { 1307 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8842 : { 1313 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8843 : { 1313 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
8844 : { 1313 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8845 : { 1313 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
8846 : { 1313 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8847 : { 1313 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
8848 : { 1313 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8849 : { 1313 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
8850 : { 1318 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8851 : { 1318 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8852 : { 1322 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8853 : { 1322 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8854 : { 1327 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8855 : { 1327 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
8856 : { 1333 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8857 : { 1333 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
8858 : { 1340 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
8859 : { 1340 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8860 : { 1347 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8861 : { 1347 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
8862 : { 1354 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
8863 : { 1354 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8864 : { 1359 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8865 : { 1359 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8866 : { 1359 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8867 : { 1359 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
8868 : { 1359 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
8869 : { 1359 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8870 : { 1359 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8871 : { 1359 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8872 : { 1359 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8873 : { 1359 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8874 : { 1363 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8875 : { 1363 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8876 : { 1363 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8877 : { 1363 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8878 : { 1369 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8879 : { 1369 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8880 : { 1369 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
8881 : { 1369 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8882 : { 1369 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8883 : { 1369 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8884 : { 1369 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8885 : { 1369 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8886 : { 1375 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
8887 : { 1375 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
8888 : { 1375 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
8889 : { 1375 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
8890 : { 1381 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
8891 : { 1381 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8892 : { 1381 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
8893 : { 1381 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
8894 : { 1381 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
8895 : { 1381 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
8896 : { 1381 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
8897 : { 1381 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
8898 : { 1381 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
8899 : { 1381 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
8900 : { 1381 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8901 : { 1381 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, },
8902 : { 1381 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
8903 : { 1381 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8904 : { 1381 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8905 : { 1381 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
8906 : { 1385 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
8907 : { 1385 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8908 : { 1385 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
8909 : { 1385 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
8910 : { 1385 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
8911 : { 1385 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
8912 : { 1385 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
8913 : { 1385 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
8914 : { 1385 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
8915 : { 1385 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8916 : { 1385 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
8917 : { 1385 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
8918 : { 1385 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8919 : { 1385 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8920 : { 1385 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
8921 : { 1390 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, },
8922 : { 1390 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8923 : { 1390 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8924 : { 1390 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8925 : { 1396 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
8926 : { 1396 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
8927 : { 1396 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
8928 : { 1396 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
8929 : { 1396 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
8930 : { 1396 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
8931 : { 1401 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
8932 : { 1401 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
8933 : { 1407 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8934 : { 1407 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
8935 : { 1414 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
8936 : { 1414 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8937 : { 1421 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
8938 : { 1421 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
8939 : { 1428 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
8940 : { 1428 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
8941 : { 1428 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
8942 : { 1428 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
8943 : { 1428 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
8944 : { 1428 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
8945 : { 1428 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
8946 : { 1428 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
8947 : { 1428 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
8948 : { 1428 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
8949 : { 1428 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
8950 : { 1428 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
8951 : { 1433 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, },
8952 : { 1433 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
8953 : { 1433 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, },
8954 : { 1439 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, },
8955 : { 1439 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
8956 : { 1439 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
8957 : { 1439 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
8958 : { 1444 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
8959 : { 1444 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095 }, },
8960 : { 1444 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
8961 : { 1444 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
8962 : { 1444 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
8963 : { 1444 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
8964 : { 1444 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
8965 : { 1444 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
8966 : { 1444 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
8967 : { 1444 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
8968 : { 1444 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
8969 : { 1444 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
8970 : { 1444 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
8971 : { 1444 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
8972 : { 1444 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
8973 : { 1444 /* sub */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, },
8974 : { 1444 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
8975 : { 1444 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
8976 : { 1444 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
8977 : { 1444 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
8978 : { 1444 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
8979 : { 1444 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
8980 : { 1444 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
8981 : { 1444 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
8982 : { 1444 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
8983 : { 1444 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
8984 : { 1444 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
8985 : { 1444 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
8986 : { 1444 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
8987 : { 1444 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
8988 : { 1444 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
8989 : { 1444 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
8990 : { 1444 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
8991 : { 1448 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_LR, MCK_Imm0_255 }, },
8992 : { 1453 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
8993 : { 1453 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, },
8994 : { 1453 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, },
8995 : { 1458 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, },
8996 : { 1458 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_Imm24bit }, },
8997 : { 1462 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
8998 : { 1466 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
8999 : { 1471 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9000 : { 1471 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
9001 : { 1471 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9002 : { 1471 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
9003 : { 1477 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9004 : { 1477 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
9005 : { 1477 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9006 : { 1477 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
9007 : { 1485 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9008 : { 1485 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
9009 : { 1485 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9010 : { 1485 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
9011 : { 1491 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
9012 : { 1491 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
9013 : { 1491 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
9014 : { 1491 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
9015 : { 1491 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9016 : { 1491 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
9017 : { 1491 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9018 : { 1496 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
9019 : { 1496 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
9020 : { 1496 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9021 : { 1496 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9022 : { 1496 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
9023 : { 1503 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
9024 : { 1503 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
9025 : { 1503 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
9026 : { 1503 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
9027 : { 1503 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9028 : { 1503 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
9029 : { 1503 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9030 : { 1508 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemTBB }, },
9031 : { 1512 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemTBH }, },
9032 : { 1516 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
9033 : { 1516 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
9034 : { 1516 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
9035 : { 1516 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
9036 : { 1516 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
9037 : { 1516 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
9038 : { 1516 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
9039 : { 1516 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
9040 : { 1516 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
9041 : { 1516 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
9042 : { 1520 /* trap */, ARM::TRAPNaCl, Convert_NoOperands, Feature_IsARM|Feature_UseNaClTrap, { }, },
9043 : { 1520 /* trap */, ARM::TRAP, Convert_NoOperands, Feature_IsARM, { }, },
9044 : { 1520 /* trap */, ARM::tTRAP, Convert_NoOperands, Feature_IsThumb, { }, },
9045 : { 1525 /* tsb */, ARM::TSB, Convert__TraceSyncBarrierOpt1_0, Feature_IsARM|Feature_HasV8_4a, { MCK_TraceSyncBarrierOpt }, },
9046 : { 1525 /* tsb */, ARM::t2TSB, Convert__TraceSyncBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasV8_4a, { MCK_CondCode, MCK_TraceSyncBarrierOpt }, },
9047 : { 1529 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
9048 : { 1529 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
9049 : { 1529 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
9050 : { 1529 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
9051 : { 1529 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
9052 : { 1529 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
9053 : { 1529 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
9054 : { 1529 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
9055 : { 1529 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
9056 : { 1529 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
9057 : { 1529 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
9058 : { 1533 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
9059 : { 1536 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
9060 : { 1540 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
9061 : { 1545 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
9062 : { 1549 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9063 : { 1549 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9064 : { 1556 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9065 : { 1556 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9066 : { 1562 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9067 : { 1562 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9068 : { 1567 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
9069 : { 1567 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
9070 : { 1572 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, Feature_IsThumb, { MCK_Imm0_255 }, },
9071 : { 1572 /* udf */, ARM::UDF, Convert__Imm0_655351_0, Feature_IsARM, { MCK_Imm0_65535 }, },
9072 : { 1572 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, Feature_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, },
9073 : { 1576 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasDivideInThumb|Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9074 : { 1576 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
9075 : { 1581 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9076 : { 1581 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9077 : { 1589 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9078 : { 1589 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9079 : { 1596 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9080 : { 1596 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9081 : { 1602 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9082 : { 1602 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9083 : { 1608 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9084 : { 1608 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9085 : { 1616 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9086 : { 1616 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9087 : { 1623 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9088 : { 1623 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
9089 : { 1629 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9090 : { 1629 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
9091 : { 1629 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
9092 : { 1635 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9093 : { 1635 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
9094 : { 1635 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
9095 : { 1641 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9096 : { 1641 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9097 : { 1649 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9098 : { 1649 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9099 : { 1656 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9100 : { 1656 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9101 : { 1662 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9102 : { 1662 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9103 : { 1668 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9104 : { 1668 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9105 : { 1676 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9106 : { 1676 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9107 : { 1683 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9108 : { 1683 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
9109 : { 1689 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9110 : { 1689 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
9111 : { 1696 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, },
9112 : { 1696 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, },
9113 : { 1696 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, },
9114 : { 1696 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, },
9115 : { 1701 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, },
9116 : { 1701 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, },
9117 : { 1708 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9118 : { 1708 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9119 : { 1713 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9120 : { 1713 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9121 : { 1720 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9122 : { 1720 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
9123 : { 1726 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9124 : { 1726 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
9125 : { 1726 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9126 : { 1726 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
9127 : { 1732 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9128 : { 1732 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
9129 : { 1732 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9130 : { 1732 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
9131 : { 1740 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
9132 : { 1740 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
9133 : { 1740 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9134 : { 1740 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
9135 : { 1746 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
9136 : { 1746 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
9137 : { 1746 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
9138 : { 1746 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
9139 : { 1746 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9140 : { 1746 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
9141 : { 1746 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9142 : { 1751 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
9143 : { 1751 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
9144 : { 1751 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9145 : { 1751 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9146 : { 1751 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
9147 : { 1758 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
9148 : { 1758 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
9149 : { 1758 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
9150 : { 1758 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
9151 : { 1758 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9152 : { 1758 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
9153 : { 1758 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
9154 : { 1763 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9155 : { 1763 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9156 : { 1763 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9157 : { 1763 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9158 : { 1763 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9159 : { 1763 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9160 : { 1763 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9161 : { 1763 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9162 : { 1763 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9163 : { 1763 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9164 : { 1763 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9165 : { 1763 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9166 : { 1768 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9167 : { 1768 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
9168 : { 1768 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
9169 : { 1768 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9170 : { 1768 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
9171 : { 1768 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
9172 : { 1774 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9173 : { 1774 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9174 : { 1774 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9175 : { 1774 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9176 : { 1774 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
9177 : { 1774 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
9178 : { 1774 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
9179 : { 1774 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
9180 : { 1774 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
9181 : { 1774 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
9182 : { 1774 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
9183 : { 1774 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
9184 : { 1774 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9185 : { 1774 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9186 : { 1774 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9187 : { 1774 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9188 : { 1774 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9189 : { 1774 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9190 : { 1774 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9191 : { 1774 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9192 : { 1774 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9193 : { 1774 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9194 : { 1774 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9195 : { 1774 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9196 : { 1774 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9197 : { 1774 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9198 : { 1774 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9199 : { 1774 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9200 : { 1774 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9201 : { 1774 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9202 : { 1774 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9203 : { 1774 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9204 : { 1779 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9205 : { 1779 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
9206 : { 1779 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
9207 : { 1779 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9208 : { 1779 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
9209 : { 1779 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
9210 : { 1785 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9211 : { 1785 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9212 : { 1785 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9213 : { 1785 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9214 : { 1785 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
9215 : { 1785 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
9216 : { 1785 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9217 : { 1785 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9218 : { 1785 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9219 : { 1785 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
9220 : { 1785 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9221 : { 1785 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9222 : { 1785 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9223 : { 1790 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9224 : { 1790 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9225 : { 1790 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9226 : { 1790 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9227 : { 1790 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9228 : { 1790 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9229 : { 1790 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9230 : { 1790 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9231 : { 1796 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9232 : { 1796 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9233 : { 1796 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9234 : { 1796 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9235 : { 1796 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9236 : { 1796 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9237 : { 1796 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9238 : { 1796 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9239 : { 1802 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9240 : { 1802 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9241 : { 1802 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9242 : { 1802 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9243 : { 1802 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9244 : { 1802 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9245 : { 1802 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9246 : { 1802 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9247 : { 1808 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9248 : { 1808 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9249 : { 1808 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9250 : { 1808 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9251 : { 1808 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9252 : { 1808 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9253 : { 1808 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9254 : { 1808 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9255 : { 1814 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9256 : { 1814 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9257 : { 1814 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9258 : { 1814 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
9259 : { 1814 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
9260 : { 1814 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
9261 : { 1814 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
9262 : { 1814 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
9263 : { 1814 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
9264 : { 1814 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
9265 : { 1814 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
9266 : { 1814 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
9267 : { 1814 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9268 : { 1814 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9269 : { 1814 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9270 : { 1814 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9271 : { 1814 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9272 : { 1814 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
9273 : { 1814 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9274 : { 1814 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9275 : { 1814 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9276 : { 1814 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9277 : { 1814 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9278 : { 1814 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
9279 : { 1814 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9280 : { 1814 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9281 : { 1814 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9282 : { 1814 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9283 : { 1814 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9284 : { 1814 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
9285 : { 1819 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
9286 : { 1819 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
9287 : { 1819 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
9288 : { 1826 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9289 : { 1826 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
9290 : { 1826 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
9291 : { 1826 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9292 : { 1826 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
9293 : { 1826 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
9294 : { 1832 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
9295 : { 1832 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
9296 : { 1832 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
9297 : { 1832 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
9298 : { 1832 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
9299 : { 1832 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
9300 : { 1832 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
9301 : { 1832 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
9302 : { 1832 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
9303 : { 1832 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
9304 : { 1832 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
9305 : { 1832 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
9306 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
9307 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
9308 : { 1838 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, },
9309 : { 1838 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, },
9310 : { 1838 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, },
9311 : { 1838 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splatNot }, },
9312 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
9313 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
9314 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
9315 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
9316 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
9317 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
9318 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
9319 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
9320 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
9321 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
9322 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9323 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9324 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9325 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9326 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
9327 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9328 : { 1838 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9329 : { 1838 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9330 : { 1843 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
9331 : { 1843 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
9332 : { 1843 /* vbic */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
9333 : { 1843 /* vbic */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
9334 : { 1843 /* vbic */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
9335 : { 1843 /* vbic */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
9336 : { 1843 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
9337 : { 1843 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
9338 : { 1843 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9339 : { 1843 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9340 : { 1843 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9341 : { 1843 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9342 : { 1843 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
9343 : { 1843 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9344 : { 1843 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9345 : { 1843 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9346 : { 1848 /* vbif */, ARM::VBIFq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
9347 : { 1848 /* vbif */, ARM::VBIFd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
9348 : { 1848 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9349 : { 1848 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9350 : { 1848 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9351 : { 1848 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9352 : { 1848 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
9353 : { 1848 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9354 : { 1848 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9355 : { 1848 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9356 : { 1853 /* vbit */, ARM::VBITq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
9357 : { 1853 /* vbit */, ARM::VBITd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
9358 : { 1853 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9359 : { 1853 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9360 : { 1853 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9361 : { 1853 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9362 : { 1853 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
9363 : { 1853 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9364 : { 1853 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9365 : { 1853 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9366 : { 1858 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
9367 : { 1858 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
9368 : { 1858 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9369 : { 1858 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9370 : { 1858 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9371 : { 1858 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9372 : { 1858 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
9373 : { 1858 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9374 : { 1858 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9375 : { 1858 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9376 : { 1863 /* vcadd */, ARM::VCADDv4f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
9377 : { 1863 /* vcadd */, ARM::VCADDv2f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
9378 : { 1863 /* vcadd */, ARM::VCADDv8f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
9379 : { 1863 /* vcadd */, ARM::VCADDv4f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
9380 : { 1869 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, },
9381 : { 1869 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9382 : { 1869 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, },
9383 : { 1869 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9384 : { 1869 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK__35_0 }, },
9385 : { 1869 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
9386 : { 1869 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK__35_0 }, },
9387 : { 1869 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
9388 : { 1869 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK__35_0 }, },
9389 : { 1869 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
9390 : { 1869 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK__35_0 }, },
9391 : { 1869 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
9392 : { 1869 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK__35_0 }, },
9393 : { 1869 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
9394 : { 1869 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK__35_0 }, },
9395 : { 1869 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
9396 : { 1869 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, },
9397 : { 1869 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9398 : { 1869 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, },
9399 : { 1869 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9400 : { 1869 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9401 : { 1869 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9402 : { 1869 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9403 : { 1869 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9404 : { 1869 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9405 : { 1869 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9406 : { 1869 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9407 : { 1869 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9408 : { 1869 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9409 : { 1869 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9410 : { 1869 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9411 : { 1869 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9412 : { 1869 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9413 : { 1869 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9414 : { 1869 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9415 : { 1869 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9416 : { 1869 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9417 : { 1869 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9418 : { 1869 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9419 : { 1869 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9420 : { 1874 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, },
9421 : { 1874 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9422 : { 1874 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, },
9423 : { 1874 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9424 : { 1874 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, },
9425 : { 1874 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9426 : { 1874 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, },
9427 : { 1874 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9428 : { 1874 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, },
9429 : { 1874 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
9430 : { 1874 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, },
9431 : { 1874 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
9432 : { 1874 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
9433 : { 1874 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
9434 : { 1874 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
9435 : { 1874 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
9436 : { 1874 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
9437 : { 1874 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
9438 : { 1874 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, },
9439 : { 1874 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9440 : { 1874 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, },
9441 : { 1874 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9442 : { 1874 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, },
9443 : { 1874 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9444 : { 1874 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, },
9445 : { 1874 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9446 : { 1874 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9447 : { 1874 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9448 : { 1874 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9449 : { 1874 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9450 : { 1874 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9451 : { 1874 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9452 : { 1874 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9453 : { 1874 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9454 : { 1874 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9455 : { 1874 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9456 : { 1874 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9457 : { 1874 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9458 : { 1874 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9459 : { 1874 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9460 : { 1874 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9461 : { 1874 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9462 : { 1874 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9463 : { 1874 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9464 : { 1874 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9465 : { 1874 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9466 : { 1874 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9467 : { 1874 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9468 : { 1874 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9469 : { 1874 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9470 : { 1874 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9471 : { 1874 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9472 : { 1879 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, },
9473 : { 1879 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9474 : { 1879 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, },
9475 : { 1879 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9476 : { 1879 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, },
9477 : { 1879 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9478 : { 1879 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, },
9479 : { 1879 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9480 : { 1879 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, },
9481 : { 1879 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
9482 : { 1879 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, },
9483 : { 1879 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
9484 : { 1879 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
9485 : { 1879 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
9486 : { 1879 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
9487 : { 1879 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
9488 : { 1879 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
9489 : { 1879 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
9490 : { 1879 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, },
9491 : { 1879 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9492 : { 1879 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, },
9493 : { 1879 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9494 : { 1879 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, },
9495 : { 1879 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9496 : { 1879 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, },
9497 : { 1879 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9498 : { 1879 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9499 : { 1879 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9500 : { 1879 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9501 : { 1879 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9502 : { 1879 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9503 : { 1879 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9504 : { 1879 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9505 : { 1879 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9506 : { 1879 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9507 : { 1879 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9508 : { 1879 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9509 : { 1879 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9510 : { 1879 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9511 : { 1879 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9512 : { 1879 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9513 : { 1879 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9514 : { 1879 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9515 : { 1879 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9516 : { 1879 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9517 : { 1879 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9518 : { 1879 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9519 : { 1879 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9520 : { 1879 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9521 : { 1879 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9522 : { 1879 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9523 : { 1879 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9524 : { 1884 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, },
9525 : { 1884 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, },
9526 : { 1884 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, },
9527 : { 1884 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, },
9528 : { 1884 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, },
9529 : { 1884 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, },
9530 : { 1884 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, },
9531 : { 1884 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, },
9532 : { 1884 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, },
9533 : { 1884 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, },
9534 : { 1884 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9535 : { 1884 /* vcle */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9536 : { 1884 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9537 : { 1884 /* vcle */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9538 : { 1884 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9539 : { 1884 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9540 : { 1884 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9541 : { 1884 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9542 : { 1884 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9543 : { 1884 /* vcle */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9544 : { 1884 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9545 : { 1884 /* vcle */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9546 : { 1884 /* vcle */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9547 : { 1884 /* vcle */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9548 : { 1884 /* vcle */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9549 : { 1884 /* vcle */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9550 : { 1884 /* vcle */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9551 : { 1884 /* vcle */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9552 : { 1884 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9553 : { 1884 /* vcle */, ARM::VCGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9554 : { 1884 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9555 : { 1884 /* vcle */, ARM::VCGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9556 : { 1884 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9557 : { 1884 /* vcle */, ARM::VCGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9558 : { 1884 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9559 : { 1884 /* vcle */, ARM::VCGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9560 : { 1889 /* vcls */, ARM::VCLSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9561 : { 1889 /* vcls */, ARM::VCLSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9562 : { 1889 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9563 : { 1889 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9564 : { 1889 /* vcls */, ARM::VCLSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
9565 : { 1889 /* vcls */, ARM::VCLSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
9566 : { 1894 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, },
9567 : { 1894 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, },
9568 : { 1894 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, },
9569 : { 1894 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, },
9570 : { 1894 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, },
9571 : { 1894 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, },
9572 : { 1894 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, },
9573 : { 1894 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, },
9574 : { 1894 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, },
9575 : { 1894 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, },
9576 : { 1894 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9577 : { 1894 /* vclt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9578 : { 1894 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9579 : { 1894 /* vclt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9580 : { 1894 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9581 : { 1894 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9582 : { 1894 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9583 : { 1894 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9584 : { 1894 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9585 : { 1894 /* vclt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9586 : { 1894 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9587 : { 1894 /* vclt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9588 : { 1894 /* vclt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9589 : { 1894 /* vclt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9590 : { 1894 /* vclt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9591 : { 1894 /* vclt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9592 : { 1894 /* vclt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9593 : { 1894 /* vclt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9594 : { 1894 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9595 : { 1894 /* vclt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9596 : { 1894 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9597 : { 1894 /* vclt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9598 : { 1894 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9599 : { 1894 /* vclt */, ARM::VCGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9600 : { 1894 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9601 : { 1894 /* vclt */, ARM::VCGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9602 : { 1899 /* vclz */, ARM::VCLZv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
9603 : { 1899 /* vclz */, ARM::VCLZv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
9604 : { 1899 /* vclz */, ARM::VCLZv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
9605 : { 1899 /* vclz */, ARM::VCLZv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
9606 : { 1899 /* vclz */, ARM::VCLZv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
9607 : { 1899 /* vclz */, ARM::VCLZv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
9608 : { 1904 /* vcmla */, ARM::VCMLAv4f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
9609 : { 1904 /* vcmla */, ARM::VCMLAv2f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
9610 : { 1904 /* vcmla */, ARM::VCMLAv8f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
9611 : { 1904 /* vcmla */, ARM::VCMLAv4f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
9612 : { 1904 /* vcmla */, ARM::VCMLAv4f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
9613 : { 1904 /* vcmla */, ARM::VCMLAv2f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
9614 : { 1904 /* vcmla */, ARM::VCMLAv8f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
9615 : { 1904 /* vcmla */, ARM::VCMLAv4f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
9616 : { 1910 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__35_0 }, },
9617 : { 1910 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9618 : { 1910 /* vcmp */, ARM::VCMPZD, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__35_0 }, },
9619 : { 1910 /* vcmp */, ARM::VCMPD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
9620 : { 1910 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__35_0 }, },
9621 : { 1910 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9622 : { 1915 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__35_0 }, },
9623 : { 1915 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9624 : { 1915 /* vcmpe */, ARM::VCMPEZD, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__35_0 }, },
9625 : { 1915 /* vcmpe */, ARM::VCMPED, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
9626 : { 1915 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__35_0 }, },
9627 : { 1915 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9628 : { 1921 /* vcnt */, ARM::VCNTq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
9629 : { 1921 /* vcnt */, ARM::VCNTd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
9630 : { 1926 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9631 : { 1926 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9632 : { 1926 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9633 : { 1926 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9634 : { 1926 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9635 : { 1926 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9636 : { 1926 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9637 : { 1926 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9638 : { 1926 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9639 : { 1926 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9640 : { 1926 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9641 : { 1926 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9642 : { 1926 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9643 : { 1926 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9644 : { 1926 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9645 : { 1926 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9646 : { 1926 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
9647 : { 1926 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
9648 : { 1926 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
9649 : { 1926 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
9650 : { 1926 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9651 : { 1926 /* vcvt */, ARM::VCVTh2f, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_QPR, MCK_DPR }, },
9652 : { 1926 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, },
9653 : { 1926 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, },
9654 : { 1926 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, },
9655 : { 1926 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9656 : { 1926 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9657 : { 1926 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
9658 : { 1926 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
9659 : { 1926 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
9660 : { 1926 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
9661 : { 1926 /* vcvt */, ARM::VCVTf2h, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, },
9662 : { 1926 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9663 : { 1926 /* vcvt */, ARM::VTOSHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
9664 : { 1926 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9665 : { 1926 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
9666 : { 1926 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9667 : { 1926 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
9668 : { 1926 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9669 : { 1926 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9670 : { 1926 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
9671 : { 1926 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9672 : { 1926 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
9673 : { 1926 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9674 : { 1926 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
9675 : { 1926 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9676 : { 1926 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9677 : { 1926 /* vcvt */, ARM::VTOUHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
9678 : { 1926 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9679 : { 1926 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
9680 : { 1926 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9681 : { 1926 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
9682 : { 1926 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9683 : { 1926 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9684 : { 1926 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
9685 : { 1926 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9686 : { 1926 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
9687 : { 1926 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9688 : { 1926 /* vcvt */, ARM::VTOULD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
9689 : { 1926 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9690 : { 1926 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9691 : { 1926 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9692 : { 1926 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
9693 : { 1926 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9694 : { 1926 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
9695 : { 1926 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9696 : { 1926 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9697 : { 1926 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9698 : { 1926 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
9699 : { 1926 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9700 : { 1926 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
9701 : { 1926 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9702 : { 1926 /* vcvt */, ARM::VSHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
9703 : { 1926 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
9704 : { 1926 /* vcvt */, ARM::VUHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
9705 : { 1926 /* vcvt */, ARM::VULTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
9706 : { 1926 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9707 : { 1926 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
9708 : { 1926 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9709 : { 1926 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
9710 : { 1926 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9711 : { 1926 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9712 : { 1926 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK__35_0 }, },
9713 : { 1926 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
9714 : { 1926 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK__35_0 }, },
9715 : { 1926 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
9716 : { 1926 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
9717 : { 1926 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
9718 : { 1931 /* vcvta */, ARM::VCVTANSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9719 : { 1931 /* vcvta */, ARM::VCVTANSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9720 : { 1931 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9721 : { 1931 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9722 : { 1931 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9723 : { 1931 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9724 : { 1931 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9725 : { 1931 /* vcvta */, ARM::VCVTANUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9726 : { 1931 /* vcvta */, ARM::VCVTANUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9727 : { 1931 /* vcvta */, ARM::VCVTANUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9728 : { 1931 /* vcvta */, ARM::VCVTANUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9729 : { 1931 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9730 : { 1931 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9731 : { 1931 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9732 : { 1937 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9733 : { 1937 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
9734 : { 1937 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9735 : { 1937 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9736 : { 1943 /* vcvtm */, ARM::VCVTMNSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9737 : { 1943 /* vcvtm */, ARM::VCVTMNSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9738 : { 1943 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9739 : { 1943 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9740 : { 1943 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9741 : { 1943 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9742 : { 1943 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9743 : { 1943 /* vcvtm */, ARM::VCVTMNUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9744 : { 1943 /* vcvtm */, ARM::VCVTMNUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9745 : { 1943 /* vcvtm */, ARM::VCVTMNUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9746 : { 1943 /* vcvtm */, ARM::VCVTMNUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9747 : { 1943 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9748 : { 1943 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9749 : { 1943 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9750 : { 1949 /* vcvtn */, ARM::VCVTNNSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9751 : { 1949 /* vcvtn */, ARM::VCVTNNSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9752 : { 1949 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9753 : { 1949 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9754 : { 1949 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9755 : { 1949 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9756 : { 1949 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9757 : { 1949 /* vcvtn */, ARM::VCVTNNUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9758 : { 1949 /* vcvtn */, ARM::VCVTNNUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9759 : { 1949 /* vcvtn */, ARM::VCVTNNUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9760 : { 1949 /* vcvtn */, ARM::VCVTNNUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9761 : { 1949 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9762 : { 1949 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9763 : { 1949 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9764 : { 1955 /* vcvtp */, ARM::VCVTPNSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9765 : { 1955 /* vcvtp */, ARM::VCVTPNSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9766 : { 1955 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9767 : { 1955 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9768 : { 1955 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9769 : { 1955 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9770 : { 1955 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9771 : { 1955 /* vcvtp */, ARM::VCVTPNUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
9772 : { 1955 /* vcvtp */, ARM::VCVTPNUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
9773 : { 1955 /* vcvtp */, ARM::VCVTPNUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
9774 : { 1955 /* vcvtp */, ARM::VCVTPNUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
9775 : { 1955 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9776 : { 1955 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9777 : { 1955 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9778 : { 1961 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9779 : { 1961 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9780 : { 1961 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9781 : { 1961 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9782 : { 1961 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9783 : { 1961 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9784 : { 1967 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9785 : { 1967 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
9786 : { 1967 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9787 : { 1967 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9788 : { 1973 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
9789 : { 1973 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
9790 : { 1973 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9791 : { 1973 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
9792 : { 1973 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9793 : { 1973 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
9794 : { 1978 /* vdup */, ARM::VDUP16q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_GPR }, },
9795 : { 1978 /* vdup */, ARM::VDUP16d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_GPR }, },
9796 : { 1978 /* vdup */, ARM::VDUP32q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_GPR }, },
9797 : { 1978 /* vdup */, ARM::VDUP32d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_GPR }, },
9798 : { 1978 /* vdup */, ARM::VDUP8q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_GPR }, },
9799 : { 1978 /* vdup */, ARM::VDUP8d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_GPR }, },
9800 : { 1978 /* vdup */, ARM::VDUPLN16q, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_DPR, MCK_VectorIndex16 }, },
9801 : { 1978 /* vdup */, ARM::VDUPLN16d, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, },
9802 : { 1978 /* vdup */, ARM::VDUPLN32q, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_DPR, MCK_VectorIndex32 }, },
9803 : { 1978 /* vdup */, ARM::VDUPLN32d, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_VectorIndex32 }, },
9804 : { 1978 /* vdup */, ARM::VDUPLN8q, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_DPR, MCK_VectorIndex8 }, },
9805 : { 1978 /* vdup */, ARM::VDUPLN8d, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_VectorIndex8 }, },
9806 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
9807 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
9808 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
9809 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
9810 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
9811 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
9812 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
9813 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
9814 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
9815 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
9816 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
9817 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
9818 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9819 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9820 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9821 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9822 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
9823 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9824 : { 1983 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9825 : { 1983 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9826 : { 1988 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9827 : { 1988 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
9828 : { 1988 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9829 : { 1988 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
9830 : { 1988 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9831 : { 1988 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9832 : { 1988 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
9833 : { 1988 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9834 : { 1988 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
9835 : { 1988 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9836 : { 1988 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
9837 : { 1988 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9838 : { 1988 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
9839 : { 1988 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
9840 : { 1993 /* vfma */, ARM::VFMAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9841 : { 1993 /* vfma */, ARM::VFMAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9842 : { 1993 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
9843 : { 1993 /* vfma */, ARM::VFMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9844 : { 1993 /* vfma */, ARM::VFMAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9845 : { 1993 /* vfma */, ARM::VFMAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9846 : { 1993 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
9847 : { 1998 /* vfmal */, ARM::VFMALQ, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9848 : { 1998 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
9849 : { 1998 /* vfmal */, ARM::VFMALQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, },
9850 : { 1998 /* vfmal */, ARM::VFMALDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR, MCK_VectorIndex32 }, },
9851 : { 2004 /* vfms */, ARM::VFMSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9852 : { 2004 /* vfms */, ARM::VFMSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9853 : { 2004 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
9854 : { 2004 /* vfms */, ARM::VFMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9855 : { 2004 /* vfms */, ARM::VFMShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9856 : { 2004 /* vfms */, ARM::VFMShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9857 : { 2004 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
9858 : { 2009 /* vfmsl */, ARM::VFMSLQ, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
9859 : { 2009 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
9860 : { 2009 /* vfmsl */, ARM::VFMSLQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, },
9861 : { 2009 /* vfmsl */, ARM::VFMSLDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasNEON|Feature_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR, MCK_VectorIndex32 }, },
9862 : { 2015 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
9863 : { 2015 /* vfnma */, ARM::VFNMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9864 : { 2015 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
9865 : { 2021 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
9866 : { 2021 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
9867 : { 2021 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
9868 : { 2027 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9869 : { 2027 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9870 : { 2027 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9871 : { 2027 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9872 : { 2027 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
9873 : { 2027 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
9874 : { 2027 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
9875 : { 2027 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
9876 : { 2027 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
9877 : { 2027 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
9878 : { 2027 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
9879 : { 2027 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
9880 : { 2027 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9881 : { 2027 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9882 : { 2027 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9883 : { 2027 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9884 : { 2027 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9885 : { 2027 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9886 : { 2027 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9887 : { 2027 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9888 : { 2027 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9889 : { 2027 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9890 : { 2027 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9891 : { 2027 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9892 : { 2033 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
9893 : { 2033 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
9894 : { 2033 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
9895 : { 2033 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
9896 : { 2033 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
9897 : { 2033 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
9898 : { 2033 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
9899 : { 2033 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
9900 : { 2033 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
9901 : { 2033 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
9902 : { 2033 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
9903 : { 2033 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
9904 : { 2033 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9905 : { 2033 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9906 : { 2033 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9907 : { 2033 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9908 : { 2033 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9909 : { 2033 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9910 : { 2033 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
9911 : { 2033 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
9912 : { 2033 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
9913 : { 2033 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
9914 : { 2033 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
9915 : { 2033 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
9916 : { 2039 /* vins */, ARM::VINSH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
9917 : { 2044 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
9918 : { 2050 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
9919 : { 2050 /* vld1 */, ARM::VLD1q16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
9920 : { 2050 /* vld1 */, ARM::VLD1d16Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
9921 : { 2050 /* vld1 */, ARM::VLD1DUPd16, Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16 }, },
9922 : { 2050 /* vld1 */, ARM::VLD1d16, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
9923 : { 2050 /* vld1 */, ARM::VLD1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
9924 : { 2050 /* vld1 */, ARM::VLD1d16T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
9925 : { 2050 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
9926 : { 2050 /* vld1 */, ARM::VLD1q32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
9927 : { 2050 /* vld1 */, ARM::VLD1d32Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
9928 : { 2050 /* vld1 */, ARM::VLD1DUPd32, Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32 }, },
9929 : { 2050 /* vld1 */, ARM::VLD1d32, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
9930 : { 2050 /* vld1 */, ARM::VLD1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
9931 : { 2050 /* vld1 */, ARM::VLD1d32T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
9932 : { 2050 /* vld1 */, ARM::VLD1q64, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
9933 : { 2050 /* vld1 */, ARM::VLD1d64Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
9934 : { 2050 /* vld1 */, ARM::VLD1d64, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
9935 : { 2050 /* vld1 */, ARM::VLD1d64T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
9936 : { 2050 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, },
9937 : { 2050 /* vld1 */, ARM::VLD1q8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
9938 : { 2050 /* vld1 */, ARM::VLD1d8Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
9939 : { 2050 /* vld1 */, ARM::VLD1DUPd8, Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone }, },
9940 : { 2050 /* vld1 */, ARM::VLD1d8, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
9941 : { 2050 /* vld1 */, ARM::VLD1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
9942 : { 2050 /* vld1 */, ARM::VLD1d8T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
9943 : { 2050 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
9944 : { 2050 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
9945 : { 2050 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
9946 : { 2050 /* vld1 */, ARM::VLD1q16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
9947 : { 2050 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
9948 : { 2050 /* vld1 */, ARM::VLD1d16Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
9949 : { 2050 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
9950 : { 2050 /* vld1 */, ARM::VLD1DUPd16wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
9951 : { 2050 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9952 : { 2050 /* vld1 */, ARM::VLD1d16wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
9953 : { 2050 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
9954 : { 2050 /* vld1 */, ARM::VLD1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
9955 : { 2050 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9956 : { 2050 /* vld1 */, ARM::VLD1d16Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
9957 : { 2050 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
9958 : { 2050 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
9959 : { 2050 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
9960 : { 2050 /* vld1 */, ARM::VLD1q32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
9961 : { 2050 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
9962 : { 2050 /* vld1 */, ARM::VLD1d32Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
9963 : { 2050 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
9964 : { 2050 /* vld1 */, ARM::VLD1DUPd32wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
9965 : { 2050 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9966 : { 2050 /* vld1 */, ARM::VLD1d32wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
9967 : { 2050 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
9968 : { 2050 /* vld1 */, ARM::VLD1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
9969 : { 2050 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9970 : { 2050 /* vld1 */, ARM::VLD1d32Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
9971 : { 2050 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
9972 : { 2050 /* vld1 */, ARM::VLD1q64wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
9973 : { 2050 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
9974 : { 2050 /* vld1 */, ARM::VLD1d64Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
9975 : { 2050 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9976 : { 2050 /* vld1 */, ARM::VLD1d64wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
9977 : { 2050 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9978 : { 2050 /* vld1 */, ARM::VLD1d64Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
9979 : { 2050 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
9980 : { 2050 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
9981 : { 2050 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
9982 : { 2050 /* vld1 */, ARM::VLD1q8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
9983 : { 2050 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
9984 : { 2050 /* vld1 */, ARM::VLD1d8Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
9985 : { 2050 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
9986 : { 2050 /* vld1 */, ARM::VLD1DUPd8wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
9987 : { 2050 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9988 : { 2050 /* vld1 */, ARM::VLD1d8wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
9989 : { 2050 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
9990 : { 2050 /* vld1 */, ARM::VLD1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
9991 : { 2050 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
9992 : { 2050 /* vld1 */, ARM::VLD1d8Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
9993 : { 2050 /* vld1 */, ARM::VLD1LNd16, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
9994 : { 2050 /* vld1 */, ARM::VLD1LNd8, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
9995 : { 2050 /* vld1 */, ARM::VLD1LNd16_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
9996 : { 2050 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
9997 : { 2050 /* vld1 */, ARM::VLD1LNd32_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
9998 : { 2050 /* vld1 */, ARM::VLD1LNd8_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
9999 : { 2055 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
10000 : { 2055 /* vld2 */, ARM::VLD2d16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
10001 : { 2055 /* vld2 */, ARM::VLD2DUPd16x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32 }, },
10002 : { 2055 /* vld2 */, ARM::VLD2b16, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
10003 : { 2055 /* vld2 */, ARM::VLD2q16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
10004 : { 2055 /* vld2 */, ARM::VLD2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
10005 : { 2055 /* vld2 */, ARM::VLD2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
10006 : { 2055 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, },
10007 : { 2055 /* vld2 */, ARM::VLD2d32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
10008 : { 2055 /* vld2 */, ARM::VLD2DUPd32x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64 }, },
10009 : { 2055 /* vld2 */, ARM::VLD2b32, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
10010 : { 2055 /* vld2 */, ARM::VLD2q32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
10011 : { 2055 /* vld2 */, ARM::VLD2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
10012 : { 2055 /* vld2 */, ARM::VLD2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
10013 : { 2055 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
10014 : { 2055 /* vld2 */, ARM::VLD2d8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
10015 : { 2055 /* vld2 */, ARM::VLD2DUPd8x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16 }, },
10016 : { 2055 /* vld2 */, ARM::VLD2b8, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
10017 : { 2055 /* vld2 */, ARM::VLD2q8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
10018 : { 2055 /* vld2 */, ARM::VLD2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
10019 : { 2055 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
10020 : { 2055 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
10021 : { 2055 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10022 : { 2055 /* vld2 */, ARM::VLD2d16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
10023 : { 2055 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
10024 : { 2055 /* vld2 */, ARM::VLD2DUPd16x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
10025 : { 2055 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10026 : { 2055 /* vld2 */, ARM::VLD2b16wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
10027 : { 2055 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10028 : { 2055 /* vld2 */, ARM::VLD2q16wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10029 : { 2055 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
10030 : { 2055 /* vld2 */, ARM::VLD2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
10031 : { 2055 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
10032 : { 2055 /* vld2 */, ARM::VLD2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
10033 : { 2055 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
10034 : { 2055 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
10035 : { 2055 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10036 : { 2055 /* vld2 */, ARM::VLD2d32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
10037 : { 2055 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
10038 : { 2055 /* vld2 */, ARM::VLD2DUPd32x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
10039 : { 2055 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10040 : { 2055 /* vld2 */, ARM::VLD2b32wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
10041 : { 2055 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10042 : { 2055 /* vld2 */, ARM::VLD2q32wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10043 : { 2055 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10044 : { 2055 /* vld2 */, ARM::VLD2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
10045 : { 2055 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10046 : { 2055 /* vld2 */, ARM::VLD2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
10047 : { 2055 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
10048 : { 2055 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
10049 : { 2055 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10050 : { 2055 /* vld2 */, ARM::VLD2d8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
10051 : { 2055 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
10052 : { 2055 /* vld2 */, ARM::VLD2DUPd8x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
10053 : { 2055 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10054 : { 2055 /* vld2 */, ARM::VLD2b8wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
10055 : { 2055 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10056 : { 2055 /* vld2 */, ARM::VLD2q8wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10057 : { 2055 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
10058 : { 2055 /* vld2 */, ARM::VLD2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
10059 : { 2060 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
10060 : { 2060 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
10061 : { 2060 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
10062 : { 2060 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
10063 : { 2060 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
10064 : { 2060 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
10065 : { 2060 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
10066 : { 2060 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
10067 : { 2060 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
10068 : { 2060 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
10069 : { 2060 /* vld3 */, ARM::VLD3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
10070 : { 2060 /* vld3 */, ARM::VLD3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
10071 : { 2060 /* vld3 */, ARM::VLD3DUPdAsm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
10072 : { 2060 /* vld3 */, ARM::VLD3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
10073 : { 2060 /* vld3 */, ARM::VLD3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
10074 : { 2060 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
10075 : { 2060 /* vld3 */, ARM::VLD3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
10076 : { 2060 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
10077 : { 2060 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
10078 : { 2060 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10079 : { 2060 /* vld3 */, ARM::VLD3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
10080 : { 2060 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
10081 : { 2060 /* vld3 */, ARM::VLD3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
10082 : { 2060 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
10083 : { 2060 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
10084 : { 2060 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10085 : { 2060 /* vld3 */, ARM::VLD3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
10086 : { 2060 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
10087 : { 2060 /* vld3 */, ARM::VLD3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
10088 : { 2060 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
10089 : { 2060 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
10090 : { 2060 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10091 : { 2060 /* vld3 */, ARM::VLD3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
10092 : { 2060 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
10093 : { 2060 /* vld3 */, ARM::VLD3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
10094 : { 2060 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
10095 : { 2060 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
10096 : { 2060 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10097 : { 2060 /* vld3 */, ARM::VLD3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
10098 : { 2060 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
10099 : { 2060 /* vld3 */, ARM::VLD3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
10100 : { 2060 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
10101 : { 2060 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
10102 : { 2060 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10103 : { 2060 /* vld3 */, ARM::VLD3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
10104 : { 2060 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
10105 : { 2060 /* vld3 */, ARM::VLD3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
10106 : { 2060 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
10107 : { 2060 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
10108 : { 2060 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10109 : { 2060 /* vld3 */, ARM::VLD3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
10110 : { 2060 /* vld3 */, ARM::VLD3d16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10111 : { 2060 /* vld3 */, ARM::VLD3q16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10112 : { 2060 /* vld3 */, ARM::VLD3d32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10113 : { 2060 /* vld3 */, ARM::VLD3q32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10114 : { 2060 /* vld3 */, ARM::VLD3d8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10115 : { 2060 /* vld3 */, ARM::VLD3q8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10116 : { 2060 /* vld3 */, ARM::VLD3d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10117 : { 2060 /* vld3 */, ARM::VLD3q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10118 : { 2060 /* vld3 */, ARM::VLD3d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10119 : { 2060 /* vld3 */, ARM::VLD3q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10120 : { 2060 /* vld3 */, ARM::VLD3d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10121 : { 2060 /* vld3 */, ARM::VLD3q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10122 : { 2060 /* vld3 */, ARM::VLD3DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10123 : { 2060 /* vld3 */, ARM::VLD3DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10124 : { 2060 /* vld3 */, ARM::VLD3DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10125 : { 2060 /* vld3 */, ARM::VLD3DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10126 : { 2060 /* vld3 */, ARM::VLD3DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10127 : { 2060 /* vld3 */, ARM::VLD3DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10128 : { 2060 /* vld3 */, ARM::VLD3DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
10129 : { 2060 /* vld3 */, ARM::VLD3DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
10130 : { 2060 /* vld3 */, ARM::VLD3DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
10131 : { 2060 /* vld3 */, ARM::VLD3DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
10132 : { 2060 /* vld3 */, ARM::VLD3DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
10133 : { 2060 /* vld3 */, ARM::VLD3DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
10134 : { 2065 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, },
10135 : { 2065 /* vld4 */, ARM::VLD4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
10136 : { 2065 /* vld4 */, ARM::VLD4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
10137 : { 2065 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, },
10138 : { 2065 /* vld4 */, ARM::VLD4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
10139 : { 2065 /* vld4 */, ARM::VLD4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
10140 : { 2065 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, },
10141 : { 2065 /* vld4 */, ARM::VLD4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
10142 : { 2065 /* vld4 */, ARM::VLD4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
10143 : { 2065 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, },
10144 : { 2065 /* vld4 */, ARM::VLD4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
10145 : { 2065 /* vld4 */, ARM::VLD4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
10146 : { 2065 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, },
10147 : { 2065 /* vld4 */, ARM::VLD4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
10148 : { 2065 /* vld4 */, ARM::VLD4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
10149 : { 2065 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, },
10150 : { 2065 /* vld4 */, ARM::VLD4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
10151 : { 2065 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
10152 : { 2065 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
10153 : { 2065 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10154 : { 2065 /* vld4 */, ARM::VLD4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10155 : { 2065 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10156 : { 2065 /* vld4 */, ARM::VLD4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
10157 : { 2065 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
10158 : { 2065 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
10159 : { 2065 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10160 : { 2065 /* vld4 */, ARM::VLD4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10161 : { 2065 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
10162 : { 2065 /* vld4 */, ARM::VLD4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
10163 : { 2065 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
10164 : { 2065 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
10165 : { 2065 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10166 : { 2065 /* vld4 */, ARM::VLD4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10167 : { 2065 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10168 : { 2065 /* vld4 */, ARM::VLD4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
10169 : { 2065 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
10170 : { 2065 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
10171 : { 2065 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10172 : { 2065 /* vld4 */, ARM::VLD4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10173 : { 2065 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
10174 : { 2065 /* vld4 */, ARM::VLD4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
10175 : { 2065 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
10176 : { 2065 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
10177 : { 2065 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10178 : { 2065 /* vld4 */, ARM::VLD4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10179 : { 2065 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
10180 : { 2065 /* vld4 */, ARM::VLD4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
10181 : { 2065 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
10182 : { 2065 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
10183 : { 2065 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
10184 : { 2065 /* vld4 */, ARM::VLD4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
10185 : { 2065 /* vld4 */, ARM::VLD4d16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10186 : { 2065 /* vld4 */, ARM::VLD4q16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10187 : { 2065 /* vld4 */, ARM::VLD4d32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10188 : { 2065 /* vld4 */, ARM::VLD4q32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10189 : { 2065 /* vld4 */, ARM::VLD4d8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10190 : { 2065 /* vld4 */, ARM::VLD4q8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
10191 : { 2065 /* vld4 */, ARM::VLD4d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10192 : { 2065 /* vld4 */, ARM::VLD4q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10193 : { 2065 /* vld4 */, ARM::VLD4d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10194 : { 2065 /* vld4 */, ARM::VLD4q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10195 : { 2065 /* vld4 */, ARM::VLD4d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10196 : { 2065 /* vld4 */, ARM::VLD4q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10197 : { 2065 /* vld4 */, ARM::VLD4DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10198 : { 2065 /* vld4 */, ARM::VLD4DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10199 : { 2065 /* vld4 */, ARM::VLD4DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10200 : { 2065 /* vld4 */, ARM::VLD4DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10201 : { 2065 /* vld4 */, ARM::VLD4DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10202 : { 2065 /* vld4 */, ARM::VLD4DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
10203 : { 2065 /* vld4 */, ARM::VLD4DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10204 : { 2065 /* vld4 */, ARM::VLD4DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10205 : { 2065 /* vld4 */, ARM::VLD4DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10206 : { 2065 /* vld4 */, ARM::VLD4DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10207 : { 2065 /* vld4 */, ARM::VLD4DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10208 : { 2065 /* vld4 */, ARM::VLD4DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
10209 : { 2070 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10210 : { 2070 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
10211 : { 2077 /* vldmia */, ARM::VLDMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
10212 : { 2077 /* vldmia */, ARM::VLDMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
10213 : { 2077 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10214 : { 2077 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
10215 : { 2084 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
10216 : { 2084 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
10217 : { 2084 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
10218 : { 2084 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
10219 : { 2084 /* vldr */, ARM::VLDRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
10220 : { 2089 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0, Feature_HasV8MMainline|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
10221 : { 2095 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0, Feature_HasV8MMainline|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
10222 : { 2101 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10223 : { 2101 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10224 : { 2101 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10225 : { 2101 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10226 : { 2101 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10227 : { 2101 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10228 : { 2101 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10229 : { 2101 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10230 : { 2101 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10231 : { 2101 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10232 : { 2101 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10233 : { 2101 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10234 : { 2101 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
10235 : { 2101 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10236 : { 2101 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
10237 : { 2101 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10238 : { 2101 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10239 : { 2101 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10240 : { 2101 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10241 : { 2101 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10242 : { 2101 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10243 : { 2101 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10244 : { 2101 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10245 : { 2101 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10246 : { 2101 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10247 : { 2101 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10248 : { 2101 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10249 : { 2101 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10250 : { 2101 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10251 : { 2101 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10252 : { 2101 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10253 : { 2101 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10254 : { 2106 /* vmaxnm */, ARM::VMAXNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10255 : { 2106 /* vmaxnm */, ARM::VMAXNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10256 : { 2106 /* vmaxnm */, ARM::VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10257 : { 2106 /* vmaxnm */, ARM::VMAXNMD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10258 : { 2106 /* vmaxnm */, ARM::VMAXNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10259 : { 2106 /* vmaxnm */, ARM::VMAXNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10260 : { 2106 /* vmaxnm */, ARM::VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10261 : { 2113 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10262 : { 2113 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10263 : { 2113 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10264 : { 2113 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10265 : { 2113 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10266 : { 2113 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10267 : { 2113 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10268 : { 2113 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10269 : { 2113 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10270 : { 2113 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10271 : { 2113 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10272 : { 2113 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10273 : { 2113 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
10274 : { 2113 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10275 : { 2113 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
10276 : { 2113 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10277 : { 2113 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10278 : { 2113 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10279 : { 2113 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10280 : { 2113 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10281 : { 2113 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10282 : { 2113 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10283 : { 2113 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10284 : { 2113 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10285 : { 2113 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10286 : { 2113 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10287 : { 2113 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10288 : { 2113 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10289 : { 2113 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10290 : { 2113 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10291 : { 2113 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10292 : { 2113 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10293 : { 2118 /* vminnm */, ARM::VMINNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10294 : { 2118 /* vminnm */, ARM::VMINNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10295 : { 2118 /* vminnm */, ARM::VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10296 : { 2118 /* vminnm */, ARM::VMINNMD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10297 : { 2118 /* vminnm */, ARM::VMINNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10298 : { 2118 /* vminnm */, ARM::VMINNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10299 : { 2118 /* vminnm */, ARM::VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10300 : { 2125 /* vmla */, ARM::VMLAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10301 : { 2125 /* vmla */, ARM::VMLAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10302 : { 2125 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10303 : { 2125 /* vmla */, ARM::VMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10304 : { 2125 /* vmla */, ARM::VMLAv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10305 : { 2125 /* vmla */, ARM::VMLAv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10306 : { 2125 /* vmla */, ARM::VMLAv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10307 : { 2125 /* vmla */, ARM::VMLAv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10308 : { 2125 /* vmla */, ARM::VMLAv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10309 : { 2125 /* vmla */, ARM::VMLAv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10310 : { 2125 /* vmla */, ARM::VMLAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10311 : { 2125 /* vmla */, ARM::VMLAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10312 : { 2125 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10313 : { 2125 /* vmla */, ARM::VMLAslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10314 : { 2125 /* vmla */, ARM::VMLAslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10315 : { 2125 /* vmla */, ARM::VMLAslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10316 : { 2125 /* vmla */, ARM::VMLAslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10317 : { 2125 /* vmla */, ARM::VMLAslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10318 : { 2125 /* vmla */, ARM::VMLAslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10319 : { 2125 /* vmla */, ARM::VMLAslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10320 : { 2125 /* vmla */, ARM::VMLAslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10321 : { 2130 /* vmlal */, ARM::VMLALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10322 : { 2130 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10323 : { 2130 /* vmlal */, ARM::VMLALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
10324 : { 2130 /* vmlal */, ARM::VMLALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10325 : { 2130 /* vmlal */, ARM::VMLALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10326 : { 2130 /* vmlal */, ARM::VMLALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
10327 : { 2130 /* vmlal */, ARM::VMLALslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10328 : { 2130 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10329 : { 2130 /* vmlal */, ARM::VMLALsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10330 : { 2130 /* vmlal */, ARM::VMLALsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10331 : { 2136 /* vmls */, ARM::VMLSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10332 : { 2136 /* vmls */, ARM::VMLSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10333 : { 2136 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10334 : { 2136 /* vmls */, ARM::VMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10335 : { 2136 /* vmls */, ARM::VMLSv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10336 : { 2136 /* vmls */, ARM::VMLSv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10337 : { 2136 /* vmls */, ARM::VMLSv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10338 : { 2136 /* vmls */, ARM::VMLSv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10339 : { 2136 /* vmls */, ARM::VMLSv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10340 : { 2136 /* vmls */, ARM::VMLSv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10341 : { 2136 /* vmls */, ARM::VMLShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10342 : { 2136 /* vmls */, ARM::VMLShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10343 : { 2136 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10344 : { 2136 /* vmls */, ARM::VMLSslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10345 : { 2136 /* vmls */, ARM::VMLSslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10346 : { 2136 /* vmls */, ARM::VMLSslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10347 : { 2136 /* vmls */, ARM::VMLSslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10348 : { 2136 /* vmls */, ARM::VMLSslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10349 : { 2136 /* vmls */, ARM::VMLSslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10350 : { 2136 /* vmls */, ARM::VMLSslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10351 : { 2136 /* vmls */, ARM::VMLSslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10352 : { 2141 /* vmlsl */, ARM::VMLSLsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10353 : { 2141 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10354 : { 2141 /* vmlsl */, ARM::VMLSLsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
10355 : { 2141 /* vmlsl */, ARM::VMLSLuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10356 : { 2141 /* vmlsl */, ARM::VMLSLuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10357 : { 2141 /* vmlsl */, ARM::VMLSLuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
10358 : { 2141 /* vmlsl */, ARM::VMLSLslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10359 : { 2141 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10360 : { 2141 /* vmlsl */, ARM::VMLSLsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10361 : { 2141 /* vmlsl */, ARM::VMLSLsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10362 : { 2147 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_HPR }, },
10363 : { 2147 /* vmov */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
10364 : { 2147 /* vmov */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
10365 : { 2147 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_GPR }, },
10366 : { 2147 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
10367 : { 2147 /* vmov */, ARM::VMOVv4f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_FPImm }, },
10368 : { 2147 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_NEONi32vmov }, },
10369 : { 2147 /* vmov */, ARM::VMOVv2f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_FPImm }, },
10370 : { 2147 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_NEONi32vmov }, },
10371 : { 2147 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
10372 : { 2147 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, },
10373 : { 2147 /* vmov */, ARM::VMOVD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
10374 : { 2147 /* vmov */, ARM::FCONSTD, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasVFP3|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_FPImm }, },
10375 : { 2147 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16vmovi8Replicate }, },
10376 : { 2147 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
10377 : { 2147 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16vmovi8Replicate }, },
10378 : { 2147 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
10379 : { 2147 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi8Replicate }, },
10380 : { 2147 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
10381 : { 2147 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
10382 : { 2147 /* vmov */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
10383 : { 2147 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi8Replicate }, },
10384 : { 2147 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
10385 : { 2147 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
10386 : { 2147 /* vmov */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
10387 : { 2147 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi8Replicate }, },
10388 : { 2147 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
10389 : { 2147 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
10390 : { 2147 /* vmov */, ARM::VMOVv2i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64splat }, },
10391 : { 2147 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi8Replicate }, },
10392 : { 2147 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
10393 : { 2147 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
10394 : { 2147 /* vmov */, ARM::VMOVv1i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64splat }, },
10395 : { 2147 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_NEONi8splat }, },
10396 : { 2147 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_NEONi8splat }, },
10397 : { 2147 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, },
10398 : { 2147 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
10399 : { 2147 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
10400 : { 2147 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, },
10401 : { 2147 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, },
10402 : { 2147 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
10403 : { 2147 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
10404 : { 2147 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, },
10405 : { 2147 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
10406 : { 2147 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
10407 : { 2147 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, },
10408 : { 2147 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10409 : { 2147 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
10410 : { 2147 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, },
10411 : { 2147 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_GPR, MCK_HPR }, },
10412 : { 2147 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_GPR }, },
10413 : { 2147 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, },
10414 : { 2147 /* vmov */, ARM::VMOVRRD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_DPR }, },
10415 : { 2147 /* vmov */, ARM::VMOVDRR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR, MCK_GPR }, },
10416 : { 2147 /* vmov */, ARM::VGETLNs16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
10417 : { 2147 /* vmov */, ARM::VGETLNs8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
10418 : { 2147 /* vmov */, ARM::VGETLNu16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
10419 : { 2147 /* vmov */, ARM::VGETLNu8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
10420 : { 2147 /* vmov */, ARM::VMOVRRD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_GPR, MCK_GPR, MCK_DPR }, },
10421 : { 2147 /* vmov */, ARM::VMOVDRR, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_GPR, MCK_GPR }, },
10422 : { 2147 /* vmov */, ARM::VSETLNi16, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_VectorIndex16, MCK_GPR }, },
10423 : { 2147 /* vmov */, ARM::VGETLNi32, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, },
10424 : { 2147 /* vmov */, ARM::VSETLNi32, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, },
10425 : { 2147 /* vmov */, ARM::VSETLNi8, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VectorIndex8, MCK_GPR }, },
10426 : { 2147 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, },
10427 : { 2147 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, },
10428 : { 2152 /* vmovl */, ARM::VMOVLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
10429 : { 2152 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
10430 : { 2152 /* vmovl */, ARM::VMOVLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
10431 : { 2152 /* vmovl */, ARM::VMOVLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
10432 : { 2152 /* vmovl */, ARM::VMOVLuv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
10433 : { 2152 /* vmovl */, ARM::VMOVLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
10434 : { 2158 /* vmovn */, ARM::VMOVNv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR }, },
10435 : { 2158 /* vmovn */, ARM::VMOVNv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR }, },
10436 : { 2158 /* vmovn */, ARM::VMOVNv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR }, },
10437 : { 2164 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
10438 : { 2170 /* vmrs */, ARM::FMSTAT, Convert__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_APSR_NZCV, MCK_FPSCR }, },
10439 : { 2170 /* vmrs */, ARM::VMRS_FPEXC, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPEXC }, },
10440 : { 2170 /* vmrs */, ARM::VMRS_FPINST, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST }, },
10441 : { 2170 /* vmrs */, ARM::VMRS_FPINST2, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST2 }, },
10442 : { 2170 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSCR }, },
10443 : { 2170 /* vmrs */, ARM::VMRS_FPSID, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSID }, },
10444 : { 2170 /* vmrs */, ARM::VMRS_MVFR0, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR0 }, },
10445 : { 2170 /* vmrs */, ARM::VMRS_MVFR1, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR1 }, },
10446 : { 2170 /* vmrs */, ARM::VMRS_MVFR2, Convert__Reg1_1__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR2 }, },
10447 : { 2175 /* vmsr */, ARM::VMSR_FPEXC, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPEXC, MCK_GPRnopc }, },
10448 : { 2175 /* vmsr */, ARM::VMSR_FPINST, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPINST, MCK_GPRnopc }, },
10449 : { 2175 /* vmsr */, ARM::VMSR_FPINST2, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPINST2, MCK_GPRnopc }, },
10450 : { 2175 /* vmsr */, ARM::VMSR, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPSCR, MCK_GPRnopc }, },
10451 : { 2175 /* vmsr */, ARM::VMSR_FPSID, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPSID, MCK_GPRnopc }, },
10452 : { 2180 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
10453 : { 2180 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10454 : { 2180 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
10455 : { 2180 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
10456 : { 2180 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
10457 : { 2180 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
10458 : { 2180 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
10459 : { 2180 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
10460 : { 2180 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
10461 : { 2180 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
10462 : { 2180 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR }, },
10463 : { 2180 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR }, },
10464 : { 2180 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
10465 : { 2180 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10466 : { 2180 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
10467 : { 2180 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10468 : { 2180 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10469 : { 2180 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10470 : { 2180 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10471 : { 2180 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10472 : { 2180 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10473 : { 2180 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10474 : { 2180 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10475 : { 2180 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10476 : { 2180 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10477 : { 2180 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10478 : { 2180 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10479 : { 2180 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10480 : { 2180 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10481 : { 2180 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10482 : { 2180 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10483 : { 2180 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10484 : { 2180 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10485 : { 2180 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10486 : { 2180 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10487 : { 2180 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10488 : { 2180 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10489 : { 2180 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10490 : { 2180 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10491 : { 2180 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10492 : { 2180 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10493 : { 2180 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10494 : { 2180 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10495 : { 2180 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10496 : { 2180 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10497 : { 2180 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10498 : { 2185 /* vmull */, ARM::VMULLp64, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_p64, MCK_QPR, MCK_DPR, MCK_DPR }, },
10499 : { 2185 /* vmull */, ARM::VMULLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10500 : { 2185 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10501 : { 2185 /* vmull */, ARM::VMULLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
10502 : { 2185 /* vmull */, ARM::VMULLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10503 : { 2185 /* vmull */, ARM::VMULLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10504 : { 2185 /* vmull */, ARM::VMULLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
10505 : { 2185 /* vmull */, ARM::VMULLp8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_DPR, MCK_DPR }, },
10506 : { 2185 /* vmull */, ARM::VMULLslsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10507 : { 2185 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10508 : { 2185 /* vmull */, ARM::VMULLsluv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10509 : { 2185 /* vmull */, ARM::VMULLsluv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10510 : { 2191 /* vmvn */, ARM::VMVNq, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
10511 : { 2191 /* vmvn */, ARM::VMVNd, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
10512 : { 2191 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16invi8Replicate }, },
10513 : { 2191 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
10514 : { 2191 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16invi8Replicate }, },
10515 : { 2191 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
10516 : { 2191 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32invi8Replicate }, },
10517 : { 2191 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
10518 : { 2191 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
10519 : { 2191 /* vmvn */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
10520 : { 2191 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32invi8Replicate }, },
10521 : { 2191 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
10522 : { 2191 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
10523 : { 2191 /* vmvn */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
10524 : { 2191 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64invi8Replicate }, },
10525 : { 2191 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
10526 : { 2191 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
10527 : { 2191 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64invi8Replicate }, },
10528 : { 2191 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
10529 : { 2191 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
10530 : { 2191 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
10531 : { 2191 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
10532 : { 2191 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
10533 : { 2191 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
10534 : { 2191 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
10535 : { 2191 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
10536 : { 2191 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10537 : { 2191 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
10538 : { 2196 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10539 : { 2196 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10540 : { 2196 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10541 : { 2196 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10542 : { 2196 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10543 : { 2196 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10544 : { 2196 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
10545 : { 2196 /* vneg */, ARM::VNEGfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10546 : { 2196 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
10547 : { 2196 /* vneg */, ARM::VNEGD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
10548 : { 2196 /* vneg */, ARM::VNEGhq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
10549 : { 2196 /* vneg */, ARM::VNEGhd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10550 : { 2196 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
10551 : { 2201 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10552 : { 2201 /* vnmla */, ARM::VNMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10553 : { 2201 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10554 : { 2207 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10555 : { 2207 /* vnmls */, ARM::VNMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10556 : { 2207 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10557 : { 2213 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
10558 : { 2213 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10559 : { 2213 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
10560 : { 2219 /* vorn */, ARM::VORNq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
10561 : { 2219 /* vorn */, ARM::VORNd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
10562 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
10563 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
10564 : { 2224 /* vorr */, ARM::VORRiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
10565 : { 2224 /* vorr */, ARM::VORRiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
10566 : { 2224 /* vorr */, ARM::VORRiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
10567 : { 2224 /* vorr */, ARM::VORRiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
10568 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
10569 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
10570 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
10571 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
10572 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
10573 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
10574 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10575 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
10576 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
10577 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
10578 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10579 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10580 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10581 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10582 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10583 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10584 : { 2224 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10585 : { 2224 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10586 : { 2229 /* vpadal */, ARM::VPADALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10587 : { 2229 /* vpadal */, ARM::VPADALsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10588 : { 2229 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10589 : { 2229 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10590 : { 2229 /* vpadal */, ARM::VPADALsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10591 : { 2229 /* vpadal */, ARM::VPADALsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10592 : { 2229 /* vpadal */, ARM::VPADALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10593 : { 2229 /* vpadal */, ARM::VPADALuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10594 : { 2229 /* vpadal */, ARM::VPADALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10595 : { 2229 /* vpadal */, ARM::VPADALuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10596 : { 2229 /* vpadal */, ARM::VPADALuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10597 : { 2229 /* vpadal */, ARM::VPADALuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10598 : { 2236 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10599 : { 2236 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
10600 : { 2236 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
10601 : { 2236 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
10602 : { 2236 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10603 : { 2236 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10604 : { 2236 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10605 : { 2236 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10606 : { 2236 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10607 : { 2236 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10608 : { 2242 /* vpaddl */, ARM::VPADDLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10609 : { 2242 /* vpaddl */, ARM::VPADDLsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10610 : { 2242 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10611 : { 2242 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10612 : { 2242 /* vpaddl */, ARM::VPADDLsv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10613 : { 2242 /* vpaddl */, ARM::VPADDLsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10614 : { 2242 /* vpaddl */, ARM::VPADDLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10615 : { 2242 /* vpaddl */, ARM::VPADDLuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10616 : { 2242 /* vpaddl */, ARM::VPADDLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10617 : { 2242 /* vpaddl */, ARM::VPADDLuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10618 : { 2242 /* vpaddl */, ARM::VPADDLuv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10619 : { 2242 /* vpaddl */, ARM::VPADDLuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10620 : { 2249 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10621 : { 2249 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10622 : { 2249 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10623 : { 2249 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10624 : { 2249 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10625 : { 2249 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10626 : { 2249 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10627 : { 2249 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10628 : { 2249 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10629 : { 2249 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10630 : { 2249 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10631 : { 2249 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10632 : { 2249 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10633 : { 2249 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10634 : { 2249 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10635 : { 2249 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10636 : { 2255 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10637 : { 2255 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10638 : { 2255 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10639 : { 2255 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10640 : { 2255 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10641 : { 2255 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10642 : { 2255 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10643 : { 2255 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10644 : { 2255 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10645 : { 2255 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10646 : { 2255 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10647 : { 2255 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10648 : { 2255 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10649 : { 2255 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10650 : { 2255 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10651 : { 2255 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10652 : { 2261 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_DPRRegList }, },
10653 : { 2261 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_SPRRegList }, },
10654 : { 2261 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
10655 : { 2261 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
10656 : { 2261 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
10657 : { 2261 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
10658 : { 2261 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
10659 : { 2261 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
10660 : { 2261 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
10661 : { 2261 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
10662 : { 2266 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_DPRRegList }, },
10663 : { 2266 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_SPRRegList }, },
10664 : { 2266 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
10665 : { 2266 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
10666 : { 2266 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
10667 : { 2266 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
10668 : { 2266 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
10669 : { 2266 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
10670 : { 2266 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
10671 : { 2266 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
10672 : { 2272 /* vqabs */, ARM::VQABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10673 : { 2272 /* vqabs */, ARM::VQABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10674 : { 2272 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10675 : { 2272 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10676 : { 2272 /* vqabs */, ARM::VQABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10677 : { 2272 /* vqabs */, ARM::VQABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10678 : { 2278 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10679 : { 2278 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10680 : { 2278 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10681 : { 2278 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10682 : { 2278 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
10683 : { 2278 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
10684 : { 2278 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10685 : { 2278 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10686 : { 2278 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10687 : { 2278 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10688 : { 2278 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10689 : { 2278 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10690 : { 2278 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
10691 : { 2278 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
10692 : { 2278 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10693 : { 2278 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10694 : { 2278 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10695 : { 2278 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10696 : { 2278 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10697 : { 2278 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10698 : { 2278 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10699 : { 2278 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10700 : { 2278 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10701 : { 2278 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10702 : { 2278 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10703 : { 2278 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10704 : { 2278 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10705 : { 2278 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10706 : { 2278 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10707 : { 2278 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10708 : { 2278 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10709 : { 2278 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10710 : { 2284 /* vqdmlal */, ARM::VQDMLALv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10711 : { 2284 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10712 : { 2284 /* vqdmlal */, ARM::VQDMLALslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10713 : { 2284 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10714 : { 2292 /* vqdmlsl */, ARM::VQDMLSLv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10715 : { 2292 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10716 : { 2292 /* vqdmlsl */, ARM::VQDMLSLslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10717 : { 2292 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10718 : { 2300 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10719 : { 2300 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10720 : { 2300 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10721 : { 2300 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10722 : { 2300 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10723 : { 2300 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10724 : { 2300 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10725 : { 2300 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10726 : { 2300 /* vqdmulh */, ARM::VQDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10727 : { 2300 /* vqdmulh */, ARM::VQDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10728 : { 2300 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10729 : { 2300 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10730 : { 2308 /* vqdmull */, ARM::VQDMULLv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
10731 : { 2308 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
10732 : { 2308 /* vqdmull */, ARM::VQDMULLslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10733 : { 2308 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10734 : { 2316 /* vqmovn */, ARM::VQMOVNsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
10735 : { 2316 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
10736 : { 2316 /* vqmovn */, ARM::VQMOVNsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
10737 : { 2316 /* vqmovn */, ARM::VQMOVNuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR }, },
10738 : { 2316 /* vqmovn */, ARM::VQMOVNuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR }, },
10739 : { 2316 /* vqmovn */, ARM::VQMOVNuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR }, },
10740 : { 2323 /* vqmovun */, ARM::VQMOVNsuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
10741 : { 2323 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
10742 : { 2323 /* vqmovun */, ARM::VQMOVNsuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
10743 : { 2331 /* vqneg */, ARM::VQNEGv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10744 : { 2331 /* vqneg */, ARM::VQNEGv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10745 : { 2331 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10746 : { 2331 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10747 : { 2331 /* vqneg */, ARM::VQNEGv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10748 : { 2331 /* vqneg */, ARM::VQNEGv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10749 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10750 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10751 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10752 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10753 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10754 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10755 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10756 : { 2337 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10757 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10758 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10759 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10760 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10761 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10762 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10763 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10764 : { 2346 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10765 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10766 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10767 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10768 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10769 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10770 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10771 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10772 : { 2355 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10773 : { 2355 /* vqrdmulh */, ARM::VQRDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10774 : { 2355 /* vqrdmulh */, ARM::VQRDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
10775 : { 2355 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10776 : { 2355 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
10777 : { 2364 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10778 : { 2364 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10779 : { 2364 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10780 : { 2364 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10781 : { 2364 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
10782 : { 2364 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
10783 : { 2364 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10784 : { 2364 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10785 : { 2364 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10786 : { 2364 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10787 : { 2364 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10788 : { 2364 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10789 : { 2364 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
10790 : { 2364 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
10791 : { 2364 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10792 : { 2364 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10793 : { 2364 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10794 : { 2364 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10795 : { 2364 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10796 : { 2364 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10797 : { 2364 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10798 : { 2364 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10799 : { 2364 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10800 : { 2364 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10801 : { 2364 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10802 : { 2364 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10803 : { 2364 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10804 : { 2364 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10805 : { 2364 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10806 : { 2364 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10807 : { 2364 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10808 : { 2364 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10809 : { 2371 /* vqrshrn */, ARM::VQRSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
10810 : { 2371 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
10811 : { 2371 /* vqrshrn */, ARM::VQRSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
10812 : { 2371 /* vqrshrn */, ARM::VQRSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
10813 : { 2371 /* vqrshrn */, ARM::VQRSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
10814 : { 2371 /* vqrshrn */, ARM::VQRSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
10815 : { 2379 /* vqrshrun */, ARM::VQRSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
10816 : { 2379 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
10817 : { 2379 /* vqrshrun */, ARM::VQRSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
10818 : { 2388 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10819 : { 2388 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
10820 : { 2388 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10821 : { 2388 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
10822 : { 2388 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10823 : { 2388 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
10824 : { 2388 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10825 : { 2388 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
10826 : { 2388 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
10827 : { 2388 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
10828 : { 2388 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
10829 : { 2388 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
10830 : { 2388 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10831 : { 2388 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
10832 : { 2388 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10833 : { 2388 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
10834 : { 2388 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10835 : { 2388 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_Imm }, },
10836 : { 2388 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10837 : { 2388 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_Imm }, },
10838 : { 2388 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10839 : { 2388 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_Imm }, },
10840 : { 2388 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10841 : { 2388 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_Imm }, },
10842 : { 2388 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
10843 : { 2388 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_Imm }, },
10844 : { 2388 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
10845 : { 2388 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_Imm }, },
10846 : { 2388 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10847 : { 2388 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_Imm }, },
10848 : { 2388 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10849 : { 2388 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_Imm }, },
10850 : { 2388 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10851 : { 2388 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
10852 : { 2388 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10853 : { 2388 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
10854 : { 2388 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10855 : { 2388 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
10856 : { 2388 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10857 : { 2388 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
10858 : { 2388 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10859 : { 2388 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
10860 : { 2388 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10861 : { 2388 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
10862 : { 2388 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10863 : { 2388 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
10864 : { 2388 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10865 : { 2388 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
10866 : { 2388 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10867 : { 2388 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
10868 : { 2388 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10869 : { 2388 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
10870 : { 2388 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10871 : { 2388 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
10872 : { 2388 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10873 : { 2388 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
10874 : { 2388 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10875 : { 2388 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_Imm }, },
10876 : { 2388 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10877 : { 2388 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_Imm }, },
10878 : { 2388 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10879 : { 2388 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_Imm }, },
10880 : { 2388 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10881 : { 2388 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_Imm }, },
10882 : { 2394 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
10883 : { 2394 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
10884 : { 2394 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
10885 : { 2394 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
10886 : { 2394 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
10887 : { 2394 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
10888 : { 2394 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
10889 : { 2394 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
10890 : { 2394 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
10891 : { 2394 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
10892 : { 2394 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
10893 : { 2394 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
10894 : { 2394 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
10895 : { 2394 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
10896 : { 2394 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
10897 : { 2394 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
10898 : { 2401 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
10899 : { 2401 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
10900 : { 2401 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
10901 : { 2401 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
10902 : { 2401 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
10903 : { 2401 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
10904 : { 2408 /* vqshrun */, ARM::VQSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
10905 : { 2408 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
10906 : { 2408 /* vqshrun */, ARM::VQSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
10907 : { 2416 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10908 : { 2416 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10909 : { 2416 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10910 : { 2416 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10911 : { 2416 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
10912 : { 2416 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
10913 : { 2416 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10914 : { 2416 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10915 : { 2416 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10916 : { 2416 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10917 : { 2416 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10918 : { 2416 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10919 : { 2416 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
10920 : { 2416 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
10921 : { 2416 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10922 : { 2416 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10923 : { 2416 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10924 : { 2416 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10925 : { 2416 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10926 : { 2416 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10927 : { 2416 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10928 : { 2416 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10929 : { 2416 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10930 : { 2416 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10931 : { 2416 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10932 : { 2416 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10933 : { 2416 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10934 : { 2416 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10935 : { 2416 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
10936 : { 2416 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
10937 : { 2416 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10938 : { 2416 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10939 : { 2422 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
10940 : { 2422 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
10941 : { 2422 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
10942 : { 2430 /* vrecpe */, ARM::VRECPEq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10943 : { 2430 /* vrecpe */, ARM::VRECPEd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10944 : { 2430 /* vrecpe */, ARM::VRECPEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
10945 : { 2430 /* vrecpe */, ARM::VRECPEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10946 : { 2430 /* vrecpe */, ARM::VRECPEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
10947 : { 2430 /* vrecpe */, ARM::VRECPEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10948 : { 2437 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
10949 : { 2437 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10950 : { 2437 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
10951 : { 2437 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10952 : { 2437 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10953 : { 2437 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10954 : { 2437 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10955 : { 2437 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10956 : { 2444 /* vrev16 */, ARM::VREV16q8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10957 : { 2444 /* vrev16 */, ARM::VREV16d8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
10958 : { 2451 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
10959 : { 2451 /* vrev32 */, ARM::VREV32d16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
10960 : { 2451 /* vrev32 */, ARM::VREV32q8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10961 : { 2451 /* vrev32 */, ARM::VREV32d8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
10962 : { 2458 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
10963 : { 2458 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
10964 : { 2458 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
10965 : { 2458 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
10966 : { 2458 /* vrev64 */, ARM::VREV64q8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10967 : { 2458 /* vrev64 */, ARM::VREV64d8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
10968 : { 2465 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
10969 : { 2465 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
10970 : { 2465 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
10971 : { 2465 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
10972 : { 2465 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
10973 : { 2465 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
10974 : { 2465 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
10975 : { 2465 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
10976 : { 2465 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
10977 : { 2465 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
10978 : { 2465 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
10979 : { 2465 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
10980 : { 2465 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10981 : { 2465 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10982 : { 2465 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10983 : { 2465 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10984 : { 2465 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10985 : { 2465 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10986 : { 2465 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
10987 : { 2465 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
10988 : { 2465 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
10989 : { 2465 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
10990 : { 2465 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
10991 : { 2465 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
10992 : { 2472 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
10993 : { 2472 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
10994 : { 2472 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
10995 : { 2472 /* vrinta */, ARM::VRINTAD, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
10996 : { 2472 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
10997 : { 2472 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
10998 : { 2472 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
10999 : { 2472 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11000 : { 2472 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11001 : { 2472 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11002 : { 2472 /* vrinta */, ARM::VRINTAD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11003 : { 2472 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11004 : { 2472 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11005 : { 2479 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11006 : { 2479 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11007 : { 2479 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11008 : { 2479 /* vrintm */, ARM::VRINTMD, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11009 : { 2479 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11010 : { 2479 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11011 : { 2479 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11012 : { 2479 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11013 : { 2479 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11014 : { 2479 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11015 : { 2479 /* vrintm */, ARM::VRINTMD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11016 : { 2479 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11017 : { 2479 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11018 : { 2486 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11019 : { 2486 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11020 : { 2486 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11021 : { 2486 /* vrintn */, ARM::VRINTND, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11022 : { 2486 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11023 : { 2486 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11024 : { 2486 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11025 : { 2486 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11026 : { 2486 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11027 : { 2486 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11028 : { 2486 /* vrintn */, ARM::VRINTND, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11029 : { 2486 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11030 : { 2486 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11031 : { 2493 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11032 : { 2493 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11033 : { 2493 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11034 : { 2493 /* vrintp */, ARM::VRINTPD, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11035 : { 2493 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11036 : { 2493 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11037 : { 2493 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11038 : { 2493 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11039 : { 2493 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11040 : { 2493 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11041 : { 2493 /* vrintp */, ARM::VRINTPD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11042 : { 2493 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11043 : { 2493 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11044 : { 2500 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11045 : { 2500 /* vrintr */, ARM::VRINTRD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11046 : { 2500 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11047 : { 2500 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11048 : { 2500 /* vrintr */, ARM::VRINTRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11049 : { 2500 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11050 : { 2507 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11051 : { 2507 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11052 : { 2507 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11053 : { 2507 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11054 : { 2507 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11055 : { 2507 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11056 : { 2507 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11057 : { 2507 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11058 : { 2507 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11059 : { 2507 /* vrintx */, ARM::VRINTXD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11060 : { 2507 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11061 : { 2507 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11062 : { 2507 /* vrintx */, ARM::VRINTXD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11063 : { 2507 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11064 : { 2514 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11065 : { 2514 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11066 : { 2514 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11067 : { 2514 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11068 : { 2514 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11069 : { 2514 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11070 : { 2514 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11071 : { 2514 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11072 : { 2514 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11073 : { 2514 /* vrintz */, ARM::VRINTZD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11074 : { 2514 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11075 : { 2514 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11076 : { 2514 /* vrintz */, ARM::VRINTZD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11077 : { 2514 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11078 : { 2521 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
11079 : { 2521 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
11080 : { 2521 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11081 : { 2521 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11082 : { 2521 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
11083 : { 2521 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
11084 : { 2521 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
11085 : { 2521 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
11086 : { 2521 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
11087 : { 2521 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
11088 : { 2521 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
11089 : { 2521 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
11090 : { 2521 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
11091 : { 2521 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
11092 : { 2521 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
11093 : { 2521 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
11094 : { 2521 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11095 : { 2521 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11096 : { 2521 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11097 : { 2521 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11098 : { 2521 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11099 : { 2521 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11100 : { 2521 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11101 : { 2521 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11102 : { 2521 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11103 : { 2521 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11104 : { 2521 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11105 : { 2521 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11106 : { 2521 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11107 : { 2521 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11108 : { 2521 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11109 : { 2521 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11110 : { 2527 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
11111 : { 2527 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
11112 : { 2527 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
11113 : { 2527 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
11114 : { 2527 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
11115 : { 2527 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
11116 : { 2527 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
11117 : { 2527 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
11118 : { 2527 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
11119 : { 2527 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
11120 : { 2527 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
11121 : { 2527 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
11122 : { 2527 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
11123 : { 2527 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
11124 : { 2527 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
11125 : { 2527 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
11126 : { 2527 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11127 : { 2527 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11128 : { 2527 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11129 : { 2527 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11130 : { 2527 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11131 : { 2527 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11132 : { 2527 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11133 : { 2527 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11134 : { 2527 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11135 : { 2527 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11136 : { 2527 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11137 : { 2527 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11138 : { 2527 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11139 : { 2527 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11140 : { 2527 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11141 : { 2527 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11142 : { 2533 /* vrshrn */, ARM::VRSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
11143 : { 2533 /* vrshrn */, ARM::VRSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
11144 : { 2533 /* vrshrn */, ARM::VRSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
11145 : { 2540 /* vrsqrte */, ARM::VRSQRTEq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
11146 : { 2540 /* vrsqrte */, ARM::VRSQRTEd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
11147 : { 2540 /* vrsqrte */, ARM::VRSQRTEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11148 : { 2540 /* vrsqrte */, ARM::VRSQRTEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11149 : { 2540 /* vrsqrte */, ARM::VRSQRTEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11150 : { 2540 /* vrsqrte */, ARM::VRSQRTEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11151 : { 2548 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11152 : { 2548 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11153 : { 2548 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11154 : { 2548 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11155 : { 2548 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11156 : { 2548 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11157 : { 2548 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11158 : { 2548 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11159 : { 2556 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
11160 : { 2556 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
11161 : { 2556 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
11162 : { 2556 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
11163 : { 2556 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
11164 : { 2556 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
11165 : { 2556 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
11166 : { 2556 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
11167 : { 2556 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
11168 : { 2556 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
11169 : { 2556 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
11170 : { 2556 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
11171 : { 2556 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
11172 : { 2556 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
11173 : { 2556 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
11174 : { 2556 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
11175 : { 2556 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11176 : { 2556 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11177 : { 2556 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11178 : { 2556 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11179 : { 2556 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11180 : { 2556 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11181 : { 2556 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11182 : { 2556 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11183 : { 2556 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11184 : { 2556 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11185 : { 2556 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11186 : { 2556 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11187 : { 2556 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11188 : { 2556 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11189 : { 2556 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11190 : { 2556 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11191 : { 2562 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
11192 : { 2562 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
11193 : { 2562 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
11194 : { 2570 /* vsdot */, ARM::VSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11195 : { 2570 /* vsdot */, ARM::VSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11196 : { 2570 /* vsdot */, ARM::VSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
11197 : { 2570 /* vsdot */, ARM::VSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
11198 : { 2576 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11199 : { 2576 /* vseleq */, ARM::VSELEQD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11200 : { 2576 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11201 : { 2583 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11202 : { 2583 /* vselge */, ARM::VSELGED, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11203 : { 2583 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11204 : { 2590 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11205 : { 2590 /* vselgt */, ARM::VSELGTD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11206 : { 2590 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11207 : { 2597 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11208 : { 2597 /* vselvs */, ARM::VSELVSD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11209 : { 2597 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11210 : { 2604 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
11211 : { 2604 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
11212 : { 2604 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11213 : { 2604 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11214 : { 2604 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
11215 : { 2604 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
11216 : { 2604 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
11217 : { 2604 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
11218 : { 2604 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
11219 : { 2604 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
11220 : { 2604 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
11221 : { 2604 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
11222 : { 2604 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
11223 : { 2604 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
11224 : { 2604 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
11225 : { 2604 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
11226 : { 2604 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_Imm }, },
11227 : { 2604 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_Imm }, },
11228 : { 2604 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_Imm }, },
11229 : { 2604 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_Imm }, },
11230 : { 2604 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_Imm }, },
11231 : { 2604 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_Imm }, },
11232 : { 2604 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_Imm }, },
11233 : { 2604 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_Imm }, },
11234 : { 2604 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11235 : { 2604 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11236 : { 2604 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11237 : { 2604 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11238 : { 2604 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11239 : { 2604 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11240 : { 2604 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11241 : { 2604 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11242 : { 2604 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11243 : { 2604 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11244 : { 2604 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11245 : { 2604 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11246 : { 2604 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11247 : { 2604 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11248 : { 2604 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11249 : { 2604 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11250 : { 2604 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_Imm }, },
11251 : { 2604 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_Imm }, },
11252 : { 2604 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_Imm }, },
11253 : { 2604 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_Imm }, },
11254 : { 2604 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_Imm }, },
11255 : { 2604 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_Imm }, },
11256 : { 2604 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_Imm }, },
11257 : { 2604 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_Imm }, },
11258 : { 2609 /* vshll */, ARM::VSHLLsv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
11259 : { 2609 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
11260 : { 2609 /* vshll */, ARM::VSHLLsv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
11261 : { 2609 /* vshll */, ARM::VSHLLuv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
11262 : { 2609 /* vshll */, ARM::VSHLLuv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
11263 : { 2609 /* vshll */, ARM::VSHLLuv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
11264 : { 2609 /* vshll */, ARM::VSHLLi16, Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR, MCK_Imm16 }, },
11265 : { 2609 /* vshll */, ARM::VSHLLi32, Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR, MCK_Imm32 }, },
11266 : { 2609 /* vshll */, ARM::VSHLLi8, Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_DPR, MCK_Imm8 }, },
11267 : { 2615 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
11268 : { 2615 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
11269 : { 2615 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
11270 : { 2615 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
11271 : { 2615 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
11272 : { 2615 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
11273 : { 2615 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
11274 : { 2615 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
11275 : { 2615 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
11276 : { 2615 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
11277 : { 2615 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
11278 : { 2615 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
11279 : { 2615 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
11280 : { 2615 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
11281 : { 2615 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
11282 : { 2615 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
11283 : { 2615 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11284 : { 2615 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11285 : { 2615 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11286 : { 2615 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11287 : { 2615 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11288 : { 2615 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11289 : { 2615 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11290 : { 2615 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11291 : { 2615 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11292 : { 2615 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11293 : { 2615 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11294 : { 2615 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11295 : { 2615 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11296 : { 2615 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11297 : { 2615 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11298 : { 2615 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11299 : { 2620 /* vshrn */, ARM::VSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
11300 : { 2620 /* vshrn */, ARM::VSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
11301 : { 2620 /* vshrn */, ARM::VSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
11302 : { 2626 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_Imm }, },
11303 : { 2626 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_Imm }, },
11304 : { 2626 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_Imm }, },
11305 : { 2626 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_Imm }, },
11306 : { 2626 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_Imm }, },
11307 : { 2626 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_Imm }, },
11308 : { 2626 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_Imm }, },
11309 : { 2626 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_Imm }, },
11310 : { 2626 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm }, },
11311 : { 2626 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm }, },
11312 : { 2626 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm }, },
11313 : { 2626 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm }, },
11314 : { 2626 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm }, },
11315 : { 2626 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_Imm }, },
11316 : { 2626 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm }, },
11317 : { 2626 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm }, },
11318 : { 2631 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
11319 : { 2631 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
11320 : { 2631 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11321 : { 2631 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11322 : { 2631 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11323 : { 2637 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
11324 : { 2637 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
11325 : { 2637 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
11326 : { 2637 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
11327 : { 2637 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
11328 : { 2637 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
11329 : { 2637 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
11330 : { 2637 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
11331 : { 2637 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
11332 : { 2637 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
11333 : { 2637 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
11334 : { 2637 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
11335 : { 2637 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
11336 : { 2637 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
11337 : { 2637 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
11338 : { 2637 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
11339 : { 2637 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11340 : { 2637 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11341 : { 2637 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11342 : { 2637 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11343 : { 2637 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11344 : { 2637 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11345 : { 2637 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11346 : { 2637 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11347 : { 2637 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11348 : { 2637 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11349 : { 2637 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11350 : { 2637 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11351 : { 2637 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11352 : { 2637 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11353 : { 2637 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11354 : { 2637 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11355 : { 2642 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_ShrImm16 }, },
11356 : { 2642 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_ShrImm16 }, },
11357 : { 2642 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_ShrImm32 }, },
11358 : { 2642 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_ShrImm32 }, },
11359 : { 2642 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_ShrImm64 }, },
11360 : { 2642 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_ShrImm64 }, },
11361 : { 2642 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_ShrImm8 }, },
11362 : { 2642 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_ShrImm8 }, },
11363 : { 2642 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
11364 : { 2642 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
11365 : { 2642 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
11366 : { 2642 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
11367 : { 2642 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
11368 : { 2642 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
11369 : { 2642 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
11370 : { 2642 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
11371 : { 2647 /* vst1 */, ARM::VST1q16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
11372 : { 2647 /* vst1 */, ARM::VST1d16Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11373 : { 2647 /* vst1 */, ARM::VST1d16, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
11374 : { 2647 /* vst1 */, ARM::VST1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
11375 : { 2647 /* vst1 */, ARM::VST1d16T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
11376 : { 2647 /* vst1 */, ARM::VST1q32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
11377 : { 2647 /* vst1 */, ARM::VST1d32Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11378 : { 2647 /* vst1 */, ARM::VST1d32, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
11379 : { 2647 /* vst1 */, ARM::VST1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
11380 : { 2647 /* vst1 */, ARM::VST1d32T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
11381 : { 2647 /* vst1 */, ARM::VST1q64, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
11382 : { 2647 /* vst1 */, ARM::VST1d64Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11383 : { 2647 /* vst1 */, ARM::VST1d64, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
11384 : { 2647 /* vst1 */, ARM::VST1d64T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
11385 : { 2647 /* vst1 */, ARM::VST1q8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
11386 : { 2647 /* vst1 */, ARM::VST1d8Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11387 : { 2647 /* vst1 */, ARM::VST1d8, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
11388 : { 2647 /* vst1 */, ARM::VST1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
11389 : { 2647 /* vst1 */, ARM::VST1d8T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
11390 : { 2647 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11391 : { 2647 /* vst1 */, ARM::VST1q16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
11392 : { 2647 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11393 : { 2647 /* vst1 */, ARM::VST1d16Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11394 : { 2647 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11395 : { 2647 /* vst1 */, ARM::VST1d16wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
11396 : { 2647 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
11397 : { 2647 /* vst1 */, ARM::VST1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
11398 : { 2647 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11399 : { 2647 /* vst1 */, ARM::VST1d16Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
11400 : { 2647 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11401 : { 2647 /* vst1 */, ARM::VST1q32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
11402 : { 2647 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11403 : { 2647 /* vst1 */, ARM::VST1d32Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11404 : { 2647 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11405 : { 2647 /* vst1 */, ARM::VST1d32wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
11406 : { 2647 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
11407 : { 2647 /* vst1 */, ARM::VST1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
11408 : { 2647 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11409 : { 2647 /* vst1 */, ARM::VST1d32Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
11410 : { 2647 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11411 : { 2647 /* vst1 */, ARM::VST1q64wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
11412 : { 2647 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11413 : { 2647 /* vst1 */, ARM::VST1d64Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11414 : { 2647 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11415 : { 2647 /* vst1 */, ARM::VST1d64wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
11416 : { 2647 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11417 : { 2647 /* vst1 */, ARM::VST1d64Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
11418 : { 2647 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11419 : { 2647 /* vst1 */, ARM::VST1q8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
11420 : { 2647 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11421 : { 2647 /* vst1 */, ARM::VST1d8Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11422 : { 2647 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11423 : { 2647 /* vst1 */, ARM::VST1d8wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
11424 : { 2647 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
11425 : { 2647 /* vst1 */, ARM::VST1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
11426 : { 2647 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11427 : { 2647 /* vst1 */, ARM::VST1d8Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
11428 : { 2647 /* vst1 */, ARM::VST1LNd16, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
11429 : { 2647 /* vst1 */, ARM::VST1LNd8, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
11430 : { 2647 /* vst1 */, ARM::VST1LNd16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11431 : { 2647 /* vst1 */, ARM::VST1LNd32, Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
11432 : { 2647 /* vst1 */, ARM::VST1LNd8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11433 : { 2647 /* vst1 */, ARM::VST1LNd32_UPD, Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm, MCK_Imm }, },
11434 : { 2652 /* vst2 */, ARM::VST2d16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
11435 : { 2652 /* vst2 */, ARM::VST2b16, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
11436 : { 2652 /* vst2 */, ARM::VST2q16, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11437 : { 2652 /* vst2 */, ARM::VST2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
11438 : { 2652 /* vst2 */, ARM::VST2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
11439 : { 2652 /* vst2 */, ARM::VST2d32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
11440 : { 2652 /* vst2 */, ARM::VST2b32, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
11441 : { 2652 /* vst2 */, ARM::VST2q32, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11442 : { 2652 /* vst2 */, ARM::VST2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
11443 : { 2652 /* vst2 */, ARM::VST2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
11444 : { 2652 /* vst2 */, ARM::VST2d8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
11445 : { 2652 /* vst2 */, ARM::VST2b8, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
11446 : { 2652 /* vst2 */, ARM::VST2q8, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11447 : { 2652 /* vst2 */, ARM::VST2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
11448 : { 2652 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11449 : { 2652 /* vst2 */, ARM::VST2d16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
11450 : { 2652 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11451 : { 2652 /* vst2 */, ARM::VST2b16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
11452 : { 2652 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11453 : { 2652 /* vst2 */, ARM::VST2q16wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11454 : { 2652 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
11455 : { 2652 /* vst2 */, ARM::VST2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
11456 : { 2652 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
11457 : { 2652 /* vst2 */, ARM::VST2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
11458 : { 2652 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11459 : { 2652 /* vst2 */, ARM::VST2d32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
11460 : { 2652 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11461 : { 2652 /* vst2 */, ARM::VST2b32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
11462 : { 2652 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11463 : { 2652 /* vst2 */, ARM::VST2q32wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11464 : { 2652 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11465 : { 2652 /* vst2 */, ARM::VST2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
11466 : { 2652 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11467 : { 2652 /* vst2 */, ARM::VST2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
11468 : { 2652 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11469 : { 2652 /* vst2 */, ARM::VST2d8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
11470 : { 2652 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11471 : { 2652 /* vst2 */, ARM::VST2b8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
11472 : { 2652 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11473 : { 2652 /* vst2 */, ARM::VST2q8wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11474 : { 2652 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
11475 : { 2652 /* vst2 */, ARM::VST2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
11476 : { 2657 /* vst3 */, ARM::VST3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
11477 : { 2657 /* vst3 */, ARM::VST3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
11478 : { 2657 /* vst3 */, ARM::VST3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
11479 : { 2657 /* vst3 */, ARM::VST3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
11480 : { 2657 /* vst3 */, ARM::VST3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
11481 : { 2657 /* vst3 */, ARM::VST3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
11482 : { 2657 /* vst3 */, ARM::VST3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
11483 : { 2657 /* vst3 */, ARM::VST3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
11484 : { 2657 /* vst3 */, ARM::VST3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
11485 : { 2657 /* vst3 */, ARM::VST3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
11486 : { 2657 /* vst3 */, ARM::VST3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
11487 : { 2657 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11488 : { 2657 /* vst3 */, ARM::VST3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
11489 : { 2657 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
11490 : { 2657 /* vst3 */, ARM::VST3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
11491 : { 2657 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11492 : { 2657 /* vst3 */, ARM::VST3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
11493 : { 2657 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
11494 : { 2657 /* vst3 */, ARM::VST3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
11495 : { 2657 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11496 : { 2657 /* vst3 */, ARM::VST3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
11497 : { 2657 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
11498 : { 2657 /* vst3 */, ARM::VST3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
11499 : { 2657 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11500 : { 2657 /* vst3 */, ARM::VST3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
11501 : { 2657 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
11502 : { 2657 /* vst3 */, ARM::VST3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
11503 : { 2657 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11504 : { 2657 /* vst3 */, ARM::VST3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
11505 : { 2657 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
11506 : { 2657 /* vst3 */, ARM::VST3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
11507 : { 2657 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11508 : { 2657 /* vst3 */, ARM::VST3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
11509 : { 2657 /* vst3 */, ARM::VST3d16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11510 : { 2657 /* vst3 */, ARM::VST3q16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11511 : { 2657 /* vst3 */, ARM::VST3d32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11512 : { 2657 /* vst3 */, ARM::VST3q32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11513 : { 2657 /* vst3 */, ARM::VST3d8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11514 : { 2657 /* vst3 */, ARM::VST3q8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11515 : { 2657 /* vst3 */, ARM::VST3d16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11516 : { 2657 /* vst3 */, ARM::VST3q16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11517 : { 2657 /* vst3 */, ARM::VST3d32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11518 : { 2657 /* vst3 */, ARM::VST3q32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11519 : { 2657 /* vst3 */, ARM::VST3d8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11520 : { 2657 /* vst3 */, ARM::VST3q8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11521 : { 2662 /* vst4 */, ARM::VST4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11522 : { 2662 /* vst4 */, ARM::VST4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
11523 : { 2662 /* vst4 */, ARM::VST4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
11524 : { 2662 /* vst4 */, ARM::VST4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
11525 : { 2662 /* vst4 */, ARM::VST4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11526 : { 2662 /* vst4 */, ARM::VST4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
11527 : { 2662 /* vst4 */, ARM::VST4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
11528 : { 2662 /* vst4 */, ARM::VST4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
11529 : { 2662 /* vst4 */, ARM::VST4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
11530 : { 2662 /* vst4 */, ARM::VST4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
11531 : { 2662 /* vst4 */, ARM::VST4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
11532 : { 2662 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11533 : { 2662 /* vst4 */, ARM::VST4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11534 : { 2662 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11535 : { 2662 /* vst4 */, ARM::VST4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
11536 : { 2662 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11537 : { 2662 /* vst4 */, ARM::VST4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11538 : { 2662 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
11539 : { 2662 /* vst4 */, ARM::VST4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
11540 : { 2662 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11541 : { 2662 /* vst4 */, ARM::VST4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11542 : { 2662 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11543 : { 2662 /* vst4 */, ARM::VST4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
11544 : { 2662 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11545 : { 2662 /* vst4 */, ARM::VST4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11546 : { 2662 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
11547 : { 2662 /* vst4 */, ARM::VST4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
11548 : { 2662 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11549 : { 2662 /* vst4 */, ARM::VST4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11550 : { 2662 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
11551 : { 2662 /* vst4 */, ARM::VST4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
11552 : { 2662 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
11553 : { 2662 /* vst4 */, ARM::VST4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
11554 : { 2662 /* vst4 */, ARM::VST4d16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11555 : { 2662 /* vst4 */, ARM::VST4q16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11556 : { 2662 /* vst4 */, ARM::VST4d32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11557 : { 2662 /* vst4 */, ARM::VST4q32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11558 : { 2662 /* vst4 */, ARM::VST4d8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11559 : { 2662 /* vst4 */, ARM::VST4q8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
11560 : { 2662 /* vst4 */, ARM::VST4d16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11561 : { 2662 /* vst4 */, ARM::VST4q16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11562 : { 2662 /* vst4 */, ARM::VST4d32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11563 : { 2662 /* vst4 */, ARM::VST4q32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11564 : { 2662 /* vst4 */, ARM::VST4d8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11565 : { 2662 /* vst4 */, ARM::VST4q8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
11566 : { 2667 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
11567 : { 2667 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
11568 : { 2674 /* vstmia */, ARM::VSTMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
11569 : { 2674 /* vstmia */, ARM::VSTMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
11570 : { 2674 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
11571 : { 2674 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
11572 : { 2681 /* vstr */, ARM::VSTRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
11573 : { 2681 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
11574 : { 2681 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
11575 : { 2681 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
11576 : { 2681 /* vstr */, ARM::VSTRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
11577 : { 2686 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11578 : { 2686 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11579 : { 2686 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11580 : { 2686 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11581 : { 2686 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
11582 : { 2686 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
11583 : { 2686 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
11584 : { 2686 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
11585 : { 2686 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
11586 : { 2686 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
11587 : { 2686 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
11588 : { 2686 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
11589 : { 2686 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11590 : { 2686 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11591 : { 2686 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11592 : { 2686 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11593 : { 2686 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11594 : { 2686 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11595 : { 2686 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11596 : { 2686 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11597 : { 2686 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11598 : { 2686 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11599 : { 2686 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11600 : { 2686 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11601 : { 2686 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11602 : { 2686 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11603 : { 2686 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11604 : { 2686 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11605 : { 2686 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11606 : { 2686 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11607 : { 2691 /* vsubhn */, ARM::VSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
11608 : { 2691 /* vsubhn */, ARM::VSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
11609 : { 2691 /* vsubhn */, ARM::VSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
11610 : { 2698 /* vsubl */, ARM::VSUBLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11611 : { 2698 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11612 : { 2698 /* vsubl */, ARM::VSUBLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11613 : { 2698 /* vsubl */, ARM::VSUBLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11614 : { 2698 /* vsubl */, ARM::VSUBLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11615 : { 2698 /* vsubl */, ARM::VSUBLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11616 : { 2704 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
11617 : { 2704 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
11618 : { 2704 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
11619 : { 2704 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
11620 : { 2704 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
11621 : { 2704 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
11622 : { 2704 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
11623 : { 2704 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
11624 : { 2704 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
11625 : { 2704 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
11626 : { 2704 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
11627 : { 2704 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
11628 : { 2710 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
11629 : { 2710 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
11630 : { 2710 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
11631 : { 2710 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
11632 : { 2710 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11633 : { 2710 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
11634 : { 2710 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
11635 : { 2710 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
11636 : { 2710 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
11637 : { 2710 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
11638 : { 2715 /* vtbl */, ARM::VTBL2, Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
11639 : { 2715 /* vtbl */, ARM::VTBL4, Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
11640 : { 2715 /* vtbl */, ARM::VTBL1, Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
11641 : { 2715 /* vtbl */, ARM::VTBL3, Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
11642 : { 2720 /* vtbx */, ARM::VTBX2, Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
11643 : { 2720 /* vtbx */, ARM::VTBX4, Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
11644 : { 2720 /* vtbx */, ARM::VTBX1, Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
11645 : { 2720 /* vtbx */, ARM::VTBX3, Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
11646 : { 2725 /* vtrn */, ARM::VTRNq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
11647 : { 2725 /* vtrn */, ARM::VTRNd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
11648 : { 2725 /* vtrn */, ARM::VTRNq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11649 : { 2725 /* vtrn */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
11650 : { 2725 /* vtrn */, ARM::VTRNq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
11651 : { 2725 /* vtrn */, ARM::VTRNd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
11652 : { 2730 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
11653 : { 2730 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
11654 : { 2730 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11655 : { 2730 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
11656 : { 2730 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
11657 : { 2730 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
11658 : { 2730 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11659 : { 2730 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11660 : { 2730 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11661 : { 2730 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11662 : { 2730 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11663 : { 2730 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11664 : { 2735 /* vudot */, ARM::VUDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11665 : { 2735 /* vudot */, ARM::VUDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11666 : { 2735 /* vudot */, ARM::VUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
11667 : { 2735 /* vudot */, ARM::VUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
11668 : { 2741 /* vuzp */, ARM::VUZPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
11669 : { 2741 /* vuzp */, ARM::VUZPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
11670 : { 2741 /* vuzp */, ARM::VUZPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11671 : { 2741 /* vuzp */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
11672 : { 2741 /* vuzp */, ARM::VUZPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
11673 : { 2741 /* vuzp */, ARM::VUZPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
11674 : { 2746 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
11675 : { 2746 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
11676 : { 2746 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11677 : { 2746 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
11678 : { 2746 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
11679 : { 2746 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
11680 : { 2751 /* wfe */, ARM::HINT, Convert__imm_95_2__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
11681 : { 2751 /* wfe */, ARM::tHINT, Convert__imm_95_2__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, },
11682 : { 2751 /* wfe */, ARM::t2HINT, Convert__imm_95_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11683 : { 2755 /* wfi */, ARM::HINT, Convert__imm_95_3__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
11684 : { 2755 /* wfi */, ARM::tHINT, Convert__imm_95_3__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, },
11685 : { 2755 /* wfi */, ARM::t2HINT, Convert__imm_95_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11686 : { 2759 /* yield */, ARM::HINT, Convert__imm_95_1__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, },
11687 : { 2759 /* yield */, ARM::tHINT, Convert__imm_95_1__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, },
11688 : { 2759 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11689 : };
11690 :
11691 : #include "llvm/Support/Debug.h"
11692 : #include "llvm/Support/Format.h"
11693 :
11694 25621 : unsigned ARMAsmParser::
11695 : MatchInstructionImpl(const OperandVector &Operands,
11696 : MCInst &Inst,
11697 : SmallVectorImpl<NearMissInfo> *NearMisses,
11698 : bool matchingInlineAsm, unsigned VariantID) {
11699 : // Get the current feature set.
11700 25621 : uint64_t AvailableFeatures = getAvailableFeatures();
11701 :
11702 : // Get the instruction mnemonic, which is the first token.
11703 25621 : StringRef Mnemonic = ((ARMOperand&)*Operands[0]).getToken();
11704 :
11705 : // Process all MnemonicAliases to remap the mnemonic.
11706 25621 : applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
11707 :
11708 : // Find the appropriate table for this asm variant.
11709 : const MatchEntry *Start, *End;
11710 25621 : switch (VariantID) {
11711 0 : default: llvm_unreachable("invalid variant!");
11712 : case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11713 : }
11714 : // Search the table.
11715 : auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
11716 :
11717 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
11718 : std::distance(MnemonicRange.first, MnemonicRange.second) <<
11719 : " encodings with mnemonic '" << Mnemonic << "'\n");
11720 :
11721 : // Return a more specific error code if no mnemonics match.
11722 25621 : if (MnemonicRange.first == MnemonicRange.second)
11723 : return Match_MnemonicFail;
11724 :
11725 316249 : for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
11726 341844 : it != ie; ++it) {
11727 337545 : bool HasRequiredFeatures =
11728 337545 : (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures;
11729 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
11730 : << MII.getName(it->Opcode) << "\n");
11731 : // Some state to record ways in which this instruction did not match.
11732 : NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();
11733 : NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();
11734 : NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();
11735 : NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();
11736 : bool MultipleInvalidOperands = false;
11737 : // equal_range guarantees that instruction mnemonic matches.
11738 : assert(Mnemonic == it->getMnemonic());
11739 1317347 : for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 18; ++FormalIdx) {
11740 1317347 : auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
11741 : DEBUG_WITH_TYPE("asm-matcher",
11742 : dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
11743 : << " against actual operand at index " << ActualIdx);
11744 1317347 : if (ActualIdx < Operands.size())
11745 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
11746 : Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
11747 : else
11748 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
11749 1317347 : if (ActualIdx >= Operands.size()) {
11750 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
11751 88539 : bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
11752 : if (!ThisOperandValid) {
11753 4435 : if (!OperandNearMiss) {
11754 : // Record info about match failure for later use.
11755 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n");
11756 : OperandNearMiss =
11757 823 : NearMissInfo::getTooFewOperands(Formal, it->Opcode);
11758 3612 : } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {
11759 : // If more than one operand is invalid, give up on this match entry.
11760 : DEBUG_WITH_TYPE(
11761 : "asm-matcher",
11762 : dbgs() << "second invalid operand, giving up on this opcode\n");
11763 : MultipleInvalidOperands = true;
11764 : break;
11765 : }
11766 : } else {
11767 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n");
11768 : break;
11769 : }
11770 1487 : continue;
11771 : }
11772 : MCParsedAsmOperand &Actual = *Operands[ActualIdx];
11773 1228808 : unsigned Diag = validateOperandClass(Actual, Formal);
11774 1228808 : if (Diag == Match_Success) {
11775 : DEBUG_WITH_TYPE("asm-matcher",
11776 : dbgs() << "match success using generic matcher\n");
11777 672036 : ++ActualIdx;
11778 672036 : continue;
11779 : }
11780 : // If the generic handler indicates an invalid operand
11781 : // failure, check for a special case.
11782 : if (Diag != Match_Success) {
11783 556772 : unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
11784 556772 : if (TargetDiag == Match_Success) {
11785 : DEBUG_WITH_TYPE("asm-matcher",
11786 : dbgs() << "match success using target matcher\n");
11787 584 : ++ActualIdx;
11788 584 : continue;
11789 : }
11790 : // If the target matcher returned a specific error code use
11791 : // that, else use the one from the generic matcher.
11792 556188 : if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
11793 : Diag = TargetDiag;
11794 : }
11795 : // If current formal operand wasn't matched and it is optional
11796 : // then try to match next formal operand
11797 556188 : if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
11798 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
11799 : continue;
11800 : }
11801 556188 : if (!OperandNearMiss) {
11802 : // If this is the first invalid operand we have seen, record some
11803 : // information about it.
11804 : DEBUG_WITH_TYPE(
11805 : "asm-matcher",
11806 : dbgs()
11807 : << "operand match failed, recording near-miss with diag code "
11808 : << Diag << "\n");
11809 : OperandNearMiss =
11810 305695 : NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);
11811 305695 : ++ActualIdx;
11812 : } else {
11813 : // If more than one operand is invalid, give up on this match entry.
11814 : DEBUG_WITH_TYPE(
11815 : "asm-matcher",
11816 : dbgs() << "second operand mismatch, skipping this opcode\n");
11817 : MultipleInvalidOperands = true;
11818 : break;
11819 : }
11820 : }
11821 :
11822 337545 : if (MultipleInvalidOperands) {
11823 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11824 : "operand mismatches, ignoring "
11825 : "this opcode\n");
11826 316249 : continue;
11827 : }
11828 84104 : if (!HasRequiredFeatures) {
11829 28977 : uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
11830 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: "
11831 : << format_hex(NewMissingFeatures, 18)
11832 : << "\n");
11833 28977 : FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);
11834 : }
11835 :
11836 : Inst.clear();
11837 :
11838 84104 : Inst.setOpcode(it->Opcode);
11839 : // We have a potential match but have not rendered the operands.
11840 : // Check the target predicate to handle any context sensitive
11841 : // constraints.
11842 : // For example, Ties that are referenced multiple times must be
11843 : // checked here to ensure the input is the same for each match
11844 : // constraints. If we leave it any later the ties will have been
11845 : // canonicalized
11846 : unsigned MatchResult;
11847 84104 : if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
11848 : Inst.clear();
11849 : DEBUG_WITH_TYPE(
11850 : "asm-matcher",
11851 : dbgs() << "Early target match predicate failed with diag code "
11852 : << MatchResult << "\n");
11853 0 : EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
11854 : }
11855 :
11856 : // If we did not successfully match the operands, then we can't convert to
11857 : // an MCInst, so bail out on this instruction variant now.
11858 84104 : if (OperandNearMiss) {
11859 : // If the operand mismatch was the only problem, reprrt it as a near-miss.
11860 53077 : if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {
11861 : DEBUG_WITH_TYPE(
11862 : "asm-matcher",
11863 : dbgs()
11864 : << "Opcode result: one mismatched operand, adding near-miss\n");
11865 33522 : NearMisses->push_back(OperandNearMiss);
11866 : } else {
11867 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11868 : "types of mismatch, so not "
11869 : "reporting near-miss\n");
11870 : }
11871 53077 : continue;
11872 : }
11873 :
11874 31027 : if (matchingInlineAsm) {
11875 0 : convertToMapAndConstraints(it->ConvertFn, Operands);
11876 21296 : return Match_Success;
11877 : }
11878 :
11879 : // We have selected a definite instruction, convert the parsed
11880 : // operands into the appropriate MCInst.
11881 31027 : convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
11882 :
11883 : // We have a potential match. Check the target predicate to
11884 : // handle any context sensitive constraints.
11885 31027 : if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
11886 : DEBUG_WITH_TYPE("asm-matcher",
11887 : dbgs() << "Target match predicate failed with diag code "
11888 : << MatchResult << "\n");
11889 : Inst.clear();
11890 157 : LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
11891 : }
11892 :
11893 31027 : int NumNearMisses = ((int)(bool)OperandNearMiss +
11894 31027 : (int)(bool)FeaturesNearMiss +
11895 31027 : (int)(bool)EarlyPredicateNearMiss +
11896 31027 : (int)(bool)LatePredicateNearMiss);
11897 31027 : if (NumNearMisses == 1) {
11898 : // We had exactly one type of near-miss, so add that to the list.
11899 : assert(!OperandNearMiss && "OperandNearMiss was handled earlier");
11900 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of "
11901 : "mismatch, so reporting a "
11902 : "near-miss\n");
11903 9719 : if (NearMisses && FeaturesNearMiss)
11904 9556 : NearMisses->push_back(FeaturesNearMiss);
11905 163 : else if (NearMisses && EarlyPredicateNearMiss)
11906 0 : NearMisses->push_back(EarlyPredicateNearMiss);
11907 163 : else if (NearMisses && LatePredicateNearMiss)
11908 144 : NearMisses->push_back(LatePredicateNearMiss);
11909 :
11910 9719 : continue;
11911 21308 : } else if (NumNearMisses > 1) {
11912 : // This instruction missed in more than one way, so ignore it.
11913 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
11914 : "types of mismatch, so not "
11915 : "reporting near-miss\n");
11916 : continue;
11917 : }
11918 : std::string Info;
11919 21296 : if (!getParser().getTargetParser().
11920 63723 : getTargetOptions().MCNoDeprecatedWarn &&
11921 42592 : MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {
11922 165 : SMLoc Loc = ((ARMOperand&)*Operands[0]).getStartLoc();
11923 330 : getParser().Warning(Loc, Info, None);
11924 : }
11925 : DEBUG_WITH_TYPE(
11926 : "asm-matcher",
11927 : dbgs() << "Opcode result: complete match, selecting this opcode\n");
11928 : return Match_Success;
11929 : }
11930 :
11931 : // No instruction variants matched exactly.
11932 : return Match_NearMisses;
11933 : }
11934 :
11935 : namespace {
11936 : struct OperandMatchEntry {
11937 : uint64_t RequiredFeatures;
11938 : uint16_t Mnemonic;
11939 : uint16_t Class;
11940 : uint8_t OperandMask;
11941 :
11942 0 : StringRef getMnemonic() const {
11943 0 : return StringRef(MnemonicTable + Mnemonic + 1,
11944 0 : MnemonicTable[Mnemonic]);
11945 : }
11946 : };
11947 :
11948 : // Predicate for searching for an opcode.
11949 : struct LessOpcodeOperand {
11950 0 : bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
11951 0 : return LHS.getMnemonic() < RHS;
11952 : }
11953 0 : bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
11954 0 : return LHS < RHS.getMnemonic();
11955 : }
11956 : bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
11957 : return LHS.getMnemonic() < RHS.getMnemonic();
11958 : }
11959 : };
11960 : } // end anonymous namespace.
11961 :
11962 : static const OperandMatchEntry OperandMatchTable[731] = {
11963 : /* Operand List Mask, Mnemonic, Operand Class, Features */
11964 : { Feature_IsARM, 10 /* adc */, MCK_ModImm, 8 /* 3 */ },
11965 : { Feature_IsARM, 10 /* adc */, MCK_ModImm, 16 /* 4 */ },
11966 : { Feature_IsARM, 14 /* add */, MCK_ModImm, 8 /* 3 */ },
11967 : { Feature_IsARM, 14 /* add */, MCK_ModImm, 16 /* 4 */ },
11968 : { Feature_IsARM, 50 /* and */, MCK_ModImm, 8 /* 3 */ },
11969 : { Feature_IsARM, 50 /* and */, MCK_ModImm, 16 /* 4 */ },
11970 : { Feature_IsThumb2, 60 /* bfc */, MCK_Bitfield, 4 /* 2 */ },
11971 : { Feature_IsARM|Feature_HasV6T2, 60 /* bfc */, MCK_Bitfield, 4 /* 2 */ },
11972 : { Feature_IsThumb2, 64 /* bfi */, MCK_Bitfield, 8 /* 3 */ },
11973 : { Feature_IsARM|Feature_HasV6T2, 64 /* bfi */, MCK_Bitfield, 8 /* 3 */ },
11974 : { Feature_IsARM, 68 /* bic */, MCK_ModImm, 8 /* 3 */ },
11975 : { Feature_IsARM, 68 /* bic */, MCK_ModImm, 16 /* 4 */ },
11976 : { Feature_IsARM|Feature_PreV8, 111 /* cdp */, MCK_CoprocNum, 2 /* 1 */ },
11977 : { Feature_IsARM|Feature_PreV8, 111 /* cdp */, MCK_CoprocReg, 56 /* 3, 4, 5 */ },
11978 : { Feature_IsThumb2|Feature_PreV8, 111 /* cdp */, MCK_CoprocNum, 2 /* 1 */ },
11979 : { Feature_IsThumb2|Feature_PreV8, 111 /* cdp */, MCK_CoprocReg, 56 /* 3, 4, 5 */ },
11980 : { Feature_IsARM|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocNum, 1 /* 0 */ },
11981 : { Feature_IsARM|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocReg, 28 /* 2, 3, 4 */ },
11982 : { Feature_IsThumb2|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocNum, 2 /* 1 */ },
11983 : { Feature_IsThumb2|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocReg, 56 /* 3, 4, 5 */ },
11984 : { Feature_IsARM, 130 /* cmn */, MCK_ModImm, 4 /* 2 */ },
11985 : { Feature_IsARM, 134 /* cmp */, MCK_ModImm, 4 /* 2 */ },
11986 : { Feature_IsARM, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ },
11987 : { Feature_IsThumb, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ },
11988 : { Feature_IsThumb2|Feature_IsNotMClass, 138 /* cps */, MCK_ProcIFlags, 4 /* 2 */ },
11989 : { Feature_IsARM, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ },
11990 : { Feature_IsThumb2|Feature_IsNotMClass, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ },
11991 : { Feature_IsThumb2, 138 /* cps */, MCK_ProcIFlags, 4 /* 2 */ },
11992 : { Feature_IsARM|Feature_HasDB, 218 /* dmb */, MCK_MemBarrierOpt, 1 /* 0 */ },
11993 : { Feature_IsThumb|Feature_HasDB, 218 /* dmb */, MCK_MemBarrierOpt, 2 /* 1 */ },
11994 : { Feature_IsARM|Feature_HasDB, 222 /* dsb */, MCK_MemBarrierOpt, 1 /* 0 */ },
11995 : { Feature_IsThumb|Feature_HasDB, 222 /* dsb */, MCK_MemBarrierOpt, 2 /* 1 */ },
11996 : { Feature_IsARM, 226 /* eor */, MCK_ModImm, 8 /* 3 */ },
11997 : { Feature_IsARM, 226 /* eor */, MCK_ModImm, 16 /* 4 */ },
11998 : { Feature_HasVFP3, 265 /* fconstd */, MCK_FPImm, 4 /* 2 */ },
11999 : { Feature_HasVFP3, 273 /* fconsts */, MCK_FPImm, 4 /* 2 */ },
12000 : { Feature_IsARM|Feature_HasDB, 357 /* isb */, MCK_InstSyncBarrierOpt, 1 /* 0 */ },
12001 : { Feature_IsThumb|Feature_HasDB, 357 /* isb */, MCK_InstSyncBarrierOpt, 2 /* 1 */ },
12002 : { Feature_IsARM, 361 /* it */, MCK_ITCondCode, 2 /* 1 */ },
12003 : { Feature_IsThumb2, 361 /* it */, MCK_ITCondCode, 2 /* 1 */ },
12004 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12005 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12006 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12007 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12008 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12009 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12010 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12011 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12012 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12013 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocOption, 16 /* 4 */ },
12014 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12015 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12016 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocOption, 16 /* 4 */ },
12017 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12018 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12019 : { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12020 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ },
12021 : { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ },
12022 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ },
12023 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ },
12024 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ },
12025 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ },
12026 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ },
12027 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ },
12028 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ },
12029 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocOption, 8 /* 3 */ },
12030 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ },
12031 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ },
12032 : { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ },
12033 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ },
12034 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ },
12035 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ },
12036 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocOption, 16 /* 4 */ },
12037 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ },
12038 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ },
12039 : { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ },
12040 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ },
12041 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ },
12042 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ },
12043 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ },
12044 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ },
12045 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ },
12046 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ },
12047 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocOption, 8 /* 3 */ },
12048 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ },
12049 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ },
12050 : { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ },
12051 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ },
12052 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ },
12053 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ },
12054 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocOption, 16 /* 4 */ },
12055 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ },
12056 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ },
12057 : { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ },
12058 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12059 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12060 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12061 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12062 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12063 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12064 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12065 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12066 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12067 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocOption, 16 /* 4 */ },
12068 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12069 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12070 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocOption, 16 /* 4 */ },
12071 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12072 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12073 : { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12074 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ },
12075 : { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ },
12076 : { Feature_IsARM, 447 /* ldr */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12077 : { Feature_IsARM, 451 /* ldrb */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12078 : { Feature_IsARM, 456 /* ldrbt */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12079 : { Feature_IsARM, 462 /* ldrd */, MCK_AM3Offset, 16 /* 4 */ },
12080 : { Feature_IsARM, 494 /* ldrh */, MCK_AM3Offset, 8 /* 3 */ },
12081 : { Feature_IsARM, 499 /* ldrht */, MCK_PostIdxReg, 8 /* 3 */ },
12082 : { Feature_IsARM, 505 /* ldrsb */, MCK_AM3Offset, 8 /* 3 */ },
12083 : { Feature_IsARM, 511 /* ldrsbt */, MCK_PostIdxReg, 8 /* 3 */ },
12084 : { Feature_IsARM, 518 /* ldrsh */, MCK_AM3Offset, 8 /* 3 */ },
12085 : { Feature_IsARM, 524 /* ldrsht */, MCK_PostIdxReg, 8 /* 3 */ },
12086 : { Feature_IsARM, 531 /* ldrt */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12087 : { Feature_IsARM, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ },
12088 : { Feature_IsARM, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ },
12089 : { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ },
12090 : { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ },
12091 : { Feature_IsARM, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ },
12092 : { Feature_IsARM, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ },
12093 : { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ },
12094 : { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ },
12095 : { Feature_IsARM, 548 /* mcr2 */, MCK_CoprocNum, 1 /* 0 */ },
12096 : { Feature_IsARM, 548 /* mcr2 */, MCK_CoprocReg, 24 /* 3, 4 */ },
12097 : { Feature_IsThumb2, 548 /* mcr2 */, MCK_CoprocNum, 2 /* 1 */ },
12098 : { Feature_IsThumb2, 548 /* mcr2 */, MCK_CoprocReg, 48 /* 4, 5 */ },
12099 : { Feature_IsARM|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocNum, 1 /* 0 */ },
12100 : { Feature_IsARM|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocReg, 24 /* 3, 4 */ },
12101 : { Feature_IsThumb2|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocNum, 2 /* 1 */ },
12102 : { Feature_IsThumb2|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocReg, 48 /* 4, 5 */ },
12103 : { Feature_IsARM, 553 /* mcrr */, MCK_CoprocNum, 2 /* 1 */ },
12104 : { Feature_IsARM, 553 /* mcrr */, MCK_CoprocReg, 32 /* 5 */ },
12105 : { Feature_IsThumb2, 553 /* mcrr */, MCK_CoprocNum, 2 /* 1 */ },
12106 : { Feature_IsThumb2, 553 /* mcrr */, MCK_CoprocReg, 32 /* 5 */ },
12107 : { Feature_IsARM|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocNum, 1 /* 0 */ },
12108 : { Feature_IsARM|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocReg, 16 /* 4 */ },
12109 : { Feature_IsThumb2|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocNum, 2 /* 1 */ },
12110 : { Feature_IsThumb2|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocReg, 32 /* 5 */ },
12111 : { Feature_IsARM, 572 /* mov */, MCK_ModImm, 8 /* 3 */ },
12112 : { Feature_IsARM, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ },
12113 : { Feature_IsARM, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ },
12114 : { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ },
12115 : { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ },
12116 : { Feature_IsARM, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ },
12117 : { Feature_IsARM, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ },
12118 : { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ },
12119 : { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ },
12120 : { Feature_IsARM, 595 /* mrc2 */, MCK_CoprocNum, 1 /* 0 */ },
12121 : { Feature_IsARM, 595 /* mrc2 */, MCK_CoprocReg, 24 /* 3, 4 */ },
12122 : { Feature_IsThumb2, 595 /* mrc2 */, MCK_CoprocNum, 2 /* 1 */ },
12123 : { Feature_IsThumb2, 595 /* mrc2 */, MCK_CoprocReg, 48 /* 4, 5 */ },
12124 : { Feature_IsARM|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocNum, 1 /* 0 */ },
12125 : { Feature_IsARM|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocReg, 24 /* 3, 4 */ },
12126 : { Feature_IsThumb2|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocNum, 2 /* 1 */ },
12127 : { Feature_IsThumb2|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocReg, 48 /* 4, 5 */ },
12128 : { Feature_IsARM, 600 /* mrrc */, MCK_CoprocNum, 2 /* 1 */ },
12129 : { Feature_IsARM, 600 /* mrrc */, MCK_CoprocReg, 32 /* 5 */ },
12130 : { Feature_IsThumb2, 600 /* mrrc */, MCK_CoprocNum, 2 /* 1 */ },
12131 : { Feature_IsThumb2, 600 /* mrrc */, MCK_CoprocReg, 32 /* 5 */ },
12132 : { Feature_IsARM|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocNum, 1 /* 0 */ },
12133 : { Feature_IsARM|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocReg, 16 /* 4 */ },
12134 : { Feature_IsThumb2|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocNum, 2 /* 1 */ },
12135 : { Feature_IsThumb2|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocReg, 32 /* 5 */ },
12136 : { Feature_IsThumb|Feature_HasVirtualization, 611 /* mrs */, MCK_BankedReg, 4 /* 2 */ },
12137 : { Feature_IsThumb|Feature_IsMClass, 611 /* mrs */, MCK_MSRMask, 4 /* 2 */ },
12138 : { Feature_IsARM|Feature_HasVirtualization, 611 /* mrs */, MCK_BankedReg, 4 /* 2 */ },
12139 : { Feature_IsThumb|Feature_HasVirtualization, 615 /* msr */, MCK_BankedReg, 2 /* 1 */ },
12140 : { Feature_IsARM|Feature_HasVirtualization, 615 /* msr */, MCK_BankedReg, 2 /* 1 */ },
12141 : { Feature_IsThumb2|Feature_IsNotMClass, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ },
12142 : { Feature_IsThumb|Feature_IsMClass, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ },
12143 : { Feature_IsARM, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ },
12144 : { Feature_IsARM, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ },
12145 : { Feature_IsARM, 615 /* msr */, MCK_ModImm, 4 /* 2 */ },
12146 : { Feature_IsARM, 623 /* mvn */, MCK_ModImm, 8 /* 3 */ },
12147 : { Feature_IsARM, 639 /* orr */, MCK_ModImm, 8 /* 3 */ },
12148 : { Feature_IsARM, 639 /* orr */, MCK_ModImm, 16 /* 4 */ },
12149 : { Feature_HasDSP|Feature_IsThumb2, 643 /* pkhbt */, MCK_PKHLSLImm, 16 /* 4 */ },
12150 : { Feature_IsARM|Feature_HasV6, 643 /* pkhbt */, MCK_PKHLSLImm, 16 /* 4 */ },
12151 : { Feature_HasDSP|Feature_IsThumb2, 649 /* pkhtb */, MCK_PKHASRImm, 16 /* 4 */ },
12152 : { Feature_IsARM|Feature_HasV6, 649 /* pkhtb */, MCK_PKHASRImm, 16 /* 4 */ },
12153 : { Feature_IsARM, 794 /* rsb */, MCK_ModImm, 8 /* 3 */ },
12154 : { Feature_IsARM, 794 /* rsb */, MCK_ModImm, 16 /* 4 */ },
12155 : { Feature_IsARM, 798 /* rsc */, MCK_ModImm, 8 /* 3 */ },
12156 : { Feature_IsARM, 798 /* rsc */, MCK_ModImm, 16 /* 4 */ },
12157 : { Feature_IsARM, 823 /* sbc */, MCK_ModImm, 8 /* 3 */ },
12158 : { Feature_IsARM, 823 /* sbc */, MCK_ModImm, 16 /* 4 */ },
12159 : { Feature_IsThumb|Feature_IsNotMClass, 841 /* setend */, MCK_SetEndImm, 1 /* 0 */ },
12160 : { Feature_IsARM, 841 /* setend */, MCK_SetEndImm, 1 /* 0 */ },
12161 : { Feature_IsThumb2, 1263 /* ssat */, MCK_ShifterImm, 16 /* 4 */ },
12162 : { Feature_IsARM|Feature_HasV6, 1263 /* ssat */, MCK_ShifterImm, 16 /* 4 */ },
12163 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12164 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12165 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12166 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12167 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12168 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12169 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12170 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12171 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12172 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocOption, 16 /* 4 */ },
12173 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12174 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12175 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocOption, 16 /* 4 */ },
12176 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12177 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12178 : { Feature_IsARM, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12179 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocNum, 2 /* 1 */ },
12180 : { Feature_IsThumb2, 1298 /* stc */, MCK_CoprocReg, 4 /* 2 */ },
12181 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ },
12182 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ },
12183 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ },
12184 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ },
12185 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ },
12186 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ },
12187 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ },
12188 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocOption, 8 /* 3 */ },
12189 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ },
12190 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ },
12191 : { Feature_IsARM|Feature_PreV8, 1302 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ },
12192 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ },
12193 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ },
12194 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ },
12195 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocOption, 16 /* 4 */ },
12196 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ },
12197 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ },
12198 : { Feature_PreV8|Feature_IsThumb2, 1302 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ },
12199 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ },
12200 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ },
12201 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ },
12202 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ },
12203 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ },
12204 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ },
12205 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ },
12206 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocOption, 8 /* 3 */ },
12207 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ },
12208 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ },
12209 : { Feature_IsARM|Feature_PreV8, 1307 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ },
12210 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ },
12211 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ },
12212 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ },
12213 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocOption, 16 /* 4 */ },
12214 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ },
12215 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ },
12216 : { Feature_PreV8|Feature_IsThumb2, 1307 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ },
12217 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12218 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12219 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12220 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12221 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12222 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12223 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12224 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12225 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12226 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocOption, 16 /* 4 */ },
12227 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12228 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12229 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocOption, 16 /* 4 */ },
12230 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12231 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12232 : { Feature_IsARM, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12233 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocNum, 2 /* 1 */ },
12234 : { Feature_IsThumb2, 1313 /* stcl */, MCK_CoprocReg, 4 /* 2 */ },
12235 : { Feature_IsARM, 1381 /* str */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12236 : { Feature_IsARM, 1385 /* strb */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12237 : { Feature_IsARM, 1390 /* strbt */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12238 : { Feature_IsARM, 1396 /* strd */, MCK_AM3Offset, 16 /* 4 */ },
12239 : { Feature_IsARM, 1428 /* strh */, MCK_AM3Offset, 8 /* 3 */ },
12240 : { Feature_IsARM, 1433 /* strht */, MCK_PostIdxReg, 8 /* 3 */ },
12241 : { Feature_IsARM, 1439 /* strt */, MCK_PostIdxRegShifted, 8 /* 3 */ },
12242 : { Feature_IsARM, 1444 /* sub */, MCK_ModImm, 8 /* 3 */ },
12243 : { Feature_IsARM, 1444 /* sub */, MCK_ModImm, 16 /* 4 */ },
12244 : { Feature_HasDSP|Feature_IsThumb2, 1471 /* sxtab */, MCK_RotImm, 16 /* 4 */ },
12245 : { Feature_IsARM|Feature_HasV6, 1471 /* sxtab */, MCK_RotImm, 16 /* 4 */ },
12246 : { Feature_HasDSP|Feature_IsThumb2, 1477 /* sxtab16 */, MCK_RotImm, 16 /* 4 */ },
12247 : { Feature_IsARM|Feature_HasV6, 1477 /* sxtab16 */, MCK_RotImm, 16 /* 4 */ },
12248 : { Feature_HasDSP|Feature_IsThumb2, 1485 /* sxtah */, MCK_RotImm, 16 /* 4 */ },
12249 : { Feature_IsARM|Feature_HasV6, 1485 /* sxtah */, MCK_RotImm, 16 /* 4 */ },
12250 : { Feature_IsThumb2, 1491 /* sxtb */, MCK_RotImm, 8 /* 3 */ },
12251 : { Feature_IsARM|Feature_HasV6, 1491 /* sxtb */, MCK_RotImm, 8 /* 3 */ },
12252 : { Feature_IsThumb2, 1491 /* sxtb */, MCK_RotImm, 16 /* 4 */ },
12253 : { Feature_HasDSP|Feature_IsThumb2, 1496 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ },
12254 : { Feature_HasDSP|Feature_IsThumb2, 1496 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ },
12255 : { Feature_IsARM|Feature_HasV6, 1496 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ },
12256 : { Feature_IsThumb2, 1503 /* sxth */, MCK_RotImm, 8 /* 3 */ },
12257 : { Feature_IsARM|Feature_HasV6, 1503 /* sxth */, MCK_RotImm, 8 /* 3 */ },
12258 : { Feature_IsThumb2, 1503 /* sxth */, MCK_RotImm, 16 /* 4 */ },
12259 : { Feature_IsARM, 1516 /* teq */, MCK_ModImm, 4 /* 2 */ },
12260 : { Feature_IsARM|Feature_HasV8_4a, 1525 /* tsb */, MCK_TraceSyncBarrierOpt, 1 /* 0 */ },
12261 : { Feature_IsThumb|Feature_HasV8_4a, 1525 /* tsb */, MCK_TraceSyncBarrierOpt, 2 /* 1 */ },
12262 : { Feature_IsARM, 1529 /* tst */, MCK_ModImm, 4 /* 2 */ },
12263 : { Feature_IsThumb2, 1696 /* usat */, MCK_ShifterImm, 16 /* 4 */ },
12264 : { Feature_IsARM|Feature_HasV6, 1696 /* usat */, MCK_ShifterImm, 16 /* 4 */ },
12265 : { Feature_HasDSP|Feature_IsThumb2, 1726 /* uxtab */, MCK_RotImm, 16 /* 4 */ },
12266 : { Feature_IsARM|Feature_HasV6, 1726 /* uxtab */, MCK_RotImm, 16 /* 4 */ },
12267 : { Feature_HasDSP|Feature_IsThumb2, 1732 /* uxtab16 */, MCK_RotImm, 16 /* 4 */ },
12268 : { Feature_IsARM|Feature_HasV6, 1732 /* uxtab16 */, MCK_RotImm, 16 /* 4 */ },
12269 : { Feature_HasDSP|Feature_IsThumb2, 1740 /* uxtah */, MCK_RotImm, 16 /* 4 */ },
12270 : { Feature_IsARM|Feature_HasV6, 1740 /* uxtah */, MCK_RotImm, 16 /* 4 */ },
12271 : { Feature_IsThumb2, 1746 /* uxtb */, MCK_RotImm, 8 /* 3 */ },
12272 : { Feature_IsARM|Feature_HasV6, 1746 /* uxtb */, MCK_RotImm, 8 /* 3 */ },
12273 : { Feature_IsThumb2, 1746 /* uxtb */, MCK_RotImm, 16 /* 4 */ },
12274 : { Feature_HasDSP|Feature_IsThumb2, 1751 /* uxtb16 */, MCK_RotImm, 8 /* 3 */ },
12275 : { Feature_HasDSP|Feature_IsThumb2, 1751 /* uxtb16 */, MCK_RotImm, 8 /* 3 */ },
12276 : { Feature_IsARM|Feature_HasV6, 1751 /* uxtb16 */, MCK_RotImm, 8 /* 3 */ },
12277 : { Feature_IsThumb2, 1758 /* uxth */, MCK_RotImm, 8 /* 3 */ },
12278 : { Feature_IsARM|Feature_HasV6, 1758 /* uxth */, MCK_RotImm, 8 /* 3 */ },
12279 : { Feature_IsThumb2, 1758 /* uxth */, MCK_RotImm, 16 /* 4 */ },
12280 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12281 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12282 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12283 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12284 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12285 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ },
12286 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12287 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12288 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12289 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12290 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12291 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12292 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ },
12293 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12294 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12295 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12296 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12297 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12298 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12299 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12300 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12301 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12302 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12303 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ },
12304 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12305 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12306 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12307 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12308 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12309 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12310 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12311 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12312 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12313 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12314 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12315 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ },
12316 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ },
12317 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12318 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12319 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12320 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12321 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12322 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12323 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12324 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12325 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12326 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12327 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12328 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12329 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ },
12330 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ },
12331 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12332 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12333 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12334 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12335 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12336 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12337 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12338 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12339 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12340 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12341 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12342 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12343 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12344 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ },
12345 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12346 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ },
12347 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12348 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ },
12349 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12350 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ },
12351 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ },
12352 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ },
12353 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12354 : { Feature_HasNEON, 2050 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ },
12355 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12356 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12357 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12358 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12359 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12360 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ },
12361 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ },
12362 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12363 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12364 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12365 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12366 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12367 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ },
12368 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ },
12369 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12370 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12371 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12372 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12373 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12374 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ },
12375 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12376 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12377 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12378 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12379 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12380 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12381 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12382 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12383 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12384 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12385 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ },
12386 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ },
12387 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ },
12388 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ },
12389 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12390 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12391 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12392 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12393 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12394 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12395 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12396 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12397 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12398 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12399 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ },
12400 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ },
12401 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ },
12402 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ },
12403 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12404 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ },
12405 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12406 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ },
12407 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12408 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ },
12409 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12410 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12411 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12412 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ },
12413 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ },
12414 : { Feature_HasNEON, 2055 /* vld2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ },
12415 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12416 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12417 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ },
12418 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12419 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12420 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ },
12421 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12422 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12423 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ },
12424 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12425 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12426 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ },
12427 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12428 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12429 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ },
12430 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12431 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12432 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12433 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12434 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12435 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12436 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ },
12437 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ },
12438 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12439 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12440 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12441 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12442 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ },
12443 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ },
12444 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12445 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12446 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12447 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12448 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ },
12449 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ },
12450 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12451 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12452 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12453 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12454 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ },
12455 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ },
12456 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12457 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ },
12458 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12459 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ },
12460 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ },
12461 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ },
12462 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12463 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ },
12464 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12465 : { Feature_HasNEON, 2060 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12466 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12467 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12468 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ },
12469 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12470 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12471 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ },
12472 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12473 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12474 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ },
12475 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12476 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12477 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ },
12478 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12479 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12480 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ },
12481 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12482 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12483 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12484 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12485 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12486 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12487 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ },
12488 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ },
12489 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12490 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12491 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12492 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12493 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ },
12494 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ },
12495 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12496 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12497 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12498 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12499 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ },
12500 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ },
12501 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12502 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12503 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12504 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12505 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ },
12506 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ },
12507 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12508 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ },
12509 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12510 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ },
12511 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ },
12512 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ },
12513 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12514 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ },
12515 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12516 : { Feature_HasNEON, 2065 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ },
12517 : { Feature_HasNEON, 2147 /* vmov */, MCK_FPImm, 8 /* 3 */ },
12518 : { Feature_HasNEON, 2147 /* vmov */, MCK_FPImm, 8 /* 3 */ },
12519 : { Feature_HasVFP3, 2147 /* vmov */, MCK_FPImm, 8 /* 3 */ },
12520 : { Feature_HasVFP3|Feature_HasDPVFP, 2147 /* vmov */, MCK_FPImm, 8 /* 3 */ },
12521 : { Feature_HasFullFP16, 2147 /* vmov */, MCK_FPImm, 8 /* 3 */ },
12522 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12523 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12524 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12525 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ },
12526 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12527 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12528 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12529 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12530 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ },
12531 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12532 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12533 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12534 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12535 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12536 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12537 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12538 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12539 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ },
12540 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12541 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12542 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12543 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12544 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12545 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12546 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12547 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ },
12548 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ },
12549 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12550 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12551 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12552 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12553 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12554 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12555 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12556 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12557 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ },
12558 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ },
12559 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12560 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12561 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12562 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12563 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12564 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12565 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12566 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12567 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12568 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12569 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12570 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ },
12571 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12572 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ },
12573 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12574 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ },
12575 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ },
12576 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ },
12577 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12578 : { Feature_HasNEON, 2647 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ },
12579 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12580 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12581 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12582 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ },
12583 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ },
12584 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12585 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12586 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12587 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ },
12588 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ },
12589 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12590 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12591 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12592 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ },
12593 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12594 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12595 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12596 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12597 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12598 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12599 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ },
12600 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ },
12601 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ },
12602 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ },
12603 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12604 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12605 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12606 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12607 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12608 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12609 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ },
12610 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ },
12611 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ },
12612 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ },
12613 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12614 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ },
12615 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12616 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ },
12617 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12618 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ },
12619 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ },
12620 : { Feature_HasNEON, 2652 /* vst2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ },
12621 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12622 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ },
12623 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12624 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ },
12625 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12626 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ },
12627 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12628 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ },
12629 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12630 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ },
12631 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12632 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12633 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12634 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ },
12635 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ },
12636 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12637 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12638 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ },
12639 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ },
12640 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12641 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12642 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ },
12643 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ },
12644 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12645 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12646 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ },
12647 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ },
12648 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12649 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ },
12650 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ },
12651 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ },
12652 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12653 : { Feature_HasNEON, 2657 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ },
12654 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12655 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ },
12656 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12657 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ },
12658 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12659 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ },
12660 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12661 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ },
12662 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12663 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ },
12664 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12665 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12666 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12667 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ },
12668 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ },
12669 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12670 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12671 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ },
12672 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ },
12673 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12674 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12675 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ },
12676 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ },
12677 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12678 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12679 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ },
12680 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ },
12681 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12682 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ },
12683 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ },
12684 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ },
12685 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12686 : { Feature_HasNEON, 2662 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ },
12687 : { Feature_HasNEON, 2715 /* vtbl */, MCK_VecListDPair, 8 /* 3 */ },
12688 : { Feature_HasNEON, 2715 /* vtbl */, MCK_VecListFourD, 8 /* 3 */ },
12689 : { Feature_HasNEON, 2715 /* vtbl */, MCK_VecListOneD, 8 /* 3 */ },
12690 : { Feature_HasNEON, 2715 /* vtbl */, MCK_VecListThreeD, 8 /* 3 */ },
12691 : { Feature_HasNEON, 2720 /* vtbx */, MCK_VecListDPair, 8 /* 3 */ },
12692 : { Feature_HasNEON, 2720 /* vtbx */, MCK_VecListFourD, 8 /* 3 */ },
12693 : { Feature_HasNEON, 2720 /* vtbx */, MCK_VecListOneD, 8 /* 3 */ },
12694 : { Feature_HasNEON, 2720 /* vtbx */, MCK_VecListThreeD, 8 /* 3 */ },
12695 : };
12696 :
12697 13219 : OperandMatchResultTy ARMAsmParser::
12698 : tryCustomParseOperand(OperandVector &Operands,
12699 : unsigned MCK) {
12700 :
12701 13219 : switch(MCK) {
12702 53 : case MCK_AM3Offset:
12703 53 : return parseAM3Offset(Operands);
12704 136 : case MCK_BankedReg:
12705 136 : return parseBankedRegOperand(Operands);
12706 34 : case MCK_Bitfield:
12707 34 : return parseBitfield(Operands);
12708 892 : case MCK_CoprocNum:
12709 892 : return parseCoprocNumOperand(Operands);
12710 288 : case MCK_CoprocOption:
12711 288 : return parseCoprocOptionOperand(Operands);
12712 1021 : case MCK_CoprocReg:
12713 1021 : return parseCoprocRegOperand(Operands);
12714 566 : case MCK_FPImm:
12715 566 : return parseFPImm(Operands);
12716 30 : case MCK_InstSyncBarrierOpt:
12717 30 : return parseInstSyncBarrierOptOperand(Operands);
12718 249 : case MCK_MSRMask:
12719 249 : return parseMSRMaskOperand(Operands);
12720 280 : case MCK_MemBarrierOpt:
12721 280 : return parseMemBarrierOptOperand(Operands);
12722 3539 : case MCK_ModImm:
12723 3539 : return parseModImm(Operands);
12724 : case MCK_PKHASRImm:
12725 14 : return parsePKHASRImm(Operands);
12726 : case MCK_PKHLSLImm:
12727 22 : return parsePKHLSLImm(Operands);
12728 28 : case MCK_PostIdxReg:
12729 28 : return parsePostIdxReg(Operands);
12730 71 : case MCK_PostIdxRegShifted:
12731 71 : return parsePostIdxReg(Operands);
12732 69 : case MCK_ProcIFlags:
12733 69 : return parseProcIFlagsOperand(Operands);
12734 244 : case MCK_RotImm:
12735 244 : return parseRotImm(Operands);
12736 26 : case MCK_SetEndImm:
12737 26 : return parseSetEndImm(Operands);
12738 50 : case MCK_ShifterImm:
12739 50 : return parseShifterImm(Operands);
12740 8 : case MCK_TraceSyncBarrierOpt:
12741 8 : return parseTraceSyncBarrierOptOperand(Operands);
12742 960 : case MCK_VecListDPairAllLanes:
12743 960 : return parseVectorList(Operands);
12744 594 : case MCK_VecListDPair:
12745 594 : return parseVectorList(Operands);
12746 0 : case MCK_VecListDPairSpacedAllLanes:
12747 0 : return parseVectorList(Operands);
12748 0 : case MCK_VecListDPairSpaced:
12749 0 : return parseVectorList(Operands);
12750 371 : case MCK_VecListFourDAllLanes:
12751 371 : return parseVectorList(Operands);
12752 274 : case MCK_VecListFourD:
12753 274 : return parseVectorList(Operands);
12754 0 : case MCK_VecListFourDByteIndexed:
12755 0 : return parseVectorList(Operands);
12756 0 : case MCK_VecListFourDHWordIndexed:
12757 0 : return parseVectorList(Operands);
12758 0 : case MCK_VecListFourDWordIndexed:
12759 0 : return parseVectorList(Operands);
12760 0 : case MCK_VecListFourQAllLanes:
12761 0 : return parseVectorList(Operands);
12762 0 : case MCK_VecListFourQ:
12763 0 : return parseVectorList(Operands);
12764 0 : case MCK_VecListFourQHWordIndexed:
12765 0 : return parseVectorList(Operands);
12766 0 : case MCK_VecListFourQWordIndexed:
12767 0 : return parseVectorList(Operands);
12768 0 : case MCK_VecListOneDAllLanes:
12769 0 : return parseVectorList(Operands);
12770 0 : case MCK_VecListOneD:
12771 0 : return parseVectorList(Operands);
12772 0 : case MCK_VecListOneDByteIndexed:
12773 0 : return parseVectorList(Operands);
12774 0 : case MCK_VecListOneDHWordIndexed:
12775 0 : return parseVectorList(Operands);
12776 0 : case MCK_VecListOneDWordIndexed:
12777 0 : return parseVectorList(Operands);
12778 371 : case MCK_VecListThreeDAllLanes:
12779 371 : return parseVectorList(Operands);
12780 245 : case MCK_VecListThreeD:
12781 245 : return parseVectorList(Operands);
12782 0 : case MCK_VecListThreeDByteIndexed:
12783 0 : return parseVectorList(Operands);
12784 0 : case MCK_VecListThreeDHWordIndexed:
12785 0 : return parseVectorList(Operands);
12786 0 : case MCK_VecListThreeDWordIndexed:
12787 0 : return parseVectorList(Operands);
12788 0 : case MCK_VecListThreeQAllLanes:
12789 0 : return parseVectorList(Operands);
12790 0 : case MCK_VecListThreeQ:
12791 0 : return parseVectorList(Operands);
12792 0 : case MCK_VecListThreeQHWordIndexed:
12793 0 : return parseVectorList(Operands);
12794 0 : case MCK_VecListThreeQWordIndexed:
12795 0 : return parseVectorList(Operands);
12796 0 : case MCK_VecListTwoDByteIndexed:
12797 0 : return parseVectorList(Operands);
12798 0 : case MCK_VecListTwoDHWordIndexed:
12799 0 : return parseVectorList(Operands);
12800 0 : case MCK_VecListTwoDWordIndexed:
12801 0 : return parseVectorList(Operands);
12802 0 : case MCK_VecListTwoQHWordIndexed:
12803 0 : return parseVectorList(Operands);
12804 0 : case MCK_VecListTwoQWordIndexed:
12805 0 : return parseVectorList(Operands);
12806 2784 : case MCK_ITCondCode:
12807 2784 : return parseITCondCode(Operands);
12808 : default:
12809 : return MatchOperand_NoMatch;
12810 : }
12811 : return MatchOperand_NoMatch;
12812 : }
12813 :
12814 57970 : OperandMatchResultTy ARMAsmParser::
12815 : MatchOperandParserImpl(OperandVector &Operands,
12816 : StringRef Mnemonic,
12817 : bool ParseForAllFeatures) {
12818 : // Get the current feature set.
12819 57970 : uint64_t AvailableFeatures = getAvailableFeatures();
12820 :
12821 : // Get the next operand index.
12822 57970 : unsigned NextOpNum = Operands.size() - 1;
12823 : // Search the table.
12824 : auto MnemonicRange =
12825 : std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
12826 : Mnemonic, LessOpcodeOperand());
12827 :
12828 57970 : if (MnemonicRange.first == MnemonicRange.second)
12829 : return MatchOperand_NoMatch;
12830 :
12831 262220 : for (const OperandMatchEntry *it = MnemonicRange.first,
12832 295680 : *ie = MnemonicRange.second; it != ie; ++it) {
12833 : // equal_range guarantees that instruction mnemonic matches.
12834 : assert(Mnemonic == it->getMnemonic());
12835 :
12836 : // check if the available features match
12837 272273 : if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures)
12838 : continue;
12839 :
12840 : // check if the operand in question has a custom parser.
12841 234225 : if (!(it->OperandMask & (1 << NextOpNum)))
12842 : continue;
12843 :
12844 : // call custom parse method to handle the operand
12845 13219 : OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
12846 13219 : if (Result != MatchOperand_NoMatch)
12847 10053 : return Result;
12848 : }
12849 :
12850 : // Okay, we had no match.
12851 : return MatchOperand_NoMatch;
12852 : }
12853 :
12854 : #endif // GET_MATCHER_IMPLEMENTATION
12855 :
12856 :
12857 : #ifdef GET_MNEMONIC_SPELL_CHECKER
12858 : #undef GET_MNEMONIC_SPELL_CHECKER
12859 :
12860 26 : static std::string ARMMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {
12861 : const unsigned MaxEditDist = 2;
12862 : std::vector<StringRef> Candidates;
12863 : StringRef Prev = "";
12864 :
12865 : // Find the appropriate table for this asm variant.
12866 : const MatchEntry *Start, *End;
12867 26 : switch (VariantID) {
12868 0 : default: llvm_unreachable("invalid variant!");
12869 : case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
12870 : }
12871 :
12872 99892 : for (auto I = Start; I < End; I++) {
12873 : // Ignore unsupported instructions.
12874 99866 : if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)
12875 94167 : continue;
12876 :
12877 15307 : StringRef T = I->getMnemonic();
12878 : // Avoid recomputing the edit distance for the same string.
12879 : if (T.equals(Prev))
12880 : continue;
12881 :
12882 : Prev = T;
12883 5699 : unsigned Dist = S.edit_distance(T, false, MaxEditDist);
12884 5699 : if (Dist <= MaxEditDist)
12885 44 : Candidates.push_back(T);
12886 : }
12887 :
12888 26 : if (Candidates.empty())
12889 8 : return "";
12890 :
12891 18 : std::string Res = ", did you mean: ";
12892 : unsigned i = 0;
12893 88 : for( ; i < Candidates.size() - 1; i++)
12894 78 : Res += Candidates[i].str() + ", ";
12895 54 : return Res + Candidates[i].str() + "?";
12896 : }
12897 :
12898 : #endif // GET_MNEMONIC_SPELL_CHECKER
12899 :
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