Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* "Fast" Instruction Selector for the ARM target *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : // FastEmit Immediate Predicate functions.
11 : static bool Predicate_mod_imm(int64_t Imm) {
12 :
13 504 : return ARM_AM::getSOImmVal(Imm) != -1;
14 :
15 : }
16 : static bool Predicate_imm0_65535(int64_t Imm) {
17 :
18 : return Imm >= 0 && Imm < 65536;
19 :
20 : }
21 : static bool Predicate_imm0_7(int64_t Imm) {
22 :
23 : return Imm >= 0 && Imm < 8;
24 :
25 : }
26 : static bool Predicate_imm8_255(int64_t Imm) {
27 :
28 462 : return Imm >= 8 && Imm < 256;
29 :
30 : }
31 : static bool Predicate_imm0_255(int64_t Imm) {
32 : return Imm >= 0 && Imm < 256;
33 : }
34 : static bool Predicate_t2_so_imm(int64_t Imm) {
35 :
36 462 : return ARM_AM::getT2SOImmVal(Imm) != -1;
37 :
38 : }
39 : static bool Predicate_imm0_4095(int64_t Imm) {
40 :
41 : return Imm >= 0 && Imm < 4096;
42 :
43 : }
44 : static bool Predicate_imm1_31(int64_t Imm) {
45 45 : return Imm > 0 && Imm < 32;
46 : }
47 : static bool Predicate_imm0_31(int64_t Imm) {
48 :
49 : return Imm >= 0 && Imm < 32;
50 :
51 : }
52 : static bool Predicate_shr_imm8(int64_t Imm) {
53 39 : return Imm > 0 && Imm <= 8;
54 : }
55 : static bool Predicate_shr_imm16(int64_t Imm) {
56 39 : return Imm > 0 && Imm <= 16;
57 : }
58 : static bool Predicate_shr_imm32(int64_t Imm) {
59 39 : return Imm > 0 && Imm <= 32;
60 : }
61 : static bool Predicate_VectorIndex32(int64_t Imm) {
62 :
63 : return ((uint64_t)Imm) < 2;
64 :
65 : }
66 : static bool Predicate_t2_so_imm_neg(int64_t Imm) {
67 :
68 : return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
69 :
70 : }
71 :
72 :
73 : // FastEmit functions for ARMISD::CALL.
74 :
75 0 : unsigned fastEmit_ARMISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
76 0 : if (RetVT.SimpleTy != MVT::isVoid)
77 : return 0;
78 0 : if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
79 0 : return fastEmitInst_r(ARM::BLX, &ARM::GPRRegClass, Op0, Op0IsKill);
80 : }
81 : return 0;
82 : }
83 :
84 : unsigned fastEmit_ARMISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
85 0 : switch (VT.SimpleTy) {
86 0 : case MVT::i32: return fastEmit_ARMISD_CALL_MVT_i32_r(RetVT, Op0, Op0IsKill);
87 : default: return 0;
88 : }
89 : }
90 :
91 : // FastEmit functions for ARMISD::CALL_NOLINK.
92 :
93 0 : unsigned fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
94 0 : if (RetVT.SimpleTy != MVT::isVoid)
95 : return 0;
96 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
97 0 : return fastEmitInst_r(ARM::tBX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
98 : }
99 0 : if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
100 0 : return fastEmitInst_r(ARM::BMOVPCRX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
101 : }
102 0 : if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
103 0 : return fastEmitInst_r(ARM::BX_CALL, &ARM::tGPRRegClass, Op0, Op0IsKill);
104 : }
105 : return 0;
106 : }
107 :
108 : unsigned fastEmit_ARMISD_CALL_NOLINK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
109 0 : switch (VT.SimpleTy) {
110 0 : case MVT::i32: return fastEmit_ARMISD_CALL_NOLINK_MVT_i32_r(RetVT, Op0, Op0IsKill);
111 : default: return 0;
112 : }
113 : }
114 :
115 : // FastEmit functions for ARMISD::CALL_PRED.
116 :
117 0 : unsigned fastEmit_ARMISD_CALL_PRED_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
118 0 : if (RetVT.SimpleTy != MVT::isVoid)
119 : return 0;
120 0 : if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
121 0 : return fastEmitInst_r(ARM::BLX_pred, &ARM::GPRRegClass, Op0, Op0IsKill);
122 : }
123 : return 0;
124 : }
125 :
126 : unsigned fastEmit_ARMISD_CALL_PRED_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
127 0 : switch (VT.SimpleTy) {
128 0 : case MVT::i32: return fastEmit_ARMISD_CALL_PRED_MVT_i32_r(RetVT, Op0, Op0IsKill);
129 : default: return 0;
130 : }
131 : }
132 :
133 : // FastEmit functions for ARMISD::RRX.
134 :
135 0 : unsigned fastEmit_ARMISD_RRX_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
136 0 : if (RetVT.SimpleTy != MVT::i32)
137 : return 0;
138 0 : if ((Subtarget->isThumb2())) {
139 0 : return fastEmitInst_r(ARM::t2RRX, &ARM::rGPRRegClass, Op0, Op0IsKill);
140 : }
141 0 : if ((!Subtarget->isThumb())) {
142 0 : return fastEmitInst_r(ARM::RRX, &ARM::GPRRegClass, Op0, Op0IsKill);
143 : }
144 : return 0;
145 : }
146 :
147 : unsigned fastEmit_ARMISD_RRX_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
148 0 : switch (VT.SimpleTy) {
149 0 : case MVT::i32: return fastEmit_ARMISD_RRX_MVT_i32_r(RetVT, Op0, Op0IsKill);
150 : default: return 0;
151 : }
152 : }
153 :
154 : // FastEmit functions for ARMISD::SRA_FLAG.
155 :
156 0 : unsigned fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
157 0 : if (RetVT.SimpleTy != MVT::i32)
158 : return 0;
159 0 : if ((Subtarget->isThumb2())) {
160 0 : return fastEmitInst_r(ARM::t2MOVsra_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
161 : }
162 0 : if ((!Subtarget->isThumb())) {
163 0 : return fastEmitInst_r(ARM::MOVsra_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
164 : }
165 : return 0;
166 : }
167 :
168 : unsigned fastEmit_ARMISD_SRA_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
169 0 : switch (VT.SimpleTy) {
170 0 : case MVT::i32: return fastEmit_ARMISD_SRA_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
171 : default: return 0;
172 : }
173 : }
174 :
175 : // FastEmit functions for ARMISD::SRL_FLAG.
176 :
177 0 : unsigned fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
178 0 : if (RetVT.SimpleTy != MVT::i32)
179 : return 0;
180 0 : if ((Subtarget->isThumb2())) {
181 0 : return fastEmitInst_r(ARM::t2MOVsrl_flag, &ARM::rGPRRegClass, Op0, Op0IsKill);
182 : }
183 0 : if ((!Subtarget->isThumb())) {
184 0 : return fastEmitInst_r(ARM::MOVsrl_flag, &ARM::GPRRegClass, Op0, Op0IsKill);
185 : }
186 : return 0;
187 : }
188 :
189 : unsigned fastEmit_ARMISD_SRL_FLAG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
190 0 : switch (VT.SimpleTy) {
191 0 : case MVT::i32: return fastEmit_ARMISD_SRL_FLAG_MVT_i32_r(RetVT, Op0, Op0IsKill);
192 : default: return 0;
193 : }
194 : }
195 :
196 : // FastEmit functions for ARMISD::TC_RETURN.
197 :
198 : unsigned fastEmit_ARMISD_TC_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
199 0 : if (RetVT.SimpleTy != MVT::isVoid)
200 : return 0;
201 0 : return fastEmitInst_r(ARM::TCRETURNri, &ARM::tcGPRRegClass, Op0, Op0IsKill);
202 : }
203 :
204 : unsigned fastEmit_ARMISD_TC_RETURN_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
205 0 : switch (VT.SimpleTy) {
206 0 : case MVT::i32: return fastEmit_ARMISD_TC_RETURN_MVT_i32_r(RetVT, Op0, Op0IsKill);
207 : default: return 0;
208 : }
209 : }
210 :
211 : // FastEmit functions for ARMISD::VCEQZ.
212 :
213 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
214 0 : if (RetVT.SimpleTy != MVT::v8i8)
215 : return 0;
216 0 : if ((Subtarget->hasNEON())) {
217 0 : return fastEmitInst_r(ARM::VCEQzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
218 : }
219 : return 0;
220 : }
221 :
222 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
223 0 : if (RetVT.SimpleTy != MVT::v16i8)
224 : return 0;
225 0 : if ((Subtarget->hasNEON())) {
226 0 : return fastEmitInst_r(ARM::VCEQzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
227 : }
228 : return 0;
229 : }
230 :
231 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
232 0 : if (RetVT.SimpleTy != MVT::v4i16)
233 : return 0;
234 0 : if ((Subtarget->hasNEON())) {
235 0 : return fastEmitInst_r(ARM::VCEQzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
236 : }
237 : return 0;
238 : }
239 :
240 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
241 0 : if (RetVT.SimpleTy != MVT::v8i16)
242 : return 0;
243 0 : if ((Subtarget->hasNEON())) {
244 0 : return fastEmitInst_r(ARM::VCEQzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
245 : }
246 : return 0;
247 : }
248 :
249 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
250 0 : if (RetVT.SimpleTy != MVT::v2i32)
251 : return 0;
252 0 : if ((Subtarget->hasNEON())) {
253 0 : return fastEmitInst_r(ARM::VCEQzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
254 : }
255 : return 0;
256 : }
257 :
258 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
259 0 : if (RetVT.SimpleTy != MVT::v4i32)
260 : return 0;
261 0 : if ((Subtarget->hasNEON())) {
262 0 : return fastEmitInst_r(ARM::VCEQzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
263 : }
264 : return 0;
265 : }
266 :
267 0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
268 0 : if (RetVT.SimpleTy != MVT::v4i16)
269 : return 0;
270 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
271 0 : return fastEmitInst_r(ARM::VCEQzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
272 : }
273 : return 0;
274 : }
275 :
276 0 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
277 0 : if (RetVT.SimpleTy != MVT::v8i16)
278 : return 0;
279 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
280 0 : return fastEmitInst_r(ARM::VCEQzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
281 : }
282 : return 0;
283 : }
284 :
285 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
286 0 : if (RetVT.SimpleTy != MVT::v2i32)
287 : return 0;
288 0 : if ((Subtarget->hasNEON())) {
289 0 : return fastEmitInst_r(ARM::VCEQzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
290 : }
291 : return 0;
292 : }
293 :
294 : unsigned fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
295 0 : if (RetVT.SimpleTy != MVT::v4i32)
296 : return 0;
297 0 : if ((Subtarget->hasNEON())) {
298 0 : return fastEmitInst_r(ARM::VCEQzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
299 : }
300 : return 0;
301 : }
302 :
303 0 : unsigned fastEmit_ARMISD_VCEQZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
304 0 : switch (VT.SimpleTy) {
305 0 : case MVT::v8i8: return fastEmit_ARMISD_VCEQZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
306 0 : case MVT::v16i8: return fastEmit_ARMISD_VCEQZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
307 0 : case MVT::v4i16: return fastEmit_ARMISD_VCEQZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
308 0 : case MVT::v8i16: return fastEmit_ARMISD_VCEQZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
309 0 : case MVT::v2i32: return fastEmit_ARMISD_VCEQZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
310 0 : case MVT::v4i32: return fastEmit_ARMISD_VCEQZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
311 0 : case MVT::v4f16: return fastEmit_ARMISD_VCEQZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
312 0 : case MVT::v8f16: return fastEmit_ARMISD_VCEQZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
313 0 : case MVT::v2f32: return fastEmit_ARMISD_VCEQZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
314 0 : case MVT::v4f32: return fastEmit_ARMISD_VCEQZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
315 : default: return 0;
316 : }
317 : }
318 :
319 : // FastEmit functions for ARMISD::VCGEZ.
320 :
321 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
322 0 : if (RetVT.SimpleTy != MVT::v8i8)
323 : return 0;
324 0 : if ((Subtarget->hasNEON())) {
325 0 : return fastEmitInst_r(ARM::VCGEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
326 : }
327 : return 0;
328 : }
329 :
330 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
331 0 : if (RetVT.SimpleTy != MVT::v16i8)
332 : return 0;
333 0 : if ((Subtarget->hasNEON())) {
334 0 : return fastEmitInst_r(ARM::VCGEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
335 : }
336 : return 0;
337 : }
338 :
339 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
340 0 : if (RetVT.SimpleTy != MVT::v4i16)
341 : return 0;
342 0 : if ((Subtarget->hasNEON())) {
343 0 : return fastEmitInst_r(ARM::VCGEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
344 : }
345 : return 0;
346 : }
347 :
348 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
349 0 : if (RetVT.SimpleTy != MVT::v8i16)
350 : return 0;
351 0 : if ((Subtarget->hasNEON())) {
352 0 : return fastEmitInst_r(ARM::VCGEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
353 : }
354 : return 0;
355 : }
356 :
357 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
358 0 : if (RetVT.SimpleTy != MVT::v2i32)
359 : return 0;
360 0 : if ((Subtarget->hasNEON())) {
361 0 : return fastEmitInst_r(ARM::VCGEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
362 : }
363 : return 0;
364 : }
365 :
366 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
367 0 : if (RetVT.SimpleTy != MVT::v4i32)
368 : return 0;
369 0 : if ((Subtarget->hasNEON())) {
370 0 : return fastEmitInst_r(ARM::VCGEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
371 : }
372 : return 0;
373 : }
374 :
375 0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
376 0 : if (RetVT.SimpleTy != MVT::v4i16)
377 : return 0;
378 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
379 0 : return fastEmitInst_r(ARM::VCGEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
380 : }
381 : return 0;
382 : }
383 :
384 0 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
385 0 : if (RetVT.SimpleTy != MVT::v8i16)
386 : return 0;
387 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
388 0 : return fastEmitInst_r(ARM::VCGEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
389 : }
390 : return 0;
391 : }
392 :
393 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
394 0 : if (RetVT.SimpleTy != MVT::v2i32)
395 : return 0;
396 0 : if ((Subtarget->hasNEON())) {
397 0 : return fastEmitInst_r(ARM::VCGEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
398 : }
399 : return 0;
400 : }
401 :
402 : unsigned fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
403 0 : if (RetVT.SimpleTy != MVT::v4i32)
404 : return 0;
405 0 : if ((Subtarget->hasNEON())) {
406 0 : return fastEmitInst_r(ARM::VCGEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
407 : }
408 : return 0;
409 : }
410 :
411 0 : unsigned fastEmit_ARMISD_VCGEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
412 0 : switch (VT.SimpleTy) {
413 0 : case MVT::v8i8: return fastEmit_ARMISD_VCGEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
414 0 : case MVT::v16i8: return fastEmit_ARMISD_VCGEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
415 0 : case MVT::v4i16: return fastEmit_ARMISD_VCGEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
416 0 : case MVT::v8i16: return fastEmit_ARMISD_VCGEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
417 0 : case MVT::v2i32: return fastEmit_ARMISD_VCGEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
418 0 : case MVT::v4i32: return fastEmit_ARMISD_VCGEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
419 0 : case MVT::v4f16: return fastEmit_ARMISD_VCGEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
420 0 : case MVT::v8f16: return fastEmit_ARMISD_VCGEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
421 0 : case MVT::v2f32: return fastEmit_ARMISD_VCGEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
422 0 : case MVT::v4f32: return fastEmit_ARMISD_VCGEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
423 : default: return 0;
424 : }
425 : }
426 :
427 : // FastEmit functions for ARMISD::VCGTZ.
428 :
429 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
430 0 : if (RetVT.SimpleTy != MVT::v8i8)
431 : return 0;
432 0 : if ((Subtarget->hasNEON())) {
433 0 : return fastEmitInst_r(ARM::VCGTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
434 : }
435 : return 0;
436 : }
437 :
438 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
439 0 : if (RetVT.SimpleTy != MVT::v16i8)
440 : return 0;
441 0 : if ((Subtarget->hasNEON())) {
442 0 : return fastEmitInst_r(ARM::VCGTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
443 : }
444 : return 0;
445 : }
446 :
447 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
448 0 : if (RetVT.SimpleTy != MVT::v4i16)
449 : return 0;
450 0 : if ((Subtarget->hasNEON())) {
451 0 : return fastEmitInst_r(ARM::VCGTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
452 : }
453 : return 0;
454 : }
455 :
456 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
457 0 : if (RetVT.SimpleTy != MVT::v8i16)
458 : return 0;
459 0 : if ((Subtarget->hasNEON())) {
460 0 : return fastEmitInst_r(ARM::VCGTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
461 : }
462 : return 0;
463 : }
464 :
465 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
466 0 : if (RetVT.SimpleTy != MVT::v2i32)
467 : return 0;
468 0 : if ((Subtarget->hasNEON())) {
469 0 : return fastEmitInst_r(ARM::VCGTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
470 : }
471 : return 0;
472 : }
473 :
474 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
475 0 : if (RetVT.SimpleTy != MVT::v4i32)
476 : return 0;
477 0 : if ((Subtarget->hasNEON())) {
478 0 : return fastEmitInst_r(ARM::VCGTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
479 : }
480 : return 0;
481 : }
482 :
483 0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
484 0 : if (RetVT.SimpleTy != MVT::v4i16)
485 : return 0;
486 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
487 0 : return fastEmitInst_r(ARM::VCGTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
488 : }
489 : return 0;
490 : }
491 :
492 0 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
493 0 : if (RetVT.SimpleTy != MVT::v8i16)
494 : return 0;
495 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
496 0 : return fastEmitInst_r(ARM::VCGTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
497 : }
498 : return 0;
499 : }
500 :
501 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
502 0 : if (RetVT.SimpleTy != MVT::v2i32)
503 : return 0;
504 0 : if ((Subtarget->hasNEON())) {
505 0 : return fastEmitInst_r(ARM::VCGTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
506 : }
507 : return 0;
508 : }
509 :
510 : unsigned fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
511 0 : if (RetVT.SimpleTy != MVT::v4i32)
512 : return 0;
513 0 : if ((Subtarget->hasNEON())) {
514 0 : return fastEmitInst_r(ARM::VCGTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
515 : }
516 : return 0;
517 : }
518 :
519 0 : unsigned fastEmit_ARMISD_VCGTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
520 0 : switch (VT.SimpleTy) {
521 0 : case MVT::v8i8: return fastEmit_ARMISD_VCGTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
522 0 : case MVT::v16i8: return fastEmit_ARMISD_VCGTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
523 0 : case MVT::v4i16: return fastEmit_ARMISD_VCGTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
524 0 : case MVT::v8i16: return fastEmit_ARMISD_VCGTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
525 0 : case MVT::v2i32: return fastEmit_ARMISD_VCGTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
526 0 : case MVT::v4i32: return fastEmit_ARMISD_VCGTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
527 0 : case MVT::v4f16: return fastEmit_ARMISD_VCGTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
528 0 : case MVT::v8f16: return fastEmit_ARMISD_VCGTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
529 0 : case MVT::v2f32: return fastEmit_ARMISD_VCGTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
530 0 : case MVT::v4f32: return fastEmit_ARMISD_VCGTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
531 : default: return 0;
532 : }
533 : }
534 :
535 : // FastEmit functions for ARMISD::VCLEZ.
536 :
537 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
538 0 : if (RetVT.SimpleTy != MVT::v8i8)
539 : return 0;
540 0 : if ((Subtarget->hasNEON())) {
541 0 : return fastEmitInst_r(ARM::VCLEzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
542 : }
543 : return 0;
544 : }
545 :
546 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
547 0 : if (RetVT.SimpleTy != MVT::v16i8)
548 : return 0;
549 0 : if ((Subtarget->hasNEON())) {
550 0 : return fastEmitInst_r(ARM::VCLEzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
551 : }
552 : return 0;
553 : }
554 :
555 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
556 0 : if (RetVT.SimpleTy != MVT::v4i16)
557 : return 0;
558 0 : if ((Subtarget->hasNEON())) {
559 0 : return fastEmitInst_r(ARM::VCLEzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
560 : }
561 : return 0;
562 : }
563 :
564 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
565 0 : if (RetVT.SimpleTy != MVT::v8i16)
566 : return 0;
567 0 : if ((Subtarget->hasNEON())) {
568 0 : return fastEmitInst_r(ARM::VCLEzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
569 : }
570 : return 0;
571 : }
572 :
573 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
574 0 : if (RetVT.SimpleTy != MVT::v2i32)
575 : return 0;
576 0 : if ((Subtarget->hasNEON())) {
577 0 : return fastEmitInst_r(ARM::VCLEzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
578 : }
579 : return 0;
580 : }
581 :
582 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
583 0 : if (RetVT.SimpleTy != MVT::v4i32)
584 : return 0;
585 0 : if ((Subtarget->hasNEON())) {
586 0 : return fastEmitInst_r(ARM::VCLEzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
587 : }
588 : return 0;
589 : }
590 :
591 0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
592 0 : if (RetVT.SimpleTy != MVT::v4i16)
593 : return 0;
594 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
595 0 : return fastEmitInst_r(ARM::VCLEzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
596 : }
597 : return 0;
598 : }
599 :
600 0 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
601 0 : if (RetVT.SimpleTy != MVT::v8i16)
602 : return 0;
603 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
604 0 : return fastEmitInst_r(ARM::VCLEzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
605 : }
606 : return 0;
607 : }
608 :
609 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
610 0 : if (RetVT.SimpleTy != MVT::v2i32)
611 : return 0;
612 0 : if ((Subtarget->hasNEON())) {
613 0 : return fastEmitInst_r(ARM::VCLEzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
614 : }
615 : return 0;
616 : }
617 :
618 : unsigned fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
619 0 : if (RetVT.SimpleTy != MVT::v4i32)
620 : return 0;
621 0 : if ((Subtarget->hasNEON())) {
622 0 : return fastEmitInst_r(ARM::VCLEzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
623 : }
624 : return 0;
625 : }
626 :
627 0 : unsigned fastEmit_ARMISD_VCLEZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
628 0 : switch (VT.SimpleTy) {
629 0 : case MVT::v8i8: return fastEmit_ARMISD_VCLEZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
630 0 : case MVT::v16i8: return fastEmit_ARMISD_VCLEZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
631 0 : case MVT::v4i16: return fastEmit_ARMISD_VCLEZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
632 0 : case MVT::v8i16: return fastEmit_ARMISD_VCLEZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
633 0 : case MVT::v2i32: return fastEmit_ARMISD_VCLEZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
634 0 : case MVT::v4i32: return fastEmit_ARMISD_VCLEZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
635 0 : case MVT::v4f16: return fastEmit_ARMISD_VCLEZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
636 0 : case MVT::v8f16: return fastEmit_ARMISD_VCLEZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
637 0 : case MVT::v2f32: return fastEmit_ARMISD_VCLEZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
638 0 : case MVT::v4f32: return fastEmit_ARMISD_VCLEZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
639 : default: return 0;
640 : }
641 : }
642 :
643 : // FastEmit functions for ARMISD::VCLTZ.
644 :
645 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
646 0 : if (RetVT.SimpleTy != MVT::v8i8)
647 : return 0;
648 0 : if ((Subtarget->hasNEON())) {
649 0 : return fastEmitInst_r(ARM::VCLTzv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
650 : }
651 : return 0;
652 : }
653 :
654 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
655 0 : if (RetVT.SimpleTy != MVT::v16i8)
656 : return 0;
657 0 : if ((Subtarget->hasNEON())) {
658 0 : return fastEmitInst_r(ARM::VCLTzv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
659 : }
660 : return 0;
661 : }
662 :
663 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
664 0 : if (RetVT.SimpleTy != MVT::v4i16)
665 : return 0;
666 0 : if ((Subtarget->hasNEON())) {
667 0 : return fastEmitInst_r(ARM::VCLTzv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
668 : }
669 : return 0;
670 : }
671 :
672 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
673 0 : if (RetVT.SimpleTy != MVT::v8i16)
674 : return 0;
675 0 : if ((Subtarget->hasNEON())) {
676 0 : return fastEmitInst_r(ARM::VCLTzv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
677 : }
678 : return 0;
679 : }
680 :
681 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
682 0 : if (RetVT.SimpleTy != MVT::v2i32)
683 : return 0;
684 0 : if ((Subtarget->hasNEON())) {
685 0 : return fastEmitInst_r(ARM::VCLTzv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
686 : }
687 : return 0;
688 : }
689 :
690 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
691 0 : if (RetVT.SimpleTy != MVT::v4i32)
692 : return 0;
693 0 : if ((Subtarget->hasNEON())) {
694 0 : return fastEmitInst_r(ARM::VCLTzv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
695 : }
696 : return 0;
697 : }
698 :
699 0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
700 0 : if (RetVT.SimpleTy != MVT::v4i16)
701 : return 0;
702 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
703 0 : return fastEmitInst_r(ARM::VCLTzv4f16, &ARM::DPRRegClass, Op0, Op0IsKill);
704 : }
705 : return 0;
706 : }
707 :
708 0 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
709 0 : if (RetVT.SimpleTy != MVT::v8i16)
710 : return 0;
711 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
712 0 : return fastEmitInst_r(ARM::VCLTzv8f16, &ARM::QPRRegClass, Op0, Op0IsKill);
713 : }
714 : return 0;
715 : }
716 :
717 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
718 0 : if (RetVT.SimpleTy != MVT::v2i32)
719 : return 0;
720 0 : if ((Subtarget->hasNEON())) {
721 0 : return fastEmitInst_r(ARM::VCLTzv2f32, &ARM::DPRRegClass, Op0, Op0IsKill);
722 : }
723 : return 0;
724 : }
725 :
726 : unsigned fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
727 0 : if (RetVT.SimpleTy != MVT::v4i32)
728 : return 0;
729 0 : if ((Subtarget->hasNEON())) {
730 0 : return fastEmitInst_r(ARM::VCLTzv4f32, &ARM::QPRRegClass, Op0, Op0IsKill);
731 : }
732 : return 0;
733 : }
734 :
735 0 : unsigned fastEmit_ARMISD_VCLTZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
736 0 : switch (VT.SimpleTy) {
737 0 : case MVT::v8i8: return fastEmit_ARMISD_VCLTZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
738 0 : case MVT::v16i8: return fastEmit_ARMISD_VCLTZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
739 0 : case MVT::v4i16: return fastEmit_ARMISD_VCLTZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
740 0 : case MVT::v8i16: return fastEmit_ARMISD_VCLTZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
741 0 : case MVT::v2i32: return fastEmit_ARMISD_VCLTZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
742 0 : case MVT::v4i32: return fastEmit_ARMISD_VCLTZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
743 0 : case MVT::v4f16: return fastEmit_ARMISD_VCLTZ_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
744 0 : case MVT::v8f16: return fastEmit_ARMISD_VCLTZ_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
745 0 : case MVT::v2f32: return fastEmit_ARMISD_VCLTZ_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
746 0 : case MVT::v4f32: return fastEmit_ARMISD_VCLTZ_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
747 : default: return 0;
748 : }
749 : }
750 :
751 : // FastEmit functions for ARMISD::VDUP.
752 :
753 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
754 0 : if ((Subtarget->hasNEON())) {
755 0 : return fastEmitInst_r(ARM::VDUP8d, &ARM::DPRRegClass, Op0, Op0IsKill);
756 : }
757 : return 0;
758 : }
759 :
760 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
761 0 : if ((Subtarget->hasNEON())) {
762 0 : return fastEmitInst_r(ARM::VDUP8q, &ARM::QPRRegClass, Op0, Op0IsKill);
763 : }
764 : return 0;
765 : }
766 :
767 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
768 0 : if ((Subtarget->hasNEON())) {
769 0 : return fastEmitInst_r(ARM::VDUP16d, &ARM::DPRRegClass, Op0, Op0IsKill);
770 : }
771 : return 0;
772 : }
773 :
774 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
775 0 : if ((Subtarget->hasNEON())) {
776 0 : return fastEmitInst_r(ARM::VDUP16q, &ARM::QPRRegClass, Op0, Op0IsKill);
777 : }
778 : return 0;
779 : }
780 :
781 0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
782 0 : if ((!Subtarget->hasSlowVDUP32()) && (Subtarget->hasNEON())) {
783 0 : return fastEmitInst_r(ARM::VDUP32d, &ARM::DPRRegClass, Op0, Op0IsKill);
784 : }
785 : return 0;
786 : }
787 :
788 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
789 0 : if ((Subtarget->hasNEON())) {
790 0 : return fastEmitInst_r(ARM::VDUP32q, &ARM::QPRRegClass, Op0, Op0IsKill);
791 : }
792 : return 0;
793 : }
794 :
795 0 : unsigned fastEmit_ARMISD_VDUP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
796 0 : switch (RetVT.SimpleTy) {
797 0 : case MVT::v8i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i8_r(Op0, Op0IsKill);
798 0 : case MVT::v16i8: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v16i8_r(Op0, Op0IsKill);
799 0 : case MVT::v4i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i16_r(Op0, Op0IsKill);
800 0 : case MVT::v8i16: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v8i16_r(Op0, Op0IsKill);
801 0 : case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill);
802 0 : case MVT::v4i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v4i32_r(Op0, Op0IsKill);
803 : default: return 0;
804 : }
805 : }
806 :
807 : unsigned fastEmit_ARMISD_VDUP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
808 0 : switch (VT.SimpleTy) {
809 0 : case MVT::i32: return fastEmit_ARMISD_VDUP_MVT_i32_r(RetVT, Op0, Op0IsKill);
810 : default: return 0;
811 : }
812 : }
813 :
814 : // FastEmit functions for ARMISD::VMOVSR.
815 :
816 0 : unsigned fastEmit_ARMISD_VMOVSR_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
817 0 : if (RetVT.SimpleTy != MVT::f32)
818 : return 0;
819 0 : if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
820 0 : return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
821 : }
822 : return 0;
823 : }
824 :
825 : unsigned fastEmit_ARMISD_VMOVSR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
826 0 : switch (VT.SimpleTy) {
827 0 : case MVT::i32: return fastEmit_ARMISD_VMOVSR_MVT_i32_r(RetVT, Op0, Op0IsKill);
828 : default: return 0;
829 : }
830 : }
831 :
832 : // FastEmit functions for ARMISD::VMOVhr.
833 :
834 : unsigned fastEmit_ARMISD_VMOVhr_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
835 0 : if (RetVT.SimpleTy != MVT::f16)
836 : return 0;
837 0 : if ((Subtarget->hasFullFP16())) {
838 0 : return fastEmitInst_r(ARM::VMOVHR, &ARM::HPRRegClass, Op0, Op0IsKill);
839 : }
840 : return 0;
841 : }
842 :
843 0 : unsigned fastEmit_ARMISD_VMOVhr_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
844 0 : switch (VT.SimpleTy) {
845 0 : case MVT::i32: return fastEmit_ARMISD_VMOVhr_MVT_i32_r(RetVT, Op0, Op0IsKill);
846 : default: return 0;
847 : }
848 : }
849 :
850 : // FastEmit functions for ARMISD::VMOVrh.
851 :
852 : unsigned fastEmit_ARMISD_VMOVrh_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
853 0 : if (RetVT.SimpleTy != MVT::i32)
854 : return 0;
855 0 : if ((Subtarget->hasFullFP16())) {
856 0 : return fastEmitInst_r(ARM::VMOVRH, &ARM::GPRRegClass, Op0, Op0IsKill);
857 : }
858 : return 0;
859 : }
860 :
861 0 : unsigned fastEmit_ARMISD_VMOVrh_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
862 0 : switch (VT.SimpleTy) {
863 0 : case MVT::f16: return fastEmit_ARMISD_VMOVrh_MVT_f16_r(RetVT, Op0, Op0IsKill);
864 : default: return 0;
865 : }
866 : }
867 :
868 : // FastEmit functions for ARMISD::VREV16.
869 :
870 : unsigned fastEmit_ARMISD_VREV16_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
871 0 : if (RetVT.SimpleTy != MVT::v8i8)
872 : return 0;
873 0 : if ((Subtarget->hasNEON())) {
874 0 : return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
875 : }
876 : return 0;
877 : }
878 :
879 : unsigned fastEmit_ARMISD_VREV16_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
880 0 : if (RetVT.SimpleTy != MVT::v16i8)
881 : return 0;
882 0 : if ((Subtarget->hasNEON())) {
883 0 : return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
884 : }
885 : return 0;
886 : }
887 :
888 0 : unsigned fastEmit_ARMISD_VREV16_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
889 0 : switch (VT.SimpleTy) {
890 0 : case MVT::v8i8: return fastEmit_ARMISD_VREV16_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
891 0 : case MVT::v16i8: return fastEmit_ARMISD_VREV16_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
892 : default: return 0;
893 : }
894 : }
895 :
896 : // FastEmit functions for ARMISD::VREV32.
897 :
898 : unsigned fastEmit_ARMISD_VREV32_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
899 0 : if (RetVT.SimpleTy != MVT::v8i8)
900 : return 0;
901 0 : if ((Subtarget->hasNEON())) {
902 0 : return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
903 : }
904 : return 0;
905 : }
906 :
907 : unsigned fastEmit_ARMISD_VREV32_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
908 0 : if (RetVT.SimpleTy != MVT::v16i8)
909 : return 0;
910 0 : if ((Subtarget->hasNEON())) {
911 0 : return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
912 : }
913 : return 0;
914 : }
915 :
916 : unsigned fastEmit_ARMISD_VREV32_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
917 0 : if (RetVT.SimpleTy != MVT::v4i16)
918 : return 0;
919 0 : if ((Subtarget->hasNEON())) {
920 0 : return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
921 : }
922 : return 0;
923 : }
924 :
925 : unsigned fastEmit_ARMISD_VREV32_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
926 0 : if (RetVT.SimpleTy != MVT::v8i16)
927 : return 0;
928 0 : if ((Subtarget->hasNEON())) {
929 0 : return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
930 : }
931 : return 0;
932 : }
933 :
934 0 : unsigned fastEmit_ARMISD_VREV32_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
935 0 : switch (VT.SimpleTy) {
936 0 : case MVT::v8i8: return fastEmit_ARMISD_VREV32_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
937 0 : case MVT::v16i8: return fastEmit_ARMISD_VREV32_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
938 0 : case MVT::v4i16: return fastEmit_ARMISD_VREV32_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
939 0 : case MVT::v8i16: return fastEmit_ARMISD_VREV32_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
940 : default: return 0;
941 : }
942 : }
943 :
944 : // FastEmit functions for ARMISD::VREV64.
945 :
946 : unsigned fastEmit_ARMISD_VREV64_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
947 0 : if (RetVT.SimpleTy != MVT::v8i8)
948 : return 0;
949 0 : if ((Subtarget->hasNEON())) {
950 0 : return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
951 : }
952 : return 0;
953 : }
954 :
955 : unsigned fastEmit_ARMISD_VREV64_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
956 0 : if (RetVT.SimpleTy != MVT::v16i8)
957 : return 0;
958 0 : if ((Subtarget->hasNEON())) {
959 0 : return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
960 : }
961 : return 0;
962 : }
963 :
964 : unsigned fastEmit_ARMISD_VREV64_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
965 0 : if (RetVT.SimpleTy != MVT::v4i16)
966 : return 0;
967 0 : if ((Subtarget->hasNEON())) {
968 0 : return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
969 : }
970 : return 0;
971 : }
972 :
973 : unsigned fastEmit_ARMISD_VREV64_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
974 0 : if (RetVT.SimpleTy != MVT::v8i16)
975 : return 0;
976 0 : if ((Subtarget->hasNEON())) {
977 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
978 : }
979 : return 0;
980 : }
981 :
982 : unsigned fastEmit_ARMISD_VREV64_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
983 0 : if (RetVT.SimpleTy != MVT::v2i32)
984 : return 0;
985 0 : if ((Subtarget->hasNEON())) {
986 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
987 : }
988 : return 0;
989 : }
990 :
991 : unsigned fastEmit_ARMISD_VREV64_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
992 0 : if (RetVT.SimpleTy != MVT::v4i32)
993 : return 0;
994 0 : if ((Subtarget->hasNEON())) {
995 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
996 : }
997 : return 0;
998 : }
999 :
1000 : unsigned fastEmit_ARMISD_VREV64_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1001 0 : if (RetVT.SimpleTy != MVT::v4f16)
1002 : return 0;
1003 0 : return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1004 : }
1005 :
1006 : unsigned fastEmit_ARMISD_VREV64_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1007 0 : if (RetVT.SimpleTy != MVT::v8f16)
1008 : return 0;
1009 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1010 : }
1011 :
1012 : unsigned fastEmit_ARMISD_VREV64_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1013 0 : if (RetVT.SimpleTy != MVT::v2f32)
1014 : return 0;
1015 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1016 : }
1017 :
1018 : unsigned fastEmit_ARMISD_VREV64_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1019 0 : if (RetVT.SimpleTy != MVT::v4f32)
1020 : return 0;
1021 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1022 : }
1023 :
1024 0 : unsigned fastEmit_ARMISD_VREV64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1025 0 : switch (VT.SimpleTy) {
1026 0 : case MVT::v8i8: return fastEmit_ARMISD_VREV64_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1027 0 : case MVT::v16i8: return fastEmit_ARMISD_VREV64_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1028 0 : case MVT::v4i16: return fastEmit_ARMISD_VREV64_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1029 0 : case MVT::v8i16: return fastEmit_ARMISD_VREV64_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1030 0 : case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1031 0 : case MVT::v4i32: return fastEmit_ARMISD_VREV64_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1032 0 : case MVT::v4f16: return fastEmit_ARMISD_VREV64_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
1033 0 : case MVT::v8f16: return fastEmit_ARMISD_VREV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1034 0 : case MVT::v2f32: return fastEmit_ARMISD_VREV64_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
1035 0 : case MVT::v4f32: return fastEmit_ARMISD_VREV64_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1036 : default: return 0;
1037 : }
1038 : }
1039 :
1040 : // FastEmit functions for ARMISD::WIN__DBZCHK.
1041 :
1042 : unsigned fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1043 0 : if (RetVT.SimpleTy != MVT::isVoid)
1044 : return 0;
1045 0 : return fastEmitInst_r(ARM::WIN__DBZCHK, &ARM::tGPRRegClass, Op0, Op0IsKill);
1046 : }
1047 :
1048 : unsigned fastEmit_ARMISD_WIN__DBZCHK_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1049 0 : switch (VT.SimpleTy) {
1050 0 : case MVT::i32: return fastEmit_ARMISD_WIN__DBZCHK_MVT_i32_r(RetVT, Op0, Op0IsKill);
1051 : default: return 0;
1052 : }
1053 : }
1054 :
1055 : // FastEmit functions for ISD::ABS.
1056 :
1057 : unsigned fastEmit_ISD_ABS_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1058 0 : if (RetVT.SimpleTy != MVT::v8i8)
1059 : return 0;
1060 0 : if ((Subtarget->hasNEON())) {
1061 0 : return fastEmitInst_r(ARM::VABSv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
1062 : }
1063 : return 0;
1064 : }
1065 :
1066 : unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1067 0 : if (RetVT.SimpleTy != MVT::v16i8)
1068 : return 0;
1069 0 : if ((Subtarget->hasNEON())) {
1070 0 : return fastEmitInst_r(ARM::VABSv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
1071 : }
1072 : return 0;
1073 : }
1074 :
1075 : unsigned fastEmit_ISD_ABS_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1076 0 : if (RetVT.SimpleTy != MVT::v4i16)
1077 : return 0;
1078 0 : if ((Subtarget->hasNEON())) {
1079 0 : return fastEmitInst_r(ARM::VABSv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
1080 : }
1081 : return 0;
1082 : }
1083 :
1084 : unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1085 0 : if (RetVT.SimpleTy != MVT::v8i16)
1086 : return 0;
1087 0 : if ((Subtarget->hasNEON())) {
1088 0 : return fastEmitInst_r(ARM::VABSv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1089 : }
1090 : return 0;
1091 : }
1092 :
1093 : unsigned fastEmit_ISD_ABS_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1094 0 : if (RetVT.SimpleTy != MVT::v2i32)
1095 : return 0;
1096 0 : if ((Subtarget->hasNEON())) {
1097 0 : return fastEmitInst_r(ARM::VABSv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
1098 : }
1099 : return 0;
1100 : }
1101 :
1102 : unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1103 0 : if (RetVT.SimpleTy != MVT::v4i32)
1104 : return 0;
1105 0 : if ((Subtarget->hasNEON())) {
1106 0 : return fastEmitInst_r(ARM::VABSv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1107 : }
1108 : return 0;
1109 : }
1110 :
1111 0 : unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1112 0 : switch (VT.SimpleTy) {
1113 0 : case MVT::v8i8: return fastEmit_ISD_ABS_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1114 0 : case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1115 0 : case MVT::v4i16: return fastEmit_ISD_ABS_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1116 0 : case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1117 0 : case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1118 0 : case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1119 : default: return 0;
1120 : }
1121 : }
1122 :
1123 : // FastEmit functions for ISD::ANY_EXTEND.
1124 :
1125 : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1126 0 : if (RetVT.SimpleTy != MVT::v8i16)
1127 : return 0;
1128 0 : return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1129 : }
1130 :
1131 : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1132 0 : if (RetVT.SimpleTy != MVT::v4i32)
1133 : return 0;
1134 0 : return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1135 : }
1136 :
1137 : unsigned fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1138 0 : if (RetVT.SimpleTy != MVT::v2i64)
1139 : return 0;
1140 0 : return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
1141 : }
1142 :
1143 0 : unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1144 0 : switch (VT.SimpleTy) {
1145 0 : case MVT::v8i8: return fastEmit_ISD_ANY_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1146 0 : case MVT::v4i16: return fastEmit_ISD_ANY_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1147 0 : case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1148 : default: return 0;
1149 : }
1150 : }
1151 :
1152 : // FastEmit functions for ISD::BITCAST.
1153 :
1154 0 : unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1155 0 : if (RetVT.SimpleTy != MVT::f32)
1156 : return 0;
1157 0 : if ((Subtarget->hasVFP2()) && (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())) {
1158 0 : return fastEmitInst_r(ARM::VMOVSR, &ARM::SPRRegClass, Op0, Op0IsKill);
1159 : }
1160 : return 0;
1161 : }
1162 :
1163 : unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1164 81 : if (RetVT.SimpleTy != MVT::i32)
1165 : return 0;
1166 81 : if ((Subtarget->hasVFP2())) {
1167 81 : return fastEmitInst_r(ARM::VMOVRS, &ARM::GPRRegClass, Op0, Op0IsKill);
1168 : }
1169 : return 0;
1170 : }
1171 :
1172 0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1173 0 : if ((MF->getDataLayout().isBigEndian())) {
1174 0 : return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1175 : }
1176 : return 0;
1177 : }
1178 :
1179 0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1180 0 : if ((MF->getDataLayout().isBigEndian())) {
1181 0 : return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1182 : }
1183 : return 0;
1184 : }
1185 :
1186 0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1187 0 : if ((MF->getDataLayout().isBigEndian())) {
1188 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1189 : }
1190 : return 0;
1191 : }
1192 :
1193 0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1194 0 : if ((MF->getDataLayout().isBigEndian())) {
1195 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1196 : }
1197 : return 0;
1198 : }
1199 :
1200 0 : unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1201 0 : switch (RetVT.SimpleTy) {
1202 0 : case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v8i8_r(Op0, Op0IsKill);
1203 0 : case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v4i16_r(Op0, Op0IsKill);
1204 0 : case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill);
1205 0 : case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2f32_r(Op0, Op0IsKill);
1206 : default: return 0;
1207 : }
1208 : }
1209 :
1210 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1211 0 : if ((MF->getDataLayout().isBigEndian())) {
1212 0 : return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1213 : }
1214 : return 0;
1215 : }
1216 :
1217 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1218 0 : if ((MF->getDataLayout().isBigEndian())) {
1219 0 : return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1220 : }
1221 : return 0;
1222 : }
1223 :
1224 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1225 0 : if ((MF->getDataLayout().isBigEndian())) {
1226 0 : return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1227 : }
1228 : return 0;
1229 : }
1230 :
1231 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1232 0 : if ((MF->getDataLayout().isBigEndian())) {
1233 0 : return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1234 : }
1235 : return 0;
1236 : }
1237 :
1238 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1239 0 : if ((MF->getDataLayout().isBigEndian())) {
1240 0 : return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1241 : }
1242 : return 0;
1243 : }
1244 :
1245 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1246 0 : switch (RetVT.SimpleTy) {
1247 0 : case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_f64_r(Op0, Op0IsKill);
1248 0 : case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v4i16_r(Op0, Op0IsKill);
1249 0 : case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill);
1250 0 : case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1i64_r(Op0, Op0IsKill);
1251 0 : case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2f32_r(Op0, Op0IsKill);
1252 : default: return 0;
1253 : }
1254 : }
1255 :
1256 0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1257 0 : if ((MF->getDataLayout().isBigEndian())) {
1258 0 : return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1259 : }
1260 : return 0;
1261 : }
1262 :
1263 2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1264 2 : if ((MF->getDataLayout().isBigEndian())) {
1265 0 : return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1266 : }
1267 : return 0;
1268 : }
1269 :
1270 0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1271 0 : if ((MF->getDataLayout().isBigEndian())) {
1272 0 : return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1273 : }
1274 : return 0;
1275 : }
1276 :
1277 0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1278 0 : if ((MF->getDataLayout().isBigEndian())) {
1279 0 : return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1280 : }
1281 : return 0;
1282 : }
1283 :
1284 0 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1285 0 : if ((MF->getDataLayout().isBigEndian())) {
1286 0 : return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1287 : }
1288 : return 0;
1289 : }
1290 :
1291 2 : unsigned fastEmit_ISD_BITCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1292 2 : switch (RetVT.SimpleTy) {
1293 0 : case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8i16_r(Op0, Op0IsKill);
1294 2 : case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4i32_r(Op0, Op0IsKill);
1295 0 : case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2i64_r(Op0, Op0IsKill);
1296 0 : case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v4f32_r(Op0, Op0IsKill);
1297 0 : case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v2f64_r(Op0, Op0IsKill);
1298 : default: return 0;
1299 : }
1300 : }
1301 :
1302 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1303 0 : if ((MF->getDataLayout().isBigEndian())) {
1304 0 : return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1305 : }
1306 : return 0;
1307 : }
1308 :
1309 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1310 0 : if ((MF->getDataLayout().isBigEndian())) {
1311 0 : return fastEmitInst_r(ARM::VREV16d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1312 : }
1313 : return 0;
1314 : }
1315 :
1316 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1317 0 : if ((MF->getDataLayout().isBigEndian())) {
1318 0 : return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1319 : }
1320 : return 0;
1321 : }
1322 :
1323 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1324 0 : if ((MF->getDataLayout().isBigEndian())) {
1325 0 : return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1326 : }
1327 : return 0;
1328 : }
1329 :
1330 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1331 0 : if ((MF->getDataLayout().isBigEndian())) {
1332 0 : return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1333 : }
1334 : return 0;
1335 : }
1336 :
1337 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1338 0 : switch (RetVT.SimpleTy) {
1339 0 : case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_f64_r(Op0, Op0IsKill);
1340 0 : case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v8i8_r(Op0, Op0IsKill);
1341 0 : case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill);
1342 0 : case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v1i64_r(Op0, Op0IsKill);
1343 0 : case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2f32_r(Op0, Op0IsKill);
1344 : default: return 0;
1345 : }
1346 : }
1347 :
1348 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1349 0 : if ((MF->getDataLayout().isBigEndian())) {
1350 0 : return fastEmitInst_r(ARM::VREV16q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1351 : }
1352 : return 0;
1353 : }
1354 :
1355 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1356 0 : if ((MF->getDataLayout().isBigEndian())) {
1357 0 : return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1358 : }
1359 : return 0;
1360 : }
1361 :
1362 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1363 0 : if ((MF->getDataLayout().isBigEndian())) {
1364 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1365 : }
1366 : return 0;
1367 : }
1368 :
1369 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1370 0 : if ((MF->getDataLayout().isBigEndian())) {
1371 0 : return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1372 : }
1373 : return 0;
1374 : }
1375 :
1376 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1377 0 : if ((MF->getDataLayout().isBigEndian())) {
1378 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1379 : }
1380 : return 0;
1381 : }
1382 :
1383 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1384 0 : switch (RetVT.SimpleTy) {
1385 0 : case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v16i8_r(Op0, Op0IsKill);
1386 0 : case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4i32_r(Op0, Op0IsKill);
1387 0 : case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2i64_r(Op0, Op0IsKill);
1388 0 : case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v4f32_r(Op0, Op0IsKill);
1389 0 : case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8i16_MVT_v2f64_r(Op0, Op0IsKill);
1390 : default: return 0;
1391 : }
1392 : }
1393 :
1394 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1395 0 : if ((MF->getDataLayout().isBigEndian())) {
1396 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1397 : }
1398 : return 0;
1399 : }
1400 :
1401 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1402 0 : if ((MF->getDataLayout().isBigEndian())) {
1403 0 : return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1404 : }
1405 : return 0;
1406 : }
1407 :
1408 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1409 0 : if ((MF->getDataLayout().isBigEndian())) {
1410 0 : return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1411 : }
1412 : return 0;
1413 : }
1414 :
1415 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1416 0 : if ((MF->getDataLayout().isBigEndian())) {
1417 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1418 : }
1419 : return 0;
1420 : }
1421 :
1422 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1423 0 : switch (RetVT.SimpleTy) {
1424 0 : case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_f64_r(Op0, Op0IsKill);
1425 0 : case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v8i8_r(Op0, Op0IsKill);
1426 0 : case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v4i16_r(Op0, Op0IsKill);
1427 0 : case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2i32_MVT_v1i64_r(Op0, Op0IsKill);
1428 : default: return 0;
1429 : }
1430 : }
1431 :
1432 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1433 0 : if ((MF->getDataLayout().isBigEndian())) {
1434 0 : return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1435 : }
1436 : return 0;
1437 : }
1438 :
1439 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1440 0 : if ((MF->getDataLayout().isBigEndian())) {
1441 0 : return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1442 : }
1443 : return 0;
1444 : }
1445 :
1446 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1447 0 : if ((MF->getDataLayout().isBigEndian())) {
1448 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1449 : }
1450 : return 0;
1451 : }
1452 :
1453 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1454 0 : if ((MF->getDataLayout().isBigEndian())) {
1455 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1456 : }
1457 : return 0;
1458 : }
1459 :
1460 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1461 0 : switch (RetVT.SimpleTy) {
1462 0 : case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v16i8_r(Op0, Op0IsKill);
1463 0 : case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8i16_r(Op0, Op0IsKill);
1464 0 : case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2i64_r(Op0, Op0IsKill);
1465 0 : case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v2f64_r(Op0, Op0IsKill);
1466 : default: return 0;
1467 : }
1468 : }
1469 :
1470 0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1471 0 : if ((MF->getDataLayout().isBigEndian())) {
1472 0 : return fastEmitInst_r(ARM::VREV64d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1473 : }
1474 : return 0;
1475 : }
1476 :
1477 0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1478 0 : if ((MF->getDataLayout().isBigEndian())) {
1479 0 : return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1480 : }
1481 : return 0;
1482 : }
1483 :
1484 0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(unsigned Op0, bool Op0IsKill) {
1485 0 : if ((MF->getDataLayout().isBigEndian())) {
1486 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1487 : }
1488 : return 0;
1489 : }
1490 :
1491 0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(unsigned Op0, bool Op0IsKill) {
1492 0 : if ((MF->getDataLayout().isBigEndian())) {
1493 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1494 : }
1495 : return 0;
1496 : }
1497 :
1498 0 : unsigned fastEmit_ISD_BITCAST_MVT_v1i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1499 0 : switch (RetVT.SimpleTy) {
1500 0 : case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v8i8_r(Op0, Op0IsKill);
1501 0 : case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v4i16_r(Op0, Op0IsKill);
1502 0 : case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill);
1503 0 : case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2f32_r(Op0, Op0IsKill);
1504 : default: return 0;
1505 : }
1506 : }
1507 :
1508 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1509 0 : if ((MF->getDataLayout().isBigEndian())) {
1510 0 : return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1511 : }
1512 : return 0;
1513 : }
1514 :
1515 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1516 0 : if ((MF->getDataLayout().isBigEndian())) {
1517 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1518 : }
1519 : return 0;
1520 : }
1521 :
1522 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1523 0 : if ((MF->getDataLayout().isBigEndian())) {
1524 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1525 : }
1526 : return 0;
1527 : }
1528 :
1529 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1530 0 : if ((MF->getDataLayout().isBigEndian())) {
1531 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1532 : }
1533 : return 0;
1534 : }
1535 :
1536 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1537 0 : switch (RetVT.SimpleTy) {
1538 0 : case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v16i8_r(Op0, Op0IsKill);
1539 0 : case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8i16_r(Op0, Op0IsKill);
1540 0 : case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4i32_r(Op0, Op0IsKill);
1541 0 : case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v4f32_r(Op0, Op0IsKill);
1542 : default: return 0;
1543 : }
1544 : }
1545 :
1546 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1547 0 : if (RetVT.SimpleTy != MVT::f64)
1548 : return 0;
1549 0 : if ((MF->getDataLayout().isBigEndian())) {
1550 0 : return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1551 : }
1552 : return 0;
1553 : }
1554 :
1555 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1556 0 : if ((MF->getDataLayout().isBigEndian())) {
1557 0 : return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1558 : }
1559 : return 0;
1560 : }
1561 :
1562 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1563 0 : if ((MF->getDataLayout().isBigEndian())) {
1564 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1565 : }
1566 : return 0;
1567 : }
1568 :
1569 0 : unsigned fastEmit_ISD_BITCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1570 0 : switch (RetVT.SimpleTy) {
1571 0 : case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v4f32_r(Op0, Op0IsKill);
1572 0 : case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v8f16_MVT_v2f64_r(Op0, Op0IsKill);
1573 : default: return 0;
1574 : }
1575 : }
1576 :
1577 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
1578 0 : if ((MF->getDataLayout().isBigEndian())) {
1579 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1580 : }
1581 : return 0;
1582 : }
1583 :
1584 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(unsigned Op0, bool Op0IsKill) {
1585 0 : if ((MF->getDataLayout().isBigEndian())) {
1586 0 : return fastEmitInst_r(ARM::VREV32d8, &ARM::DPRRegClass, Op0, Op0IsKill);
1587 : }
1588 : return 0;
1589 : }
1590 :
1591 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(unsigned Op0, bool Op0IsKill) {
1592 0 : if ((MF->getDataLayout().isBigEndian())) {
1593 0 : return fastEmitInst_r(ARM::VREV32d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1594 : }
1595 : return 0;
1596 : }
1597 :
1598 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(unsigned Op0, bool Op0IsKill) {
1599 0 : if ((MF->getDataLayout().isBigEndian())) {
1600 0 : return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1601 : }
1602 : return 0;
1603 : }
1604 :
1605 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1606 0 : switch (RetVT.SimpleTy) {
1607 0 : case MVT::f64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_f64_r(Op0, Op0IsKill);
1608 0 : case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v8i8_r(Op0, Op0IsKill);
1609 0 : case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v4i16_r(Op0, Op0IsKill);
1610 0 : case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v2f32_MVT_v1i64_r(Op0, Op0IsKill);
1611 : default: return 0;
1612 : }
1613 : }
1614 :
1615 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1616 0 : if ((MF->getDataLayout().isBigEndian())) {
1617 0 : return fastEmitInst_r(ARM::VREV32q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1618 : }
1619 : return 0;
1620 : }
1621 :
1622 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1623 0 : if ((MF->getDataLayout().isBigEndian())) {
1624 0 : return fastEmitInst_r(ARM::VREV32q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1625 : }
1626 : return 0;
1627 : }
1628 :
1629 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(unsigned Op0, bool Op0IsKill) {
1630 0 : if ((MF->getDataLayout().isBigEndian())) {
1631 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1632 : }
1633 : return 0;
1634 : }
1635 :
1636 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(unsigned Op0, bool Op0IsKill) {
1637 0 : if ((MF->getDataLayout().isBigEndian())) {
1638 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1639 : }
1640 : return 0;
1641 : }
1642 :
1643 0 : unsigned fastEmit_ISD_BITCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1644 0 : switch (RetVT.SimpleTy) {
1645 0 : case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v16i8_r(Op0, Op0IsKill);
1646 0 : case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8i16_r(Op0, Op0IsKill);
1647 0 : case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2i64_r(Op0, Op0IsKill);
1648 0 : case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v2f64_r(Op0, Op0IsKill);
1649 : default: return 0;
1650 : }
1651 : }
1652 :
1653 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(unsigned Op0, bool Op0IsKill) {
1654 0 : if ((MF->getDataLayout().isBigEndian())) {
1655 0 : return fastEmitInst_r(ARM::VREV64q8, &ARM::QPRRegClass, Op0, Op0IsKill);
1656 : }
1657 : return 0;
1658 : }
1659 :
1660 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(unsigned Op0, bool Op0IsKill) {
1661 0 : if ((MF->getDataLayout().isBigEndian())) {
1662 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1663 : }
1664 : return 0;
1665 : }
1666 :
1667 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(unsigned Op0, bool Op0IsKill) {
1668 0 : if ((MF->getDataLayout().isBigEndian())) {
1669 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1670 : }
1671 : return 0;
1672 : }
1673 :
1674 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(unsigned Op0, bool Op0IsKill) {
1675 0 : if ((MF->getDataLayout().isBigEndian())) {
1676 0 : return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
1677 : }
1678 : return 0;
1679 : }
1680 :
1681 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(unsigned Op0, bool Op0IsKill) {
1682 0 : if ((MF->getDataLayout().isBigEndian())) {
1683 0 : return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1684 : }
1685 : return 0;
1686 : }
1687 :
1688 0 : unsigned fastEmit_ISD_BITCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1689 0 : switch (RetVT.SimpleTy) {
1690 0 : case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v16i8_r(Op0, Op0IsKill);
1691 0 : case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8i16_r(Op0, Op0IsKill);
1692 0 : case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4i32_r(Op0, Op0IsKill);
1693 0 : case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill);
1694 0 : case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v4f32_r(Op0, Op0IsKill);
1695 : default: return 0;
1696 : }
1697 : }
1698 :
1699 83 : unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1700 83 : switch (VT.SimpleTy) {
1701 0 : case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
1702 81 : case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
1703 0 : case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
1704 0 : case MVT::v8i8: return fastEmit_ISD_BITCAST_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1705 2 : case MVT::v16i8: return fastEmit_ISD_BITCAST_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1706 0 : case MVT::v4i16: return fastEmit_ISD_BITCAST_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1707 0 : case MVT::v8i16: return fastEmit_ISD_BITCAST_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1708 0 : case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1709 0 : case MVT::v4i32: return fastEmit_ISD_BITCAST_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1710 0 : case MVT::v1i64: return fastEmit_ISD_BITCAST_MVT_v1i64_r(RetVT, Op0, Op0IsKill);
1711 0 : case MVT::v2i64: return fastEmit_ISD_BITCAST_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
1712 0 : case MVT::v4f16: return fastEmit_ISD_BITCAST_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
1713 0 : case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1714 0 : case MVT::v2f32: return fastEmit_ISD_BITCAST_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
1715 0 : case MVT::v4f32: return fastEmit_ISD_BITCAST_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1716 0 : case MVT::v2f64: return fastEmit_ISD_BITCAST_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
1717 : default: return 0;
1718 : }
1719 : }
1720 :
1721 : // FastEmit functions for ISD::BITREVERSE.
1722 :
1723 0 : unsigned fastEmit_ISD_BITREVERSE_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1724 0 : if (RetVT.SimpleTy != MVT::i32)
1725 : return 0;
1726 0 : if ((Subtarget->isThumb2())) {
1727 0 : return fastEmitInst_r(ARM::t2RBIT, &ARM::rGPRRegClass, Op0, Op0IsKill);
1728 : }
1729 0 : if ((Subtarget->hasV6T2Ops()) && (!Subtarget->isThumb())) {
1730 0 : return fastEmitInst_r(ARM::RBIT, &ARM::GPRRegClass, Op0, Op0IsKill);
1731 : }
1732 : return 0;
1733 : }
1734 :
1735 : unsigned fastEmit_ISD_BITREVERSE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1736 0 : switch (VT.SimpleTy) {
1737 0 : case MVT::i32: return fastEmit_ISD_BITREVERSE_MVT_i32_r(RetVT, Op0, Op0IsKill);
1738 : default: return 0;
1739 : }
1740 : }
1741 :
1742 : // FastEmit functions for ISD::BRIND.
1743 :
1744 0 : unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1745 0 : if (RetVT.SimpleTy != MVT::isVoid)
1746 : return 0;
1747 0 : if ((Subtarget->isThumb())) {
1748 0 : return fastEmitInst_r(ARM::tBRIND, &ARM::GPRRegClass, Op0, Op0IsKill);
1749 : }
1750 0 : if ((!Subtarget->isThumb()) && (!Subtarget->hasV4TOps())) {
1751 0 : return fastEmitInst_r(ARM::MOVPCRX, &ARM::GPRRegClass, Op0, Op0IsKill);
1752 : }
1753 0 : if ((Subtarget->hasV4TOps()) && (!Subtarget->isThumb())) {
1754 0 : return fastEmitInst_r(ARM::BX, &ARM::GPRRegClass, Op0, Op0IsKill);
1755 : }
1756 : return 0;
1757 : }
1758 :
1759 : unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1760 0 : switch (VT.SimpleTy) {
1761 0 : case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
1762 : default: return 0;
1763 : }
1764 : }
1765 :
1766 : // FastEmit functions for ISD::BSWAP.
1767 :
1768 0 : unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1769 0 : if (RetVT.SimpleTy != MVT::i32)
1770 : return 0;
1771 0 : if ((Subtarget->isThumb2())) {
1772 0 : return fastEmitInst_r(ARM::t2REV, &ARM::rGPRRegClass, Op0, Op0IsKill);
1773 : }
1774 0 : if ((Subtarget->hasV6Ops()) && (Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
1775 0 : return fastEmitInst_r(ARM::tREV, &ARM::tGPRRegClass, Op0, Op0IsKill);
1776 : }
1777 0 : if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
1778 0 : return fastEmitInst_r(ARM::REV, &ARM::GPRRegClass, Op0, Op0IsKill);
1779 : }
1780 : return 0;
1781 : }
1782 :
1783 : unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1784 0 : switch (VT.SimpleTy) {
1785 0 : case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0, Op0IsKill);
1786 : default: return 0;
1787 : }
1788 : }
1789 :
1790 : // FastEmit functions for ISD::CTLZ.
1791 :
1792 0 : unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1793 0 : if (RetVT.SimpleTy != MVT::i32)
1794 : return 0;
1795 0 : if ((Subtarget->isThumb2())) {
1796 0 : return fastEmitInst_r(ARM::t2CLZ, &ARM::rGPRRegClass, Op0, Op0IsKill);
1797 : }
1798 0 : if ((Subtarget->hasV5TOps()) && (!Subtarget->isThumb())) {
1799 0 : return fastEmitInst_r(ARM::CLZ, &ARM::GPRRegClass, Op0, Op0IsKill);
1800 : }
1801 : return 0;
1802 : }
1803 :
1804 : unsigned fastEmit_ISD_CTLZ_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1805 0 : if (RetVT.SimpleTy != MVT::v8i8)
1806 : return 0;
1807 0 : if ((Subtarget->hasNEON())) {
1808 0 : return fastEmitInst_r(ARM::VCLZv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
1809 : }
1810 : return 0;
1811 : }
1812 :
1813 : unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1814 0 : if (RetVT.SimpleTy != MVT::v16i8)
1815 : return 0;
1816 0 : if ((Subtarget->hasNEON())) {
1817 0 : return fastEmitInst_r(ARM::VCLZv16i8, &ARM::QPRRegClass, Op0, Op0IsKill);
1818 : }
1819 : return 0;
1820 : }
1821 :
1822 : unsigned fastEmit_ISD_CTLZ_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1823 0 : if (RetVT.SimpleTy != MVT::v4i16)
1824 : return 0;
1825 0 : if ((Subtarget->hasNEON())) {
1826 0 : return fastEmitInst_r(ARM::VCLZv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
1827 : }
1828 : return 0;
1829 : }
1830 :
1831 : unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1832 0 : if (RetVT.SimpleTy != MVT::v8i16)
1833 : return 0;
1834 0 : if ((Subtarget->hasNEON())) {
1835 0 : return fastEmitInst_r(ARM::VCLZv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
1836 : }
1837 : return 0;
1838 : }
1839 :
1840 : unsigned fastEmit_ISD_CTLZ_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1841 0 : if (RetVT.SimpleTy != MVT::v2i32)
1842 : return 0;
1843 0 : if ((Subtarget->hasNEON())) {
1844 0 : return fastEmitInst_r(ARM::VCLZv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
1845 : }
1846 : return 0;
1847 : }
1848 :
1849 : unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1850 0 : if (RetVT.SimpleTy != MVT::v4i32)
1851 : return 0;
1852 0 : if ((Subtarget->hasNEON())) {
1853 0 : return fastEmitInst_r(ARM::VCLZv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
1854 : }
1855 : return 0;
1856 : }
1857 :
1858 0 : unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1859 0 : switch (VT.SimpleTy) {
1860 0 : case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
1861 0 : case MVT::v8i8: return fastEmit_ISD_CTLZ_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1862 0 : case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1863 0 : case MVT::v4i16: return fastEmit_ISD_CTLZ_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
1864 0 : case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
1865 0 : case MVT::v2i32: return fastEmit_ISD_CTLZ_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
1866 0 : case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
1867 : default: return 0;
1868 : }
1869 : }
1870 :
1871 : // FastEmit functions for ISD::CTPOP.
1872 :
1873 : unsigned fastEmit_ISD_CTPOP_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1874 0 : if (RetVT.SimpleTy != MVT::v8i8)
1875 : return 0;
1876 0 : if ((Subtarget->hasNEON())) {
1877 0 : return fastEmitInst_r(ARM::VCNTd, &ARM::DPRRegClass, Op0, Op0IsKill);
1878 : }
1879 : return 0;
1880 : }
1881 :
1882 : unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1883 0 : if (RetVT.SimpleTy != MVT::v16i8)
1884 : return 0;
1885 0 : if ((Subtarget->hasNEON())) {
1886 0 : return fastEmitInst_r(ARM::VCNTq, &ARM::QPRRegClass, Op0, Op0IsKill);
1887 : }
1888 : return 0;
1889 : }
1890 :
1891 0 : unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1892 0 : switch (VT.SimpleTy) {
1893 0 : case MVT::v8i8: return fastEmit_ISD_CTPOP_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
1894 0 : case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
1895 : default: return 0;
1896 : }
1897 : }
1898 :
1899 : // FastEmit functions for ISD::FABS.
1900 :
1901 0 : unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1902 0 : if (RetVT.SimpleTy != MVT::f32)
1903 : return 0;
1904 0 : if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
1905 0 : return fastEmitInst_r(ARM::VABSS, &ARM::SPRRegClass, Op0, Op0IsKill);
1906 : }
1907 : return 0;
1908 : }
1909 :
1910 0 : unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1911 0 : if (RetVT.SimpleTy != MVT::f64)
1912 : return 0;
1913 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
1914 0 : return fastEmitInst_r(ARM::VABSD, &ARM::DPRRegClass, Op0, Op0IsKill);
1915 : }
1916 : return 0;
1917 : }
1918 :
1919 0 : unsigned fastEmit_ISD_FABS_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1920 0 : if (RetVT.SimpleTy != MVT::v4f16)
1921 : return 0;
1922 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
1923 0 : return fastEmitInst_r(ARM::VABShd, &ARM::DPRRegClass, Op0, Op0IsKill);
1924 : }
1925 : return 0;
1926 : }
1927 :
1928 0 : unsigned fastEmit_ISD_FABS_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1929 0 : if (RetVT.SimpleTy != MVT::v8f16)
1930 : return 0;
1931 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
1932 0 : return fastEmitInst_r(ARM::VABShq, &ARM::QPRRegClass, Op0, Op0IsKill);
1933 : }
1934 : return 0;
1935 : }
1936 :
1937 : unsigned fastEmit_ISD_FABS_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1938 0 : if (RetVT.SimpleTy != MVT::v2f32)
1939 : return 0;
1940 0 : if ((Subtarget->hasNEON())) {
1941 0 : return fastEmitInst_r(ARM::VABSfd, &ARM::DPRRegClass, Op0, Op0IsKill);
1942 : }
1943 : return 0;
1944 : }
1945 :
1946 : unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1947 0 : if (RetVT.SimpleTy != MVT::v4f32)
1948 : return 0;
1949 0 : if ((Subtarget->hasNEON())) {
1950 0 : return fastEmitInst_r(ARM::VABSfq, &ARM::QPRRegClass, Op0, Op0IsKill);
1951 : }
1952 : return 0;
1953 : }
1954 :
1955 0 : unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1956 0 : switch (VT.SimpleTy) {
1957 0 : case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
1958 0 : case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
1959 0 : case MVT::v4f16: return fastEmit_ISD_FABS_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
1960 0 : case MVT::v8f16: return fastEmit_ISD_FABS_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1961 0 : case MVT::v2f32: return fastEmit_ISD_FABS_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
1962 0 : case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
1963 : default: return 0;
1964 : }
1965 : }
1966 :
1967 : // FastEmit functions for ISD::FCEIL.
1968 :
1969 : unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1970 0 : if (RetVT.SimpleTy != MVT::f32)
1971 : return 0;
1972 0 : if ((Subtarget->hasFPARMv8())) {
1973 0 : return fastEmitInst_r(ARM::VRINTPS, &ARM::SPRRegClass, Op0, Op0IsKill);
1974 : }
1975 : return 0;
1976 : }
1977 :
1978 0 : unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1979 0 : if (RetVT.SimpleTy != MVT::f64)
1980 : return 0;
1981 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
1982 0 : return fastEmitInst_r(ARM::VRINTPD, &ARM::DPRRegClass, Op0, Op0IsKill);
1983 : }
1984 : return 0;
1985 : }
1986 :
1987 0 : unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
1988 0 : switch (VT.SimpleTy) {
1989 0 : case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0, Op0IsKill);
1990 0 : case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0, Op0IsKill);
1991 : default: return 0;
1992 : }
1993 : }
1994 :
1995 : // FastEmit functions for ISD::FFLOOR.
1996 :
1997 : unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
1998 0 : if (RetVT.SimpleTy != MVT::f32)
1999 : return 0;
2000 0 : if ((Subtarget->hasFPARMv8())) {
2001 0 : return fastEmitInst_r(ARM::VRINTMS, &ARM::SPRRegClass, Op0, Op0IsKill);
2002 : }
2003 : return 0;
2004 : }
2005 :
2006 0 : unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2007 0 : if (RetVT.SimpleTy != MVT::f64)
2008 : return 0;
2009 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2010 0 : return fastEmitInst_r(ARM::VRINTMD, &ARM::DPRRegClass, Op0, Op0IsKill);
2011 : }
2012 : return 0;
2013 : }
2014 :
2015 0 : unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2016 0 : switch (VT.SimpleTy) {
2017 0 : case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0, Op0IsKill);
2018 0 : case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0, Op0IsKill);
2019 : default: return 0;
2020 : }
2021 : }
2022 :
2023 : // FastEmit functions for ISD::FNEARBYINT.
2024 :
2025 : unsigned fastEmit_ISD_FNEARBYINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2026 0 : if (RetVT.SimpleTy != MVT::f32)
2027 : return 0;
2028 0 : if ((Subtarget->hasFPARMv8())) {
2029 0 : return fastEmitInst_r(ARM::VRINTRS, &ARM::SPRRegClass, Op0, Op0IsKill);
2030 : }
2031 : return 0;
2032 : }
2033 :
2034 0 : unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2035 0 : if (RetVT.SimpleTy != MVT::f64)
2036 : return 0;
2037 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2038 0 : return fastEmitInst_r(ARM::VRINTRD, &ARM::DPRRegClass, Op0, Op0IsKill);
2039 : }
2040 : return 0;
2041 : }
2042 :
2043 0 : unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2044 0 : switch (VT.SimpleTy) {
2045 0 : case MVT::f32: return fastEmit_ISD_FNEARBYINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2046 0 : case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2047 : default: return 0;
2048 : }
2049 : }
2050 :
2051 : // FastEmit functions for ISD::FNEG.
2052 :
2053 : unsigned fastEmit_ISD_FNEG_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2054 0 : if (RetVT.SimpleTy != MVT::f16)
2055 : return 0;
2056 0 : if ((Subtarget->hasFullFP16())) {
2057 0 : return fastEmitInst_r(ARM::VNEGH, &ARM::HPRRegClass, Op0, Op0IsKill);
2058 : }
2059 : return 0;
2060 : }
2061 :
2062 0 : unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2063 0 : if (RetVT.SimpleTy != MVT::f32)
2064 : return 0;
2065 0 : if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
2066 0 : return fastEmitInst_r(ARM::VNEGS, &ARM::SPRRegClass, Op0, Op0IsKill);
2067 : }
2068 : return 0;
2069 : }
2070 :
2071 0 : unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2072 0 : if (RetVT.SimpleTy != MVT::f64)
2073 : return 0;
2074 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2075 0 : return fastEmitInst_r(ARM::VNEGD, &ARM::DPRRegClass, Op0, Op0IsKill);
2076 : }
2077 : return 0;
2078 : }
2079 :
2080 0 : unsigned fastEmit_ISD_FNEG_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2081 0 : if (RetVT.SimpleTy != MVT::v4f16)
2082 : return 0;
2083 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2084 0 : return fastEmitInst_r(ARM::VNEGhd, &ARM::DPRRegClass, Op0, Op0IsKill);
2085 : }
2086 : return 0;
2087 : }
2088 :
2089 0 : unsigned fastEmit_ISD_FNEG_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2090 0 : if (RetVT.SimpleTy != MVT::v8f16)
2091 : return 0;
2092 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2093 0 : return fastEmitInst_r(ARM::VNEGhq, &ARM::QPRRegClass, Op0, Op0IsKill);
2094 : }
2095 : return 0;
2096 : }
2097 :
2098 : unsigned fastEmit_ISD_FNEG_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2099 0 : if (RetVT.SimpleTy != MVT::v2f32)
2100 : return 0;
2101 0 : if ((Subtarget->hasNEON())) {
2102 0 : return fastEmitInst_r(ARM::VNEGfd, &ARM::DPRRegClass, Op0, Op0IsKill);
2103 : }
2104 : return 0;
2105 : }
2106 :
2107 : unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2108 0 : if (RetVT.SimpleTy != MVT::v4f32)
2109 : return 0;
2110 0 : if ((Subtarget->hasNEON())) {
2111 0 : return fastEmitInst_r(ARM::VNEGf32q, &ARM::QPRRegClass, Op0, Op0IsKill);
2112 : }
2113 : return 0;
2114 : }
2115 :
2116 0 : unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2117 0 : switch (VT.SimpleTy) {
2118 0 : case MVT::f16: return fastEmit_ISD_FNEG_MVT_f16_r(RetVT, Op0, Op0IsKill);
2119 0 : case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
2120 0 : case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
2121 0 : case MVT::v4f16: return fastEmit_ISD_FNEG_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
2122 0 : case MVT::v8f16: return fastEmit_ISD_FNEG_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2123 0 : case MVT::v2f32: return fastEmit_ISD_FNEG_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
2124 0 : case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
2125 : default: return 0;
2126 : }
2127 : }
2128 :
2129 : // FastEmit functions for ISD::FP_EXTEND.
2130 :
2131 0 : unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2132 0 : if (RetVT.SimpleTy != MVT::f64)
2133 : return 0;
2134 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2135 0 : return fastEmitInst_r(ARM::VCVTDS, &ARM::DPRRegClass, Op0, Op0IsKill);
2136 : }
2137 : return 0;
2138 : }
2139 :
2140 : unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2141 0 : switch (VT.SimpleTy) {
2142 0 : case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2143 : default: return 0;
2144 : }
2145 : }
2146 :
2147 : // FastEmit functions for ISD::FP_ROUND.
2148 :
2149 0 : unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2150 0 : if (RetVT.SimpleTy != MVT::f32)
2151 : return 0;
2152 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2153 0 : return fastEmitInst_r(ARM::VCVTSD, &ARM::SPRRegClass, Op0, Op0IsKill);
2154 : }
2155 : return 0;
2156 : }
2157 :
2158 : unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2159 0 : switch (VT.SimpleTy) {
2160 0 : case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
2161 : default: return 0;
2162 : }
2163 : }
2164 :
2165 : // FastEmit functions for ISD::FP_TO_SINT.
2166 :
2167 0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2168 0 : if (RetVT.SimpleTy != MVT::v4i16)
2169 : return 0;
2170 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2171 0 : return fastEmitInst_r(ARM::VCVTh2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
2172 : }
2173 : return 0;
2174 : }
2175 :
2176 0 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2177 0 : if (RetVT.SimpleTy != MVT::v8i16)
2178 : return 0;
2179 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2180 0 : return fastEmitInst_r(ARM::VCVTh2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
2181 : }
2182 : return 0;
2183 : }
2184 :
2185 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2186 0 : if (RetVT.SimpleTy != MVT::v2i32)
2187 : return 0;
2188 0 : if ((Subtarget->hasNEON())) {
2189 0 : return fastEmitInst_r(ARM::VCVTf2sd, &ARM::DPRRegClass, Op0, Op0IsKill);
2190 : }
2191 : return 0;
2192 : }
2193 :
2194 : unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2195 0 : if (RetVT.SimpleTy != MVT::v4i32)
2196 : return 0;
2197 0 : if ((Subtarget->hasNEON())) {
2198 0 : return fastEmitInst_r(ARM::VCVTf2sq, &ARM::QPRRegClass, Op0, Op0IsKill);
2199 : }
2200 : return 0;
2201 : }
2202 :
2203 6 : unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2204 6 : switch (VT.SimpleTy) {
2205 0 : case MVT::v4f16: return fastEmit_ISD_FP_TO_SINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
2206 0 : case MVT::v8f16: return fastEmit_ISD_FP_TO_SINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2207 0 : case MVT::v2f32: return fastEmit_ISD_FP_TO_SINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
2208 0 : case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
2209 : default: return 0;
2210 : }
2211 : }
2212 :
2213 : // FastEmit functions for ISD::FP_TO_UINT.
2214 :
2215 0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2216 0 : if (RetVT.SimpleTy != MVT::v4i16)
2217 : return 0;
2218 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2219 0 : return fastEmitInst_r(ARM::VCVTh2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
2220 : }
2221 : return 0;
2222 : }
2223 :
2224 0 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2225 0 : if (RetVT.SimpleTy != MVT::v8i16)
2226 : return 0;
2227 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2228 0 : return fastEmitInst_r(ARM::VCVTh2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
2229 : }
2230 : return 0;
2231 : }
2232 :
2233 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2234 0 : if (RetVT.SimpleTy != MVT::v2i32)
2235 : return 0;
2236 0 : if ((Subtarget->hasNEON())) {
2237 0 : return fastEmitInst_r(ARM::VCVTf2ud, &ARM::DPRRegClass, Op0, Op0IsKill);
2238 : }
2239 : return 0;
2240 : }
2241 :
2242 : unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2243 0 : if (RetVT.SimpleTy != MVT::v4i32)
2244 : return 0;
2245 0 : if ((Subtarget->hasNEON())) {
2246 0 : return fastEmitInst_r(ARM::VCVTf2uq, &ARM::QPRRegClass, Op0, Op0IsKill);
2247 : }
2248 : return 0;
2249 : }
2250 :
2251 0 : unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2252 0 : switch (VT.SimpleTy) {
2253 0 : case MVT::v4f16: return fastEmit_ISD_FP_TO_UINT_MVT_v4f16_r(RetVT, Op0, Op0IsKill);
2254 0 : case MVT::v8f16: return fastEmit_ISD_FP_TO_UINT_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2255 0 : case MVT::v2f32: return fastEmit_ISD_FP_TO_UINT_MVT_v2f32_r(RetVT, Op0, Op0IsKill);
2256 0 : case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
2257 : default: return 0;
2258 : }
2259 : }
2260 :
2261 : // FastEmit functions for ISD::FRINT.
2262 :
2263 : unsigned fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2264 0 : if (RetVT.SimpleTy != MVT::f32)
2265 : return 0;
2266 0 : if ((Subtarget->hasFPARMv8())) {
2267 0 : return fastEmitInst_r(ARM::VRINTXS, &ARM::SPRRegClass, Op0, Op0IsKill);
2268 : }
2269 : return 0;
2270 : }
2271 :
2272 0 : unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2273 0 : if (RetVT.SimpleTy != MVT::f64)
2274 : return 0;
2275 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2276 0 : return fastEmitInst_r(ARM::VRINTXD, &ARM::DPRRegClass, Op0, Op0IsKill);
2277 : }
2278 : return 0;
2279 : }
2280 :
2281 0 : unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2282 0 : switch (VT.SimpleTy) {
2283 0 : case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2284 0 : case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2285 : default: return 0;
2286 : }
2287 : }
2288 :
2289 : // FastEmit functions for ISD::FROUND.
2290 :
2291 : unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2292 0 : if (RetVT.SimpleTy != MVT::f32)
2293 : return 0;
2294 0 : if ((Subtarget->hasFPARMv8())) {
2295 0 : return fastEmitInst_r(ARM::VRINTAS, &ARM::SPRRegClass, Op0, Op0IsKill);
2296 : }
2297 : return 0;
2298 : }
2299 :
2300 0 : unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2301 0 : if (RetVT.SimpleTy != MVT::f64)
2302 : return 0;
2303 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2304 0 : return fastEmitInst_r(ARM::VRINTAD, &ARM::DPRRegClass, Op0, Op0IsKill);
2305 : }
2306 : return 0;
2307 : }
2308 :
2309 0 : unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2310 0 : switch (VT.SimpleTy) {
2311 0 : case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
2312 0 : case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
2313 : default: return 0;
2314 : }
2315 : }
2316 :
2317 : // FastEmit functions for ISD::FSQRT.
2318 :
2319 : unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2320 0 : if (RetVT.SimpleTy != MVT::f32)
2321 : return 0;
2322 0 : if ((Subtarget->hasVFP2())) {
2323 0 : return fastEmitInst_r(ARM::VSQRTS, &ARM::SPRRegClass, Op0, Op0IsKill);
2324 : }
2325 : return 0;
2326 : }
2327 :
2328 0 : unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2329 0 : if (RetVT.SimpleTy != MVT::f64)
2330 : return 0;
2331 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
2332 0 : return fastEmitInst_r(ARM::VSQRTD, &ARM::DPRRegClass, Op0, Op0IsKill);
2333 : }
2334 : return 0;
2335 : }
2336 :
2337 0 : unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2338 0 : switch (VT.SimpleTy) {
2339 0 : case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
2340 0 : case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
2341 : default: return 0;
2342 : }
2343 : }
2344 :
2345 : // FastEmit functions for ISD::FTRUNC.
2346 :
2347 : unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2348 0 : if (RetVT.SimpleTy != MVT::f32)
2349 : return 0;
2350 0 : if ((Subtarget->hasFPARMv8())) {
2351 0 : return fastEmitInst_r(ARM::VRINTZS, &ARM::SPRRegClass, Op0, Op0IsKill);
2352 : }
2353 : return 0;
2354 : }
2355 :
2356 0 : unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2357 0 : if (RetVT.SimpleTy != MVT::f64)
2358 : return 0;
2359 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
2360 0 : return fastEmitInst_r(ARM::VRINTZD, &ARM::DPRRegClass, Op0, Op0IsKill);
2361 : }
2362 : return 0;
2363 : }
2364 :
2365 0 : unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2366 0 : switch (VT.SimpleTy) {
2367 0 : case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0, Op0IsKill);
2368 0 : case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0, Op0IsKill);
2369 : default: return 0;
2370 : }
2371 : }
2372 :
2373 : // FastEmit functions for ISD::SIGN_EXTEND.
2374 :
2375 : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2376 0 : if (RetVT.SimpleTy != MVT::v8i16)
2377 : return 0;
2378 0 : if ((Subtarget->hasNEON())) {
2379 0 : return fastEmitInst_r(ARM::VMOVLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
2380 : }
2381 : return 0;
2382 : }
2383 :
2384 : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2385 0 : if (RetVT.SimpleTy != MVT::v4i32)
2386 : return 0;
2387 0 : if ((Subtarget->hasNEON())) {
2388 0 : return fastEmitInst_r(ARM::VMOVLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
2389 : }
2390 : return 0;
2391 : }
2392 :
2393 : unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2394 0 : if (RetVT.SimpleTy != MVT::v2i64)
2395 : return 0;
2396 0 : if ((Subtarget->hasNEON())) {
2397 0 : return fastEmitInst_r(ARM::VMOVLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
2398 : }
2399 : return 0;
2400 : }
2401 :
2402 1 : unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2403 1 : switch (VT.SimpleTy) {
2404 0 : case MVT::v8i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
2405 0 : case MVT::v4i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2406 0 : case MVT::v2i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2407 : default: return 0;
2408 : }
2409 : }
2410 :
2411 : // FastEmit functions for ISD::SINT_TO_FP.
2412 :
2413 0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2414 0 : if (RetVT.SimpleTy != MVT::v4f16)
2415 : return 0;
2416 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2417 0 : return fastEmitInst_r(ARM::VCVTs2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
2418 : }
2419 : return 0;
2420 : }
2421 :
2422 0 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2423 0 : if (RetVT.SimpleTy != MVT::v8f16)
2424 : return 0;
2425 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2426 0 : return fastEmitInst_r(ARM::VCVTs2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
2427 : }
2428 : return 0;
2429 : }
2430 :
2431 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2432 0 : if (RetVT.SimpleTy != MVT::v2f32)
2433 : return 0;
2434 0 : if ((Subtarget->hasNEON())) {
2435 0 : return fastEmitInst_r(ARM::VCVTs2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
2436 : }
2437 : return 0;
2438 : }
2439 :
2440 : unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2441 2 : if (RetVT.SimpleTy != MVT::v4f32)
2442 : return 0;
2443 2 : if ((Subtarget->hasNEON())) {
2444 2 : return fastEmitInst_r(ARM::VCVTs2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
2445 : }
2446 : return 0;
2447 : }
2448 :
2449 9 : unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2450 9 : switch (VT.SimpleTy) {
2451 0 : case MVT::v4i16: return fastEmit_ISD_SINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2452 0 : case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
2453 0 : case MVT::v2i32: return fastEmit_ISD_SINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2454 2 : case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
2455 : default: return 0;
2456 : }
2457 : }
2458 :
2459 : // FastEmit functions for ISD::TRUNCATE.
2460 :
2461 : unsigned fastEmit_ISD_TRUNCATE_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2462 0 : if (RetVT.SimpleTy != MVT::v8i8)
2463 : return 0;
2464 0 : if ((Subtarget->hasNEON())) {
2465 0 : return fastEmitInst_r(ARM::VMOVNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill);
2466 : }
2467 : return 0;
2468 : }
2469 :
2470 : unsigned fastEmit_ISD_TRUNCATE_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2471 0 : if (RetVT.SimpleTy != MVT::v4i16)
2472 : return 0;
2473 0 : if ((Subtarget->hasNEON())) {
2474 0 : return fastEmitInst_r(ARM::VMOVNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill);
2475 : }
2476 : return 0;
2477 : }
2478 :
2479 : unsigned fastEmit_ISD_TRUNCATE_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2480 0 : if (RetVT.SimpleTy != MVT::v2i32)
2481 : return 0;
2482 0 : if ((Subtarget->hasNEON())) {
2483 0 : return fastEmitInst_r(ARM::VMOVNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill);
2484 : }
2485 : return 0;
2486 : }
2487 :
2488 0 : unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2489 0 : switch (VT.SimpleTy) {
2490 0 : case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
2491 0 : case MVT::v4i32: return fastEmit_ISD_TRUNCATE_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
2492 0 : case MVT::v2i64: return fastEmit_ISD_TRUNCATE_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
2493 : default: return 0;
2494 : }
2495 : }
2496 :
2497 : // FastEmit functions for ISD::UINT_TO_FP.
2498 :
2499 0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2500 0 : if (RetVT.SimpleTy != MVT::v4f16)
2501 : return 0;
2502 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2503 0 : return fastEmitInst_r(ARM::VCVTu2hd, &ARM::DPRRegClass, Op0, Op0IsKill);
2504 : }
2505 : return 0;
2506 : }
2507 :
2508 0 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2509 0 : if (RetVT.SimpleTy != MVT::v8f16)
2510 : return 0;
2511 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2512 0 : return fastEmitInst_r(ARM::VCVTu2hq, &ARM::QPRRegClass, Op0, Op0IsKill);
2513 : }
2514 : return 0;
2515 : }
2516 :
2517 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2518 0 : if (RetVT.SimpleTy != MVT::v2f32)
2519 : return 0;
2520 0 : if ((Subtarget->hasNEON())) {
2521 0 : return fastEmitInst_r(ARM::VCVTu2fd, &ARM::DPRRegClass, Op0, Op0IsKill);
2522 : }
2523 : return 0;
2524 : }
2525 :
2526 : unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2527 0 : if (RetVT.SimpleTy != MVT::v4f32)
2528 : return 0;
2529 0 : if ((Subtarget->hasNEON())) {
2530 0 : return fastEmitInst_r(ARM::VCVTu2fq, &ARM::QPRRegClass, Op0, Op0IsKill);
2531 : }
2532 : return 0;
2533 : }
2534 :
2535 0 : unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2536 0 : switch (VT.SimpleTy) {
2537 0 : case MVT::v4i16: return fastEmit_ISD_UINT_TO_FP_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2538 0 : case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
2539 0 : case MVT::v2i32: return fastEmit_ISD_UINT_TO_FP_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2540 0 : case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
2541 : default: return 0;
2542 : }
2543 : }
2544 :
2545 : // FastEmit functions for ISD::ZERO_EXTEND.
2546 :
2547 : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2548 0 : if (RetVT.SimpleTy != MVT::v8i16)
2549 : return 0;
2550 0 : if ((Subtarget->hasNEON())) {
2551 0 : return fastEmitInst_r(ARM::VMOVLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill);
2552 : }
2553 : return 0;
2554 : }
2555 :
2556 : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2557 0 : if (RetVT.SimpleTy != MVT::v4i32)
2558 : return 0;
2559 0 : if ((Subtarget->hasNEON())) {
2560 0 : return fastEmitInst_r(ARM::VMOVLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill);
2561 : }
2562 : return 0;
2563 : }
2564 :
2565 : unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
2566 0 : if (RetVT.SimpleTy != MVT::v2i64)
2567 : return 0;
2568 0 : if ((Subtarget->hasNEON())) {
2569 0 : return fastEmitInst_r(ARM::VMOVLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill);
2570 : }
2571 : return 0;
2572 : }
2573 :
2574 0 : unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
2575 0 : switch (VT.SimpleTy) {
2576 0 : case MVT::v8i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i8_r(RetVT, Op0, Op0IsKill);
2577 0 : case MVT::v4i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i16_r(RetVT, Op0, Op0IsKill);
2578 0 : case MVT::v2i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
2579 : default: return 0;
2580 : }
2581 : }
2582 :
2583 : // Top-level FastEmit function.
2584 :
2585 99 : unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
2586 99 : switch (Opcode) {
2587 0 : case ARMISD::CALL: return fastEmit_ARMISD_CALL_r(VT, RetVT, Op0, Op0IsKill);
2588 0 : case ARMISD::CALL_NOLINK: return fastEmit_ARMISD_CALL_NOLINK_r(VT, RetVT, Op0, Op0IsKill);
2589 0 : case ARMISD::CALL_PRED: return fastEmit_ARMISD_CALL_PRED_r(VT, RetVT, Op0, Op0IsKill);
2590 0 : case ARMISD::RRX: return fastEmit_ARMISD_RRX_r(VT, RetVT, Op0, Op0IsKill);
2591 0 : case ARMISD::SRA_FLAG: return fastEmit_ARMISD_SRA_FLAG_r(VT, RetVT, Op0, Op0IsKill);
2592 0 : case ARMISD::SRL_FLAG: return fastEmit_ARMISD_SRL_FLAG_r(VT, RetVT, Op0, Op0IsKill);
2593 0 : case ARMISD::TC_RETURN: return fastEmit_ARMISD_TC_RETURN_r(VT, RetVT, Op0, Op0IsKill);
2594 0 : case ARMISD::VCEQZ: return fastEmit_ARMISD_VCEQZ_r(VT, RetVT, Op0, Op0IsKill);
2595 0 : case ARMISD::VCGEZ: return fastEmit_ARMISD_VCGEZ_r(VT, RetVT, Op0, Op0IsKill);
2596 0 : case ARMISD::VCGTZ: return fastEmit_ARMISD_VCGTZ_r(VT, RetVT, Op0, Op0IsKill);
2597 0 : case ARMISD::VCLEZ: return fastEmit_ARMISD_VCLEZ_r(VT, RetVT, Op0, Op0IsKill);
2598 0 : case ARMISD::VCLTZ: return fastEmit_ARMISD_VCLTZ_r(VT, RetVT, Op0, Op0IsKill);
2599 0 : case ARMISD::VDUP: return fastEmit_ARMISD_VDUP_r(VT, RetVT, Op0, Op0IsKill);
2600 0 : case ARMISD::VMOVSR: return fastEmit_ARMISD_VMOVSR_r(VT, RetVT, Op0, Op0IsKill);
2601 0 : case ARMISD::VMOVhr: return fastEmit_ARMISD_VMOVhr_r(VT, RetVT, Op0, Op0IsKill);
2602 0 : case ARMISD::VMOVrh: return fastEmit_ARMISD_VMOVrh_r(VT, RetVT, Op0, Op0IsKill);
2603 0 : case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill);
2604 0 : case ARMISD::VREV32: return fastEmit_ARMISD_VREV32_r(VT, RetVT, Op0, Op0IsKill);
2605 0 : case ARMISD::VREV64: return fastEmit_ARMISD_VREV64_r(VT, RetVT, Op0, Op0IsKill);
2606 0 : case ARMISD::WIN__DBZCHK: return fastEmit_ARMISD_WIN__DBZCHK_r(VT, RetVT, Op0, Op0IsKill);
2607 0 : case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0, Op0IsKill);
2608 0 : case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
2609 83 : case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
2610 0 : case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill);
2611 0 : case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
2612 0 : case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0, Op0IsKill);
2613 0 : case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
2614 0 : case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
2615 0 : case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
2616 0 : case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
2617 0 : case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
2618 0 : case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0, Op0IsKill);
2619 0 : case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
2620 0 : case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
2621 0 : case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
2622 6 : case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
2623 0 : case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
2624 0 : case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
2625 0 : case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0, Op0IsKill);
2626 0 : case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
2627 0 : case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
2628 1 : case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
2629 9 : case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
2630 0 : case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0, Op0IsKill);
2631 0 : case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
2632 0 : case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
2633 : default: return 0;
2634 : }
2635 : }
2636 :
2637 : // FastEmit functions for ARMISD::CMP.
2638 :
2639 0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2640 0 : if (RetVT.SimpleTy != MVT::isVoid)
2641 : return 0;
2642 0 : if ((Subtarget->isThumb2())) {
2643 0 : return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2644 : }
2645 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2646 0 : return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2647 : }
2648 0 : if ((!Subtarget->isThumb())) {
2649 0 : return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2650 : }
2651 : return 0;
2652 : }
2653 :
2654 : unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2655 0 : switch (VT.SimpleTy) {
2656 0 : case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2657 : default: return 0;
2658 : }
2659 : }
2660 :
2661 : // FastEmit functions for ARMISD::CMPZ.
2662 :
2663 0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2664 0 : if (RetVT.SimpleTy != MVT::isVoid)
2665 : return 0;
2666 0 : if ((Subtarget->isThumb2())) {
2667 0 : return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2668 : }
2669 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2670 0 : return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2671 : }
2672 0 : if ((!Subtarget->isThumb())) {
2673 0 : return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2674 : }
2675 : return 0;
2676 : }
2677 :
2678 : unsigned fastEmit_ARMISD_CMPZ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2679 0 : switch (VT.SimpleTy) {
2680 0 : case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2681 : default: return 0;
2682 : }
2683 : }
2684 :
2685 : // FastEmit functions for ARMISD::EH_SJLJ_LONGJMP.
2686 :
2687 0 : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2688 0 : if (RetVT.SimpleTy != MVT::isVoid)
2689 : return 0;
2690 0 : if ((Subtarget->isThumb()) && (Subtarget->isTargetWindows())) {
2691 0 : return fastEmitInst_rr(ARM::tInt_WIN_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2692 : }
2693 0 : if ((!Subtarget->isTargetWindows()) && (Subtarget->isThumb())) {
2694 0 : return fastEmitInst_rr(ARM::tInt_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2695 : }
2696 0 : if ((!Subtarget->isThumb())) {
2697 0 : return fastEmitInst_rr(ARM::Int_eh_sjlj_longjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2698 : }
2699 : return 0;
2700 : }
2701 :
2702 : unsigned fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2703 0 : switch (VT.SimpleTy) {
2704 0 : case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2705 : default: return 0;
2706 : }
2707 : }
2708 :
2709 : // FastEmit functions for ARMISD::EH_SJLJ_SETJMP.
2710 :
2711 0 : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2712 0 : if (RetVT.SimpleTy != MVT::i32)
2713 : return 0;
2714 0 : if ((Subtarget->isThumb2()) && (!Subtarget->hasVFP2())) {
2715 0 : return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp_nofp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2716 : }
2717 0 : if ((Subtarget->hasVFP2()) && (Subtarget->isThumb2())) {
2718 0 : return fastEmitInst_rr(ARM::t2Int_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2719 : }
2720 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
2721 0 : return fastEmitInst_rr(ARM::tInt_eh_sjlj_setjmp, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2722 : }
2723 0 : if ((!Subtarget->isThumb()) && (!Subtarget->hasVFP2())) {
2724 0 : return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp_nofp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2725 : }
2726 0 : if ((Subtarget->hasVFP2()) && (!Subtarget->isThumb())) {
2727 0 : return fastEmitInst_rr(ARM::Int_eh_sjlj_setjmp, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2728 : }
2729 : return 0;
2730 : }
2731 :
2732 : unsigned fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2733 0 : switch (VT.SimpleTy) {
2734 0 : case MVT::i32: return fastEmit_ARMISD_EH_SJLJ_SETJMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2735 : default: return 0;
2736 : }
2737 : }
2738 :
2739 : // FastEmit functions for ARMISD::SMULWB.
2740 :
2741 0 : unsigned fastEmit_ARMISD_SMULWB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2742 0 : if (RetVT.SimpleTy != MVT::i32)
2743 : return 0;
2744 0 : if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
2745 0 : return fastEmitInst_rr(ARM::t2SMULWB, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2746 : }
2747 0 : if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
2748 0 : return fastEmitInst_rr(ARM::SMULWB, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2749 : }
2750 : return 0;
2751 : }
2752 :
2753 : unsigned fastEmit_ARMISD_SMULWB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2754 0 : switch (VT.SimpleTy) {
2755 0 : case MVT::i32: return fastEmit_ARMISD_SMULWB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2756 : default: return 0;
2757 : }
2758 : }
2759 :
2760 : // FastEmit functions for ARMISD::SMULWT.
2761 :
2762 0 : unsigned fastEmit_ARMISD_SMULWT_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2763 0 : if (RetVT.SimpleTy != MVT::i32)
2764 : return 0;
2765 0 : if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
2766 0 : return fastEmitInst_rr(ARM::t2SMULWT, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2767 : }
2768 0 : if ((Subtarget->hasV5TEOps()) && (!Subtarget->isThumb())) {
2769 0 : return fastEmitInst_rr(ARM::SMULWT, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2770 : }
2771 : return 0;
2772 : }
2773 :
2774 : unsigned fastEmit_ARMISD_SMULWT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2775 0 : switch (VT.SimpleTy) {
2776 0 : case MVT::i32: return fastEmit_ARMISD_SMULWT_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2777 : default: return 0;
2778 : }
2779 : }
2780 :
2781 : // FastEmit functions for ARMISD::VCEQ.
2782 :
2783 : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2784 0 : if (RetVT.SimpleTy != MVT::v8i8)
2785 : return 0;
2786 0 : if ((Subtarget->hasNEON())) {
2787 0 : return fastEmitInst_rr(ARM::VCEQv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2788 : }
2789 : return 0;
2790 : }
2791 :
2792 : unsigned fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2793 0 : if (RetVT.SimpleTy != MVT::v16i8)
2794 : return 0;
2795 0 : if ((Subtarget->hasNEON())) {
2796 0 : return fastEmitInst_rr(ARM::VCEQv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2797 : }
2798 : return 0;
2799 : }
2800 :
2801 : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2802 0 : if (RetVT.SimpleTy != MVT::v4i16)
2803 : return 0;
2804 0 : if ((Subtarget->hasNEON())) {
2805 0 : return fastEmitInst_rr(ARM::VCEQv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2806 : }
2807 : return 0;
2808 : }
2809 :
2810 : unsigned fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2811 0 : if (RetVT.SimpleTy != MVT::v8i16)
2812 : return 0;
2813 0 : if ((Subtarget->hasNEON())) {
2814 0 : return fastEmitInst_rr(ARM::VCEQv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2815 : }
2816 : return 0;
2817 : }
2818 :
2819 : unsigned fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2820 0 : if (RetVT.SimpleTy != MVT::v2i32)
2821 : return 0;
2822 0 : if ((Subtarget->hasNEON())) {
2823 0 : return fastEmitInst_rr(ARM::VCEQv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2824 : }
2825 : return 0;
2826 : }
2827 :
2828 : unsigned fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2829 0 : if (RetVT.SimpleTy != MVT::v4i32)
2830 : return 0;
2831 0 : if ((Subtarget->hasNEON())) {
2832 0 : return fastEmitInst_rr(ARM::VCEQv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2833 : }
2834 : return 0;
2835 : }
2836 :
2837 0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2838 0 : if (RetVT.SimpleTy != MVT::v4i16)
2839 : return 0;
2840 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2841 0 : return fastEmitInst_rr(ARM::VCEQhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2842 : }
2843 : return 0;
2844 : }
2845 :
2846 0 : unsigned fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2847 0 : if (RetVT.SimpleTy != MVT::v8i16)
2848 : return 0;
2849 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2850 0 : return fastEmitInst_rr(ARM::VCEQhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2851 : }
2852 : return 0;
2853 : }
2854 :
2855 : unsigned fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2856 0 : if (RetVT.SimpleTy != MVT::v2i32)
2857 : return 0;
2858 0 : if ((Subtarget->hasNEON())) {
2859 0 : return fastEmitInst_rr(ARM::VCEQfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2860 : }
2861 : return 0;
2862 : }
2863 :
2864 : unsigned fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2865 0 : if (RetVT.SimpleTy != MVT::v4i32)
2866 : return 0;
2867 0 : if ((Subtarget->hasNEON())) {
2868 0 : return fastEmitInst_rr(ARM::VCEQfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2869 : }
2870 : return 0;
2871 : }
2872 :
2873 0 : unsigned fastEmit_ARMISD_VCEQ_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2874 0 : switch (VT.SimpleTy) {
2875 0 : case MVT::v8i8: return fastEmit_ARMISD_VCEQ_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2876 0 : case MVT::v16i8: return fastEmit_ARMISD_VCEQ_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2877 0 : case MVT::v4i16: return fastEmit_ARMISD_VCEQ_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2878 0 : case MVT::v8i16: return fastEmit_ARMISD_VCEQ_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2879 0 : case MVT::v2i32: return fastEmit_ARMISD_VCEQ_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2880 0 : case MVT::v4i32: return fastEmit_ARMISD_VCEQ_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2881 0 : case MVT::v4f16: return fastEmit_ARMISD_VCEQ_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2882 0 : case MVT::v8f16: return fastEmit_ARMISD_VCEQ_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2883 0 : case MVT::v2f32: return fastEmit_ARMISD_VCEQ_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2884 0 : case MVT::v4f32: return fastEmit_ARMISD_VCEQ_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2885 : default: return 0;
2886 : }
2887 : }
2888 :
2889 : // FastEmit functions for ARMISD::VCGE.
2890 :
2891 : unsigned fastEmit_ARMISD_VCGE_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2892 0 : if (RetVT.SimpleTy != MVT::v8i8)
2893 : return 0;
2894 0 : if ((Subtarget->hasNEON())) {
2895 0 : return fastEmitInst_rr(ARM::VCGEsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2896 : }
2897 : return 0;
2898 : }
2899 :
2900 : unsigned fastEmit_ARMISD_VCGE_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2901 0 : if (RetVT.SimpleTy != MVT::v16i8)
2902 : return 0;
2903 0 : if ((Subtarget->hasNEON())) {
2904 0 : return fastEmitInst_rr(ARM::VCGEsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2905 : }
2906 : return 0;
2907 : }
2908 :
2909 : unsigned fastEmit_ARMISD_VCGE_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2910 0 : if (RetVT.SimpleTy != MVT::v4i16)
2911 : return 0;
2912 0 : if ((Subtarget->hasNEON())) {
2913 0 : return fastEmitInst_rr(ARM::VCGEsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2914 : }
2915 : return 0;
2916 : }
2917 :
2918 : unsigned fastEmit_ARMISD_VCGE_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2919 0 : if (RetVT.SimpleTy != MVT::v8i16)
2920 : return 0;
2921 0 : if ((Subtarget->hasNEON())) {
2922 0 : return fastEmitInst_rr(ARM::VCGEsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2923 : }
2924 : return 0;
2925 : }
2926 :
2927 : unsigned fastEmit_ARMISD_VCGE_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2928 0 : if (RetVT.SimpleTy != MVT::v2i32)
2929 : return 0;
2930 0 : if ((Subtarget->hasNEON())) {
2931 0 : return fastEmitInst_rr(ARM::VCGEsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2932 : }
2933 : return 0;
2934 : }
2935 :
2936 : unsigned fastEmit_ARMISD_VCGE_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2937 0 : if (RetVT.SimpleTy != MVT::v4i32)
2938 : return 0;
2939 0 : if ((Subtarget->hasNEON())) {
2940 0 : return fastEmitInst_rr(ARM::VCGEsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2941 : }
2942 : return 0;
2943 : }
2944 :
2945 0 : unsigned fastEmit_ARMISD_VCGE_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2946 0 : if (RetVT.SimpleTy != MVT::v4i16)
2947 : return 0;
2948 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2949 0 : return fastEmitInst_rr(ARM::VCGEhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2950 : }
2951 : return 0;
2952 : }
2953 :
2954 0 : unsigned fastEmit_ARMISD_VCGE_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2955 0 : if (RetVT.SimpleTy != MVT::v8i16)
2956 : return 0;
2957 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
2958 0 : return fastEmitInst_rr(ARM::VCGEhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2959 : }
2960 : return 0;
2961 : }
2962 :
2963 : unsigned fastEmit_ARMISD_VCGE_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2964 0 : if (RetVT.SimpleTy != MVT::v2i32)
2965 : return 0;
2966 0 : if ((Subtarget->hasNEON())) {
2967 0 : return fastEmitInst_rr(ARM::VCGEfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2968 : }
2969 : return 0;
2970 : }
2971 :
2972 : unsigned fastEmit_ARMISD_VCGE_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2973 0 : if (RetVT.SimpleTy != MVT::v4i32)
2974 : return 0;
2975 0 : if ((Subtarget->hasNEON())) {
2976 0 : return fastEmitInst_rr(ARM::VCGEfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2977 : }
2978 : return 0;
2979 : }
2980 :
2981 0 : unsigned fastEmit_ARMISD_VCGE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
2982 0 : switch (VT.SimpleTy) {
2983 0 : case MVT::v8i8: return fastEmit_ARMISD_VCGE_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2984 0 : case MVT::v16i8: return fastEmit_ARMISD_VCGE_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2985 0 : case MVT::v4i16: return fastEmit_ARMISD_VCGE_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2986 0 : case MVT::v8i16: return fastEmit_ARMISD_VCGE_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2987 0 : case MVT::v2i32: return fastEmit_ARMISD_VCGE_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2988 0 : case MVT::v4i32: return fastEmit_ARMISD_VCGE_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2989 0 : case MVT::v4f16: return fastEmit_ARMISD_VCGE_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2990 0 : case MVT::v8f16: return fastEmit_ARMISD_VCGE_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2991 0 : case MVT::v2f32: return fastEmit_ARMISD_VCGE_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2992 0 : case MVT::v4f32: return fastEmit_ARMISD_VCGE_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2993 : default: return 0;
2994 : }
2995 : }
2996 :
2997 : // FastEmit functions for ARMISD::VCGEU.
2998 :
2999 : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3000 0 : if (RetVT.SimpleTy != MVT::v8i8)
3001 : return 0;
3002 0 : if ((Subtarget->hasNEON())) {
3003 0 : return fastEmitInst_rr(ARM::VCGEuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3004 : }
3005 : return 0;
3006 : }
3007 :
3008 : unsigned fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3009 0 : if (RetVT.SimpleTy != MVT::v16i8)
3010 : return 0;
3011 0 : if ((Subtarget->hasNEON())) {
3012 0 : return fastEmitInst_rr(ARM::VCGEuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3013 : }
3014 : return 0;
3015 : }
3016 :
3017 : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3018 0 : if (RetVT.SimpleTy != MVT::v4i16)
3019 : return 0;
3020 0 : if ((Subtarget->hasNEON())) {
3021 0 : return fastEmitInst_rr(ARM::VCGEuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3022 : }
3023 : return 0;
3024 : }
3025 :
3026 : unsigned fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3027 0 : if (RetVT.SimpleTy != MVT::v8i16)
3028 : return 0;
3029 0 : if ((Subtarget->hasNEON())) {
3030 0 : return fastEmitInst_rr(ARM::VCGEuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3031 : }
3032 : return 0;
3033 : }
3034 :
3035 : unsigned fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3036 0 : if (RetVT.SimpleTy != MVT::v2i32)
3037 : return 0;
3038 0 : if ((Subtarget->hasNEON())) {
3039 0 : return fastEmitInst_rr(ARM::VCGEuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3040 : }
3041 : return 0;
3042 : }
3043 :
3044 : unsigned fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3045 0 : if (RetVT.SimpleTy != MVT::v4i32)
3046 : return 0;
3047 0 : if ((Subtarget->hasNEON())) {
3048 0 : return fastEmitInst_rr(ARM::VCGEuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3049 : }
3050 : return 0;
3051 : }
3052 :
3053 0 : unsigned fastEmit_ARMISD_VCGEU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3054 0 : switch (VT.SimpleTy) {
3055 0 : case MVT::v8i8: return fastEmit_ARMISD_VCGEU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3056 0 : case MVT::v16i8: return fastEmit_ARMISD_VCGEU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3057 0 : case MVT::v4i16: return fastEmit_ARMISD_VCGEU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3058 0 : case MVT::v8i16: return fastEmit_ARMISD_VCGEU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3059 0 : case MVT::v2i32: return fastEmit_ARMISD_VCGEU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3060 0 : case MVT::v4i32: return fastEmit_ARMISD_VCGEU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3061 : default: return 0;
3062 : }
3063 : }
3064 :
3065 : // FastEmit functions for ARMISD::VCGT.
3066 :
3067 : unsigned fastEmit_ARMISD_VCGT_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3068 0 : if (RetVT.SimpleTy != MVT::v8i8)
3069 : return 0;
3070 0 : if ((Subtarget->hasNEON())) {
3071 0 : return fastEmitInst_rr(ARM::VCGTsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3072 : }
3073 : return 0;
3074 : }
3075 :
3076 : unsigned fastEmit_ARMISD_VCGT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3077 0 : if (RetVT.SimpleTy != MVT::v16i8)
3078 : return 0;
3079 0 : if ((Subtarget->hasNEON())) {
3080 0 : return fastEmitInst_rr(ARM::VCGTsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3081 : }
3082 : return 0;
3083 : }
3084 :
3085 : unsigned fastEmit_ARMISD_VCGT_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3086 0 : if (RetVT.SimpleTy != MVT::v4i16)
3087 : return 0;
3088 0 : if ((Subtarget->hasNEON())) {
3089 0 : return fastEmitInst_rr(ARM::VCGTsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3090 : }
3091 : return 0;
3092 : }
3093 :
3094 : unsigned fastEmit_ARMISD_VCGT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3095 0 : if (RetVT.SimpleTy != MVT::v8i16)
3096 : return 0;
3097 0 : if ((Subtarget->hasNEON())) {
3098 0 : return fastEmitInst_rr(ARM::VCGTsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3099 : }
3100 : return 0;
3101 : }
3102 :
3103 : unsigned fastEmit_ARMISD_VCGT_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3104 0 : if (RetVT.SimpleTy != MVT::v2i32)
3105 : return 0;
3106 0 : if ((Subtarget->hasNEON())) {
3107 0 : return fastEmitInst_rr(ARM::VCGTsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3108 : }
3109 : return 0;
3110 : }
3111 :
3112 : unsigned fastEmit_ARMISD_VCGT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3113 0 : if (RetVT.SimpleTy != MVT::v4i32)
3114 : return 0;
3115 0 : if ((Subtarget->hasNEON())) {
3116 0 : return fastEmitInst_rr(ARM::VCGTsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3117 : }
3118 : return 0;
3119 : }
3120 :
3121 0 : unsigned fastEmit_ARMISD_VCGT_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3122 0 : if (RetVT.SimpleTy != MVT::v4i16)
3123 : return 0;
3124 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3125 0 : return fastEmitInst_rr(ARM::VCGThd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3126 : }
3127 : return 0;
3128 : }
3129 :
3130 0 : unsigned fastEmit_ARMISD_VCGT_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3131 0 : if (RetVT.SimpleTy != MVT::v8i16)
3132 : return 0;
3133 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3134 0 : return fastEmitInst_rr(ARM::VCGThq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3135 : }
3136 : return 0;
3137 : }
3138 :
3139 : unsigned fastEmit_ARMISD_VCGT_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3140 0 : if (RetVT.SimpleTy != MVT::v2i32)
3141 : return 0;
3142 0 : if ((Subtarget->hasNEON())) {
3143 0 : return fastEmitInst_rr(ARM::VCGTfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3144 : }
3145 : return 0;
3146 : }
3147 :
3148 : unsigned fastEmit_ARMISD_VCGT_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3149 0 : if (RetVT.SimpleTy != MVT::v4i32)
3150 : return 0;
3151 0 : if ((Subtarget->hasNEON())) {
3152 0 : return fastEmitInst_rr(ARM::VCGTfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3153 : }
3154 : return 0;
3155 : }
3156 :
3157 0 : unsigned fastEmit_ARMISD_VCGT_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3158 0 : switch (VT.SimpleTy) {
3159 0 : case MVT::v8i8: return fastEmit_ARMISD_VCGT_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3160 0 : case MVT::v16i8: return fastEmit_ARMISD_VCGT_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3161 0 : case MVT::v4i16: return fastEmit_ARMISD_VCGT_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3162 0 : case MVT::v8i16: return fastEmit_ARMISD_VCGT_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3163 0 : case MVT::v2i32: return fastEmit_ARMISD_VCGT_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3164 0 : case MVT::v4i32: return fastEmit_ARMISD_VCGT_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3165 0 : case MVT::v4f16: return fastEmit_ARMISD_VCGT_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3166 0 : case MVT::v8f16: return fastEmit_ARMISD_VCGT_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3167 0 : case MVT::v2f32: return fastEmit_ARMISD_VCGT_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3168 0 : case MVT::v4f32: return fastEmit_ARMISD_VCGT_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3169 : default: return 0;
3170 : }
3171 : }
3172 :
3173 : // FastEmit functions for ARMISD::VCGTU.
3174 :
3175 : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3176 0 : if (RetVT.SimpleTy != MVT::v8i8)
3177 : return 0;
3178 0 : if ((Subtarget->hasNEON())) {
3179 0 : return fastEmitInst_rr(ARM::VCGTuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3180 : }
3181 : return 0;
3182 : }
3183 :
3184 : unsigned fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3185 0 : if (RetVT.SimpleTy != MVT::v16i8)
3186 : return 0;
3187 0 : if ((Subtarget->hasNEON())) {
3188 0 : return fastEmitInst_rr(ARM::VCGTuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3189 : }
3190 : return 0;
3191 : }
3192 :
3193 : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3194 0 : if (RetVT.SimpleTy != MVT::v4i16)
3195 : return 0;
3196 0 : if ((Subtarget->hasNEON())) {
3197 0 : return fastEmitInst_rr(ARM::VCGTuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3198 : }
3199 : return 0;
3200 : }
3201 :
3202 : unsigned fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3203 0 : if (RetVT.SimpleTy != MVT::v8i16)
3204 : return 0;
3205 0 : if ((Subtarget->hasNEON())) {
3206 0 : return fastEmitInst_rr(ARM::VCGTuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3207 : }
3208 : return 0;
3209 : }
3210 :
3211 : unsigned fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3212 0 : if (RetVT.SimpleTy != MVT::v2i32)
3213 : return 0;
3214 0 : if ((Subtarget->hasNEON())) {
3215 0 : return fastEmitInst_rr(ARM::VCGTuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3216 : }
3217 : return 0;
3218 : }
3219 :
3220 : unsigned fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3221 0 : if (RetVT.SimpleTy != MVT::v4i32)
3222 : return 0;
3223 0 : if ((Subtarget->hasNEON())) {
3224 0 : return fastEmitInst_rr(ARM::VCGTuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3225 : }
3226 : return 0;
3227 : }
3228 :
3229 0 : unsigned fastEmit_ARMISD_VCGTU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3230 0 : switch (VT.SimpleTy) {
3231 0 : case MVT::v8i8: return fastEmit_ARMISD_VCGTU_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3232 0 : case MVT::v16i8: return fastEmit_ARMISD_VCGTU_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3233 0 : case MVT::v4i16: return fastEmit_ARMISD_VCGTU_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3234 0 : case MVT::v8i16: return fastEmit_ARMISD_VCGTU_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3235 0 : case MVT::v2i32: return fastEmit_ARMISD_VCGTU_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3236 0 : case MVT::v4i32: return fastEmit_ARMISD_VCGTU_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3237 : default: return 0;
3238 : }
3239 : }
3240 :
3241 : // FastEmit functions for ARMISD::VMOVDRR.
3242 :
3243 : unsigned fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3244 0 : if (RetVT.SimpleTy != MVT::f64)
3245 : return 0;
3246 0 : if ((Subtarget->hasVFP2())) {
3247 0 : return fastEmitInst_rr(ARM::VMOVDRR, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3248 : }
3249 : return 0;
3250 : }
3251 :
3252 0 : unsigned fastEmit_ARMISD_VMOVDRR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3253 0 : switch (VT.SimpleTy) {
3254 0 : case MVT::i32: return fastEmit_ARMISD_VMOVDRR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3255 : default: return 0;
3256 : }
3257 : }
3258 :
3259 : // FastEmit functions for ARMISD::VMULLs.
3260 :
3261 : unsigned fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3262 0 : if (RetVT.SimpleTy != MVT::v8i16)
3263 : return 0;
3264 0 : if ((Subtarget->hasNEON())) {
3265 0 : return fastEmitInst_rr(ARM::VMULLsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3266 : }
3267 : return 0;
3268 : }
3269 :
3270 : unsigned fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3271 0 : if (RetVT.SimpleTy != MVT::v4i32)
3272 : return 0;
3273 0 : if ((Subtarget->hasNEON())) {
3274 0 : return fastEmitInst_rr(ARM::VMULLsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3275 : }
3276 : return 0;
3277 : }
3278 :
3279 : unsigned fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3280 0 : if (RetVT.SimpleTy != MVT::v2i64)
3281 : return 0;
3282 0 : if ((Subtarget->hasNEON())) {
3283 0 : return fastEmitInst_rr(ARM::VMULLsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3284 : }
3285 : return 0;
3286 : }
3287 :
3288 0 : unsigned fastEmit_ARMISD_VMULLs_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3289 0 : switch (VT.SimpleTy) {
3290 0 : case MVT::v8i8: return fastEmit_ARMISD_VMULLs_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3291 0 : case MVT::v4i16: return fastEmit_ARMISD_VMULLs_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3292 0 : case MVT::v2i32: return fastEmit_ARMISD_VMULLs_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3293 : default: return 0;
3294 : }
3295 : }
3296 :
3297 : // FastEmit functions for ARMISD::VMULLu.
3298 :
3299 : unsigned fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3300 0 : if (RetVT.SimpleTy != MVT::v8i16)
3301 : return 0;
3302 0 : if ((Subtarget->hasNEON())) {
3303 0 : return fastEmitInst_rr(ARM::VMULLuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3304 : }
3305 : return 0;
3306 : }
3307 :
3308 : unsigned fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3309 0 : if (RetVT.SimpleTy != MVT::v4i32)
3310 : return 0;
3311 0 : if ((Subtarget->hasNEON())) {
3312 0 : return fastEmitInst_rr(ARM::VMULLuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3313 : }
3314 : return 0;
3315 : }
3316 :
3317 : unsigned fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3318 0 : if (RetVT.SimpleTy != MVT::v2i64)
3319 : return 0;
3320 0 : if ((Subtarget->hasNEON())) {
3321 0 : return fastEmitInst_rr(ARM::VMULLuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3322 : }
3323 : return 0;
3324 : }
3325 :
3326 0 : unsigned fastEmit_ARMISD_VMULLu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3327 0 : switch (VT.SimpleTy) {
3328 0 : case MVT::v8i8: return fastEmit_ARMISD_VMULLu_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3329 0 : case MVT::v4i16: return fastEmit_ARMISD_VMULLu_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3330 0 : case MVT::v2i32: return fastEmit_ARMISD_VMULLu_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3331 : default: return 0;
3332 : }
3333 : }
3334 :
3335 : // FastEmit functions for ARMISD::VTBL1.
3336 :
3337 : unsigned fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3338 0 : if (RetVT.SimpleTy != MVT::v8i8)
3339 : return 0;
3340 0 : if ((Subtarget->hasNEON())) {
3341 0 : return fastEmitInst_rr(ARM::VTBL1, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3342 : }
3343 : return 0;
3344 : }
3345 :
3346 0 : unsigned fastEmit_ARMISD_VTBL1_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3347 0 : switch (VT.SimpleTy) {
3348 0 : case MVT::v8i8: return fastEmit_ARMISD_VTBL1_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3349 : default: return 0;
3350 : }
3351 : }
3352 :
3353 : // FastEmit functions for ARMISD::VTST.
3354 :
3355 : unsigned fastEmit_ARMISD_VTST_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3356 0 : if (RetVT.SimpleTy != MVT::v8i8)
3357 : return 0;
3358 0 : if ((Subtarget->hasNEON())) {
3359 0 : return fastEmitInst_rr(ARM::VTSTv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3360 : }
3361 : return 0;
3362 : }
3363 :
3364 : unsigned fastEmit_ARMISD_VTST_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3365 0 : if (RetVT.SimpleTy != MVT::v16i8)
3366 : return 0;
3367 0 : if ((Subtarget->hasNEON())) {
3368 0 : return fastEmitInst_rr(ARM::VTSTv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3369 : }
3370 : return 0;
3371 : }
3372 :
3373 : unsigned fastEmit_ARMISD_VTST_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3374 0 : if (RetVT.SimpleTy != MVT::v4i16)
3375 : return 0;
3376 0 : if ((Subtarget->hasNEON())) {
3377 0 : return fastEmitInst_rr(ARM::VTSTv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3378 : }
3379 : return 0;
3380 : }
3381 :
3382 : unsigned fastEmit_ARMISD_VTST_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3383 0 : if (RetVT.SimpleTy != MVT::v8i16)
3384 : return 0;
3385 0 : if ((Subtarget->hasNEON())) {
3386 0 : return fastEmitInst_rr(ARM::VTSTv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3387 : }
3388 : return 0;
3389 : }
3390 :
3391 : unsigned fastEmit_ARMISD_VTST_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3392 0 : if (RetVT.SimpleTy != MVT::v2i32)
3393 : return 0;
3394 0 : if ((Subtarget->hasNEON())) {
3395 0 : return fastEmitInst_rr(ARM::VTSTv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3396 : }
3397 : return 0;
3398 : }
3399 :
3400 : unsigned fastEmit_ARMISD_VTST_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3401 0 : if (RetVT.SimpleTy != MVT::v4i32)
3402 : return 0;
3403 0 : if ((Subtarget->hasNEON())) {
3404 0 : return fastEmitInst_rr(ARM::VTSTv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3405 : }
3406 : return 0;
3407 : }
3408 :
3409 0 : unsigned fastEmit_ARMISD_VTST_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3410 0 : switch (VT.SimpleTy) {
3411 0 : case MVT::v8i8: return fastEmit_ARMISD_VTST_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3412 0 : case MVT::v16i8: return fastEmit_ARMISD_VTST_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3413 0 : case MVT::v4i16: return fastEmit_ARMISD_VTST_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3414 0 : case MVT::v8i16: return fastEmit_ARMISD_VTST_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3415 0 : case MVT::v2i32: return fastEmit_ARMISD_VTST_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3416 0 : case MVT::v4i32: return fastEmit_ARMISD_VTST_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3417 : default: return 0;
3418 : }
3419 : }
3420 :
3421 : // FastEmit functions for ISD::ADD.
3422 :
3423 94 : unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3424 94 : if (RetVT.SimpleTy != MVT::i32)
3425 : return 0;
3426 94 : if ((Subtarget->isThumb2())) {
3427 20 : return fastEmitInst_rr(ARM::t2ADDrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3428 : }
3429 74 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
3430 0 : return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3431 : }
3432 74 : if ((!Subtarget->isThumb())) {
3433 74 : return fastEmitInst_rr(ARM::ADDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3434 : }
3435 : return 0;
3436 : }
3437 :
3438 : unsigned fastEmit_ISD_ADD_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3439 0 : if (RetVT.SimpleTy != MVT::v8i8)
3440 : return 0;
3441 0 : if ((Subtarget->hasNEON())) {
3442 0 : return fastEmitInst_rr(ARM::VADDv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3443 : }
3444 : return 0;
3445 : }
3446 :
3447 : unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3448 0 : if (RetVT.SimpleTy != MVT::v16i8)
3449 : return 0;
3450 0 : if ((Subtarget->hasNEON())) {
3451 0 : return fastEmitInst_rr(ARM::VADDv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3452 : }
3453 : return 0;
3454 : }
3455 :
3456 : unsigned fastEmit_ISD_ADD_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3457 0 : if (RetVT.SimpleTy != MVT::v4i16)
3458 : return 0;
3459 0 : if ((Subtarget->hasNEON())) {
3460 0 : return fastEmitInst_rr(ARM::VADDv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3461 : }
3462 : return 0;
3463 : }
3464 :
3465 : unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3466 0 : if (RetVT.SimpleTy != MVT::v8i16)
3467 : return 0;
3468 0 : if ((Subtarget->hasNEON())) {
3469 0 : return fastEmitInst_rr(ARM::VADDv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3470 : }
3471 : return 0;
3472 : }
3473 :
3474 : unsigned fastEmit_ISD_ADD_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3475 0 : if (RetVT.SimpleTy != MVT::v2i32)
3476 : return 0;
3477 0 : if ((Subtarget->hasNEON())) {
3478 0 : return fastEmitInst_rr(ARM::VADDv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3479 : }
3480 : return 0;
3481 : }
3482 :
3483 : unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3484 0 : if (RetVT.SimpleTy != MVT::v4i32)
3485 : return 0;
3486 0 : if ((Subtarget->hasNEON())) {
3487 0 : return fastEmitInst_rr(ARM::VADDv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3488 : }
3489 : return 0;
3490 : }
3491 :
3492 : unsigned fastEmit_ISD_ADD_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3493 0 : if (RetVT.SimpleTy != MVT::v1i64)
3494 : return 0;
3495 0 : if ((Subtarget->hasNEON())) {
3496 0 : return fastEmitInst_rr(ARM::VADDv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3497 : }
3498 : return 0;
3499 : }
3500 :
3501 : unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3502 0 : if (RetVT.SimpleTy != MVT::v2i64)
3503 : return 0;
3504 0 : if ((Subtarget->hasNEON())) {
3505 0 : return fastEmitInst_rr(ARM::VADDv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3506 : }
3507 : return 0;
3508 : }
3509 :
3510 94 : unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3511 94 : switch (VT.SimpleTy) {
3512 94 : case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3513 0 : case MVT::v8i8: return fastEmit_ISD_ADD_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3514 0 : case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3515 0 : case MVT::v4i16: return fastEmit_ISD_ADD_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3516 0 : case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3517 0 : case MVT::v2i32: return fastEmit_ISD_ADD_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3518 0 : case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3519 0 : case MVT::v1i64: return fastEmit_ISD_ADD_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3520 0 : case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3521 : default: return 0;
3522 : }
3523 : }
3524 :
3525 : // FastEmit functions for ISD::AND.
3526 :
3527 0 : unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3528 0 : if (RetVT.SimpleTy != MVT::i32)
3529 : return 0;
3530 0 : if ((Subtarget->isThumb2())) {
3531 0 : return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3532 : }
3533 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
3534 0 : return fastEmitInst_rr(ARM::tAND, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3535 : }
3536 0 : if ((!Subtarget->isThumb())) {
3537 0 : return fastEmitInst_rr(ARM::ANDrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3538 : }
3539 : return 0;
3540 : }
3541 :
3542 : unsigned fastEmit_ISD_AND_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3543 0 : if (RetVT.SimpleTy != MVT::v2i32)
3544 : return 0;
3545 0 : if ((Subtarget->hasNEON())) {
3546 0 : return fastEmitInst_rr(ARM::VANDd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3547 : }
3548 : return 0;
3549 : }
3550 :
3551 : unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3552 0 : if (RetVT.SimpleTy != MVT::v4i32)
3553 : return 0;
3554 0 : if ((Subtarget->hasNEON())) {
3555 0 : return fastEmitInst_rr(ARM::VANDq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3556 : }
3557 : return 0;
3558 : }
3559 :
3560 0 : unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3561 0 : switch (VT.SimpleTy) {
3562 0 : case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3563 0 : case MVT::v2i32: return fastEmit_ISD_AND_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3564 0 : case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3565 : default: return 0;
3566 : }
3567 : }
3568 :
3569 : // FastEmit functions for ISD::FADD.
3570 :
3571 : unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3572 0 : if (RetVT.SimpleTy != MVT::f16)
3573 : return 0;
3574 0 : if ((Subtarget->hasFullFP16())) {
3575 0 : return fastEmitInst_rr(ARM::VADDH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3576 : }
3577 : return 0;
3578 : }
3579 :
3580 17 : unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3581 17 : if (RetVT.SimpleTy != MVT::f32)
3582 : return 0;
3583 34 : if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
3584 17 : return fastEmitInst_rr(ARM::VADDS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3585 : }
3586 : return 0;
3587 : }
3588 :
3589 15 : unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3590 15 : if (RetVT.SimpleTy != MVT::f64)
3591 : return 0;
3592 15 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
3593 14 : return fastEmitInst_rr(ARM::VADDD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3594 : }
3595 : return 0;
3596 : }
3597 :
3598 0 : unsigned fastEmit_ISD_FADD_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3599 0 : if (RetVT.SimpleTy != MVT::v4f16)
3600 : return 0;
3601 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3602 0 : return fastEmitInst_rr(ARM::VADDhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3603 : }
3604 : return 0;
3605 : }
3606 :
3607 0 : unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3608 0 : if (RetVT.SimpleTy != MVT::v8f16)
3609 : return 0;
3610 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3611 0 : return fastEmitInst_rr(ARM::VADDhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3612 : }
3613 : return 0;
3614 : }
3615 :
3616 : unsigned fastEmit_ISD_FADD_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3617 0 : if (RetVT.SimpleTy != MVT::v2f32)
3618 : return 0;
3619 0 : if ((Subtarget->hasNEON())) {
3620 0 : return fastEmitInst_rr(ARM::VADDfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3621 : }
3622 : return 0;
3623 : }
3624 :
3625 : unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3626 0 : if (RetVT.SimpleTy != MVT::v4f32)
3627 : return 0;
3628 0 : if ((Subtarget->hasNEON())) {
3629 0 : return fastEmitInst_rr(ARM::VADDfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3630 : }
3631 : return 0;
3632 : }
3633 :
3634 33 : unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3635 33 : switch (VT.SimpleTy) {
3636 0 : case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3637 17 : case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3638 15 : case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3639 0 : case MVT::v4f16: return fastEmit_ISD_FADD_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3640 0 : case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3641 0 : case MVT::v2f32: return fastEmit_ISD_FADD_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3642 0 : case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3643 : default: return 0;
3644 : }
3645 : }
3646 :
3647 : // FastEmit functions for ISD::FDIV.
3648 :
3649 : unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3650 0 : if (RetVT.SimpleTy != MVT::f16)
3651 : return 0;
3652 0 : if ((Subtarget->hasFullFP16())) {
3653 0 : return fastEmitInst_rr(ARM::VDIVH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3654 : }
3655 : return 0;
3656 : }
3657 :
3658 : unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3659 0 : if (RetVT.SimpleTy != MVT::f32)
3660 : return 0;
3661 0 : if ((Subtarget->hasVFP2())) {
3662 0 : return fastEmitInst_rr(ARM::VDIVS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3663 : }
3664 : return 0;
3665 : }
3666 :
3667 0 : unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3668 0 : if (RetVT.SimpleTy != MVT::f64)
3669 : return 0;
3670 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
3671 0 : return fastEmitInst_rr(ARM::VDIVD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3672 : }
3673 : return 0;
3674 : }
3675 :
3676 0 : unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3677 0 : switch (VT.SimpleTy) {
3678 0 : case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3679 0 : case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3680 0 : case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3681 : default: return 0;
3682 : }
3683 : }
3684 :
3685 : // FastEmit functions for ISD::FMAXNAN.
3686 :
3687 0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3688 0 : if (RetVT.SimpleTy != MVT::v4f16)
3689 : return 0;
3690 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3691 0 : return fastEmitInst_rr(ARM::VMAXhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3692 : }
3693 : return 0;
3694 : }
3695 :
3696 0 : unsigned fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3697 0 : if (RetVT.SimpleTy != MVT::v8f16)
3698 : return 0;
3699 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3700 0 : return fastEmitInst_rr(ARM::VMAXhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3701 : }
3702 : return 0;
3703 : }
3704 :
3705 : unsigned fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3706 0 : if (RetVT.SimpleTy != MVT::v2f32)
3707 : return 0;
3708 0 : if ((Subtarget->hasNEON())) {
3709 0 : return fastEmitInst_rr(ARM::VMAXfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3710 : }
3711 : return 0;
3712 : }
3713 :
3714 : unsigned fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3715 0 : if (RetVT.SimpleTy != MVT::v4f32)
3716 : return 0;
3717 0 : if ((Subtarget->hasNEON())) {
3718 0 : return fastEmitInst_rr(ARM::VMAXfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3719 : }
3720 : return 0;
3721 : }
3722 :
3723 0 : unsigned fastEmit_ISD_FMAXNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3724 0 : switch (VT.SimpleTy) {
3725 0 : case MVT::v4f16: return fastEmit_ISD_FMAXNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3726 0 : case MVT::v8f16: return fastEmit_ISD_FMAXNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3727 0 : case MVT::v2f32: return fastEmit_ISD_FMAXNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3728 0 : case MVT::v4f32: return fastEmit_ISD_FMAXNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3729 : default: return 0;
3730 : }
3731 : }
3732 :
3733 : // FastEmit functions for ISD::FMAXNUM.
3734 :
3735 : unsigned fastEmit_ISD_FMAXNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3736 0 : if (RetVT.SimpleTy != MVT::f16)
3737 : return 0;
3738 0 : if ((Subtarget->hasFullFP16())) {
3739 0 : return fastEmitInst_rr(ARM::VMAXNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3740 : }
3741 : return 0;
3742 : }
3743 :
3744 : unsigned fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3745 0 : if (RetVT.SimpleTy != MVT::f32)
3746 : return 0;
3747 0 : if ((Subtarget->hasFPARMv8())) {
3748 0 : return fastEmitInst_rr(ARM::VMAXNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3749 : }
3750 : return 0;
3751 : }
3752 :
3753 0 : unsigned fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3754 0 : if (RetVT.SimpleTy != MVT::f64)
3755 : return 0;
3756 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
3757 0 : return fastEmitInst_rr(ARM::VMAXNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3758 : }
3759 : return 0;
3760 : }
3761 :
3762 0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3763 0 : if (RetVT.SimpleTy != MVT::v4f16)
3764 : return 0;
3765 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3766 0 : return fastEmitInst_rr(ARM::VMAXNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3767 : }
3768 : return 0;
3769 : }
3770 :
3771 0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3772 0 : if (RetVT.SimpleTy != MVT::v8f16)
3773 : return 0;
3774 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3775 0 : return fastEmitInst_rr(ARM::VMAXNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3776 : }
3777 : return 0;
3778 : }
3779 :
3780 0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3781 0 : if (RetVT.SimpleTy != MVT::v2f32)
3782 : return 0;
3783 0 : if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3784 0 : return fastEmitInst_rr(ARM::VMAXNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3785 : }
3786 : return 0;
3787 : }
3788 :
3789 0 : unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3790 0 : if (RetVT.SimpleTy != MVT::v4f32)
3791 : return 0;
3792 0 : if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3793 0 : return fastEmitInst_rr(ARM::VMAXNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3794 : }
3795 : return 0;
3796 : }
3797 :
3798 0 : unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3799 0 : switch (VT.SimpleTy) {
3800 0 : case MVT::f16: return fastEmit_ISD_FMAXNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3801 0 : case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3802 0 : case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3803 0 : case MVT::v4f16: return fastEmit_ISD_FMAXNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3804 0 : case MVT::v8f16: return fastEmit_ISD_FMAXNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3805 0 : case MVT::v2f32: return fastEmit_ISD_FMAXNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3806 0 : case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3807 : default: return 0;
3808 : }
3809 : }
3810 :
3811 : // FastEmit functions for ISD::FMINNAN.
3812 :
3813 0 : unsigned fastEmit_ISD_FMINNAN_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3814 0 : if (RetVT.SimpleTy != MVT::v4f16)
3815 : return 0;
3816 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3817 0 : return fastEmitInst_rr(ARM::VMINhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3818 : }
3819 : return 0;
3820 : }
3821 :
3822 0 : unsigned fastEmit_ISD_FMINNAN_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3823 0 : if (RetVT.SimpleTy != MVT::v8f16)
3824 : return 0;
3825 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3826 0 : return fastEmitInst_rr(ARM::VMINhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3827 : }
3828 : return 0;
3829 : }
3830 :
3831 : unsigned fastEmit_ISD_FMINNAN_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3832 0 : if (RetVT.SimpleTy != MVT::v2f32)
3833 : return 0;
3834 0 : if ((Subtarget->hasNEON())) {
3835 0 : return fastEmitInst_rr(ARM::VMINfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3836 : }
3837 : return 0;
3838 : }
3839 :
3840 : unsigned fastEmit_ISD_FMINNAN_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3841 0 : if (RetVT.SimpleTy != MVT::v4f32)
3842 : return 0;
3843 0 : if ((Subtarget->hasNEON())) {
3844 0 : return fastEmitInst_rr(ARM::VMINfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3845 : }
3846 : return 0;
3847 : }
3848 :
3849 0 : unsigned fastEmit_ISD_FMINNAN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3850 0 : switch (VT.SimpleTy) {
3851 0 : case MVT::v4f16: return fastEmit_ISD_FMINNAN_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3852 0 : case MVT::v8f16: return fastEmit_ISD_FMINNAN_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3853 0 : case MVT::v2f32: return fastEmit_ISD_FMINNAN_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3854 0 : case MVT::v4f32: return fastEmit_ISD_FMINNAN_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3855 : default: return 0;
3856 : }
3857 : }
3858 :
3859 : // FastEmit functions for ISD::FMINNUM.
3860 :
3861 : unsigned fastEmit_ISD_FMINNUM_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3862 0 : if (RetVT.SimpleTy != MVT::f16)
3863 : return 0;
3864 0 : if ((Subtarget->hasFullFP16())) {
3865 0 : return fastEmitInst_rr(ARM::VMINNMH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3866 : }
3867 : return 0;
3868 : }
3869 :
3870 : unsigned fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3871 0 : if (RetVT.SimpleTy != MVT::f32)
3872 : return 0;
3873 0 : if ((Subtarget->hasFPARMv8())) {
3874 0 : return fastEmitInst_rr(ARM::VMINNMS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3875 : }
3876 : return 0;
3877 : }
3878 :
3879 0 : unsigned fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3880 0 : if (RetVT.SimpleTy != MVT::f64)
3881 : return 0;
3882 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasFPARMv8())) {
3883 0 : return fastEmitInst_rr(ARM::VMINNMD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3884 : }
3885 : return 0;
3886 : }
3887 :
3888 0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3889 0 : if (RetVT.SimpleTy != MVT::v4f16)
3890 : return 0;
3891 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3892 0 : return fastEmitInst_rr(ARM::VMINNMNDh, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3893 : }
3894 : return 0;
3895 : }
3896 :
3897 0 : unsigned fastEmit_ISD_FMINNUM_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3898 0 : if (RetVT.SimpleTy != MVT::v8f16)
3899 : return 0;
3900 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3901 0 : return fastEmitInst_rr(ARM::VMINNMNQh, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3902 : }
3903 : return 0;
3904 : }
3905 :
3906 0 : unsigned fastEmit_ISD_FMINNUM_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3907 0 : if (RetVT.SimpleTy != MVT::v2f32)
3908 : return 0;
3909 0 : if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3910 0 : return fastEmitInst_rr(ARM::VMINNMNDf, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3911 : }
3912 : return 0;
3913 : }
3914 :
3915 0 : unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3916 0 : if (RetVT.SimpleTy != MVT::v4f32)
3917 : return 0;
3918 0 : if ((Subtarget->hasNEON()) && (Subtarget->hasV8Ops())) {
3919 0 : return fastEmitInst_rr(ARM::VMINNMNQf, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3920 : }
3921 : return 0;
3922 : }
3923 :
3924 0 : unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3925 0 : switch (VT.SimpleTy) {
3926 0 : case MVT::f16: return fastEmit_ISD_FMINNUM_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3927 0 : case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3928 0 : case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3929 0 : case MVT::v4f16: return fastEmit_ISD_FMINNUM_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3930 0 : case MVT::v8f16: return fastEmit_ISD_FMINNUM_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3931 0 : case MVT::v2f32: return fastEmit_ISD_FMINNUM_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3932 0 : case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3933 : default: return 0;
3934 : }
3935 : }
3936 :
3937 : // FastEmit functions for ISD::FMUL.
3938 :
3939 : unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3940 0 : if (RetVT.SimpleTy != MVT::f16)
3941 : return 0;
3942 0 : if ((Subtarget->hasFullFP16())) {
3943 0 : return fastEmitInst_rr(ARM::VMULH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3944 : }
3945 : return 0;
3946 : }
3947 :
3948 1 : unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3949 1 : if (RetVT.SimpleTy != MVT::f32)
3950 : return 0;
3951 2 : if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
3952 1 : return fastEmitInst_rr(ARM::VMULS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3953 : }
3954 : return 0;
3955 : }
3956 :
3957 0 : unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3958 0 : if (RetVT.SimpleTy != MVT::f64)
3959 : return 0;
3960 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
3961 0 : return fastEmitInst_rr(ARM::VMULD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3962 : }
3963 : return 0;
3964 : }
3965 :
3966 0 : unsigned fastEmit_ISD_FMUL_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3967 0 : if (RetVT.SimpleTy != MVT::v4f16)
3968 : return 0;
3969 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3970 0 : return fastEmitInst_rr(ARM::VMULhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3971 : }
3972 : return 0;
3973 : }
3974 :
3975 0 : unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3976 0 : if (RetVT.SimpleTy != MVT::v8f16)
3977 : return 0;
3978 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
3979 0 : return fastEmitInst_rr(ARM::VMULhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3980 : }
3981 : return 0;
3982 : }
3983 :
3984 : unsigned fastEmit_ISD_FMUL_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3985 0 : if (RetVT.SimpleTy != MVT::v2f32)
3986 : return 0;
3987 0 : if ((Subtarget->hasNEON())) {
3988 0 : return fastEmitInst_rr(ARM::VMULfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3989 : }
3990 : return 0;
3991 : }
3992 :
3993 : unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
3994 0 : if (RetVT.SimpleTy != MVT::v4f32)
3995 : return 0;
3996 0 : if ((Subtarget->hasNEON())) {
3997 0 : return fastEmitInst_rr(ARM::VMULfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
3998 : }
3999 : return 0;
4000 : }
4001 :
4002 1 : unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4003 1 : switch (VT.SimpleTy) {
4004 0 : case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4005 1 : case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4006 0 : case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4007 0 : case MVT::v4f16: return fastEmit_ISD_FMUL_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4008 0 : case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4009 0 : case MVT::v2f32: return fastEmit_ISD_FMUL_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4010 0 : case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4011 : default: return 0;
4012 : }
4013 : }
4014 :
4015 : // FastEmit functions for ISD::FSUB.
4016 :
4017 : unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4018 0 : if (RetVT.SimpleTy != MVT::f16)
4019 : return 0;
4020 0 : if ((Subtarget->hasFullFP16())) {
4021 0 : return fastEmitInst_rr(ARM::VSUBH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4022 : }
4023 : return 0;
4024 : }
4025 :
4026 0 : unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4027 0 : if (RetVT.SimpleTy != MVT::f32)
4028 : return 0;
4029 0 : if ((!Subtarget->useNEONForSinglePrecisionFP()) && (Subtarget->hasVFP2())) {
4030 0 : return fastEmitInst_rr(ARM::VSUBS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4031 : }
4032 : return 0;
4033 : }
4034 :
4035 0 : unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4036 0 : if (RetVT.SimpleTy != MVT::f64)
4037 : return 0;
4038 0 : if ((!Subtarget->isFPOnlySP()) && (Subtarget->hasVFP2())) {
4039 0 : return fastEmitInst_rr(ARM::VSUBD, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4040 : }
4041 : return 0;
4042 : }
4043 :
4044 0 : unsigned fastEmit_ISD_FSUB_MVT_v4f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4045 0 : if (RetVT.SimpleTy != MVT::v4f16)
4046 : return 0;
4047 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
4048 0 : return fastEmitInst_rr(ARM::VSUBhd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4049 : }
4050 : return 0;
4051 : }
4052 :
4053 0 : unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4054 0 : if (RetVT.SimpleTy != MVT::v8f16)
4055 : return 0;
4056 0 : if ((Subtarget->hasFullFP16()) && (Subtarget->hasNEON())) {
4057 0 : return fastEmitInst_rr(ARM::VSUBhq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4058 : }
4059 : return 0;
4060 : }
4061 :
4062 : unsigned fastEmit_ISD_FSUB_MVT_v2f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4063 0 : if (RetVT.SimpleTy != MVT::v2f32)
4064 : return 0;
4065 0 : if ((Subtarget->hasNEON())) {
4066 0 : return fastEmitInst_rr(ARM::VSUBfd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4067 : }
4068 : return 0;
4069 : }
4070 :
4071 : unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4072 0 : if (RetVT.SimpleTy != MVT::v4f32)
4073 : return 0;
4074 0 : if ((Subtarget->hasNEON())) {
4075 0 : return fastEmitInst_rr(ARM::VSUBfq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4076 : }
4077 : return 0;
4078 : }
4079 :
4080 0 : unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4081 0 : switch (VT.SimpleTy) {
4082 0 : case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4083 0 : case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4084 0 : case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4085 0 : case MVT::v4f16: return fastEmit_ISD_FSUB_MVT_v4f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4086 0 : case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4087 0 : case MVT::v2f32: return fastEmit_ISD_FSUB_MVT_v2f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4088 0 : case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4089 : default: return 0;
4090 : }
4091 : }
4092 :
4093 : // FastEmit functions for ISD::MUL.
4094 :
4095 3 : unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4096 3 : if (RetVT.SimpleTy != MVT::i32)
4097 : return 0;
4098 3 : if ((Subtarget->isThumb2())) {
4099 3 : return fastEmitInst_rr(ARM::t2MUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4100 : }
4101 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4102 0 : return fastEmitInst_rr(ARM::tMUL, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4103 : }
4104 0 : if ((!Subtarget->isThumb()) && (!Subtarget->hasV6Ops()) && (Subtarget->useMulOps())) {
4105 0 : return fastEmitInst_rr(ARM::MULv5, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4106 : }
4107 0 : if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
4108 0 : return fastEmitInst_rr(ARM::MUL, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4109 : }
4110 : return 0;
4111 : }
4112 :
4113 : unsigned fastEmit_ISD_MUL_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4114 0 : if (RetVT.SimpleTy != MVT::v8i8)
4115 : return 0;
4116 0 : if ((Subtarget->hasNEON())) {
4117 0 : return fastEmitInst_rr(ARM::VMULv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4118 : }
4119 : return 0;
4120 : }
4121 :
4122 : unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4123 0 : if (RetVT.SimpleTy != MVT::v16i8)
4124 : return 0;
4125 0 : if ((Subtarget->hasNEON())) {
4126 0 : return fastEmitInst_rr(ARM::VMULv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4127 : }
4128 : return 0;
4129 : }
4130 :
4131 : unsigned fastEmit_ISD_MUL_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4132 0 : if (RetVT.SimpleTy != MVT::v4i16)
4133 : return 0;
4134 0 : if ((Subtarget->hasNEON())) {
4135 0 : return fastEmitInst_rr(ARM::VMULv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4136 : }
4137 : return 0;
4138 : }
4139 :
4140 : unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4141 0 : if (RetVT.SimpleTy != MVT::v8i16)
4142 : return 0;
4143 0 : if ((Subtarget->hasNEON())) {
4144 0 : return fastEmitInst_rr(ARM::VMULv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4145 : }
4146 : return 0;
4147 : }
4148 :
4149 : unsigned fastEmit_ISD_MUL_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4150 0 : if (RetVT.SimpleTy != MVT::v2i32)
4151 : return 0;
4152 0 : if ((Subtarget->hasNEON())) {
4153 0 : return fastEmitInst_rr(ARM::VMULv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4154 : }
4155 : return 0;
4156 : }
4157 :
4158 : unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4159 0 : if (RetVT.SimpleTy != MVT::v4i32)
4160 : return 0;
4161 0 : if ((Subtarget->hasNEON())) {
4162 0 : return fastEmitInst_rr(ARM::VMULv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4163 : }
4164 : return 0;
4165 : }
4166 :
4167 3 : unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4168 3 : switch (VT.SimpleTy) {
4169 3 : case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4170 0 : case MVT::v8i8: return fastEmit_ISD_MUL_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4171 0 : case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4172 0 : case MVT::v4i16: return fastEmit_ISD_MUL_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4173 0 : case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4174 0 : case MVT::v2i32: return fastEmit_ISD_MUL_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4175 0 : case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4176 : default: return 0;
4177 : }
4178 : }
4179 :
4180 : // FastEmit functions for ISD::MULHS.
4181 :
4182 0 : unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4183 0 : if (RetVT.SimpleTy != MVT::i32)
4184 : return 0;
4185 0 : if ((Subtarget->hasDSP()) && (Subtarget->isThumb2())) {
4186 0 : return fastEmitInst_rr(ARM::t2SMMUL, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4187 : }
4188 0 : if ((Subtarget->hasV6Ops()) && (!Subtarget->isThumb())) {
4189 0 : return fastEmitInst_rr(ARM::SMMUL, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4190 : }
4191 : return 0;
4192 : }
4193 :
4194 : unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4195 0 : switch (VT.SimpleTy) {
4196 0 : case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4197 : default: return 0;
4198 : }
4199 : }
4200 :
4201 : // FastEmit functions for ISD::OR.
4202 :
4203 3 : unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4204 3 : if (RetVT.SimpleTy != MVT::i32)
4205 : return 0;
4206 3 : if ((Subtarget->isThumb2())) {
4207 1 : return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4208 : }
4209 2 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4210 0 : return fastEmitInst_rr(ARM::tORR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4211 : }
4212 2 : if ((!Subtarget->isThumb())) {
4213 2 : return fastEmitInst_rr(ARM::ORRrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4214 : }
4215 : return 0;
4216 : }
4217 :
4218 : unsigned fastEmit_ISD_OR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4219 0 : if (RetVT.SimpleTy != MVT::v2i32)
4220 : return 0;
4221 0 : if ((Subtarget->hasNEON())) {
4222 0 : return fastEmitInst_rr(ARM::VORRd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4223 : }
4224 : return 0;
4225 : }
4226 :
4227 : unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4228 0 : if (RetVT.SimpleTy != MVT::v4i32)
4229 : return 0;
4230 0 : if ((Subtarget->hasNEON())) {
4231 0 : return fastEmitInst_rr(ARM::VORRq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4232 : }
4233 : return 0;
4234 : }
4235 :
4236 3 : unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4237 3 : switch (VT.SimpleTy) {
4238 3 : case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4239 0 : case MVT::v2i32: return fastEmit_ISD_OR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4240 0 : case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4241 : default: return 0;
4242 : }
4243 : }
4244 :
4245 : // FastEmit functions for ISD::ROTR.
4246 :
4247 0 : unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4248 0 : if (RetVT.SimpleTy != MVT::i32)
4249 : return 0;
4250 0 : if ((Subtarget->isThumb2())) {
4251 0 : return fastEmitInst_rr(ARM::t2RORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4252 : }
4253 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4254 0 : return fastEmitInst_rr(ARM::tROR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4255 : }
4256 : return 0;
4257 : }
4258 :
4259 : unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4260 0 : switch (VT.SimpleTy) {
4261 0 : case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4262 : default: return 0;
4263 : }
4264 : }
4265 :
4266 : // FastEmit functions for ISD::SDIV.
4267 :
4268 4 : unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4269 4 : if (RetVT.SimpleTy != MVT::i32)
4270 : return 0;
4271 4 : if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
4272 0 : return fastEmitInst_rr(ARM::t2SDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4273 : }
4274 4 : if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
4275 0 : return fastEmitInst_rr(ARM::SDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4276 : }
4277 : return 0;
4278 : }
4279 :
4280 : unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4281 4 : switch (VT.SimpleTy) {
4282 4 : case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4283 : default: return 0;
4284 : }
4285 : }
4286 :
4287 : // FastEmit functions for ISD::SHL.
4288 :
4289 5 : unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4290 5 : if (RetVT.SimpleTy != MVT::i32)
4291 : return 0;
4292 5 : if ((Subtarget->isThumb2())) {
4293 0 : return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4294 : }
4295 5 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4296 0 : return fastEmitInst_rr(ARM::tLSLrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4297 : }
4298 : return 0;
4299 : }
4300 :
4301 : unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4302 5 : switch (VT.SimpleTy) {
4303 5 : case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4304 : default: return 0;
4305 : }
4306 : }
4307 :
4308 : // FastEmit functions for ISD::SMAX.
4309 :
4310 : unsigned fastEmit_ISD_SMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4311 0 : if (RetVT.SimpleTy != MVT::v8i8)
4312 : return 0;
4313 0 : if ((Subtarget->hasNEON())) {
4314 0 : return fastEmitInst_rr(ARM::VMAXsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4315 : }
4316 : return 0;
4317 : }
4318 :
4319 : unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4320 0 : if (RetVT.SimpleTy != MVT::v16i8)
4321 : return 0;
4322 0 : if ((Subtarget->hasNEON())) {
4323 0 : return fastEmitInst_rr(ARM::VMAXsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4324 : }
4325 : return 0;
4326 : }
4327 :
4328 : unsigned fastEmit_ISD_SMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4329 0 : if (RetVT.SimpleTy != MVT::v4i16)
4330 : return 0;
4331 0 : if ((Subtarget->hasNEON())) {
4332 0 : return fastEmitInst_rr(ARM::VMAXsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4333 : }
4334 : return 0;
4335 : }
4336 :
4337 : unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4338 0 : if (RetVT.SimpleTy != MVT::v8i16)
4339 : return 0;
4340 0 : if ((Subtarget->hasNEON())) {
4341 0 : return fastEmitInst_rr(ARM::VMAXsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4342 : }
4343 : return 0;
4344 : }
4345 :
4346 : unsigned fastEmit_ISD_SMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4347 0 : if (RetVT.SimpleTy != MVT::v2i32)
4348 : return 0;
4349 0 : if ((Subtarget->hasNEON())) {
4350 0 : return fastEmitInst_rr(ARM::VMAXsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4351 : }
4352 : return 0;
4353 : }
4354 :
4355 : unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4356 0 : if (RetVT.SimpleTy != MVT::v4i32)
4357 : return 0;
4358 0 : if ((Subtarget->hasNEON())) {
4359 0 : return fastEmitInst_rr(ARM::VMAXsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4360 : }
4361 : return 0;
4362 : }
4363 :
4364 0 : unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4365 0 : switch (VT.SimpleTy) {
4366 0 : case MVT::v8i8: return fastEmit_ISD_SMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4367 0 : case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4368 0 : case MVT::v4i16: return fastEmit_ISD_SMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4369 0 : case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4370 0 : case MVT::v2i32: return fastEmit_ISD_SMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4371 0 : case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4372 : default: return 0;
4373 : }
4374 : }
4375 :
4376 : // FastEmit functions for ISD::SMIN.
4377 :
4378 : unsigned fastEmit_ISD_SMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4379 0 : if (RetVT.SimpleTy != MVT::v8i8)
4380 : return 0;
4381 0 : if ((Subtarget->hasNEON())) {
4382 0 : return fastEmitInst_rr(ARM::VMINsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4383 : }
4384 : return 0;
4385 : }
4386 :
4387 : unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4388 0 : if (RetVT.SimpleTy != MVT::v16i8)
4389 : return 0;
4390 0 : if ((Subtarget->hasNEON())) {
4391 0 : return fastEmitInst_rr(ARM::VMINsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4392 : }
4393 : return 0;
4394 : }
4395 :
4396 : unsigned fastEmit_ISD_SMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4397 0 : if (RetVT.SimpleTy != MVT::v4i16)
4398 : return 0;
4399 0 : if ((Subtarget->hasNEON())) {
4400 0 : return fastEmitInst_rr(ARM::VMINsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4401 : }
4402 : return 0;
4403 : }
4404 :
4405 : unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4406 0 : if (RetVT.SimpleTy != MVT::v8i16)
4407 : return 0;
4408 0 : if ((Subtarget->hasNEON())) {
4409 0 : return fastEmitInst_rr(ARM::VMINsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4410 : }
4411 : return 0;
4412 : }
4413 :
4414 : unsigned fastEmit_ISD_SMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4415 0 : if (RetVT.SimpleTy != MVT::v2i32)
4416 : return 0;
4417 0 : if ((Subtarget->hasNEON())) {
4418 0 : return fastEmitInst_rr(ARM::VMINsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4419 : }
4420 : return 0;
4421 : }
4422 :
4423 : unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4424 0 : if (RetVT.SimpleTy != MVT::v4i32)
4425 : return 0;
4426 0 : if ((Subtarget->hasNEON())) {
4427 0 : return fastEmitInst_rr(ARM::VMINsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4428 : }
4429 : return 0;
4430 : }
4431 :
4432 0 : unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4433 0 : switch (VT.SimpleTy) {
4434 0 : case MVT::v8i8: return fastEmit_ISD_SMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4435 0 : case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4436 0 : case MVT::v4i16: return fastEmit_ISD_SMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4437 0 : case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4438 0 : case MVT::v2i32: return fastEmit_ISD_SMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4439 0 : case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4440 : default: return 0;
4441 : }
4442 : }
4443 :
4444 : // FastEmit functions for ISD::SRA.
4445 :
4446 4 : unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4447 4 : if (RetVT.SimpleTy != MVT::i32)
4448 : return 0;
4449 4 : if ((Subtarget->isThumb2())) {
4450 0 : return fastEmitInst_rr(ARM::t2ASRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4451 : }
4452 4 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4453 0 : return fastEmitInst_rr(ARM::tASRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4454 : }
4455 : return 0;
4456 : }
4457 :
4458 : unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4459 4 : switch (VT.SimpleTy) {
4460 4 : case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4461 : default: return 0;
4462 : }
4463 : }
4464 :
4465 : // FastEmit functions for ISD::SRL.
4466 :
4467 6 : unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4468 6 : if (RetVT.SimpleTy != MVT::i32)
4469 : return 0;
4470 6 : if ((Subtarget->isThumb2())) {
4471 2 : return fastEmitInst_rr(ARM::t2LSRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4472 : }
4473 4 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4474 0 : return fastEmitInst_rr(ARM::tLSRrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4475 : }
4476 : return 0;
4477 : }
4478 :
4479 : unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4480 6 : switch (VT.SimpleTy) {
4481 6 : case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4482 : default: return 0;
4483 : }
4484 : }
4485 :
4486 : // FastEmit functions for ISD::SUB.
4487 :
4488 3 : unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4489 3 : if (RetVT.SimpleTy != MVT::i32)
4490 : return 0;
4491 3 : if ((Subtarget->isThumb2())) {
4492 1 : return fastEmitInst_rr(ARM::t2SUBrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4493 : }
4494 2 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4495 0 : return fastEmitInst_rr(ARM::tSUBrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4496 : }
4497 2 : if ((!Subtarget->isThumb())) {
4498 2 : return fastEmitInst_rr(ARM::SUBrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4499 : }
4500 : return 0;
4501 : }
4502 :
4503 : unsigned fastEmit_ISD_SUB_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4504 0 : if (RetVT.SimpleTy != MVT::v8i8)
4505 : return 0;
4506 0 : if ((Subtarget->hasNEON())) {
4507 0 : return fastEmitInst_rr(ARM::VSUBv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4508 : }
4509 : return 0;
4510 : }
4511 :
4512 : unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4513 0 : if (RetVT.SimpleTy != MVT::v16i8)
4514 : return 0;
4515 0 : if ((Subtarget->hasNEON())) {
4516 0 : return fastEmitInst_rr(ARM::VSUBv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4517 : }
4518 : return 0;
4519 : }
4520 :
4521 : unsigned fastEmit_ISD_SUB_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4522 0 : if (RetVT.SimpleTy != MVT::v4i16)
4523 : return 0;
4524 0 : if ((Subtarget->hasNEON())) {
4525 0 : return fastEmitInst_rr(ARM::VSUBv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4526 : }
4527 : return 0;
4528 : }
4529 :
4530 : unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4531 0 : if (RetVT.SimpleTy != MVT::v8i16)
4532 : return 0;
4533 0 : if ((Subtarget->hasNEON())) {
4534 0 : return fastEmitInst_rr(ARM::VSUBv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4535 : }
4536 : return 0;
4537 : }
4538 :
4539 : unsigned fastEmit_ISD_SUB_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4540 0 : if (RetVT.SimpleTy != MVT::v2i32)
4541 : return 0;
4542 0 : if ((Subtarget->hasNEON())) {
4543 0 : return fastEmitInst_rr(ARM::VSUBv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4544 : }
4545 : return 0;
4546 : }
4547 :
4548 : unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4549 0 : if (RetVT.SimpleTy != MVT::v4i32)
4550 : return 0;
4551 0 : if ((Subtarget->hasNEON())) {
4552 0 : return fastEmitInst_rr(ARM::VSUBv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4553 : }
4554 : return 0;
4555 : }
4556 :
4557 : unsigned fastEmit_ISD_SUB_MVT_v1i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4558 0 : if (RetVT.SimpleTy != MVT::v1i64)
4559 : return 0;
4560 0 : if ((Subtarget->hasNEON())) {
4561 0 : return fastEmitInst_rr(ARM::VSUBv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4562 : }
4563 : return 0;
4564 : }
4565 :
4566 : unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4567 0 : if (RetVT.SimpleTy != MVT::v2i64)
4568 : return 0;
4569 0 : if ((Subtarget->hasNEON())) {
4570 0 : return fastEmitInst_rr(ARM::VSUBv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4571 : }
4572 : return 0;
4573 : }
4574 :
4575 3 : unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4576 3 : switch (VT.SimpleTy) {
4577 3 : case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4578 0 : case MVT::v8i8: return fastEmit_ISD_SUB_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4579 0 : case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4580 0 : case MVT::v4i16: return fastEmit_ISD_SUB_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4581 0 : case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4582 0 : case MVT::v2i32: return fastEmit_ISD_SUB_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4583 0 : case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4584 0 : case MVT::v1i64: return fastEmit_ISD_SUB_MVT_v1i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4585 0 : case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4586 : default: return 0;
4587 : }
4588 : }
4589 :
4590 : // FastEmit functions for ISD::UDIV.
4591 :
4592 10 : unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4593 10 : if (RetVT.SimpleTy != MVT::i32)
4594 : return 0;
4595 10 : if ((Subtarget->hasDivideInThumbMode()) && (Subtarget->hasV8MBaselineOps()) && (Subtarget->isThumb())) {
4596 0 : return fastEmitInst_rr(ARM::t2UDIV, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4597 : }
4598 10 : if ((Subtarget->hasDivideInARMMode()) && (!Subtarget->isThumb())) {
4599 0 : return fastEmitInst_rr(ARM::UDIV, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4600 : }
4601 : return 0;
4602 : }
4603 :
4604 : unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4605 10 : switch (VT.SimpleTy) {
4606 10 : case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4607 : default: return 0;
4608 : }
4609 : }
4610 :
4611 : // FastEmit functions for ISD::UMAX.
4612 :
4613 : unsigned fastEmit_ISD_UMAX_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4614 0 : if (RetVT.SimpleTy != MVT::v8i8)
4615 : return 0;
4616 0 : if ((Subtarget->hasNEON())) {
4617 0 : return fastEmitInst_rr(ARM::VMAXuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4618 : }
4619 : return 0;
4620 : }
4621 :
4622 : unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4623 0 : if (RetVT.SimpleTy != MVT::v16i8)
4624 : return 0;
4625 0 : if ((Subtarget->hasNEON())) {
4626 0 : return fastEmitInst_rr(ARM::VMAXuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4627 : }
4628 : return 0;
4629 : }
4630 :
4631 : unsigned fastEmit_ISD_UMAX_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4632 0 : if (RetVT.SimpleTy != MVT::v4i16)
4633 : return 0;
4634 0 : if ((Subtarget->hasNEON())) {
4635 0 : return fastEmitInst_rr(ARM::VMAXuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4636 : }
4637 : return 0;
4638 : }
4639 :
4640 : unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4641 0 : if (RetVT.SimpleTy != MVT::v8i16)
4642 : return 0;
4643 0 : if ((Subtarget->hasNEON())) {
4644 0 : return fastEmitInst_rr(ARM::VMAXuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4645 : }
4646 : return 0;
4647 : }
4648 :
4649 : unsigned fastEmit_ISD_UMAX_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4650 0 : if (RetVT.SimpleTy != MVT::v2i32)
4651 : return 0;
4652 0 : if ((Subtarget->hasNEON())) {
4653 0 : return fastEmitInst_rr(ARM::VMAXuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4654 : }
4655 : return 0;
4656 : }
4657 :
4658 : unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4659 0 : if (RetVT.SimpleTy != MVT::v4i32)
4660 : return 0;
4661 0 : if ((Subtarget->hasNEON())) {
4662 0 : return fastEmitInst_rr(ARM::VMAXuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4663 : }
4664 : return 0;
4665 : }
4666 :
4667 0 : unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4668 0 : switch (VT.SimpleTy) {
4669 0 : case MVT::v8i8: return fastEmit_ISD_UMAX_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4670 0 : case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4671 0 : case MVT::v4i16: return fastEmit_ISD_UMAX_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4672 0 : case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4673 0 : case MVT::v2i32: return fastEmit_ISD_UMAX_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4674 0 : case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4675 : default: return 0;
4676 : }
4677 : }
4678 :
4679 : // FastEmit functions for ISD::UMIN.
4680 :
4681 : unsigned fastEmit_ISD_UMIN_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4682 0 : if (RetVT.SimpleTy != MVT::v8i8)
4683 : return 0;
4684 0 : if ((Subtarget->hasNEON())) {
4685 0 : return fastEmitInst_rr(ARM::VMINuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4686 : }
4687 : return 0;
4688 : }
4689 :
4690 : unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4691 0 : if (RetVT.SimpleTy != MVT::v16i8)
4692 : return 0;
4693 0 : if ((Subtarget->hasNEON())) {
4694 0 : return fastEmitInst_rr(ARM::VMINuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4695 : }
4696 : return 0;
4697 : }
4698 :
4699 : unsigned fastEmit_ISD_UMIN_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4700 0 : if (RetVT.SimpleTy != MVT::v4i16)
4701 : return 0;
4702 0 : if ((Subtarget->hasNEON())) {
4703 0 : return fastEmitInst_rr(ARM::VMINuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4704 : }
4705 : return 0;
4706 : }
4707 :
4708 : unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4709 0 : if (RetVT.SimpleTy != MVT::v8i16)
4710 : return 0;
4711 0 : if ((Subtarget->hasNEON())) {
4712 0 : return fastEmitInst_rr(ARM::VMINuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4713 : }
4714 : return 0;
4715 : }
4716 :
4717 : unsigned fastEmit_ISD_UMIN_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4718 0 : if (RetVT.SimpleTy != MVT::v2i32)
4719 : return 0;
4720 0 : if ((Subtarget->hasNEON())) {
4721 0 : return fastEmitInst_rr(ARM::VMINuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4722 : }
4723 : return 0;
4724 : }
4725 :
4726 : unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4727 0 : if (RetVT.SimpleTy != MVT::v4i32)
4728 : return 0;
4729 0 : if ((Subtarget->hasNEON())) {
4730 0 : return fastEmitInst_rr(ARM::VMINuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4731 : }
4732 : return 0;
4733 : }
4734 :
4735 0 : unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4736 0 : switch (VT.SimpleTy) {
4737 0 : case MVT::v8i8: return fastEmit_ISD_UMIN_MVT_v8i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4738 0 : case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4739 0 : case MVT::v4i16: return fastEmit_ISD_UMIN_MVT_v4i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4740 0 : case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4741 0 : case MVT::v2i32: return fastEmit_ISD_UMIN_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4742 0 : case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4743 : default: return 0;
4744 : }
4745 : }
4746 :
4747 : // FastEmit functions for ISD::XOR.
4748 :
4749 11 : unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4750 11 : if (RetVT.SimpleTy != MVT::i32)
4751 : return 0;
4752 11 : if ((Subtarget->isThumb2())) {
4753 8 : return fastEmitInst_rr(ARM::t2EORrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4754 : }
4755 3 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
4756 0 : return fastEmitInst_rr(ARM::tEOR, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4757 : }
4758 3 : if ((!Subtarget->isThumb())) {
4759 3 : return fastEmitInst_rr(ARM::EORrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4760 : }
4761 : return 0;
4762 : }
4763 :
4764 : unsigned fastEmit_ISD_XOR_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4765 0 : if (RetVT.SimpleTy != MVT::v2i32)
4766 : return 0;
4767 0 : if ((Subtarget->hasNEON())) {
4768 0 : return fastEmitInst_rr(ARM::VEORd, &ARM::DPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4769 : }
4770 : return 0;
4771 : }
4772 :
4773 : unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4774 0 : if (RetVT.SimpleTy != MVT::v4i32)
4775 : return 0;
4776 0 : if ((Subtarget->hasNEON())) {
4777 0 : return fastEmitInst_rr(ARM::VEORq, &ARM::QPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4778 : }
4779 : return 0;
4780 : }
4781 :
4782 11 : unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4783 11 : switch (VT.SimpleTy) {
4784 11 : case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4785 0 : case MVT::v2i32: return fastEmit_ISD_XOR_MVT_v2i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4786 0 : case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4787 : default: return 0;
4788 : }
4789 : }
4790 :
4791 : // Top-level FastEmit function.
4792 :
4793 209 : unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
4794 209 : switch (Opcode) {
4795 0 : case ARMISD::CMP: return fastEmit_ARMISD_CMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4796 0 : case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4797 0 : case ARMISD::EH_SJLJ_LONGJMP: return fastEmit_ARMISD_EH_SJLJ_LONGJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4798 0 : case ARMISD::EH_SJLJ_SETJMP: return fastEmit_ARMISD_EH_SJLJ_SETJMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4799 0 : case ARMISD::SMULWB: return fastEmit_ARMISD_SMULWB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4800 0 : case ARMISD::SMULWT: return fastEmit_ARMISD_SMULWT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4801 0 : case ARMISD::VCEQ: return fastEmit_ARMISD_VCEQ_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4802 0 : case ARMISD::VCGE: return fastEmit_ARMISD_VCGE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4803 0 : case ARMISD::VCGEU: return fastEmit_ARMISD_VCGEU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4804 0 : case ARMISD::VCGT: return fastEmit_ARMISD_VCGT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4805 0 : case ARMISD::VCGTU: return fastEmit_ARMISD_VCGTU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4806 0 : case ARMISD::VMOVDRR: return fastEmit_ARMISD_VMOVDRR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4807 0 : case ARMISD::VMULLs: return fastEmit_ARMISD_VMULLs_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4808 0 : case ARMISD::VMULLu: return fastEmit_ARMISD_VMULLu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4809 0 : case ARMISD::VTBL1: return fastEmit_ARMISD_VTBL1_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4810 0 : case ARMISD::VTST: return fastEmit_ARMISD_VTST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4811 94 : case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4812 0 : case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4813 33 : case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4814 0 : case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4815 0 : case ISD::FMAXNAN: return fastEmit_ISD_FMAXNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4816 0 : case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4817 0 : case ISD::FMINNAN: return fastEmit_ISD_FMINNAN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4818 0 : case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4819 1 : case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4820 0 : case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4821 3 : case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4822 0 : case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4823 3 : case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4824 0 : case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4825 8 : case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4826 10 : case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4827 0 : case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4828 0 : case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4829 8 : case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4830 12 : case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4831 3 : case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4832 20 : case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4833 0 : case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4834 0 : case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4835 11 : case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
4836 : default: return 0;
4837 : }
4838 : }
4839 :
4840 : // FastEmit functions for ARMISD::PIC_ADD.
4841 :
4842 0 : unsigned fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4843 0 : if (RetVT.SimpleTy != MVT::i32)
4844 : return 0;
4845 0 : if ((Subtarget->isThumb())) {
4846 0 : return fastEmitInst_ri(ARM::tPICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4847 : }
4848 : if ((!Subtarget->isThumb())) {
4849 0 : return fastEmitInst_ri(ARM::PICADD, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4850 : }
4851 : return 0;
4852 : }
4853 :
4854 : unsigned fastEmit_ARMISD_PIC_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4855 0 : switch (VT.SimpleTy) {
4856 0 : case MVT::i32: return fastEmit_ARMISD_PIC_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
4857 : default: return 0;
4858 : }
4859 : }
4860 :
4861 : // FastEmit functions for ARMISD::VDUPLANE.
4862 :
4863 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4864 0 : if (RetVT.SimpleTy != MVT::v8i8)
4865 : return 0;
4866 0 : if ((Subtarget->hasNEON())) {
4867 0 : return fastEmitInst_ri(ARM::VDUPLN8d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4868 : }
4869 : return 0;
4870 : }
4871 :
4872 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4873 0 : if (RetVT.SimpleTy != MVT::v4i16)
4874 : return 0;
4875 0 : if ((Subtarget->hasNEON())) {
4876 0 : return fastEmitInst_ri(ARM::VDUPLN16d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4877 : }
4878 : return 0;
4879 : }
4880 :
4881 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4882 0 : if (RetVT.SimpleTy != MVT::v2i32)
4883 : return 0;
4884 0 : if ((Subtarget->hasNEON())) {
4885 0 : return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4886 : }
4887 : return 0;
4888 : }
4889 :
4890 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4f16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4891 0 : if (RetVT.SimpleTy != MVT::v4f16)
4892 : return 0;
4893 0 : return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4894 : }
4895 :
4896 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4897 0 : return fastEmitInst_ri(ARM::VDUPLN32d, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4898 : }
4899 :
4900 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4901 0 : return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
4902 : }
4903 :
4904 0 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4905 0 : switch (RetVT.SimpleTy) {
4906 0 : case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v2f32_ri(Op0, Op0IsKill, imm1);
4907 0 : case MVT::v4f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_MVT_v4f32_ri(Op0, Op0IsKill, imm1);
4908 : default: return 0;
4909 : }
4910 : }
4911 :
4912 0 : unsigned fastEmit_ARMISD_VDUPLANE_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4913 0 : switch (VT.SimpleTy) {
4914 0 : case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
4915 0 : case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
4916 0 : case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
4917 0 : case MVT::v4f16: return fastEmit_ARMISD_VDUPLANE_MVT_v4f16_ri(RetVT, Op0, Op0IsKill, imm1);
4918 0 : case MVT::v2f32: return fastEmit_ARMISD_VDUPLANE_MVT_v2f32_ri(RetVT, Op0, Op0IsKill, imm1);
4919 : default: return 0;
4920 : }
4921 : }
4922 :
4923 : // FastEmit functions for ARMISD::VGETLANEs.
4924 :
4925 : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4926 0 : if (RetVT.SimpleTy != MVT::i32)
4927 : return 0;
4928 0 : if ((Subtarget->hasNEON())) {
4929 0 : return fastEmitInst_ri(ARM::VGETLNs8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4930 : }
4931 : return 0;
4932 : }
4933 :
4934 : unsigned fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4935 0 : if (RetVT.SimpleTy != MVT::i32)
4936 : return 0;
4937 0 : if ((Subtarget->hasNEON())) {
4938 0 : return fastEmitInst_ri(ARM::VGETLNs16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4939 : }
4940 : return 0;
4941 : }
4942 :
4943 0 : unsigned fastEmit_ARMISD_VGETLANEs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4944 0 : switch (VT.SimpleTy) {
4945 0 : case MVT::v8i8: return fastEmit_ARMISD_VGETLANEs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
4946 0 : case MVT::v4i16: return fastEmit_ARMISD_VGETLANEs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
4947 : default: return 0;
4948 : }
4949 : }
4950 :
4951 : // FastEmit functions for ARMISD::VGETLANEu.
4952 :
4953 : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4954 0 : if (RetVT.SimpleTy != MVT::i32)
4955 : return 0;
4956 0 : if ((Subtarget->hasNEON())) {
4957 0 : return fastEmitInst_ri(ARM::VGETLNu8, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4958 : }
4959 : return 0;
4960 : }
4961 :
4962 : unsigned fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4963 0 : if (RetVT.SimpleTy != MVT::i32)
4964 : return 0;
4965 0 : if ((Subtarget->hasNEON())) {
4966 0 : return fastEmitInst_ri(ARM::VGETLNu16, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
4967 : }
4968 : return 0;
4969 : }
4970 :
4971 0 : unsigned fastEmit_ARMISD_VGETLANEu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4972 0 : switch (VT.SimpleTy) {
4973 0 : case MVT::v8i8: return fastEmit_ARMISD_VGETLANEu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
4974 0 : case MVT::v4i16: return fastEmit_ARMISD_VGETLANEu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
4975 : default: return 0;
4976 : }
4977 : }
4978 :
4979 : // FastEmit functions for ARMISD::VQSHLs.
4980 :
4981 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4982 0 : if (RetVT.SimpleTy != MVT::v8i8)
4983 : return 0;
4984 0 : if ((Subtarget->hasNEON())) {
4985 0 : return fastEmitInst_ri(ARM::VQSHLsiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
4986 : }
4987 : return 0;
4988 : }
4989 :
4990 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4991 0 : if (RetVT.SimpleTy != MVT::v16i8)
4992 : return 0;
4993 0 : if ((Subtarget->hasNEON())) {
4994 0 : return fastEmitInst_ri(ARM::VQSHLsiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
4995 : }
4996 : return 0;
4997 : }
4998 :
4999 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5000 0 : if (RetVT.SimpleTy != MVT::v4i16)
5001 : return 0;
5002 0 : if ((Subtarget->hasNEON())) {
5003 0 : return fastEmitInst_ri(ARM::VQSHLsiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5004 : }
5005 : return 0;
5006 : }
5007 :
5008 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5009 0 : if (RetVT.SimpleTy != MVT::v8i16)
5010 : return 0;
5011 0 : if ((Subtarget->hasNEON())) {
5012 0 : return fastEmitInst_ri(ARM::VQSHLsiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5013 : }
5014 : return 0;
5015 : }
5016 :
5017 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5018 0 : if (RetVT.SimpleTy != MVT::v2i32)
5019 : return 0;
5020 0 : if ((Subtarget->hasNEON())) {
5021 0 : return fastEmitInst_ri(ARM::VQSHLsiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5022 : }
5023 : return 0;
5024 : }
5025 :
5026 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5027 0 : if (RetVT.SimpleTy != MVT::v4i32)
5028 : return 0;
5029 0 : if ((Subtarget->hasNEON())) {
5030 0 : return fastEmitInst_ri(ARM::VQSHLsiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5031 : }
5032 : return 0;
5033 : }
5034 :
5035 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5036 0 : if (RetVT.SimpleTy != MVT::v1i64)
5037 : return 0;
5038 0 : if ((Subtarget->hasNEON())) {
5039 0 : return fastEmitInst_ri(ARM::VQSHLsiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5040 : }
5041 : return 0;
5042 : }
5043 :
5044 : unsigned fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5045 0 : if (RetVT.SimpleTy != MVT::v2i64)
5046 : return 0;
5047 0 : if ((Subtarget->hasNEON())) {
5048 0 : return fastEmitInst_ri(ARM::VQSHLsiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5049 : }
5050 : return 0;
5051 : }
5052 :
5053 0 : unsigned fastEmit_ARMISD_VQSHLs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5054 0 : switch (VT.SimpleTy) {
5055 0 : case MVT::v8i8: return fastEmit_ARMISD_VQSHLs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5056 0 : case MVT::v16i8: return fastEmit_ARMISD_VQSHLs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5057 0 : case MVT::v4i16: return fastEmit_ARMISD_VQSHLs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5058 0 : case MVT::v8i16: return fastEmit_ARMISD_VQSHLs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5059 0 : case MVT::v2i32: return fastEmit_ARMISD_VQSHLs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5060 0 : case MVT::v4i32: return fastEmit_ARMISD_VQSHLs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5061 0 : case MVT::v1i64: return fastEmit_ARMISD_VQSHLs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5062 0 : case MVT::v2i64: return fastEmit_ARMISD_VQSHLs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5063 : default: return 0;
5064 : }
5065 : }
5066 :
5067 : // FastEmit functions for ARMISD::VQSHLsu.
5068 :
5069 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5070 0 : if (RetVT.SimpleTy != MVT::v8i8)
5071 : return 0;
5072 0 : if ((Subtarget->hasNEON())) {
5073 0 : return fastEmitInst_ri(ARM::VQSHLsuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5074 : }
5075 : return 0;
5076 : }
5077 :
5078 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5079 0 : if (RetVT.SimpleTy != MVT::v16i8)
5080 : return 0;
5081 0 : if ((Subtarget->hasNEON())) {
5082 0 : return fastEmitInst_ri(ARM::VQSHLsuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5083 : }
5084 : return 0;
5085 : }
5086 :
5087 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5088 0 : if (RetVT.SimpleTy != MVT::v4i16)
5089 : return 0;
5090 0 : if ((Subtarget->hasNEON())) {
5091 0 : return fastEmitInst_ri(ARM::VQSHLsuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5092 : }
5093 : return 0;
5094 : }
5095 :
5096 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5097 0 : if (RetVT.SimpleTy != MVT::v8i16)
5098 : return 0;
5099 0 : if ((Subtarget->hasNEON())) {
5100 0 : return fastEmitInst_ri(ARM::VQSHLsuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5101 : }
5102 : return 0;
5103 : }
5104 :
5105 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5106 0 : if (RetVT.SimpleTy != MVT::v2i32)
5107 : return 0;
5108 0 : if ((Subtarget->hasNEON())) {
5109 0 : return fastEmitInst_ri(ARM::VQSHLsuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5110 : }
5111 : return 0;
5112 : }
5113 :
5114 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5115 0 : if (RetVT.SimpleTy != MVT::v4i32)
5116 : return 0;
5117 0 : if ((Subtarget->hasNEON())) {
5118 0 : return fastEmitInst_ri(ARM::VQSHLsuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5119 : }
5120 : return 0;
5121 : }
5122 :
5123 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5124 0 : if (RetVT.SimpleTy != MVT::v1i64)
5125 : return 0;
5126 0 : if ((Subtarget->hasNEON())) {
5127 0 : return fastEmitInst_ri(ARM::VQSHLsuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5128 : }
5129 : return 0;
5130 : }
5131 :
5132 : unsigned fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5133 0 : if (RetVT.SimpleTy != MVT::v2i64)
5134 : return 0;
5135 0 : if ((Subtarget->hasNEON())) {
5136 0 : return fastEmitInst_ri(ARM::VQSHLsuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5137 : }
5138 : return 0;
5139 : }
5140 :
5141 0 : unsigned fastEmit_ARMISD_VQSHLsu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5142 0 : switch (VT.SimpleTy) {
5143 0 : case MVT::v8i8: return fastEmit_ARMISD_VQSHLsu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5144 0 : case MVT::v16i8: return fastEmit_ARMISD_VQSHLsu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5145 0 : case MVT::v4i16: return fastEmit_ARMISD_VQSHLsu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5146 0 : case MVT::v8i16: return fastEmit_ARMISD_VQSHLsu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5147 0 : case MVT::v2i32: return fastEmit_ARMISD_VQSHLsu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5148 0 : case MVT::v4i32: return fastEmit_ARMISD_VQSHLsu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5149 0 : case MVT::v1i64: return fastEmit_ARMISD_VQSHLsu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5150 0 : case MVT::v2i64: return fastEmit_ARMISD_VQSHLsu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5151 : default: return 0;
5152 : }
5153 : }
5154 :
5155 : // FastEmit functions for ARMISD::VQSHLu.
5156 :
5157 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5158 0 : if (RetVT.SimpleTy != MVT::v8i8)
5159 : return 0;
5160 0 : if ((Subtarget->hasNEON())) {
5161 0 : return fastEmitInst_ri(ARM::VQSHLuiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5162 : }
5163 : return 0;
5164 : }
5165 :
5166 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5167 0 : if (RetVT.SimpleTy != MVT::v16i8)
5168 : return 0;
5169 0 : if ((Subtarget->hasNEON())) {
5170 0 : return fastEmitInst_ri(ARM::VQSHLuiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5171 : }
5172 : return 0;
5173 : }
5174 :
5175 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5176 0 : if (RetVT.SimpleTy != MVT::v4i16)
5177 : return 0;
5178 0 : if ((Subtarget->hasNEON())) {
5179 0 : return fastEmitInst_ri(ARM::VQSHLuiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5180 : }
5181 : return 0;
5182 : }
5183 :
5184 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5185 0 : if (RetVT.SimpleTy != MVT::v8i16)
5186 : return 0;
5187 0 : if ((Subtarget->hasNEON())) {
5188 0 : return fastEmitInst_ri(ARM::VQSHLuiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5189 : }
5190 : return 0;
5191 : }
5192 :
5193 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5194 0 : if (RetVT.SimpleTy != MVT::v2i32)
5195 : return 0;
5196 0 : if ((Subtarget->hasNEON())) {
5197 0 : return fastEmitInst_ri(ARM::VQSHLuiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5198 : }
5199 : return 0;
5200 : }
5201 :
5202 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5203 0 : if (RetVT.SimpleTy != MVT::v4i32)
5204 : return 0;
5205 0 : if ((Subtarget->hasNEON())) {
5206 0 : return fastEmitInst_ri(ARM::VQSHLuiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5207 : }
5208 : return 0;
5209 : }
5210 :
5211 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5212 0 : if (RetVT.SimpleTy != MVT::v1i64)
5213 : return 0;
5214 0 : if ((Subtarget->hasNEON())) {
5215 0 : return fastEmitInst_ri(ARM::VQSHLuiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5216 : }
5217 : return 0;
5218 : }
5219 :
5220 : unsigned fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5221 0 : if (RetVT.SimpleTy != MVT::v2i64)
5222 : return 0;
5223 0 : if ((Subtarget->hasNEON())) {
5224 0 : return fastEmitInst_ri(ARM::VQSHLuiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5225 : }
5226 : return 0;
5227 : }
5228 :
5229 0 : unsigned fastEmit_ARMISD_VQSHLu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5230 0 : switch (VT.SimpleTy) {
5231 0 : case MVT::v8i8: return fastEmit_ARMISD_VQSHLu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5232 0 : case MVT::v16i8: return fastEmit_ARMISD_VQSHLu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5233 0 : case MVT::v4i16: return fastEmit_ARMISD_VQSHLu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5234 0 : case MVT::v8i16: return fastEmit_ARMISD_VQSHLu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5235 0 : case MVT::v2i32: return fastEmit_ARMISD_VQSHLu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5236 0 : case MVT::v4i32: return fastEmit_ARMISD_VQSHLu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5237 0 : case MVT::v1i64: return fastEmit_ARMISD_VQSHLu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5238 0 : case MVT::v2i64: return fastEmit_ARMISD_VQSHLu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5239 : default: return 0;
5240 : }
5241 : }
5242 :
5243 : // FastEmit functions for ARMISD::VRSHRs.
5244 :
5245 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5246 0 : if (RetVT.SimpleTy != MVT::v8i8)
5247 : return 0;
5248 0 : if ((Subtarget->hasNEON())) {
5249 0 : return fastEmitInst_ri(ARM::VRSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5250 : }
5251 : return 0;
5252 : }
5253 :
5254 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5255 0 : if (RetVT.SimpleTy != MVT::v16i8)
5256 : return 0;
5257 0 : if ((Subtarget->hasNEON())) {
5258 0 : return fastEmitInst_ri(ARM::VRSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5259 : }
5260 : return 0;
5261 : }
5262 :
5263 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5264 0 : if (RetVT.SimpleTy != MVT::v4i16)
5265 : return 0;
5266 0 : if ((Subtarget->hasNEON())) {
5267 0 : return fastEmitInst_ri(ARM::VRSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5268 : }
5269 : return 0;
5270 : }
5271 :
5272 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5273 0 : if (RetVT.SimpleTy != MVT::v8i16)
5274 : return 0;
5275 0 : if ((Subtarget->hasNEON())) {
5276 0 : return fastEmitInst_ri(ARM::VRSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5277 : }
5278 : return 0;
5279 : }
5280 :
5281 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5282 0 : if (RetVT.SimpleTy != MVT::v2i32)
5283 : return 0;
5284 0 : if ((Subtarget->hasNEON())) {
5285 0 : return fastEmitInst_ri(ARM::VRSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5286 : }
5287 : return 0;
5288 : }
5289 :
5290 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5291 0 : if (RetVT.SimpleTy != MVT::v4i32)
5292 : return 0;
5293 0 : if ((Subtarget->hasNEON())) {
5294 0 : return fastEmitInst_ri(ARM::VRSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5295 : }
5296 : return 0;
5297 : }
5298 :
5299 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5300 0 : if (RetVT.SimpleTy != MVT::v1i64)
5301 : return 0;
5302 0 : if ((Subtarget->hasNEON())) {
5303 0 : return fastEmitInst_ri(ARM::VRSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5304 : }
5305 : return 0;
5306 : }
5307 :
5308 : unsigned fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5309 0 : if (RetVT.SimpleTy != MVT::v2i64)
5310 : return 0;
5311 0 : if ((Subtarget->hasNEON())) {
5312 0 : return fastEmitInst_ri(ARM::VRSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5313 : }
5314 : return 0;
5315 : }
5316 :
5317 0 : unsigned fastEmit_ARMISD_VRSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5318 0 : switch (VT.SimpleTy) {
5319 0 : case MVT::v8i8: return fastEmit_ARMISD_VRSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5320 0 : case MVT::v16i8: return fastEmit_ARMISD_VRSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5321 0 : case MVT::v4i16: return fastEmit_ARMISD_VRSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5322 0 : case MVT::v8i16: return fastEmit_ARMISD_VRSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5323 0 : case MVT::v2i32: return fastEmit_ARMISD_VRSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5324 0 : case MVT::v4i32: return fastEmit_ARMISD_VRSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5325 0 : case MVT::v1i64: return fastEmit_ARMISD_VRSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5326 0 : case MVT::v2i64: return fastEmit_ARMISD_VRSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5327 : default: return 0;
5328 : }
5329 : }
5330 :
5331 : // FastEmit functions for ARMISD::VRSHRu.
5332 :
5333 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5334 0 : if (RetVT.SimpleTy != MVT::v8i8)
5335 : return 0;
5336 0 : if ((Subtarget->hasNEON())) {
5337 0 : return fastEmitInst_ri(ARM::VRSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5338 : }
5339 : return 0;
5340 : }
5341 :
5342 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5343 0 : if (RetVT.SimpleTy != MVT::v16i8)
5344 : return 0;
5345 0 : if ((Subtarget->hasNEON())) {
5346 0 : return fastEmitInst_ri(ARM::VRSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5347 : }
5348 : return 0;
5349 : }
5350 :
5351 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5352 0 : if (RetVT.SimpleTy != MVT::v4i16)
5353 : return 0;
5354 0 : if ((Subtarget->hasNEON())) {
5355 0 : return fastEmitInst_ri(ARM::VRSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5356 : }
5357 : return 0;
5358 : }
5359 :
5360 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5361 0 : if (RetVT.SimpleTy != MVT::v8i16)
5362 : return 0;
5363 0 : if ((Subtarget->hasNEON())) {
5364 0 : return fastEmitInst_ri(ARM::VRSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5365 : }
5366 : return 0;
5367 : }
5368 :
5369 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5370 0 : if (RetVT.SimpleTy != MVT::v2i32)
5371 : return 0;
5372 0 : if ((Subtarget->hasNEON())) {
5373 0 : return fastEmitInst_ri(ARM::VRSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5374 : }
5375 : return 0;
5376 : }
5377 :
5378 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5379 0 : if (RetVT.SimpleTy != MVT::v4i32)
5380 : return 0;
5381 0 : if ((Subtarget->hasNEON())) {
5382 0 : return fastEmitInst_ri(ARM::VRSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5383 : }
5384 : return 0;
5385 : }
5386 :
5387 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5388 0 : if (RetVT.SimpleTy != MVT::v1i64)
5389 : return 0;
5390 0 : if ((Subtarget->hasNEON())) {
5391 0 : return fastEmitInst_ri(ARM::VRSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5392 : }
5393 : return 0;
5394 : }
5395 :
5396 : unsigned fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5397 0 : if (RetVT.SimpleTy != MVT::v2i64)
5398 : return 0;
5399 0 : if ((Subtarget->hasNEON())) {
5400 0 : return fastEmitInst_ri(ARM::VRSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5401 : }
5402 : return 0;
5403 : }
5404 :
5405 0 : unsigned fastEmit_ARMISD_VRSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5406 0 : switch (VT.SimpleTy) {
5407 0 : case MVT::v8i8: return fastEmit_ARMISD_VRSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5408 0 : case MVT::v16i8: return fastEmit_ARMISD_VRSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5409 0 : case MVT::v4i16: return fastEmit_ARMISD_VRSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5410 0 : case MVT::v8i16: return fastEmit_ARMISD_VRSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5411 0 : case MVT::v2i32: return fastEmit_ARMISD_VRSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5412 0 : case MVT::v4i32: return fastEmit_ARMISD_VRSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5413 0 : case MVT::v1i64: return fastEmit_ARMISD_VRSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5414 0 : case MVT::v2i64: return fastEmit_ARMISD_VRSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5415 : default: return 0;
5416 : }
5417 : }
5418 :
5419 : // FastEmit functions for ARMISD::VSHL.
5420 :
5421 : unsigned fastEmit_ARMISD_VSHL_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5422 0 : if (RetVT.SimpleTy != MVT::v8i8)
5423 : return 0;
5424 0 : if ((Subtarget->hasNEON())) {
5425 0 : return fastEmitInst_ri(ARM::VSHLiv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5426 : }
5427 : return 0;
5428 : }
5429 :
5430 : unsigned fastEmit_ARMISD_VSHL_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5431 0 : if (RetVT.SimpleTy != MVT::v16i8)
5432 : return 0;
5433 0 : if ((Subtarget->hasNEON())) {
5434 0 : return fastEmitInst_ri(ARM::VSHLiv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5435 : }
5436 : return 0;
5437 : }
5438 :
5439 : unsigned fastEmit_ARMISD_VSHL_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5440 0 : if (RetVT.SimpleTy != MVT::v4i16)
5441 : return 0;
5442 0 : if ((Subtarget->hasNEON())) {
5443 0 : return fastEmitInst_ri(ARM::VSHLiv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5444 : }
5445 : return 0;
5446 : }
5447 :
5448 : unsigned fastEmit_ARMISD_VSHL_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5449 0 : if (RetVT.SimpleTy != MVT::v8i16)
5450 : return 0;
5451 0 : if ((Subtarget->hasNEON())) {
5452 0 : return fastEmitInst_ri(ARM::VSHLiv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5453 : }
5454 : return 0;
5455 : }
5456 :
5457 : unsigned fastEmit_ARMISD_VSHL_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5458 0 : if (RetVT.SimpleTy != MVT::v2i32)
5459 : return 0;
5460 0 : if ((Subtarget->hasNEON())) {
5461 0 : return fastEmitInst_ri(ARM::VSHLiv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5462 : }
5463 : return 0;
5464 : }
5465 :
5466 : unsigned fastEmit_ARMISD_VSHL_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5467 0 : if (RetVT.SimpleTy != MVT::v4i32)
5468 : return 0;
5469 0 : if ((Subtarget->hasNEON())) {
5470 0 : return fastEmitInst_ri(ARM::VSHLiv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5471 : }
5472 : return 0;
5473 : }
5474 :
5475 : unsigned fastEmit_ARMISD_VSHL_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5476 0 : if (RetVT.SimpleTy != MVT::v1i64)
5477 : return 0;
5478 0 : if ((Subtarget->hasNEON())) {
5479 0 : return fastEmitInst_ri(ARM::VSHLiv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5480 : }
5481 : return 0;
5482 : }
5483 :
5484 : unsigned fastEmit_ARMISD_VSHL_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5485 0 : if (RetVT.SimpleTy != MVT::v2i64)
5486 : return 0;
5487 0 : if ((Subtarget->hasNEON())) {
5488 0 : return fastEmitInst_ri(ARM::VSHLiv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5489 : }
5490 : return 0;
5491 : }
5492 :
5493 0 : unsigned fastEmit_ARMISD_VSHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5494 0 : switch (VT.SimpleTy) {
5495 0 : case MVT::v8i8: return fastEmit_ARMISD_VSHL_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5496 0 : case MVT::v16i8: return fastEmit_ARMISD_VSHL_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5497 0 : case MVT::v4i16: return fastEmit_ARMISD_VSHL_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5498 0 : case MVT::v8i16: return fastEmit_ARMISD_VSHL_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5499 0 : case MVT::v2i32: return fastEmit_ARMISD_VSHL_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5500 0 : case MVT::v4i32: return fastEmit_ARMISD_VSHL_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5501 0 : case MVT::v1i64: return fastEmit_ARMISD_VSHL_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5502 0 : case MVT::v2i64: return fastEmit_ARMISD_VSHL_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5503 : default: return 0;
5504 : }
5505 : }
5506 :
5507 : // FastEmit functions for ARMISD::VSHRs.
5508 :
5509 : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5510 0 : if (RetVT.SimpleTy != MVT::v8i8)
5511 : return 0;
5512 0 : if ((Subtarget->hasNEON())) {
5513 0 : return fastEmitInst_ri(ARM::VSHRsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5514 : }
5515 : return 0;
5516 : }
5517 :
5518 : unsigned fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5519 0 : if (RetVT.SimpleTy != MVT::v16i8)
5520 : return 0;
5521 0 : if ((Subtarget->hasNEON())) {
5522 0 : return fastEmitInst_ri(ARM::VSHRsv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5523 : }
5524 : return 0;
5525 : }
5526 :
5527 : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5528 0 : if (RetVT.SimpleTy != MVT::v4i16)
5529 : return 0;
5530 0 : if ((Subtarget->hasNEON())) {
5531 0 : return fastEmitInst_ri(ARM::VSHRsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5532 : }
5533 : return 0;
5534 : }
5535 :
5536 : unsigned fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5537 0 : if (RetVT.SimpleTy != MVT::v8i16)
5538 : return 0;
5539 0 : if ((Subtarget->hasNEON())) {
5540 0 : return fastEmitInst_ri(ARM::VSHRsv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5541 : }
5542 : return 0;
5543 : }
5544 :
5545 : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5546 0 : if (RetVT.SimpleTy != MVT::v2i32)
5547 : return 0;
5548 0 : if ((Subtarget->hasNEON())) {
5549 0 : return fastEmitInst_ri(ARM::VSHRsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5550 : }
5551 : return 0;
5552 : }
5553 :
5554 : unsigned fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5555 0 : if (RetVT.SimpleTy != MVT::v4i32)
5556 : return 0;
5557 0 : if ((Subtarget->hasNEON())) {
5558 0 : return fastEmitInst_ri(ARM::VSHRsv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5559 : }
5560 : return 0;
5561 : }
5562 :
5563 : unsigned fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5564 0 : if (RetVT.SimpleTy != MVT::v1i64)
5565 : return 0;
5566 0 : if ((Subtarget->hasNEON())) {
5567 0 : return fastEmitInst_ri(ARM::VSHRsv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5568 : }
5569 : return 0;
5570 : }
5571 :
5572 : unsigned fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5573 0 : if (RetVT.SimpleTy != MVT::v2i64)
5574 : return 0;
5575 0 : if ((Subtarget->hasNEON())) {
5576 0 : return fastEmitInst_ri(ARM::VSHRsv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5577 : }
5578 : return 0;
5579 : }
5580 :
5581 0 : unsigned fastEmit_ARMISD_VSHRs_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5582 0 : switch (VT.SimpleTy) {
5583 0 : case MVT::v8i8: return fastEmit_ARMISD_VSHRs_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5584 0 : case MVT::v16i8: return fastEmit_ARMISD_VSHRs_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5585 0 : case MVT::v4i16: return fastEmit_ARMISD_VSHRs_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5586 0 : case MVT::v8i16: return fastEmit_ARMISD_VSHRs_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5587 0 : case MVT::v2i32: return fastEmit_ARMISD_VSHRs_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5588 0 : case MVT::v4i32: return fastEmit_ARMISD_VSHRs_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5589 0 : case MVT::v1i64: return fastEmit_ARMISD_VSHRs_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5590 0 : case MVT::v2i64: return fastEmit_ARMISD_VSHRs_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5591 : default: return 0;
5592 : }
5593 : }
5594 :
5595 : // FastEmit functions for ARMISD::VSHRu.
5596 :
5597 : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5598 0 : if (RetVT.SimpleTy != MVT::v8i8)
5599 : return 0;
5600 0 : if ((Subtarget->hasNEON())) {
5601 0 : return fastEmitInst_ri(ARM::VSHRuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5602 : }
5603 : return 0;
5604 : }
5605 :
5606 : unsigned fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5607 0 : if (RetVT.SimpleTy != MVT::v16i8)
5608 : return 0;
5609 0 : if ((Subtarget->hasNEON())) {
5610 0 : return fastEmitInst_ri(ARM::VSHRuv16i8, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5611 : }
5612 : return 0;
5613 : }
5614 :
5615 : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5616 0 : if (RetVT.SimpleTy != MVT::v4i16)
5617 : return 0;
5618 0 : if ((Subtarget->hasNEON())) {
5619 0 : return fastEmitInst_ri(ARM::VSHRuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5620 : }
5621 : return 0;
5622 : }
5623 :
5624 : unsigned fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5625 0 : if (RetVT.SimpleTy != MVT::v8i16)
5626 : return 0;
5627 0 : if ((Subtarget->hasNEON())) {
5628 0 : return fastEmitInst_ri(ARM::VSHRuv8i16, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5629 : }
5630 : return 0;
5631 : }
5632 :
5633 : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5634 0 : if (RetVT.SimpleTy != MVT::v2i32)
5635 : return 0;
5636 0 : if ((Subtarget->hasNEON())) {
5637 0 : return fastEmitInst_ri(ARM::VSHRuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5638 : }
5639 : return 0;
5640 : }
5641 :
5642 : unsigned fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5643 0 : if (RetVT.SimpleTy != MVT::v4i32)
5644 : return 0;
5645 0 : if ((Subtarget->hasNEON())) {
5646 0 : return fastEmitInst_ri(ARM::VSHRuv4i32, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5647 : }
5648 : return 0;
5649 : }
5650 :
5651 : unsigned fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5652 0 : if (RetVT.SimpleTy != MVT::v1i64)
5653 : return 0;
5654 0 : if ((Subtarget->hasNEON())) {
5655 0 : return fastEmitInst_ri(ARM::VSHRuv1i64, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
5656 : }
5657 : return 0;
5658 : }
5659 :
5660 : unsigned fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5661 0 : if (RetVT.SimpleTy != MVT::v2i64)
5662 : return 0;
5663 0 : if ((Subtarget->hasNEON())) {
5664 0 : return fastEmitInst_ri(ARM::VSHRuv2i64, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
5665 : }
5666 : return 0;
5667 : }
5668 :
5669 0 : unsigned fastEmit_ARMISD_VSHRu_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5670 0 : switch (VT.SimpleTy) {
5671 0 : case MVT::v8i8: return fastEmit_ARMISD_VSHRu_MVT_v8i8_ri(RetVT, Op0, Op0IsKill, imm1);
5672 0 : case MVT::v16i8: return fastEmit_ARMISD_VSHRu_MVT_v16i8_ri(RetVT, Op0, Op0IsKill, imm1);
5673 0 : case MVT::v4i16: return fastEmit_ARMISD_VSHRu_MVT_v4i16_ri(RetVT, Op0, Op0IsKill, imm1);
5674 0 : case MVT::v8i16: return fastEmit_ARMISD_VSHRu_MVT_v8i16_ri(RetVT, Op0, Op0IsKill, imm1);
5675 0 : case MVT::v2i32: return fastEmit_ARMISD_VSHRu_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5676 0 : case MVT::v4i32: return fastEmit_ARMISD_VSHRu_MVT_v4i32_ri(RetVT, Op0, Op0IsKill, imm1);
5677 0 : case MVT::v1i64: return fastEmit_ARMISD_VSHRu_MVT_v1i64_ri(RetVT, Op0, Op0IsKill, imm1);
5678 0 : case MVT::v2i64: return fastEmit_ARMISD_VSHRu_MVT_v2i64_ri(RetVT, Op0, Op0IsKill, imm1);
5679 : default: return 0;
5680 : }
5681 : }
5682 :
5683 : // FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
5684 :
5685 0 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5686 0 : if (RetVT.SimpleTy != MVT::i32)
5687 : return 0;
5688 0 : if ((!Subtarget->hasSlowVGETLNi32()) && (Subtarget->hasVFP2())) {
5689 0 : return fastEmitInst_ri(ARM::VGETLNi32, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5690 : }
5691 : return 0;
5692 : }
5693 :
5694 : unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5695 0 : switch (VT.SimpleTy) {
5696 0 : case MVT::v2i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2i32_ri(RetVT, Op0, Op0IsKill, imm1);
5697 : default: return 0;
5698 : }
5699 : }
5700 :
5701 : // FastEmit functions for ISD::SHL.
5702 :
5703 3 : unsigned fastEmit_ISD_SHL_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5704 3 : if (RetVT.SimpleTy != MVT::i32)
5705 : return 0;
5706 3 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
5707 0 : return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
5708 : }
5709 : return 0;
5710 : }
5711 :
5712 : unsigned fastEmit_ISD_SHL_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5713 3 : switch (VT.SimpleTy) {
5714 3 : case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
5715 : default: return 0;
5716 : }
5717 : }
5718 :
5719 : // Top-level FastEmit function.
5720 :
5721 504 : unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
5722 504 : if (VT == MVT::i32 && Predicate_mod_imm(imm1))
5723 255 : if (unsigned Reg = fastEmit_ri_Predicate_mod_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5724 : return Reg;
5725 :
5726 462 : if (VT == MVT::i32 && Predicate_imm0_7(imm1))
5727 38 : if (unsigned Reg = fastEmit_ri_Predicate_imm0_7(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5728 : return Reg;
5729 :
5730 462 : if (VT == MVT::i32 && Predicate_imm8_255(imm1))
5731 25 : if (unsigned Reg = fastEmit_ri_Predicate_imm8_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5732 : return Reg;
5733 :
5734 462 : if (VT == MVT::i32 && Predicate_imm0_255(imm1))
5735 40 : if (unsigned Reg = fastEmit_ri_Predicate_imm0_255(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5736 : return Reg;
5737 :
5738 462 : if (VT == MVT::i32 && Predicate_t2_so_imm(imm1))
5739 243 : if (unsigned Reg = fastEmit_ri_Predicate_t2_so_imm(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5740 : return Reg;
5741 :
5742 234 : if (VT == MVT::i32 && Predicate_imm0_4095(imm1))
5743 210 : if (unsigned Reg = fastEmit_ri_Predicate_imm0_4095(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5744 : return Reg;
5745 :
5746 45 : if (VT == MVT::i32 && Predicate_imm1_31(imm1))
5747 24 : if (unsigned Reg = fastEmit_ri_Predicate_imm1_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5748 : return Reg;
5749 :
5750 39 : if (VT == MVT::i32 && Predicate_imm0_31(imm1))
5751 9 : if (unsigned Reg = fastEmit_ri_Predicate_imm0_31(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5752 : return Reg;
5753 :
5754 39 : if (VT == MVT::i32 && Predicate_shr_imm8(imm1))
5755 9 : if (unsigned Reg = fastEmit_ri_Predicate_shr_imm8(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5756 : return Reg;
5757 :
5758 39 : if (VT == MVT::i32 && Predicate_shr_imm16(imm1))
5759 9 : if (unsigned Reg = fastEmit_ri_Predicate_shr_imm16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5760 : return Reg;
5761 :
5762 39 : if (VT == MVT::i32 && Predicate_shr_imm32(imm1))
5763 9 : if (unsigned Reg = fastEmit_ri_Predicate_shr_imm32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5764 : return Reg;
5765 :
5766 39 : if (VT == MVT::i32 && Predicate_VectorIndex32(imm1))
5767 0 : if (unsigned Reg = fastEmit_ri_Predicate_VectorIndex32(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
5768 : return Reg;
5769 :
5770 39 : switch (Opcode) {
5771 0 : case ARMISD::PIC_ADD: return fastEmit_ARMISD_PIC_ADD_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5772 0 : case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5773 0 : case ARMISD::VGETLANEs: return fastEmit_ARMISD_VGETLANEs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5774 0 : case ARMISD::VGETLANEu: return fastEmit_ARMISD_VGETLANEu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5775 0 : case ARMISD::VQSHLs: return fastEmit_ARMISD_VQSHLs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5776 0 : case ARMISD::VQSHLsu: return fastEmit_ARMISD_VQSHLsu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5777 0 : case ARMISD::VQSHLu: return fastEmit_ARMISD_VQSHLu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5778 0 : case ARMISD::VRSHRs: return fastEmit_ARMISD_VRSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5779 0 : case ARMISD::VRSHRu: return fastEmit_ARMISD_VRSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5780 0 : case ARMISD::VSHL: return fastEmit_ARMISD_VSHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5781 0 : case ARMISD::VSHRs: return fastEmit_ARMISD_VSHRs_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5782 0 : case ARMISD::VSHRu: return fastEmit_ARMISD_VSHRu_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5783 0 : case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5784 6 : case ISD::SHL: return fastEmit_ISD_SHL_ri(VT, RetVT, Op0, Op0IsKill, imm1);
5785 : default: return 0;
5786 : }
5787 : }
5788 :
5789 : // FastEmit functions for ARMISD::CMN.
5790 :
5791 : unsigned fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5792 0 : if (RetVT.SimpleTy != MVT::isVoid)
5793 : return 0;
5794 0 : if ((!Subtarget->isThumb())) {
5795 0 : return fastEmitInst_ri(ARM::CMNri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5796 : }
5797 : return 0;
5798 : }
5799 :
5800 0 : unsigned fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5801 0 : switch (VT.SimpleTy) {
5802 0 : case MVT::i32: return fastEmit_ARMISD_CMN_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5803 : default: return 0;
5804 : }
5805 : }
5806 :
5807 : // FastEmit functions for ARMISD::CMP.
5808 :
5809 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5810 0 : if (RetVT.SimpleTy != MVT::isVoid)
5811 : return 0;
5812 0 : if ((!Subtarget->isThumb())) {
5813 0 : return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5814 : }
5815 : return 0;
5816 : }
5817 :
5818 0 : unsigned fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5819 0 : switch (VT.SimpleTy) {
5820 0 : case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5821 : default: return 0;
5822 : }
5823 : }
5824 :
5825 : // FastEmit functions for ARMISD::CMPZ.
5826 :
5827 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5828 0 : if (RetVT.SimpleTy != MVT::isVoid)
5829 : return 0;
5830 0 : if ((!Subtarget->isThumb())) {
5831 0 : return fastEmitInst_ri(ARM::CMPri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5832 : }
5833 : return 0;
5834 : }
5835 :
5836 0 : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5837 0 : switch (VT.SimpleTy) {
5838 0 : case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5839 : default: return 0;
5840 : }
5841 : }
5842 :
5843 : // FastEmit functions for ISD::ADD.
5844 :
5845 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5846 234 : if (RetVT.SimpleTy != MVT::i32)
5847 : return 0;
5848 234 : if ((!Subtarget->isThumb())) {
5849 38 : return fastEmitInst_ri(ARM::ADDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5850 : }
5851 : return 0;
5852 : }
5853 :
5854 234 : unsigned fastEmit_ISD_ADD_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5855 234 : switch (VT.SimpleTy) {
5856 234 : case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5857 : default: return 0;
5858 : }
5859 : }
5860 :
5861 : // FastEmit functions for ISD::AND.
5862 :
5863 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5864 3 : if (RetVT.SimpleTy != MVT::i32)
5865 : return 0;
5866 3 : if ((!Subtarget->isThumb())) {
5867 2 : return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5868 : }
5869 : return 0;
5870 : }
5871 :
5872 3 : unsigned fastEmit_ISD_AND_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5873 3 : switch (VT.SimpleTy) {
5874 3 : case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5875 : default: return 0;
5876 : }
5877 : }
5878 :
5879 : // FastEmit functions for ISD::OR.
5880 :
5881 : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5882 3 : if (RetVT.SimpleTy != MVT::i32)
5883 : return 0;
5884 3 : if ((!Subtarget->isThumb())) {
5885 2 : return fastEmitInst_ri(ARM::ORRri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5886 : }
5887 : return 0;
5888 : }
5889 :
5890 3 : unsigned fastEmit_ISD_OR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5891 3 : switch (VT.SimpleTy) {
5892 3 : case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5893 : default: return 0;
5894 : }
5895 : }
5896 :
5897 : // FastEmit functions for ISD::SUB.
5898 :
5899 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5900 0 : if (RetVT.SimpleTy != MVT::i32)
5901 : return 0;
5902 0 : if ((!Subtarget->isThumb())) {
5903 0 : return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5904 : }
5905 : return 0;
5906 : }
5907 :
5908 0 : unsigned fastEmit_ISD_SUB_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5909 0 : switch (VT.SimpleTy) {
5910 0 : case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5911 : default: return 0;
5912 : }
5913 : }
5914 :
5915 : // FastEmit functions for ISD::XOR.
5916 :
5917 : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5918 0 : if (RetVT.SimpleTy != MVT::i32)
5919 : return 0;
5920 0 : if ((!Subtarget->isThumb())) {
5921 0 : return fastEmitInst_ri(ARM::EORri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
5922 : }
5923 : return 0;
5924 : }
5925 :
5926 0 : unsigned fastEmit_ISD_XOR_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5927 0 : switch (VT.SimpleTy) {
5928 0 : case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_mod_imm(RetVT, Op0, Op0IsKill, imm1);
5929 : default: return 0;
5930 : }
5931 : }
5932 :
5933 : // Top-level FastEmit function.
5934 :
5935 255 : unsigned fastEmit_ri_Predicate_mod_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5936 255 : switch (Opcode) {
5937 0 : case ARMISD::CMN: return fastEmit_ARMISD_CMN_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5938 0 : case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5939 0 : case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5940 234 : case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5941 3 : case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5942 3 : case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5943 0 : case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5944 0 : case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
5945 : default: return 0;
5946 : }
5947 : }
5948 :
5949 : // FastEmit functions for ISD::ADD.
5950 :
5951 11 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5952 11 : if (RetVT.SimpleTy != MVT::i32)
5953 : return 0;
5954 11 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
5955 0 : return fastEmitInst_ri(ARM::tADDi3, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
5956 : }
5957 : return 0;
5958 : }
5959 :
5960 : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5961 : switch (VT.SimpleTy) {
5962 11 : case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_7(RetVT, Op0, Op0IsKill, imm1);
5963 : default: return 0;
5964 : }
5965 : }
5966 :
5967 : // Top-level FastEmit function.
5968 :
5969 : unsigned fastEmit_ri_Predicate_imm0_7(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5970 27 : switch (Opcode) {
5971 11 : case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill, imm1);
5972 : default: return 0;
5973 : }
5974 : }
5975 :
5976 : // FastEmit functions for ISD::ADD.
5977 :
5978 12 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5979 12 : if (RetVT.SimpleTy != MVT::i32)
5980 : return 0;
5981 12 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
5982 0 : return fastEmitInst_ri(ARM::tADDi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
5983 : }
5984 : return 0;
5985 : }
5986 :
5987 : unsigned fastEmit_ISD_ADD_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5988 : switch (VT.SimpleTy) {
5989 12 : case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm8_255(RetVT, Op0, Op0IsKill, imm1);
5990 : default: return 0;
5991 : }
5992 : }
5993 :
5994 : // Top-level FastEmit function.
5995 :
5996 : unsigned fastEmit_ri_Predicate_imm8_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
5997 13 : switch (Opcode) {
5998 12 : case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm8_255(VT, RetVT, Op0, Op0IsKill, imm1);
5999 : default: return 0;
6000 : }
6001 : }
6002 :
6003 : // FastEmit functions for ARMISD::CMP.
6004 :
6005 0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6006 0 : if (RetVT.SimpleTy != MVT::isVoid)
6007 : return 0;
6008 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
6009 0 : return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
6010 : }
6011 : return 0;
6012 : }
6013 :
6014 : unsigned fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6015 0 : switch (VT.SimpleTy) {
6016 0 : case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
6017 : default: return 0;
6018 : }
6019 : }
6020 :
6021 : // FastEmit functions for ARMISD::CMPZ.
6022 :
6023 0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6024 0 : if (RetVT.SimpleTy != MVT::isVoid)
6025 : return 0;
6026 0 : if ((Subtarget->isThumb()) && (Subtarget->isThumb1Only())) {
6027 0 : return fastEmitInst_ri(ARM::tCMPi8, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
6028 : }
6029 : return 0;
6030 : }
6031 :
6032 : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6033 0 : switch (VT.SimpleTy) {
6034 0 : case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_imm0_255(RetVT, Op0, Op0IsKill, imm1);
6035 : default: return 0;
6036 : }
6037 : }
6038 :
6039 : // Top-level FastEmit function.
6040 :
6041 40 : unsigned fastEmit_ri_Predicate_imm0_255(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6042 40 : switch (Opcode) {
6043 0 : case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
6044 0 : case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_imm0_255(VT, RetVT, Op0, Op0IsKill, imm1);
6045 : default: return 0;
6046 : }
6047 : }
6048 :
6049 : // FastEmit functions for ARMISD::CMP.
6050 :
6051 0 : unsigned fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6052 0 : if (RetVT.SimpleTy != MVT::isVoid)
6053 : return 0;
6054 0 : if ((Subtarget->isThumb2())) {
6055 0 : return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
6056 : }
6057 : return 0;
6058 : }
6059 :
6060 : unsigned fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6061 0 : switch (VT.SimpleTy) {
6062 0 : case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
6063 : default: return 0;
6064 : }
6065 : }
6066 :
6067 : // FastEmit functions for ARMISD::CMPZ.
6068 :
6069 0 : unsigned fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6070 0 : if (RetVT.SimpleTy != MVT::isVoid)
6071 : return 0;
6072 0 : if ((Subtarget->isThumb2())) {
6073 0 : return fastEmitInst_ri(ARM::t2CMPri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
6074 : }
6075 : return 0;
6076 : }
6077 :
6078 : unsigned fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6079 0 : switch (VT.SimpleTy) {
6080 0 : case MVT::i32: return fastEmit_ARMISD_CMPZ_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
6081 : default: return 0;
6082 : }
6083 : }
6084 :
6085 : // FastEmit functions for ISD::ADD.
6086 :
6087 226 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6088 226 : if (RetVT.SimpleTy != MVT::i32)
6089 : return 0;
6090 226 : if ((Subtarget->isThumb2())) {
6091 226 : return fastEmitInst_ri(ARM::t2ADDri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
6092 : }
6093 : return 0;
6094 : }
6095 :
6096 : unsigned fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6097 226 : switch (VT.SimpleTy) {
6098 226 : case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
6099 : default: return 0;
6100 : }
6101 : }
6102 :
6103 : // FastEmit functions for ISD::AND.
6104 :
6105 1 : unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6106 1 : if (RetVT.SimpleTy != MVT::i32)
6107 : return 0;
6108 1 : if ((Subtarget->isThumb2())) {
6109 1 : return fastEmitInst_ri(ARM::t2ANDri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
6110 : }
6111 : return 0;
6112 : }
6113 :
6114 : unsigned fastEmit_ISD_AND_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6115 1 : switch (VT.SimpleTy) {
6116 1 : case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
6117 : default: return 0;
6118 : }
6119 : }
6120 :
6121 : // FastEmit functions for ISD::OR.
6122 :
6123 1 : unsigned fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6124 1 : if (RetVT.SimpleTy != MVT::i32)
6125 : return 0;
6126 1 : if ((Subtarget->isThumb2())) {
6127 1 : return fastEmitInst_ri(ARM::t2ORRri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
6128 : }
6129 : return 0;
6130 : }
6131 :
6132 : unsigned fastEmit_ISD_OR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6133 1 : switch (VT.SimpleTy) {
6134 1 : case MVT::i32: return fastEmit_ISD_OR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
6135 : default: return 0;
6136 : }
6137 : }
6138 :
6139 : // FastEmit functions for ISD::SUB.
6140 :
6141 0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6142 0 : if (RetVT.SimpleTy != MVT::i32)
6143 : return 0;
6144 0 : if ((Subtarget->isThumb2())) {
6145 0 : return fastEmitInst_ri(ARM::t2SUBri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
6146 : }
6147 : return 0;
6148 : }
6149 :
6150 : unsigned fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6151 0 : switch (VT.SimpleTy) {
6152 0 : case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
6153 : default: return 0;
6154 : }
6155 : }
6156 :
6157 : // FastEmit functions for ISD::XOR.
6158 :
6159 0 : unsigned fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6160 0 : if (RetVT.SimpleTy != MVT::i32)
6161 : return 0;
6162 0 : if ((Subtarget->isThumb2())) {
6163 0 : return fastEmitInst_ri(ARM::t2EORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
6164 : }
6165 : return 0;
6166 : }
6167 :
6168 : unsigned fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6169 0 : switch (VT.SimpleTy) {
6170 0 : case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_ri_Predicate_t2_so_imm(RetVT, Op0, Op0IsKill, imm1);
6171 : default: return 0;
6172 : }
6173 : }
6174 :
6175 : // Top-level FastEmit function.
6176 :
6177 243 : unsigned fastEmit_ri_Predicate_t2_so_imm(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6178 243 : switch (Opcode) {
6179 0 : case ARMISD::CMP: return fastEmit_ARMISD_CMP_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6180 0 : case ARMISD::CMPZ: return fastEmit_ARMISD_CMPZ_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6181 452 : case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6182 2 : case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6183 2 : case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6184 0 : case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6185 0 : case ISD::XOR: return fastEmit_ISD_XOR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6186 : default: return 0;
6187 : }
6188 : }
6189 :
6190 : // FastEmit functions for ISD::ADD.
6191 :
6192 195 : unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6193 195 : if (RetVT.SimpleTy != MVT::i32)
6194 : return 0;
6195 195 : if ((Subtarget->isThumb2())) {
6196 189 : return fastEmitInst_ri(ARM::t2ADDri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
6197 : }
6198 : return 0;
6199 : }
6200 :
6201 : unsigned fastEmit_ISD_ADD_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6202 195 : switch (VT.SimpleTy) {
6203 195 : case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
6204 : default: return 0;
6205 : }
6206 : }
6207 :
6208 : // FastEmit functions for ISD::SUB.
6209 :
6210 0 : unsigned fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6211 0 : if (RetVT.SimpleTy != MVT::i32)
6212 : return 0;
6213 0 : if ((Subtarget->isThumb2())) {
6214 0 : return fastEmitInst_ri(ARM::t2SUBri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
6215 : }
6216 : return 0;
6217 : }
6218 :
6219 : unsigned fastEmit_ISD_SUB_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6220 0 : switch (VT.SimpleTy) {
6221 0 : case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_ri_Predicate_imm0_4095(RetVT, Op0, Op0IsKill, imm1);
6222 : default: return 0;
6223 : }
6224 : }
6225 :
6226 : // Top-level FastEmit function.
6227 :
6228 210 : unsigned fastEmit_ri_Predicate_imm0_4095(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6229 210 : switch (Opcode) {
6230 390 : case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
6231 0 : case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
6232 : default: return 0;
6233 : }
6234 : }
6235 :
6236 : // FastEmit functions for ISD::SHL.
6237 :
6238 9 : unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6239 9 : if (RetVT.SimpleTy != MVT::i32)
6240 : return 0;
6241 9 : if ((Subtarget->isThumb2())) {
6242 6 : return fastEmitInst_ri(ARM::t2LSLri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
6243 : }
6244 : return 0;
6245 : }
6246 :
6247 : unsigned fastEmit_ISD_SHL_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6248 : switch (VT.SimpleTy) {
6249 9 : case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_imm1_31(RetVT, Op0, Op0IsKill, imm1);
6250 : default: return 0;
6251 : }
6252 : }
6253 :
6254 : // Top-level FastEmit function.
6255 :
6256 : unsigned fastEmit_ri_Predicate_imm1_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6257 15 : switch (Opcode) {
6258 9 : case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_imm1_31(VT, RetVT, Op0, Op0IsKill, imm1);
6259 : default: return 0;
6260 : }
6261 : }
6262 :
6263 : // FastEmit functions for ISD::ROTR.
6264 :
6265 0 : unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6266 0 : if (RetVT.SimpleTy != MVT::i32)
6267 : return 0;
6268 0 : if ((Subtarget->isThumb2())) {
6269 0 : return fastEmitInst_ri(ARM::t2RORri, &ARM::rGPRRegClass, Op0, Op0IsKill, imm1);
6270 : }
6271 : return 0;
6272 : }
6273 :
6274 : unsigned fastEmit_ISD_ROTR_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6275 : switch (VT.SimpleTy) {
6276 0 : case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_imm0_31(RetVT, Op0, Op0IsKill, imm1);
6277 : default: return 0;
6278 : }
6279 : }
6280 :
6281 : // Top-level FastEmit function.
6282 :
6283 : unsigned fastEmit_ri_Predicate_imm0_31(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6284 9 : switch (Opcode) {
6285 0 : case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1);
6286 : default: return 0;
6287 : }
6288 : }
6289 :
6290 : // FastEmit functions for ARMISD::VQRSHRNs.
6291 :
6292 : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6293 0 : if (RetVT.SimpleTy != MVT::v8i8)
6294 : return 0;
6295 0 : if ((Subtarget->hasNEON())) {
6296 0 : return fastEmitInst_ri(ARM::VQRSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6297 : }
6298 : return 0;
6299 : }
6300 :
6301 0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6302 0 : switch (VT.SimpleTy) {
6303 0 : case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
6304 : default: return 0;
6305 : }
6306 : }
6307 :
6308 : // FastEmit functions for ARMISD::VQRSHRNsu.
6309 :
6310 : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6311 0 : if (RetVT.SimpleTy != MVT::v8i8)
6312 : return 0;
6313 0 : if ((Subtarget->hasNEON())) {
6314 0 : return fastEmitInst_ri(ARM::VQRSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6315 : }
6316 : return 0;
6317 : }
6318 :
6319 0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6320 0 : switch (VT.SimpleTy) {
6321 0 : case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
6322 : default: return 0;
6323 : }
6324 : }
6325 :
6326 : // FastEmit functions for ARMISD::VQRSHRNu.
6327 :
6328 : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6329 0 : if (RetVT.SimpleTy != MVT::v8i8)
6330 : return 0;
6331 0 : if ((Subtarget->hasNEON())) {
6332 0 : return fastEmitInst_ri(ARM::VQRSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6333 : }
6334 : return 0;
6335 : }
6336 :
6337 0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6338 0 : switch (VT.SimpleTy) {
6339 0 : case MVT::v8i16: return fastEmit_ARMISD_VQRSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
6340 : default: return 0;
6341 : }
6342 : }
6343 :
6344 : // FastEmit functions for ARMISD::VQSHRNs.
6345 :
6346 : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6347 0 : if (RetVT.SimpleTy != MVT::v8i8)
6348 : return 0;
6349 0 : if ((Subtarget->hasNEON())) {
6350 0 : return fastEmitInst_ri(ARM::VQSHRNsv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6351 : }
6352 : return 0;
6353 : }
6354 :
6355 0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6356 0 : switch (VT.SimpleTy) {
6357 0 : case MVT::v8i16: return fastEmit_ARMISD_VQSHRNs_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
6358 : default: return 0;
6359 : }
6360 : }
6361 :
6362 : // FastEmit functions for ARMISD::VQSHRNsu.
6363 :
6364 : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6365 0 : if (RetVT.SimpleTy != MVT::v8i8)
6366 : return 0;
6367 0 : if ((Subtarget->hasNEON())) {
6368 0 : return fastEmitInst_ri(ARM::VQSHRUNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6369 : }
6370 : return 0;
6371 : }
6372 :
6373 0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6374 0 : switch (VT.SimpleTy) {
6375 0 : case MVT::v8i16: return fastEmit_ARMISD_VQSHRNsu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
6376 : default: return 0;
6377 : }
6378 : }
6379 :
6380 : // FastEmit functions for ARMISD::VQSHRNu.
6381 :
6382 : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6383 0 : if (RetVT.SimpleTy != MVT::v8i8)
6384 : return 0;
6385 0 : if ((Subtarget->hasNEON())) {
6386 0 : return fastEmitInst_ri(ARM::VQSHRNuv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6387 : }
6388 : return 0;
6389 : }
6390 :
6391 0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6392 0 : switch (VT.SimpleTy) {
6393 0 : case MVT::v8i16: return fastEmit_ARMISD_VQSHRNu_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
6394 : default: return 0;
6395 : }
6396 : }
6397 :
6398 : // FastEmit functions for ARMISD::VRSHRN.
6399 :
6400 : unsigned fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6401 0 : if (RetVT.SimpleTy != MVT::v8i8)
6402 : return 0;
6403 0 : if ((Subtarget->hasNEON())) {
6404 0 : return fastEmitInst_ri(ARM::VRSHRNv8i8, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6405 : }
6406 : return 0;
6407 : }
6408 :
6409 0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6410 0 : switch (VT.SimpleTy) {
6411 0 : case MVT::v8i16: return fastEmit_ARMISD_VRSHRN_MVT_v8i16_ri_Predicate_shr_imm8(RetVT, Op0, Op0IsKill, imm1);
6412 : default: return 0;
6413 : }
6414 : }
6415 :
6416 : // Top-level FastEmit function.
6417 :
6418 9 : unsigned fastEmit_ri_Predicate_shr_imm8(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6419 9 : switch (Opcode) {
6420 0 : case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
6421 0 : case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
6422 0 : case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
6423 0 : case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
6424 0 : case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
6425 0 : case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
6426 0 : case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm8(VT, RetVT, Op0, Op0IsKill, imm1);
6427 : default: return 0;
6428 : }
6429 : }
6430 :
6431 : // FastEmit functions for ARMISD::VQRSHRNs.
6432 :
6433 : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6434 0 : if (RetVT.SimpleTy != MVT::v4i16)
6435 : return 0;
6436 0 : if ((Subtarget->hasNEON())) {
6437 0 : return fastEmitInst_ri(ARM::VQRSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6438 : }
6439 : return 0;
6440 : }
6441 :
6442 0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6443 0 : switch (VT.SimpleTy) {
6444 0 : case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
6445 : default: return 0;
6446 : }
6447 : }
6448 :
6449 : // FastEmit functions for ARMISD::VQRSHRNsu.
6450 :
6451 : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6452 0 : if (RetVT.SimpleTy != MVT::v4i16)
6453 : return 0;
6454 0 : if ((Subtarget->hasNEON())) {
6455 0 : return fastEmitInst_ri(ARM::VQRSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6456 : }
6457 : return 0;
6458 : }
6459 :
6460 0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6461 0 : switch (VT.SimpleTy) {
6462 0 : case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
6463 : default: return 0;
6464 : }
6465 : }
6466 :
6467 : // FastEmit functions for ARMISD::VQRSHRNu.
6468 :
6469 : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6470 0 : if (RetVT.SimpleTy != MVT::v4i16)
6471 : return 0;
6472 0 : if ((Subtarget->hasNEON())) {
6473 0 : return fastEmitInst_ri(ARM::VQRSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6474 : }
6475 : return 0;
6476 : }
6477 :
6478 0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6479 0 : switch (VT.SimpleTy) {
6480 0 : case MVT::v4i32: return fastEmit_ARMISD_VQRSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
6481 : default: return 0;
6482 : }
6483 : }
6484 :
6485 : // FastEmit functions for ARMISD::VQSHRNs.
6486 :
6487 : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6488 0 : if (RetVT.SimpleTy != MVT::v4i16)
6489 : return 0;
6490 0 : if ((Subtarget->hasNEON())) {
6491 0 : return fastEmitInst_ri(ARM::VQSHRNsv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6492 : }
6493 : return 0;
6494 : }
6495 :
6496 0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6497 0 : switch (VT.SimpleTy) {
6498 0 : case MVT::v4i32: return fastEmit_ARMISD_VQSHRNs_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
6499 : default: return 0;
6500 : }
6501 : }
6502 :
6503 : // FastEmit functions for ARMISD::VQSHRNsu.
6504 :
6505 : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6506 0 : if (RetVT.SimpleTy != MVT::v4i16)
6507 : return 0;
6508 0 : if ((Subtarget->hasNEON())) {
6509 0 : return fastEmitInst_ri(ARM::VQSHRUNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6510 : }
6511 : return 0;
6512 : }
6513 :
6514 0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6515 0 : switch (VT.SimpleTy) {
6516 0 : case MVT::v4i32: return fastEmit_ARMISD_VQSHRNsu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
6517 : default: return 0;
6518 : }
6519 : }
6520 :
6521 : // FastEmit functions for ARMISD::VQSHRNu.
6522 :
6523 : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6524 0 : if (RetVT.SimpleTy != MVT::v4i16)
6525 : return 0;
6526 0 : if ((Subtarget->hasNEON())) {
6527 0 : return fastEmitInst_ri(ARM::VQSHRNuv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6528 : }
6529 : return 0;
6530 : }
6531 :
6532 0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6533 0 : switch (VT.SimpleTy) {
6534 0 : case MVT::v4i32: return fastEmit_ARMISD_VQSHRNu_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
6535 : default: return 0;
6536 : }
6537 : }
6538 :
6539 : // FastEmit functions for ARMISD::VRSHRN.
6540 :
6541 : unsigned fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6542 0 : if (RetVT.SimpleTy != MVT::v4i16)
6543 : return 0;
6544 0 : if ((Subtarget->hasNEON())) {
6545 0 : return fastEmitInst_ri(ARM::VRSHRNv4i16, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6546 : }
6547 : return 0;
6548 : }
6549 :
6550 0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6551 0 : switch (VT.SimpleTy) {
6552 0 : case MVT::v4i32: return fastEmit_ARMISD_VRSHRN_MVT_v4i32_ri_Predicate_shr_imm16(RetVT, Op0, Op0IsKill, imm1);
6553 : default: return 0;
6554 : }
6555 : }
6556 :
6557 : // Top-level FastEmit function.
6558 :
6559 9 : unsigned fastEmit_ri_Predicate_shr_imm16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6560 9 : switch (Opcode) {
6561 0 : case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
6562 0 : case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
6563 0 : case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
6564 0 : case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
6565 0 : case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
6566 0 : case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
6567 0 : case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm16(VT, RetVT, Op0, Op0IsKill, imm1);
6568 : default: return 0;
6569 : }
6570 : }
6571 :
6572 : // FastEmit functions for ARMISD::VQRSHRNs.
6573 :
6574 : unsigned fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6575 0 : if (RetVT.SimpleTy != MVT::v2i32)
6576 : return 0;
6577 0 : if ((Subtarget->hasNEON())) {
6578 0 : return fastEmitInst_ri(ARM::VQRSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6579 : }
6580 : return 0;
6581 : }
6582 :
6583 0 : unsigned fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6584 0 : switch (VT.SimpleTy) {
6585 0 : case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
6586 : default: return 0;
6587 : }
6588 : }
6589 :
6590 : // FastEmit functions for ARMISD::VQRSHRNsu.
6591 :
6592 : unsigned fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6593 0 : if (RetVT.SimpleTy != MVT::v2i32)
6594 : return 0;
6595 0 : if ((Subtarget->hasNEON())) {
6596 0 : return fastEmitInst_ri(ARM::VQRSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6597 : }
6598 : return 0;
6599 : }
6600 :
6601 0 : unsigned fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6602 0 : switch (VT.SimpleTy) {
6603 0 : case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
6604 : default: return 0;
6605 : }
6606 : }
6607 :
6608 : // FastEmit functions for ARMISD::VQRSHRNu.
6609 :
6610 : unsigned fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6611 0 : if (RetVT.SimpleTy != MVT::v2i32)
6612 : return 0;
6613 0 : if ((Subtarget->hasNEON())) {
6614 0 : return fastEmitInst_ri(ARM::VQRSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6615 : }
6616 : return 0;
6617 : }
6618 :
6619 0 : unsigned fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6620 0 : switch (VT.SimpleTy) {
6621 0 : case MVT::v2i64: return fastEmit_ARMISD_VQRSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
6622 : default: return 0;
6623 : }
6624 : }
6625 :
6626 : // FastEmit functions for ARMISD::VQSHRNs.
6627 :
6628 : unsigned fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6629 0 : if (RetVT.SimpleTy != MVT::v2i32)
6630 : return 0;
6631 0 : if ((Subtarget->hasNEON())) {
6632 0 : return fastEmitInst_ri(ARM::VQSHRNsv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6633 : }
6634 : return 0;
6635 : }
6636 :
6637 0 : unsigned fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6638 0 : switch (VT.SimpleTy) {
6639 0 : case MVT::v2i64: return fastEmit_ARMISD_VQSHRNs_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
6640 : default: return 0;
6641 : }
6642 : }
6643 :
6644 : // FastEmit functions for ARMISD::VQSHRNsu.
6645 :
6646 : unsigned fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6647 0 : if (RetVT.SimpleTy != MVT::v2i32)
6648 : return 0;
6649 0 : if ((Subtarget->hasNEON())) {
6650 0 : return fastEmitInst_ri(ARM::VQSHRUNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6651 : }
6652 : return 0;
6653 : }
6654 :
6655 0 : unsigned fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6656 0 : switch (VT.SimpleTy) {
6657 0 : case MVT::v2i64: return fastEmit_ARMISD_VQSHRNsu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
6658 : default: return 0;
6659 : }
6660 : }
6661 :
6662 : // FastEmit functions for ARMISD::VQSHRNu.
6663 :
6664 : unsigned fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6665 0 : if (RetVT.SimpleTy != MVT::v2i32)
6666 : return 0;
6667 0 : if ((Subtarget->hasNEON())) {
6668 0 : return fastEmitInst_ri(ARM::VQSHRNuv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6669 : }
6670 : return 0;
6671 : }
6672 :
6673 0 : unsigned fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6674 0 : switch (VT.SimpleTy) {
6675 0 : case MVT::v2i64: return fastEmit_ARMISD_VQSHRNu_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
6676 : default: return 0;
6677 : }
6678 : }
6679 :
6680 : // FastEmit functions for ARMISD::VRSHRN.
6681 :
6682 : unsigned fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6683 0 : if (RetVT.SimpleTy != MVT::v2i32)
6684 : return 0;
6685 0 : if ((Subtarget->hasNEON())) {
6686 0 : return fastEmitInst_ri(ARM::VRSHRNv2i32, &ARM::DPRRegClass, Op0, Op0IsKill, imm1);
6687 : }
6688 : return 0;
6689 : }
6690 :
6691 0 : unsigned fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6692 0 : switch (VT.SimpleTy) {
6693 0 : case MVT::v2i64: return fastEmit_ARMISD_VRSHRN_MVT_v2i64_ri_Predicate_shr_imm32(RetVT, Op0, Op0IsKill, imm1);
6694 : default: return 0;
6695 : }
6696 : }
6697 :
6698 : // Top-level FastEmit function.
6699 :
6700 9 : unsigned fastEmit_ri_Predicate_shr_imm32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6701 9 : switch (Opcode) {
6702 0 : case ARMISD::VQRSHRNs: return fastEmit_ARMISD_VQRSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
6703 0 : case ARMISD::VQRSHRNsu: return fastEmit_ARMISD_VQRSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
6704 0 : case ARMISD::VQRSHRNu: return fastEmit_ARMISD_VQRSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
6705 0 : case ARMISD::VQSHRNs: return fastEmit_ARMISD_VQSHRNs_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
6706 0 : case ARMISD::VQSHRNsu: return fastEmit_ARMISD_VQSHRNsu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
6707 0 : case ARMISD::VQSHRNu: return fastEmit_ARMISD_VQSHRNu_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
6708 0 : case ARMISD::VRSHRN: return fastEmit_ARMISD_VRSHRN_ri_Predicate_shr_imm32(VT, RetVT, Op0, Op0IsKill, imm1);
6709 : default: return 0;
6710 : }
6711 : }
6712 :
6713 : // FastEmit functions for ARMISD::VDUPLANE.
6714 :
6715 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6716 0 : if (RetVT.SimpleTy != MVT::v16i8)
6717 : return 0;
6718 0 : if ((Subtarget->hasNEON())) {
6719 0 : return fastEmitInst_ri(ARM::VDUPLN8q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
6720 : }
6721 : return 0;
6722 : }
6723 :
6724 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6725 0 : if (RetVT.SimpleTy != MVT::v8i16)
6726 : return 0;
6727 0 : if ((Subtarget->hasNEON())) {
6728 0 : return fastEmitInst_ri(ARM::VDUPLN16q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
6729 : }
6730 : return 0;
6731 : }
6732 :
6733 : unsigned fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6734 0 : if (RetVT.SimpleTy != MVT::v4i32)
6735 : return 0;
6736 0 : if ((Subtarget->hasNEON())) {
6737 0 : return fastEmitInst_ri(ARM::VDUPLN32q, &ARM::QPRRegClass, Op0, Op0IsKill, imm1);
6738 : }
6739 : return 0;
6740 : }
6741 :
6742 0 : unsigned fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6743 0 : switch (VT.SimpleTy) {
6744 0 : case MVT::v8i8: return fastEmit_ARMISD_VDUPLANE_MVT_v8i8_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
6745 0 : case MVT::v4i16: return fastEmit_ARMISD_VDUPLANE_MVT_v4i16_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
6746 0 : case MVT::v2i32: return fastEmit_ARMISD_VDUPLANE_MVT_v2i32_ri_Predicate_VectorIndex32(RetVT, Op0, Op0IsKill, imm1);
6747 : default: return 0;
6748 : }
6749 : }
6750 :
6751 : // Top-level FastEmit function.
6752 :
6753 : unsigned fastEmit_ri_Predicate_VectorIndex32(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
6754 0 : switch (Opcode) {
6755 0 : case ARMISD::VDUPLANE: return fastEmit_ARMISD_VDUPLANE_ri_Predicate_VectorIndex32(VT, RetVT, Op0, Op0IsKill, imm1);
6756 : default: return 0;
6757 : }
6758 : }
6759 :
6760 : // FastEmit functions for ISD::Constant.
6761 :
6762 45 : unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
6763 45 : if (RetVT.SimpleTy != MVT::i32)
6764 : return 0;
6765 45 : if ((Subtarget->isThumb()) && (Subtarget->useMovt(*MF))) {
6766 15 : return fastEmitInst_i(ARM::t2MOVi32imm, &ARM::rGPRRegClass, imm0);
6767 : }
6768 : return 0;
6769 : }
6770 :
6771 : unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
6772 6 : switch (VT.SimpleTy) {
6773 45 : case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
6774 : default: return 0;
6775 : }
6776 : }
6777 :
6778 : // Top-level FastEmit function.
6779 :
6780 39 : unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
6781 39 : switch (Opcode) {
6782 84 : case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
6783 : default: return 0;
6784 : }
6785 : }
6786 :
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