Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Target Instruction Enum Values and Descriptors *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 : #ifdef GET_INSTRINFO_ENUM
10 : #undef GET_INSTRINFO_ENUM
11 : namespace llvm {
12 :
13 : namespace Lanai {
14 : enum {
15 : PHI = 0,
16 : INLINEASM = 1,
17 : CFI_INSTRUCTION = 2,
18 : EH_LABEL = 3,
19 : GC_LABEL = 4,
20 : ANNOTATION_LABEL = 5,
21 : KILL = 6,
22 : EXTRACT_SUBREG = 7,
23 : INSERT_SUBREG = 8,
24 : IMPLICIT_DEF = 9,
25 : SUBREG_TO_REG = 10,
26 : COPY_TO_REGCLASS = 11,
27 : DBG_VALUE = 12,
28 : DBG_LABEL = 13,
29 : REG_SEQUENCE = 14,
30 : COPY = 15,
31 : BUNDLE = 16,
32 : LIFETIME_START = 17,
33 : LIFETIME_END = 18,
34 : STACKMAP = 19,
35 : FENTRY_CALL = 20,
36 : PATCHPOINT = 21,
37 : LOAD_STACK_GUARD = 22,
38 : STATEPOINT = 23,
39 : LOCAL_ESCAPE = 24,
40 : FAULTING_OP = 25,
41 : PATCHABLE_OP = 26,
42 : PATCHABLE_FUNCTION_ENTER = 27,
43 : PATCHABLE_RET = 28,
44 : PATCHABLE_FUNCTION_EXIT = 29,
45 : PATCHABLE_TAIL_CALL = 30,
46 : PATCHABLE_EVENT_CALL = 31,
47 : PATCHABLE_TYPED_EVENT_CALL = 32,
48 : ICALL_BRANCH_FUNNEL = 33,
49 : G_ADD = 34,
50 : G_SUB = 35,
51 : G_MUL = 36,
52 : G_SDIV = 37,
53 : G_UDIV = 38,
54 : G_SREM = 39,
55 : G_UREM = 40,
56 : G_AND = 41,
57 : G_OR = 42,
58 : G_XOR = 43,
59 : G_IMPLICIT_DEF = 44,
60 : G_PHI = 45,
61 : G_FRAME_INDEX = 46,
62 : G_GLOBAL_VALUE = 47,
63 : G_EXTRACT = 48,
64 : G_UNMERGE_VALUES = 49,
65 : G_INSERT = 50,
66 : G_MERGE_VALUES = 51,
67 : G_PTRTOINT = 52,
68 : G_INTTOPTR = 53,
69 : G_BITCAST = 54,
70 : G_INTRINSIC_TRUNC = 55,
71 : G_INTRINSIC_ROUND = 56,
72 : G_LOAD = 57,
73 : G_SEXTLOAD = 58,
74 : G_ZEXTLOAD = 59,
75 : G_STORE = 60,
76 : G_ATOMIC_CMPXCHG_WITH_SUCCESS = 61,
77 : G_ATOMIC_CMPXCHG = 62,
78 : G_ATOMICRMW_XCHG = 63,
79 : G_ATOMICRMW_ADD = 64,
80 : G_ATOMICRMW_SUB = 65,
81 : G_ATOMICRMW_AND = 66,
82 : G_ATOMICRMW_NAND = 67,
83 : G_ATOMICRMW_OR = 68,
84 : G_ATOMICRMW_XOR = 69,
85 : G_ATOMICRMW_MAX = 70,
86 : G_ATOMICRMW_MIN = 71,
87 : G_ATOMICRMW_UMAX = 72,
88 : G_ATOMICRMW_UMIN = 73,
89 : G_BRCOND = 74,
90 : G_BRINDIRECT = 75,
91 : G_INTRINSIC = 76,
92 : G_INTRINSIC_W_SIDE_EFFECTS = 77,
93 : G_ANYEXT = 78,
94 : G_TRUNC = 79,
95 : G_CONSTANT = 80,
96 : G_FCONSTANT = 81,
97 : G_VASTART = 82,
98 : G_VAARG = 83,
99 : G_SEXT = 84,
100 : G_ZEXT = 85,
101 : G_SHL = 86,
102 : G_LSHR = 87,
103 : G_ASHR = 88,
104 : G_ICMP = 89,
105 : G_FCMP = 90,
106 : G_SELECT = 91,
107 : G_UADDO = 92,
108 : G_UADDE = 93,
109 : G_USUBO = 94,
110 : G_USUBE = 95,
111 : G_SADDO = 96,
112 : G_SADDE = 97,
113 : G_SSUBO = 98,
114 : G_SSUBE = 99,
115 : G_UMULO = 100,
116 : G_SMULO = 101,
117 : G_UMULH = 102,
118 : G_SMULH = 103,
119 : G_FADD = 104,
120 : G_FSUB = 105,
121 : G_FMUL = 106,
122 : G_FMA = 107,
123 : G_FDIV = 108,
124 : G_FREM = 109,
125 : G_FPOW = 110,
126 : G_FEXP = 111,
127 : G_FEXP2 = 112,
128 : G_FLOG = 113,
129 : G_FLOG2 = 114,
130 : G_FNEG = 115,
131 : G_FPEXT = 116,
132 : G_FPTRUNC = 117,
133 : G_FPTOSI = 118,
134 : G_FPTOUI = 119,
135 : G_SITOFP = 120,
136 : G_UITOFP = 121,
137 : G_FABS = 122,
138 : G_GEP = 123,
139 : G_PTR_MASK = 124,
140 : G_BR = 125,
141 : G_INSERT_VECTOR_ELT = 126,
142 : G_EXTRACT_VECTOR_ELT = 127,
143 : G_SHUFFLE_VECTOR = 128,
144 : G_CTTZ = 129,
145 : G_CTTZ_ZERO_UNDEF = 130,
146 : G_CTLZ = 131,
147 : G_CTLZ_ZERO_UNDEF = 132,
148 : G_CTPOP = 133,
149 : G_BSWAP = 134,
150 : G_ADDRSPACE_CAST = 135,
151 : G_BLOCK_ADDR = 136,
152 : ADJCALLSTACKDOWN = 137,
153 : ADJCALLSTACKUP = 138,
154 : ADJDYNALLOC = 139,
155 : CALL = 140,
156 : CALLR = 141,
157 : ADDC_F_I_HI = 142,
158 : ADDC_F_I_LO = 143,
159 : ADDC_F_R = 144,
160 : ADDC_I_HI = 145,
161 : ADDC_I_LO = 146,
162 : ADDC_R = 147,
163 : ADD_F_I_HI = 148,
164 : ADD_F_I_LO = 149,
165 : ADD_F_R = 150,
166 : ADD_I_HI = 151,
167 : ADD_I_LO = 152,
168 : ADD_R = 153,
169 : AND_F_I_HI = 154,
170 : AND_F_I_LO = 155,
171 : AND_F_R = 156,
172 : AND_I_HI = 157,
173 : AND_I_LO = 158,
174 : AND_R = 159,
175 : BRCC = 160,
176 : BRIND_CC = 161,
177 : BRIND_CCA = 162,
178 : BRR = 163,
179 : BT = 164,
180 : JR = 165,
181 : LDADDR = 166,
182 : LDBs_RI = 167,
183 : LDBs_RR = 168,
184 : LDBz_RI = 169,
185 : LDBz_RR = 170,
186 : LDHs_RI = 171,
187 : LDHs_RR = 172,
188 : LDHz_RI = 173,
189 : LDHz_RR = 174,
190 : LDW_RI = 175,
191 : LDW_RR = 176,
192 : LDWz_RR = 177,
193 : LEADZ = 178,
194 : LOG0 = 179,
195 : LOG1 = 180,
196 : LOG2 = 181,
197 : LOG3 = 182,
198 : LOG4 = 183,
199 : MOVHI = 184,
200 : NOP = 185,
201 : OR_F_I_HI = 186,
202 : OR_F_I_LO = 187,
203 : OR_F_R = 188,
204 : OR_I_HI = 189,
205 : OR_I_LO = 190,
206 : OR_R = 191,
207 : POPC = 192,
208 : RET = 193,
209 : SA_F_I = 194,
210 : SA_I = 195,
211 : SCC = 196,
212 : SELECT = 197,
213 : SFSUB_F_RI_HI = 198,
214 : SFSUB_F_RI_LO = 199,
215 : SFSUB_F_RR = 200,
216 : SHL_F_R = 201,
217 : SHL_R = 202,
218 : SLI = 203,
219 : SL_F_I = 204,
220 : SL_I = 205,
221 : SRA_F_R = 206,
222 : SRA_R = 207,
223 : SRL_F_R = 208,
224 : SRL_R = 209,
225 : STADDR = 210,
226 : STB_RI = 211,
227 : STB_RR = 212,
228 : STH_RI = 213,
229 : STH_RR = 214,
230 : SUBB_F_I_HI = 215,
231 : SUBB_F_I_LO = 216,
232 : SUBB_F_R = 217,
233 : SUBB_I_HI = 218,
234 : SUBB_I_LO = 219,
235 : SUBB_R = 220,
236 : SUB_F_I_HI = 221,
237 : SUB_F_I_LO = 222,
238 : SUB_F_R = 223,
239 : SUB_I_HI = 224,
240 : SUB_I_LO = 225,
241 : SUB_R = 226,
242 : SW_RI = 227,
243 : SW_RR = 228,
244 : TRAILZ = 229,
245 : XOR_F_I_HI = 230,
246 : XOR_F_I_LO = 231,
247 : XOR_F_R = 232,
248 : XOR_I_HI = 233,
249 : XOR_I_LO = 234,
250 : XOR_R = 235,
251 : INSTRUCTION_LIST_END = 236
252 : };
253 :
254 : } // end Lanai namespace
255 : } // end llvm namespace
256 : #endif // GET_INSTRINFO_ENUM
257 :
258 : #ifdef GET_INSTRINFO_SCHED_ENUM
259 : #undef GET_INSTRINFO_SCHED_ENUM
260 : namespace llvm {
261 :
262 : namespace Lanai {
263 : namespace Sched {
264 : enum {
265 : NoInstrModel = 0,
266 : IIC_ALU_WriteALU = 1,
267 : IIC_ALU = 2,
268 : IIC_LD_WriteLD = 3,
269 : IIC_LDSW_WriteLDSW = 4,
270 : WriteLD = 5,
271 : IIC_ST_WriteST = 6,
272 : IIC_STSW_WriteSTSW = 7,
273 : SCHED_LIST_END = 8
274 : };
275 : } // end Sched namespace
276 : } // end Lanai namespace
277 : } // end llvm namespace
278 : #endif // GET_INSTRINFO_SCHED_ENUM
279 :
280 : #ifdef GET_INSTRINFO_MC_DESC
281 : #undef GET_INSTRINFO_MC_DESC
282 : namespace llvm {
283 :
284 : static const MCPhysReg ImplicitList1[] = { Lanai::SP, 0 };
285 : static const MCPhysReg ImplicitList2[] = { Lanai::RCA, 0 };
286 : static const MCPhysReg ImplicitList3[] = { Lanai::SR, 0 };
287 :
288 : static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
289 : static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
290 : static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
291 : static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
292 : static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
293 : static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
294 : static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
295 : static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
296 : static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
297 : static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
298 : static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
299 : static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
300 : static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
301 : static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
302 : static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
303 : static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
304 : static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
305 : static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
306 : static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
307 : static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
308 : static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
309 : static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
310 : static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
311 : static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
312 : static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
313 : static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
314 : static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
315 : static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
316 : static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
317 : static const MCOperandInfo OperandInfo31[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
318 : static const MCOperandInfo OperandInfo32[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
319 : static const MCOperandInfo OperandInfo33[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
320 : static const MCOperandInfo OperandInfo34[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
321 : static const MCOperandInfo OperandInfo35[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
322 : static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
323 : static const MCOperandInfo OperandInfo37[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
324 : static const MCOperandInfo OperandInfo38[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
325 : static const MCOperandInfo OperandInfo39[] = { { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
326 :
327 : extern const MCInstrDesc LanaiInsts[] = {
328 : { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
329 : { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
330 : { 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2 = CFI_INSTRUCTION
331 : { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = EH_LABEL
332 : { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = GC_LABEL
333 : { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = ANNOTATION_LABEL
334 : { 6, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #6 = KILL
335 : { 7, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #7 = EXTRACT_SUBREG
336 : { 8, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #8 = INSERT_SUBREG
337 : { 9, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #9 = IMPLICIT_DEF
338 : { 10, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #10 = SUBREG_TO_REG
339 : { 11, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #11 = COPY_TO_REGCLASS
340 : { 12, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #12 = DBG_VALUE
341 : { 13, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #13 = DBG_LABEL
342 : { 14, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #14 = REG_SEQUENCE
343 : { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = COPY
344 : { 16, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #16 = BUNDLE
345 : { 17, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #17 = LIFETIME_START
346 : { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_END
347 : { 19, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #19 = STACKMAP
348 : { 20, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #20 = FENTRY_CALL
349 : { 21, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #21 = PATCHPOINT
350 : { 22, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #22 = LOAD_STACK_GUARD
351 : { 23, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #23 = STATEPOINT
352 : { 24, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #24 = LOCAL_ESCAPE
353 : { 25, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #25 = FAULTING_OP
354 : { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = PATCHABLE_OP
355 : { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_FUNCTION_ENTER
356 : { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_RET
357 : { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_FUNCTION_EXIT
358 : { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_TAIL_CALL
359 : { 31, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #31 = PATCHABLE_EVENT_CALL
360 : { 32, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
361 : { 33, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #33 = ICALL_BRANCH_FUNNEL
362 : { 34, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #34 = G_ADD
363 : { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_SUB
364 : { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_MUL
365 : { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_SDIV
366 : { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_UDIV
367 : { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_SREM
368 : { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_UREM
369 : { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_AND
370 : { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_OR
371 : { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_XOR
372 : { 44, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = G_IMPLICIT_DEF
373 : { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_PHI
374 : { 46, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = G_FRAME_INDEX
375 : { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_GLOBAL_VALUE
376 : { 48, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #48 = G_EXTRACT
377 : { 49, 2, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #49 = G_UNMERGE_VALUES
378 : { 50, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #50 = G_INSERT
379 : { 51, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #51 = G_MERGE_VALUES
380 : { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_PTRTOINT
381 : { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_INTTOPTR
382 : { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BITCAST
383 : { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #55 = G_INTRINSIC_TRUNC
384 : { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #56 = G_INTRINSIC_ROUND
385 : { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_LOAD
386 : { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_SEXTLOAD
387 : { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #59 = G_ZEXTLOAD
388 : { 60, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #60 = G_STORE
389 : { 61, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #61 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
390 : { 62, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #62 = G_ATOMIC_CMPXCHG
391 : { 63, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #63 = G_ATOMICRMW_XCHG
392 : { 64, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #64 = G_ATOMICRMW_ADD
393 : { 65, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #65 = G_ATOMICRMW_SUB
394 : { 66, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #66 = G_ATOMICRMW_AND
395 : { 67, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #67 = G_ATOMICRMW_NAND
396 : { 68, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #68 = G_ATOMICRMW_OR
397 : { 69, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_ATOMICRMW_XOR
398 : { 70, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #70 = G_ATOMICRMW_MAX
399 : { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_MIN
400 : { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_UMAX
401 : { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_UMIN
402 : { 74, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #74 = G_BRCOND
403 : { 75, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #75 = G_BRINDIRECT
404 : { 76, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #76 = G_INTRINSIC
405 : { 77, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #77 = G_INTRINSIC_W_SIDE_EFFECTS
406 : { 78, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #78 = G_ANYEXT
407 : { 79, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #79 = G_TRUNC
408 : { 80, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #80 = G_CONSTANT
409 : { 81, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #81 = G_FCONSTANT
410 : { 82, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #82 = G_VASTART
411 : { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #83 = G_VAARG
412 : { 84, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #84 = G_SEXT
413 : { 85, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #85 = G_ZEXT
414 : { 86, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #86 = G_SHL
415 : { 87, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #87 = G_LSHR
416 : { 88, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #88 = G_ASHR
417 : { 89, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #89 = G_ICMP
418 : { 90, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #90 = G_FCMP
419 : { 91, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #91 = G_SELECT
420 : { 92, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #92 = G_UADDO
421 : { 93, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #93 = G_UADDE
422 : { 94, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #94 = G_USUBO
423 : { 95, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #95 = G_USUBE
424 : { 96, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #96 = G_SADDO
425 : { 97, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #97 = G_SADDE
426 : { 98, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #98 = G_SSUBO
427 : { 99, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #99 = G_SSUBE
428 : { 100, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #100 = G_UMULO
429 : { 101, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #101 = G_SMULO
430 : { 102, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #102 = G_UMULH
431 : { 103, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #103 = G_SMULH
432 : { 104, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #104 = G_FADD
433 : { 105, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #105 = G_FSUB
434 : { 106, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #106 = G_FMUL
435 : { 107, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #107 = G_FMA
436 : { 108, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #108 = G_FDIV
437 : { 109, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #109 = G_FREM
438 : { 110, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #110 = G_FPOW
439 : { 111, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #111 = G_FEXP
440 : { 112, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #112 = G_FEXP2
441 : { 113, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #113 = G_FLOG
442 : { 114, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #114 = G_FLOG2
443 : { 115, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #115 = G_FNEG
444 : { 116, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #116 = G_FPEXT
445 : { 117, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #117 = G_FPTRUNC
446 : { 118, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #118 = G_FPTOSI
447 : { 119, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #119 = G_FPTOUI
448 : { 120, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #120 = G_SITOFP
449 : { 121, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #121 = G_UITOFP
450 : { 122, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #122 = G_FABS
451 : { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #123 = G_GEP
452 : { 124, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #124 = G_PTR_MASK
453 : { 125, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #125 = G_BR
454 : { 126, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #126 = G_INSERT_VECTOR_ELT
455 : { 127, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #127 = G_EXTRACT_VECTOR_ELT
456 : { 128, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #128 = G_SHUFFLE_VECTOR
457 : { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #129 = G_CTTZ
458 : { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #130 = G_CTTZ_ZERO_UNDEF
459 : { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #131 = G_CTLZ
460 : { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #132 = G_CTLZ_ZERO_UNDEF
461 : { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #133 = G_CTPOP
462 : { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #134 = G_BSWAP
463 : { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #135 = G_ADDRSPACE_CAST
464 : { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #136 = G_BLOCK_ADDR
465 : { 137, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #137 = ADJCALLSTACKDOWN
466 : { 138, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #138 = ADJCALLSTACKUP
467 : { 139, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #139 = ADJDYNALLOC
468 : { 140, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #140 = CALL
469 : { 141, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList2, OperandInfo32, -1 ,nullptr }, // Inst #141 = CALLR
470 : { 142, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #142 = ADDC_F_I_HI
471 : { 143, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #143 = ADDC_F_I_LO
472 : { 144, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #144 = ADDC_F_R
473 : { 145, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #145 = ADDC_I_HI
474 : { 146, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #146 = ADDC_I_LO
475 : { 147, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #147 = ADDC_R
476 : { 148, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #148 = ADD_F_I_HI
477 : { 149, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #149 = ADD_F_I_LO
478 : { 150, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #150 = ADD_F_R
479 : { 151, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #151 = ADD_I_HI
480 : { 152, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #152 = ADD_I_LO
481 : { 153, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #153 = ADD_R
482 : { 154, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #154 = AND_F_I_HI
483 : { 155, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #155 = AND_F_I_LO
484 : { 156, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #156 = AND_F_R
485 : { 157, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #157 = AND_I_HI
486 : { 158, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #158 = AND_I_LO
487 : { 159, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #159 = AND_R
488 : { 160, 2, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #160 = BRCC
489 : { 161, 2, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #161 = BRIND_CC
490 : { 162, 3, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #162 = BRIND_CCA
491 : { 163, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #163 = BRR
492 : { 164, 1, 0, 4, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #164 = BT
493 : { 165, 1, 0, 4, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #165 = JR
494 : { 166, 2, 1, 4, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #166 = LDADDR
495 : { 167, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #167 = LDBs_RI
496 : { 168, 4, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #168 = LDBs_RR
497 : { 169, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #169 = LDBz_RI
498 : { 170, 4, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #170 = LDBz_RR
499 : { 171, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #171 = LDHs_RI
500 : { 172, 4, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #172 = LDHs_RR
501 : { 173, 4, 1, 4, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #173 = LDHz_RI
502 : { 174, 4, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #174 = LDHz_RR
503 : { 175, 4, 1, 4, 3, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #175 = LDW_RI
504 : { 176, 4, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #176 = LDW_RR
505 : { 177, 4, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #177 = LDWz_RR
506 : { 178, 2, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #178 = LEADZ
507 : { 179, 0, 0, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #179 = LOG0
508 : { 180, 0, 0, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #180 = LOG1
509 : { 181, 0, 0, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #181 = LOG2
510 : { 182, 0, 0, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #182 = LOG3
511 : { 183, 0, 0, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #183 = LOG4
512 : { 184, 2, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #184 = MOVHI
513 : { 185, 0, 0, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #185 = NOP
514 : { 186, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #186 = OR_F_I_HI
515 : { 187, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #187 = OR_F_I_LO
516 : { 188, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #188 = OR_F_R
517 : { 189, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #189 = OR_I_HI
518 : { 190, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #190 = OR_I_LO
519 : { 191, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #191 = OR_R
520 : { 192, 2, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #192 = POPC
521 : { 193, 0, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, nullptr, nullptr, -1 ,nullptr }, // Inst #193 = RET
522 : { 194, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #194 = SA_F_I
523 : { 195, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #195 = SA_I
524 : { 196, 2, 1, 4, 2, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #196 = SCC
525 : { 197, 4, 1, 4, 1, 0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #197 = SELECT
526 : { 198, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr }, // Inst #198 = SFSUB_F_RI_HI
527 : { 199, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo35, -1 ,nullptr }, // Inst #199 = SFSUB_F_RI_LO
528 : { 200, 2, 0, 4, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #200 = SFSUB_F_RR
529 : { 201, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #201 = SHL_F_R
530 : { 202, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #202 = SHL_R
531 : { 203, 2, 1, 4, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #203 = SLI
532 : { 204, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #204 = SL_F_I
533 : { 205, 3, 1, 4, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #205 = SL_I
534 : { 206, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #206 = SRA_F_R
535 : { 207, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #207 = SRA_R
536 : { 208, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #208 = SRL_F_R
537 : { 209, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #209 = SRL_R
538 : { 210, 2, 0, 4, 6, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #210 = STADDR
539 : { 211, 4, 0, 4, 7, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #211 = STB_RI
540 : { 212, 4, 0, 4, 6, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #212 = STB_RR
541 : { 213, 4, 0, 4, 7, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #213 = STH_RI
542 : { 214, 4, 0, 4, 6, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #214 = STH_RR
543 : { 215, 3, 1, 4, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #215 = SUBB_F_I_HI
544 : { 216, 3, 1, 4, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #216 = SUBB_F_I_LO
545 : { 217, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #217 = SUBB_F_R
546 : { 218, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #218 = SUBB_I_HI
547 : { 219, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #219 = SUBB_I_LO
548 : { 220, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #220 = SUBB_R
549 : { 221, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #221 = SUB_F_I_HI
550 : { 222, 3, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #222 = SUB_F_I_LO
551 : { 223, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #223 = SUB_F_R
552 : { 224, 3, 1, 4, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #224 = SUB_I_HI
553 : { 225, 3, 1, 4, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #225 = SUB_I_LO
554 : { 226, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #226 = SUB_R
555 : { 227, 4, 0, 4, 6, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #227 = SW_RI
556 : { 228, 4, 0, 4, 6, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #228 = SW_RR
557 : { 229, 2, 1, 4, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #229 = TRAILZ
558 : { 230, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #230 = XOR_F_I_HI
559 : { 231, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo33, -1 ,nullptr }, // Inst #231 = XOR_F_I_LO
560 : { 232, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #232 = XOR_F_R
561 : { 233, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #233 = XOR_I_HI
562 : { 234, 3, 1, 4, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #234 = XOR_I_LO
563 : { 235, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #235 = XOR_R
564 : };
565 :
566 : extern const char LanaiInstrNameData[] = {
567 : /* 0 */ 'L', 'O', 'G', '0', 0,
568 : /* 5 */ 'L', 'O', 'G', '1', 0,
569 : /* 10 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
570 : /* 18 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
571 : /* 26 */ 'L', 'O', 'G', '3', 0,
572 : /* 31 */ 'L', 'O', 'G', '4', 0,
573 : /* 36 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 'A', 0,
574 : /* 46 */ 'G', '_', 'F', 'M', 'A', 0,
575 : /* 52 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
576 : /* 59 */ 'G', '_', 'S', 'U', 'B', 0,
577 : /* 65 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
578 : /* 81 */ 'B', 'R', 'C', 'C', 0,
579 : /* 86 */ 'S', 'C', 'C', 0,
580 : /* 90 */ 'B', 'R', 'I', 'N', 'D', '_', 'C', 'C', 0,
581 : /* 99 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
582 : /* 111 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
583 : /* 121 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
584 : /* 139 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
585 : /* 147 */ 'A', 'D', 'J', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0,
586 : /* 159 */ 'P', 'O', 'P', 'C', 0,
587 : /* 164 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
588 : /* 175 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
589 : /* 186 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
590 : /* 193 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
591 : /* 200 */ 'G', '_', 'A', 'D', 'D', 0,
592 : /* 206 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
593 : /* 222 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
594 : /* 239 */ 'G', '_', 'A', 'N', 'D', 0,
595 : /* 245 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
596 : /* 261 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
597 : /* 274 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
598 : /* 283 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
599 : /* 301 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
600 : /* 318 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
601 : /* 326 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
602 : /* 334 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
603 : /* 347 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
604 : /* 355 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
605 : /* 363 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
606 : /* 370 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
607 : /* 383 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
608 : /* 391 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
609 : /* 401 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
610 : /* 416 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
611 : /* 434 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
612 : /* 452 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
613 : /* 467 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
614 : /* 474 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
615 : /* 489 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
616 : /* 503 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
617 : /* 517 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
618 : /* 534 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
619 : /* 551 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
620 : /* 558 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
621 : /* 566 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
622 : /* 574 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
623 : /* 582 */ 'G', '_', 'P', 'H', 'I', 0,
624 : /* 588 */ 'M', 'O', 'V', 'H', 'I', 0,
625 : /* 594 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'H', 'I', 0,
626 : /* 608 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'H', 'I', 0,
627 : /* 618 */ 'S', 'U', 'B', '_', 'I', '_', 'H', 'I', 0,
628 : /* 627 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'H', 'I', 0,
629 : /* 637 */ 'A', 'D', 'D', '_', 'I', '_', 'H', 'I', 0,
630 : /* 646 */ 'A', 'N', 'D', '_', 'I', '_', 'H', 'I', 0,
631 : /* 655 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
632 : /* 667 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
633 : /* 678 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
634 : /* 690 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
635 : /* 701 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
636 : /* 712 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'H', 'I', 0,
637 : /* 723 */ 'X', 'O', 'R', '_', 'I', '_', 'H', 'I', 0,
638 : /* 732 */ 'S', 'L', 'I', 0,
639 : /* 736 */ 'S', 'T', 'B', '_', 'R', 'I', 0,
640 : /* 743 */ 'S', 'T', 'H', '_', 'R', 'I', 0,
641 : /* 750 */ 'L', 'D', 'W', '_', 'R', 'I', 0,
642 : /* 757 */ 'S', 'W', '_', 'R', 'I', 0,
643 : /* 763 */ 'L', 'D', 'B', 's', '_', 'R', 'I', 0,
644 : /* 771 */ 'L', 'D', 'H', 's', '_', 'R', 'I', 0,
645 : /* 779 */ 'L', 'D', 'B', 'z', '_', 'R', 'I', 0,
646 : /* 787 */ 'L', 'D', 'H', 'z', '_', 'R', 'I', 0,
647 : /* 795 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
648 : /* 804 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
649 : /* 813 */ 'S', 'A', '_', 'I', 0,
650 : /* 818 */ 'S', 'A', '_', 'F', '_', 'I', 0,
651 : /* 825 */ 'S', 'L', '_', 'F', '_', 'I', 0,
652 : /* 832 */ 'S', 'L', '_', 'I', 0,
653 : /* 837 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
654 : /* 848 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
655 : /* 857 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
656 : /* 867 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
657 : /* 876 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
658 : /* 893 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
659 : /* 913 */ 'G', '_', 'S', 'H', 'L', 0,
660 : /* 919 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
661 : /* 939 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
662 : /* 966 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
663 : /* 987 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
664 : /* 999 */ 'K', 'I', 'L', 'L', 0,
665 : /* 1004 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
666 : /* 1011 */ 'G', '_', 'M', 'U', 'L', 0,
667 : /* 1017 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
668 : /* 1024 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
669 : /* 1031 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
670 : /* 1038 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
671 : /* 1048 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
672 : /* 1065 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
673 : /* 1081 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
674 : /* 1097 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
675 : /* 1114 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
676 : /* 1122 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
677 : /* 1130 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
678 : /* 1138 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
679 : /* 1146 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
680 : /* 1154 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
681 : /* 1162 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'I', '_', 'L', 'O', 0,
682 : /* 1176 */ 'S', 'U', 'B', 'B', '_', 'I', '_', 'L', 'O', 0,
683 : /* 1186 */ 'S', 'U', 'B', '_', 'I', '_', 'L', 'O', 0,
684 : /* 1195 */ 'A', 'D', 'D', 'C', '_', 'I', '_', 'L', 'O', 0,
685 : /* 1205 */ 'A', 'D', 'D', '_', 'I', '_', 'L', 'O', 0,
686 : /* 1214 */ 'A', 'N', 'D', '_', 'I', '_', 'L', 'O', 0,
687 : /* 1223 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
688 : /* 1235 */ 'S', 'U', 'B', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
689 : /* 1246 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
690 : /* 1258 */ 'A', 'D', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
691 : /* 1269 */ 'A', 'N', 'D', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
692 : /* 1280 */ 'X', 'O', 'R', '_', 'F', '_', 'I', '_', 'L', 'O', 0,
693 : /* 1291 */ 'X', 'O', 'R', '_', 'I', '_', 'L', 'O', 0,
694 : /* 1300 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
695 : /* 1309 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
696 : /* 1317 */ 'G', '_', 'G', 'E', 'P', 0,
697 : /* 1323 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
698 : /* 1332 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
699 : /* 1341 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
700 : /* 1348 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
701 : /* 1355 */ 'N', 'O', 'P', 0,
702 : /* 1359 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
703 : /* 1367 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
704 : /* 1380 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
705 : /* 1392 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
706 : /* 1407 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
707 : /* 1414 */ 'G', '_', 'B', 'R', 0,
708 : /* 1419 */ 'L', 'D', 'A', 'D', 'D', 'R', 0,
709 : /* 1426 */ 'S', 'T', 'A', 'D', 'D', 'R', 0,
710 : /* 1433 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
711 : /* 1446 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
712 : /* 1471 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
713 : /* 1478 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
714 : /* 1485 */ 'J', 'R', 0,
715 : /* 1488 */ 'C', 'A', 'L', 'L', 'R', 0,
716 : /* 1494 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
717 : /* 1511 */ 'G', '_', 'X', 'O', 'R', 0,
718 : /* 1517 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
719 : /* 1533 */ 'G', '_', 'O', 'R', 0,
720 : /* 1538 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
721 : /* 1553 */ 'B', 'R', 'R', 0,
722 : /* 1557 */ 'S', 'T', 'B', '_', 'R', 'R', 0,
723 : /* 1564 */ 'S', 'F', 'S', 'U', 'B', '_', 'F', '_', 'R', 'R', 0,
724 : /* 1575 */ 'S', 'T', 'H', '_', 'R', 'R', 0,
725 : /* 1582 */ 'L', 'D', 'W', '_', 'R', 'R', 0,
726 : /* 1589 */ 'S', 'W', '_', 'R', 'R', 0,
727 : /* 1595 */ 'L', 'D', 'B', 's', '_', 'R', 'R', 0,
728 : /* 1603 */ 'L', 'D', 'H', 's', '_', 'R', 'R', 0,
729 : /* 1611 */ 'L', 'D', 'B', 'z', '_', 'R', 'R', 0,
730 : /* 1619 */ 'L', 'D', 'H', 'z', '_', 'R', 'R', 0,
731 : /* 1627 */ 'L', 'D', 'W', 'z', '_', 'R', 'R', 0,
732 : /* 1635 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
733 : /* 1646 */ 'S', 'R', 'A', '_', 'R', 0,
734 : /* 1652 */ 'S', 'U', 'B', 'B', '_', 'R', 0,
735 : /* 1659 */ 'S', 'U', 'B', '_', 'R', 0,
736 : /* 1665 */ 'A', 'D', 'D', 'C', '_', 'R', 0,
737 : /* 1672 */ 'A', 'D', 'D', '_', 'R', 0,
738 : /* 1678 */ 'A', 'N', 'D', '_', 'R', 0,
739 : /* 1684 */ 'S', 'R', 'A', '_', 'F', '_', 'R', 0,
740 : /* 1692 */ 'S', 'U', 'B', 'B', '_', 'F', '_', 'R', 0,
741 : /* 1701 */ 'S', 'U', 'B', '_', 'F', '_', 'R', 0,
742 : /* 1709 */ 'A', 'D', 'D', 'C', '_', 'F', '_', 'R', 0,
743 : /* 1718 */ 'A', 'D', 'D', '_', 'F', '_', 'R', 0,
744 : /* 1726 */ 'A', 'N', 'D', '_', 'F', '_', 'R', 0,
745 : /* 1734 */ 'S', 'H', 'L', '_', 'F', '_', 'R', 0,
746 : /* 1742 */ 'S', 'R', 'L', '_', 'F', '_', 'R', 0,
747 : /* 1750 */ 'X', 'O', 'R', '_', 'F', '_', 'R', 0,
748 : /* 1758 */ 'S', 'H', 'L', '_', 'R', 0,
749 : /* 1764 */ 'S', 'R', 'L', '_', 'R', 0,
750 : /* 1770 */ 'X', 'O', 'R', '_', 'R', 0,
751 : /* 1776 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
752 : /* 1783 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
753 : /* 1800 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
754 : /* 1815 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
755 : /* 1832 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
756 : /* 1862 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
757 : /* 1889 */ 'B', 'T', 0,
758 : /* 1892 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
759 : /* 1902 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
760 : /* 1911 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
761 : /* 1924 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
762 : /* 1938 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
763 : /* 1962 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
764 : /* 1983 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
765 : /* 2003 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
766 : /* 2015 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
767 : /* 2026 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
768 : /* 2037 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
769 : /* 2048 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
770 : /* 2059 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
771 : /* 2069 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
772 : /* 2084 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
773 : /* 2093 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
774 : /* 2103 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
775 : /* 2120 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
776 : /* 2128 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
777 : /* 2135 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
778 : /* 2144 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
779 : /* 2151 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
780 : /* 2158 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
781 : /* 2165 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
782 : /* 2172 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
783 : /* 2179 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
784 : /* 2196 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
785 : /* 2212 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
786 : /* 2226 */ 'C', 'O', 'P', 'Y', 0,
787 : /* 2231 */ 'L', 'E', 'A', 'D', 'Z', 0,
788 : /* 2237 */ 'T', 'R', 'A', 'I', 'L', 'Z', 0,
789 : /* 2244 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
790 : /* 2251 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
791 : };
792 :
793 : extern const unsigned LanaiInstrNameIndices[] = {
794 : 584U, 1038U, 1081U, 867U, 848U, 876U, 999U, 474U,
795 : 489U, 454U, 503U, 1815U, 391U, 857U, 334U, 2226U,
796 : 363U, 2069U, 261U, 1300U, 987U, 2037U, 301U, 2026U,
797 : 370U, 1380U, 1367U, 1446U, 1924U, 1938U, 919U, 966U,
798 : 939U, 893U, 200U, 59U, 1011U, 2158U, 2165U, 1024U,
799 : 1031U, 239U, 1533U, 1511U, 452U, 582U, 2212U, 401U,
800 : 1892U, 1783U, 2084U, 1800U, 2048U, 1635U, 2093U, 121U,
801 : 283U, 186U, 164U, 175U, 383U, 1832U, 517U, 534U,
802 : 206U, 65U, 245U, 222U, 1538U, 1517U, 2196U, 1065U,
803 : 2179U, 1048U, 274U, 1911U, 99U, 1862U, 2135U, 139U,
804 : 2015U, 2003U, 2059U, 558U, 2128U, 2144U, 913U, 1478U,
805 : 1471U, 1348U, 1341U, 1902U, 1138U, 355U, 1122U, 326U,
806 : 1130U, 347U, 1114U, 318U, 1154U, 1146U, 574U, 566U,
807 : 193U, 52U, 1004U, 46U, 2151U, 1017U, 2172U, 1407U,
808 : 18U, 551U, 10U, 467U, 2120U, 111U, 795U, 804U,
809 : 1323U, 1332U, 1776U, 1317U, 837U, 1414U, 1983U, 1962U,
810 : 1494U, 2251U, 434U, 2244U, 416U, 1359U, 1309U, 2103U,
811 : 1433U, 1097U, 1392U, 147U, 934U, 1488U, 678U, 1246U,
812 : 1709U, 627U, 1195U, 1665U, 690U, 1258U, 1718U, 637U,
813 : 1205U, 1672U, 701U, 1269U, 1726U, 646U, 1214U, 1678U,
814 : 81U, 90U, 36U, 1553U, 1889U, 1485U, 1419U, 763U,
815 : 1595U, 779U, 1611U, 771U, 1603U, 787U, 1619U, 750U,
816 : 1582U, 1627U, 2231U, 0U, 5U, 13U, 26U, 31U,
817 : 588U, 1355U, 713U, 1281U, 1751U, 724U, 1292U, 1771U,
818 : 159U, 1934U, 818U, 813U, 86U, 1904U, 594U, 1162U,
819 : 1564U, 1734U, 1758U, 732U, 825U, 832U, 1684U, 1646U,
820 : 1742U, 1764U, 1426U, 736U, 1557U, 743U, 1575U, 655U,
821 : 1223U, 1692U, 608U, 1176U, 1652U, 667U, 1235U, 1701U,
822 : 618U, 1186U, 1659U, 757U, 1589U, 2237U, 712U, 1280U,
823 : 1750U, 723U, 1291U, 1770U,
824 : };
825 :
826 : static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
827 : II->InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 236);
828 : }
829 :
830 : } // end llvm namespace
831 : #endif // GET_INSTRINFO_MC_DESC
832 :
833 : #ifdef GET_INSTRINFO_HEADER
834 : #undef GET_INSTRINFO_HEADER
835 : namespace llvm {
836 : struct LanaiGenInstrInfo : public TargetInstrInfo {
837 : explicit LanaiGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
838 0 : ~LanaiGenInstrInfo() override = default;
839 :
840 : };
841 : } // end llvm namespace
842 : #endif // GET_INSTRINFO_HEADER
843 :
844 : #ifdef GET_INSTRINFO_CTOR_DTOR
845 : #undef GET_INSTRINFO_CTOR_DTOR
846 : namespace llvm {
847 : extern const MCInstrDesc LanaiInsts[];
848 : extern const unsigned LanaiInstrNameIndices[];
849 : extern const char LanaiInstrNameData[];
850 26 : LanaiGenInstrInfo::LanaiGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
851 52 : : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
852 : InitMCInstrInfo(LanaiInsts, LanaiInstrNameIndices, LanaiInstrNameData, 236);
853 26 : }
854 : } // end llvm namespace
855 : #endif // GET_INSTRINFO_CTOR_DTOR
856 :
857 : #ifdef GET_INSTRINFO_OPERAND_ENUM
858 : #undef GET_INSTRINFO_OPERAND_ENUM
859 : namespace llvm {
860 : namespace Lanai {
861 : namespace OpName {
862 : enum {
863 : OPERAND_LAST
864 : };
865 : } // end namespace OpName
866 : } // end namespace Lanai
867 : } // end namespace llvm
868 : #endif //GET_INSTRINFO_OPERAND_ENUM
869 :
870 : #ifdef GET_INSTRINFO_NAMED_OPS
871 : #undef GET_INSTRINFO_NAMED_OPS
872 : namespace llvm {
873 : namespace Lanai {
874 : LLVM_READONLY
875 : int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
876 : return -1;
877 : }
878 : } // end namespace Lanai
879 : } // end namespace llvm
880 : #endif //GET_INSTRINFO_NAMED_OPS
881 :
882 : #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
883 : #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
884 : namespace llvm {
885 : namespace Lanai {
886 : namespace OpTypes {
887 : enum OperandType {
888 : AluOp = 0,
889 : BrTarget = 1,
890 : CCOp = 2,
891 : CallTarget = 3,
892 : MEMi = 4,
893 : MEMri = 5,
894 : MEMrr = 6,
895 : MEMspls = 7,
896 : f32imm = 8,
897 : f64imm = 9,
898 : i16imm = 10,
899 : i1imm = 11,
900 : i32hi16 = 12,
901 : i32hi16and = 13,
902 : i32imm = 14,
903 : i32lo16and = 15,
904 : i32lo16s = 16,
905 : i32lo16z = 17,
906 : i32lo21 = 18,
907 : i32neg16 = 19,
908 : i64imm = 20,
909 : i8imm = 21,
910 : imm10 = 22,
911 : immShift = 23,
912 : pred = 24,
913 : ptype0 = 25,
914 : ptype1 = 26,
915 : ptype2 = 27,
916 : ptype3 = 28,
917 : ptype4 = 29,
918 : ptype5 = 30,
919 : type0 = 31,
920 : type1 = 32,
921 : type2 = 33,
922 : type3 = 34,
923 : type4 = 35,
924 : type5 = 36,
925 : OPERAND_TYPE_LIST_END
926 : };
927 : } // end namespace OpTypes
928 : } // end namespace Lanai
929 : } // end namespace llvm
930 : #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
931 :
932 : #ifdef GET_INSTRMAP_INFO
933 : #undef GET_INSTRMAP_INFO
934 : namespace llvm {
935 :
936 : namespace Lanai {
937 :
938 : enum PostEncoderMethod {
939 : PostEncoderMethod_adjustPqBitsSpls
940 : };
941 :
942 : // splsIdempotent
943 : LLVM_READONLY
944 128 : int splsIdempotent(uint16_t Opcode) {
945 : static const uint16_t splsIdempotentTable[][2] = {
946 : { Lanai::LDBs_RI, Lanai::LDBs_RI },
947 : { Lanai::LDBz_RI, Lanai::LDBz_RI },
948 : { Lanai::LDHs_RI, Lanai::LDHs_RI },
949 : { Lanai::LDHz_RI, Lanai::LDHz_RI },
950 : { Lanai::STB_RI, Lanai::STB_RI },
951 : { Lanai::STH_RI, Lanai::STH_RI },
952 : }; // End of splsIdempotentTable
953 :
954 : unsigned mid;
955 : unsigned start = 0;
956 : unsigned end = 6;
957 488 : while (start < end) {
958 368 : mid = start + (end - start)/2;
959 368 : if (Opcode == splsIdempotentTable[mid][0]) {
960 : break;
961 : }
962 360 : if (Opcode < splsIdempotentTable[mid][0])
963 : end = mid;
964 : else
965 128 : start = mid + 1;
966 : }
967 128 : if (start == end)
968 : return -1; // Instruction doesn't exist in this table.
969 :
970 8 : return splsIdempotentTable[mid][1];
971 : }
972 :
973 : } // End Lanai namespace
974 : } // End llvm namespace
975 : #endif // GET_INSTRMAP_INFO
976 :
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