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1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Subtarget Enumeration Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_SUBTARGETINFO_ENUM
11 : #undef GET_SUBTARGETINFO_ENUM
12 :
13 : namespace llvm {
14 : } // end namespace llvm
15 :
16 : #endif // GET_SUBTARGETINFO_ENUM
17 :
18 :
19 : #ifdef GET_SUBTARGETINFO_MC_DESC
20 : #undef GET_SUBTARGETINFO_MC_DESC
21 :
22 : namespace llvm {
23 :
24 : // Sorted (by key) array of values for CPU subtype.
25 : extern const llvm::SubtargetFeatureKV LanaiSubTypeKV[] = {
26 : { "generic", "Select the generic processor", { }, { } },
27 : { "v11", "Select the v11 processor", { }, { } },
28 : };
29 :
30 : #ifdef DBGFIELD
31 : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
32 : #endif
33 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
34 : #define DBGFIELD(x) x,
35 : #else
36 : #define DBGFIELD(x)
37 : #endif
38 :
39 : // Functional units for "LanaiItinerary"
40 : namespace LanaiItineraryFU {
41 : const unsigned ALU_FU = 1 << 0;
42 : const unsigned LDST_FU = 1 << 1;
43 : } // end namespace LanaiItineraryFU
44 :
45 : extern const llvm::InstrStage LanaiStages[] = {
46 : { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
47 : { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
48 : { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
49 : { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
50 : { 0, 0, 0, llvm::InstrStage::Required } // End stages
51 : };
52 : extern const unsigned LanaiOperandCycles[] = {
53 : 0, // No itinerary
54 : 0 // End operand cycles
55 : };
56 : extern const unsigned LanaiForwardingPaths[] = {
57 : 0, // No itinerary
58 : 0 // End bypass tables
59 : };
60 :
61 : static const llvm::InstrItinerary LanaiItinerary[] = {
62 : { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
63 : { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
64 : { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
65 : { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
66 : { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
67 : { 0, 0, 0, 0, 0 }, // 5 WriteLD
68 : { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
69 : { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
70 : { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
71 : };
72 :
73 : // ===============================================================
74 : // Data tables for the new per-operand machine model.
75 :
76 : // {ProcResourceIdx, Cycles}
77 : extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
78 : { 0, 0}, // Invalid
79 : { 1, 1}, // #1
80 : { 2, 1} // #2
81 : }; // LanaiWriteProcResTable
82 :
83 : // {Cycles, WriteResourceID}
84 : extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
85 : { 0, 0}, // Invalid
86 : { 1, 0}, // #1 WriteALU
87 : { 2, 0}, // #2 WriteLD_WriteLDSW_WriteST
88 : { 4, 0} // #3 WriteSTSW
89 : }; // LanaiWriteLatencyTable
90 :
91 : // {UseIdx, WriteResourceID, Cycles}
92 : extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
93 : {0, 0, 0}, // Invalid
94 : }; // LanaiReadAdvanceTable
95 :
96 : // {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
97 : static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
98 : {DBGFIELD("InvalidSchedClass") 16383, false, false, 0, 0, 0, 0, 0, 0},
99 : {DBGFIELD("IIC_ALU_WriteALU") 1, false, false, 1, 1, 1, 1, 0, 0}, // #1
100 : {DBGFIELD("IIC_ALU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #2
101 : {DBGFIELD("IIC_LD_WriteLD") 1, false, false, 2, 1, 2, 1, 0, 0}, // #3
102 : {DBGFIELD("IIC_LDSW_WriteLDSW") 1, false, false, 2, 1, 2, 1, 0, 0}, // #4
103 : {DBGFIELD("WriteLD") 1, false, false, 2, 1, 2, 1, 0, 0}, // #5
104 : {DBGFIELD("IIC_ST_WriteST") 1, false, false, 2, 1, 2, 1, 0, 0}, // #6
105 : {DBGFIELD("IIC_STSW_WriteSTSW") 1, false, false, 2, 1, 3, 1, 0, 0}, // #7
106 : }; // LanaiSchedModelSchedClasses
107 :
108 : static const llvm::MCSchedModel NoSchedModel = {
109 : MCSchedModel::DefaultIssueWidth,
110 : MCSchedModel::DefaultMicroOpBufferSize,
111 : MCSchedModel::DefaultLoopMicroOpBufferSize,
112 : MCSchedModel::DefaultLoadLatency,
113 : MCSchedModel::DefaultHighLatency,
114 : MCSchedModel::DefaultMispredictPenalty,
115 : false, // PostRAScheduler
116 : false, // CompleteModel
117 : 0, // Processor ID
118 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
119 : nullptr, // No Itinerary
120 : nullptr // No extra processor descriptor
121 : };
122 :
123 : static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
124 : 0, // Invalid
125 : };
126 :
127 : // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
128 : static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
129 : {"InvalidUnit", 0, 0, 0, 0},
130 : {"ALU", 1, 0, 0, nullptr}, // #1
131 : {"LdSt", 1, 0, 0, nullptr}, // #2
132 : };
133 :
134 : static const llvm::MCSchedModel LanaiSchedModel = {
135 : 1, // IssueWidth
136 : 0, // MicroOpBufferSize
137 : 0, // LoopMicroOpBufferSize
138 : 2, // LoadLatency
139 : MCSchedModel::DefaultHighLatency,
140 : 10, // MispredictPenalty
141 : false, // PostRAScheduler
142 : false, // CompleteModel
143 : 1, // Processor ID
144 : LanaiSchedModelProcResources,
145 : LanaiSchedModelSchedClasses,
146 : 3,
147 : 8,
148 : LanaiItinerary,
149 : nullptr // No extra processor descriptor
150 : };
151 :
152 : // Sorted (by key) array of itineraries for CPU subtype.
153 : extern const llvm::SubtargetInfoKV LanaiProcSchedKV[] = {
154 : { "generic", (const void *)&LanaiSchedModel },
155 : { "v11", (const void *)&LanaiSchedModel },
156 : };
157 :
158 : #undef DBGFIELD
159 : namespace Lanai_MC {
160 0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
161 : const MCInst *MI, unsigned CPUID) {
162 : // Don't know how to resolve this scheduling class.
163 0 : return 0;
164 : }
165 : } // end of namespace Lanai_MC
166 :
167 : struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
168 : LanaiGenMCSubtargetInfo(const Triple &TT,
169 : StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
170 : ArrayRef<SubtargetFeatureKV> PD,
171 : const SubtargetInfoKV *ProcSched,
172 : const MCWriteProcResEntry *WPR,
173 : const MCWriteLatencyEntry *WL,
174 : const MCReadAdvanceEntry *RA, const InstrStage *IS,
175 31 : const unsigned *OC, const unsigned *FP) :
176 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
177 31 : WPR, WL, RA, IS, OC, FP) { }
178 :
179 0 : unsigned resolveVariantSchedClass(unsigned SchedClass,
180 : const MCInst *MI, unsigned CPUID) const override {
181 0 : return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
182 : }
183 : };
184 :
185 31 : static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
186 : return new LanaiGenMCSubtargetInfo(TT, CPU, FS, None, LanaiSubTypeKV,
187 : LanaiProcSchedKV, LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
188 31 : LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
189 : }
190 :
191 : } // end namespace llvm
192 :
193 : #endif // GET_SUBTARGETINFO_MC_DESC
194 :
195 :
196 : #ifdef GET_SUBTARGETINFO_TARGET_DESC
197 : #undef GET_SUBTARGETINFO_TARGET_DESC
198 :
199 : #include "llvm/Support/Debug.h"
200 : #include "llvm/Support/raw_ostream.h"
201 :
202 : // ParseSubtargetFeatures - Parses features string setting specified
203 : // subtarget options.
204 26 : void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
205 : LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
206 : LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
207 26 : }
208 : #endif // GET_SUBTARGETINFO_TARGET_DESC
209 :
210 :
211 : #ifdef GET_SUBTARGETINFO_HEADER
212 : #undef GET_SUBTARGETINFO_HEADER
213 :
214 : namespace llvm {
215 : class DFAPacketizer;
216 : namespace Lanai_MC {
217 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
218 : }
219 :
220 : struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
221 : explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
222 : public:
223 : unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
224 : unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
225 : DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
226 : };
227 : } // end namespace llvm
228 :
229 : #endif // GET_SUBTARGETINFO_HEADER
230 :
231 :
232 : #ifdef GET_SUBTARGETINFO_CTOR
233 : #undef GET_SUBTARGETINFO_CTOR
234 :
235 : #include "llvm/CodeGen/TargetSchedule.h"
236 :
237 : namespace llvm {
238 : extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
239 : extern const llvm::SubtargetFeatureKV LanaiSubTypeKV[];
240 : extern const llvm::SubtargetInfoKV LanaiProcSchedKV[];
241 : extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
242 : extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
243 : extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
244 : extern const llvm::InstrStage LanaiStages[];
245 : extern const unsigned LanaiOperandCycles[];
246 : extern const unsigned LanaiForwardingPaths[];
247 26 : LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
248 : : TargetSubtargetInfo(TT, CPU, FS, None, makeArrayRef(LanaiSubTypeKV, 2),
249 : LanaiProcSchedKV, LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
250 52 : LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
251 :
252 0 : unsigned LanaiGenSubtargetInfo
253 : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
254 0 : report_fatal_error("Expected a variant SchedClass");
255 : } // LanaiGenSubtargetInfo::resolveSchedClass
256 :
257 0 : unsigned LanaiGenSubtargetInfo
258 : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
259 0 : return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
260 : } // LanaiGenSubtargetInfo::resolveVariantSchedClass
261 :
262 : } // end namespace llvm
263 :
264 : #endif // GET_SUBTARGETINFO_CTOR
265 :
266 :
267 : #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
268 : #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
269 :
270 : #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
271 :
272 :
273 : #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
274 : #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
275 :
276 : #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
277 :
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