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1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Subtarget Enumeration Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_SUBTARGETINFO_ENUM
11 : #undef GET_SUBTARGETINFO_ENUM
12 :
13 : namespace llvm {
14 : namespace MSP430 {
15 : enum {
16 : FeatureHWMult16 = 0,
17 : FeatureHWMult32 = 1,
18 : FeatureHWMultF5 = 2,
19 : FeatureX = 3,
20 : };
21 : } // end namespace MSP430
22 : } // end namespace llvm
23 :
24 : #endif // GET_SUBTARGETINFO_ENUM
25 :
26 :
27 : #ifdef GET_SUBTARGETINFO_MC_DESC
28 : #undef GET_SUBTARGETINFO_MC_DESC
29 :
30 : namespace llvm {
31 : // Sorted (by key) array of values for CPU features.
32 : extern const llvm::SubtargetFeatureKV MSP430FeatureKV[] = {
33 : { "ext", "Enable MSP430-X extensions", { MSP430::FeatureX }, { } },
34 : { "hwmult16", "Enable 16-bit hardware multiplier", { MSP430::FeatureHWMult16 }, { } },
35 : { "hwmult32", "Enable 32-bit hardware multiplier", { MSP430::FeatureHWMult32 }, { } },
36 : { "hwmultf5", "Enable F5 series hardware multiplier", { MSP430::FeatureHWMultF5 }, { } },
37 : };
38 :
39 : // Sorted (by key) array of values for CPU subtype.
40 : extern const llvm::SubtargetFeatureKV MSP430SubTypeKV[] = {
41 : { "generic", "Select the generic processor", { }, { } },
42 : { "msp430", "Select the msp430 processor", { }, { } },
43 : { "msp430x", "Select the msp430x processor", { MSP430::FeatureX }, { } },
44 : };
45 :
46 : #ifdef DBGFIELD
47 : #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
48 : #endif
49 : #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
50 : #define DBGFIELD(x) x,
51 : #else
52 : #define DBGFIELD(x)
53 : #endif
54 :
55 : // ===============================================================
56 : // Data tables for the new per-operand machine model.
57 :
58 : // {ProcResourceIdx, Cycles}
59 : extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[] = {
60 : { 0, 0}, // Invalid
61 : }; // MSP430WriteProcResTable
62 :
63 : // {Cycles, WriteResourceID}
64 : extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[] = {
65 : { 0, 0}, // Invalid
66 : }; // MSP430WriteLatencyTable
67 :
68 : // {UseIdx, WriteResourceID, Cycles}
69 : extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = {
70 : {0, 0, 0}, // Invalid
71 : }; // MSP430ReadAdvanceTable
72 :
73 : static const llvm::MCSchedModel NoSchedModel = {
74 : MCSchedModel::DefaultIssueWidth,
75 : MCSchedModel::DefaultMicroOpBufferSize,
76 : MCSchedModel::DefaultLoopMicroOpBufferSize,
77 : MCSchedModel::DefaultLoadLatency,
78 : MCSchedModel::DefaultHighLatency,
79 : MCSchedModel::DefaultMispredictPenalty,
80 : false, // PostRAScheduler
81 : false, // CompleteModel
82 : 0, // Processor ID
83 : nullptr, nullptr, 0, 0, // No instruction-level machine model.
84 : nullptr, // No Itinerary
85 : nullptr // No extra processor descriptor
86 : };
87 :
88 : // Sorted (by key) array of itineraries for CPU subtype.
89 : extern const llvm::SubtargetInfoKV MSP430ProcSchedKV[] = {
90 : { "generic", (const void *)&NoSchedModel },
91 : { "msp430", (const void *)&NoSchedModel },
92 : { "msp430x", (const void *)&NoSchedModel },
93 : };
94 :
95 : #undef DBGFIELD
96 : namespace MSP430_MC {
97 0 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
98 : const MCInst *MI, unsigned CPUID) {
99 : // Don't know how to resolve this scheduling class.
100 0 : return 0;
101 : }
102 : } // end of namespace MSP430_MC
103 :
104 : struct MSP430GenMCSubtargetInfo : public MCSubtargetInfo {
105 : MSP430GenMCSubtargetInfo(const Triple &TT,
106 : StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
107 : ArrayRef<SubtargetFeatureKV> PD,
108 : const SubtargetInfoKV *ProcSched,
109 : const MCWriteProcResEntry *WPR,
110 : const MCWriteLatencyEntry *WL,
111 : const MCReadAdvanceEntry *RA, const InstrStage *IS,
112 64 : const unsigned *OC, const unsigned *FP) :
113 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
114 64 : WPR, WL, RA, IS, OC, FP) { }
115 :
116 0 : unsigned resolveVariantSchedClass(unsigned SchedClass,
117 : const MCInst *MI, unsigned CPUID) const override {
118 0 : return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
119 : }
120 : };
121 :
122 64 : static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
123 : return new MSP430GenMCSubtargetInfo(TT, CPU, FS, MSP430FeatureKV, MSP430SubTypeKV,
124 : MSP430ProcSchedKV, MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
125 64 : nullptr, nullptr, nullptr);
126 : }
127 :
128 : } // end namespace llvm
129 :
130 : #endif // GET_SUBTARGETINFO_MC_DESC
131 :
132 :
133 : #ifdef GET_SUBTARGETINFO_TARGET_DESC
134 : #undef GET_SUBTARGETINFO_TARGET_DESC
135 :
136 : #include "llvm/Support/Debug.h"
137 : #include "llvm/Support/raw_ostream.h"
138 :
139 : // ParseSubtargetFeatures - Parses features string setting specified
140 : // subtarget options.
141 64 : void llvm::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
142 : LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
143 : LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
144 64 : InitMCProcessorInfo(CPU, FS);
145 : const FeatureBitset& Bits = getFeatureBits();
146 64 : if (Bits[MSP430::FeatureHWMult16] && HWMultMode < HWMult16) HWMultMode = HWMult16;
147 64 : if (Bits[MSP430::FeatureHWMult32] && HWMultMode < HWMult32) HWMultMode = HWMult32;
148 64 : if (Bits[MSP430::FeatureHWMultF5] && HWMultMode < HWMultF5) HWMultMode = HWMultF5;
149 64 : if (Bits[MSP430::FeatureX]) ExtendedInsts = true;
150 64 : }
151 : #endif // GET_SUBTARGETINFO_TARGET_DESC
152 :
153 :
154 : #ifdef GET_SUBTARGETINFO_HEADER
155 : #undef GET_SUBTARGETINFO_HEADER
156 :
157 : namespace llvm {
158 : class DFAPacketizer;
159 : namespace MSP430_MC {
160 : unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
161 : }
162 :
163 : struct MSP430GenSubtargetInfo : public TargetSubtargetInfo {
164 : explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
165 : public:
166 : unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
167 : unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
168 : DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
169 : };
170 : } // end namespace llvm
171 :
172 : #endif // GET_SUBTARGETINFO_HEADER
173 :
174 :
175 : #ifdef GET_SUBTARGETINFO_CTOR
176 : #undef GET_SUBTARGETINFO_CTOR
177 :
178 : #include "llvm/CodeGen/TargetSchedule.h"
179 :
180 : namespace llvm {
181 : extern const llvm::SubtargetFeatureKV MSP430FeatureKV[];
182 : extern const llvm::SubtargetFeatureKV MSP430SubTypeKV[];
183 : extern const llvm::SubtargetInfoKV MSP430ProcSchedKV[];
184 : extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[];
185 : extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[];
186 : extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[];
187 64 : MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
188 : : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(MSP430FeatureKV, 4), makeArrayRef(MSP430SubTypeKV, 3),
189 : MSP430ProcSchedKV, MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
190 64 : nullptr, nullptr, nullptr) {}
191 :
192 0 : unsigned MSP430GenSubtargetInfo
193 : ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
194 0 : report_fatal_error("Expected a variant SchedClass");
195 : } // MSP430GenSubtargetInfo::resolveSchedClass
196 :
197 0 : unsigned MSP430GenSubtargetInfo
198 : ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
199 0 : return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
200 : } // MSP430GenSubtargetInfo::resolveVariantSchedClass
201 :
202 : } // end namespace llvm
203 :
204 : #endif // GET_SUBTARGETINFO_CTOR
205 :
206 :
207 : #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
208 : #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
209 :
210 : #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
211 :
212 :
213 : #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
214 : #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
215 :
216 : #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
217 :
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