Line data Source code
1 : /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 : |* *|
3 : |* Assembly Matcher Source Fragment *|
4 : |* *|
5 : |* Automatically generated file, do not edit! *|
6 : |* *|
7 : \*===----------------------------------------------------------------------===*/
8 :
9 :
10 : #ifdef GET_ASSEMBLER_HEADER
11 : #undef GET_ASSEMBLER_HEADER
12 : // This should be included into the middle of the declaration of
13 : // your subclasses implementation of MCTargetAsmParser.
14 : uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15 : void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16 : const OperandVector &Operands);
17 : void convertToMapAndConstraints(unsigned Kind,
18 : const OperandVector &Operands) override;
19 : unsigned MatchInstructionImpl(const OperandVector &Operands,
20 : MCInst &Inst,
21 : uint64_t &ErrorInfo,
22 : bool matchingInlineAsm,
23 : unsigned VariantID = 0);
24 : OperandMatchResultTy MatchOperandParserImpl(
25 : OperandVector &Operands,
26 : StringRef Mnemonic,
27 : bool ParseForAllFeatures = false);
28 : OperandMatchResultTy tryCustomParseOperand(
29 : OperandVector &Operands,
30 : unsigned MCK);
31 :
32 : #endif // GET_ASSEMBLER_HEADER_INFO
33 :
34 :
35 : #ifdef GET_OPERAND_DIAGNOSTIC_TYPES
36 : #undef GET_OPERAND_DIAGNOSTIC_TYPES
37 :
38 : Match_Immz,
39 : Match_MemSImm10,
40 : Match_MemSImm10Lsl1,
41 : Match_MemSImm10Lsl2,
42 : Match_MemSImm10Lsl3,
43 : Match_MemSImm11,
44 : Match_MemSImm12,
45 : Match_MemSImm16,
46 : Match_MemSImm9,
47 : Match_MemSImmPtr,
48 : Match_SImm10_0,
49 : Match_SImm10_Lsl1,
50 : Match_SImm10_Lsl2,
51 : Match_SImm10_Lsl3,
52 : Match_SImm11_0,
53 : Match_SImm16,
54 : Match_SImm16_Relaxed,
55 : Match_SImm19_Lsl2,
56 : Match_SImm32,
57 : Match_SImm32_Relaxed,
58 : Match_SImm4_0,
59 : Match_SImm5_0,
60 : Match_SImm6_0,
61 : Match_SImm7_Lsl2,
62 : Match_SImm9_0,
63 : Match_UImm10_0,
64 : Match_UImm16,
65 : Match_UImm16_AltRelaxed,
66 : Match_UImm16_Relaxed,
67 : Match_UImm1_0,
68 : Match_UImm20_0,
69 : Match_UImm26_0,
70 : Match_UImm2_0,
71 : Match_UImm2_1,
72 : Match_UImm32_Coerced,
73 : Match_UImm3_0,
74 : Match_UImm4_0,
75 : Match_UImm5_0,
76 : Match_UImm5_0_Report_UImm6,
77 : Match_UImm5_1,
78 : Match_UImm5_32,
79 : Match_UImm5_33,
80 : Match_UImm5_Lsl2,
81 : Match_UImm6_0,
82 : Match_UImm6_Lsl2,
83 : Match_UImm7_0,
84 : Match_UImm7_N1,
85 : Match_UImm8_0,
86 : Match_UImmRange2_64,
87 : END_OPERAND_DIAGNOSTIC_TYPES
88 : #endif // GET_OPERAND_DIAGNOSTIC_TYPES
89 :
90 :
91 : #ifdef GET_REGISTER_MATCHER
92 : #undef GET_REGISTER_MATCHER
93 :
94 : // Flags for subtarget features that participate in instruction matching.
95 : enum SubtargetFeatureFlag : uint64_t {
96 : Feature_HasMips2 = (1ULL << 10),
97 : Feature_HasMips3_32 = (1ULL << 16),
98 : Feature_HasMips3_32r2 = (1ULL << 17),
99 : Feature_HasMips3 = (1ULL << 11),
100 : Feature_NotMips3 = (1ULL << 44),
101 : Feature_HasMips4_32 = (1ULL << 18),
102 : Feature_NotMips4_32 = (1ULL << 46),
103 : Feature_HasMips4_32r2 = (1ULL << 19),
104 : Feature_HasMips5_32r2 = (1ULL << 20),
105 : Feature_HasMips32 = (1ULL << 12),
106 : Feature_HasMips32r2 = (1ULL << 13),
107 : Feature_HasMips32r5 = (1ULL << 14),
108 : Feature_HasMips32r6 = (1ULL << 15),
109 : Feature_NotMips32r6 = (1ULL << 45),
110 : Feature_IsGP64bit = (1ULL << 31),
111 : Feature_IsGP32bit = (1ULL << 30),
112 : Feature_IsPTR64bit = (1ULL << 35),
113 : Feature_IsPTR32bit = (1ULL << 34),
114 : Feature_HasMips64 = (1ULL << 21),
115 : Feature_NotMips64 = (1ULL << 47),
116 : Feature_HasMips64r2 = (1ULL << 22),
117 : Feature_HasMips64r5 = (1ULL << 23),
118 : Feature_HasMips64r6 = (1ULL << 24),
119 : Feature_NotMips64r6 = (1ULL << 48),
120 : Feature_InMips16Mode = (1ULL << 28),
121 : Feature_NotInMips16Mode = (1ULL << 43),
122 : Feature_HasCnMips = (1ULL << 1),
123 : Feature_NotCnMips = (1ULL << 40),
124 : Feature_IsSym32 = (1ULL << 37),
125 : Feature_IsSym64 = (1ULL << 38),
126 : Feature_HasStdEnc = (1ULL << 25),
127 : Feature_InMicroMips = (1ULL << 27),
128 : Feature_NotInMicroMips = (1ULL << 42),
129 : Feature_HasEVA = (1ULL << 5),
130 : Feature_HasMSA = (1ULL << 7),
131 : Feature_HasMadd4 = (1ULL << 9),
132 : Feature_HasMT = (1ULL << 8),
133 : Feature_UseIndirectJumpsHazard = (1ULL << 49),
134 : Feature_NoIndirectJumpGuards = (1ULL << 39),
135 : Feature_HasCRC = (1ULL << 0),
136 : Feature_HasVirt = (1ULL << 26),
137 : Feature_HasGINV = (1ULL << 6),
138 : Feature_IsFP64bit = (1ULL << 29),
139 : Feature_NotFP64bit = (1ULL << 41),
140 : Feature_IsSingleFloat = (1ULL << 36),
141 : Feature_IsNotSingleFloat = (1ULL << 32),
142 : Feature_IsNotSoftFloat = (1ULL << 33),
143 : Feature_HasDSP = (1ULL << 2),
144 : Feature_HasDSPR2 = (1ULL << 3),
145 : Feature_HasDSPR3 = (1ULL << 4),
146 : Feature_None = 0
147 : };
148 :
149 : #endif // GET_REGISTER_MATCHER
150 :
151 :
152 : #ifdef GET_SUBTARGET_FEATURE_NAME
153 : #undef GET_SUBTARGET_FEATURE_NAME
154 :
155 : // User-level names for subtarget features that participate in
156 : // instruction matching.
157 : static const char *getSubtargetFeatureName(uint64_t Val) {
158 : switch(Val) {
159 : case Feature_HasMips2: return "";
160 : case Feature_HasMips3_32: return "";
161 : case Feature_HasMips3_32r2: return "";
162 : case Feature_HasMips3: return "";
163 : case Feature_NotMips3: return "";
164 : case Feature_HasMips4_32: return "";
165 : case Feature_NotMips4_32: return "";
166 : case Feature_HasMips4_32r2: return "";
167 : case Feature_HasMips5_32r2: return "";
168 : case Feature_HasMips32: return "";
169 : case Feature_HasMips32r2: return "";
170 : case Feature_HasMips32r5: return "";
171 : case Feature_HasMips32r6: return "";
172 : case Feature_NotMips32r6: return "";
173 : case Feature_IsGP64bit: return "";
174 : case Feature_IsGP32bit: return "";
175 : case Feature_IsPTR64bit: return "";
176 : case Feature_IsPTR32bit: return "";
177 : case Feature_HasMips64: return "";
178 : case Feature_NotMips64: return "";
179 : case Feature_HasMips64r2: return "";
180 : case Feature_HasMips64r5: return "";
181 : case Feature_HasMips64r6: return "";
182 : case Feature_NotMips64r6: return "";
183 : case Feature_InMips16Mode: return "";
184 : case Feature_NotInMips16Mode: return "";
185 : case Feature_HasCnMips: return "";
186 : case Feature_NotCnMips: return "";
187 : case Feature_IsSym32: return "";
188 : case Feature_IsSym64: return "";
189 : case Feature_HasStdEnc: return "";
190 : case Feature_InMicroMips: return "";
191 : case Feature_NotInMicroMips: return "";
192 : case Feature_HasEVA: return "";
193 : case Feature_HasMSA: return "";
194 : case Feature_HasMadd4: return "";
195 : case Feature_HasMT: return "";
196 : case Feature_UseIndirectJumpsHazard: return "";
197 : case Feature_NoIndirectJumpGuards: return "";
198 : case Feature_HasCRC: return "";
199 : case Feature_HasVirt: return "";
200 : case Feature_HasGINV: return "";
201 : case Feature_IsFP64bit: return "";
202 : case Feature_NotFP64bit: return "";
203 : case Feature_IsSingleFloat: return "";
204 : case Feature_IsNotSingleFloat: return "";
205 : case Feature_IsNotSoftFloat: return "";
206 : case Feature_HasDSP: return "";
207 : case Feature_HasDSPR2: return "";
208 : case Feature_HasDSPR3: return "";
209 : default: return "(unknown)";
210 : }
211 : }
212 :
213 : #endif // GET_SUBTARGET_FEATURE_NAME
214 :
215 :
216 : #ifdef GET_MATCHER_IMPLEMENTATION
217 : #undef GET_MATCHER_IMPLEMENTATION
218 :
219 : enum {
220 : Tie0_1_1,
221 : Tie0_1_2,
222 : };
223 :
224 : static const uint8_t TiedAsmOperandTable[][3] = {
225 : /* Tie0_1_1 */ { 0, 1, 1 },
226 : /* Tie0_1_2 */ { 0, 1, 2 },
227 : };
228 :
229 : namespace {
230 : enum OperatorConversionKind {
231 : CVT_Done,
232 : CVT_Reg,
233 : CVT_Tied,
234 : CVT_95_addGPR32AsmRegOperands,
235 : CVT_95_addAFGR64AsmRegOperands,
236 : CVT_95_addFGR64AsmRegOperands,
237 : CVT_95_addFGR32AsmRegOperands,
238 : CVT_95_addSImmOperands_LT_32_GT_,
239 : CVT_95_addMSA128AsmRegOperands,
240 : CVT_95_addSImmOperands_LT_16_GT_,
241 : CVT_95_Reg,
242 : CVT_95_addImmOperands,
243 : CVT_95_addGPRMM16AsmRegOperands,
244 : CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
245 : CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
246 : CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
247 : CVT_95_addUImmOperands_LT_16_GT_,
248 : CVT_95_addGPR64AsmRegOperands,
249 : CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
250 : CVT_regZERO,
251 : CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
252 : CVT_regFCC0,
253 : CVT_95_addFCCAsmRegOperands,
254 : CVT_95_addCOP2AsmRegOperands,
255 : CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
256 : CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
257 : CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
258 : CVT_imm_95_0,
259 : CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
260 : CVT_95_addMemOperands,
261 : CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
262 : CVT_95_addCCRAsmRegOperands,
263 : CVT_95_addMSACtrlAsmRegOperands,
264 : CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
265 : CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
266 : CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
267 : CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
268 : CVT_95_addGPR32NonZeroAsmRegOperands,
269 : CVT_95_addGPR32ZeroAsmRegOperands,
270 : CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
271 : CVT_95_addCOP0AsmRegOperands,
272 : CVT_regZERO_64,
273 : CVT_95_addACC64DSPAsmRegOperands,
274 : CVT_95_addConstantUImmOperands_LT_1_GT_,
275 : CVT_regRA,
276 : CVT_regRA_64,
277 : CVT_95_addMicroMipsMemOperands,
278 : CVT_95_addCOP3AsmRegOperands,
279 : CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
280 : CVT_95_addConstantUImmOperands_LT_32_GT_,
281 : CVT_95_addStrictlyAFGR64AsmRegOperands,
282 : CVT_95_addStrictlyFGR64AsmRegOperands,
283 : CVT_95_addStrictlyFGR32AsmRegOperands,
284 : CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
285 : CVT_95_addRegListOperands,
286 : CVT_ConvertXWPOperands,
287 : CVT_regAC0,
288 : CVT_95_addGPRMM16AsmRegMovePPairFirstOperands,
289 : CVT_95_addGPRMM16AsmRegMovePPairSecondOperands,
290 : CVT_95_addGPRMM16AsmRegMovePOperands,
291 : CVT_95_addHI32DSPAsmRegOperands,
292 : CVT_95_addLO32DSPAsmRegOperands,
293 : CVT_regS0,
294 : CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
295 : CVT_95_addHWRegsAsmRegOperands,
296 : CVT_95_addGPRMM16AsmRegZeroOperands,
297 : CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
298 : CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
299 : CVT_imm_95_2,
300 : CVT_imm_95_6,
301 : CVT_imm_95_4,
302 : CVT_imm_95_5,
303 : CVT_imm_95_31,
304 : CVT_NUM_CONVERTERS
305 : };
306 :
307 : enum InstructionConversionKind {
308 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
309 : Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
310 : Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
311 : Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
312 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
313 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
314 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
315 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
316 : Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
317 : Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
318 : Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
319 : Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
320 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
321 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
322 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
323 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
324 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
325 : Convert__SImm161_1,
326 : Convert__Reg1_0__SImm161_1,
327 : Convert__Reg1_0__SImm161_2,
328 : Convert__Reg1_0__Reg1_1__SImm161_2,
329 : Convert__Reg1_0__Tie0_1_1__SImm161_1,
330 : Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
331 : Convert__GPRMM16AsmReg1_0__Imm1_1,
332 : Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
333 : Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
334 : Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
335 : Convert__Imm1_0,
336 : Convert__Reg1_0__Reg1_1__Reg1_2,
337 : Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
338 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
339 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
340 : Convert__GPR32AsmReg1_0__SImm161_1,
341 : Convert__Reg1_0__Tie0_1_1__Reg1_1,
342 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
343 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
344 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
345 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
346 : Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
347 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
348 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
349 : Convert__regZERO__regZERO__JumpTarget1_0,
350 : Convert__JumpTarget1_0,
351 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
352 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
353 : Convert__regZERO__JumpTarget1_0,
354 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
355 : Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
356 : Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
357 : Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
358 : Convert__FGR64AsmReg1_0__JumpTarget1_1,
359 : Convert__regFCC0__JumpTarget1_0,
360 : Convert__FCCAsmReg1_0__JumpTarget1_1,
361 : Convert__COP2AsmReg1_0__JumpTarget1_1,
362 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
363 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
364 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
365 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
366 : Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
367 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
368 : Convert__Reg1_0__JumpTarget1_1,
369 : Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
370 : Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
371 : Convert__GPR32AsmReg1_0__JumpTarget1_1,
372 : Convert__GPR64AsmReg1_0__JumpTarget1_1,
373 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
374 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
375 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
376 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
377 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
378 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
379 : Convert__MSA128AsmReg1_0__JumpTarget1_1,
380 : Convert__imm_95_0__imm_95_0,
381 : Convert_NoOperands,
382 : Convert__ConstantUImm10_01_0__imm_95_0,
383 : Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
384 : Convert__ConstantUImm4_01_0,
385 : Convert__SImm161_0,
386 : Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
387 : Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
388 : Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
389 : Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
390 : Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
391 : Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
392 : Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
393 : Convert__Mem2_1__ConstantUImm5_01_0,
394 : Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
395 : Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
396 : Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
397 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
398 : Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
399 : Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
400 : Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
401 : Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
402 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
403 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
404 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
405 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
406 : Convert__Reg1_0__Reg1_1,
407 : Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
408 : Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
409 : Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
410 : Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
411 : Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
412 : Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
413 : Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
414 : Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
415 : Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
416 : Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
417 : Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
418 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
419 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
420 : Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
421 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
422 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
423 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
424 : Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
425 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
426 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
427 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
428 : Convert__regZERO,
429 : Convert__GPR32AsmReg1_0,
430 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
431 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
432 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
433 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
434 : Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
435 : Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
436 : Convert__Reg1_1__Reg1_2,
437 : Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
438 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
439 : Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
440 : Convert__GPR64AsmReg1_0__Imm1_1,
441 : Convert__GPR64AsmReg1_0__Mem2_1,
442 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
443 : Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
444 : Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
445 : Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
446 : Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
447 : Convert__GPR64AsmReg1_0__UImm161_1,
448 : Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
449 : Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
450 : Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
451 : Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
452 : Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
453 : Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
454 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
455 : Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
456 : Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
457 : Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
458 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
459 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
460 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
461 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
462 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
463 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
464 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
465 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
466 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
467 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
468 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
469 : Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
470 : Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
471 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
472 : Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
473 : Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
474 : Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
475 : Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
476 : Convert__imm_95_0,
477 : Convert__ConstantUImm10_01_0,
478 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
479 : Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
480 : Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
481 : Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
482 : Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
483 : Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
484 : Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
485 : Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
486 : Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
487 : Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
488 : Convert__regRA__GPR32AsmReg1_0,
489 : Convert__regRA_64__GPR64AsmReg1_0,
490 : Convert__Reg1_0,
491 : Convert__GPR32AsmReg1_0__imm_95_0,
492 : Convert__GPR64AsmReg1_0__imm_95_0,
493 : Convert__regZERO__GPR32AsmReg1_0,
494 : Convert__GPR64AsmReg1_0,
495 : Convert__regZERO_64__GPR64AsmReg1_0,
496 : Convert__UImm5Lsl21_0,
497 : Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
498 : Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
499 : Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
500 : Convert__GPR32AsmReg1_0__Imm1_1,
501 : Convert__GPR32AsmReg1_0__Mem2_1,
502 : Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
503 : Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
504 : Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
505 : Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
506 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
507 : Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
508 : Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
509 : Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
510 : Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
511 : Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
512 : Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
513 : Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
514 : Convert__COP3AsmReg1_0__Mem2_1,
515 : Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
516 : Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
517 : Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
518 : Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
519 : Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
520 : Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
521 : Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
522 : Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
523 : Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
524 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
525 : Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
526 : Convert__GPR32AsmReg1_0__UImm161_1,
527 : Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
528 : Convert__Reg1_0__Imm1_1__imm_95_0,
529 : Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
530 : Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
531 : Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
532 : Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1,
533 : Convert__RegList1_0__Mem2_1,
534 : Convert__RegList161_0__MemOffsetUimm42_1,
535 : ConvertCustom_ConvertXWPOperands,
536 : Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
537 : Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
538 : Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
539 : Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
540 : Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
541 : Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
542 : Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
543 : Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
544 : Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
545 : Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
546 : Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
547 : Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
548 : Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
549 : Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
550 : Convert__GPR32AsmReg1_0__regAC0,
551 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
552 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
553 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
554 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
555 : Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3,
556 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
557 : Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
558 : Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
559 : Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
560 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
561 : Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
562 : Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
563 : Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
564 : Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
565 : Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
566 : Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
567 : Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
568 : Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
569 : Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
570 : Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
571 : Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
572 : Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
573 : Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
574 : Convert__regAC0__GPR32AsmReg1_0,
575 : Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
576 : Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
577 : Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
578 : Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
579 : Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
580 : Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
581 : Convert__regZERO__regZERO__imm_95_0,
582 : Convert__regZERO__regS0,
583 : Convert__regZERO__regZERO,
584 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
585 : Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
586 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
587 : Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
588 : Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
589 : Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
590 : Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
591 : Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
592 : Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
593 : Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
594 : Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
595 : Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
596 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
597 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
598 : Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
599 : Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
600 : Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
601 : Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
602 : Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
603 : Convert__ConstantUImm20_01_0,
604 : Convert__Reg1_0__Tie0_1_1,
605 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
606 : Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
607 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
608 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
609 : Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
610 : Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
611 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
612 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
613 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
614 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
615 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
616 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
617 : Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
618 : Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
619 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
620 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
621 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
622 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
623 : Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
624 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
625 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
626 : Convert__ConstantUImm5_01_0,
627 : Convert__MemOffsetSimm162_0,
628 : Convert__imm_95_2,
629 : Convert__imm_95_6,
630 : Convert__imm_95_4,
631 : Convert__imm_95_5,
632 : Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
633 : Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
634 : Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
635 : Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
636 : Convert__GPR32AsmReg1_0__imm_95_31,
637 : CVT_NUM_SIGNATURES
638 : };
639 :
640 : } // end anonymous namespace
641 :
642 : static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
643 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
644 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
645 : // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
646 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
647 : // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
648 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
649 : // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
650 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
651 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
652 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
653 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
654 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
655 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
656 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
657 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
658 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
659 : // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
660 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
661 : // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
662 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
663 : // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
664 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
665 : // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
666 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
667 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
668 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
669 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
670 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
671 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
672 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
673 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
674 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
675 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
676 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
677 : // Convert__SImm161_1
678 : { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
679 : // Convert__Reg1_0__SImm161_1
680 : { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
681 : // Convert__Reg1_0__SImm161_2
682 : { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
683 : // Convert__Reg1_0__Reg1_1__SImm161_2
684 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
685 : // Convert__Reg1_0__Tie0_1_1__SImm161_1
686 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
687 : // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
688 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
689 : // Convert__GPRMM16AsmReg1_0__Imm1_1
690 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
691 : // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
692 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
693 : // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
694 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
695 : // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
696 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
697 : // Convert__Imm1_0
698 : { CVT_95_addImmOperands, 1, CVT_Done },
699 : // Convert__Reg1_0__Reg1_1__Reg1_2
700 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
701 : // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
702 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
703 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
704 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
705 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
706 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
707 : // Convert__GPR32AsmReg1_0__SImm161_1
708 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
709 : // Convert__Reg1_0__Tie0_1_1__Reg1_1
710 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
711 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
712 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
713 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
714 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
715 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
716 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
717 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
718 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
719 : // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
720 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
721 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
722 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
723 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
724 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
725 : // Convert__regZERO__regZERO__JumpTarget1_0
726 : { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
727 : // Convert__JumpTarget1_0
728 : { CVT_95_addImmOperands, 1, CVT_Done },
729 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
730 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
731 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
732 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
733 : // Convert__regZERO__JumpTarget1_0
734 : { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
735 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
736 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
737 : // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
738 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
739 : // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
740 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
741 : // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
742 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
743 : // Convert__FGR64AsmReg1_0__JumpTarget1_1
744 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
745 : // Convert__regFCC0__JumpTarget1_0
746 : { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
747 : // Convert__FCCAsmReg1_0__JumpTarget1_1
748 : { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
749 : // Convert__COP2AsmReg1_0__JumpTarget1_1
750 : { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
751 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
752 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
753 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
754 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
755 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
756 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
757 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
758 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
759 : // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
760 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
761 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
762 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
763 : // Convert__Reg1_0__JumpTarget1_1
764 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
765 : // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
766 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
767 : // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
768 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
769 : // Convert__GPR32AsmReg1_0__JumpTarget1_1
770 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
771 : // Convert__GPR64AsmReg1_0__JumpTarget1_1
772 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
773 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
774 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
775 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
776 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
777 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
778 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
779 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
780 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
781 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
782 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
783 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
784 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
785 : // Convert__MSA128AsmReg1_0__JumpTarget1_1
786 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
787 : // Convert__imm_95_0__imm_95_0
788 : { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
789 : // Convert_NoOperands
790 : { CVT_Done },
791 : // Convert__ConstantUImm10_01_0__imm_95_0
792 : { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
793 : // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
794 : { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
795 : // Convert__ConstantUImm4_01_0
796 : { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
797 : // Convert__SImm161_0
798 : { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
799 : // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
800 : { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
801 : // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
802 : { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
803 : // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
804 : { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
805 : // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
806 : { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
807 : // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
808 : { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
809 : // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
810 : { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
811 : // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
812 : { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
813 : // Convert__Mem2_1__ConstantUImm5_01_0
814 : { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
815 : // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
816 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
817 : // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
818 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
819 : // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
820 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
821 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
822 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
823 : // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
824 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
825 : // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
826 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
827 : // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
828 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
829 : // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
830 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
831 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
832 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
833 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
834 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
835 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
836 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
837 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
838 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
839 : // Convert__Reg1_0__Reg1_1
840 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
841 : // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
842 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
843 : // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
844 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
845 : // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
846 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
847 : // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
848 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
849 : // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
850 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
851 : // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
852 : { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
853 : // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
854 : { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
855 : // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
856 : { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
857 : // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
858 : { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
859 : // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
860 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
861 : // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
862 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
863 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
864 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
865 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
866 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
867 : // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
868 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
869 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
870 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
871 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
872 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
873 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
874 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
875 : // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
876 : { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
877 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
878 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
879 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
880 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
881 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
882 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
883 : // Convert__regZERO
884 : { CVT_regZERO, 0, CVT_Done },
885 : // Convert__GPR32AsmReg1_0
886 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
887 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
888 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
889 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
890 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
891 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
892 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
893 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
894 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
895 : // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
896 : { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
897 : // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
898 : { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
899 : // Convert__Reg1_1__Reg1_2
900 : { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
901 : // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
902 : { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
903 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
904 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
905 : // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
906 : { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
907 : // Convert__GPR64AsmReg1_0__Imm1_1
908 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
909 : // Convert__GPR64AsmReg1_0__Mem2_1
910 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
911 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
912 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
913 : // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
914 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
915 : // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
916 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
917 : // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
918 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
919 : // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
920 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
921 : // Convert__GPR64AsmReg1_0__UImm161_1
922 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
923 : // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
924 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
925 : // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
926 : { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
927 : // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
928 : { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
929 : // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
930 : { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
931 : // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
932 : { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
933 : // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
934 : { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
935 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
936 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
937 : // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
938 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
939 : // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
940 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
941 : // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
942 : { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
943 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
944 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
945 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
946 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
947 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
948 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
949 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
950 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
951 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
952 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
953 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
954 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
955 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
956 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
957 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
958 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
959 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
960 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
961 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
962 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
963 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
964 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
965 : // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
966 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
967 : // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
968 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
969 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
970 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
971 : // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
972 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
973 : // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
974 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
975 : // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
976 : { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
977 : // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
978 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
979 : // Convert__imm_95_0
980 : { CVT_imm_95_0, 0, CVT_Done },
981 : // Convert__ConstantUImm10_01_0
982 : { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
983 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
984 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
985 : // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
986 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
987 : // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
988 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
989 : // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
990 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
991 : // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
992 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
993 : // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
994 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
995 : // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
996 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
997 : // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
998 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
999 : // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1000 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1001 : // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1002 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1003 : // Convert__regRA__GPR32AsmReg1_0
1004 : { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1005 : // Convert__regRA_64__GPR64AsmReg1_0
1006 : { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1007 : // Convert__Reg1_0
1008 : { CVT_95_Reg, 1, CVT_Done },
1009 : // Convert__GPR32AsmReg1_0__imm_95_0
1010 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1011 : // Convert__GPR64AsmReg1_0__imm_95_0
1012 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1013 : // Convert__regZERO__GPR32AsmReg1_0
1014 : { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1015 : // Convert__GPR64AsmReg1_0
1016 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1017 : // Convert__regZERO_64__GPR64AsmReg1_0
1018 : { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1019 : // Convert__UImm5Lsl21_0
1020 : { CVT_95_addImmOperands, 1, CVT_Done },
1021 : // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
1022 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1023 : // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
1024 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1025 : // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
1026 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1027 : // Convert__GPR32AsmReg1_0__Imm1_1
1028 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1029 : // Convert__GPR32AsmReg1_0__Mem2_1
1030 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1031 : // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
1032 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1033 : // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
1034 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1035 : // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
1036 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1037 : // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
1038 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1039 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1040 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1041 : // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
1042 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1043 : // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
1044 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1045 : // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
1046 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1047 : // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
1048 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1049 : // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
1050 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1051 : // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
1052 : { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1053 : // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
1054 : { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1055 : // Convert__COP3AsmReg1_0__Mem2_1
1056 : { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1057 : // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1058 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1059 : // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
1060 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1061 : // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1062 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1063 : // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1064 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1065 : // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1066 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1067 : // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1068 : { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1069 : // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1070 : { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1071 : // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1072 : { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1073 : // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1074 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1075 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1076 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1077 : // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1078 : { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1079 : // Convert__GPR32AsmReg1_0__UImm161_1
1080 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1081 : // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1082 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1083 : // Convert__Reg1_0__Imm1_1__imm_95_0
1084 : { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1085 : // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
1086 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1087 : // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
1088 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1089 : // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
1090 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1091 : // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1
1092 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1093 : // Convert__RegList1_0__Mem2_1
1094 : { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1095 : // Convert__RegList161_0__MemOffsetUimm42_1
1096 : { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1097 : // ConvertCustom_ConvertXWPOperands
1098 : { CVT_ConvertXWPOperands, 0, CVT_Done },
1099 : // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
1100 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1101 : // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1102 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1103 : // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1104 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1105 : // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1106 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1107 : // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1108 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1109 : // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1110 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1111 : // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1112 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1113 : // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1114 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1115 : // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1116 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1117 : // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1118 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1119 : // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1120 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1121 : // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1122 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1123 : // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1124 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1125 : // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1126 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1127 : // Convert__GPR32AsmReg1_0__regAC0
1128 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1129 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1130 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1131 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1132 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1133 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
1134 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
1135 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
1136 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
1137 : // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3
1138 : { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done },
1139 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1140 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1141 : // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1142 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1143 : // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1144 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1145 : // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1146 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1147 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1148 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1149 : // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1150 : { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1151 : // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1152 : { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1153 : // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1154 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1155 : // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1156 : { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1157 : // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1158 : { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1159 : // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
1160 : { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1161 : // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1162 : { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1163 : // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1164 : { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1165 : // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1166 : { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1167 : // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1168 : { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1169 : // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
1170 : { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1171 : // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
1172 : { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1173 : // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
1174 : { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1175 : // Convert__regAC0__GPR32AsmReg1_0
1176 : { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1177 : // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
1178 : { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1179 : // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
1180 : { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1181 : // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1182 : { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1183 : // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1184 : { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1185 : // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
1186 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1187 : // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
1188 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1189 : // Convert__regZERO__regZERO__imm_95_0
1190 : { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
1191 : // Convert__regZERO__regS0
1192 : { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
1193 : // Convert__regZERO__regZERO
1194 : { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
1195 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
1196 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
1197 : // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
1198 : { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
1199 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
1200 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1201 : // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
1202 : { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1203 : // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
1204 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
1205 : // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
1206 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1207 : // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1208 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1209 : // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1210 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1211 : // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
1212 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1213 : // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
1214 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1215 : // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
1216 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1217 : // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
1218 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
1219 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
1220 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1221 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
1222 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1223 : // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
1224 : { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1225 : // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1226 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1227 : // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
1228 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1229 : // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
1230 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1231 : // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
1232 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1233 : // Convert__ConstantUImm20_01_0
1234 : { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
1235 : // Convert__Reg1_0__Tie0_1_1
1236 : { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1237 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
1238 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1239 : // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
1240 : { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1241 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
1242 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1243 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
1244 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1245 : // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
1246 : { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1247 : // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
1248 : { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1249 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
1250 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1251 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
1252 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1253 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
1254 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1255 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
1256 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1257 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
1258 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1259 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
1260 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1261 : // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
1262 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1263 : // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
1264 : { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1265 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
1266 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1267 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1268 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1269 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1270 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1271 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1272 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1273 : // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1274 : { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1275 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
1276 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1277 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
1278 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1279 : // Convert__ConstantUImm5_01_0
1280 : { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1281 : // Convert__MemOffsetSimm162_0
1282 : { CVT_95_addMemOperands, 1, CVT_Done },
1283 : // Convert__imm_95_2
1284 : { CVT_imm_95_2, 0, CVT_Done },
1285 : // Convert__imm_95_6
1286 : { CVT_imm_95_6, 0, CVT_Done },
1287 : // Convert__imm_95_4
1288 : { CVT_imm_95_4, 0, CVT_Done },
1289 : // Convert__imm_95_5
1290 : { CVT_imm_95_5, 0, CVT_Done },
1291 : // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
1292 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1293 : // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
1294 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1295 : // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
1296 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1297 : // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
1298 : { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1299 : // Convert__GPR32AsmReg1_0__imm_95_31
1300 : { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
1301 : };
1302 :
1303 0 : void MipsAsmParser::
1304 : convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1305 : const OperandVector &Operands) {
1306 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1307 0 : const uint8_t *Converter = ConversionTable[Kind];
1308 : unsigned OpIdx;
1309 : Inst.setOpcode(Opcode);
1310 0 : for (const uint8_t *p = Converter; *p; p+= 2) {
1311 0 : OpIdx = *(p + 1);
1312 0 : switch (*p) {
1313 0 : default: llvm_unreachable("invalid conversion entry!");
1314 0 : case CVT_Reg:
1315 : static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1316 : break;
1317 0 : case CVT_Tied: {
1318 : assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1319 : std::begin(TiedAsmOperandTable)) &&
1320 : "Tied operand not found");
1321 0 : unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
1322 0 : if (TiedResOpnd != (uint8_t) -1)
1323 : Inst.addOperand(Inst.getOperand(TiedResOpnd));
1324 : break;
1325 : }
1326 0 : case CVT_95_addGPR32AsmRegOperands:
1327 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
1328 0 : break;
1329 0 : case CVT_95_addAFGR64AsmRegOperands:
1330 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
1331 0 : break;
1332 0 : case CVT_95_addFGR64AsmRegOperands:
1333 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
1334 0 : break;
1335 0 : case CVT_95_addFGR32AsmRegOperands:
1336 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
1337 0 : break;
1338 0 : case CVT_95_addSImmOperands_LT_32_GT_:
1339 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
1340 0 : break;
1341 0 : case CVT_95_addMSA128AsmRegOperands:
1342 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
1343 0 : break;
1344 0 : case CVT_95_addSImmOperands_LT_16_GT_:
1345 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
1346 0 : break;
1347 0 : case CVT_95_Reg:
1348 : static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1349 : break;
1350 0 : case CVT_95_addImmOperands:
1351 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
1352 : break;
1353 0 : case CVT_95_addGPRMM16AsmRegOperands:
1354 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
1355 0 : break;
1356 0 : case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1357 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
1358 0 : break;
1359 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1360 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
1361 0 : break;
1362 0 : case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1363 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
1364 0 : break;
1365 0 : case CVT_95_addUImmOperands_LT_16_GT_:
1366 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
1367 0 : break;
1368 0 : case CVT_95_addGPR64AsmRegOperands:
1369 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
1370 0 : break;
1371 0 : case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1372 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
1373 0 : break;
1374 : case CVT_regZERO:
1375 0 : Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1376 0 : break;
1377 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1378 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
1379 0 : break;
1380 : case CVT_regFCC0:
1381 0 : Inst.addOperand(MCOperand::createReg(Mips::FCC0));
1382 0 : break;
1383 0 : case CVT_95_addFCCAsmRegOperands:
1384 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
1385 0 : break;
1386 0 : case CVT_95_addCOP2AsmRegOperands:
1387 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
1388 0 : break;
1389 0 : case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1390 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
1391 0 : break;
1392 0 : case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1393 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
1394 0 : break;
1395 0 : case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1396 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
1397 0 : break;
1398 : case CVT_imm_95_0:
1399 0 : Inst.addOperand(MCOperand::createImm(0));
1400 0 : break;
1401 0 : case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1402 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
1403 0 : break;
1404 0 : case CVT_95_addMemOperands:
1405 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
1406 0 : break;
1407 0 : case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1408 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
1409 0 : break;
1410 0 : case CVT_95_addCCRAsmRegOperands:
1411 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
1412 0 : break;
1413 0 : case CVT_95_addMSACtrlAsmRegOperands:
1414 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
1415 0 : break;
1416 0 : case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1417 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
1418 0 : break;
1419 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1420 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
1421 0 : break;
1422 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1423 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
1424 0 : break;
1425 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1426 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
1427 0 : break;
1428 0 : case CVT_95_addGPR32NonZeroAsmRegOperands:
1429 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
1430 0 : break;
1431 0 : case CVT_95_addGPR32ZeroAsmRegOperands:
1432 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
1433 0 : break;
1434 0 : case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1435 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
1436 0 : break;
1437 0 : case CVT_95_addCOP0AsmRegOperands:
1438 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
1439 0 : break;
1440 : case CVT_regZERO_64:
1441 0 : Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
1442 0 : break;
1443 0 : case CVT_95_addACC64DSPAsmRegOperands:
1444 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
1445 0 : break;
1446 0 : case CVT_95_addConstantUImmOperands_LT_1_GT_:
1447 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
1448 0 : break;
1449 : case CVT_regRA:
1450 0 : Inst.addOperand(MCOperand::createReg(Mips::RA));
1451 0 : break;
1452 : case CVT_regRA_64:
1453 0 : Inst.addOperand(MCOperand::createReg(Mips::RA_64));
1454 0 : break;
1455 0 : case CVT_95_addMicroMipsMemOperands:
1456 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
1457 0 : break;
1458 0 : case CVT_95_addCOP3AsmRegOperands:
1459 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
1460 0 : break;
1461 0 : case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1462 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
1463 0 : break;
1464 0 : case CVT_95_addConstantUImmOperands_LT_32_GT_:
1465 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
1466 0 : break;
1467 0 : case CVT_95_addStrictlyAFGR64AsmRegOperands:
1468 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
1469 0 : break;
1470 0 : case CVT_95_addStrictlyFGR64AsmRegOperands:
1471 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
1472 0 : break;
1473 0 : case CVT_95_addStrictlyFGR32AsmRegOperands:
1474 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
1475 0 : break;
1476 0 : case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1477 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
1478 0 : break;
1479 0 : case CVT_95_addRegListOperands:
1480 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
1481 0 : break;
1482 0 : case CVT_ConvertXWPOperands:
1483 0 : ConvertXWPOperands(Inst, Operands);
1484 0 : break;
1485 : case CVT_regAC0:
1486 0 : Inst.addOperand(MCOperand::createReg(Mips::AC0));
1487 0 : break;
1488 0 : case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1489 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1);
1490 0 : break;
1491 0 : case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1492 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1);
1493 0 : break;
1494 0 : case CVT_95_addGPRMM16AsmRegMovePOperands:
1495 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
1496 0 : break;
1497 0 : case CVT_95_addHI32DSPAsmRegOperands:
1498 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
1499 0 : break;
1500 0 : case CVT_95_addLO32DSPAsmRegOperands:
1501 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
1502 0 : break;
1503 : case CVT_regS0:
1504 0 : Inst.addOperand(MCOperand::createReg(Mips::S0));
1505 0 : break;
1506 0 : case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1507 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
1508 0 : break;
1509 0 : case CVT_95_addHWRegsAsmRegOperands:
1510 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
1511 0 : break;
1512 0 : case CVT_95_addGPRMM16AsmRegZeroOperands:
1513 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
1514 0 : break;
1515 0 : case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1516 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
1517 0 : break;
1518 0 : case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1519 0 : static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
1520 0 : break;
1521 : case CVT_imm_95_2:
1522 0 : Inst.addOperand(MCOperand::createImm(2));
1523 0 : break;
1524 : case CVT_imm_95_6:
1525 0 : Inst.addOperand(MCOperand::createImm(6));
1526 0 : break;
1527 : case CVT_imm_95_4:
1528 0 : Inst.addOperand(MCOperand::createImm(4));
1529 0 : break;
1530 : case CVT_imm_95_5:
1531 0 : Inst.addOperand(MCOperand::createImm(5));
1532 0 : break;
1533 : case CVT_imm_95_31:
1534 0 : Inst.addOperand(MCOperand::createImm(31));
1535 0 : break;
1536 : }
1537 : }
1538 0 : }
1539 :
1540 0 : void MipsAsmParser::
1541 : convertToMapAndConstraints(unsigned Kind,
1542 : const OperandVector &Operands) {
1543 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1544 : unsigned NumMCOperands = 0;
1545 0 : const uint8_t *Converter = ConversionTable[Kind];
1546 0 : for (const uint8_t *p = Converter; *p; p+= 2) {
1547 0 : switch (*p) {
1548 0 : default: llvm_unreachable("invalid conversion entry!");
1549 0 : case CVT_Reg:
1550 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1551 0 : Operands[*(p + 1)]->setConstraint("r");
1552 0 : ++NumMCOperands;
1553 0 : break;
1554 0 : case CVT_Tied:
1555 0 : ++NumMCOperands;
1556 0 : break;
1557 0 : case CVT_95_addGPR32AsmRegOperands:
1558 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1559 0 : Operands[*(p + 1)]->setConstraint("m");
1560 0 : NumMCOperands += 1;
1561 0 : break;
1562 0 : case CVT_95_addAFGR64AsmRegOperands:
1563 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1564 0 : Operands[*(p + 1)]->setConstraint("m");
1565 0 : NumMCOperands += 1;
1566 0 : break;
1567 0 : case CVT_95_addFGR64AsmRegOperands:
1568 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1569 0 : Operands[*(p + 1)]->setConstraint("m");
1570 0 : NumMCOperands += 1;
1571 0 : break;
1572 0 : case CVT_95_addFGR32AsmRegOperands:
1573 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1574 0 : Operands[*(p + 1)]->setConstraint("m");
1575 0 : NumMCOperands += 1;
1576 0 : break;
1577 0 : case CVT_95_addSImmOperands_LT_32_GT_:
1578 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1579 0 : Operands[*(p + 1)]->setConstraint("m");
1580 0 : NumMCOperands += 1;
1581 0 : break;
1582 0 : case CVT_95_addMSA128AsmRegOperands:
1583 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1584 0 : Operands[*(p + 1)]->setConstraint("m");
1585 0 : NumMCOperands += 1;
1586 0 : break;
1587 0 : case CVT_95_addSImmOperands_LT_16_GT_:
1588 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1589 0 : Operands[*(p + 1)]->setConstraint("m");
1590 0 : NumMCOperands += 1;
1591 0 : break;
1592 0 : case CVT_95_Reg:
1593 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1594 0 : Operands[*(p + 1)]->setConstraint("r");
1595 0 : NumMCOperands += 1;
1596 0 : break;
1597 0 : case CVT_95_addImmOperands:
1598 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1599 0 : Operands[*(p + 1)]->setConstraint("m");
1600 0 : NumMCOperands += 1;
1601 0 : break;
1602 0 : case CVT_95_addGPRMM16AsmRegOperands:
1603 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1604 0 : Operands[*(p + 1)]->setConstraint("m");
1605 0 : NumMCOperands += 1;
1606 0 : break;
1607 0 : case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1608 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1609 0 : Operands[*(p + 1)]->setConstraint("m");
1610 0 : NumMCOperands += 1;
1611 0 : break;
1612 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1613 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1614 0 : Operands[*(p + 1)]->setConstraint("m");
1615 0 : NumMCOperands += 1;
1616 0 : break;
1617 0 : case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1618 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1619 0 : Operands[*(p + 1)]->setConstraint("m");
1620 0 : NumMCOperands += 1;
1621 0 : break;
1622 0 : case CVT_95_addUImmOperands_LT_16_GT_:
1623 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1624 0 : Operands[*(p + 1)]->setConstraint("m");
1625 0 : NumMCOperands += 1;
1626 0 : break;
1627 0 : case CVT_95_addGPR64AsmRegOperands:
1628 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1629 0 : Operands[*(p + 1)]->setConstraint("m");
1630 0 : NumMCOperands += 1;
1631 0 : break;
1632 0 : case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1633 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1634 0 : Operands[*(p + 1)]->setConstraint("m");
1635 0 : NumMCOperands += 1;
1636 0 : break;
1637 0 : case CVT_regZERO:
1638 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1639 0 : Operands[*(p + 1)]->setConstraint("m");
1640 0 : ++NumMCOperands;
1641 0 : break;
1642 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1643 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1644 0 : Operands[*(p + 1)]->setConstraint("m");
1645 0 : NumMCOperands += 1;
1646 0 : break;
1647 0 : case CVT_regFCC0:
1648 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1649 0 : Operands[*(p + 1)]->setConstraint("m");
1650 0 : ++NumMCOperands;
1651 0 : break;
1652 0 : case CVT_95_addFCCAsmRegOperands:
1653 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1654 0 : Operands[*(p + 1)]->setConstraint("m");
1655 0 : NumMCOperands += 1;
1656 0 : break;
1657 0 : case CVT_95_addCOP2AsmRegOperands:
1658 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1659 0 : Operands[*(p + 1)]->setConstraint("m");
1660 0 : NumMCOperands += 1;
1661 0 : break;
1662 0 : case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1663 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1664 0 : Operands[*(p + 1)]->setConstraint("m");
1665 0 : NumMCOperands += 1;
1666 0 : break;
1667 0 : case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1668 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1669 0 : Operands[*(p + 1)]->setConstraint("m");
1670 0 : NumMCOperands += 1;
1671 0 : break;
1672 0 : case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1673 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1674 0 : Operands[*(p + 1)]->setConstraint("m");
1675 0 : NumMCOperands += 1;
1676 0 : break;
1677 0 : case CVT_imm_95_0:
1678 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1679 0 : Operands[*(p + 1)]->setConstraint("");
1680 0 : ++NumMCOperands;
1681 0 : break;
1682 0 : case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1683 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1684 0 : Operands[*(p + 1)]->setConstraint("m");
1685 0 : NumMCOperands += 1;
1686 0 : break;
1687 0 : case CVT_95_addMemOperands:
1688 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1689 0 : Operands[*(p + 1)]->setConstraint("m");
1690 0 : NumMCOperands += 2;
1691 0 : break;
1692 0 : case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1693 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1694 0 : Operands[*(p + 1)]->setConstraint("m");
1695 0 : NumMCOperands += 1;
1696 0 : break;
1697 0 : case CVT_95_addCCRAsmRegOperands:
1698 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1699 0 : Operands[*(p + 1)]->setConstraint("m");
1700 0 : NumMCOperands += 1;
1701 0 : break;
1702 0 : case CVT_95_addMSACtrlAsmRegOperands:
1703 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1704 0 : Operands[*(p + 1)]->setConstraint("m");
1705 0 : NumMCOperands += 1;
1706 0 : break;
1707 0 : case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1708 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1709 0 : Operands[*(p + 1)]->setConstraint("m");
1710 0 : NumMCOperands += 1;
1711 0 : break;
1712 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1713 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1714 0 : Operands[*(p + 1)]->setConstraint("m");
1715 0 : NumMCOperands += 1;
1716 0 : break;
1717 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1718 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1719 0 : Operands[*(p + 1)]->setConstraint("m");
1720 0 : NumMCOperands += 1;
1721 0 : break;
1722 0 : case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1723 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1724 0 : Operands[*(p + 1)]->setConstraint("m");
1725 0 : NumMCOperands += 1;
1726 0 : break;
1727 0 : case CVT_95_addGPR32NonZeroAsmRegOperands:
1728 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1729 0 : Operands[*(p + 1)]->setConstraint("m");
1730 0 : NumMCOperands += 1;
1731 0 : break;
1732 0 : case CVT_95_addGPR32ZeroAsmRegOperands:
1733 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1734 0 : Operands[*(p + 1)]->setConstraint("m");
1735 0 : NumMCOperands += 1;
1736 0 : break;
1737 0 : case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1738 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1739 0 : Operands[*(p + 1)]->setConstraint("m");
1740 0 : NumMCOperands += 1;
1741 0 : break;
1742 0 : case CVT_95_addCOP0AsmRegOperands:
1743 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1744 0 : Operands[*(p + 1)]->setConstraint("m");
1745 0 : NumMCOperands += 1;
1746 0 : break;
1747 0 : case CVT_regZERO_64:
1748 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1749 0 : Operands[*(p + 1)]->setConstraint("m");
1750 0 : ++NumMCOperands;
1751 0 : break;
1752 0 : case CVT_95_addACC64DSPAsmRegOperands:
1753 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1754 0 : Operands[*(p + 1)]->setConstraint("m");
1755 0 : NumMCOperands += 1;
1756 0 : break;
1757 0 : case CVT_95_addConstantUImmOperands_LT_1_GT_:
1758 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1759 0 : Operands[*(p + 1)]->setConstraint("m");
1760 0 : NumMCOperands += 1;
1761 0 : break;
1762 0 : case CVT_regRA:
1763 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1764 0 : Operands[*(p + 1)]->setConstraint("m");
1765 0 : ++NumMCOperands;
1766 0 : break;
1767 0 : case CVT_regRA_64:
1768 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1769 0 : Operands[*(p + 1)]->setConstraint("m");
1770 0 : ++NumMCOperands;
1771 0 : break;
1772 0 : case CVT_95_addMicroMipsMemOperands:
1773 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1774 0 : Operands[*(p + 1)]->setConstraint("m");
1775 0 : NumMCOperands += 2;
1776 0 : break;
1777 0 : case CVT_95_addCOP3AsmRegOperands:
1778 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1779 0 : Operands[*(p + 1)]->setConstraint("m");
1780 0 : NumMCOperands += 1;
1781 0 : break;
1782 0 : case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1783 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1784 0 : Operands[*(p + 1)]->setConstraint("m");
1785 0 : NumMCOperands += 1;
1786 0 : break;
1787 0 : case CVT_95_addConstantUImmOperands_LT_32_GT_:
1788 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1789 0 : Operands[*(p + 1)]->setConstraint("m");
1790 0 : NumMCOperands += 1;
1791 0 : break;
1792 0 : case CVT_95_addStrictlyAFGR64AsmRegOperands:
1793 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1794 0 : Operands[*(p + 1)]->setConstraint("m");
1795 0 : NumMCOperands += 1;
1796 0 : break;
1797 0 : case CVT_95_addStrictlyFGR64AsmRegOperands:
1798 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1799 0 : Operands[*(p + 1)]->setConstraint("m");
1800 0 : NumMCOperands += 1;
1801 0 : break;
1802 0 : case CVT_95_addStrictlyFGR32AsmRegOperands:
1803 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1804 0 : Operands[*(p + 1)]->setConstraint("m");
1805 0 : NumMCOperands += 1;
1806 0 : break;
1807 0 : case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1808 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1809 0 : Operands[*(p + 1)]->setConstraint("m");
1810 0 : NumMCOperands += 1;
1811 0 : break;
1812 0 : case CVT_95_addRegListOperands:
1813 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1814 0 : Operands[*(p + 1)]->setConstraint("m");
1815 0 : NumMCOperands += 1;
1816 0 : break;
1817 0 : case CVT_regAC0:
1818 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1819 0 : Operands[*(p + 1)]->setConstraint("m");
1820 0 : ++NumMCOperands;
1821 0 : break;
1822 0 : case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1823 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1824 0 : Operands[*(p + 1)]->setConstraint("m");
1825 0 : NumMCOperands += 1;
1826 0 : break;
1827 0 : case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1828 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1829 0 : Operands[*(p + 1)]->setConstraint("m");
1830 0 : NumMCOperands += 1;
1831 0 : break;
1832 0 : case CVT_95_addGPRMM16AsmRegMovePOperands:
1833 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1834 0 : Operands[*(p + 1)]->setConstraint("m");
1835 0 : NumMCOperands += 1;
1836 0 : break;
1837 0 : case CVT_95_addHI32DSPAsmRegOperands:
1838 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1839 0 : Operands[*(p + 1)]->setConstraint("m");
1840 0 : NumMCOperands += 1;
1841 0 : break;
1842 0 : case CVT_95_addLO32DSPAsmRegOperands:
1843 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1844 0 : Operands[*(p + 1)]->setConstraint("m");
1845 0 : NumMCOperands += 1;
1846 0 : break;
1847 0 : case CVT_regS0:
1848 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1849 0 : Operands[*(p + 1)]->setConstraint("m");
1850 0 : ++NumMCOperands;
1851 0 : break;
1852 0 : case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1853 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1854 0 : Operands[*(p + 1)]->setConstraint("m");
1855 0 : NumMCOperands += 1;
1856 0 : break;
1857 0 : case CVT_95_addHWRegsAsmRegOperands:
1858 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1859 0 : Operands[*(p + 1)]->setConstraint("m");
1860 0 : NumMCOperands += 1;
1861 0 : break;
1862 0 : case CVT_95_addGPRMM16AsmRegZeroOperands:
1863 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1864 0 : Operands[*(p + 1)]->setConstraint("m");
1865 0 : NumMCOperands += 1;
1866 0 : break;
1867 0 : case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1868 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1869 0 : Operands[*(p + 1)]->setConstraint("m");
1870 0 : NumMCOperands += 1;
1871 0 : break;
1872 0 : case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1873 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1874 0 : Operands[*(p + 1)]->setConstraint("m");
1875 0 : NumMCOperands += 1;
1876 0 : break;
1877 0 : case CVT_imm_95_2:
1878 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1879 0 : Operands[*(p + 1)]->setConstraint("");
1880 0 : ++NumMCOperands;
1881 0 : break;
1882 0 : case CVT_imm_95_6:
1883 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1884 0 : Operands[*(p + 1)]->setConstraint("");
1885 0 : ++NumMCOperands;
1886 0 : break;
1887 0 : case CVT_imm_95_4:
1888 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1889 0 : Operands[*(p + 1)]->setConstraint("");
1890 0 : ++NumMCOperands;
1891 0 : break;
1892 0 : case CVT_imm_95_5:
1893 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1894 0 : Operands[*(p + 1)]->setConstraint("");
1895 0 : ++NumMCOperands;
1896 0 : break;
1897 0 : case CVT_imm_95_31:
1898 0 : Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1899 0 : Operands[*(p + 1)]->setConstraint("");
1900 0 : ++NumMCOperands;
1901 0 : break;
1902 : }
1903 : }
1904 0 : }
1905 :
1906 : namespace {
1907 :
1908 : /// MatchClassKind - The kinds of classes which participate in
1909 : /// instruction matching.
1910 : enum MatchClassKind {
1911 : InvalidMatchClass = 0,
1912 : OptionalMatchClass = 1,
1913 : MCK__35_, // '#'
1914 : MCK__40_, // '('
1915 : MCK__41_, // ')'
1916 : MCK_0, // '0'
1917 : MCK_16, // '16'
1918 : MCK__91_, // '['
1919 : MCK__93_, // ']'
1920 : MCK_bit, // 'bit'
1921 : MCK_inst, // 'inst'
1922 : MCK_LAST_TOKEN = MCK_inst,
1923 : MCK_Reg19, // derived register class
1924 : MCK_Reg37, // derived register class
1925 : MCK_ACC128, // register class 'ACC128'
1926 : MCK_ACC64, // register class 'ACC64'
1927 : MCK_CPURAReg, // register class 'CPURAReg,RA'
1928 : MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
1929 : MCK_DSPCC, // register class 'DSPCC'
1930 : MCK_GP32, // register class 'GP32'
1931 : MCK_GP64, // register class 'GP64'
1932 : MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
1933 : MCK_HI32, // register class 'HI32'
1934 : MCK_HI64, // register class 'HI64'
1935 : MCK_LO32, // register class 'LO32'
1936 : MCK_LO64, // register class 'LO64'
1937 : MCK_PC, // register class 'PC'
1938 : MCK_SP64, // register class 'SP64'
1939 : MCK_Reg13, // derived register class
1940 : MCK_Reg32, // derived register class
1941 : MCK_Reg11, // derived register class
1942 : MCK_Reg14, // derived register class
1943 : MCK_Reg30, // derived register class
1944 : MCK_Reg31, // derived register class
1945 : MCK_Reg33, // derived register class
1946 : MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst'
1947 : MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
1948 : MCK_OCTEON_P, // register class 'OCTEON_P'
1949 : MCK_Reg4, // derived register class
1950 : MCK_Reg9, // derived register class
1951 : MCK_Reg23, // derived register class
1952 : MCK_Reg28, // derived register class
1953 : MCK_ACC64DSP, // register class 'ACC64DSP'
1954 : MCK_HI32DSP, // register class 'HI32DSP'
1955 : MCK_LO32DSP, // register class 'LO32DSP'
1956 : MCK_Reg34, // derived register class
1957 : MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond'
1958 : MCK_Reg8, // derived register class
1959 : MCK_Reg10, // derived register class
1960 : MCK_Reg27, // derived register class
1961 : MCK_Reg29, // derived register class
1962 : MCK_Reg21, // derived register class
1963 : MCK_Reg22, // derived register class
1964 : MCK_Reg25, // derived register class
1965 : MCK_Reg44, // derived register class
1966 : MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
1967 : MCK_FCC, // register class 'FCC'
1968 : MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
1969 : MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
1970 : MCK_MSACtrl, // register class 'MSACtrl'
1971 : MCK_Reg26, // derived register class
1972 : MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
1973 : MCK_Reg39, // derived register class
1974 : MCK_Reg42, // derived register class
1975 : MCK_Reg47, // derived register class
1976 : MCK_Reg50, // derived register class
1977 : MCK_AFGR64, // register class 'AFGR64'
1978 : MCK_MSA128WEvens, // register class 'MSA128WEvens'
1979 : MCK_Reg45, // derived register class
1980 : MCK_Reg24, // derived register class
1981 : MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
1982 : MCK_CCR, // register class 'CCR'
1983 : MCK_COP0, // register class 'COP0'
1984 : MCK_COP2, // register class 'COP2'
1985 : MCK_COP3, // register class 'COP3'
1986 : MCK_DSPR, // register class 'DSPR,GPR32'
1987 : MCK_FGR32, // register class 'FGR32,FGRCC'
1988 : MCK_FGR64, // register class 'FGR64'
1989 : MCK_FGRH32, // register class 'FGRH32'
1990 : MCK_GPR64, // register class 'GPR64'
1991 : MCK_HWRegs, // register class 'HWRegs'
1992 : MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
1993 : MCK_OddSP, // register class 'OddSP'
1994 : MCK_LAST_REGISTER = MCK_OddSP,
1995 : MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
1996 : MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
1997 : MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
1998 : MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
1999 : MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
2000 : MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
2001 : MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
2002 : MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
2003 : MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
2004 : MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
2005 : MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
2006 : MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
2007 : MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
2008 : MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
2009 : MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
2010 : MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
2011 : MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst'
2012 : MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond'
2013 : MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
2014 : MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
2015 : MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
2016 : MCK_Imm, // user defined class 'ImmAsmOperand'
2017 : MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
2018 : MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
2019 : MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
2020 : MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
2021 : MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
2022 : MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
2023 : MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
2024 : MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2025 : MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
2026 : MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
2027 : MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
2028 : MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
2029 : MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
2030 : MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
2031 : MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
2032 : MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
2033 : MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
2034 : MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
2035 : MCK_Mem, // user defined class 'MipsMemAsmOperand'
2036 : MCK_RegList16, // user defined class 'RegList16AsmOperand'
2037 : MCK_RegList, // user defined class 'RegListAsmOperand'
2038 : MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2039 : MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2040 : MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2041 : MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2042 : MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2043 : MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2044 : MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2045 : MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2046 : MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2047 : MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2048 : MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2049 : MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2050 : MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2051 : MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2052 : MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2053 : MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2054 : MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2055 : MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2056 : MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2057 : MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2058 : MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2059 : MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2060 : MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2061 : MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2062 : MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2063 : MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2064 : MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2065 : MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2066 : MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2067 : MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2068 : MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2069 : MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2070 : MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2071 : MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2072 : MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2073 : MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2074 : MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2075 : MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2076 : MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2077 : MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2078 : MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2079 : MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2080 : MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2081 : MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2082 : MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2083 : MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2084 : NumMatchClassKinds
2085 : };
2086 :
2087 : }
2088 :
2089 0 : static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2090 0 : return MCTargetAsmParser::Match_InvalidOperand;
2091 : }
2092 :
2093 880 : static MatchClassKind matchTokenString(StringRef Name) {
2094 880 : switch (Name.size()) {
2095 : default: break;
2096 880 : case 1: // 6 strings to match.
2097 : switch (Name[0]) {
2098 : default: break;
2099 : case '#': // 1 string to match.
2100 : return MCK__35_; // "#"
2101 363 : case '(': // 1 string to match.
2102 363 : return MCK__40_; // "("
2103 363 : case ')': // 1 string to match.
2104 363 : return MCK__41_; // ")"
2105 0 : case '0': // 1 string to match.
2106 0 : return MCK_0; // "0"
2107 112 : case '[': // 1 string to match.
2108 112 : return MCK__91_; // "["
2109 42 : case ']': // 1 string to match.
2110 42 : return MCK__93_; // "]"
2111 : }
2112 : break;
2113 : case 2: // 1 string to match.
2114 0 : if (memcmp(Name.data()+0, "16", 2) != 0)
2115 : break;
2116 : return MCK_16; // "16"
2117 : case 3: // 1 string to match.
2118 0 : if (memcmp(Name.data()+0, "bit", 3) != 0)
2119 : break;
2120 : return MCK_bit; // "bit"
2121 : case 4: // 1 string to match.
2122 0 : if (memcmp(Name.data()+0, "inst", 4) != 0)
2123 : break;
2124 : return MCK_inst; // "inst"
2125 : }
2126 : return InvalidMatchClass;
2127 : }
2128 :
2129 : /// isSubclass - Compute whether \p A is a subclass of \p B.
2130 39679 : static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2131 39679 : if (A == B)
2132 : return true;
2133 :
2134 38679 : switch (A) {
2135 : default:
2136 : return false;
2137 :
2138 0 : case MCK_Reg19:
2139 0 : switch (B) {
2140 : default: return false;
2141 0 : case MCK_Reg23: return true;
2142 0 : case MCK_Reg21: return true;
2143 0 : case MCK_Reg22: return true;
2144 0 : case MCK_GPR64: return true;
2145 : }
2146 :
2147 0 : case MCK_Reg37:
2148 0 : switch (B) {
2149 : default: return false;
2150 0 : case MCK_Reg24: return true;
2151 0 : case MCK_GPR64: return true;
2152 : }
2153 :
2154 0 : case MCK_ACC64:
2155 0 : return B == MCK_ACC64DSP;
2156 :
2157 133 : case MCK_CPURAReg:
2158 133 : switch (B) {
2159 : default: return false;
2160 0 : case MCK_GPR32NONZERO: return true;
2161 0 : case MCK_DSPR: return true;
2162 : }
2163 :
2164 548 : case MCK_CPUSPReg:
2165 : switch (B) {
2166 : default: return false;
2167 : case MCK_CPU16RegsPlusSP: return true;
2168 : case MCK_GPR32NONZERO: return true;
2169 : case MCK_DSPR: return true;
2170 : }
2171 :
2172 0 : case MCK_GP32:
2173 0 : switch (B) {
2174 : default: return false;
2175 0 : case MCK_GPR32NONZERO: return true;
2176 0 : case MCK_DSPR: return true;
2177 : }
2178 :
2179 0 : case MCK_GP64:
2180 0 : switch (B) {
2181 : default: return false;
2182 0 : case MCK_Reg24: return true;
2183 0 : case MCK_GPR64: return true;
2184 : }
2185 :
2186 351 : case MCK_GPR32ZERO:
2187 351 : switch (B) {
2188 : default: return false;
2189 0 : case MCK_Reg4: return true;
2190 0 : case MCK_GPRMM16MoveP: return true;
2191 0 : case MCK_GPRMM16Zero: return true;
2192 0 : case MCK_DSPR: return true;
2193 : }
2194 :
2195 0 : case MCK_HI32:
2196 0 : return B == MCK_HI32DSP;
2197 :
2198 0 : case MCK_LO32:
2199 0 : return B == MCK_LO32DSP;
2200 :
2201 0 : case MCK_SP64:
2202 : switch (B) {
2203 : default: return false;
2204 : case MCK_Reg26: return true;
2205 : case MCK_Reg24: return true;
2206 : case MCK_GPR64: return true;
2207 : }
2208 :
2209 0 : case MCK_Reg13:
2210 : switch (B) {
2211 : default: return false;
2212 : case MCK_Reg14: return true;
2213 : case MCK_GPRMM16MovePPairFirst: return true;
2214 : case MCK_GPRMM16MovePPairSecond: return true;
2215 : case MCK_Reg8: return true;
2216 : case MCK_CPU16Regs: return true;
2217 : case MCK_GPRMM16Zero: return true;
2218 : case MCK_CPU16RegsPlusSP: return true;
2219 : case MCK_GPR32NONZERO: return true;
2220 : case MCK_DSPR: return true;
2221 : }
2222 :
2223 0 : case MCK_Reg32:
2224 : switch (B) {
2225 : default: return false;
2226 : case MCK_Reg31: return true;
2227 : case MCK_Reg33: return true;
2228 : case MCK_Reg34: return true;
2229 : case MCK_Reg27: return true;
2230 : case MCK_Reg21: return true;
2231 : case MCK_Reg25: return true;
2232 : case MCK_Reg26: return true;
2233 : case MCK_Reg24: return true;
2234 : case MCK_GPR64: return true;
2235 : }
2236 :
2237 0 : case MCK_Reg11:
2238 : switch (B) {
2239 : default: return false;
2240 : case MCK_Reg4: return true;
2241 : case MCK_Reg9: return true;
2242 : case MCK_Reg8: return true;
2243 : case MCK_Reg10: return true;
2244 : case MCK_CPU16Regs: return true;
2245 : case MCK_GPRMM16MoveP: return true;
2246 : case MCK_GPRMM16Zero: return true;
2247 : case MCK_CPU16RegsPlusSP: return true;
2248 : case MCK_GPR32NONZERO: return true;
2249 : case MCK_DSPR: return true;
2250 : }
2251 :
2252 0 : case MCK_Reg14:
2253 : switch (B) {
2254 : default: return false;
2255 : case MCK_GPRMM16MovePPairSecond: return true;
2256 : case MCK_Reg8: return true;
2257 : case MCK_CPU16Regs: return true;
2258 : case MCK_GPRMM16Zero: return true;
2259 : case MCK_CPU16RegsPlusSP: return true;
2260 : case MCK_GPR32NONZERO: return true;
2261 : case MCK_DSPR: return true;
2262 : }
2263 :
2264 0 : case MCK_Reg30:
2265 : switch (B) {
2266 : default: return false;
2267 : case MCK_Reg23: return true;
2268 : case MCK_Reg28: return true;
2269 : case MCK_Reg27: return true;
2270 : case MCK_Reg29: return true;
2271 : case MCK_Reg21: return true;
2272 : case MCK_Reg22: return true;
2273 : case MCK_Reg25: return true;
2274 : case MCK_Reg26: return true;
2275 : case MCK_Reg24: return true;
2276 : case MCK_GPR64: return true;
2277 : }
2278 :
2279 0 : case MCK_Reg31:
2280 : switch (B) {
2281 : default: return false;
2282 : case MCK_Reg27: return true;
2283 : case MCK_Reg21: return true;
2284 : case MCK_Reg25: return true;
2285 : case MCK_Reg26: return true;
2286 : case MCK_Reg24: return true;
2287 : case MCK_GPR64: return true;
2288 : }
2289 :
2290 0 : case MCK_Reg33:
2291 : switch (B) {
2292 : default: return false;
2293 : case MCK_Reg34: return true;
2294 : case MCK_Reg27: return true;
2295 : case MCK_Reg21: return true;
2296 : case MCK_Reg25: return true;
2297 : case MCK_Reg26: return true;
2298 : case MCK_Reg24: return true;
2299 : case MCK_GPR64: return true;
2300 : }
2301 :
2302 0 : case MCK_GPRMM16MovePPairFirst:
2303 : switch (B) {
2304 : default: return false;
2305 : case MCK_Reg8: return true;
2306 : case MCK_CPU16Regs: return true;
2307 : case MCK_GPRMM16Zero: return true;
2308 : case MCK_CPU16RegsPlusSP: return true;
2309 : case MCK_GPR32NONZERO: return true;
2310 : case MCK_DSPR: return true;
2311 : }
2312 :
2313 0 : case MCK_Reg4:
2314 : switch (B) {
2315 : default: return false;
2316 : case MCK_GPRMM16MoveP: return true;
2317 : case MCK_GPRMM16Zero: return true;
2318 : case MCK_DSPR: return true;
2319 : }
2320 :
2321 0 : case MCK_Reg9:
2322 : switch (B) {
2323 : default: return false;
2324 : case MCK_Reg10: return true;
2325 : case MCK_CPU16Regs: return true;
2326 : case MCK_GPRMM16MoveP: return true;
2327 : case MCK_CPU16RegsPlusSP: return true;
2328 : case MCK_GPR32NONZERO: return true;
2329 : case MCK_DSPR: return true;
2330 : }
2331 :
2332 0 : case MCK_Reg23:
2333 0 : switch (B) {
2334 : default: return false;
2335 0 : case MCK_Reg21: return true;
2336 0 : case MCK_Reg22: return true;
2337 0 : case MCK_GPR64: return true;
2338 : }
2339 :
2340 0 : case MCK_Reg28:
2341 : switch (B) {
2342 : default: return false;
2343 : case MCK_Reg29: return true;
2344 : case MCK_Reg22: return true;
2345 : case MCK_Reg25: return true;
2346 : case MCK_Reg26: return true;
2347 : case MCK_Reg24: return true;
2348 : case MCK_GPR64: return true;
2349 : }
2350 :
2351 0 : case MCK_Reg34:
2352 0 : switch (B) {
2353 : default: return false;
2354 0 : case MCK_Reg24: return true;
2355 0 : case MCK_GPR64: return true;
2356 : }
2357 :
2358 0 : case MCK_GPRMM16MovePPairSecond:
2359 0 : switch (B) {
2360 : default: return false;
2361 0 : case MCK_GPR32NONZERO: return true;
2362 0 : case MCK_DSPR: return true;
2363 : }
2364 :
2365 0 : case MCK_Reg8:
2366 : switch (B) {
2367 : default: return false;
2368 : case MCK_CPU16Regs: return true;
2369 : case MCK_GPRMM16Zero: return true;
2370 : case MCK_CPU16RegsPlusSP: return true;
2371 : case MCK_GPR32NONZERO: return true;
2372 : case MCK_DSPR: return true;
2373 : }
2374 :
2375 0 : case MCK_Reg10:
2376 : switch (B) {
2377 : default: return false;
2378 : case MCK_GPRMM16MoveP: return true;
2379 : case MCK_GPR32NONZERO: return true;
2380 : case MCK_DSPR: return true;
2381 : }
2382 :
2383 0 : case MCK_Reg27:
2384 : switch (B) {
2385 : default: return false;
2386 : case MCK_Reg21: return true;
2387 : case MCK_Reg25: return true;
2388 : case MCK_Reg26: return true;
2389 : case MCK_Reg24: return true;
2390 : case MCK_GPR64: return true;
2391 : }
2392 :
2393 0 : case MCK_Reg29:
2394 0 : switch (B) {
2395 : default: return false;
2396 0 : case MCK_Reg22: return true;
2397 0 : case MCK_Reg24: return true;
2398 0 : case MCK_GPR64: return true;
2399 : }
2400 :
2401 0 : case MCK_Reg21:
2402 0 : return B == MCK_GPR64;
2403 :
2404 0 : case MCK_Reg22:
2405 0 : return B == MCK_GPR64;
2406 :
2407 0 : case MCK_Reg25:
2408 : switch (B) {
2409 : default: return false;
2410 : case MCK_Reg26: return true;
2411 : case MCK_Reg24: return true;
2412 : case MCK_GPR64: return true;
2413 : }
2414 :
2415 0 : case MCK_Reg44:
2416 : switch (B) {
2417 : default: return false;
2418 : case MCK_AFGR64: return true;
2419 : case MCK_Reg45: return true;
2420 : case MCK_OddSP: return true;
2421 : }
2422 :
2423 13332 : case MCK_CPU16Regs:
2424 : switch (B) {
2425 : default: return false;
2426 : case MCK_CPU16RegsPlusSP: return true;
2427 : case MCK_GPR32NONZERO: return true;
2428 : case MCK_DSPR: return true;
2429 : }
2430 :
2431 0 : case MCK_GPRMM16MoveP:
2432 0 : return B == MCK_DSPR;
2433 :
2434 0 : case MCK_GPRMM16Zero:
2435 0 : return B == MCK_DSPR;
2436 :
2437 0 : case MCK_Reg26:
2438 0 : switch (B) {
2439 : default: return false;
2440 0 : case MCK_Reg24: return true;
2441 0 : case MCK_GPR64: return true;
2442 : }
2443 :
2444 0 : case MCK_CPU16RegsPlusSP:
2445 0 : switch (B) {
2446 : default: return false;
2447 0 : case MCK_GPR32NONZERO: return true;
2448 0 : case MCK_DSPR: return true;
2449 : }
2450 :
2451 0 : case MCK_Reg39:
2452 0 : switch (B) {
2453 : default: return false;
2454 0 : case MCK_FGR32: return true;
2455 0 : case MCK_OddSP: return true;
2456 : }
2457 :
2458 0 : case MCK_Reg42:
2459 0 : switch (B) {
2460 : default: return false;
2461 0 : case MCK_FGRH32: return true;
2462 0 : case MCK_OddSP: return true;
2463 : }
2464 :
2465 0 : case MCK_Reg47:
2466 : switch (B) {
2467 : default: return false;
2468 : case MCK_Reg45: return true;
2469 : case MCK_FGR64: return true;
2470 : case MCK_OddSP: return true;
2471 : }
2472 :
2473 0 : case MCK_Reg50:
2474 0 : return B == MCK_MSA128F16;
2475 :
2476 0 : case MCK_MSA128WEvens:
2477 0 : return B == MCK_MSA128F16;
2478 :
2479 0 : case MCK_Reg45:
2480 0 : return B == MCK_OddSP;
2481 :
2482 0 : case MCK_Reg24:
2483 0 : return B == MCK_GPR64;
2484 :
2485 0 : case MCK_GPR32NONZERO:
2486 0 : return B == MCK_DSPR;
2487 :
2488 0 : case MCK_MemOffsetSimm10:
2489 0 : return B == MCK_Mem;
2490 :
2491 0 : case MCK_MemOffsetSimm10_1:
2492 0 : return B == MCK_Mem;
2493 :
2494 0 : case MCK_MemOffsetSimm10_2:
2495 0 : return B == MCK_Mem;
2496 :
2497 0 : case MCK_MemOffsetSimm10_3:
2498 0 : return B == MCK_Mem;
2499 :
2500 0 : case MCK_MemOffsetSimm11:
2501 0 : return B == MCK_Mem;
2502 :
2503 0 : case MCK_MemOffsetSimm12:
2504 0 : return B == MCK_Mem;
2505 :
2506 0 : case MCK_MemOffsetSimm16:
2507 0 : return B == MCK_Mem;
2508 :
2509 0 : case MCK_MemOffsetSimm9:
2510 0 : return B == MCK_Mem;
2511 :
2512 0 : case MCK_MemOffsetSimmPtr:
2513 0 : return B == MCK_Mem;
2514 :
2515 8 : case MCK_MemOffsetUimm4:
2516 8 : return B == MCK_Mem;
2517 :
2518 0 : case MCK_ConstantImmz:
2519 : switch (B) {
2520 : default: return false;
2521 : case MCK_ConstantUImm1_0: return true;
2522 : case MCK_ConstantUImm2_0: return true;
2523 : case MCK_ConstantUImm3_0: return true;
2524 : case MCK_ConstantSImm4_0: return true;
2525 : case MCK_ConstantUImm4_0: return true;
2526 : case MCK_ConstantSImm5_0: return true;
2527 : case MCK_ConstantUImm5_0: return true;
2528 : case MCK_ConstantUImm5_1: return true;
2529 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2530 : case MCK_ConstantUImm5_32_Norm: return true;
2531 : case MCK_ConstantUImm5_32: return true;
2532 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2533 : case MCK_ConstantUImm5_33: return true;
2534 : case MCK_ConstantUImmRange2_64: return true;
2535 : case MCK_UImm5Lsl2: return true;
2536 : case MCK_ConstantSImm6_0: return true;
2537 : case MCK_ConstantUImm6_0: return true;
2538 : case MCK_UImm6Lsl2: return true;
2539 : case MCK_ConstantUImm7_0: return true;
2540 : case MCK_UImm7_N1: return true;
2541 : case MCK_ConstantUImm8_0: return true;
2542 : case MCK_SImm7Lsl2: return true;
2543 : case MCK_ConstantSImm9_0: return true;
2544 : case MCK_ConstantSImm10_0: return true;
2545 : case MCK_ConstantUImm10_0: return true;
2546 : case MCK_SImm10Lsl1: return true;
2547 : case MCK_ConstantSImm11_0: return true;
2548 : case MCK_SImm10Lsl2: return true;
2549 : case MCK_SImm10Lsl3: return true;
2550 : case MCK_SImm16: return true;
2551 : case MCK_SImm16_Relaxed: return true;
2552 : case MCK_UImm16_Relaxed: return true;
2553 : case MCK_ConstantUImm20_0: return true;
2554 : case MCK_ConstantUImm26_0: return true;
2555 : case MCK_SImm32: return true;
2556 : case MCK_SImm32_Relaxed: return true;
2557 : case MCK_UImm32_Coerced: return true;
2558 : }
2559 :
2560 0 : case MCK_ConstantUImm1_0:
2561 : switch (B) {
2562 : default: return false;
2563 : case MCK_ConstantUImm2_0: return true;
2564 : case MCK_ConstantUImm3_0: return true;
2565 : case MCK_ConstantSImm4_0: return true;
2566 : case MCK_ConstantUImm4_0: return true;
2567 : case MCK_ConstantSImm5_0: return true;
2568 : case MCK_ConstantUImm5_0: return true;
2569 : case MCK_ConstantUImm5_1: return true;
2570 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2571 : case MCK_ConstantUImm5_32_Norm: return true;
2572 : case MCK_ConstantUImm5_32: return true;
2573 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2574 : case MCK_ConstantUImm5_33: return true;
2575 : case MCK_ConstantUImmRange2_64: return true;
2576 : case MCK_UImm5Lsl2: return true;
2577 : case MCK_ConstantSImm6_0: return true;
2578 : case MCK_ConstantUImm6_0: return true;
2579 : case MCK_UImm6Lsl2: return true;
2580 : case MCK_ConstantUImm7_0: return true;
2581 : case MCK_UImm7_N1: return true;
2582 : case MCK_ConstantUImm8_0: return true;
2583 : case MCK_SImm7Lsl2: return true;
2584 : case MCK_ConstantSImm9_0: return true;
2585 : case MCK_ConstantSImm10_0: return true;
2586 : case MCK_ConstantUImm10_0: return true;
2587 : case MCK_SImm10Lsl1: return true;
2588 : case MCK_ConstantSImm11_0: return true;
2589 : case MCK_SImm10Lsl2: return true;
2590 : case MCK_SImm10Lsl3: return true;
2591 : case MCK_SImm16: return true;
2592 : case MCK_SImm16_Relaxed: return true;
2593 : case MCK_UImm16_Relaxed: return true;
2594 : case MCK_ConstantUImm20_0: return true;
2595 : case MCK_ConstantUImm26_0: return true;
2596 : case MCK_SImm32: return true;
2597 : case MCK_SImm32_Relaxed: return true;
2598 : case MCK_UImm32_Coerced: return true;
2599 : }
2600 :
2601 6 : case MCK_ConstantUImm2_0:
2602 : switch (B) {
2603 : default: return false;
2604 : case MCK_ConstantUImm3_0: return true;
2605 : case MCK_ConstantSImm4_0: return true;
2606 : case MCK_ConstantUImm4_0: return true;
2607 : case MCK_ConstantSImm5_0: return true;
2608 : case MCK_ConstantUImm5_0: return true;
2609 : case MCK_ConstantUImm5_1: return true;
2610 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2611 : case MCK_ConstantUImm5_32_Norm: return true;
2612 : case MCK_ConstantUImm5_32: return true;
2613 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2614 : case MCK_ConstantUImm5_33: return true;
2615 : case MCK_ConstantUImmRange2_64: return true;
2616 : case MCK_UImm5Lsl2: return true;
2617 : case MCK_ConstantSImm6_0: return true;
2618 : case MCK_ConstantUImm6_0: return true;
2619 : case MCK_UImm6Lsl2: return true;
2620 : case MCK_ConstantUImm7_0: return true;
2621 : case MCK_UImm7_N1: return true;
2622 : case MCK_ConstantUImm8_0: return true;
2623 : case MCK_SImm7Lsl2: return true;
2624 : case MCK_ConstantSImm9_0: return true;
2625 : case MCK_ConstantSImm10_0: return true;
2626 : case MCK_ConstantUImm10_0: return true;
2627 : case MCK_SImm10Lsl1: return true;
2628 : case MCK_ConstantSImm11_0: return true;
2629 : case MCK_SImm10Lsl2: return true;
2630 : case MCK_SImm10Lsl3: return true;
2631 : case MCK_SImm16: return true;
2632 : case MCK_SImm16_Relaxed: return true;
2633 : case MCK_UImm16_Relaxed: return true;
2634 : case MCK_ConstantUImm20_0: return true;
2635 : case MCK_ConstantUImm26_0: return true;
2636 : case MCK_SImm32: return true;
2637 : case MCK_SImm32_Relaxed: return true;
2638 : case MCK_UImm32_Coerced: return true;
2639 : }
2640 :
2641 0 : case MCK_ConstantUImm2_1:
2642 : switch (B) {
2643 : default: return false;
2644 : case MCK_ConstantUImm3_0: return true;
2645 : case MCK_ConstantSImm4_0: return true;
2646 : case MCK_ConstantUImm4_0: return true;
2647 : case MCK_ConstantSImm5_0: return true;
2648 : case MCK_ConstantUImm5_0: return true;
2649 : case MCK_ConstantUImm5_1: return true;
2650 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2651 : case MCK_ConstantUImm5_32_Norm: return true;
2652 : case MCK_ConstantUImm5_32: return true;
2653 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2654 : case MCK_ConstantUImm5_33: return true;
2655 : case MCK_ConstantUImmRange2_64: return true;
2656 : case MCK_UImm5Lsl2: return true;
2657 : case MCK_ConstantSImm6_0: return true;
2658 : case MCK_ConstantUImm6_0: return true;
2659 : case MCK_UImm6Lsl2: return true;
2660 : case MCK_ConstantUImm7_0: return true;
2661 : case MCK_UImm7_N1: return true;
2662 : case MCK_ConstantUImm8_0: return true;
2663 : case MCK_SImm7Lsl2: return true;
2664 : case MCK_ConstantSImm9_0: return true;
2665 : case MCK_ConstantSImm10_0: return true;
2666 : case MCK_ConstantUImm10_0: return true;
2667 : case MCK_SImm10Lsl1: return true;
2668 : case MCK_ConstantSImm11_0: return true;
2669 : case MCK_SImm10Lsl2: return true;
2670 : case MCK_SImm10Lsl3: return true;
2671 : case MCK_SImm16: return true;
2672 : case MCK_SImm16_Relaxed: return true;
2673 : case MCK_UImm16_Relaxed: return true;
2674 : case MCK_ConstantUImm20_0: return true;
2675 : case MCK_ConstantUImm26_0: return true;
2676 : case MCK_SImm32: return true;
2677 : case MCK_SImm32_Relaxed: return true;
2678 : case MCK_UImm32_Coerced: return true;
2679 : }
2680 :
2681 0 : case MCK_ConstantUImm3_0:
2682 : switch (B) {
2683 : default: return false;
2684 : case MCK_ConstantSImm4_0: return true;
2685 : case MCK_ConstantUImm4_0: return true;
2686 : case MCK_ConstantSImm5_0: return true;
2687 : case MCK_ConstantUImm5_0: return true;
2688 : case MCK_ConstantUImm5_1: return true;
2689 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2690 : case MCK_ConstantUImm5_32_Norm: return true;
2691 : case MCK_ConstantUImm5_32: return true;
2692 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2693 : case MCK_ConstantUImm5_33: return true;
2694 : case MCK_ConstantUImmRange2_64: return true;
2695 : case MCK_UImm5Lsl2: return true;
2696 : case MCK_ConstantSImm6_0: return true;
2697 : case MCK_ConstantUImm6_0: return true;
2698 : case MCK_UImm6Lsl2: return true;
2699 : case MCK_ConstantUImm7_0: return true;
2700 : case MCK_UImm7_N1: return true;
2701 : case MCK_ConstantUImm8_0: return true;
2702 : case MCK_SImm7Lsl2: return true;
2703 : case MCK_ConstantSImm9_0: return true;
2704 : case MCK_ConstantSImm10_0: return true;
2705 : case MCK_ConstantUImm10_0: return true;
2706 : case MCK_SImm10Lsl1: return true;
2707 : case MCK_ConstantSImm11_0: return true;
2708 : case MCK_SImm10Lsl2: return true;
2709 : case MCK_SImm10Lsl3: return true;
2710 : case MCK_SImm16: return true;
2711 : case MCK_SImm16_Relaxed: return true;
2712 : case MCK_UImm16_Relaxed: return true;
2713 : case MCK_ConstantUImm20_0: return true;
2714 : case MCK_ConstantUImm26_0: return true;
2715 : case MCK_SImm32: return true;
2716 : case MCK_SImm32_Relaxed: return true;
2717 : case MCK_UImm32_Coerced: return true;
2718 : }
2719 :
2720 0 : case MCK_ConstantSImm4_0:
2721 : switch (B) {
2722 : default: return false;
2723 : case MCK_ConstantUImm4_0: return true;
2724 : case MCK_ConstantSImm5_0: return true;
2725 : case MCK_ConstantUImm5_0: return true;
2726 : case MCK_ConstantUImm5_1: return true;
2727 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2728 : case MCK_ConstantUImm5_32_Norm: return true;
2729 : case MCK_ConstantUImm5_32: return true;
2730 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2731 : case MCK_ConstantUImm5_33: return true;
2732 : case MCK_ConstantUImmRange2_64: return true;
2733 : case MCK_UImm5Lsl2: return true;
2734 : case MCK_ConstantSImm6_0: return true;
2735 : case MCK_ConstantUImm6_0: return true;
2736 : case MCK_UImm6Lsl2: return true;
2737 : case MCK_ConstantUImm7_0: return true;
2738 : case MCK_UImm7_N1: return true;
2739 : case MCK_ConstantUImm8_0: return true;
2740 : case MCK_SImm7Lsl2: return true;
2741 : case MCK_ConstantSImm9_0: return true;
2742 : case MCK_ConstantSImm10_0: return true;
2743 : case MCK_ConstantUImm10_0: return true;
2744 : case MCK_SImm10Lsl1: return true;
2745 : case MCK_ConstantSImm11_0: return true;
2746 : case MCK_SImm10Lsl2: return true;
2747 : case MCK_SImm10Lsl3: return true;
2748 : case MCK_SImm16: return true;
2749 : case MCK_SImm16_Relaxed: return true;
2750 : case MCK_UImm16_Relaxed: return true;
2751 : case MCK_ConstantUImm20_0: return true;
2752 : case MCK_ConstantUImm26_0: return true;
2753 : case MCK_SImm32: return true;
2754 : case MCK_SImm32_Relaxed: return true;
2755 : case MCK_UImm32_Coerced: return true;
2756 : }
2757 :
2758 6 : case MCK_ConstantUImm4_0:
2759 : switch (B) {
2760 : default: return false;
2761 : case MCK_ConstantSImm5_0: return true;
2762 : case MCK_ConstantUImm5_0: return true;
2763 : case MCK_ConstantUImm5_1: return true;
2764 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2765 : case MCK_ConstantUImm5_32_Norm: return true;
2766 : case MCK_ConstantUImm5_32: return true;
2767 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2768 : case MCK_ConstantUImm5_33: return true;
2769 : case MCK_ConstantUImmRange2_64: return true;
2770 : case MCK_UImm5Lsl2: return true;
2771 : case MCK_ConstantSImm6_0: return true;
2772 : case MCK_ConstantUImm6_0: return true;
2773 : case MCK_UImm6Lsl2: return true;
2774 : case MCK_ConstantUImm7_0: return true;
2775 : case MCK_UImm7_N1: return true;
2776 : case MCK_ConstantUImm8_0: return true;
2777 : case MCK_SImm7Lsl2: return true;
2778 : case MCK_ConstantSImm9_0: return true;
2779 : case MCK_ConstantSImm10_0: return true;
2780 : case MCK_ConstantUImm10_0: return true;
2781 : case MCK_SImm10Lsl1: return true;
2782 : case MCK_ConstantSImm11_0: return true;
2783 : case MCK_SImm10Lsl2: return true;
2784 : case MCK_SImm10Lsl3: return true;
2785 : case MCK_SImm16: return true;
2786 : case MCK_SImm16_Relaxed: return true;
2787 : case MCK_UImm16_Relaxed: return true;
2788 : case MCK_ConstantUImm20_0: return true;
2789 : case MCK_ConstantUImm26_0: return true;
2790 : case MCK_SImm32: return true;
2791 : case MCK_SImm32_Relaxed: return true;
2792 : case MCK_UImm32_Coerced: return true;
2793 : }
2794 :
2795 0 : case MCK_ConstantSImm5_0:
2796 : switch (B) {
2797 : default: return false;
2798 : case MCK_ConstantUImm5_0: return true;
2799 : case MCK_ConstantUImm5_1: return true;
2800 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2801 : case MCK_ConstantUImm5_32_Norm: return true;
2802 : case MCK_ConstantUImm5_32: return true;
2803 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2804 : case MCK_ConstantUImm5_33: return true;
2805 : case MCK_ConstantUImmRange2_64: return true;
2806 : case MCK_UImm5Lsl2: return true;
2807 : case MCK_ConstantSImm6_0: return true;
2808 : case MCK_ConstantUImm6_0: return true;
2809 : case MCK_UImm6Lsl2: return true;
2810 : case MCK_ConstantUImm7_0: return true;
2811 : case MCK_UImm7_N1: return true;
2812 : case MCK_ConstantUImm8_0: return true;
2813 : case MCK_SImm7Lsl2: return true;
2814 : case MCK_ConstantSImm9_0: return true;
2815 : case MCK_ConstantSImm10_0: return true;
2816 : case MCK_ConstantUImm10_0: return true;
2817 : case MCK_SImm10Lsl1: return true;
2818 : case MCK_ConstantSImm11_0: return true;
2819 : case MCK_SImm10Lsl2: return true;
2820 : case MCK_SImm10Lsl3: return true;
2821 : case MCK_SImm16: return true;
2822 : case MCK_SImm16_Relaxed: return true;
2823 : case MCK_UImm16_Relaxed: return true;
2824 : case MCK_ConstantUImm20_0: return true;
2825 : case MCK_ConstantUImm26_0: return true;
2826 : case MCK_SImm32: return true;
2827 : case MCK_SImm32_Relaxed: return true;
2828 : case MCK_UImm32_Coerced: return true;
2829 : }
2830 :
2831 3 : case MCK_ConstantUImm5_0:
2832 : switch (B) {
2833 : default: return false;
2834 : case MCK_ConstantUImm5_1: return true;
2835 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2836 : case MCK_ConstantUImm5_32_Norm: return true;
2837 : case MCK_ConstantUImm5_32: return true;
2838 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2839 : case MCK_ConstantUImm5_33: return true;
2840 : case MCK_ConstantUImmRange2_64: return true;
2841 : case MCK_UImm5Lsl2: return true;
2842 : case MCK_ConstantSImm6_0: return true;
2843 : case MCK_ConstantUImm6_0: return true;
2844 : case MCK_UImm6Lsl2: return true;
2845 : case MCK_ConstantUImm7_0: return true;
2846 : case MCK_UImm7_N1: return true;
2847 : case MCK_ConstantUImm8_0: return true;
2848 : case MCK_SImm7Lsl2: return true;
2849 : case MCK_ConstantSImm9_0: return true;
2850 : case MCK_ConstantSImm10_0: return true;
2851 : case MCK_ConstantUImm10_0: return true;
2852 : case MCK_SImm10Lsl1: return true;
2853 : case MCK_ConstantSImm11_0: return true;
2854 : case MCK_SImm10Lsl2: return true;
2855 : case MCK_SImm10Lsl3: return true;
2856 : case MCK_SImm16: return true;
2857 : case MCK_SImm16_Relaxed: return true;
2858 : case MCK_UImm16_Relaxed: return true;
2859 : case MCK_ConstantUImm20_0: return true;
2860 : case MCK_ConstantUImm26_0: return true;
2861 : case MCK_SImm32: return true;
2862 : case MCK_SImm32_Relaxed: return true;
2863 : case MCK_UImm32_Coerced: return true;
2864 : }
2865 :
2866 0 : case MCK_ConstantUImm5_1:
2867 : switch (B) {
2868 : default: return false;
2869 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2870 : case MCK_ConstantUImm5_32_Norm: return true;
2871 : case MCK_ConstantUImm5_32: return true;
2872 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2873 : case MCK_ConstantUImm5_33: return true;
2874 : case MCK_ConstantUImmRange2_64: return true;
2875 : case MCK_UImm5Lsl2: return true;
2876 : case MCK_ConstantSImm6_0: return true;
2877 : case MCK_ConstantUImm6_0: return true;
2878 : case MCK_UImm6Lsl2: return true;
2879 : case MCK_ConstantUImm7_0: return true;
2880 : case MCK_UImm7_N1: return true;
2881 : case MCK_ConstantUImm8_0: return true;
2882 : case MCK_SImm7Lsl2: return true;
2883 : case MCK_ConstantSImm9_0: return true;
2884 : case MCK_ConstantSImm10_0: return true;
2885 : case MCK_ConstantUImm10_0: return true;
2886 : case MCK_SImm10Lsl1: return true;
2887 : case MCK_ConstantSImm11_0: return true;
2888 : case MCK_SImm10Lsl2: return true;
2889 : case MCK_SImm10Lsl3: return true;
2890 : case MCK_SImm16: return true;
2891 : case MCK_SImm16_Relaxed: return true;
2892 : case MCK_UImm16_Relaxed: return true;
2893 : case MCK_ConstantUImm20_0: return true;
2894 : case MCK_ConstantUImm26_0: return true;
2895 : case MCK_SImm32: return true;
2896 : case MCK_SImm32_Relaxed: return true;
2897 : case MCK_UImm32_Coerced: return true;
2898 : }
2899 :
2900 0 : case MCK_ConstantUImm5_Plus1_Report_UImm6:
2901 : switch (B) {
2902 : default: return false;
2903 : case MCK_ConstantUImm5_32_Norm: return true;
2904 : case MCK_ConstantUImm5_32: return true;
2905 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2906 : case MCK_ConstantUImm5_33: return true;
2907 : case MCK_ConstantUImmRange2_64: return true;
2908 : case MCK_UImm5Lsl2: return true;
2909 : case MCK_ConstantSImm6_0: return true;
2910 : case MCK_ConstantUImm6_0: return true;
2911 : case MCK_UImm6Lsl2: return true;
2912 : case MCK_ConstantUImm7_0: return true;
2913 : case MCK_UImm7_N1: return true;
2914 : case MCK_ConstantUImm8_0: return true;
2915 : case MCK_SImm7Lsl2: return true;
2916 : case MCK_ConstantSImm9_0: return true;
2917 : case MCK_ConstantSImm10_0: return true;
2918 : case MCK_ConstantUImm10_0: return true;
2919 : case MCK_SImm10Lsl1: return true;
2920 : case MCK_ConstantSImm11_0: return true;
2921 : case MCK_SImm10Lsl2: return true;
2922 : case MCK_SImm10Lsl3: return true;
2923 : case MCK_SImm16: return true;
2924 : case MCK_SImm16_Relaxed: return true;
2925 : case MCK_UImm16_Relaxed: return true;
2926 : case MCK_ConstantUImm20_0: return true;
2927 : case MCK_ConstantUImm26_0: return true;
2928 : case MCK_SImm32: return true;
2929 : case MCK_SImm32_Relaxed: return true;
2930 : case MCK_UImm32_Coerced: return true;
2931 : }
2932 :
2933 0 : case MCK_ConstantUImm5_32_Norm:
2934 : switch (B) {
2935 : default: return false;
2936 : case MCK_ConstantUImm5_32: return true;
2937 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2938 : case MCK_ConstantUImm5_33: return true;
2939 : case MCK_ConstantUImmRange2_64: return true;
2940 : case MCK_UImm5Lsl2: return true;
2941 : case MCK_ConstantSImm6_0: return true;
2942 : case MCK_ConstantUImm6_0: return true;
2943 : case MCK_UImm6Lsl2: return true;
2944 : case MCK_ConstantUImm7_0: return true;
2945 : case MCK_UImm7_N1: return true;
2946 : case MCK_ConstantUImm8_0: return true;
2947 : case MCK_SImm7Lsl2: return true;
2948 : case MCK_ConstantSImm9_0: return true;
2949 : case MCK_ConstantSImm10_0: return true;
2950 : case MCK_ConstantUImm10_0: return true;
2951 : case MCK_SImm10Lsl1: return true;
2952 : case MCK_ConstantSImm11_0: return true;
2953 : case MCK_SImm10Lsl2: return true;
2954 : case MCK_SImm10Lsl3: return true;
2955 : case MCK_SImm16: return true;
2956 : case MCK_SImm16_Relaxed: return true;
2957 : case MCK_UImm16_Relaxed: return true;
2958 : case MCK_ConstantUImm20_0: return true;
2959 : case MCK_ConstantUImm26_0: return true;
2960 : case MCK_SImm32: return true;
2961 : case MCK_SImm32_Relaxed: return true;
2962 : case MCK_UImm32_Coerced: return true;
2963 : }
2964 :
2965 0 : case MCK_ConstantUImm5_32:
2966 : switch (B) {
2967 : default: return false;
2968 : case MCK_ConstantUImm5_0_Report_UImm6: return true;
2969 : case MCK_ConstantUImm5_33: return true;
2970 : case MCK_ConstantUImmRange2_64: return true;
2971 : case MCK_UImm5Lsl2: return true;
2972 : case MCK_ConstantSImm6_0: return true;
2973 : case MCK_ConstantUImm6_0: return true;
2974 : case MCK_UImm6Lsl2: return true;
2975 : case MCK_ConstantUImm7_0: return true;
2976 : case MCK_UImm7_N1: return true;
2977 : case MCK_ConstantUImm8_0: return true;
2978 : case MCK_SImm7Lsl2: return true;
2979 : case MCK_ConstantSImm9_0: return true;
2980 : case MCK_ConstantSImm10_0: return true;
2981 : case MCK_ConstantUImm10_0: return true;
2982 : case MCK_SImm10Lsl1: return true;
2983 : case MCK_ConstantSImm11_0: return true;
2984 : case MCK_SImm10Lsl2: return true;
2985 : case MCK_SImm10Lsl3: return true;
2986 : case MCK_SImm16: return true;
2987 : case MCK_SImm16_Relaxed: return true;
2988 : case MCK_UImm16_Relaxed: return true;
2989 : case MCK_ConstantUImm20_0: return true;
2990 : case MCK_ConstantUImm26_0: return true;
2991 : case MCK_SImm32: return true;
2992 : case MCK_SImm32_Relaxed: return true;
2993 : case MCK_UImm32_Coerced: return true;
2994 : }
2995 :
2996 0 : case MCK_ConstantUImm5_0_Report_UImm6:
2997 : switch (B) {
2998 : default: return false;
2999 : case MCK_ConstantUImm5_33: return true;
3000 : case MCK_ConstantUImmRange2_64: return true;
3001 : case MCK_UImm5Lsl2: return true;
3002 : case MCK_ConstantSImm6_0: return true;
3003 : case MCK_ConstantUImm6_0: return true;
3004 : case MCK_UImm6Lsl2: return true;
3005 : case MCK_ConstantUImm7_0: return true;
3006 : case MCK_UImm7_N1: return true;
3007 : case MCK_ConstantUImm8_0: return true;
3008 : case MCK_SImm7Lsl2: return true;
3009 : case MCK_ConstantSImm9_0: return true;
3010 : case MCK_ConstantSImm10_0: return true;
3011 : case MCK_ConstantUImm10_0: return true;
3012 : case MCK_SImm10Lsl1: return true;
3013 : case MCK_ConstantSImm11_0: return true;
3014 : case MCK_SImm10Lsl2: return true;
3015 : case MCK_SImm10Lsl3: return true;
3016 : case MCK_SImm16: return true;
3017 : case MCK_SImm16_Relaxed: return true;
3018 : case MCK_UImm16_Relaxed: return true;
3019 : case MCK_ConstantUImm20_0: return true;
3020 : case MCK_ConstantUImm26_0: return true;
3021 : case MCK_SImm32: return true;
3022 : case MCK_SImm32_Relaxed: return true;
3023 : case MCK_UImm32_Coerced: return true;
3024 : }
3025 :
3026 0 : case MCK_ConstantUImm5_33:
3027 : switch (B) {
3028 : default: return false;
3029 : case MCK_ConstantUImmRange2_64: return true;
3030 : case MCK_UImm5Lsl2: return true;
3031 : case MCK_ConstantSImm6_0: return true;
3032 : case MCK_ConstantUImm6_0: return true;
3033 : case MCK_UImm6Lsl2: return true;
3034 : case MCK_ConstantUImm7_0: return true;
3035 : case MCK_UImm7_N1: return true;
3036 : case MCK_ConstantUImm8_0: return true;
3037 : case MCK_SImm7Lsl2: return true;
3038 : case MCK_ConstantSImm9_0: return true;
3039 : case MCK_ConstantSImm10_0: return true;
3040 : case MCK_ConstantUImm10_0: return true;
3041 : case MCK_SImm10Lsl1: return true;
3042 : case MCK_ConstantSImm11_0: return true;
3043 : case MCK_SImm10Lsl2: return true;
3044 : case MCK_SImm10Lsl3: return true;
3045 : case MCK_SImm16: return true;
3046 : case MCK_SImm16_Relaxed: return true;
3047 : case MCK_UImm16_Relaxed: return true;
3048 : case MCK_ConstantUImm20_0: return true;
3049 : case MCK_ConstantUImm26_0: return true;
3050 : case MCK_SImm32: return true;
3051 : case MCK_SImm32_Relaxed: return true;
3052 : case MCK_UImm32_Coerced: return true;
3053 : }
3054 :
3055 0 : case MCK_ConstantUImmRange2_64:
3056 : switch (B) {
3057 : default: return false;
3058 : case MCK_UImm5Lsl2: return true;
3059 : case MCK_ConstantSImm6_0: return true;
3060 : case MCK_ConstantUImm6_0: return true;
3061 : case MCK_UImm6Lsl2: return true;
3062 : case MCK_ConstantUImm7_0: return true;
3063 : case MCK_UImm7_N1: return true;
3064 : case MCK_ConstantUImm8_0: return true;
3065 : case MCK_SImm7Lsl2: return true;
3066 : case MCK_ConstantSImm9_0: return true;
3067 : case MCK_ConstantSImm10_0: return true;
3068 : case MCK_ConstantUImm10_0: return true;
3069 : case MCK_SImm10Lsl1: return true;
3070 : case MCK_ConstantSImm11_0: return true;
3071 : case MCK_SImm10Lsl2: return true;
3072 : case MCK_SImm10Lsl3: return true;
3073 : case MCK_SImm16: return true;
3074 : case MCK_SImm16_Relaxed: return true;
3075 : case MCK_UImm16_Relaxed: return true;
3076 : case MCK_ConstantUImm20_0: return true;
3077 : case MCK_ConstantUImm26_0: return true;
3078 : case MCK_SImm32: return true;
3079 : case MCK_SImm32_Relaxed: return true;
3080 : case MCK_UImm32_Coerced: return true;
3081 : }
3082 :
3083 0 : case MCK_UImm5Lsl2:
3084 : switch (B) {
3085 : default: return false;
3086 : case MCK_ConstantSImm6_0: return true;
3087 : case MCK_ConstantUImm6_0: return true;
3088 : case MCK_UImm6Lsl2: return true;
3089 : case MCK_ConstantUImm7_0: return true;
3090 : case MCK_UImm7_N1: return true;
3091 : case MCK_ConstantUImm8_0: return true;
3092 : case MCK_SImm7Lsl2: return true;
3093 : case MCK_ConstantSImm9_0: return true;
3094 : case MCK_ConstantSImm10_0: return true;
3095 : case MCK_ConstantUImm10_0: return true;
3096 : case MCK_SImm10Lsl1: return true;
3097 : case MCK_ConstantSImm11_0: return true;
3098 : case MCK_SImm10Lsl2: return true;
3099 : case MCK_SImm10Lsl3: return true;
3100 : case MCK_SImm16: return true;
3101 : case MCK_SImm16_Relaxed: return true;
3102 : case MCK_UImm16_Relaxed: return true;
3103 : case MCK_ConstantUImm20_0: return true;
3104 : case MCK_ConstantUImm26_0: return true;
3105 : case MCK_SImm32: return true;
3106 : case MCK_SImm32_Relaxed: return true;
3107 : case MCK_UImm32_Coerced: return true;
3108 : }
3109 :
3110 0 : case MCK_ConstantSImm6_0:
3111 : switch (B) {
3112 : default: return false;
3113 : case MCK_ConstantUImm6_0: return true;
3114 : case MCK_UImm6Lsl2: return true;
3115 : case MCK_ConstantUImm7_0: return true;
3116 : case MCK_UImm7_N1: return true;
3117 : case MCK_ConstantUImm8_0: return true;
3118 : case MCK_SImm7Lsl2: return true;
3119 : case MCK_ConstantSImm9_0: return true;
3120 : case MCK_ConstantSImm10_0: return true;
3121 : case MCK_ConstantUImm10_0: return true;
3122 : case MCK_SImm10Lsl1: return true;
3123 : case MCK_ConstantSImm11_0: return true;
3124 : case MCK_SImm10Lsl2: return true;
3125 : case MCK_SImm10Lsl3: return true;
3126 : case MCK_SImm16: return true;
3127 : case MCK_SImm16_Relaxed: return true;
3128 : case MCK_UImm16_Relaxed: return true;
3129 : case MCK_ConstantUImm20_0: return true;
3130 : case MCK_ConstantUImm26_0: return true;
3131 : case MCK_SImm32: return true;
3132 : case MCK_SImm32_Relaxed: return true;
3133 : case MCK_UImm32_Coerced: return true;
3134 : }
3135 :
3136 0 : case MCK_ConstantUImm6_0:
3137 : switch (B) {
3138 : default: return false;
3139 : case MCK_UImm6Lsl2: return true;
3140 : case MCK_ConstantUImm7_0: return true;
3141 : case MCK_UImm7_N1: return true;
3142 : case MCK_ConstantUImm8_0: return true;
3143 : case MCK_SImm7Lsl2: return true;
3144 : case MCK_ConstantSImm9_0: return true;
3145 : case MCK_ConstantSImm10_0: return true;
3146 : case MCK_ConstantUImm10_0: return true;
3147 : case MCK_SImm10Lsl1: return true;
3148 : case MCK_ConstantSImm11_0: return true;
3149 : case MCK_SImm10Lsl2: return true;
3150 : case MCK_SImm10Lsl3: return true;
3151 : case MCK_SImm16: return true;
3152 : case MCK_SImm16_Relaxed: return true;
3153 : case MCK_UImm16_Relaxed: return true;
3154 : case MCK_ConstantUImm20_0: return true;
3155 : case MCK_ConstantUImm26_0: return true;
3156 : case MCK_SImm32: return true;
3157 : case MCK_SImm32_Relaxed: return true;
3158 : case MCK_UImm32_Coerced: return true;
3159 : }
3160 :
3161 0 : case MCK_UImm6Lsl2:
3162 : switch (B) {
3163 : default: return false;
3164 : case MCK_ConstantUImm7_0: return true;
3165 : case MCK_UImm7_N1: return true;
3166 : case MCK_ConstantUImm8_0: return true;
3167 : case MCK_SImm7Lsl2: return true;
3168 : case MCK_ConstantSImm9_0: return true;
3169 : case MCK_ConstantSImm10_0: return true;
3170 : case MCK_ConstantUImm10_0: return true;
3171 : case MCK_SImm10Lsl1: return true;
3172 : case MCK_ConstantSImm11_0: return true;
3173 : case MCK_SImm10Lsl2: return true;
3174 : case MCK_SImm10Lsl3: return true;
3175 : case MCK_SImm16: return true;
3176 : case MCK_SImm16_Relaxed: return true;
3177 : case MCK_UImm16_Relaxed: return true;
3178 : case MCK_ConstantUImm20_0: return true;
3179 : case MCK_ConstantUImm26_0: return true;
3180 : case MCK_SImm32: return true;
3181 : case MCK_SImm32_Relaxed: return true;
3182 : case MCK_UImm32_Coerced: return true;
3183 : }
3184 :
3185 0 : case MCK_ConstantUImm7_0:
3186 : switch (B) {
3187 : default: return false;
3188 : case MCK_UImm7_N1: return true;
3189 : case MCK_ConstantUImm8_0: return true;
3190 : case MCK_SImm7Lsl2: return true;
3191 : case MCK_ConstantSImm9_0: return true;
3192 : case MCK_ConstantSImm10_0: return true;
3193 : case MCK_ConstantUImm10_0: return true;
3194 : case MCK_SImm10Lsl1: return true;
3195 : case MCK_ConstantSImm11_0: return true;
3196 : case MCK_SImm10Lsl2: return true;
3197 : case MCK_SImm10Lsl3: return true;
3198 : case MCK_SImm16: return true;
3199 : case MCK_SImm16_Relaxed: return true;
3200 : case MCK_UImm16_Relaxed: return true;
3201 : case MCK_ConstantUImm20_0: return true;
3202 : case MCK_ConstantUImm26_0: return true;
3203 : case MCK_SImm32: return true;
3204 : case MCK_SImm32_Relaxed: return true;
3205 : case MCK_UImm32_Coerced: return true;
3206 : }
3207 :
3208 0 : case MCK_UImm7_N1:
3209 : switch (B) {
3210 : default: return false;
3211 : case MCK_ConstantUImm8_0: return true;
3212 : case MCK_SImm7Lsl2: return true;
3213 : case MCK_ConstantSImm9_0: return true;
3214 : case MCK_ConstantSImm10_0: return true;
3215 : case MCK_ConstantUImm10_0: return true;
3216 : case MCK_SImm10Lsl1: return true;
3217 : case MCK_ConstantSImm11_0: return true;
3218 : case MCK_SImm10Lsl2: return true;
3219 : case MCK_SImm10Lsl3: return true;
3220 : case MCK_SImm16: return true;
3221 : case MCK_SImm16_Relaxed: return true;
3222 : case MCK_UImm16_Relaxed: return true;
3223 : case MCK_ConstantUImm20_0: return true;
3224 : case MCK_ConstantUImm26_0: return true;
3225 : case MCK_SImm32: return true;
3226 : case MCK_SImm32_Relaxed: return true;
3227 : case MCK_UImm32_Coerced: return true;
3228 : }
3229 :
3230 0 : case MCK_ConstantUImm8_0:
3231 : switch (B) {
3232 : default: return false;
3233 : case MCK_SImm7Lsl2: return true;
3234 : case MCK_ConstantSImm9_0: return true;
3235 : case MCK_ConstantSImm10_0: return true;
3236 : case MCK_ConstantUImm10_0: return true;
3237 : case MCK_SImm10Lsl1: return true;
3238 : case MCK_ConstantSImm11_0: return true;
3239 : case MCK_SImm10Lsl2: return true;
3240 : case MCK_SImm10Lsl3: return true;
3241 : case MCK_SImm16: return true;
3242 : case MCK_SImm16_Relaxed: return true;
3243 : case MCK_UImm16_Relaxed: return true;
3244 : case MCK_ConstantUImm20_0: return true;
3245 : case MCK_ConstantUImm26_0: return true;
3246 : case MCK_SImm32: return true;
3247 : case MCK_SImm32_Relaxed: return true;
3248 : case MCK_UImm32_Coerced: return true;
3249 : }
3250 :
3251 0 : case MCK_SImm7Lsl2:
3252 : switch (B) {
3253 : default: return false;
3254 : case MCK_ConstantSImm9_0: return true;
3255 : case MCK_ConstantSImm10_0: return true;
3256 : case MCK_ConstantUImm10_0: return true;
3257 : case MCK_SImm10Lsl1: return true;
3258 : case MCK_ConstantSImm11_0: return true;
3259 : case MCK_SImm10Lsl2: return true;
3260 : case MCK_SImm10Lsl3: return true;
3261 : case MCK_SImm16: return true;
3262 : case MCK_SImm16_Relaxed: return true;
3263 : case MCK_UImm16_Relaxed: return true;
3264 : case MCK_ConstantUImm20_0: return true;
3265 : case MCK_ConstantUImm26_0: return true;
3266 : case MCK_SImm32: return true;
3267 : case MCK_SImm32_Relaxed: return true;
3268 : case MCK_UImm32_Coerced: return true;
3269 : }
3270 :
3271 0 : case MCK_ConstantSImm9_0:
3272 : switch (B) {
3273 : default: return false;
3274 : case MCK_ConstantSImm10_0: return true;
3275 : case MCK_ConstantUImm10_0: return true;
3276 : case MCK_SImm10Lsl1: return true;
3277 : case MCK_ConstantSImm11_0: return true;
3278 : case MCK_SImm10Lsl2: return true;
3279 : case MCK_SImm10Lsl3: return true;
3280 : case MCK_SImm16: return true;
3281 : case MCK_SImm16_Relaxed: return true;
3282 : case MCK_UImm16_Relaxed: return true;
3283 : case MCK_ConstantUImm20_0: return true;
3284 : case MCK_ConstantUImm26_0: return true;
3285 : case MCK_SImm32: return true;
3286 : case MCK_SImm32_Relaxed: return true;
3287 : case MCK_UImm32_Coerced: return true;
3288 : }
3289 :
3290 0 : case MCK_ConstantSImm10_0:
3291 : switch (B) {
3292 : default: return false;
3293 : case MCK_ConstantUImm10_0: return true;
3294 : case MCK_SImm10Lsl1: return true;
3295 : case MCK_ConstantSImm11_0: return true;
3296 : case MCK_SImm10Lsl2: return true;
3297 : case MCK_SImm10Lsl3: return true;
3298 : case MCK_SImm16: return true;
3299 : case MCK_SImm16_Relaxed: return true;
3300 : case MCK_UImm16_Relaxed: return true;
3301 : case MCK_ConstantUImm20_0: return true;
3302 : case MCK_ConstantUImm26_0: return true;
3303 : case MCK_SImm32: return true;
3304 : case MCK_SImm32_Relaxed: return true;
3305 : case MCK_UImm32_Coerced: return true;
3306 : }
3307 :
3308 10 : case MCK_ConstantUImm10_0:
3309 : switch (B) {
3310 : default: return false;
3311 : case MCK_SImm10Lsl1: return true;
3312 : case MCK_ConstantSImm11_0: return true;
3313 : case MCK_SImm10Lsl2: return true;
3314 : case MCK_SImm10Lsl3: return true;
3315 : case MCK_SImm16: return true;
3316 : case MCK_SImm16_Relaxed: return true;
3317 : case MCK_UImm16_Relaxed: return true;
3318 : case MCK_ConstantUImm20_0: return true;
3319 : case MCK_ConstantUImm26_0: return true;
3320 : case MCK_SImm32: return true;
3321 : case MCK_SImm32_Relaxed: return true;
3322 : case MCK_UImm32_Coerced: return true;
3323 : }
3324 :
3325 0 : case MCK_SImm10Lsl1:
3326 : switch (B) {
3327 : default: return false;
3328 : case MCK_ConstantSImm11_0: return true;
3329 : case MCK_SImm10Lsl2: return true;
3330 : case MCK_SImm10Lsl3: return true;
3331 : case MCK_SImm16: return true;
3332 : case MCK_SImm16_Relaxed: return true;
3333 : case MCK_UImm16_Relaxed: return true;
3334 : case MCK_ConstantUImm20_0: return true;
3335 : case MCK_ConstantUImm26_0: return true;
3336 : case MCK_SImm32: return true;
3337 : case MCK_SImm32_Relaxed: return true;
3338 : case MCK_UImm32_Coerced: return true;
3339 : }
3340 :
3341 0 : case MCK_ConstantSImm11_0:
3342 : switch (B) {
3343 : default: return false;
3344 : case MCK_SImm10Lsl2: return true;
3345 : case MCK_SImm10Lsl3: return true;
3346 : case MCK_SImm16: return true;
3347 : case MCK_SImm16_Relaxed: return true;
3348 : case MCK_UImm16_Relaxed: return true;
3349 : case MCK_ConstantUImm20_0: return true;
3350 : case MCK_ConstantUImm26_0: return true;
3351 : case MCK_SImm32: return true;
3352 : case MCK_SImm32_Relaxed: return true;
3353 : case MCK_UImm32_Coerced: return true;
3354 : }
3355 :
3356 0 : case MCK_SImm10Lsl2:
3357 : switch (B) {
3358 : default: return false;
3359 : case MCK_SImm10Lsl3: return true;
3360 : case MCK_SImm16: return true;
3361 : case MCK_SImm16_Relaxed: return true;
3362 : case MCK_UImm16_Relaxed: return true;
3363 : case MCK_ConstantUImm20_0: return true;
3364 : case MCK_ConstantUImm26_0: return true;
3365 : case MCK_SImm32: return true;
3366 : case MCK_SImm32_Relaxed: return true;
3367 : case MCK_UImm32_Coerced: return true;
3368 : }
3369 :
3370 0 : case MCK_SImm10Lsl3:
3371 : switch (B) {
3372 : default: return false;
3373 : case MCK_SImm16: return true;
3374 : case MCK_SImm16_Relaxed: return true;
3375 : case MCK_UImm16_Relaxed: return true;
3376 : case MCK_ConstantUImm20_0: return true;
3377 : case MCK_ConstantUImm26_0: return true;
3378 : case MCK_SImm32: return true;
3379 : case MCK_SImm32_Relaxed: return true;
3380 : case MCK_UImm32_Coerced: return true;
3381 : }
3382 :
3383 10 : case MCK_SImm16:
3384 : switch (B) {
3385 : default: return false;
3386 : case MCK_SImm16_Relaxed: return true;
3387 : case MCK_UImm16_Relaxed: return true;
3388 : case MCK_ConstantUImm20_0: return true;
3389 : case MCK_ConstantUImm26_0: return true;
3390 : case MCK_SImm32: return true;
3391 : case MCK_SImm32_Relaxed: return true;
3392 : case MCK_UImm32_Coerced: return true;
3393 : }
3394 :
3395 0 : case MCK_SImm16_Relaxed:
3396 : switch (B) {
3397 : default: return false;
3398 : case MCK_UImm16_Relaxed: return true;
3399 : case MCK_ConstantUImm20_0: return true;
3400 : case MCK_ConstantUImm26_0: return true;
3401 : case MCK_SImm32: return true;
3402 : case MCK_SImm32_Relaxed: return true;
3403 : case MCK_UImm32_Coerced: return true;
3404 : }
3405 :
3406 0 : case MCK_UImm16_AltRelaxed:
3407 : switch (B) {
3408 : default: return false;
3409 : case MCK_UImm16_Relaxed: return true;
3410 : case MCK_ConstantUImm20_0: return true;
3411 : case MCK_ConstantUImm26_0: return true;
3412 : case MCK_SImm32: return true;
3413 : case MCK_SImm32_Relaxed: return true;
3414 : case MCK_UImm32_Coerced: return true;
3415 : }
3416 :
3417 0 : case MCK_UImm16:
3418 : switch (B) {
3419 : default: return false;
3420 : case MCK_UImm16_Relaxed: return true;
3421 : case MCK_ConstantUImm20_0: return true;
3422 : case MCK_ConstantUImm26_0: return true;
3423 : case MCK_SImm32: return true;
3424 : case MCK_SImm32_Relaxed: return true;
3425 : case MCK_UImm32_Coerced: return true;
3426 : }
3427 :
3428 0 : case MCK_SImm19Lsl2:
3429 : switch (B) {
3430 : default: return false;
3431 : case MCK_ConstantUImm20_0: return true;
3432 : case MCK_ConstantUImm26_0: return true;
3433 : case MCK_SImm32: return true;
3434 : case MCK_SImm32_Relaxed: return true;
3435 : case MCK_UImm32_Coerced: return true;
3436 : }
3437 :
3438 0 : case MCK_UImm16_Relaxed:
3439 : switch (B) {
3440 : default: return false;
3441 : case MCK_ConstantUImm20_0: return true;
3442 : case MCK_ConstantUImm26_0: return true;
3443 : case MCK_SImm32: return true;
3444 : case MCK_SImm32_Relaxed: return true;
3445 : case MCK_UImm32_Coerced: return true;
3446 : }
3447 :
3448 0 : case MCK_ConstantUImm20_0:
3449 : switch (B) {
3450 : default: return false;
3451 : case MCK_ConstantUImm26_0: return true;
3452 : case MCK_SImm32: return true;
3453 : case MCK_SImm32_Relaxed: return true;
3454 : case MCK_UImm32_Coerced: return true;
3455 : }
3456 :
3457 0 : case MCK_ConstantUImm26_0:
3458 : switch (B) {
3459 : default: return false;
3460 : case MCK_SImm32: return true;
3461 : case MCK_SImm32_Relaxed: return true;
3462 : case MCK_UImm32_Coerced: return true;
3463 : }
3464 :
3465 0 : case MCK_SImm32:
3466 0 : switch (B) {
3467 : default: return false;
3468 0 : case MCK_SImm32_Relaxed: return true;
3469 0 : case MCK_UImm32_Coerced: return true;
3470 : }
3471 :
3472 0 : case MCK_SImm32_Relaxed:
3473 0 : return B == MCK_UImm32_Coerced;
3474 : }
3475 : }
3476 :
3477 162934 : static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
3478 : MipsOperand &Operand = (MipsOperand&)GOp;
3479 162934 : if (Kind == InvalidMatchClass)
3480 : return MCTargetAsmParser::Match_InvalidOperand;
3481 :
3482 157867 : if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
3483 1760 : return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3484 : MCTargetAsmParser::Match_Success :
3485 : MCTargetAsmParser::Match_InvalidOperand;
3486 :
3487 156987 : switch (Kind) {
3488 : default: break;
3489 : // 'ACC64DSPAsmReg' class
3490 : case MCK_ACC64DSPAsmReg: {
3491 : DiagnosticPredicate DP(Operand.isACCAsmReg());
3492 571 : if (DP.isMatch())
3493 : return MCTargetAsmParser::Match_Success;
3494 : break;
3495 : }
3496 : // 'AFGR64AsmReg' class
3497 : case MCK_AFGR64AsmReg: {
3498 : DiagnosticPredicate DP(Operand.isFGRAsmReg());
3499 4716 : if (DP.isMatch())
3500 : return MCTargetAsmParser::Match_Success;
3501 : break;
3502 : }
3503 : // 'CCRAsmReg' class
3504 : case MCK_CCRAsmReg: {
3505 : DiagnosticPredicate DP(Operand.isCCRAsmReg());
3506 46 : if (DP.isMatch())
3507 : return MCTargetAsmParser::Match_Success;
3508 : break;
3509 : }
3510 : // 'COP0AsmReg' class
3511 : case MCK_COP0AsmReg: {
3512 : DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3513 680 : if (DP.isMatch())
3514 : return MCTargetAsmParser::Match_Success;
3515 : break;
3516 : }
3517 : // 'COP2AsmReg' class
3518 : case MCK_COP2AsmReg: {
3519 : DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3520 566 : if (DP.isMatch())
3521 : return MCTargetAsmParser::Match_Success;
3522 : break;
3523 : }
3524 : // 'COP3AsmReg' class
3525 : case MCK_COP3AsmReg: {
3526 : DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3527 16 : if (DP.isMatch())
3528 : return MCTargetAsmParser::Match_Success;
3529 : break;
3530 : }
3531 : // 'FCCAsmReg' class
3532 : case MCK_FCCAsmReg: {
3533 : DiagnosticPredicate DP(Operand.isFCCAsmReg());
3534 2076 : if (DP.isMatch())
3535 : return MCTargetAsmParser::Match_Success;
3536 : break;
3537 : }
3538 : // 'FGR32AsmReg' class
3539 : case MCK_FGR32AsmReg: {
3540 : DiagnosticPredicate DP(Operand.isFGRAsmReg());
3541 6778 : if (DP.isMatch())
3542 : return MCTargetAsmParser::Match_Success;
3543 : break;
3544 : }
3545 : // 'FGR64AsmReg' class
3546 : case MCK_FGR64AsmReg: {
3547 : DiagnosticPredicate DP(Operand.isFGRAsmReg());
3548 4322 : if (DP.isMatch())
3549 : return MCTargetAsmParser::Match_Success;
3550 : break;
3551 : }
3552 : // 'FGRH32AsmReg' class
3553 : case MCK_FGRH32AsmReg: {
3554 : DiagnosticPredicate DP(Operand.isFGRAsmReg());
3555 0 : if (DP.isMatch())
3556 : return MCTargetAsmParser::Match_Success;
3557 : break;
3558 : }
3559 : // 'GPR32AsmReg' class
3560 : case MCK_GPR32AsmReg: {
3561 : DiagnosticPredicate DP(Operand.isGPRAsmReg());
3562 66092 : if (DP.isMatch())
3563 : return MCTargetAsmParser::Match_Success;
3564 : break;
3565 : }
3566 : // 'GPR32NonZeroAsmReg' class
3567 : case MCK_GPR32NonZeroAsmReg: {
3568 : DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3569 130 : if (DP.isMatch())
3570 : return MCTargetAsmParser::Match_Success;
3571 : break;
3572 : }
3573 : // 'GPR32ZeroAsmReg' class
3574 : case MCK_GPR32ZeroAsmReg: {
3575 : DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3576 100 : if (DP.isMatch())
3577 : return MCTargetAsmParser::Match_Success;
3578 : break;
3579 : }
3580 : // 'GPR64AsmReg' class
3581 : case MCK_GPR64AsmReg: {
3582 : DiagnosticPredicate DP(Operand.isGPRAsmReg());
3583 8341 : if (DP.isMatch())
3584 : return MCTargetAsmParser::Match_Success;
3585 : break;
3586 : }
3587 : // 'GPRMM16AsmReg' class
3588 : case MCK_GPRMM16AsmReg: {
3589 : DiagnosticPredicate DP(Operand.isMM16AsmReg());
3590 269 : if (DP.isMatch())
3591 : return MCTargetAsmParser::Match_Success;
3592 : break;
3593 : }
3594 : // 'GPRMM16AsmRegMoveP' class
3595 : case MCK_GPRMM16AsmRegMoveP: {
3596 : DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3597 28 : if (DP.isMatch())
3598 : return MCTargetAsmParser::Match_Success;
3599 : break;
3600 : }
3601 : // 'GPRMM16AsmRegMovePPairFirst' class
3602 : case MCK_GPRMM16AsmRegMovePPairFirst: {
3603 : DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst());
3604 20 : if (DP.isMatch())
3605 : return MCTargetAsmParser::Match_Success;
3606 : break;
3607 : }
3608 : // 'GPRMM16AsmRegMovePPairSecond' class
3609 : case MCK_GPRMM16AsmRegMovePPairSecond: {
3610 : DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond());
3611 16 : if (DP.isMatch())
3612 : return MCTargetAsmParser::Match_Success;
3613 : break;
3614 : }
3615 : // 'GPRMM16AsmRegZero' class
3616 : case MCK_GPRMM16AsmRegZero: {
3617 : DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3618 65 : if (DP.isMatch())
3619 : return MCTargetAsmParser::Match_Success;
3620 : break;
3621 : }
3622 : // 'HI32DSPAsmReg' class
3623 : case MCK_HI32DSPAsmReg: {
3624 : DiagnosticPredicate DP(Operand.isACCAsmReg());
3625 9 : if (DP.isMatch())
3626 : return MCTargetAsmParser::Match_Success;
3627 : break;
3628 : }
3629 : // 'HWRegsAsmReg' class
3630 : case MCK_HWRegsAsmReg: {
3631 : DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3632 85 : if (DP.isMatch())
3633 : return MCTargetAsmParser::Match_Success;
3634 : break;
3635 : }
3636 : // 'Imm' class
3637 2970 : case MCK_Imm: {
3638 : DiagnosticPredicate DP(Operand.isImm());
3639 2970 : if (DP.isMatch())
3640 : return MCTargetAsmParser::Match_Success;
3641 : break;
3642 : }
3643 : // 'LO32DSPAsmReg' class
3644 : case MCK_LO32DSPAsmReg: {
3645 : DiagnosticPredicate DP(Operand.isACCAsmReg());
3646 9 : if (DP.isMatch())
3647 : return MCTargetAsmParser::Match_Success;
3648 : break;
3649 : }
3650 : // 'MSA128AsmReg' class
3651 : case MCK_MSA128AsmReg: {
3652 : DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3653 2131 : if (DP.isMatch())
3654 : return MCTargetAsmParser::Match_Success;
3655 : break;
3656 : }
3657 : // 'MSACtrlAsmReg' class
3658 : case MCK_MSACtrlAsmReg: {
3659 : DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3660 38 : if (DP.isMatch())
3661 : return MCTargetAsmParser::Match_Success;
3662 : break;
3663 : }
3664 : // 'MicroMipsMemGP' class
3665 0 : case MCK_MicroMipsMemGP: {
3666 0 : DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
3667 0 : if (DP.isMatch())
3668 : return MCTargetAsmParser::Match_Success;
3669 : break;
3670 : }
3671 : // 'MicroMipsMem' class
3672 75 : case MCK_MicroMipsMem: {
3673 75 : DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
3674 75 : if (DP.isMatch())
3675 : return MCTargetAsmParser::Match_Success;
3676 : break;
3677 : }
3678 : // 'MicroMipsMemSP' class
3679 10458 : case MCK_MicroMipsMemSP: {
3680 10458 : DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
3681 10458 : if (DP.isMatch())
3682 : return MCTargetAsmParser::Match_Success;
3683 : break;
3684 : }
3685 : // 'InvNum' class
3686 245 : case MCK_InvNum: {
3687 : DiagnosticPredicate DP(Operand.isInvNum());
3688 245 : if (DP.isMatch())
3689 : return MCTargetAsmParser::Match_Success;
3690 : break;
3691 : }
3692 : // 'JumpTarget' class
3693 2588 : case MCK_JumpTarget: {
3694 : DiagnosticPredicate DP(Operand.isImm());
3695 2588 : if (DP.isMatch())
3696 : return MCTargetAsmParser::Match_Success;
3697 : break;
3698 : }
3699 : // 'MemOffsetSimm10' class
3700 7 : case MCK_MemOffsetSimm10: {
3701 7 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>());
3702 7 : if (DP.isMatch())
3703 : return MCTargetAsmParser::Match_Success;
3704 : if (DP.isNearMatch())
3705 4 : return MipsAsmParser::Match_MemSImm10;
3706 : break;
3707 : }
3708 : // 'MemOffsetSimm10_1' class
3709 9 : case MCK_MemOffsetSimm10_1: {
3710 9 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
3711 9 : if (DP.isMatch())
3712 : return MCTargetAsmParser::Match_Success;
3713 : if (DP.isNearMatch())
3714 4 : return MipsAsmParser::Match_MemSImm10Lsl1;
3715 : break;
3716 : }
3717 : // 'MemOffsetSimm10_2' class
3718 10 : case MCK_MemOffsetSimm10_2: {
3719 10 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
3720 10 : if (DP.isMatch())
3721 : return MCTargetAsmParser::Match_Success;
3722 : if (DP.isNearMatch())
3723 4 : return MipsAsmParser::Match_MemSImm10Lsl2;
3724 : break;
3725 : }
3726 : // 'MemOffsetSimm10_3' class
3727 13 : case MCK_MemOffsetSimm10_3: {
3728 13 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
3729 13 : if (DP.isMatch())
3730 : return MCTargetAsmParser::Match_Success;
3731 : if (DP.isNearMatch())
3732 4 : return MipsAsmParser::Match_MemSImm10Lsl3;
3733 : break;
3734 : }
3735 : // 'MemOffsetSimm11' class
3736 304 : case MCK_MemOffsetSimm11: {
3737 304 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>());
3738 304 : if (DP.isMatch())
3739 : return MCTargetAsmParser::Match_Success;
3740 : if (DP.isNearMatch())
3741 246 : return MipsAsmParser::Match_MemSImm11;
3742 : break;
3743 : }
3744 : // 'MemOffsetSimm12' class
3745 40 : case MCK_MemOffsetSimm12: {
3746 40 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>());
3747 40 : if (DP.isMatch())
3748 : return MCTargetAsmParser::Match_Success;
3749 : if (DP.isNearMatch())
3750 15 : return MipsAsmParser::Match_MemSImm12;
3751 : break;
3752 : }
3753 : // 'MemOffsetSimm16' class
3754 977 : case MCK_MemOffsetSimm16: {
3755 977 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>());
3756 977 : if (DP.isMatch())
3757 : return MCTargetAsmParser::Match_Success;
3758 : if (DP.isNearMatch())
3759 287 : return MipsAsmParser::Match_MemSImm16;
3760 : break;
3761 : }
3762 : // 'MemOffsetSimm9' class
3763 1836 : case MCK_MemOffsetSimm9: {
3764 1836 : DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>());
3765 1836 : if (DP.isMatch())
3766 : return MCTargetAsmParser::Match_Success;
3767 : if (DP.isNearMatch())
3768 1250 : return MipsAsmParser::Match_MemSImm9;
3769 : break;
3770 : }
3771 : // 'MemOffsetSimmPtr' class
3772 381 : case MCK_MemOffsetSimmPtr: {
3773 381 : DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
3774 381 : if (DP.isMatch())
3775 : return MCTargetAsmParser::Match_Success;
3776 : if (DP.isNearMatch())
3777 46 : return MipsAsmParser::Match_MemSImmPtr;
3778 : break;
3779 : }
3780 : // 'MemOffsetUimm4' class
3781 18 : case MCK_MemOffsetUimm4: {
3782 18 : DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
3783 18 : if (DP.isMatch())
3784 : return MCTargetAsmParser::Match_Success;
3785 : break;
3786 : }
3787 : // 'Mem' class
3788 12041 : case MCK_Mem: {
3789 : DiagnosticPredicate DP(Operand.isMem());
3790 12041 : if (DP.isMatch())
3791 : return MCTargetAsmParser::Match_Success;
3792 : break;
3793 : }
3794 : // 'RegList16' class
3795 36 : case MCK_RegList16: {
3796 36 : DiagnosticPredicate DP(Operand.isRegList16());
3797 36 : if (DP.isMatch())
3798 : return MCTargetAsmParser::Match_Success;
3799 : break;
3800 : }
3801 : // 'RegList' class
3802 55 : case MCK_RegList: {
3803 : DiagnosticPredicate DP(Operand.isRegList());
3804 55 : if (DP.isMatch())
3805 : return MCTargetAsmParser::Match_Success;
3806 : break;
3807 : }
3808 : // 'Simm19_Lsl2' class
3809 94 : case MCK_Simm19_Lsl2: {
3810 94 : DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3811 94 : if (DP.isMatch())
3812 : return MCTargetAsmParser::Match_Success;
3813 : if (DP.isNearMatch())
3814 42 : return MipsAsmParser::Match_SImm19_Lsl2;
3815 : break;
3816 : }
3817 : // 'StrictlyAFGR64AsmReg' class
3818 : case MCK_StrictlyAFGR64AsmReg: {
3819 : DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3820 91 : if (DP.isMatch())
3821 : return MCTargetAsmParser::Match_Success;
3822 : break;
3823 : }
3824 : // 'StrictlyFGR32AsmReg' class
3825 : case MCK_StrictlyFGR32AsmReg: {
3826 : DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3827 66 : if (DP.isMatch())
3828 : return MCTargetAsmParser::Match_Success;
3829 : break;
3830 : }
3831 : // 'StrictlyFGR64AsmReg' class
3832 : case MCK_StrictlyFGR64AsmReg: {
3833 : DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3834 52 : if (DP.isMatch())
3835 : return MCTargetAsmParser::Match_Success;
3836 : break;
3837 : }
3838 : // 'ConstantImmz' class
3839 12 : case MCK_ConstantImmz: {
3840 12 : DiagnosticPredicate DP(Operand.isConstantImmz());
3841 12 : if (DP.isMatch())
3842 : return MCTargetAsmParser::Match_Success;
3843 : if (DP.isNearMatch())
3844 8 : return MipsAsmParser::Match_Immz;
3845 : break;
3846 : }
3847 : // 'ConstantUImm1_0' class
3848 69 : case MCK_ConstantUImm1_0: {
3849 69 : DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3850 69 : if (DP.isMatch())
3851 : return MCTargetAsmParser::Match_Success;
3852 : if (DP.isNearMatch())
3853 14 : return MipsAsmParser::Match_UImm1_0;
3854 : break;
3855 : }
3856 : // 'ConstantUImm2_0' class
3857 85 : case MCK_ConstantUImm2_0: {
3858 85 : DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3859 85 : if (DP.isMatch())
3860 : return MCTargetAsmParser::Match_Success;
3861 : if (DP.isNearMatch())
3862 54 : return MipsAsmParser::Match_UImm2_0;
3863 : break;
3864 : }
3865 : // 'ConstantUImm2_1' class
3866 56 : case MCK_ConstantUImm2_1: {
3867 56 : DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3868 56 : if (DP.isMatch())
3869 : return MCTargetAsmParser::Match_Success;
3870 : if (DP.isNearMatch())
3871 38 : return MipsAsmParser::Match_UImm2_1;
3872 : break;
3873 : }
3874 : // 'ConstantUImm3_0' class
3875 410 : case MCK_ConstantUImm3_0: {
3876 410 : DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3877 410 : if (DP.isMatch())
3878 : return MCTargetAsmParser::Match_Success;
3879 : if (DP.isNearMatch())
3880 181 : return MipsAsmParser::Match_UImm3_0;
3881 : break;
3882 : }
3883 : // 'ConstantSImm4_0' class
3884 8 : case MCK_ConstantSImm4_0: {
3885 8 : DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
3886 8 : if (DP.isMatch())
3887 : return MCTargetAsmParser::Match_Success;
3888 : if (DP.isNearMatch())
3889 4 : return MipsAsmParser::Match_SImm4_0;
3890 : break;
3891 : }
3892 : // 'ConstantUImm4_0' class
3893 291 : case MCK_ConstantUImm4_0: {
3894 291 : DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
3895 291 : if (DP.isMatch())
3896 : return MCTargetAsmParser::Match_Success;
3897 : if (DP.isNearMatch())
3898 210 : return MipsAsmParser::Match_UImm4_0;
3899 : break;
3900 : }
3901 : // 'ConstantSImm5_0' class
3902 60 : case MCK_ConstantSImm5_0: {
3903 60 : DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
3904 60 : if (DP.isMatch())
3905 : return MCTargetAsmParser::Match_Success;
3906 : if (DP.isNearMatch())
3907 40 : return MipsAsmParser::Match_SImm5_0;
3908 : break;
3909 : }
3910 : // 'ConstantUImm5_0' class
3911 2094 : case MCK_ConstantUImm5_0: {
3912 2094 : DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3913 2094 : if (DP.isMatch())
3914 : return MCTargetAsmParser::Match_Success;
3915 : if (DP.isNearMatch())
3916 1225 : return MipsAsmParser::Match_UImm5_0;
3917 : break;
3918 : }
3919 : // 'ConstantUImm5_1' class
3920 129 : case MCK_ConstantUImm5_1: {
3921 129 : DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3922 129 : if (DP.isMatch())
3923 : return MCTargetAsmParser::Match_Success;
3924 : if (DP.isNearMatch())
3925 50 : return MipsAsmParser::Match_UImm5_1;
3926 : break;
3927 : }
3928 : // 'ConstantUImm5_Plus1_Report_UImm6' class
3929 11 : case MCK_ConstantUImm5_Plus1_Report_UImm6: {
3930 11 : DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3931 11 : if (DP.isMatch())
3932 : return MCTargetAsmParser::Match_Success;
3933 : if (DP.isNearMatch())
3934 2 : return MipsAsmParser::Match_UImm5_1;
3935 : break;
3936 : }
3937 : // 'ConstantUImm5_32_Norm' class
3938 16 : case MCK_ConstantUImm5_32_Norm: {
3939 16 : DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3940 16 : if (DP.isMatch())
3941 : return MCTargetAsmParser::Match_Success;
3942 : if (DP.isNearMatch())
3943 10 : return MipsAsmParser::Match_UImm5_32;
3944 : break;
3945 : }
3946 : // 'ConstantUImm5_32' class
3947 76 : case MCK_ConstantUImm5_32: {
3948 76 : DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3949 76 : if (DP.isMatch())
3950 : return MCTargetAsmParser::Match_Success;
3951 : if (DP.isNearMatch())
3952 42 : return MipsAsmParser::Match_UImm5_32;
3953 : break;
3954 : }
3955 : // 'ConstantUImm5_0_Report_UImm6' class
3956 23 : case MCK_ConstantUImm5_0_Report_UImm6: {
3957 23 : DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3958 23 : if (DP.isMatch())
3959 : return MCTargetAsmParser::Match_Success;
3960 : if (DP.isNearMatch())
3961 10 : return MipsAsmParser::Match_UImm5_0_Report_UImm6;
3962 : break;
3963 : }
3964 : // 'ConstantUImm5_33' class
3965 26 : case MCK_ConstantUImm5_33: {
3966 26 : DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
3967 26 : if (DP.isMatch())
3968 : return MCTargetAsmParser::Match_Success;
3969 : if (DP.isNearMatch())
3970 15 : return MipsAsmParser::Match_UImm5_33;
3971 : break;
3972 : }
3973 : // 'ConstantUImmRange2_64' class
3974 28 : case MCK_ConstantUImmRange2_64: {
3975 28 : DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
3976 28 : if (DP.isMatch())
3977 : return MCTargetAsmParser::Match_Success;
3978 : if (DP.isNearMatch())
3979 10 : return MipsAsmParser::Match_UImmRange2_64;
3980 : break;
3981 : }
3982 : // 'UImm5Lsl2' class
3983 26 : case MCK_UImm5Lsl2: {
3984 26 : DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
3985 26 : if (DP.isMatch())
3986 : return MCTargetAsmParser::Match_Success;
3987 : if (DP.isNearMatch())
3988 22 : return MipsAsmParser::Match_UImm5_Lsl2;
3989 : break;
3990 : }
3991 : // 'ConstantSImm6_0' class
3992 22 : case MCK_ConstantSImm6_0: {
3993 22 : DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
3994 22 : if (DP.isMatch())
3995 : return MCTargetAsmParser::Match_Success;
3996 : if (DP.isNearMatch())
3997 8 : return MipsAsmParser::Match_SImm6_0;
3998 : break;
3999 : }
4000 : // 'ConstantUImm6_0' class
4001 302 : case MCK_ConstantUImm6_0: {
4002 302 : DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
4003 302 : if (DP.isMatch())
4004 : return MCTargetAsmParser::Match_Success;
4005 : if (DP.isNearMatch())
4006 183 : return MipsAsmParser::Match_UImm6_0;
4007 : break;
4008 : }
4009 : // 'UImm6Lsl2' class
4010 10 : case MCK_UImm6Lsl2: {
4011 10 : DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
4012 10 : if (DP.isMatch())
4013 : return MCTargetAsmParser::Match_Success;
4014 : if (DP.isNearMatch())
4015 6 : return MipsAsmParser::Match_UImm6_Lsl2;
4016 : break;
4017 : }
4018 : // 'ConstantUImm7_0' class
4019 19 : case MCK_ConstantUImm7_0: {
4020 19 : DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
4021 19 : if (DP.isMatch())
4022 : return MCTargetAsmParser::Match_Success;
4023 : if (DP.isNearMatch())
4024 8 : return MipsAsmParser::Match_UImm7_0;
4025 : break;
4026 : }
4027 : // 'UImm7_N1' class
4028 16 : case MCK_UImm7_N1: {
4029 16 : DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
4030 16 : if (DP.isMatch())
4031 : return MCTargetAsmParser::Match_Success;
4032 : if (DP.isNearMatch())
4033 8 : return MipsAsmParser::Match_UImm7_N1;
4034 : break;
4035 : }
4036 : // 'ConstantUImm8_0' class
4037 46 : case MCK_ConstantUImm8_0: {
4038 46 : DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
4039 46 : if (DP.isMatch())
4040 : return MCTargetAsmParser::Match_Success;
4041 : if (DP.isNearMatch())
4042 27 : return MipsAsmParser::Match_UImm8_0;
4043 : break;
4044 : }
4045 : // 'SImm7Lsl2' class
4046 0 : case MCK_SImm7Lsl2: {
4047 0 : DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
4048 0 : if (DP.isMatch())
4049 : return MCTargetAsmParser::Match_Success;
4050 : if (DP.isNearMatch())
4051 0 : return MipsAsmParser::Match_SImm7_Lsl2;
4052 : break;
4053 : }
4054 : // 'ConstantSImm9_0' class
4055 0 : case MCK_ConstantSImm9_0: {
4056 0 : DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
4057 0 : if (DP.isMatch())
4058 : return MCTargetAsmParser::Match_Success;
4059 : if (DP.isNearMatch())
4060 0 : return MipsAsmParser::Match_SImm9_0;
4061 : break;
4062 : }
4063 : // 'ConstantSImm10_0' class
4064 44 : case MCK_ConstantSImm10_0: {
4065 44 : DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
4066 44 : if (DP.isMatch())
4067 : return MCTargetAsmParser::Match_Success;
4068 : if (DP.isNearMatch())
4069 26 : return MipsAsmParser::Match_SImm10_0;
4070 : break;
4071 : }
4072 : // 'ConstantUImm10_0' class
4073 470 : case MCK_ConstantUImm10_0: {
4074 470 : DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
4075 470 : if (DP.isMatch())
4076 : return MCTargetAsmParser::Match_Success;
4077 : if (DP.isNearMatch())
4078 212 : return MipsAsmParser::Match_UImm10_0;
4079 : break;
4080 : }
4081 : // 'SImm10Lsl1' class
4082 0 : case MCK_SImm10Lsl1: {
4083 0 : DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
4084 0 : if (DP.isMatch())
4085 : return MCTargetAsmParser::Match_Success;
4086 : if (DP.isNearMatch())
4087 0 : return MipsAsmParser::Match_SImm10_Lsl1;
4088 : break;
4089 : }
4090 : // 'ConstantSImm11_0' class
4091 0 : case MCK_ConstantSImm11_0: {
4092 0 : DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
4093 0 : if (DP.isMatch())
4094 : return MCTargetAsmParser::Match_Success;
4095 : if (DP.isNearMatch())
4096 0 : return MipsAsmParser::Match_SImm11_0;
4097 : break;
4098 : }
4099 : // 'SImm10Lsl2' class
4100 0 : case MCK_SImm10Lsl2: {
4101 0 : DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
4102 0 : if (DP.isMatch())
4103 : return MCTargetAsmParser::Match_Success;
4104 : if (DP.isNearMatch())
4105 0 : return MipsAsmParser::Match_SImm10_Lsl2;
4106 : break;
4107 : }
4108 : // 'SImm10Lsl3' class
4109 0 : case MCK_SImm10Lsl3: {
4110 0 : DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
4111 0 : if (DP.isMatch())
4112 : return MCTargetAsmParser::Match_Success;
4113 : if (DP.isNearMatch())
4114 0 : return MipsAsmParser::Match_SImm10_Lsl3;
4115 : break;
4116 : }
4117 : // 'SImm16' class
4118 3680 : case MCK_SImm16: {
4119 3680 : DiagnosticPredicate DP(Operand.isSImm<16>());
4120 3680 : if (DP.isMatch())
4121 : return MCTargetAsmParser::Match_Success;
4122 : if (DP.isNearMatch())
4123 1691 : return MipsAsmParser::Match_SImm16;
4124 : break;
4125 : }
4126 : // 'SImm16_Relaxed' class
4127 1135 : case MCK_SImm16_Relaxed: {
4128 1135 : DiagnosticPredicate DP(Operand.isAnyImm<16>());
4129 1135 : if (DP.isMatch())
4130 : return MCTargetAsmParser::Match_Success;
4131 : if (DP.isNearMatch())
4132 619 : return MipsAsmParser::Match_SImm16_Relaxed;
4133 : break;
4134 : }
4135 : // 'UImm16_AltRelaxed' class
4136 11 : case MCK_UImm16_AltRelaxed: {
4137 11 : DiagnosticPredicate DP(Operand.isUImm<16>());
4138 11 : if (DP.isMatch())
4139 : return MCTargetAsmParser::Match_Success;
4140 : if (DP.isNearMatch())
4141 5 : return MipsAsmParser::Match_UImm16_AltRelaxed;
4142 : break;
4143 : }
4144 : // 'UImm16' class
4145 913 : case MCK_UImm16: {
4146 913 : DiagnosticPredicate DP(Operand.isUImm<16>());
4147 913 : if (DP.isMatch())
4148 : return MCTargetAsmParser::Match_Success;
4149 : if (DP.isNearMatch())
4150 556 : return MipsAsmParser::Match_UImm16;
4151 : break;
4152 : }
4153 : // 'SImm19Lsl2' class
4154 0 : case MCK_SImm19Lsl2: {
4155 0 : DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4156 0 : if (DP.isMatch())
4157 : return MCTargetAsmParser::Match_Success;
4158 : if (DP.isNearMatch())
4159 0 : return MipsAsmParser::Match_SImm19_Lsl2;
4160 : break;
4161 : }
4162 : // 'UImm16_Relaxed' class
4163 225 : case MCK_UImm16_Relaxed: {
4164 225 : DiagnosticPredicate DP(Operand.isAnyImm<16>());
4165 225 : if (DP.isMatch())
4166 : return MCTargetAsmParser::Match_Success;
4167 : if (DP.isNearMatch())
4168 0 : return MipsAsmParser::Match_UImm16_Relaxed;
4169 : break;
4170 : }
4171 : // 'ConstantUImm20_0' class
4172 47 : case MCK_ConstantUImm20_0: {
4173 47 : DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4174 47 : if (DP.isMatch())
4175 : return MCTargetAsmParser::Match_Success;
4176 : if (DP.isNearMatch())
4177 15 : return MipsAsmParser::Match_UImm20_0;
4178 : break;
4179 : }
4180 : // 'ConstantUImm26_0' class
4181 0 : case MCK_ConstantUImm26_0: {
4182 0 : DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4183 0 : if (DP.isMatch())
4184 : return MCTargetAsmParser::Match_Success;
4185 : if (DP.isNearMatch())
4186 0 : return MipsAsmParser::Match_UImm26_0;
4187 : break;
4188 : }
4189 : // 'SImm32' class
4190 198 : case MCK_SImm32: {
4191 198 : DiagnosticPredicate DP(Operand.isSImm<32>());
4192 198 : if (DP.isMatch())
4193 : return MCTargetAsmParser::Match_Success;
4194 : if (DP.isNearMatch())
4195 148 : return MipsAsmParser::Match_SImm32;
4196 : break;
4197 : }
4198 : // 'SImm32_Relaxed' class
4199 2242 : case MCK_SImm32_Relaxed: {
4200 2242 : DiagnosticPredicate DP(Operand.isAnyImm<33>());
4201 2242 : if (DP.isMatch())
4202 : return MCTargetAsmParser::Match_Success;
4203 : if (DP.isNearMatch())
4204 1216 : return MipsAsmParser::Match_SImm32_Relaxed;
4205 : break;
4206 : }
4207 : // 'UImm32_Coerced' class
4208 209 : case MCK_UImm32_Coerced: {
4209 209 : DiagnosticPredicate DP(Operand.isSImm<33>());
4210 209 : if (DP.isMatch())
4211 : return MCTargetAsmParser::Match_Success;
4212 : if (DP.isNearMatch())
4213 3 : return MipsAsmParser::Match_UImm32_Coerced;
4214 : break;
4215 : }
4216 : } // end switch (Kind)
4217 :
4218 : if (Operand.isReg()) {
4219 : MatchClassKind OpKind;
4220 : switch (Operand.getReg()) {
4221 : default: OpKind = InvalidMatchClass; break;
4222 : case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
4223 : case Mips::AT: OpKind = MCK_GPR32NONZERO; break;
4224 : case Mips::V0: OpKind = MCK_Reg11; break;
4225 : case Mips::V1: OpKind = MCK_Reg11; break;
4226 : case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break;
4227 : case Mips::A1: OpKind = MCK_Reg13; break;
4228 : case Mips::A2: OpKind = MCK_Reg13; break;
4229 : case Mips::A3: OpKind = MCK_Reg14; break;
4230 : case Mips::T0: OpKind = MCK_GPR32NONZERO; break;
4231 : case Mips::T1: OpKind = MCK_GPR32NONZERO; break;
4232 : case Mips::T2: OpKind = MCK_GPR32NONZERO; break;
4233 : case Mips::T3: OpKind = MCK_GPR32NONZERO; break;
4234 : case Mips::T4: OpKind = MCK_GPR32NONZERO; break;
4235 : case Mips::T5: OpKind = MCK_GPR32NONZERO; break;
4236 : case Mips::T6: OpKind = MCK_GPR32NONZERO; break;
4237 : case Mips::T7: OpKind = MCK_GPR32NONZERO; break;
4238 : case Mips::S0: OpKind = MCK_Reg9; break;
4239 : case Mips::S1: OpKind = MCK_Reg11; break;
4240 : case Mips::S2: OpKind = MCK_Reg10; break;
4241 : case Mips::S3: OpKind = MCK_Reg10; break;
4242 : case Mips::S4: OpKind = MCK_Reg10; break;
4243 : case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break;
4244 : case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break;
4245 : case Mips::S7: OpKind = MCK_GPR32NONZERO; break;
4246 : case Mips::T8: OpKind = MCK_GPR32NONZERO; break;
4247 : case Mips::T9: OpKind = MCK_GPR32NONZERO; break;
4248 : case Mips::K0: OpKind = MCK_GPR32NONZERO; break;
4249 : case Mips::K1: OpKind = MCK_GPR32NONZERO; break;
4250 : case Mips::GP: OpKind = MCK_GP32; break;
4251 : case Mips::SP: OpKind = MCK_CPUSPReg; break;
4252 : case Mips::FP: OpKind = MCK_GPR32NONZERO; break;
4253 : case Mips::RA: OpKind = MCK_CPURAReg; break;
4254 : case Mips::ZERO_64: OpKind = MCK_Reg19; break;
4255 : case Mips::AT_64: OpKind = MCK_Reg24; break;
4256 : case Mips::V0_64: OpKind = MCK_Reg30; break;
4257 : case Mips::V1_64: OpKind = MCK_Reg30; break;
4258 : case Mips::A0_64: OpKind = MCK_Reg31; break;
4259 : case Mips::A1_64: OpKind = MCK_Reg32; break;
4260 : case Mips::A2_64: OpKind = MCK_Reg32; break;
4261 : case Mips::A3_64: OpKind = MCK_Reg33; break;
4262 : case Mips::T0_64: OpKind = MCK_Reg24; break;
4263 : case Mips::T1_64: OpKind = MCK_Reg24; break;
4264 : case Mips::T2_64: OpKind = MCK_Reg24; break;
4265 : case Mips::T3_64: OpKind = MCK_Reg24; break;
4266 : case Mips::T4_64: OpKind = MCK_Reg24; break;
4267 : case Mips::T5_64: OpKind = MCK_Reg24; break;
4268 : case Mips::T6_64: OpKind = MCK_Reg24; break;
4269 : case Mips::T7_64: OpKind = MCK_Reg24; break;
4270 : case Mips::S0_64: OpKind = MCK_Reg28; break;
4271 : case Mips::S1_64: OpKind = MCK_Reg30; break;
4272 : case Mips::S2_64: OpKind = MCK_Reg29; break;
4273 : case Mips::S3_64: OpKind = MCK_Reg29; break;
4274 : case Mips::S4_64: OpKind = MCK_Reg29; break;
4275 : case Mips::S5_64: OpKind = MCK_Reg34; break;
4276 : case Mips::S6_64: OpKind = MCK_Reg34; break;
4277 : case Mips::S7_64: OpKind = MCK_Reg24; break;
4278 : case Mips::T8_64: OpKind = MCK_Reg24; break;
4279 : case Mips::T9_64: OpKind = MCK_Reg24; break;
4280 : case Mips::K0_64: OpKind = MCK_Reg24; break;
4281 : case Mips::K1_64: OpKind = MCK_Reg24; break;
4282 : case Mips::GP_64: OpKind = MCK_GP64; break;
4283 : case Mips::SP_64: OpKind = MCK_SP64; break;
4284 : case Mips::FP_64: OpKind = MCK_Reg24; break;
4285 : case Mips::RA_64: OpKind = MCK_Reg37; break;
4286 : case Mips::F0: OpKind = MCK_FGR32; break;
4287 : case Mips::F1: OpKind = MCK_Reg39; break;
4288 : case Mips::F2: OpKind = MCK_FGR32; break;
4289 : case Mips::F3: OpKind = MCK_Reg39; break;
4290 : case Mips::F4: OpKind = MCK_FGR32; break;
4291 : case Mips::F5: OpKind = MCK_Reg39; break;
4292 : case Mips::F6: OpKind = MCK_FGR32; break;
4293 : case Mips::F7: OpKind = MCK_Reg39; break;
4294 : case Mips::F8: OpKind = MCK_FGR32; break;
4295 : case Mips::F9: OpKind = MCK_Reg39; break;
4296 : case Mips::F10: OpKind = MCK_FGR32; break;
4297 : case Mips::F11: OpKind = MCK_Reg39; break;
4298 : case Mips::F12: OpKind = MCK_FGR32; break;
4299 : case Mips::F13: OpKind = MCK_Reg39; break;
4300 : case Mips::F14: OpKind = MCK_FGR32; break;
4301 : case Mips::F15: OpKind = MCK_Reg39; break;
4302 : case Mips::F16: OpKind = MCK_FGR32; break;
4303 : case Mips::F17: OpKind = MCK_Reg39; break;
4304 : case Mips::F18: OpKind = MCK_FGR32; break;
4305 : case Mips::F19: OpKind = MCK_Reg39; break;
4306 : case Mips::F20: OpKind = MCK_FGR32; break;
4307 : case Mips::F21: OpKind = MCK_Reg39; break;
4308 : case Mips::F22: OpKind = MCK_FGR32; break;
4309 : case Mips::F23: OpKind = MCK_Reg39; break;
4310 : case Mips::F24: OpKind = MCK_FGR32; break;
4311 : case Mips::F25: OpKind = MCK_Reg39; break;
4312 : case Mips::F26: OpKind = MCK_FGR32; break;
4313 : case Mips::F27: OpKind = MCK_Reg39; break;
4314 : case Mips::F28: OpKind = MCK_FGR32; break;
4315 : case Mips::F29: OpKind = MCK_Reg39; break;
4316 : case Mips::F30: OpKind = MCK_FGR32; break;
4317 : case Mips::F31: OpKind = MCK_Reg39; break;
4318 : case Mips::F_HI0: OpKind = MCK_FGRH32; break;
4319 : case Mips::F_HI1: OpKind = MCK_Reg42; break;
4320 : case Mips::F_HI2: OpKind = MCK_FGRH32; break;
4321 : case Mips::F_HI3: OpKind = MCK_Reg42; break;
4322 : case Mips::F_HI4: OpKind = MCK_FGRH32; break;
4323 : case Mips::F_HI5: OpKind = MCK_Reg42; break;
4324 : case Mips::F_HI6: OpKind = MCK_FGRH32; break;
4325 : case Mips::F_HI7: OpKind = MCK_Reg42; break;
4326 : case Mips::F_HI8: OpKind = MCK_FGRH32; break;
4327 : case Mips::F_HI9: OpKind = MCK_Reg42; break;
4328 : case Mips::F_HI10: OpKind = MCK_FGRH32; break;
4329 : case Mips::F_HI11: OpKind = MCK_Reg42; break;
4330 : case Mips::F_HI12: OpKind = MCK_FGRH32; break;
4331 : case Mips::F_HI13: OpKind = MCK_Reg42; break;
4332 : case Mips::F_HI14: OpKind = MCK_FGRH32; break;
4333 : case Mips::F_HI15: OpKind = MCK_Reg42; break;
4334 : case Mips::F_HI16: OpKind = MCK_FGRH32; break;
4335 : case Mips::F_HI17: OpKind = MCK_Reg42; break;
4336 : case Mips::F_HI18: OpKind = MCK_FGRH32; break;
4337 : case Mips::F_HI19: OpKind = MCK_Reg42; break;
4338 : case Mips::F_HI20: OpKind = MCK_FGRH32; break;
4339 : case Mips::F_HI21: OpKind = MCK_Reg42; break;
4340 : case Mips::F_HI22: OpKind = MCK_FGRH32; break;
4341 : case Mips::F_HI23: OpKind = MCK_Reg42; break;
4342 : case Mips::F_HI24: OpKind = MCK_FGRH32; break;
4343 : case Mips::F_HI25: OpKind = MCK_Reg42; break;
4344 : case Mips::F_HI26: OpKind = MCK_FGRH32; break;
4345 : case Mips::F_HI27: OpKind = MCK_Reg42; break;
4346 : case Mips::F_HI28: OpKind = MCK_FGRH32; break;
4347 : case Mips::F_HI29: OpKind = MCK_Reg42; break;
4348 : case Mips::F_HI30: OpKind = MCK_FGRH32; break;
4349 : case Mips::F_HI31: OpKind = MCK_Reg42; break;
4350 : case Mips::D0: OpKind = MCK_AFGR64; break;
4351 : case Mips::D1: OpKind = MCK_Reg44; break;
4352 : case Mips::D2: OpKind = MCK_AFGR64; break;
4353 : case Mips::D3: OpKind = MCK_Reg44; break;
4354 : case Mips::D4: OpKind = MCK_AFGR64; break;
4355 : case Mips::D5: OpKind = MCK_Reg44; break;
4356 : case Mips::D6: OpKind = MCK_AFGR64; break;
4357 : case Mips::D7: OpKind = MCK_Reg44; break;
4358 : case Mips::D8: OpKind = MCK_AFGR64; break;
4359 : case Mips::D9: OpKind = MCK_Reg44; break;
4360 : case Mips::D10: OpKind = MCK_AFGR64; break;
4361 : case Mips::D11: OpKind = MCK_Reg44; break;
4362 : case Mips::D12: OpKind = MCK_AFGR64; break;
4363 : case Mips::D13: OpKind = MCK_Reg44; break;
4364 : case Mips::D14: OpKind = MCK_AFGR64; break;
4365 : case Mips::D15: OpKind = MCK_Reg44; break;
4366 : case Mips::D0_64: OpKind = MCK_FGR64; break;
4367 : case Mips::D1_64: OpKind = MCK_Reg47; break;
4368 : case Mips::D2_64: OpKind = MCK_FGR64; break;
4369 : case Mips::D3_64: OpKind = MCK_Reg47; break;
4370 : case Mips::D4_64: OpKind = MCK_FGR64; break;
4371 : case Mips::D5_64: OpKind = MCK_Reg47; break;
4372 : case Mips::D6_64: OpKind = MCK_FGR64; break;
4373 : case Mips::D7_64: OpKind = MCK_Reg47; break;
4374 : case Mips::D8_64: OpKind = MCK_FGR64; break;
4375 : case Mips::D9_64: OpKind = MCK_Reg47; break;
4376 : case Mips::D10_64: OpKind = MCK_FGR64; break;
4377 : case Mips::D11_64: OpKind = MCK_Reg47; break;
4378 : case Mips::D12_64: OpKind = MCK_FGR64; break;
4379 : case Mips::D13_64: OpKind = MCK_Reg47; break;
4380 : case Mips::D14_64: OpKind = MCK_FGR64; break;
4381 : case Mips::D15_64: OpKind = MCK_Reg47; break;
4382 : case Mips::D16_64: OpKind = MCK_FGR64; break;
4383 : case Mips::D17_64: OpKind = MCK_Reg47; break;
4384 : case Mips::D18_64: OpKind = MCK_FGR64; break;
4385 : case Mips::D19_64: OpKind = MCK_Reg47; break;
4386 : case Mips::D20_64: OpKind = MCK_FGR64; break;
4387 : case Mips::D21_64: OpKind = MCK_Reg47; break;
4388 : case Mips::D22_64: OpKind = MCK_FGR64; break;
4389 : case Mips::D23_64: OpKind = MCK_Reg47; break;
4390 : case Mips::D24_64: OpKind = MCK_FGR64; break;
4391 : case Mips::D25_64: OpKind = MCK_Reg47; break;
4392 : case Mips::D26_64: OpKind = MCK_FGR64; break;
4393 : case Mips::D27_64: OpKind = MCK_Reg47; break;
4394 : case Mips::D28_64: OpKind = MCK_FGR64; break;
4395 : case Mips::D29_64: OpKind = MCK_Reg47; break;
4396 : case Mips::D30_64: OpKind = MCK_FGR64; break;
4397 : case Mips::D31_64: OpKind = MCK_Reg47; break;
4398 : case Mips::W0: OpKind = MCK_MSA128WEvens; break;
4399 : case Mips::W1: OpKind = MCK_Reg50; break;
4400 : case Mips::W2: OpKind = MCK_MSA128WEvens; break;
4401 : case Mips::W3: OpKind = MCK_Reg50; break;
4402 : case Mips::W4: OpKind = MCK_MSA128WEvens; break;
4403 : case Mips::W5: OpKind = MCK_Reg50; break;
4404 : case Mips::W6: OpKind = MCK_MSA128WEvens; break;
4405 : case Mips::W7: OpKind = MCK_Reg50; break;
4406 : case Mips::W8: OpKind = MCK_MSA128WEvens; break;
4407 : case Mips::W9: OpKind = MCK_Reg50; break;
4408 : case Mips::W10: OpKind = MCK_MSA128WEvens; break;
4409 : case Mips::W11: OpKind = MCK_Reg50; break;
4410 : case Mips::W12: OpKind = MCK_MSA128WEvens; break;
4411 : case Mips::W13: OpKind = MCK_Reg50; break;
4412 : case Mips::W14: OpKind = MCK_MSA128WEvens; break;
4413 : case Mips::W15: OpKind = MCK_Reg50; break;
4414 : case Mips::W16: OpKind = MCK_MSA128WEvens; break;
4415 : case Mips::W17: OpKind = MCK_Reg50; break;
4416 : case Mips::W18: OpKind = MCK_MSA128WEvens; break;
4417 : case Mips::W19: OpKind = MCK_Reg50; break;
4418 : case Mips::W20: OpKind = MCK_MSA128WEvens; break;
4419 : case Mips::W21: OpKind = MCK_Reg50; break;
4420 : case Mips::W22: OpKind = MCK_MSA128WEvens; break;
4421 : case Mips::W23: OpKind = MCK_Reg50; break;
4422 : case Mips::W24: OpKind = MCK_MSA128WEvens; break;
4423 : case Mips::W25: OpKind = MCK_Reg50; break;
4424 : case Mips::W26: OpKind = MCK_MSA128WEvens; break;
4425 : case Mips::W27: OpKind = MCK_Reg50; break;
4426 : case Mips::W28: OpKind = MCK_MSA128WEvens; break;
4427 : case Mips::W29: OpKind = MCK_Reg50; break;
4428 : case Mips::W30: OpKind = MCK_MSA128WEvens; break;
4429 : case Mips::W31: OpKind = MCK_Reg50; break;
4430 : case Mips::HI0: OpKind = MCK_HI32; break;
4431 : case Mips::HI1: OpKind = MCK_HI32DSP; break;
4432 : case Mips::HI2: OpKind = MCK_HI32DSP; break;
4433 : case Mips::HI3: OpKind = MCK_HI32DSP; break;
4434 : case Mips::LO0: OpKind = MCK_LO32; break;
4435 : case Mips::LO1: OpKind = MCK_LO32DSP; break;
4436 : case Mips::LO2: OpKind = MCK_LO32DSP; break;
4437 : case Mips::LO3: OpKind = MCK_LO32DSP; break;
4438 : case Mips::HI0_64: OpKind = MCK_HI64; break;
4439 : case Mips::LO0_64: OpKind = MCK_LO64; break;
4440 : case Mips::FCR0: OpKind = MCK_CCR; break;
4441 : case Mips::FCR1: OpKind = MCK_CCR; break;
4442 : case Mips::FCR2: OpKind = MCK_CCR; break;
4443 : case Mips::FCR3: OpKind = MCK_CCR; break;
4444 : case Mips::FCR4: OpKind = MCK_CCR; break;
4445 : case Mips::FCR5: OpKind = MCK_CCR; break;
4446 : case Mips::FCR6: OpKind = MCK_CCR; break;
4447 : case Mips::FCR7: OpKind = MCK_CCR; break;
4448 : case Mips::FCR8: OpKind = MCK_CCR; break;
4449 : case Mips::FCR9: OpKind = MCK_CCR; break;
4450 : case Mips::FCR10: OpKind = MCK_CCR; break;
4451 : case Mips::FCR11: OpKind = MCK_CCR; break;
4452 : case Mips::FCR12: OpKind = MCK_CCR; break;
4453 : case Mips::FCR13: OpKind = MCK_CCR; break;
4454 : case Mips::FCR14: OpKind = MCK_CCR; break;
4455 : case Mips::FCR15: OpKind = MCK_CCR; break;
4456 : case Mips::FCR16: OpKind = MCK_CCR; break;
4457 : case Mips::FCR17: OpKind = MCK_CCR; break;
4458 : case Mips::FCR18: OpKind = MCK_CCR; break;
4459 : case Mips::FCR19: OpKind = MCK_CCR; break;
4460 : case Mips::FCR20: OpKind = MCK_CCR; break;
4461 : case Mips::FCR21: OpKind = MCK_CCR; break;
4462 : case Mips::FCR22: OpKind = MCK_CCR; break;
4463 : case Mips::FCR23: OpKind = MCK_CCR; break;
4464 : case Mips::FCR24: OpKind = MCK_CCR; break;
4465 : case Mips::FCR25: OpKind = MCK_CCR; break;
4466 : case Mips::FCR26: OpKind = MCK_CCR; break;
4467 : case Mips::FCR27: OpKind = MCK_CCR; break;
4468 : case Mips::FCR28: OpKind = MCK_CCR; break;
4469 : case Mips::FCR29: OpKind = MCK_CCR; break;
4470 : case Mips::FCR30: OpKind = MCK_CCR; break;
4471 : case Mips::FCR31: OpKind = MCK_CCR; break;
4472 : case Mips::FCC0: OpKind = MCK_FCC; break;
4473 : case Mips::FCC1: OpKind = MCK_FCC; break;
4474 : case Mips::FCC2: OpKind = MCK_FCC; break;
4475 : case Mips::FCC3: OpKind = MCK_FCC; break;
4476 : case Mips::FCC4: OpKind = MCK_FCC; break;
4477 : case Mips::FCC5: OpKind = MCK_FCC; break;
4478 : case Mips::FCC6: OpKind = MCK_FCC; break;
4479 : case Mips::FCC7: OpKind = MCK_FCC; break;
4480 : case Mips::COP00: OpKind = MCK_COP0; break;
4481 : case Mips::COP01: OpKind = MCK_COP0; break;
4482 : case Mips::COP02: OpKind = MCK_COP0; break;
4483 : case Mips::COP03: OpKind = MCK_COP0; break;
4484 : case Mips::COP04: OpKind = MCK_COP0; break;
4485 : case Mips::COP05: OpKind = MCK_COP0; break;
4486 : case Mips::COP06: OpKind = MCK_COP0; break;
4487 : case Mips::COP07: OpKind = MCK_COP0; break;
4488 : case Mips::COP08: OpKind = MCK_COP0; break;
4489 : case Mips::COP09: OpKind = MCK_COP0; break;
4490 : case Mips::COP010: OpKind = MCK_COP0; break;
4491 : case Mips::COP011: OpKind = MCK_COP0; break;
4492 : case Mips::COP012: OpKind = MCK_COP0; break;
4493 : case Mips::COP013: OpKind = MCK_COP0; break;
4494 : case Mips::COP014: OpKind = MCK_COP0; break;
4495 : case Mips::COP015: OpKind = MCK_COP0; break;
4496 : case Mips::COP016: OpKind = MCK_COP0; break;
4497 : case Mips::COP017: OpKind = MCK_COP0; break;
4498 : case Mips::COP018: OpKind = MCK_COP0; break;
4499 : case Mips::COP019: OpKind = MCK_COP0; break;
4500 : case Mips::COP020: OpKind = MCK_COP0; break;
4501 : case Mips::COP021: OpKind = MCK_COP0; break;
4502 : case Mips::COP022: OpKind = MCK_COP0; break;
4503 : case Mips::COP023: OpKind = MCK_COP0; break;
4504 : case Mips::COP024: OpKind = MCK_COP0; break;
4505 : case Mips::COP025: OpKind = MCK_COP0; break;
4506 : case Mips::COP026: OpKind = MCK_COP0; break;
4507 : case Mips::COP027: OpKind = MCK_COP0; break;
4508 : case Mips::COP028: OpKind = MCK_COP0; break;
4509 : case Mips::COP029: OpKind = MCK_COP0; break;
4510 : case Mips::COP030: OpKind = MCK_COP0; break;
4511 : case Mips::COP031: OpKind = MCK_COP0; break;
4512 : case Mips::COP20: OpKind = MCK_COP2; break;
4513 : case Mips::COP21: OpKind = MCK_COP2; break;
4514 : case Mips::COP22: OpKind = MCK_COP2; break;
4515 : case Mips::COP23: OpKind = MCK_COP2; break;
4516 : case Mips::COP24: OpKind = MCK_COP2; break;
4517 : case Mips::COP25: OpKind = MCK_COP2; break;
4518 : case Mips::COP26: OpKind = MCK_COP2; break;
4519 : case Mips::COP27: OpKind = MCK_COP2; break;
4520 : case Mips::COP28: OpKind = MCK_COP2; break;
4521 : case Mips::COP29: OpKind = MCK_COP2; break;
4522 : case Mips::COP210: OpKind = MCK_COP2; break;
4523 : case Mips::COP211: OpKind = MCK_COP2; break;
4524 : case Mips::COP212: OpKind = MCK_COP2; break;
4525 : case Mips::COP213: OpKind = MCK_COP2; break;
4526 : case Mips::COP214: OpKind = MCK_COP2; break;
4527 : case Mips::COP215: OpKind = MCK_COP2; break;
4528 : case Mips::COP216: OpKind = MCK_COP2; break;
4529 : case Mips::COP217: OpKind = MCK_COP2; break;
4530 : case Mips::COP218: OpKind = MCK_COP2; break;
4531 : case Mips::COP219: OpKind = MCK_COP2; break;
4532 : case Mips::COP220: OpKind = MCK_COP2; break;
4533 : case Mips::COP221: OpKind = MCK_COP2; break;
4534 : case Mips::COP222: OpKind = MCK_COP2; break;
4535 : case Mips::COP223: OpKind = MCK_COP2; break;
4536 : case Mips::COP224: OpKind = MCK_COP2; break;
4537 : case Mips::COP225: OpKind = MCK_COP2; break;
4538 : case Mips::COP226: OpKind = MCK_COP2; break;
4539 : case Mips::COP227: OpKind = MCK_COP2; break;
4540 : case Mips::COP228: OpKind = MCK_COP2; break;
4541 : case Mips::COP229: OpKind = MCK_COP2; break;
4542 : case Mips::COP230: OpKind = MCK_COP2; break;
4543 : case Mips::COP231: OpKind = MCK_COP2; break;
4544 : case Mips::COP30: OpKind = MCK_COP3; break;
4545 : case Mips::COP31: OpKind = MCK_COP3; break;
4546 : case Mips::COP32: OpKind = MCK_COP3; break;
4547 : case Mips::COP33: OpKind = MCK_COP3; break;
4548 : case Mips::COP34: OpKind = MCK_COP3; break;
4549 : case Mips::COP35: OpKind = MCK_COP3; break;
4550 : case Mips::COP36: OpKind = MCK_COP3; break;
4551 : case Mips::COP37: OpKind = MCK_COP3; break;
4552 : case Mips::COP38: OpKind = MCK_COP3; break;
4553 : case Mips::COP39: OpKind = MCK_COP3; break;
4554 : case Mips::COP310: OpKind = MCK_COP3; break;
4555 : case Mips::COP311: OpKind = MCK_COP3; break;
4556 : case Mips::COP312: OpKind = MCK_COP3; break;
4557 : case Mips::COP313: OpKind = MCK_COP3; break;
4558 : case Mips::COP314: OpKind = MCK_COP3; break;
4559 : case Mips::COP315: OpKind = MCK_COP3; break;
4560 : case Mips::COP316: OpKind = MCK_COP3; break;
4561 : case Mips::COP317: OpKind = MCK_COP3; break;
4562 : case Mips::COP318: OpKind = MCK_COP3; break;
4563 : case Mips::COP319: OpKind = MCK_COP3; break;
4564 : case Mips::COP320: OpKind = MCK_COP3; break;
4565 : case Mips::COP321: OpKind = MCK_COP3; break;
4566 : case Mips::COP322: OpKind = MCK_COP3; break;
4567 : case Mips::COP323: OpKind = MCK_COP3; break;
4568 : case Mips::COP324: OpKind = MCK_COP3; break;
4569 : case Mips::COP325: OpKind = MCK_COP3; break;
4570 : case Mips::COP326: OpKind = MCK_COP3; break;
4571 : case Mips::COP327: OpKind = MCK_COP3; break;
4572 : case Mips::COP328: OpKind = MCK_COP3; break;
4573 : case Mips::COP329: OpKind = MCK_COP3; break;
4574 : case Mips::COP330: OpKind = MCK_COP3; break;
4575 : case Mips::COP331: OpKind = MCK_COP3; break;
4576 : case Mips::PC: OpKind = MCK_PC; break;
4577 : case Mips::HWR0: OpKind = MCK_HWRegs; break;
4578 : case Mips::HWR1: OpKind = MCK_HWRegs; break;
4579 : case Mips::HWR2: OpKind = MCK_HWRegs; break;
4580 : case Mips::HWR3: OpKind = MCK_HWRegs; break;
4581 : case Mips::HWR4: OpKind = MCK_HWRegs; break;
4582 : case Mips::HWR5: OpKind = MCK_HWRegs; break;
4583 : case Mips::HWR6: OpKind = MCK_HWRegs; break;
4584 : case Mips::HWR7: OpKind = MCK_HWRegs; break;
4585 : case Mips::HWR8: OpKind = MCK_HWRegs; break;
4586 : case Mips::HWR9: OpKind = MCK_HWRegs; break;
4587 : case Mips::HWR10: OpKind = MCK_HWRegs; break;
4588 : case Mips::HWR11: OpKind = MCK_HWRegs; break;
4589 : case Mips::HWR12: OpKind = MCK_HWRegs; break;
4590 : case Mips::HWR13: OpKind = MCK_HWRegs; break;
4591 : case Mips::HWR14: OpKind = MCK_HWRegs; break;
4592 : case Mips::HWR15: OpKind = MCK_HWRegs; break;
4593 : case Mips::HWR16: OpKind = MCK_HWRegs; break;
4594 : case Mips::HWR17: OpKind = MCK_HWRegs; break;
4595 : case Mips::HWR18: OpKind = MCK_HWRegs; break;
4596 : case Mips::HWR19: OpKind = MCK_HWRegs; break;
4597 : case Mips::HWR20: OpKind = MCK_HWRegs; break;
4598 : case Mips::HWR21: OpKind = MCK_HWRegs; break;
4599 : case Mips::HWR22: OpKind = MCK_HWRegs; break;
4600 : case Mips::HWR23: OpKind = MCK_HWRegs; break;
4601 : case Mips::HWR24: OpKind = MCK_HWRegs; break;
4602 : case Mips::HWR25: OpKind = MCK_HWRegs; break;
4603 : case Mips::HWR26: OpKind = MCK_HWRegs; break;
4604 : case Mips::HWR27: OpKind = MCK_HWRegs; break;
4605 : case Mips::HWR28: OpKind = MCK_HWRegs; break;
4606 : case Mips::HWR29: OpKind = MCK_HWRegs; break;
4607 : case Mips::HWR30: OpKind = MCK_HWRegs; break;
4608 : case Mips::HWR31: OpKind = MCK_HWRegs; break;
4609 : case Mips::AC0: OpKind = MCK_ACC64; break;
4610 : case Mips::AC1: OpKind = MCK_ACC64DSP; break;
4611 : case Mips::AC2: OpKind = MCK_ACC64DSP; break;
4612 : case Mips::AC3: OpKind = MCK_ACC64DSP; break;
4613 : case Mips::AC0_64: OpKind = MCK_ACC128; break;
4614 : case Mips::DSPCCond: OpKind = MCK_DSPCC; break;
4615 : case Mips::MSAIR: OpKind = MCK_MSACtrl; break;
4616 : case Mips::MSACSR: OpKind = MCK_MSACtrl; break;
4617 : case Mips::MSAAccess: OpKind = MCK_MSACtrl; break;
4618 : case Mips::MSASave: OpKind = MCK_MSACtrl; break;
4619 : case Mips::MSAModify: OpKind = MCK_MSACtrl; break;
4620 : case Mips::MSARequest: OpKind = MCK_MSACtrl; break;
4621 : case Mips::MSAMap: OpKind = MCK_MSACtrl; break;
4622 : case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break;
4623 : case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break;
4624 : case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break;
4625 : case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break;
4626 : case Mips::P0: OpKind = MCK_OCTEON_P; break;
4627 : case Mips::P1: OpKind = MCK_OCTEON_P; break;
4628 : case Mips::P2: OpKind = MCK_OCTEON_P; break;
4629 : }
4630 251 : return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
4631 : getDiagKindFromRegisterClass(Kind);
4632 : }
4633 :
4634 : if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
4635 : return getDiagKindFromRegisterClass(Kind);
4636 :
4637 : return MCTargetAsmParser::Match_InvalidOperand;
4638 : }
4639 :
4640 : #ifndef NDEBUG
4641 : const char *getMatchClassName(MatchClassKind Kind) {
4642 : switch (Kind) {
4643 : case InvalidMatchClass: return "InvalidMatchClass";
4644 : case OptionalMatchClass: return "OptionalMatchClass";
4645 : case MCK__35_: return "MCK__35_";
4646 : case MCK__40_: return "MCK__40_";
4647 : case MCK__41_: return "MCK__41_";
4648 : case MCK_0: return "MCK_0";
4649 : case MCK_16: return "MCK_16";
4650 : case MCK__91_: return "MCK__91_";
4651 : case MCK__93_: return "MCK__93_";
4652 : case MCK_bit: return "MCK_bit";
4653 : case MCK_inst: return "MCK_inst";
4654 : case MCK_Reg19: return "MCK_Reg19";
4655 : case MCK_Reg37: return "MCK_Reg37";
4656 : case MCK_ACC128: return "MCK_ACC128";
4657 : case MCK_ACC64: return "MCK_ACC64";
4658 : case MCK_CPURAReg: return "MCK_CPURAReg";
4659 : case MCK_CPUSPReg: return "MCK_CPUSPReg";
4660 : case MCK_DSPCC: return "MCK_DSPCC";
4661 : case MCK_GP32: return "MCK_GP32";
4662 : case MCK_GP64: return "MCK_GP64";
4663 : case MCK_GPR32ZERO: return "MCK_GPR32ZERO";
4664 : case MCK_HI32: return "MCK_HI32";
4665 : case MCK_HI64: return "MCK_HI64";
4666 : case MCK_LO32: return "MCK_LO32";
4667 : case MCK_LO64: return "MCK_LO64";
4668 : case MCK_PC: return "MCK_PC";
4669 : case MCK_SP64: return "MCK_SP64";
4670 : case MCK_Reg13: return "MCK_Reg13";
4671 : case MCK_Reg32: return "MCK_Reg32";
4672 : case MCK_Reg11: return "MCK_Reg11";
4673 : case MCK_Reg14: return "MCK_Reg14";
4674 : case MCK_Reg30: return "MCK_Reg30";
4675 : case MCK_Reg31: return "MCK_Reg31";
4676 : case MCK_Reg33: return "MCK_Reg33";
4677 : case MCK_GPRMM16MovePPairFirst: return "MCK_GPRMM16MovePPairFirst";
4678 : case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL";
4679 : case MCK_OCTEON_P: return "MCK_OCTEON_P";
4680 : case MCK_Reg4: return "MCK_Reg4";
4681 : case MCK_Reg9: return "MCK_Reg9";
4682 : case MCK_Reg23: return "MCK_Reg23";
4683 : case MCK_Reg28: return "MCK_Reg28";
4684 : case MCK_ACC64DSP: return "MCK_ACC64DSP";
4685 : case MCK_HI32DSP: return "MCK_HI32DSP";
4686 : case MCK_LO32DSP: return "MCK_LO32DSP";
4687 : case MCK_Reg34: return "MCK_Reg34";
4688 : case MCK_GPRMM16MovePPairSecond: return "MCK_GPRMM16MovePPairSecond";
4689 : case MCK_Reg8: return "MCK_Reg8";
4690 : case MCK_Reg10: return "MCK_Reg10";
4691 : case MCK_Reg27: return "MCK_Reg27";
4692 : case MCK_Reg29: return "MCK_Reg29";
4693 : case MCK_Reg21: return "MCK_Reg21";
4694 : case MCK_Reg22: return "MCK_Reg22";
4695 : case MCK_Reg25: return "MCK_Reg25";
4696 : case MCK_Reg44: return "MCK_Reg44";
4697 : case MCK_CPU16Regs: return "MCK_CPU16Regs";
4698 : case MCK_FCC: return "MCK_FCC";
4699 : case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP";
4700 : case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero";
4701 : case MCK_MSACtrl: return "MCK_MSACtrl";
4702 : case MCK_Reg26: return "MCK_Reg26";
4703 : case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP";
4704 : case MCK_Reg39: return "MCK_Reg39";
4705 : case MCK_Reg42: return "MCK_Reg42";
4706 : case MCK_Reg47: return "MCK_Reg47";
4707 : case MCK_Reg50: return "MCK_Reg50";
4708 : case MCK_AFGR64: return "MCK_AFGR64";
4709 : case MCK_MSA128WEvens: return "MCK_MSA128WEvens";
4710 : case MCK_Reg45: return "MCK_Reg45";
4711 : case MCK_Reg24: return "MCK_Reg24";
4712 : case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO";
4713 : case MCK_CCR: return "MCK_CCR";
4714 : case MCK_COP0: return "MCK_COP0";
4715 : case MCK_COP2: return "MCK_COP2";
4716 : case MCK_COP3: return "MCK_COP3";
4717 : case MCK_DSPR: return "MCK_DSPR";
4718 : case MCK_FGR32: return "MCK_FGR32";
4719 : case MCK_FGR64: return "MCK_FGR64";
4720 : case MCK_FGRH32: return "MCK_FGRH32";
4721 : case MCK_GPR64: return "MCK_GPR64";
4722 : case MCK_HWRegs: return "MCK_HWRegs";
4723 : case MCK_MSA128F16: return "MCK_MSA128F16";
4724 : case MCK_OddSP: return "MCK_OddSP";
4725 : case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg";
4726 : case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg";
4727 : case MCK_CCRAsmReg: return "MCK_CCRAsmReg";
4728 : case MCK_COP0AsmReg: return "MCK_COP0AsmReg";
4729 : case MCK_COP2AsmReg: return "MCK_COP2AsmReg";
4730 : case MCK_COP3AsmReg: return "MCK_COP3AsmReg";
4731 : case MCK_FCCAsmReg: return "MCK_FCCAsmReg";
4732 : case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg";
4733 : case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg";
4734 : case MCK_FGRH32AsmReg: return "MCK_FGRH32AsmReg";
4735 : case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg";
4736 : case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg";
4737 : case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg";
4738 : case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg";
4739 : case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg";
4740 : case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP";
4741 : case MCK_GPRMM16AsmRegMovePPairFirst: return "MCK_GPRMM16AsmRegMovePPairFirst";
4742 : case MCK_GPRMM16AsmRegMovePPairSecond: return "MCK_GPRMM16AsmRegMovePPairSecond";
4743 : case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero";
4744 : case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg";
4745 : case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg";
4746 : case MCK_Imm: return "MCK_Imm";
4747 : case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg";
4748 : case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg";
4749 : case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg";
4750 : case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP";
4751 : case MCK_MicroMipsMem: return "MCK_MicroMipsMem";
4752 : case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP";
4753 : case MCK_InvNum: return "MCK_InvNum";
4754 : case MCK_JumpTarget: return "MCK_JumpTarget";
4755 : case MCK_MemOffsetSimm10: return "MCK_MemOffsetSimm10";
4756 : case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1";
4757 : case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2";
4758 : case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3";
4759 : case MCK_MemOffsetSimm11: return "MCK_MemOffsetSimm11";
4760 : case MCK_MemOffsetSimm12: return "MCK_MemOffsetSimm12";
4761 : case MCK_MemOffsetSimm16: return "MCK_MemOffsetSimm16";
4762 : case MCK_MemOffsetSimm9: return "MCK_MemOffsetSimm9";
4763 : case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr";
4764 : case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4";
4765 : case MCK_Mem: return "MCK_Mem";
4766 : case MCK_RegList16: return "MCK_RegList16";
4767 : case MCK_RegList: return "MCK_RegList";
4768 : case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2";
4769 : case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg";
4770 : case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg";
4771 : case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg";
4772 : case MCK_ConstantImmz: return "MCK_ConstantImmz";
4773 : case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0";
4774 : case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0";
4775 : case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1";
4776 : case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0";
4777 : case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0";
4778 : case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0";
4779 : case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0";
4780 : case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0";
4781 : case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1";
4782 : case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6";
4783 : case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm";
4784 : case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32";
4785 : case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6";
4786 : case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33";
4787 : case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64";
4788 : case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2";
4789 : case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0";
4790 : case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0";
4791 : case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2";
4792 : case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0";
4793 : case MCK_UImm7_N1: return "MCK_UImm7_N1";
4794 : case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0";
4795 : case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2";
4796 : case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0";
4797 : case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0";
4798 : case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0";
4799 : case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1";
4800 : case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0";
4801 : case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2";
4802 : case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3";
4803 : case MCK_SImm16: return "MCK_SImm16";
4804 : case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed";
4805 : case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed";
4806 : case MCK_UImm16: return "MCK_UImm16";
4807 : case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2";
4808 : case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed";
4809 : case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0";
4810 : case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0";
4811 : case MCK_SImm32: return "MCK_SImm32";
4812 : case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed";
4813 : case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced";
4814 : case NumMatchClassKinds: return "NumMatchClassKinds";
4815 : }
4816 : llvm_unreachable("unhandled MatchClassKind!");
4817 : }
4818 :
4819 : #endif // NDEBUG
4820 0 : uint64_t MipsAsmParser::
4821 : ComputeAvailableFeatures(const FeatureBitset& FB) const {
4822 : uint64_t Features = 0;
4823 0 : if ((FB[Mips::FeatureMips2]))
4824 : Features |= Feature_HasMips2;
4825 0 : if ((FB[Mips::FeatureMips3_32]))
4826 0 : Features |= Feature_HasMips3_32;
4827 0 : if ((FB[Mips::FeatureMips3_32r2]))
4828 0 : Features |= Feature_HasMips3_32r2;
4829 0 : if ((FB[Mips::FeatureMips3]))
4830 0 : Features |= Feature_HasMips3;
4831 0 : if ((!FB[Mips::FeatureMips3]))
4832 0 : Features |= Feature_NotMips3;
4833 0 : if ((FB[Mips::FeatureMips4_32]))
4834 0 : Features |= Feature_HasMips4_32;
4835 0 : if ((!FB[Mips::FeatureMips4_32]))
4836 0 : Features |= Feature_NotMips4_32;
4837 0 : if ((FB[Mips::FeatureMips4_32r2]))
4838 0 : Features |= Feature_HasMips4_32r2;
4839 0 : if ((FB[Mips::FeatureMips5_32r2]))
4840 0 : Features |= Feature_HasMips5_32r2;
4841 0 : if ((FB[Mips::FeatureMips32]))
4842 0 : Features |= Feature_HasMips32;
4843 0 : if ((FB[Mips::FeatureMips32r2]))
4844 0 : Features |= Feature_HasMips32r2;
4845 0 : if ((FB[Mips::FeatureMips32r5]))
4846 0 : Features |= Feature_HasMips32r5;
4847 0 : if ((FB[Mips::FeatureMips32r6]))
4848 0 : Features |= Feature_HasMips32r6;
4849 0 : if ((!FB[Mips::FeatureMips32r6]))
4850 0 : Features |= Feature_NotMips32r6;
4851 0 : if ((FB[Mips::FeatureGP64Bit]))
4852 0 : Features |= Feature_IsGP64bit;
4853 0 : if ((!FB[Mips::FeatureGP64Bit]))
4854 0 : Features |= Feature_IsGP32bit;
4855 0 : if ((FB[Mips::FeaturePTR64Bit]))
4856 0 : Features |= Feature_IsPTR64bit;
4857 0 : if ((!FB[Mips::FeaturePTR64Bit]))
4858 0 : Features |= Feature_IsPTR32bit;
4859 0 : if ((FB[Mips::FeatureMips64]))
4860 0 : Features |= Feature_HasMips64;
4861 0 : if ((!FB[Mips::FeatureMips64]))
4862 0 : Features |= Feature_NotMips64;
4863 0 : if ((FB[Mips::FeatureMips64r2]))
4864 0 : Features |= Feature_HasMips64r2;
4865 0 : if ((FB[Mips::FeatureMips64r5]))
4866 0 : Features |= Feature_HasMips64r5;
4867 0 : if ((FB[Mips::FeatureMips64r6]))
4868 0 : Features |= Feature_HasMips64r6;
4869 0 : if ((!FB[Mips::FeatureMips64r6]))
4870 0 : Features |= Feature_NotMips64r6;
4871 0 : if ((FB[Mips::FeatureMips16]))
4872 0 : Features |= Feature_InMips16Mode;
4873 0 : if ((!FB[Mips::FeatureMips16]))
4874 0 : Features |= Feature_NotInMips16Mode;
4875 0 : if ((FB[Mips::FeatureCnMips]))
4876 0 : Features |= Feature_HasCnMips;
4877 0 : if ((!FB[Mips::FeatureCnMips]))
4878 0 : Features |= Feature_NotCnMips;
4879 0 : if ((FB[Mips::FeatureSym32]))
4880 0 : Features |= Feature_IsSym32;
4881 0 : if ((!FB[Mips::FeatureSym32]))
4882 0 : Features |= Feature_IsSym64;
4883 0 : if ((!FB[Mips::FeatureMips16]))
4884 0 : Features |= Feature_HasStdEnc;
4885 0 : if ((FB[Mips::FeatureMicroMips]))
4886 0 : Features |= Feature_InMicroMips;
4887 0 : if ((!FB[Mips::FeatureMicroMips]))
4888 0 : Features |= Feature_NotInMicroMips;
4889 0 : if ((FB[Mips::FeatureEVA]))
4890 0 : Features |= Feature_HasEVA;
4891 0 : if ((FB[Mips::FeatureMSA]))
4892 0 : Features |= Feature_HasMSA;
4893 0 : if ((!FB[Mips::FeatureMadd4]))
4894 0 : Features |= Feature_HasMadd4;
4895 0 : if ((FB[Mips::FeatureMT]))
4896 0 : Features |= Feature_HasMT;
4897 0 : if ((FB[Mips::FeatureUseIndirectJumpsHazard]))
4898 0 : Features |= Feature_UseIndirectJumpsHazard;
4899 0 : if ((!FB[Mips::FeatureUseIndirectJumpsHazard]))
4900 0 : Features |= Feature_NoIndirectJumpGuards;
4901 0 : if ((FB[Mips::FeatureCRC]))
4902 0 : Features |= Feature_HasCRC;
4903 0 : if ((FB[Mips::FeatureVirt]))
4904 0 : Features |= Feature_HasVirt;
4905 0 : if ((FB[Mips::FeatureGINV]))
4906 0 : Features |= Feature_HasGINV;
4907 0 : if ((FB[Mips::FeatureFP64Bit]))
4908 0 : Features |= Feature_IsFP64bit;
4909 0 : if ((!FB[Mips::FeatureFP64Bit]))
4910 0 : Features |= Feature_NotFP64bit;
4911 0 : if ((FB[Mips::FeatureSingleFloat]))
4912 0 : Features |= Feature_IsSingleFloat;
4913 0 : if ((!FB[Mips::FeatureSingleFloat]))
4914 0 : Features |= Feature_IsNotSingleFloat;
4915 0 : if ((!FB[Mips::FeatureSoftFloat]))
4916 0 : Features |= Feature_IsNotSoftFloat;
4917 0 : if ((FB[Mips::FeatureDSP]))
4918 0 : Features |= Feature_HasDSP;
4919 0 : if ((FB[Mips::FeatureDSPR2]))
4920 0 : Features |= Feature_HasDSPR2;
4921 0 : if ((FB[Mips::FeatureDSPR3]))
4922 0 : Features |= Feature_HasDSPR3;
4923 0 : return Features;
4924 : }
4925 :
4926 35721 : static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser,
4927 : unsigned Kind,
4928 : const OperandVector &Operands,
4929 : uint64_t &ErrorInfo) {
4930 : assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4931 35721 : const uint8_t *Converter = ConversionTable[Kind];
4932 124347 : for (const uint8_t *p = Converter; *p; p+= 2) {
4933 88626 : switch (*p) {
4934 617 : case CVT_Tied: {
4935 617 : unsigned OpIdx = *(p+1);
4936 : assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
4937 : std::begin(TiedAsmOperandTable)) &&
4938 : "Tied operand not found");
4939 617 : unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
4940 617 : unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
4941 617 : if (OpndNum1 != OpndNum2) {
4942 2 : auto &SrcOp1 = Operands[OpndNum1];
4943 2 : auto &SrcOp2 = Operands[OpndNum2];
4944 2 : if (SrcOp1->isReg() && SrcOp2->isReg()) {
4945 0 : if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
4946 0 : ErrorInfo = OpndNum2;
4947 0 : return false;
4948 : }
4949 : }
4950 : }
4951 : break;
4952 : }
4953 : default:
4954 : break;
4955 : }
4956 : }
4957 : return true;
4958 : }
4959 :
4960 : static const char *const MnemonicTable =
4961 : "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
4962 : "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad"
4963 : "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t"
4964 : "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010"
4965 : "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010"
4966 : "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005"
4967 : "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010"
4968 : "adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv.h\006addv.w\007addvi.b"
4969 : "\007addvi.d\007addvi.h\007addvi.w\005addwc\005align\006aluipc\003and\005"
4970 : "and.v\005and16\004andi\006andi.b\006andi16\006append\010asub_s.b\010asu"
4971 : "b_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asub_u.d\010asub_u.h\010as"
4972 : "ub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007ave_s.h\007ave_s.w\007a"
4973 : "ve_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_s.b\010aver_s.d\010aver"
4974 : "_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver_u.h\010aver_u.w\001b\003"
4975 : "b16\005baddu\003bal\004balc\006balign\005bbit0\007bbit032\005bbit1\007b"
4976 : "bit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004bc1f\005bc1fl\006bc1nez\007"
4977 : "bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc\006bc2nez\007bc2nezc\006b"
4978 : "clr.b\006bclr.d\006bclr.h\006bclr.w\007bclri.b\007bclri.d\007bclri.h\007"
4979 : "bclri.w\003beq\004beqc\004beql\004beqz\006beqz16\007beqzalc\005beqzc\007"
4980 : "beqzc16\005beqzl\003bge\004bgec\004bgel\004bgeu\005bgeuc\005bgeul\004bg"
4981 : "ez\006bgezal\007bgezalc\007bgezall\007bgezals\005bgezc\005bgezl\003bgt\004"
4982 : "bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc\005bgtzc\005bgtzl\007binsl.b\007"
4983 : "binsl.d\007binsl.h\007binsl.w\010binsli.b\010binsli.d\010binsli.h\010bi"
4984 : "nsli.w\007binsr.b\007binsr.d\007binsr.h\007binsr.w\010binsri.b\010binsr"
4985 : "i.d\010binsri.h\010binsri.w\006bitrev\007bitswap\003ble\004blel\004bleu"
4986 : "\005bleul\004blez\007blezalc\005blezc\005blezl\003blt\004bltc\004bltl\004"
4987 : "bltu\005bltuc\005bltul\004bltz\006bltzal\007bltzalc\007bltzall\007bltza"
4988 : "ls\005bltzc\005bltzl\006bmnz.v\007bmnzi.b\005bmz.v\006bmzi.b\003bne\004"
4989 : "bnec\006bneg.b\006bneg.d\006bneg.h\006bneg.w\007bnegi.b\007bnegi.d\007b"
4990 : "negi.h\007bnegi.w\004bnel\004bnez\006bnez16\007bnezalc\005bnezc\007bnez"
4991 : "c16\005bnezl\004bnvc\005bnz.b\005bnz.d\005bnz.h\005bnz.v\005bnz.w\004bo"
4992 : "vc\010bposge32\tbposge32c\005break\007break16\006bsel.v\007bseli.b\006b"
4993 : "set.b\006bset.d\006bset.h\006bset.w\007bseti.b\007bseti.d\007bseti.h\007"
4994 : "bseti.w\005bteqz\005btnez\004bz.b\004bz.d\004bz.h\004bz.v\004bz.w\006c."
4995 : "eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le.d\006c.le.s\006c.lt.d\006c.lt."
4996 : "s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.ngl.s\010c.ngle.d\010c.ngle.s\007"
4997 : "c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole.s\007c.olt.d\007c.olt.s\007c.seq"
4998 : ".d\007c.seq.s\006c.sf.d\006c.sf.s\007c.ueq.d\007c.ueq.s\007c.ule.d\007c"
4999 : ".ule.s\007c.ult.d\007c.ult.s\006c.un.d\006c.un.s\005cache\006cachee\010"
5000 : "ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w.s\005ceq.b\005ceq.d\005ceq.h"
5001 : "\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006ceqi.w\004cfc1\004cfc2\006cf"
5002 : "cmsa\005cftc1\004cins\006cins32\007class.d\007class.s\007cle_s.b\007cle"
5003 : "_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u.d\007cle_u.h\007cle_u.w\010"
5004 : "clei_s.b\010clei_s.d\010clei_s.h\010clei_s.w\010clei_u.b\010clei_u.d\010"
5005 : "clei_u.h\010clei_u.w\003clo\007clt_s.b\007clt_s.d\007clt_s.h\007clt_s.w"
5006 : "\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u.w\010clti_s.b\010clti_s.d\010"
5007 : "clti_s.h\010clti_s.w\010clti_u.b\010clti_u.d\010clti_u.h\010clti_u.w\003"
5008 : "clz\003cmp\010cmp.af.d\010cmp.af.s\010cmp.eq.d\tcmp.eq.ph\010cmp.eq.s\010"
5009 : "cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp.lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp"
5010 : ".saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq.s\tcmp.sle.d\tcmp.sle.s\tcmp.slt."
5011 : "d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\ncmp.sule.d\ncmp.sule.s\ncmp.sult."
5012 : "d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tcmp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tc"
5013 : "mp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp.un.d\010cmp.un.s\014cmpgdu.eq.qb\014"
5014 : "cmpgdu.le.qb\014cmpgdu.lt.qb\013cmpgu.eq.qb\013cmpgu.le.qb\013cmpgu.lt."
5015 : "qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\ncmpu.lt.qb\010copy_s.b\010copy_s.d\010"
5016 : "copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\006crc32b\007c"
5017 : "rc32cb\007crc32cd\007crc32ch\007crc32cw\006crc32d\006crc32h\006crc32w\004"
5018 : "ctc1\004ctc2\006ctcmsa\005cttc1\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt"
5019 : ".l.d\007cvt.l.s\010cvt.ps.s\007cvt.s.d\007cvt.s.l\010cvt.s.pl\010cvt.s."
5020 : "pu\007cvt.s.w\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005daddu"
5021 : "\004dahi\006dalign\004dati\004daui\010dbitswap\004dclo\004dclz\004ddiv\005"
5022 : "ddivu\005deret\004dext\005dextm\005dextu\002di\004dins\005dinsm\005dins"
5023 : "u\003div\005div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007div_s.w\007"
5024 : "div_u.b\007div_u.d\007div_u.h\007div_u.w\004divu\003dla\003dli\004dlsa\005"
5025 : "dmfc0\005dmfc1\005dmfc2\006dmfgc0\004dmod\005dmodu\003dmt\005dmtc0\005d"
5026 : "mtc1\005dmtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005"
5027 : "dmult\006dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010do"
5028 : "tp_s.w\010dotp_u.d\010dotp_u.h\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpad"
5029 : "d_s.h\tdpadd_s.w\tdpadd_u.d\tdpadd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpa"
5030 : "q_sa.l.w\014dpaqx_s.w.ph\015dpaqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax"
5031 : ".w.ph\004dpop\010dps.w.ph\013dpsq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph"
5032 : "\015dpsqx_sa.w.ph\ndpsu.h.qbl\ndpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_"
5033 : "s.w\tdpsub_u.d\tdpsub_u.h\tdpsub_u.w\tdpsx.w.ph\004drem\005dremu\004dro"
5034 : "l\004dror\005drotr\007drotr32\006drotrv\004dsbh\004dshd\004dsll\006dsll"
5035 : "32\005dsllv\004dsra\006dsra32\005dsrav\004dsrl\006dsrl32\005dsrlv\004ds"
5036 : "ub\005dsubi\005dsubu\003dvp\004dvpe\003ehb\002ei\003emt\004eret\006eret"
5037 : "nc\003evp\004evpe\003ext\004extp\006extpdp\007extpdpv\005extpv\006extr."
5038 : "w\010extr_r.w\textr_rs.w\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\t"
5039 : "extrv_s.h\004exts\006exts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006"
5040 : "fceq.d\006fceq.w\010fclass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006"
5041 : "fclt.w\006fcne.d\006fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007"
5042 : "fcule.d\007fcule.w\007fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d"
5043 : "\007fcune.w\006fdiv.d\006fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fex"
5044 : "p2.w\010fexupl.d\010fexupl.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_"
5045 : "s.w\tffint_u.d\tffint_u.w\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fi"
5046 : "ll.b\006fill.d\006fill.h\006fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfl"
5047 : "oor.l.s\tfloor.w.d\tfloor.w.s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w"
5048 : "\010fmax_a.d\010fmax_a.w\006fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007"
5049 : "fmsub.d\007fmsub.w\006fmul.d\006fmul.w\004fork\006frcp.d\006frcp.w\007f"
5050 : "rint.d\007frint.w\010frsqrt.d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d"
5051 : "\006fseq.w\006fsle.d\006fsle.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006"
5052 : "fsor.d\006fsor.w\007fsqrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007"
5053 : "fsueq.w\007fsule.d\007fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w"
5054 : "\007fsune.d\007fsune.w\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005f"
5055 : "tq.h\005ftq.w\nftrunc_s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005"
5056 : "ginvt\010hadd_s.d\010hadd_s.h\010hadd_s.w\010hadd_u.d\010hadd_u.h\010ha"
5057 : "dd_u.w\010hsub_s.d\010hsub_s.h\010hsub_s.w\010hsub_u.d\010hsub_u.h\010h"
5058 : "sub_u.w\007hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl."
5059 : "b\006ilvl.d\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilv"
5060 : "od.w\006ilvr.b\006ilvr.d\006ilvr.h\006ilvr.w\003ins\010insert.b\010inse"
5061 : "rt.d\010insert.h\010insert.w\004insv\007insve.b\007insve.d\007insve.h\007"
5062 : "insve.w\001j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007"
5063 : "jalrs16\004jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiu"
5064 : "sp\003jrc\005jrc16\njrcaddiusp\003l.d\003l.s\002la\004lapc\002lb\003lbe"
5065 : "\003lbu\005lbu16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004"
5066 : "ldc1\004ldc2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc"
5067 : "\003ldr\005ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004l"
5068 : "i.d\004li.s\004li16\002ll\003lld\003lle\003lsa\003lui\005luxc1\002lw\004"
5069 : "lw16\004lwc1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005l"
5070 : "wm32\003lwp\004lwpc\003lwr\004lwre\003lwu\005lwupc\003lwx\005lwxc1\004l"
5071 : "wxs\004madd\006madd.d\006madd.s\010madd_q.h\010madd_q.w\007maddf.d\007m"
5072 : "addf.s\tmaddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007maddv.d\007maddv.h\007"
5073 : "maddv.w\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005"
5074 : "max.d\005max.s\007max_a.b\007max_a.d\007max_a.h\007max_a.w\007max_s.b\007"
5075 : "max_s.d\007max_s.h\007max_s.w\007max_u.b\007max_u.d\007max_u.h\007max_u"
5076 : ".w\006maxa.d\006maxa.s\010maxi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010"
5077 : "maxi_u.b\010maxi_u.d\010maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005"
5078 : "mfgc0\005mfhc0\005mfhc1\005mfhc2\006mfhgc0\004mfhi\006mfhi16\004mflo\006"
5079 : "mflo16\006mftacx\005mftc0\005mftc1\006mftdsp\006mftgpr\006mfthc1\005mft"
5080 : "hi\005mftlo\004mftr\005min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007"
5081 : "min_a.w\007min_s.b\007min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u"
5082 : ".d\007min_u.h\007min_u.w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010"
5083 : "mini_s.h\010mini_s.w\010mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003"
5084 : "mod\007mod_s.b\007mod_s.d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007"
5085 : "mod_u.h\007mod_u.w\006modsub\004modu\005mov.d\005mov.s\004move\006move."
5086 : "v\006move16\005movep\004movf\006movf.d\006movf.s\004movn\006movn.d\006m"
5087 : "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006"
5088 : "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q"
5089 : ".h\tmsubr_q.w\005msubu\007msubv.b\007msubv.d\007msubv.h\007msubv.w\004m"
5090 : "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt"
5091 : "hi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004mtp2\006"
5092 : "mttacx\005mttc0\005mttc1\006mttdsp\006mttgpr\006mtthc1\005mtthi\005mttl"
5093 : "o\004mttr\003muh\004muhu\003mul\005mul.d\006mul.ph\005mul.s\007mul_q.h\007"
5094 : "mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016muleu_s.ph.qbl"
5095 : "\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\tmulq_s.ph\010"
5096 : "mulq_s.w\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015mulsaq_s.w.ph\004mult\005"
5097 : "multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006mulv.w\003neg\005neg.d\005"
5098 : "neg.s\004negu\006nloc.b\006nloc.d\006nloc.h\006nloc.w\006nlzc.b\006nlzc"
5099 : ".d\006nlzc.h\006nlzc.w\007nmadd.d\007nmadd.s\007nmsub.d\007nmsub.s\003n"
5100 : "op\003nor\005nor.v\006nori.b\003not\005not16\002or\004or.v\004or16\003o"
5101 : "ri\005ori.b\tpackrl.ph\005pause\007pckev.b\007pckev.d\007pckev.h\007pck"
5102 : "ev.w\007pckod.b\007pckod.d\007pckod.h\007pckod.w\006pcnt.b\006pcnt.d\006"
5103 : "pcnt.h\006pcnt.w\007pick.ph\007pick.qb\006pll.ps\006plu.ps\003pop\014pr"
5104 : "eceq.w.phl\014preceq.w.phr\016precequ.ph.qbl\017precequ.ph.qbla\016prec"
5105 : "equ.ph.qbr\017precequ.ph.qbra\015preceu.ph.qbl\016preceu.ph.qbla\015pre"
5106 : "ceu.ph.qbr\016preceu.ph.qbra\013precr.qb.ph\016precr_sra.ph.w\020precr_"
5107 : "sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016precrq_rs.ph.w\017precrqu_"
5108 : "s.qb.ph\004pref\005prefe\005prefx\007prepend\nraddu.w.qb\005rddsp\005rd"
5109 : "hwr\006rdpgpr\007recip.d\007recip.s\003rem\004remu\007repl.ph\007repl.q"
5110 : "b\010replv.ph\010replv.qb\006rint.d\006rint.s\003rol\003ror\004rotr\005"
5111 : "rotrv\tround.l.d\tround.l.s\tround.w.d\tround.w.s\007rsqrt.d\007rsqrt.s"
5112 : "\003s.d\003s.s\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007"
5113 : "sat_u.d\007sat_u.h\007sat_u.w\002sb\004sb16\003sbe\002sc\003scd\003sce\002"
5114 : "sd\005sdbbp\007sdbbp16\004sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003"
5115 : "seb\003seh\005sel.d\005sel.s\006seleqz\010seleqz.d\010seleqz.s\006selne"
5116 : "z\010selnez.d\010selnez.s\003seq\004seqi\003sgt\004sgtu\002sh\004sh16\003"
5117 : "she\005shf.b\005shf.h\005shf.w\005shilo\006shilov\007shll.ph\007shll.qb"
5118 : "\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\nshllv_s.ph\tshllv_s.w\007"
5119 : "shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010shra_r.w\010shrav.ph\010shr"
5120 : "av.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007shrl.ph\007shrl.qb\010shrlv"
5121 : ".ph\010shrlv.qb\005sld.b\005sld.d\005sld.h\005sld.w\006sldi.b\006sldi.d"
5122 : "\006sldi.h\006sldi.w\003sll\005sll.b\005sll.d\005sll.h\005sll.w\005sll1"
5123 : "6\006slli.b\006slli.d\006slli.h\006slli.w\004sllv\003slt\004slti\005slt"
5124 : "iu\004sltu\003sne\004snei\007splat.b\007splat.d\007splat.h\007splat.w\010"
5125 : "splati.b\010splati.d\010splati.h\010splati.w\006sqrt.d\006sqrt.s\003sra"
5126 : "\005sra.b\005sra.d\005sra.h\005sra.w\006srai.b\006srai.d\006srai.h\006s"
5127 : "rai.w\006srar.b\006srar.d\006srar.h\006srar.w\007srari.b\007srari.d\007"
5128 : "srari.h\007srari.w\004srav\003srl\005srl.b\005srl.d\005srl.h\005srl.w\005"
5129 : "srl16\006srli.b\006srli.d\006srli.h\006srli.w\006srlr.b\006srlr.d\006sr"
5130 : "lr.h\006srlr.w\007srlri.b\007srlri.d\007srlri.h\007srlri.w\004srlv\005s"
5131 : "snop\004st.b\004st.d\004st.h\004st.w\003sub\005sub.d\005sub.s\007subq.p"
5132 : "h\tsubq_s.ph\010subq_s.w\010subqh.ph\007subqh.w\nsubqh_r.ph\tsubqh_r.w\010"
5133 : "subs_s.b\010subs_s.d\010subs_s.h\010subs_s.w\010subs_u.b\010subs_u.d\010"
5134 : "subs_u.h\010subs_u.w\nsubsus_u.b\nsubsus_u.d\nsubsus_u.h\nsubsus_u.w\ns"
5135 : "ubsuu_s.b\nsubsuu_s.d\nsubsuu_s.h\nsubsuu_s.w\004subu\007subu.ph\007sub"
5136 : "u.qb\006subu16\tsubu_s.ph\tsubu_s.qb\010subuh.qb\nsubuh_r.qb\006subv.b\006"
5137 : "subv.d\006subv.h\006subv.w\007subvi.b\007subvi.d\007subvi.h\007subvi.w\005"
5138 : "suxc1\002sw\004sw16\004swc1\004swc2\004swc3\003swe\003swl\004swle\003sw"
5139 : "m\005swm16\005swm32\003swp\003swr\004swre\005swxc1\004sync\005synci\nsy"
5140 : "nciobdma\005syncs\005syncw\006syncws\007syscall\003teq\004teqi\003tge\004"
5141 : "tgei\005tgeiu\004tgeu\007tlbginv\010tlbginvf\005tlbgp\005tlbgr\006tlbgw"
5142 : "i\006tlbgwr\006tlbinv\007tlbinvf\004tlbp\004tlbr\005tlbwi\005tlbwr\003t"
5143 : "lt\004tlti\005tltiu\004tltu\003tne\004tnei\ttrunc.l.d\ttrunc.l.s\ttrunc"
5144 : ".w.d\ttrunc.w.s\003ulh\004ulhu\003ulw\003ush\003usw\006v3mulu\004vmm0\005"
5145 : "vmulu\006vshf.b\006vshf.d\006vshf.h\006vshf.w\004wait\005wrdsp\006wrpgp"
5146 : "r\004wsbh\003xor\005xor.v\005xor16\004xori\006xori.b\005yield";
5147 :
5148 : namespace {
5149 : struct MatchEntry {
5150 : uint16_t Mnemonic;
5151 : uint16_t Opcode;
5152 : uint16_t ConvertFn;
5153 : uint64_t RequiredFeatures;
5154 : uint8_t Classes[8];
5155 0 : StringRef getMnemonic() const {
5156 273604 : return StringRef(MnemonicTable + Mnemonic + 1,
5157 273604 : MnemonicTable[Mnemonic]);
5158 : }
5159 : };
5160 :
5161 : // Predicate for searching for an opcode.
5162 : struct LessOpcode {
5163 0 : bool operator()(const MatchEntry &LHS, StringRef RHS) {
5164 0 : return LHS.getMnemonic() < RHS;
5165 : }
5166 0 : bool operator()(StringRef LHS, const MatchEntry &RHS) {
5167 0 : return LHS < RHS.getMnemonic();
5168 : }
5169 : bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
5170 : return LHS.getMnemonic() < RHS.getMnemonic();
5171 : }
5172 : };
5173 : } // end anonymous namespace.
5174 :
5175 : static const MatchEntry MatchTable0[] = {
5176 : { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5177 : { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5178 : { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5179 : { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5180 : { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5181 : { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5182 : { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5183 : { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5184 : { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5185 : { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5186 : { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5187 : { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5188 : { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5189 : { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5190 : { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5191 : { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5192 : { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5193 : { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5194 : { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5195 : { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5196 : { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5197 : { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5198 : { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5199 : { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5200 : { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5201 : { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5202 : { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5203 : { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5204 : { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5205 : { 55 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5206 : { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5207 : { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5208 : { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5209 : { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5210 : { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5211 : { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5212 : { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5213 : { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5214 : { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, },
5215 : { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
5216 : { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5217 : { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5218 : { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5219 : { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, },
5220 : { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
5221 : { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5222 : { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5223 : { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5224 : { 98 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5225 : { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5226 : { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5227 : { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5228 : { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
5229 : { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
5230 : { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5231 : { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
5232 : { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
5233 : { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5234 : { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5235 : { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5236 : { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5237 : { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5238 : { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5239 : { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5240 : { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5241 : { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5242 : { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5243 : { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5244 : { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5245 : { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5246 : { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5247 : { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5248 : { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5249 : { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5250 : { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5251 : { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5252 : { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5253 : { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5254 : { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5255 : { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5256 : { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5257 : { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5258 : { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5259 : { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5260 : { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5261 : { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5262 : { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5263 : { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5264 : { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5265 : { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5266 : { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
5267 : { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5268 : { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5269 : { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5270 : { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5271 : { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5272 : { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5273 : { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5274 : { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5275 : { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5276 : { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5277 : { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5278 : { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5279 : { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5280 : { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5281 : { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5282 : { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5283 : { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5284 : { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5285 : { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5286 : { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5287 : { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5288 : { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5289 : { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5290 : { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5291 : { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5292 : { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5293 : { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5294 : { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5295 : { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5296 : { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5297 : { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5298 : { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5299 : { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5300 : { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
5301 : { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5302 : { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5303 : { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5304 : { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5305 : { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5306 : { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5307 : { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
5308 : { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5309 : { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5310 : { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5311 : { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5312 : { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5313 : { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5314 : { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
5315 : { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5316 : { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5317 : { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5318 : { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5319 : { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5320 : { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5321 : { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5322 : { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5323 : { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5324 : { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5325 : { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5326 : { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5327 : { 507 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5328 : { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5329 : { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5330 : { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5331 : { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5332 : { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5333 : { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5334 : { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5335 : { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5336 : { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5337 : { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5338 : { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5339 : { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5340 : { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5341 : { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5342 : { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5343 : { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5344 : { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5345 : { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5346 : { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5347 : { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5348 : { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5349 : { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5350 : { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5351 : { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5352 : { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5353 : { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5354 : { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5355 : { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5356 : { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5357 : { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5358 : { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
5359 : { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget }, },
5360 : { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, 0, { MCK_JumpTarget }, },
5361 : { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5362 : { 734 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
5363 : { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
5364 : { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5365 : { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5366 : { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5367 : { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
5368 : { 744 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, },
5369 : { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
5370 : { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
5371 : { 753 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5372 : { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5373 : { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5374 : { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5375 : { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5376 : { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5377 : { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5378 : { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5379 : { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5380 : { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
5381 : { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
5382 : { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5383 : { 803 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5384 : { 811 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5385 : { 811 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
5386 : { 811 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5387 : { 811 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5388 : { 816 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5389 : { 816 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5390 : { 822 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5391 : { 829 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5392 : { 837 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5393 : { 837 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
5394 : { 837 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5395 : { 837 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5396 : { 842 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5397 : { 842 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5398 : { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5399 : { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5400 : { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5401 : { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5402 : { 878 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5403 : { 885 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5404 : { 892 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5405 : { 899 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5406 : { 906 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5407 : { 914 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5408 : { 922 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5409 : { 930 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5410 : { 938 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5411 : { 938 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5412 : { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5413 : { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5414 : { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5415 : { 942 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5416 : { 947 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5417 : { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5418 : { 952 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5419 : { 952 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5420 : { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5421 : { 952 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5422 : { 957 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5423 : { 957 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5424 : { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5425 : { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5426 : { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5427 : { 972 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5428 : { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5429 : { 972 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5430 : { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5431 : { 986 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5432 : { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5433 : { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5434 : { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5435 : { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5436 : { 996 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5437 : { 1001 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5438 : { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5439 : { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5440 : { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5441 : { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5442 : { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5443 : { 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5444 : { 1017 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5445 : { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5446 : { 1023 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5447 : { 1023 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5448 : { 1028 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5449 : { 1028 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5450 : { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5451 : { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5452 : { 1043 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5453 : { 1051 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5454 : { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5455 : { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5456 : { 1059 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5457 : { 1065 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5458 : { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5459 : { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5460 : { 1075 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5461 : { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5462 : { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5463 : { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5464 : { 1085 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5465 : { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5466 : { 1091 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5467 : { 1091 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5468 : { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5469 : { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5470 : { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5471 : { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5472 : { 1104 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5473 : { 1110 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5474 : { 1116 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5475 : { 1124 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5476 : { 1132 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5477 : { 1140 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5478 : { 1148 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5479 : { 1157 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5480 : { 1166 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5481 : { 1175 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5482 : { 1184 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5483 : { 1192 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5484 : { 1200 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5485 : { 1208 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5486 : { 1216 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5487 : { 1225 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5488 : { 1234 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5489 : { 1243 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5490 : { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5491 : { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5492 : { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5493 : { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5494 : { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5495 : { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5496 : { 1271 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5497 : { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5498 : { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5499 : { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5500 : { 1281 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5501 : { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5502 : { 1287 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5503 : { 1287 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5504 : { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5505 : { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5506 : { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5507 : { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5508 : { 1300 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5509 : { 1306 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5510 : { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5511 : { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5512 : { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5513 : { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5514 : { 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5515 : { 1321 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5516 : { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5517 : { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5518 : { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5519 : { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5520 : { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5521 : { 1331 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5522 : { 1337 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5523 : { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5524 : { 1343 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5525 : { 1343 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5526 : { 1348 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5527 : { 1348 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5528 : { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5529 : { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5530 : { 1363 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5531 : { 1371 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5532 : { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5533 : { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5534 : { 1379 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5535 : { 1385 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5536 : { 1391 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5537 : { 1398 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5538 : { 1406 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5539 : { 1412 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5540 : { 1419 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5541 : { 1419 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5542 : { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5543 : { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5544 : { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5545 : { 1423 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5546 : { 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5547 : { 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5548 : { 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5549 : { 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5550 : { 1456 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5551 : { 1464 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5552 : { 1472 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5553 : { 1480 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5554 : { 1488 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5555 : { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5556 : { 1493 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5557 : { 1493 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5558 : { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5559 : { 1493 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5560 : { 1498 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5561 : { 1498 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5562 : { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5563 : { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5564 : { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5565 : { 1513 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5566 : { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5567 : { 1513 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5568 : { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5569 : { 1527 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5570 : { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5571 : { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5572 : { 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5573 : { 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5574 : { 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5575 : { 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5576 : { 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5577 : { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5578 : { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5579 : { 1573 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, { MCK_JumpTarget }, },
5580 : { 1573 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, Feature_HasDSP|Feature_NotInMicroMips, { MCK_JumpTarget }, },
5581 : { 1582 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasDSPR3, { MCK_JumpTarget }, },
5582 : { 1592 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
5583 : { 1592 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, Feature_InMicroMips, { }, },
5584 : { 1592 /* break */, Mips::Break16, Convert_NoOperands, Feature_InMips16Mode, { MCK_0 }, },
5585 : { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
5586 : { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
5587 : { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5588 : { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5589 : { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5590 : { 1598 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, },
5591 : { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, },
5592 : { 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5593 : { 1613 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5594 : { 1621 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5595 : { 1628 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5596 : { 1635 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5597 : { 1642 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5598 : { 1649 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5599 : { 1657 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5600 : { 1665 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5601 : { 1673 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5602 : { 1681 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
5603 : { 1681 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5604 : { 1687 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
5605 : { 1687 /* btnez */, Mips::Btnez16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5606 : { 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5607 : { 1698 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5608 : { 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5609 : { 1708 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5610 : { 1713 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5611 : { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5612 : { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5613 : { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5614 : { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5615 : { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5616 : { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5617 : { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5618 : { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5619 : { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5620 : { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5621 : { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5622 : { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5623 : { 1732 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5624 : { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5625 : { 1732 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5626 : { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5627 : { 1732 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5628 : { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5629 : { 1732 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5630 : { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5631 : { 1738 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5632 : { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5633 : { 1738 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5634 : { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5635 : { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5636 : { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5637 : { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5638 : { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5639 : { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5640 : { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5641 : { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5642 : { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5643 : { 1751 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5644 : { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5645 : { 1751 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5646 : { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5647 : { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5648 : { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5649 : { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5650 : { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5651 : { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5652 : { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5653 : { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5654 : { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5655 : { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5656 : { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5657 : { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5658 : { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5659 : { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5660 : { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5661 : { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5662 : { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5663 : { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5664 : { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5665 : { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5666 : { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5667 : { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5668 : { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5669 : { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5670 : { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5671 : { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5672 : { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5673 : { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5674 : { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5675 : { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5676 : { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5677 : { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5678 : { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5679 : { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5680 : { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5681 : { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5682 : { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5683 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5684 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5685 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5686 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5687 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5688 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5689 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5690 : { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5691 : { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5692 : { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5693 : { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5694 : { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5695 : { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5696 : { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5697 : { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5698 : { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5699 : { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5700 : { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5701 : { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5702 : { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5703 : { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5704 : { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5705 : { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5706 : { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5707 : { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5708 : { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5709 : { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5710 : { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5711 : { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5712 : { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5713 : { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5714 : { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5715 : { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5716 : { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5717 : { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5718 : { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5719 : { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5720 : { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5721 : { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5722 : { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5723 : { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5724 : { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5725 : { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5726 : { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5727 : { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5728 : { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5729 : { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5730 : { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5731 : { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5732 : { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5733 : { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5734 : { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5735 : { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5736 : { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5737 : { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5738 : { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5739 : { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5740 : { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5741 : { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5742 : { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5743 : { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5744 : { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5745 : { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5746 : { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5747 : { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5748 : { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5749 : { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5750 : { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5751 : { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5752 : { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5753 : { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5754 : { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5755 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5756 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5757 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5758 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5759 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5760 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5761 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5762 : { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5763 : { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5764 : { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5765 : { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5766 : { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5767 : { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5768 : { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5769 : { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5770 : { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5771 : { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5772 : { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5773 : { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5774 : { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5775 : { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5776 : { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5777 : { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5778 : { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5779 : { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5780 : { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5781 : { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5782 : { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5783 : { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5784 : { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5785 : { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5786 : { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5787 : { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5788 : { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5789 : { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5790 : { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5791 : { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5792 : { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5793 : { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5794 : { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5795 : { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5796 : { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5797 : { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5798 : { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5799 : { 1955 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5800 : { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5801 : { 1955 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5802 : { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5803 : { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
5804 : { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
5805 : { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
5806 : { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
5807 : { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
5808 : { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
5809 : { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5810 : { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5811 : { 1984 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
5812 : { 1984 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
5813 : { 1993 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
5814 : { 1993 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
5815 : { 1993 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
5816 : { 1993 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
5817 : { 2002 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5818 : { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5819 : { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5820 : { 2011 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5821 : { 2017 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5822 : { 2023 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5823 : { 2029 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5824 : { 2035 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5825 : { 2042 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5826 : { 2049 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5827 : { 2056 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5828 : { 2063 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
5829 : { 2063 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
5830 : { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
5831 : { 2073 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
5832 : { 2080 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
5833 : { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
5834 : { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
5835 : { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
5836 : { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
5837 : { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
5838 : { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
5839 : { 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5840 : { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5841 : { 2106 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5842 : { 2106 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5843 : { 2114 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5844 : { 2122 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5845 : { 2130 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5846 : { 2138 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5847 : { 2146 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5848 : { 2154 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5849 : { 2162 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5850 : { 2170 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5851 : { 2178 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5852 : { 2187 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5853 : { 2196 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5854 : { 2205 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5855 : { 2214 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5856 : { 2223 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5857 : { 2232 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5858 : { 2241 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5859 : { 2250 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5860 : { 2250 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5861 : { 2250 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5862 : { 2250 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5863 : { 2254 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5864 : { 2262 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5865 : { 2270 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5866 : { 2278 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5867 : { 2286 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5868 : { 2294 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5869 : { 2302 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5870 : { 2310 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5871 : { 2318 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5872 : { 2327 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5873 : { 2336 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5874 : { 2345 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
5875 : { 2354 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5876 : { 2363 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5877 : { 2372 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5878 : { 2381 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5879 : { 2390 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5880 : { 2390 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5881 : { 2390 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5882 : { 2390 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5883 : { 2394 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
5884 : { 2398 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5885 : { 2398 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5886 : { 2407 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5887 : { 2407 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5888 : { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5889 : { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5890 : { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5891 : { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5892 : { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5893 : { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5894 : { 2444 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5895 : { 2444 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5896 : { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5897 : { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5898 : { 2463 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5899 : { 2463 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5900 : { 2472 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5901 : { 2472 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5902 : { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5903 : { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5904 : { 2491 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5905 : { 2491 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5906 : { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5907 : { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5908 : { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5909 : { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5910 : { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5911 : { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5912 : { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5913 : { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5914 : { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5915 : { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5916 : { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5917 : { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5918 : { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5919 : { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5920 : { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5921 : { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5922 : { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5923 : { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5924 : { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5925 : { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5926 : { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5927 : { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5928 : { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5929 : { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5930 : { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5931 : { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5932 : { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5933 : { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5934 : { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5935 : { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5936 : { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5937 : { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5938 : { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5939 : { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5940 : { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5941 : { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5942 : { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5943 : { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5944 : { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5945 : { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5946 : { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5947 : { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5948 : { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5949 : { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5950 : { 2726 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5951 : { 2726 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5952 : { 2735 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5953 : { 2735 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5954 : { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5955 : { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5956 : { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5957 : { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5958 : { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5959 : { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5960 : { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5961 : { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5962 : { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5963 : { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5964 : { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5965 : { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5966 : { 2819 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
5967 : { 2819 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
5968 : { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5969 : { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5970 : { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5971 : { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5972 : { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5973 : { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5974 : { 2857 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
5975 : { 2866 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
5976 : { 2875 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
5977 : { 2884 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
5978 : { 2893 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
5979 : { 2902 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
5980 : { 2911 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
5981 : { 2920 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5982 : { 2927 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5983 : { 2935 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5984 : { 2943 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5985 : { 2951 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5986 : { 2959 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5987 : { 2966 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5988 : { 2973 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5989 : { 2980 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
5990 : { 2980 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
5991 : { 2985 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
5992 : { 2990 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
5993 : { 2997 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
5994 : { 3003 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5995 : { 3003 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5996 : { 3011 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
5997 : { 3011 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
5998 : { 3011 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
5999 : { 3011 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6000 : { 3019 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6001 : { 3019 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6002 : { 3019 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6003 : { 3019 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6004 : { 3027 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6005 : { 3027 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6006 : { 3027 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6007 : { 3035 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6008 : { 3035 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6009 : { 3035 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6010 : { 3043 /* cvt.ps.s */, Mips::CVT_PS_S64, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6011 : { 3052 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6012 : { 3052 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6013 : { 3052 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6014 : { 3052 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6015 : { 3060 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6016 : { 3060 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6017 : { 3068 /* cvt.s.pl */, Mips::CVT_S_PL64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6018 : { 3077 /* cvt.s.pu */, Mips::CVT_S_PU64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6019 : { 3086 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6020 : { 3086 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6021 : { 3086 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6022 : { 3094 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6023 : { 3094 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6024 : { 3094 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6025 : { 3094 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6026 : { 3102 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6027 : { 3102 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6028 : { 3102 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6029 : { 3110 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6030 : { 3110 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6031 : { 3110 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6032 : { 3110 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6033 : { 3115 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6034 : { 3115 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6035 : { 3121 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6036 : { 3121 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6037 : { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6038 : { 3128 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6039 : { 3128 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6040 : { 3128 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6041 : { 3134 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6042 : { 3139 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
6043 : { 3146 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6044 : { 3151 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
6045 : { 3156 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6046 : { 3165 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6047 : { 3165 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6048 : { 3170 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6049 : { 3170 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6050 : { 3175 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6051 : { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6052 : { 3175 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6053 : { 3175 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6054 : { 3175 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6055 : { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6056 : { 3180 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6057 : { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6058 : { 3180 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6059 : { 3180 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6060 : { 3180 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6061 : { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6062 : { 3186 /* deret */, Mips::DERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { }, },
6063 : { 3186 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6064 : { 3186 /* deret */, Mips::DERET_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
6065 : { 3192 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6066 : { 3192 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6067 : { 3192 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, },
6068 : { 3197 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6069 : { 3203 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6070 : { 3209 /* di */, Mips::DI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, },
6071 : { 3209 /* di */, Mips::DI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6072 : { 3209 /* di */, Mips::DI_MM, Convert__regZERO, Feature_InMicroMips, { }, },
6073 : { 3209 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6074 : { 3209 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6075 : { 3209 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
6076 : { 3212 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6077 : { 3212 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6078 : { 3212 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, },
6079 : { 3217 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6080 : { 3223 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6081 : { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6082 : { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6083 : { 3229 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6084 : { 3229 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6085 : { 3229 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6086 : { 3229 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6087 : { 3229 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6088 : { 3229 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6089 : { 3229 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6090 : { 3229 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6091 : { 3229 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6092 : { 3233 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6093 : { 3233 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6094 : { 3233 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6095 : { 3233 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6096 : { 3239 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6097 : { 3239 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6098 : { 3239 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6099 : { 3245 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6100 : { 3253 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6101 : { 3261 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6102 : { 3269 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6103 : { 3277 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6104 : { 3285 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6105 : { 3293 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6106 : { 3301 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6107 : { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6108 : { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6109 : { 3309 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6110 : { 3309 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6111 : { 3309 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6112 : { 3309 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6113 : { 3309 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6114 : { 3309 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6115 : { 3309 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6116 : { 3309 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6117 : { 3309 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6118 : { 3314 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
6119 : { 3314 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, 0, { MCK_GPR64AsmReg, MCK_Mem }, },
6120 : { 3318 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
6121 : { 3322 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6122 : { 3322 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6123 : { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6124 : { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6125 : { 3333 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6126 : { 3339 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6127 : { 3339 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6128 : { 3339 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6129 : { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6130 : { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6131 : { 3352 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6132 : { 3357 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6133 : { 3363 /* dmt */, Mips::DMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
6134 : { 3363 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6135 : { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6136 : { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6137 : { 3373 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6138 : { 3379 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6139 : { 3379 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6140 : { 3379 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6141 : { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6142 : { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6143 : { 3392 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6144 : { 3397 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6145 : { 3403 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6146 : { 3403 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6147 : { 3403 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6148 : { 3403 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6149 : { 3403 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6150 : { 3408 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6151 : { 3414 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6152 : { 3421 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6153 : { 3427 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6154 : { 3434 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6155 : { 3440 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
6156 : { 3440 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6157 : { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
6158 : { 3445 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6159 : { 3451 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6160 : { 3460 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6161 : { 3469 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6162 : { 3478 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6163 : { 3487 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6164 : { 3496 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6165 : { 3505 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6166 : { 3505 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6167 : { 3514 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6168 : { 3524 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6169 : { 3534 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6170 : { 3544 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6171 : { 3554 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6172 : { 3564 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6173 : { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6174 : { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6175 : { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6176 : { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6177 : { 3598 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6178 : { 3598 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6179 : { 3611 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6180 : { 3611 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6181 : { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6182 : { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6183 : { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6184 : { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6185 : { 3647 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6186 : { 3647 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6187 : { 3657 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
6188 : { 3657 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6189 : { 3662 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6190 : { 3662 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6191 : { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6192 : { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6193 : { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6194 : { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6195 : { 3695 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6196 : { 3695 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6197 : { 3708 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6198 : { 3708 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6199 : { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6200 : { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6201 : { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6202 : { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6203 : { 3744 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6204 : { 3754 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6205 : { 3764 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6206 : { 3774 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6207 : { 3784 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6208 : { 3794 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6209 : { 3804 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6210 : { 3804 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6211 : { 3814 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6212 : { 3814 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6213 : { 3814 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6214 : { 3814 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6215 : { 3819 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6216 : { 3819 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6217 : { 3819 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6218 : { 3819 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6219 : { 3825 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6220 : { 3825 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6221 : { 3825 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6222 : { 3825 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6223 : { 3830 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6224 : { 3830 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6225 : { 3830 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6226 : { 3830 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6227 : { 3835 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6228 : { 3835 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6229 : { 3841 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6230 : { 3841 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6231 : { 3849 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6232 : { 3856 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6233 : { 3861 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6234 : { 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6235 : { 3866 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6236 : { 3866 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6237 : { 3866 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6238 : { 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6239 : { 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6240 : { 3878 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6241 : { 3884 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6242 : { 3884 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6243 : { 3884 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6244 : { 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6245 : { 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6246 : { 3896 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6247 : { 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6248 : { 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6249 : { 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6250 : { 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6251 : { 3907 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6252 : { 3907 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6253 : { 3914 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6254 : { 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6255 : { 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6256 : { 3920 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6257 : { 3920 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6258 : { 3925 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6259 : { 3925 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6260 : { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6261 : { 3931 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, },
6262 : { 3931 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6263 : { 3931 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6264 : { 3937 /* dvp */, Mips::DVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, { }, },
6265 : { 3937 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6266 : { 3937 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6267 : { 3937 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6268 : { 3941 /* dvpe */, Mips::DVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
6269 : { 3941 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6270 : { 3946 /* ehb */, Mips::EHB, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
6271 : { 3946 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6272 : { 3946 /* ehb */, Mips::EHB_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
6273 : { 3950 /* ei */, Mips::EI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, },
6274 : { 3950 /* ei */, Mips::EI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6275 : { 3950 /* ei */, Mips::EI_MM, Convert__regZERO, Feature_InMicroMips, { }, },
6276 : { 3950 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6277 : { 3950 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6278 : { 3950 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
6279 : { 3953 /* emt */, Mips::EMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
6280 : { 3953 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6281 : { 3957 /* eret */, Mips::ERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, { }, },
6282 : { 3957 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6283 : { 3957 /* eret */, Mips::ERET_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
6284 : { 3962 /* eretnc */, Mips::ERETNC, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_NotInMicroMips, { }, },
6285 : { 3962 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6286 : { 3969 /* evp */, Mips::EVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, { }, },
6287 : { 3969 /* evp */, Mips::EVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
6288 : { 3969 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6289 : { 3969 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6290 : { 3973 /* evpe */, Mips::EVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
6291 : { 3973 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6292 : { 3978 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6293 : { 3978 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6294 : { 3978 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6295 : { 3982 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6296 : { 3982 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6297 : { 3987 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6298 : { 3987 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6299 : { 3994 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6300 : { 3994 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6301 : { 4002 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6302 : { 4002 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6303 : { 4008 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6304 : { 4008 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6305 : { 4015 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6306 : { 4015 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6307 : { 4024 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6308 : { 4024 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6309 : { 4034 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6310 : { 4034 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6311 : { 4043 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6312 : { 4043 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6313 : { 4051 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6314 : { 4051 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6315 : { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6316 : { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6317 : { 4072 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6318 : { 4072 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6319 : { 4082 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6320 : { 4082 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6321 : { 4082 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6322 : { 4082 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6323 : { 4087 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6324 : { 4087 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6325 : { 4094 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6326 : { 4101 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6327 : { 4108 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6328 : { 4115 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6329 : { 4122 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6330 : { 4129 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6331 : { 4136 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6332 : { 4145 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6333 : { 4154 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6334 : { 4161 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6335 : { 4168 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6336 : { 4175 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6337 : { 4182 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6338 : { 4189 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6339 : { 4196 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6340 : { 4203 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6341 : { 4210 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6342 : { 4218 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6343 : { 4226 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6344 : { 4234 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6345 : { 4242 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6346 : { 4250 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6347 : { 4258 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6348 : { 4265 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6349 : { 4272 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6350 : { 4280 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6351 : { 4288 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6352 : { 4295 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6353 : { 4302 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6354 : { 4310 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6355 : { 4318 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6356 : { 4326 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6357 : { 4334 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6358 : { 4343 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6359 : { 4352 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6360 : { 4361 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6361 : { 4370 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6362 : { 4380 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6363 : { 4390 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6364 : { 4400 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6365 : { 4410 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6366 : { 4417 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6367 : { 4424 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6368 : { 4431 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6369 : { 4438 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6370 : { 4445 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
6371 : { 4452 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6372 : { 4459 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6373 : { 4466 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6374 : { 4474 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6375 : { 4482 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6376 : { 4482 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6377 : { 4492 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6378 : { 4492 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6379 : { 4502 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6380 : { 4502 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6381 : { 4502 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6382 : { 4502 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6383 : { 4512 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6384 : { 4512 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6385 : { 4512 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6386 : { 4522 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6387 : { 4530 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6388 : { 4538 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6389 : { 4545 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6390 : { 4552 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6391 : { 4561 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6392 : { 4570 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6393 : { 4577 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6394 : { 4584 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6395 : { 4593 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6396 : { 4602 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6397 : { 4610 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6398 : { 4618 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6399 : { 4625 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6400 : { 4632 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6401 : { 4637 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6402 : { 4644 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6403 : { 4651 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6404 : { 4659 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6405 : { 4667 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6406 : { 4676 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6407 : { 4685 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6408 : { 4692 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6409 : { 4699 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6410 : { 4706 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6411 : { 4713 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6412 : { 4720 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6413 : { 4727 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6414 : { 4734 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6415 : { 4741 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6416 : { 4748 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6417 : { 4755 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6418 : { 4762 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6419 : { 4769 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6420 : { 4777 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6421 : { 4785 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6422 : { 4792 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6423 : { 4799 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6424 : { 4807 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6425 : { 4815 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6426 : { 4823 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6427 : { 4831 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6428 : { 4839 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6429 : { 4847 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6430 : { 4854 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6431 : { 4861 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6432 : { 4869 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6433 : { 4877 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6434 : { 4887 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6435 : { 4897 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6436 : { 4907 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6437 : { 4917 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6438 : { 4923 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6439 : { 4929 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6440 : { 4940 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6441 : { 4951 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6442 : { 4962 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6443 : { 4973 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6444 : { 4973 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg }, },
6445 : { 4979 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6446 : { 4979 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6447 : { 4985 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6448 : { 4994 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6449 : { 5003 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6450 : { 5012 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6451 : { 5021 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6452 : { 5030 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6453 : { 5039 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6454 : { 5048 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6455 : { 5057 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6456 : { 5066 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6457 : { 5075 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6458 : { 5084 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6459 : { 5093 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
6460 : { 5093 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
6461 : { 5093 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
6462 : { 5093 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_ConstantUImm10_0 }, },
6463 : { 5101 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6464 : { 5109 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6465 : { 5117 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6466 : { 5125 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6467 : { 5133 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6468 : { 5140 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6469 : { 5147 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6470 : { 5154 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6471 : { 5161 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6472 : { 5169 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6473 : { 5177 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6474 : { 5185 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6475 : { 5193 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6476 : { 5200 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6477 : { 5207 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6478 : { 5214 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6479 : { 5221 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6480 : { 5221 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6481 : { 5221 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6482 : { 5225 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, },
6483 : { 5234 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, },
6484 : { 5243 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, },
6485 : { 5252 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, },
6486 : { 5261 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6487 : { 5261 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6488 : { 5266 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6489 : { 5274 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6490 : { 5282 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6491 : { 5290 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6492 : { 5298 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6493 : { 5298 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6494 : { 5298 /* j */, Mips::J_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
6495 : { 5298 /* j */, Mips::J, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
6496 : { 5300 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
6497 : { 5300 /* jal */, Mips::JAL_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
6498 : { 5300 /* jal */, Mips::JAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
6499 : { 5300 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
6500 : { 5300 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6501 : { 5304 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6502 : { 5304 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6503 : { 5304 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6504 : { 5304 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6505 : { 5304 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6506 : { 5304 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_NotInMips16Mode, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6507 : { 5309 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6508 : { 5309 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
6509 : { 5309 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6510 : { 5309 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6511 : { 5317 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
6512 : { 5317 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6513 : { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6514 : { 5317 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
6515 : { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6516 : { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6517 : { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6518 : { 5332 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6519 : { 5338 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6520 : { 5346 /* jals */, Mips::JALS_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
6521 : { 5351 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
6522 : { 5351 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, },
6523 : { 5356 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6524 : { 5356 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6525 : { 5356 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6526 : { 5362 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6527 : { 5362 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6528 : { 5362 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6529 : { 5366 /* jr */, Mips::JrRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
6530 : { 5366 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6531 : { 5366 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6532 : { 5366 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6533 : { 5366 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
6534 : { 5366 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
6535 : { 5369 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
6536 : { 5369 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6537 : { 5369 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
6538 : { 5369 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg }, },
6539 : { 5375 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6540 : { 5380 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_UImm5Lsl2 }, },
6541 : { 5390 /* jrc */, Mips::JrcRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
6542 : { 5390 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
6543 : { 5390 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6544 : { 5390 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6545 : { 5390 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
6546 : { 5394 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
6547 : { 5400 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_UImm5Lsl2 }, },
6548 : { 5411 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
6549 : { 5411 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
6550 : { 5415 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
6551 : { 5419 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
6552 : { 5419 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
6553 : { 5422 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6554 : { 5422 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6555 : { 5427 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6556 : { 5427 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6557 : { 5427 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6558 : { 5430 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6559 : { 5430 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6560 : { 5434 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6561 : { 5434 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6562 : { 5434 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6563 : { 5438 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6564 : { 5444 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6565 : { 5444 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6566 : { 5449 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6567 : { 5449 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6568 : { 5454 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6569 : { 5454 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6570 : { 5457 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
6571 : { 5462 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
6572 : { 5467 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
6573 : { 5472 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
6574 : { 5477 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
6575 : { 5477 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
6576 : { 5477 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
6577 : { 5477 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
6578 : { 5482 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
6579 : { 5482 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
6580 : { 5482 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
6581 : { 5487 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
6582 : { 5492 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6583 : { 5498 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6584 : { 5504 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6585 : { 5510 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6586 : { 5516 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
6587 : { 5520 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6588 : { 5525 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
6589 : { 5529 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6590 : { 5529 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6591 : { 5535 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6592 : { 5535 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6593 : { 5538 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6594 : { 5538 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6595 : { 5542 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6596 : { 5542 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6597 : { 5546 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6598 : { 5552 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6599 : { 5552 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6600 : { 5557 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6601 : { 5557 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6602 : { 5561 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
6603 : { 5561 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, 0, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
6604 : { 5561 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
6605 : { 5564 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
6606 : { 5564 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
6607 : { 5564 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
6608 : { 5569 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
6609 : { 5569 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, Feature_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
6610 : { 5574 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
6611 : { 5574 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
6612 : { 5579 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6613 : { 5579 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6614 : { 5579 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6615 : { 5579 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6616 : { 5579 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6617 : { 5579 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6618 : { 5582 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6619 : { 5582 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6620 : { 5586 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6621 : { 5586 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6622 : { 5590 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6623 : { 5590 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6624 : { 5590 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6625 : { 5594 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
6626 : { 5594 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
6627 : { 5594 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
6628 : { 5598 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6629 : { 5598 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6630 : { 5598 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6631 : { 5604 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
6632 : { 5604 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
6633 : { 5604 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6634 : { 5604 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
6635 : { 5604 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
6636 : { 5604 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6637 : { 5604 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6638 : { 5604 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, },
6639 : { 5604 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
6640 : { 5604 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
6641 : { 5607 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6642 : { 5612 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
6643 : { 5612 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
6644 : { 5617 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
6645 : { 5617 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
6646 : { 5617 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
6647 : { 5622 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
6648 : { 5627 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6649 : { 5627 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6650 : { 5631 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6651 : { 5631 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6652 : { 5635 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6653 : { 5635 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6654 : { 5640 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
6655 : { 5644 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
6656 : { 5644 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
6657 : { 5650 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
6658 : { 5656 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
6659 : { 5660 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6660 : { 5660 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6661 : { 5665 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6662 : { 5665 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6663 : { 5669 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6664 : { 5669 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6665 : { 5674 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
6666 : { 5674 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, },
6667 : { 5678 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6668 : { 5684 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6669 : { 5684 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6670 : { 5688 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6671 : { 5688 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6672 : { 5694 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6673 : { 5699 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6674 : { 5699 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6675 : { 5699 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6676 : { 5699 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6677 : { 5704 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6678 : { 5704 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6679 : { 5704 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6680 : { 5711 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6681 : { 5711 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6682 : { 5718 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6683 : { 5727 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6684 : { 5736 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6685 : { 5736 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6686 : { 5744 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6687 : { 5744 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6688 : { 5752 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6689 : { 5762 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6690 : { 5772 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6691 : { 5772 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6692 : { 5772 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6693 : { 5772 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6694 : { 5778 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6695 : { 5786 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6696 : { 5794 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6697 : { 5802 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6698 : { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6699 : { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6700 : { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6701 : { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6702 : { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6703 : { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6704 : { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6705 : { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6706 : { 5860 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6707 : { 5860 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6708 : { 5866 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6709 : { 5866 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6710 : { 5872 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6711 : { 5880 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6712 : { 5888 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6713 : { 5896 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6714 : { 5904 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6715 : { 5912 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6716 : { 5920 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6717 : { 5928 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6718 : { 5936 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6719 : { 5944 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6720 : { 5952 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6721 : { 5960 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6722 : { 5968 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6723 : { 5968 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6724 : { 5975 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6725 : { 5975 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6726 : { 5982 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6727 : { 5991 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6728 : { 6000 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6729 : { 6009 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6730 : { 6018 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6731 : { 6027 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6732 : { 6036 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6733 : { 6045 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6734 : { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6735 : { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6736 : { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6737 : { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6738 : { 6059 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6739 : { 6059 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6740 : { 6059 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6741 : { 6059 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
6742 : { 6064 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6743 : { 6064 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6744 : { 6064 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6745 : { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6746 : { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6747 : { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6748 : { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6749 : { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6750 : { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6751 : { 6081 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
6752 : { 6081 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
6753 : { 6081 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
6754 : { 6081 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
6755 : { 6087 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6756 : { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6757 : { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6758 : { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6759 : { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6760 : { 6100 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
6761 : { 6100 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6762 : { 6100 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6763 : { 6100 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6764 : { 6100 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6765 : { 6105 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6766 : { 6112 /* mflo */, Mips::Mflo16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
6767 : { 6112 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6768 : { 6112 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6769 : { 6112 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6770 : { 6112 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6771 : { 6117 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6772 : { 6124 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6773 : { 6124 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6774 : { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6775 : { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6776 : { 6137 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6777 : { 6143 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, },
6778 : { 6150 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6779 : { 6157 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6780 : { 6164 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6781 : { 6164 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6782 : { 6170 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6783 : { 6170 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6784 : { 6176 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
6785 : { 6181 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6786 : { 6181 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6787 : { 6187 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6788 : { 6187 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6789 : { 6193 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6790 : { 6201 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6791 : { 6209 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6792 : { 6217 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6793 : { 6225 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6794 : { 6233 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6795 : { 6241 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6796 : { 6249 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6797 : { 6257 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6798 : { 6265 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6799 : { 6273 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6800 : { 6281 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6801 : { 6289 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6802 : { 6289 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6803 : { 6296 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6804 : { 6296 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6805 : { 6303 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6806 : { 6312 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6807 : { 6321 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6808 : { 6330 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6809 : { 6339 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6810 : { 6348 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6811 : { 6357 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6812 : { 6366 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6813 : { 6375 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6814 : { 6375 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6815 : { 6379 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6816 : { 6387 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6817 : { 6395 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6818 : { 6403 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6819 : { 6411 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6820 : { 6419 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6821 : { 6427 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6822 : { 6435 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6823 : { 6443 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6824 : { 6443 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6825 : { 6450 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6826 : { 6450 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6827 : { 6455 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6828 : { 6455 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6829 : { 6455 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6830 : { 6455 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6831 : { 6461 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6832 : { 6461 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6833 : { 6461 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6834 : { 6467 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
6835 : { 6467 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
6836 : { 6467 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6837 : { 6467 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6838 : { 6467 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6839 : { 6467 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6840 : { 6467 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6841 : { 6472 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6842 : { 6479 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6843 : { 6486 /* movep */, Mips::MOVEP_MM, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
6844 : { 6486 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
6845 : { 6492 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
6846 : { 6492 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
6847 : { 6497 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
6848 : { 6497 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
6849 : { 6497 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
6850 : { 6504 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
6851 : { 6504 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
6852 : { 6511 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6853 : { 6511 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6854 : { 6516 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
6855 : { 6516 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
6856 : { 6516 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
6857 : { 6523 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
6858 : { 6523 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
6859 : { 6530 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
6860 : { 6530 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
6861 : { 6535 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
6862 : { 6535 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
6863 : { 6535 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
6864 : { 6542 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
6865 : { 6542 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
6866 : { 6549 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6867 : { 6549 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6868 : { 6554 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
6869 : { 6554 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
6870 : { 6554 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
6871 : { 6561 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
6872 : { 6561 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
6873 : { 6568 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6874 : { 6568 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6875 : { 6568 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6876 : { 6568 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6877 : { 6573 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6878 : { 6573 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6879 : { 6573 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6880 : { 6580 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6881 : { 6580 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6882 : { 6587 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6883 : { 6596 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6884 : { 6605 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6885 : { 6605 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6886 : { 6613 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6887 : { 6613 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6888 : { 6621 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6889 : { 6631 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6890 : { 6641 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6891 : { 6641 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6892 : { 6641 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6893 : { 6641 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6894 : { 6647 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6895 : { 6655 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6896 : { 6663 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6897 : { 6671 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6898 : { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6899 : { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6900 : { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6901 : { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6902 : { 6684 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6903 : { 6684 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6904 : { 6684 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6905 : { 6684 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
6906 : { 6684 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
6907 : { 6689 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6908 : { 6689 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6909 : { 6689 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6910 : { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6911 : { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6912 : { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6913 : { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6914 : { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6915 : { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6916 : { 6706 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
6917 : { 6706 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
6918 : { 6706 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
6919 : { 6706 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
6920 : { 6712 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6921 : { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6922 : { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6923 : { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6924 : { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6925 : { 6725 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6926 : { 6725 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6927 : { 6725 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
6928 : { 6725 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
6929 : { 6730 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6930 : { 6730 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6931 : { 6737 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6932 : { 6737 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
6933 : { 6737 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
6934 : { 6737 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
6935 : { 6742 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
6936 : { 6747 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
6937 : { 6752 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
6938 : { 6757 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
6939 : { 6762 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
6940 : { 6767 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
6941 : { 6772 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6942 : { 6772 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6943 : { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6944 : { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6945 : { 6785 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6946 : { 6791 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, },
6947 : { 6798 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6948 : { 6805 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6949 : { 6812 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6950 : { 6812 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6951 : { 6818 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
6952 : { 6818 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
6953 : { 6824 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
6954 : { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6955 : { 6829 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6956 : { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6957 : { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6958 : { 6833 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6959 : { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6960 : { 6838 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6961 : { 6838 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6962 : { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6963 : { 6838 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6964 : { 6838 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6965 : { 6838 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6966 : { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6967 : { 6838 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
6968 : { 6842 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6969 : { 6842 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6970 : { 6842 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6971 : { 6842 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6972 : { 6848 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6973 : { 6848 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6974 : { 6855 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6975 : { 6855 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6976 : { 6855 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6977 : { 6861 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6978 : { 6869 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6979 : { 6877 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6980 : { 6877 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6981 : { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6982 : { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6983 : { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6984 : { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6985 : { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6986 : { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6987 : { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6988 : { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6989 : { 6944 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6990 : { 6944 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6991 : { 6949 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6992 : { 6949 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6993 : { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6994 : { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6995 : { 6966 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6996 : { 6966 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6997 : { 6976 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6998 : { 6976 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6999 : { 6986 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7000 : { 6986 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7001 : { 6995 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7002 : { 7004 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7003 : { 7013 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7004 : { 7013 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7005 : { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7006 : { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7007 : { 7038 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7008 : { 7038 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7009 : { 7038 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7010 : { 7038 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7011 : { 7043 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7012 : { 7043 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7013 : { 7043 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7014 : { 7043 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7015 : { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7016 : { 7049 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7017 : { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7018 : { 7054 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7019 : { 7061 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7020 : { 7068 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7021 : { 7075 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7022 : { 7082 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
7023 : { 7082 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
7024 : { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
7025 : { 7082 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7026 : { 7082 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7027 : { 7082 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7028 : { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7029 : { 7086 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7030 : { 7086 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7031 : { 7086 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7032 : { 7086 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7033 : { 7092 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7034 : { 7092 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7035 : { 7092 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7036 : { 7098 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
7037 : { 7098 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
7038 : { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
7039 : { 7098 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7040 : { 7098 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7041 : { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7042 : { 7103 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7043 : { 7110 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7044 : { 7117 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7045 : { 7124 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7046 : { 7131 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7047 : { 7138 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7048 : { 7145 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7049 : { 7152 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7050 : { 7159 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7051 : { 7159 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7052 : { 7159 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7053 : { 7167 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7054 : { 7167 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7055 : { 7175 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7056 : { 7175 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7057 : { 7175 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7058 : { 7183 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7059 : { 7183 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7060 : { 7191 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
7061 : { 7191 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, },
7062 : { 7191 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, Feature_InMips16Mode, { }, },
7063 : { 7191 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips, { }, },
7064 : { 7191 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, Feature_InMicroMips, { }, },
7065 : { 7195 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7066 : { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7067 : { 7195 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7068 : { 7195 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7069 : { 7195 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7070 : { 7195 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7071 : { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7072 : { 7199 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7073 : { 7205 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7074 : { 7212 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
7075 : { 7212 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
7076 : { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
7077 : { 7212 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7078 : { 7212 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7079 : { 7212 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7080 : { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7081 : { 7216 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7082 : { 7216 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7083 : { 7222 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7084 : { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7085 : { 7222 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7086 : { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7087 : { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7088 : { 7222 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7089 : { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7090 : { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
7091 : { 7222 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7092 : { 7222 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7093 : { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7094 : { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7095 : { 7222 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7096 : { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7097 : { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7098 : { 7225 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7099 : { 7230 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7100 : { 7230 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7101 : { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7102 : { 7235 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7103 : { 7235 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7104 : { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7105 : { 7235 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7106 : { 7235 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7107 : { 7239 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7108 : { 7245 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7109 : { 7245 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7110 : { 7255 /* pause */, Mips::PAUSE, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, },
7111 : { 7255 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
7112 : { 7255 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
7113 : { 7261 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7114 : { 7269 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7115 : { 7277 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7116 : { 7285 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7117 : { 7293 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7118 : { 7301 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7119 : { 7309 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7120 : { 7317 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7121 : { 7325 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7122 : { 7332 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7123 : { 7339 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7124 : { 7346 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7125 : { 7353 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7126 : { 7353 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7127 : { 7361 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7128 : { 7361 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7129 : { 7369 /* pll.ps */, Mips::PLL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7130 : { 7376 /* plu.ps */, Mips::PLU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7131 : { 7383 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasCnMips, { MCK_GPR32AsmReg }, },
7132 : { 7383 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7133 : { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7134 : { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7135 : { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7136 : { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7137 : { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7138 : { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7139 : { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7140 : { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7141 : { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7142 : { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7143 : { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7144 : { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7145 : { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7146 : { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7147 : { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7148 : { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7149 : { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7150 : { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7151 : { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7152 : { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7153 : { 7533 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7154 : { 7533 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7155 : { 7545 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7156 : { 7545 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7157 : { 7560 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7158 : { 7560 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7159 : { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7160 : { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7161 : { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7162 : { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7163 : { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7164 : { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7165 : { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7166 : { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7167 : { 7633 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7168 : { 7633 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
7169 : { 7633 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
7170 : { 7633 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
7171 : { 7638 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7172 : { 7638 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7173 : { 7644 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7174 : { 7650 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7175 : { 7650 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7176 : { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7177 : { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7178 : { 7669 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
7179 : { 7669 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7180 : { 7675 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7181 : { 7675 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7182 : { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7183 : { 7675 /* rdhwr */, Mips::RDHWR64, Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_HWRegsAsmReg }, },
7184 : { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
7185 : { 7675 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7186 : { 7675 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7187 : { 7681 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7188 : { 7688 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7189 : { 7688 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7190 : { 7688 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7191 : { 7688 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7192 : { 7696 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7193 : { 7696 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7194 : { 7704 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7195 : { 7704 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7196 : { 7704 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7197 : { 7704 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7198 : { 7708 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7199 : { 7708 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7200 : { 7708 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7201 : { 7708 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7202 : { 7713 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7203 : { 7713 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7204 : { 7721 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7205 : { 7721 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7206 : { 7729 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7207 : { 7729 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7208 : { 7738 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7209 : { 7738 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7210 : { 7747 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7211 : { 7747 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7212 : { 7754 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7213 : { 7754 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7214 : { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7215 : { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7216 : { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7217 : { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7218 : { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7219 : { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7220 : { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7221 : { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7222 : { 7769 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7223 : { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7224 : { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7225 : { 7769 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7226 : { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7227 : { 7774 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7228 : { 7774 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7229 : { 7780 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7230 : { 7780 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7231 : { 7790 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7232 : { 7790 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7233 : { 7800 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7234 : { 7800 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7235 : { 7800 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
7236 : { 7800 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7237 : { 7810 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7238 : { 7810 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7239 : { 7810 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7240 : { 7820 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7241 : { 7820 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7242 : { 7820 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7243 : { 7820 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7244 : { 7828 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7245 : { 7828 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotInMips16Mode|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7246 : { 7836 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
7247 : { 7836 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
7248 : { 7840 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
7249 : { 7844 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7250 : { 7852 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7251 : { 7860 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7252 : { 7868 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7253 : { 7876 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7254 : { 7884 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7255 : { 7892 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7256 : { 7900 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7257 : { 7908 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7258 : { 7908 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7259 : { 7908 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7260 : { 7908 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7261 : { 7911 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7262 : { 7911 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7263 : { 7916 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7264 : { 7916 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7265 : { 7920 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7266 : { 7920 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7267 : { 7920 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7268 : { 7920 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7269 : { 7920 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7270 : { 7920 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7271 : { 7923 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
7272 : { 7923 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7273 : { 7927 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7274 : { 7927 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7275 : { 7931 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
7276 : { 7931 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
7277 : { 7934 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { }, },
7278 : { 7934 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { }, },
7279 : { 7934 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, },
7280 : { 7934 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
7281 : { 7934 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7282 : { 7934 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7283 : { 7934 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm20_0 }, },
7284 : { 7940 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, },
7285 : { 7940 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, },
7286 : { 7948 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
7287 : { 7948 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
7288 : { 7948 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
7289 : { 7948 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
7290 : { 7953 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7291 : { 7953 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7292 : { 7953 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
7293 : { 7958 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
7294 : { 7963 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7295 : { 7967 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7296 : { 7971 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7297 : { 7971 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7298 : { 7977 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, },
7299 : { 7977 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
7300 : { 7977 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
7301 : { 7977 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7302 : { 7977 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7303 : { 7981 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, },
7304 : { 7981 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
7305 : { 7981 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
7306 : { 7981 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7307 : { 7981 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7308 : { 7985 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7309 : { 7985 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7310 : { 7991 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7311 : { 7991 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7312 : { 7997 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7313 : { 7997 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7314 : { 7997 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7315 : { 8004 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7316 : { 8004 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7317 : { 8013 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7318 : { 8013 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7319 : { 8022 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7320 : { 8022 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7321 : { 8022 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7322 : { 8029 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7323 : { 8029 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7324 : { 8038 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7325 : { 8038 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7326 : { 8047 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7327 : { 8047 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7328 : { 8047 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7329 : { 8047 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7330 : { 8047 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7331 : { 8047 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7332 : { 8051 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7333 : { 8051 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7334 : { 8056 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7335 : { 8056 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7336 : { 8056 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7337 : { 8056 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7338 : { 8060 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7339 : { 8060 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7340 : { 8060 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7341 : { 8060 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7342 : { 8065 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7343 : { 8065 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7344 : { 8065 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7345 : { 8065 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7346 : { 8068 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7347 : { 8068 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7348 : { 8073 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7349 : { 8073 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7350 : { 8077 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7351 : { 8083 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7352 : { 8089 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7353 : { 8095 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7354 : { 8095 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7355 : { 8101 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7356 : { 8101 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7357 : { 8108 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7358 : { 8108 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7359 : { 8116 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7360 : { 8116 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7361 : { 8124 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7362 : { 8124 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7363 : { 8134 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7364 : { 8134 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7365 : { 8143 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7366 : { 8143 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7367 : { 8152 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7368 : { 8152 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7369 : { 8161 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7370 : { 8161 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7371 : { 8172 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7372 : { 8172 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7373 : { 8182 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7374 : { 8182 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7375 : { 8190 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7376 : { 8190 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7377 : { 8198 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7378 : { 8198 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7379 : { 8208 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7380 : { 8208 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7381 : { 8218 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7382 : { 8218 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7383 : { 8227 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7384 : { 8227 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7385 : { 8236 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7386 : { 8236 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7387 : { 8245 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7388 : { 8245 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7389 : { 8256 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7390 : { 8256 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7391 : { 8267 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7392 : { 8267 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7393 : { 8277 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7394 : { 8277 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7395 : { 8285 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7396 : { 8285 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7397 : { 8293 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7398 : { 8293 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7399 : { 8302 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7400 : { 8302 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7401 : { 8311 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7402 : { 8317 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7403 : { 8323 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7404 : { 8329 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7405 : { 8335 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7406 : { 8342 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7407 : { 8349 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7408 : { 8356 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7409 : { 8363 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7410 : { 8363 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7411 : { 8363 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7412 : { 8363 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7413 : { 8363 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7414 : { 8363 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7415 : { 8363 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7416 : { 8363 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7417 : { 8363 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7418 : { 8363 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7419 : { 8363 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7420 : { 8363 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7421 : { 8367 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7422 : { 8373 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7423 : { 8379 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7424 : { 8385 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7425 : { 8391 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7426 : { 8391 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7427 : { 8397 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7428 : { 8404 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7429 : { 8411 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7430 : { 8418 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7431 : { 8425 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7432 : { 8425 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7433 : { 8425 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7434 : { 8430 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7435 : { 8430 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7436 : { 8430 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7437 : { 8430 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7438 : { 8430 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7439 : { 8430 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7440 : { 8430 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7441 : { 8430 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7442 : { 8430 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7443 : { 8434 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7444 : { 8434 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7445 : { 8434 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7446 : { 8434 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
7447 : { 8439 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7448 : { 8439 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7449 : { 8439 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7450 : { 8439 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
7451 : { 8445 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7452 : { 8445 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7453 : { 8445 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7454 : { 8445 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7455 : { 8445 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7456 : { 8445 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7457 : { 8445 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7458 : { 8445 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7459 : { 8445 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7460 : { 8450 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7461 : { 8450 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7462 : { 8454 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7463 : { 8454 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7464 : { 8459 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7465 : { 8467 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7466 : { 8475 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7467 : { 8483 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7468 : { 8491 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7469 : { 8500 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7470 : { 8509 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7471 : { 8518 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7472 : { 8527 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7473 : { 8527 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7474 : { 8527 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7475 : { 8527 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7476 : { 8534 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7477 : { 8534 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7478 : { 8541 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7479 : { 8541 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7480 : { 8541 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7481 : { 8541 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7482 : { 8541 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7483 : { 8541 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7484 : { 8541 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7485 : { 8541 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7486 : { 8541 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7487 : { 8541 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7488 : { 8545 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7489 : { 8551 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7490 : { 8557 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7491 : { 8563 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7492 : { 8569 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7493 : { 8576 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7494 : { 8583 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7495 : { 8590 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7496 : { 8597 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7497 : { 8604 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7498 : { 8611 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7499 : { 8618 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7500 : { 8625 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7501 : { 8633 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7502 : { 8641 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7503 : { 8649 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7504 : { 8657 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7505 : { 8657 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7506 : { 8657 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7507 : { 8662 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7508 : { 8662 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7509 : { 8662 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7510 : { 8662 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7511 : { 8662 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7512 : { 8662 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7513 : { 8662 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7514 : { 8662 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7515 : { 8662 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7516 : { 8662 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7517 : { 8666 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7518 : { 8672 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7519 : { 8678 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7520 : { 8684 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7521 : { 8690 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7522 : { 8690 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7523 : { 8696 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7524 : { 8703 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7525 : { 8710 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7526 : { 8717 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7527 : { 8724 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7528 : { 8731 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7529 : { 8738 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7530 : { 8745 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7531 : { 8752 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7532 : { 8760 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7533 : { 8768 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7534 : { 8776 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7535 : { 8784 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7536 : { 8784 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7537 : { 8784 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7538 : { 8789 /* ssnop */, Mips::SSNOP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
7539 : { 8789 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
7540 : { 8789 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
7541 : { 8795 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
7542 : { 8800 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
7543 : { 8805 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
7544 : { 8810 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
7545 : { 8815 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7546 : { 8815 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7547 : { 8815 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7548 : { 8815 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
7549 : { 8815 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7550 : { 8815 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7551 : { 8815 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7552 : { 8815 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
7553 : { 8819 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7554 : { 8819 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7555 : { 8819 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7556 : { 8819 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7557 : { 8825 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7558 : { 8825 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7559 : { 8825 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7560 : { 8831 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7561 : { 8831 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7562 : { 8839 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7563 : { 8839 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7564 : { 8849 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7565 : { 8849 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7566 : { 8858 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7567 : { 8858 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7568 : { 8867 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7569 : { 8867 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7570 : { 8875 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7571 : { 8875 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7572 : { 8886 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7573 : { 8886 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7574 : { 8896 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7575 : { 8905 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7576 : { 8914 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7577 : { 8923 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7578 : { 8932 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7579 : { 8941 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7580 : { 8950 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7581 : { 8959 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7582 : { 8968 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7583 : { 8979 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7584 : { 8990 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7585 : { 9001 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7586 : { 9012 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7587 : { 9023 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7588 : { 9034 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7589 : { 9045 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7590 : { 9056 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7591 : { 9056 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7592 : { 9056 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7593 : { 9056 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 0, { MCK_GPR32AsmReg, MCK_InvNum }, },
7594 : { 9056 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
7595 : { 9056 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7596 : { 9056 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7597 : { 9056 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7598 : { 9056 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
7599 : { 9061 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7600 : { 9061 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7601 : { 9069 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7602 : { 9069 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7603 : { 9077 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7604 : { 9077 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7605 : { 9084 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7606 : { 9084 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7607 : { 9094 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7608 : { 9094 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7609 : { 9104 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7610 : { 9104 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7611 : { 9113 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7612 : { 9113 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7613 : { 9124 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7614 : { 9131 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7615 : { 9138 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7616 : { 9145 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7617 : { 9152 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7618 : { 9160 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7619 : { 9168 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7620 : { 9176 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7621 : { 9184 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7622 : { 9184 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7623 : { 9184 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7624 : { 9190 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
7625 : { 9190 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
7626 : { 9190 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7627 : { 9190 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
7628 : { 9190 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
7629 : { 9190 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7630 : { 9190 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7631 : { 9190 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7632 : { 9190 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
7633 : { 9193 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7634 : { 9193 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7635 : { 9198 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
7636 : { 9198 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
7637 : { 9203 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7638 : { 9203 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7639 : { 9203 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
7640 : { 9208 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
7641 : { 9213 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7642 : { 9213 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7643 : { 9217 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7644 : { 9217 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7645 : { 9221 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7646 : { 9221 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7647 : { 9226 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
7648 : { 9230 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
7649 : { 9230 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
7650 : { 9236 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
7651 : { 9242 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
7652 : { 9246 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7653 : { 9246 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7654 : { 9250 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7655 : { 9250 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7656 : { 9255 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7657 : { 9255 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7658 : { 9261 /* sync */, Mips::SYNC, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { }, },
7659 : { 9261 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, },
7660 : { 9261 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, Feature_InMicroMips, { }, },
7661 : { 9261 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_ConstantUImm5_0 }, },
7662 : { 9261 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0 }, },
7663 : { 9261 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0 }, },
7664 : { 9266 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm162_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_MemOffsetSimm16 }, },
7665 : { 9266 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_MemOffsetSimm16 }, },
7666 : { 9266 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_MemOffsetSimm16 }, },
7667 : { 9272 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, Feature_HasMips64|Feature_HasCnMips, { }, },
7668 : { 9283 /* syncs */, Mips::SYNC, Convert__imm_95_6, Feature_HasMips64|Feature_HasCnMips, { }, },
7669 : { 9289 /* syncw */, Mips::SYNC, Convert__imm_95_4, Feature_HasMips64|Feature_HasCnMips, { }, },
7670 : { 9295 /* syncws */, Mips::SYNC, Convert__imm_95_5, Feature_HasMips64|Feature_HasCnMips, { }, },
7671 : { 9302 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
7672 : { 9302 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, Feature_InMicroMips, { }, },
7673 : { 9302 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
7674 : { 9302 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7675 : { 9310 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7676 : { 9310 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7677 : { 9310 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7678 : { 9310 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7679 : { 9314 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7680 : { 9314 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7681 : { 9319 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7682 : { 9319 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7683 : { 9319 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7684 : { 9319 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7685 : { 9323 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7686 : { 9323 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7687 : { 9328 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7688 : { 9328 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7689 : { 9334 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7690 : { 9334 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7691 : { 9334 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7692 : { 9334 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7693 : { 9339 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
7694 : { 9339 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
7695 : { 9347 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
7696 : { 9347 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
7697 : { 9356 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
7698 : { 9356 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
7699 : { 9362 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
7700 : { 9362 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
7701 : { 9368 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
7702 : { 9368 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
7703 : { 9375 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
7704 : { 9375 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
7705 : { 9382 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { }, },
7706 : { 9382 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
7707 : { 9389 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { }, },
7708 : { 9389 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
7709 : { 9397 /* tlbp */, Mips::TLBP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
7710 : { 9397 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
7711 : { 9402 /* tlbr */, Mips::TLBR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
7712 : { 9402 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
7713 : { 9407 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
7714 : { 9407 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
7715 : { 9413 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
7716 : { 9413 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
7717 : { 9419 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7718 : { 9419 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7719 : { 9419 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7720 : { 9419 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7721 : { 9423 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7722 : { 9423 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7723 : { 9428 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7724 : { 9428 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7725 : { 9434 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7726 : { 9434 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7727 : { 9434 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7728 : { 9434 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7729 : { 9439 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7730 : { 9439 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7731 : { 9439 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7732 : { 9439 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7733 : { 9443 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7734 : { 9443 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7735 : { 9448 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7736 : { 9448 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7737 : { 9458 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7738 : { 9458 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7739 : { 9468 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7740 : { 9468 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7741 : { 9468 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7742 : { 9468 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
7743 : { 9468 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7744 : { 9468 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
7745 : { 9478 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7746 : { 9478 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7747 : { 9478 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7748 : { 9478 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7749 : { 9488 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
7750 : { 9492 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
7751 : { 9497 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
7752 : { 9501 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
7753 : { 9505 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
7754 : { 9509 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7755 : { 9509 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7756 : { 9516 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7757 : { 9516 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7758 : { 9521 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7759 : { 9521 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7760 : { 9527 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7761 : { 9534 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7762 : { 9541 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7763 : { 9548 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7764 : { 9555 /* wait */, Mips::WAIT, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, { }, },
7765 : { 9555 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, Feature_InMicroMips, { }, },
7766 : { 9555 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0 }, },
7767 : { 9555 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
7768 : { 9560 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
7769 : { 9560 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg }, },
7770 : { 9560 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
7771 : { 9560 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7772 : { 9566 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7773 : { 9573 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7774 : { 9573 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7775 : { 9573 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7776 : { 9578 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7777 : { 9578 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7778 : { 9578 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7779 : { 9578 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7780 : { 9578 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7781 : { 9578 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7782 : { 9578 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7783 : { 9578 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
7784 : { 9578 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7785 : { 9578 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7786 : { 9578 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7787 : { 9578 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7788 : { 9578 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7789 : { 9578 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7790 : { 9578 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7791 : { 9582 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7792 : { 9588 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7793 : { 9588 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7794 : { 9594 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7795 : { 9594 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7796 : { 9594 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7797 : { 9594 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7798 : { 9594 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7799 : { 9594 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7800 : { 9599 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7801 : { 9606 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
7802 : { 9606 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7803 : };
7804 :
7805 : #include "llvm/Support/Debug.h"
7806 : #include "llvm/Support/Format.h"
7807 :
7808 40613 : unsigned MipsAsmParser::
7809 : MatchInstructionImpl(const OperandVector &Operands,
7810 : MCInst &Inst,
7811 : uint64_t &ErrorInfo,
7812 : bool matchingInlineAsm, unsigned VariantID) {
7813 : // Eliminate obvious mismatches.
7814 40613 : if (Operands.size() > 9) {
7815 0 : ErrorInfo = 9;
7816 0 : return Match_InvalidOperand;
7817 : }
7818 :
7819 : // Get the current feature set.
7820 40613 : uint64_t AvailableFeatures = getAvailableFeatures();
7821 :
7822 : // Get the instruction mnemonic, which is the first token.
7823 40613 : StringRef Mnemonic = ((MipsOperand&)*Operands[0]).getToken();
7824 :
7825 : // Some state to try to produce better error messages.
7826 : bool HadMatchOtherThanFeatures = false;
7827 : bool HadMatchOtherThanPredicate = false;
7828 : unsigned RetCode = Match_InvalidOperand;
7829 : uint64_t MissingFeatures = ~0ULL;
7830 : // Set ErrorInfo to the operand that mismatches if it is
7831 : // wrong for all instances of the instruction.
7832 40613 : ErrorInfo = ~0ULL;
7833 : // Find the appropriate table for this asm variant.
7834 : const MatchEntry *Start, *End;
7835 40613 : switch (VariantID) {
7836 0 : default: llvm_unreachable("invalid variant!");
7837 : case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
7838 : }
7839 : // Search the table.
7840 : auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
7841 :
7842 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
7843 : std::distance(MnemonicRange.first, MnemonicRange.second) <<
7844 : " encodings with mnemonic '" << Mnemonic << "'\n");
7845 :
7846 : // Return a more specific error code if no mnemonics match.
7847 40613 : if (MnemonicRange.first == MnemonicRange.second)
7848 : return Match_MnemonicFail;
7849 :
7850 58691 : for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
7851 99304 : it != ie; ++it) {
7852 94412 : bool HasRequiredFeatures =
7853 94412 : (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures;
7854 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
7855 : << MII.getName(it->Opcode) << "\n");
7856 : // equal_range guarantees that instruction mnemonic matches.
7857 : assert(Mnemonic == it->getMnemonic());
7858 : bool OperandsValid = true;
7859 210646 : for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) {
7860 210642 : auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
7861 : DEBUG_WITH_TYPE("asm-matcher",
7862 : dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
7863 : << " against actual operand at index " << ActualIdx);
7864 210642 : if (ActualIdx < Operands.size())
7865 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
7866 : Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
7867 : else
7868 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
7869 210642 : if (ActualIdx >= Operands.size()) {
7870 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
7871 47708 : OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
7872 416 : if (!OperandsValid) ErrorInfo = ActualIdx;
7873 : break;
7874 : }
7875 : MCParsedAsmOperand &Actual = *Operands[ActualIdx];
7876 162934 : unsigned Diag = validateOperandClass(Actual, Formal);
7877 162934 : if (Diag == Match_Success) {
7878 : DEBUG_WITH_TYPE("asm-matcher",
7879 : dbgs() << "match success using generic matcher\n");
7880 116234 : ++ActualIdx;
7881 116234 : continue;
7882 : }
7883 : // If the generic handler indicates an invalid operand
7884 : // failure, check for a special case.
7885 : if (Diag != Match_Success) {
7886 46700 : unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
7887 46700 : if (TargetDiag == Match_Success) {
7888 : DEBUG_WITH_TYPE("asm-matcher",
7889 : dbgs() << "match success using target matcher\n");
7890 0 : ++ActualIdx;
7891 0 : continue;
7892 : }
7893 : // If the target matcher returned a specific error code use
7894 : // that, else use the one from the generic matcher.
7895 46700 : if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
7896 : Diag = TargetDiag;
7897 : }
7898 : // If current formal operand wasn't matched and it is optional
7899 : // then try to match next formal operand
7900 46700 : if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
7901 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
7902 : continue;
7903 : }
7904 : // If this operand is broken for all of the instances of this
7905 : // mnemonic, keep track of it so we can report loc info.
7906 : // If we already had a match that only failed due to a
7907 : // target predicate, that diagnostic is preferred.
7908 46700 : if (!HadMatchOtherThanPredicate &&
7909 27626 : (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
7910 41741 : if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
7911 : RetCode = Diag;
7912 41741 : ErrorInfo = ActualIdx;
7913 : }
7914 : // Otherwise, just reject this instance of the mnemonic.
7915 : OperandsValid = false;
7916 : break;
7917 : }
7918 :
7919 94412 : if (!OperandsValid) {
7920 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
7921 : "operand mismatches, ignoring "
7922 : "this opcode\n");
7923 : continue;
7924 : }
7925 47296 : if (!HasRequiredFeatures) {
7926 : HadMatchOtherThanFeatures = true;
7927 11179 : uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
7928 : DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: "
7929 : << format_hex(NewMissingFeatures, 18)
7930 : << "\n");
7931 11179 : if (countPopulation(NewMissingFeatures) <=
7932 : countPopulation(MissingFeatures))
7933 : MissingFeatures = NewMissingFeatures;
7934 11179 : continue;
7935 : }
7936 :
7937 : Inst.clear();
7938 :
7939 36117 : Inst.setOpcode(it->Opcode);
7940 : // We have a potential match but have not rendered the operands.
7941 : // Check the target predicate to handle any context sensitive
7942 : // constraints.
7943 : // For example, Ties that are referenced multiple times must be
7944 : // checked here to ensure the input is the same for each match
7945 : // constraints. If we leave it any later the ties will have been
7946 : // canonicalized
7947 : unsigned MatchResult;
7948 36117 : if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
7949 : Inst.clear();
7950 : DEBUG_WITH_TYPE(
7951 : "asm-matcher",
7952 : dbgs() << "Early target match predicate failed with diag code "
7953 : << MatchResult << "\n");
7954 : RetCode = MatchResult;
7955 : HadMatchOtherThanPredicate = true;
7956 : continue;
7957 : }
7958 :
7959 36113 : if (matchingInlineAsm) {
7960 0 : convertToMapAndConstraints(it->ConvertFn, Operands);
7961 0 : if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
7962 : return Match_InvalidTiedOperand;
7963 :
7964 0 : return Match_Success;
7965 : }
7966 :
7967 : // We have selected a definite instruction, convert the parsed
7968 : // operands into the appropriate MCInst.
7969 36113 : convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
7970 :
7971 : // We have a potential match. Check the target predicate to
7972 : // handle any context sensitive constraints.
7973 36113 : if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
7974 : DEBUG_WITH_TYPE("asm-matcher",
7975 : dbgs() << "Target match predicate failed with diag code "
7976 : << MatchResult << "\n");
7977 : Inst.clear();
7978 : RetCode = MatchResult;
7979 : HadMatchOtherThanPredicate = true;
7980 392 : continue;
7981 : }
7982 :
7983 35721 : if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
7984 0 : return Match_InvalidTiedOperand;
7985 :
7986 : DEBUG_WITH_TYPE(
7987 : "asm-matcher",
7988 : dbgs() << "Opcode result: complete match, selecting this opcode\n");
7989 : return Match_Success;
7990 : }
7991 :
7992 : // Okay, we had no match. Try to return a useful error code.
7993 4892 : if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
7994 : return RetCode;
7995 :
7996 : // Missing feature matches return which features were missing
7997 2275 : ErrorInfo = MissingFeatures;
7998 2275 : return Match_MissingFeature;
7999 : }
8000 :
8001 : namespace {
8002 : struct OperandMatchEntry {
8003 : uint64_t RequiredFeatures;
8004 : uint16_t Mnemonic;
8005 : uint8_t Class;
8006 : uint8_t OperandMask;
8007 :
8008 0 : StringRef getMnemonic() const {
8009 0 : return StringRef(MnemonicTable + Mnemonic + 1,
8010 0 : MnemonicTable[Mnemonic]);
8011 : }
8012 : };
8013 :
8014 : // Predicate for searching for an opcode.
8015 : struct LessOpcodeOperand {
8016 0 : bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
8017 0 : return LHS.getMnemonic() < RHS;
8018 : }
8019 0 : bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
8020 0 : return LHS < RHS.getMnemonic();
8021 : }
8022 : bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
8023 : return LHS.getMnemonic() < RHS.getMnemonic();
8024 : }
8025 : };
8026 : } // end anonymous namespace.
8027 :
8028 : static const OperandMatchEntry OperandMatchTable[3251] = {
8029 : /* Operand List Mask, Mnemonic, Operand Class, Features */
8030 : { 0, 0 /* abs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8031 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8032 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8033 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8034 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8035 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8036 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8037 : { Feature_InMicroMips|Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8038 : { Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8039 : { Feature_InMicroMips|Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8040 : { Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8041 : { Feature_InMicroMips|Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8042 : { Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8043 : { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8044 : { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8045 : { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8046 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ },
8047 : { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ },
8048 : { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8049 : { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8050 : { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8051 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8052 : { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8053 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
8054 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
8055 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
8056 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
8057 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
8058 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
8059 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
8060 : { Feature_HasStdEnc|Feature_HasMSA, 61 /* add_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8061 : { Feature_HasStdEnc|Feature_HasMSA, 69 /* add_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8062 : { Feature_HasStdEnc|Feature_HasMSA, 77 /* add_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8063 : { Feature_HasStdEnc|Feature_HasMSA, 85 /* add_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8064 : { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
8065 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
8066 : { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8067 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8068 : { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8069 : { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8070 : { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8071 : { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8072 : { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8073 : { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8074 : { Feature_HasStdEnc|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8075 : { Feature_InMicroMips|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8076 : { Feature_InMicroMips|Feature_NotMips32r6, 104 /* addiupc */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8077 : { Feature_InMicroMips, 112 /* addiur1sp */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8078 : { Feature_InMicroMips, 122 /* addiur2 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
8079 : { Feature_InMicroMips, 130 /* addius5 */, MCK_GPR32AsmReg, 1 /* 0 */ },
8080 : { Feature_InMicroMips|Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8081 : { Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8082 : { Feature_InMicroMips|Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8083 : { Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8084 : { Feature_InMicroMips|Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8085 : { Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8086 : { Feature_InMicroMips|Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8087 : { Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8088 : { Feature_InMicroMips|Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8089 : { Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8090 : { Feature_InMicroMips|Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8091 : { Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8092 : { Feature_InMicroMips|Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8093 : { Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8094 : { Feature_HasStdEnc|Feature_HasMSA, 211 /* adds_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8095 : { Feature_HasStdEnc|Feature_HasMSA, 220 /* adds_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8096 : { Feature_HasStdEnc|Feature_HasMSA, 229 /* adds_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8097 : { Feature_HasStdEnc|Feature_HasMSA, 238 /* adds_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8098 : { Feature_HasStdEnc|Feature_HasMSA, 247 /* adds_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8099 : { Feature_HasStdEnc|Feature_HasMSA, 256 /* adds_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8100 : { Feature_HasStdEnc|Feature_HasMSA, 265 /* adds_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8101 : { Feature_HasStdEnc|Feature_HasMSA, 274 /* adds_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8102 : { Feature_HasStdEnc|Feature_HasMSA, 283 /* adds_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8103 : { Feature_HasStdEnc|Feature_HasMSA, 292 /* adds_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8104 : { Feature_HasStdEnc|Feature_HasMSA, 301 /* adds_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8105 : { Feature_HasStdEnc|Feature_HasMSA, 310 /* adds_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8106 : { Feature_InMicroMips|Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8107 : { Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8108 : { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8109 : { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8110 : { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8111 : { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8112 : { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8113 : { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8114 : { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8115 : { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8116 : { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8117 : { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8118 : { Feature_InMicroMips|Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8119 : { Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8120 : { Feature_InMicroMips|Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8121 : { Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8122 : { Feature_InMicroMips|Feature_NotMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
8123 : { Feature_InMicroMips|Feature_HasMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
8124 : { Feature_InMicroMips|Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8125 : { Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8126 : { Feature_InMicroMips|Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8127 : { Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8128 : { Feature_InMicroMips|Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8129 : { Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8130 : { Feature_InMicroMips|Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8131 : { Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8132 : { Feature_HasStdEnc|Feature_HasMSA, 393 /* addv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8133 : { Feature_HasStdEnc|Feature_HasMSA, 400 /* addv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8134 : { Feature_HasStdEnc|Feature_HasMSA, 407 /* addv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8135 : { Feature_HasStdEnc|Feature_HasMSA, 414 /* addv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8136 : { Feature_HasStdEnc|Feature_HasMSA, 421 /* addvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8137 : { Feature_HasStdEnc|Feature_HasMSA, 429 /* addvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8138 : { Feature_HasStdEnc|Feature_HasMSA, 437 /* addvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8139 : { Feature_HasStdEnc|Feature_HasMSA, 445 /* addvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8140 : { Feature_InMicroMips|Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8141 : { Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8142 : { Feature_HasStdEnc|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8143 : { Feature_InMicroMips|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8144 : { Feature_HasStdEnc|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8145 : { Feature_InMicroMips|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8146 : { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8147 : { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8148 : { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8149 : { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
8150 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
8151 : { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
8152 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 1 /* 0 */ },
8153 : { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8154 : { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8155 : { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
8156 : { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8157 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8158 : { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8159 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8160 : { Feature_HasStdEnc|Feature_HasMSA, 476 /* and.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8161 : { Feature_InMicroMips|Feature_NotMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
8162 : { Feature_InMicroMips|Feature_HasMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
8163 : { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
8164 : { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
8165 : { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
8166 : { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8167 : { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8168 : { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8169 : { Feature_HasStdEnc|Feature_HasMSA, 493 /* andi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8170 : { Feature_InMicroMips|Feature_NotMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
8171 : { Feature_InMicroMips|Feature_HasMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
8172 : { Feature_InMicroMips|Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8173 : { Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8174 : { Feature_HasStdEnc|Feature_HasMSA, 514 /* asub_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8175 : { Feature_HasStdEnc|Feature_HasMSA, 523 /* asub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8176 : { Feature_HasStdEnc|Feature_HasMSA, 532 /* asub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8177 : { Feature_HasStdEnc|Feature_HasMSA, 541 /* asub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8178 : { Feature_HasStdEnc|Feature_HasMSA, 550 /* asub_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8179 : { Feature_HasStdEnc|Feature_HasMSA, 559 /* asub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8180 : { Feature_HasStdEnc|Feature_HasMSA, 568 /* asub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8181 : { Feature_HasStdEnc|Feature_HasMSA, 577 /* asub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8182 : { Feature_HasStdEnc|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8183 : { Feature_InMicroMips|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8184 : { Feature_HasStdEnc|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8185 : { Feature_InMicroMips|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8186 : { Feature_HasStdEnc|Feature_HasMSA, 596 /* ave_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8187 : { Feature_HasStdEnc|Feature_HasMSA, 604 /* ave_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8188 : { Feature_HasStdEnc|Feature_HasMSA, 612 /* ave_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8189 : { Feature_HasStdEnc|Feature_HasMSA, 620 /* ave_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8190 : { Feature_HasStdEnc|Feature_HasMSA, 628 /* ave_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8191 : { Feature_HasStdEnc|Feature_HasMSA, 636 /* ave_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8192 : { Feature_HasStdEnc|Feature_HasMSA, 644 /* ave_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8193 : { Feature_HasStdEnc|Feature_HasMSA, 652 /* ave_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8194 : { Feature_HasStdEnc|Feature_HasMSA, 660 /* aver_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8195 : { Feature_HasStdEnc|Feature_HasMSA, 669 /* aver_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8196 : { Feature_HasStdEnc|Feature_HasMSA, 678 /* aver_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8197 : { Feature_HasStdEnc|Feature_HasMSA, 687 /* aver_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8198 : { Feature_HasStdEnc|Feature_HasMSA, 696 /* aver_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8199 : { Feature_HasStdEnc|Feature_HasMSA, 705 /* aver_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8200 : { Feature_HasStdEnc|Feature_HasMSA, 714 /* aver_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8201 : { Feature_HasStdEnc|Feature_HasMSA, 723 /* aver_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8202 : { Feature_HasStdEnc|Feature_NotInMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
8203 : { Feature_InMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
8204 : { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
8205 : { 0, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
8206 : { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
8207 : { Feature_InMicroMips|Feature_HasMips32r6, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ },
8208 : { Feature_InMicroMips, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ },
8209 : { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8210 : { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
8211 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
8212 : { Feature_HasStdEnc|Feature_HasMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
8213 : { Feature_InMicroMips|Feature_NotMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
8214 : { Feature_HasStdEnc|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
8215 : { Feature_InMicroMips|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
8216 : { Feature_InMicroMips|Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8217 : { Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8218 : { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
8219 : { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
8220 : { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
8221 : { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
8222 : { Feature_HasCnMips, 766 /* bbit032 */, MCK_GPR64AsmReg, 1 /* 0 */ },
8223 : { Feature_HasCnMips, 766 /* bbit032 */, MCK_JumpTarget, 4 /* 2 */ },
8224 : { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
8225 : { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
8226 : { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
8227 : { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
8228 : { Feature_HasCnMips, 780 /* bbit132 */, MCK_GPR64AsmReg, 1 /* 0 */ },
8229 : { Feature_HasCnMips, 780 /* bbit132 */, MCK_JumpTarget, 4 /* 2 */ },
8230 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
8231 : { Feature_InMicroMips|Feature_HasMips32r6, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
8232 : { Feature_InMicroMips|Feature_HasMips32r6, 791 /* bc16 */, MCK_JumpTarget, 1 /* 0 */ },
8233 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_FGR64AsmReg, 1 /* 0 */ },
8234 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_JumpTarget, 2 /* 1 */ },
8235 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_FGR64AsmReg, 1 /* 0 */ },
8236 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_JumpTarget, 2 /* 1 */ },
8237 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ },
8238 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ },
8239 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ },
8240 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ },
8241 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ },
8242 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ },
8243 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 1 /* 0 */ },
8244 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_FCCAsmReg, 1 /* 0 */ },
8245 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 2 /* 1 */ },
8246 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_FGR64AsmReg, 1 /* 0 */ },
8247 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_JumpTarget, 2 /* 1 */ },
8248 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_FGR64AsmReg, 1 /* 0 */ },
8249 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_JumpTarget, 2 /* 1 */ },
8250 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ },
8251 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ },
8252 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ },
8253 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ },
8254 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ },
8255 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ },
8256 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 1 /* 0 */ },
8257 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_FCCAsmReg, 1 /* 0 */ },
8258 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 2 /* 1 */ },
8259 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_COP2AsmReg, 1 /* 0 */ },
8260 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_JumpTarget, 2 /* 1 */ },
8261 : { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_COP2AsmReg, 1 /* 0 */ },
8262 : { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_JumpTarget, 2 /* 1 */ },
8263 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_COP2AsmReg, 1 /* 0 */ },
8264 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_JumpTarget, 2 /* 1 */ },
8265 : { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_COP2AsmReg, 1 /* 0 */ },
8266 : { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_JumpTarget, 2 /* 1 */ },
8267 : { Feature_HasStdEnc|Feature_HasMSA, 878 /* bclr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8268 : { Feature_HasStdEnc|Feature_HasMSA, 885 /* bclr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8269 : { Feature_HasStdEnc|Feature_HasMSA, 892 /* bclr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8270 : { Feature_HasStdEnc|Feature_HasMSA, 899 /* bclr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8271 : { Feature_HasStdEnc|Feature_HasMSA, 906 /* bclri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8272 : { Feature_HasStdEnc|Feature_HasMSA, 914 /* bclri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8273 : { Feature_HasStdEnc|Feature_HasMSA, 922 /* bclri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8274 : { Feature_HasStdEnc|Feature_HasMSA, 930 /* bclri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8275 : { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8276 : { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
8277 : { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8278 : { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
8279 : { 0, 938 /* beq */, MCK_GPR32AsmReg, 1 /* 0 */ },
8280 : { 0, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
8281 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8282 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
8283 : { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8284 : { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
8285 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8286 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
8287 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8288 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ },
8289 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_GPR32AsmReg, 1 /* 0 */ },
8290 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ },
8291 : { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
8292 : { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ },
8293 : { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
8294 : { Feature_InMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ },
8295 : { Feature_InMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
8296 : { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
8297 : { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8298 : { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ },
8299 : { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8300 : { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ },
8301 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8302 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
8303 : { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8304 : { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
8305 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8306 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
8307 : { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8308 : { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
8309 : { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8310 : { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
8311 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
8312 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
8313 : { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8314 : { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_JumpTarget, 2 /* 1 */ },
8315 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8316 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_JumpTarget, 2 /* 1 */ },
8317 : { 0, 992 /* bge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8318 : { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
8319 : { 0, 992 /* bge */, MCK_GPR32AsmReg, 1 /* 0 */ },
8320 : { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
8321 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8322 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
8323 : { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8324 : { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
8325 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8326 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
8327 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8328 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
8329 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 1 /* 0 */ },
8330 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
8331 : { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8332 : { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
8333 : { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8334 : { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
8335 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8336 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
8337 : { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8338 : { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
8339 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8340 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
8341 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8342 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
8343 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 1 /* 0 */ },
8344 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
8345 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
8346 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
8347 : { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
8348 : { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
8349 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
8350 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
8351 : { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
8352 : { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
8353 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8354 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
8355 : { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8356 : { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
8357 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_GPR32AsmReg, 1 /* 0 */ },
8358 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_JumpTarget, 2 /* 1 */ },
8359 : { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_GPR32AsmReg, 1 /* 0 */ },
8360 : { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_JumpTarget, 2 /* 1 */ },
8361 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8362 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
8363 : { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8364 : { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
8365 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
8366 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
8367 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8368 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_JumpTarget, 2 /* 1 */ },
8369 : { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8370 : { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
8371 : { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 1 /* 0 */ },
8372 : { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
8373 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8374 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
8375 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8376 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
8377 : { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8378 : { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
8379 : { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8380 : { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
8381 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8382 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
8383 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 1 /* 0 */ },
8384 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
8385 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
8386 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
8387 : { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
8388 : { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
8389 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8390 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
8391 : { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8392 : { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
8393 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8394 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
8395 : { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8396 : { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
8397 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
8398 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
8399 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8400 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_JumpTarget, 2 /* 1 */ },
8401 : { Feature_HasStdEnc|Feature_HasMSA, 1116 /* binsl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8402 : { Feature_HasStdEnc|Feature_HasMSA, 1124 /* binsl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8403 : { Feature_HasStdEnc|Feature_HasMSA, 1132 /* binsl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8404 : { Feature_HasStdEnc|Feature_HasMSA, 1140 /* binsl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8405 : { Feature_HasStdEnc|Feature_HasMSA, 1148 /* binsli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8406 : { Feature_HasStdEnc|Feature_HasMSA, 1157 /* binsli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8407 : { Feature_HasStdEnc|Feature_HasMSA, 1166 /* binsli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8408 : { Feature_HasStdEnc|Feature_HasMSA, 1175 /* binsli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8409 : { Feature_HasStdEnc|Feature_HasMSA, 1184 /* binsr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8410 : { Feature_HasStdEnc|Feature_HasMSA, 1192 /* binsr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8411 : { Feature_HasStdEnc|Feature_HasMSA, 1200 /* binsr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8412 : { Feature_HasStdEnc|Feature_HasMSA, 1208 /* binsr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8413 : { Feature_HasStdEnc|Feature_HasMSA, 1216 /* binsri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8414 : { Feature_HasStdEnc|Feature_HasMSA, 1225 /* binsri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8415 : { Feature_HasStdEnc|Feature_HasMSA, 1234 /* binsri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8416 : { Feature_HasStdEnc|Feature_HasMSA, 1243 /* binsri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8417 : { Feature_InMicroMips|Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8418 : { Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8419 : { Feature_HasStdEnc|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8420 : { Feature_InMicroMips|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8421 : { 0, 1267 /* ble */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8422 : { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
8423 : { 0, 1267 /* ble */, MCK_GPR32AsmReg, 1 /* 0 */ },
8424 : { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
8425 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8426 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
8427 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 1 /* 0 */ },
8428 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
8429 : { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8430 : { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
8431 : { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8432 : { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
8433 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8434 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
8435 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 1 /* 0 */ },
8436 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
8437 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
8438 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
8439 : { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
8440 : { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
8441 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8442 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
8443 : { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8444 : { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
8445 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8446 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
8447 : { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8448 : { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
8449 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
8450 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
8451 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8452 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_JumpTarget, 2 /* 1 */ },
8453 : { 0, 1312 /* blt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8454 : { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
8455 : { 0, 1312 /* blt */, MCK_GPR32AsmReg, 1 /* 0 */ },
8456 : { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
8457 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8458 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
8459 : { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8460 : { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
8461 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8462 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
8463 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8464 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
8465 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8466 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
8467 : { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8468 : { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
8469 : { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
8470 : { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
8471 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8472 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
8473 : { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8474 : { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
8475 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8476 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
8477 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8478 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
8479 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 1 /* 0 */ },
8480 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
8481 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
8482 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
8483 : { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
8484 : { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
8485 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
8486 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
8487 : { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
8488 : { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
8489 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8490 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
8491 : { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8492 : { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
8493 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_GPR32AsmReg, 1 /* 0 */ },
8494 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_JumpTarget, 2 /* 1 */ },
8495 : { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_GPR32AsmReg, 1 /* 0 */ },
8496 : { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_JumpTarget, 2 /* 1 */ },
8497 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8498 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
8499 : { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8500 : { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
8501 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
8502 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
8503 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8504 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_JumpTarget, 2 /* 1 */ },
8505 : { Feature_HasStdEnc|Feature_HasMSA, 1391 /* bmnz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8506 : { Feature_HasStdEnc|Feature_HasMSA, 1398 /* bmnzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8507 : { Feature_HasStdEnc|Feature_HasMSA, 1406 /* bmz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8508 : { Feature_HasStdEnc|Feature_HasMSA, 1412 /* bmzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8509 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8510 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
8511 : { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8512 : { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
8513 : { 0, 1419 /* bne */, MCK_GPR32AsmReg, 1 /* 0 */ },
8514 : { 0, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
8515 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8516 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
8517 : { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8518 : { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
8519 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8520 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
8521 : { Feature_HasStdEnc|Feature_HasMSA, 1428 /* bneg.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8522 : { Feature_HasStdEnc|Feature_HasMSA, 1435 /* bneg.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8523 : { Feature_HasStdEnc|Feature_HasMSA, 1442 /* bneg.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8524 : { Feature_HasStdEnc|Feature_HasMSA, 1449 /* bneg.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8525 : { Feature_HasStdEnc|Feature_HasMSA, 1456 /* bnegi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8526 : { Feature_HasStdEnc|Feature_HasMSA, 1464 /* bnegi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8527 : { Feature_HasStdEnc|Feature_HasMSA, 1472 /* bnegi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8528 : { Feature_HasStdEnc|Feature_HasMSA, 1480 /* bnegi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8529 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8530 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ },
8531 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_GPR32AsmReg, 1 /* 0 */ },
8532 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ },
8533 : { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
8534 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ },
8535 : { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
8536 : { Feature_InMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ },
8537 : { Feature_InMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
8538 : { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
8539 : { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8540 : { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ },
8541 : { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8542 : { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ },
8543 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8544 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
8545 : { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8546 : { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
8547 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8548 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
8549 : { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8550 : { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
8551 : { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
8552 : { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
8553 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
8554 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
8555 : { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
8556 : { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_JumpTarget, 2 /* 1 */ },
8557 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
8558 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_JumpTarget, 2 /* 1 */ },
8559 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8560 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ },
8561 : { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8562 : { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ },
8563 : { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
8564 : { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_JumpTarget, 2 /* 1 */ },
8565 : { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
8566 : { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_JumpTarget, 2 /* 1 */ },
8567 : { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
8568 : { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_JumpTarget, 2 /* 1 */ },
8569 : { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
8570 : { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_JumpTarget, 2 /* 1 */ },
8571 : { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
8572 : { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_JumpTarget, 2 /* 1 */ },
8573 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8574 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ },
8575 : { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8576 : { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ },
8577 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ },
8578 : { Feature_HasDSP|Feature_NotInMicroMips, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ },
8579 : { Feature_InMicroMips|Feature_HasDSPR3, 1582 /* bposge32c */, MCK_JumpTarget, 1 /* 0 */ },
8580 : { Feature_HasStdEnc|Feature_HasMSA, 1606 /* bsel.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8581 : { Feature_HasStdEnc|Feature_HasMSA, 1613 /* bseli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8582 : { Feature_HasStdEnc|Feature_HasMSA, 1621 /* bset.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8583 : { Feature_HasStdEnc|Feature_HasMSA, 1628 /* bset.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8584 : { Feature_HasStdEnc|Feature_HasMSA, 1635 /* bset.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8585 : { Feature_HasStdEnc|Feature_HasMSA, 1642 /* bset.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8586 : { Feature_HasStdEnc|Feature_HasMSA, 1649 /* bseti.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8587 : { Feature_HasStdEnc|Feature_HasMSA, 1657 /* bseti.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8588 : { Feature_HasStdEnc|Feature_HasMSA, 1665 /* bseti.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8589 : { Feature_HasStdEnc|Feature_HasMSA, 1673 /* bseti.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8590 : { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
8591 : { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_JumpTarget, 2 /* 1 */ },
8592 : { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
8593 : { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_JumpTarget, 2 /* 1 */ },
8594 : { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
8595 : { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_JumpTarget, 2 /* 1 */ },
8596 : { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
8597 : { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_JumpTarget, 2 /* 1 */ },
8598 : { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
8599 : { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_JumpTarget, 2 /* 1 */ },
8600 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8601 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8602 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8603 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8604 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8605 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8606 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8607 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8608 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8609 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8610 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8611 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8612 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8613 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8614 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8615 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8616 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8617 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8618 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8619 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8620 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8621 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8622 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8623 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8624 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8625 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8626 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8627 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8628 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8629 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8630 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8631 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8632 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8633 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8634 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8635 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8636 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8637 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8638 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8639 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8640 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8641 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8642 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8643 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8644 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8645 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8646 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8647 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8648 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8649 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8650 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8651 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8652 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8653 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8654 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8655 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8656 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8657 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8658 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8659 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8660 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8661 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8662 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8663 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8664 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8665 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8666 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8667 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8668 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8669 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8670 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8671 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8672 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8673 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8674 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8675 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8676 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8677 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8678 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8679 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8680 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8681 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8682 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8683 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8684 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8685 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8686 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8687 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8688 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8689 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8690 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8691 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8692 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8693 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8694 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8695 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8696 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8697 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8698 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8699 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8700 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8701 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8702 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8703 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8704 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8705 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8706 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8707 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8708 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8709 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8710 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8711 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8712 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8713 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8714 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8715 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8716 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8717 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8718 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8719 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8720 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8721 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8722 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8723 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8724 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8725 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8726 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8727 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8728 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8729 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8730 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8731 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8732 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8733 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8734 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8735 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8736 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8737 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8738 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8739 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8740 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8741 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8742 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8743 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8744 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8745 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8746 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8747 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8748 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8749 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8750 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8751 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8752 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8753 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8754 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8755 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8756 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8757 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8758 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8759 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8760 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8761 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8762 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8763 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8764 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8765 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8766 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8767 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8768 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8769 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8770 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8771 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8772 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8773 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8774 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8775 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8776 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8777 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8778 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8779 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8780 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8781 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8782 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8783 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8784 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8785 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8786 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8787 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8788 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8789 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8790 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8791 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8792 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8793 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8794 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8795 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8796 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8797 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8798 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8799 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8800 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8801 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8802 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8803 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8804 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8805 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8806 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8807 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8808 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8809 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8810 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8811 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8812 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8813 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8814 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8815 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8816 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8817 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8818 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8819 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8820 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8821 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8822 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8823 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8824 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8825 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8826 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8827 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8828 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8829 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8830 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8831 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8832 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8833 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8834 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8835 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8836 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8837 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8838 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8839 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8840 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8841 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8842 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8843 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8844 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8845 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8846 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8847 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8848 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8849 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8850 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8851 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8852 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8853 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8854 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8855 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8856 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8857 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8858 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8859 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8860 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8861 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8862 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8863 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8864 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8865 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8866 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8867 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8868 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8869 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8870 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8871 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
8872 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8873 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8874 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8875 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8876 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
8877 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8878 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8879 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8880 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
8881 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8882 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8883 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8884 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8885 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8886 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ },
8887 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
8888 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_MemOffsetSimm9, 2 /* 1 */ },
8889 : { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
8890 : { Feature_InMicroMips|Feature_NotMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
8891 : { Feature_InMicroMips|Feature_HasMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
8892 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ },
8893 : { Feature_InMicroMips|Feature_HasEVA, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ },
8894 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8895 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8896 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
8897 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
8898 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
8899 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
8900 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
8901 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8902 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
8903 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8904 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
8905 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8906 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8907 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
8908 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8909 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8910 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8911 : { Feature_HasStdEnc|Feature_HasMSA, 2011 /* ceq.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8912 : { Feature_HasStdEnc|Feature_HasMSA, 2017 /* ceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8913 : { Feature_HasStdEnc|Feature_HasMSA, 2023 /* ceq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8914 : { Feature_HasStdEnc|Feature_HasMSA, 2029 /* ceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8915 : { Feature_HasStdEnc|Feature_HasMSA, 2035 /* ceqi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8916 : { Feature_HasStdEnc|Feature_HasMSA, 2042 /* ceqi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8917 : { Feature_HasStdEnc|Feature_HasMSA, 2049 /* ceqi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8918 : { Feature_HasStdEnc|Feature_HasMSA, 2056 /* ceqi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8919 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
8920 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
8921 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
8922 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
8923 : { Feature_InMicroMips, 2068 /* cfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
8924 : { Feature_InMicroMips, 2068 /* cfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
8925 : { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_GPR32AsmReg, 1 /* 0 */ },
8926 : { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_MSACtrlAsmReg, 2 /* 1 */ },
8927 : { Feature_HasMT, 2080 /* cftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
8928 : { Feature_HasMT, 2080 /* cftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
8929 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
8930 : { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
8931 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8932 : { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8933 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
8934 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
8935 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8936 : { Feature_InMicroMips|Feature_HasMips32r6, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
8937 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8938 : { Feature_InMicroMips|Feature_HasMips32r6, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
8939 : { Feature_HasStdEnc|Feature_HasMSA, 2114 /* cle_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8940 : { Feature_HasStdEnc|Feature_HasMSA, 2122 /* cle_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8941 : { Feature_HasStdEnc|Feature_HasMSA, 2130 /* cle_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8942 : { Feature_HasStdEnc|Feature_HasMSA, 2138 /* cle_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8943 : { Feature_HasStdEnc|Feature_HasMSA, 2146 /* cle_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8944 : { Feature_HasStdEnc|Feature_HasMSA, 2154 /* cle_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8945 : { Feature_HasStdEnc|Feature_HasMSA, 2162 /* cle_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8946 : { Feature_HasStdEnc|Feature_HasMSA, 2170 /* cle_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8947 : { Feature_HasStdEnc|Feature_HasMSA, 2178 /* clei_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8948 : { Feature_HasStdEnc|Feature_HasMSA, 2187 /* clei_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8949 : { Feature_HasStdEnc|Feature_HasMSA, 2196 /* clei_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8950 : { Feature_HasStdEnc|Feature_HasMSA, 2205 /* clei_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8951 : { Feature_HasStdEnc|Feature_HasMSA, 2214 /* clei_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8952 : { Feature_HasStdEnc|Feature_HasMSA, 2223 /* clei_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8953 : { Feature_HasStdEnc|Feature_HasMSA, 2232 /* clei_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8954 : { Feature_HasStdEnc|Feature_HasMSA, 2241 /* clei_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8955 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8956 : { Feature_InMicroMips|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8957 : { Feature_HasStdEnc|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8958 : { Feature_InMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8959 : { Feature_HasStdEnc|Feature_HasMSA, 2254 /* clt_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8960 : { Feature_HasStdEnc|Feature_HasMSA, 2262 /* clt_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8961 : { Feature_HasStdEnc|Feature_HasMSA, 2270 /* clt_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8962 : { Feature_HasStdEnc|Feature_HasMSA, 2278 /* clt_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8963 : { Feature_HasStdEnc|Feature_HasMSA, 2286 /* clt_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8964 : { Feature_HasStdEnc|Feature_HasMSA, 2294 /* clt_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8965 : { Feature_HasStdEnc|Feature_HasMSA, 2302 /* clt_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8966 : { Feature_HasStdEnc|Feature_HasMSA, 2310 /* clt_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
8967 : { Feature_HasStdEnc|Feature_HasMSA, 2318 /* clti_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8968 : { Feature_HasStdEnc|Feature_HasMSA, 2327 /* clti_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8969 : { Feature_HasStdEnc|Feature_HasMSA, 2336 /* clti_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8970 : { Feature_HasStdEnc|Feature_HasMSA, 2345 /* clti_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8971 : { Feature_HasStdEnc|Feature_HasMSA, 2354 /* clti_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8972 : { Feature_HasStdEnc|Feature_HasMSA, 2363 /* clti_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8973 : { Feature_HasStdEnc|Feature_HasMSA, 2372 /* clti_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8974 : { Feature_HasStdEnc|Feature_HasMSA, 2381 /* clti_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
8975 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8976 : { Feature_InMicroMips|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8977 : { Feature_HasStdEnc|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8978 : { Feature_InMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8979 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8980 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8981 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8982 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8983 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
8984 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
8985 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8986 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8987 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8988 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8989 : { Feature_InMicroMips|Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8990 : { Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8991 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
8992 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
8993 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8994 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8995 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
8996 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
8997 : { Feature_InMicroMips|Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8998 : { Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
8999 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9000 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9001 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9002 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9003 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9004 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9005 : { Feature_InMicroMips|Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9006 : { Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9007 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9008 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9009 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9010 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9011 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9012 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9013 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9014 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9015 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9016 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9017 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9018 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9019 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9020 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9021 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9022 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9023 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9024 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9025 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9026 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9027 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9028 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9029 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9030 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9031 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9032 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9033 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9034 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9035 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9036 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9037 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9038 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9039 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9040 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9041 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9042 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9043 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9044 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9045 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9046 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9047 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9048 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9049 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9050 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9051 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9052 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9053 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9054 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9055 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9056 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9057 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9058 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9059 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9060 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9061 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9062 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9063 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9064 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9065 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9066 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9067 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9068 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9069 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9070 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9071 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9072 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9073 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9074 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9075 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9076 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9077 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9078 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
9079 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9080 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9081 : { Feature_InMicroMips|Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9082 : { Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9083 : { Feature_InMicroMips|Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9084 : { Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9085 : { Feature_InMicroMips|Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9086 : { Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9087 : { Feature_InMicroMips|Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9088 : { Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9089 : { Feature_InMicroMips|Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9090 : { Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9091 : { Feature_InMicroMips|Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9092 : { Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9093 : { Feature_InMicroMips|Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9094 : { Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9095 : { Feature_InMicroMips|Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9096 : { Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9097 : { Feature_InMicroMips|Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9098 : { Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9099 : { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
9100 : { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
9101 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_GPR64AsmReg, 1 /* 0 */ },
9102 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_MSA128AsmReg, 2 /* 1 */ },
9103 : { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
9104 : { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
9105 : { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9106 : { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
9107 : { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
9108 : { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
9109 : { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
9110 : { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
9111 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9112 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
9113 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2920 /* crc32b */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9114 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2927 /* crc32cb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9115 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2935 /* crc32cd */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9116 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2943 /* crc32ch */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9117 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2951 /* crc32cw */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9118 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2959 /* crc32d */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9119 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2966 /* crc32h */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9120 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2973 /* crc32w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9121 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
9122 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
9123 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
9124 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
9125 : { Feature_InMicroMips, 2985 /* ctc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
9126 : { Feature_InMicroMips, 2985 /* ctc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
9127 : { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_GPR32AsmReg, 2 /* 1 */ },
9128 : { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_MSACtrlAsmReg, 1 /* 0 */ },
9129 : { Feature_HasMT, 2997 /* cttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
9130 : { Feature_HasMT, 2997 /* cttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
9131 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
9132 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
9133 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9134 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9135 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9136 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9137 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9138 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9139 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9140 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9141 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9142 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
9143 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9144 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
9145 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
9146 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ },
9147 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
9148 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ },
9149 : { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
9150 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
9151 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
9152 : { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9153 : { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9154 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9155 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9156 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9157 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9158 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.ps.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
9159 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.ps.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9160 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3052 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
9161 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3052 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9162 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3052 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
9163 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3052 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9164 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3052 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9165 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3052 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
9166 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3052 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9167 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3052 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
9168 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3060 /* cvt.s.l */, MCK_FGR32AsmReg, 1 /* 0 */ },
9169 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3060 /* cvt.s.l */, MCK_FGR64AsmReg, 2 /* 1 */ },
9170 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3060 /* cvt.s.l */, MCK_FGR32AsmReg, 2 /* 1 */ },
9171 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3060 /* cvt.s.l */, MCK_FGR64AsmReg, 1 /* 0 */ },
9172 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3068 /* cvt.s.pl */, MCK_FGR32AsmReg, 1 /* 0 */ },
9173 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3068 /* cvt.s.pl */, MCK_FGR64AsmReg, 2 /* 1 */ },
9174 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3077 /* cvt.s.pu */, MCK_FGR32AsmReg, 1 /* 0 */ },
9175 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3077 /* cvt.s.pu */, MCK_FGR64AsmReg, 2 /* 1 */ },
9176 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3086 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9177 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3086 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9178 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 3086 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9179 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3094 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
9180 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3094 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9181 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3094 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
9182 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3094 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9183 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3094 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9184 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3094 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
9185 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3094 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9186 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3094 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
9187 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3102 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9188 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3102 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9189 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 3102 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9190 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3110 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9191 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3110 /* dadd */, MCK_GPR64AsmReg, 1 /* 0 */ },
9192 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3110 /* dadd */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9193 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3110 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9194 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3115 /* daddi */, MCK_GPR64AsmReg, 1 /* 0 */ },
9195 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3115 /* daddi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9196 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3121 /* daddiu */, MCK_GPR64AsmReg, 1 /* 0 */ },
9197 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3121 /* daddiu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9198 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3128 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9199 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3128 /* daddu */, MCK_GPR64AsmReg, 1 /* 0 */ },
9200 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3128 /* daddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9201 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3128 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9202 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3134 /* dahi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9203 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3139 /* dalign */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9204 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3146 /* dati */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9205 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3151 /* daui */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9206 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3156 /* dbitswap */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9207 : { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3165 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9208 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3165 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9209 : { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3170 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9210 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3170 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9211 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3175 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9212 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3175 /* ddiv */, MCK_GPR64AsmReg, 1 /* 0 */ },
9213 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3175 /* ddiv */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
9214 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3175 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9215 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3175 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9216 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3175 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9217 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3180 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9218 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3180 /* ddivu */, MCK_GPR64AsmReg, 1 /* 0 */ },
9219 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3180 /* ddivu */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
9220 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3180 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9221 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3180 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9222 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3180 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9223 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3192 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9224 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3192 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9225 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3192 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9226 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3197 /* dextm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9227 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3203 /* dextu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9228 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3209 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
9229 : { Feature_InMicroMips|Feature_HasMips32r6, 3209 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
9230 : { Feature_InMicroMips, 3209 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
9231 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3212 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9232 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3212 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9233 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3212 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9234 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3217 /* dinsm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9235 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3223 /* dinsu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9236 : { Feature_HasStdEnc|Feature_HasMips32r6, 3229 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9237 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32AsmReg, 1 /* 0 */ },
9238 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ },
9239 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
9240 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ },
9241 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ },
9242 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3229 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9243 : { Feature_InMicroMips|Feature_NotMips32r6, 3229 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9244 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3229 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9245 : { Feature_InMicroMips|Feature_HasMips32r6, 3229 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9246 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9247 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9248 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3229 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
9249 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3233 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
9250 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3233 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
9251 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3233 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
9252 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3233 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
9253 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3239 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9254 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3239 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9255 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 3239 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
9256 : { Feature_HasStdEnc|Feature_HasMSA, 3245 /* div_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9257 : { Feature_HasStdEnc|Feature_HasMSA, 3253 /* div_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9258 : { Feature_HasStdEnc|Feature_HasMSA, 3261 /* div_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9259 : { Feature_HasStdEnc|Feature_HasMSA, 3269 /* div_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9260 : { Feature_HasStdEnc|Feature_HasMSA, 3277 /* div_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9261 : { Feature_HasStdEnc|Feature_HasMSA, 3285 /* div_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9262 : { Feature_HasStdEnc|Feature_HasMSA, 3293 /* div_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9263 : { Feature_HasStdEnc|Feature_HasMSA, 3301 /* div_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9264 : { Feature_HasStdEnc|Feature_HasMips32r6, 3309 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9265 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3309 /* divu */, MCK_GPR32AsmReg, 1 /* 0 */ },
9266 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3309 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ },
9267 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3309 /* divu */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
9268 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3309 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ },
9269 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3309 /* divu */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ },
9270 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3309 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9271 : { Feature_InMicroMips|Feature_NotMips32r6, 3309 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9272 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3309 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9273 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3309 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9274 : { Feature_InMicroMips|Feature_HasMips32r6, 3309 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9275 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3309 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9276 : { 0, 3314 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
9277 : { 0, 3314 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
9278 : { 0, 3314 /* dla */, MCK_Mem, 2 /* 1 */ },
9279 : { 0, 3318 /* dli */, MCK_GPR64AsmReg, 1 /* 0 */ },
9280 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 3322 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9281 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3322 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9282 : { Feature_NotInMicroMips, 3327 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9283 : { Feature_NotInMicroMips, 3327 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9284 : { Feature_HasMips64, 3327 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9285 : { Feature_HasMips64, 3327 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9286 : { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3333 /* dmfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
9287 : { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3333 /* dmfc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9288 : { 0, 3339 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
9289 : { 0, 3339 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9290 : { Feature_HasCnMips, 3339 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9291 : { Feature_HasMips64, 3339 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
9292 : { Feature_HasMips64, 3339 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9293 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3345 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9294 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3345 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9295 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3345 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9296 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3345 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9297 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3352 /* dmod */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9298 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3357 /* dmodu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9299 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3363 /* dmt */, MCK_GPR32AsmReg, 1 /* 0 */ },
9300 : { Feature_NotInMicroMips, 3367 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9301 : { Feature_NotInMicroMips, 3367 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9302 : { Feature_HasMips64, 3367 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9303 : { Feature_HasMips64, 3367 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9304 : { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3373 /* dmtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
9305 : { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3373 /* dmtc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9306 : { 0, 3379 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
9307 : { 0, 3379 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9308 : { Feature_HasCnMips, 3379 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9309 : { Feature_HasMips64, 3379 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
9310 : { Feature_HasMips64, 3379 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9311 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3385 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9312 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3385 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9313 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3385 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
9314 : { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3385 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9315 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3392 /* dmuh */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9316 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3397 /* dmuhu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9317 : { Feature_HasCnMips, 3403 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9318 : { Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, 3403 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9319 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3403 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9320 : { Feature_HasCnMips, 3403 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9321 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3403 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9322 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3408 /* dmulo */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9323 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3414 /* dmulou */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9324 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3421 /* dmult */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9325 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3427 /* dmultu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9326 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3434 /* dmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9327 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3440 /* dneg */, MCK_GPR64AsmReg, 1 /* 0 */ },
9328 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3440 /* dneg */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9329 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3445 /* dnegu */, MCK_GPR64AsmReg, 1 /* 0 */ },
9330 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3445 /* dnegu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9331 : { Feature_HasStdEnc|Feature_HasMSA, 3451 /* dotp_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9332 : { Feature_HasStdEnc|Feature_HasMSA, 3460 /* dotp_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9333 : { Feature_HasStdEnc|Feature_HasMSA, 3469 /* dotp_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9334 : { Feature_HasStdEnc|Feature_HasMSA, 3478 /* dotp_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9335 : { Feature_HasStdEnc|Feature_HasMSA, 3487 /* dotp_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9336 : { Feature_HasStdEnc|Feature_HasMSA, 3496 /* dotp_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9337 : { Feature_InMicroMips|Feature_HasDSPR2, 3505 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9338 : { Feature_InMicroMips|Feature_HasDSPR2, 3505 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9339 : { Feature_HasDSPR2, 3505 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9340 : { Feature_HasDSPR2, 3505 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9341 : { Feature_HasStdEnc|Feature_HasMSA, 3514 /* dpadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9342 : { Feature_HasStdEnc|Feature_HasMSA, 3524 /* dpadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9343 : { Feature_HasStdEnc|Feature_HasMSA, 3534 /* dpadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9344 : { Feature_HasStdEnc|Feature_HasMSA, 3544 /* dpadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9345 : { Feature_HasStdEnc|Feature_HasMSA, 3554 /* dpadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9346 : { Feature_HasStdEnc|Feature_HasMSA, 3564 /* dpadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9347 : { Feature_InMicroMips|Feature_HasDSP, 3574 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9348 : { Feature_InMicroMips|Feature_HasDSP, 3574 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9349 : { Feature_HasDSP, 3574 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9350 : { Feature_HasDSP, 3574 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9351 : { Feature_InMicroMips|Feature_HasDSP, 3586 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9352 : { Feature_InMicroMips|Feature_HasDSP, 3586 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9353 : { Feature_HasDSP, 3586 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9354 : { Feature_HasDSP, 3586 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9355 : { Feature_InMicroMips|Feature_HasDSPR2, 3598 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9356 : { Feature_InMicroMips|Feature_HasDSPR2, 3598 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9357 : { Feature_HasDSPR2, 3598 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9358 : { Feature_HasDSPR2, 3598 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9359 : { Feature_InMicroMips|Feature_HasDSPR2, 3611 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9360 : { Feature_InMicroMips|Feature_HasDSPR2, 3611 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9361 : { Feature_HasDSPR2, 3611 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9362 : { Feature_HasDSPR2, 3611 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9363 : { Feature_InMicroMips|Feature_HasDSP, 3625 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9364 : { Feature_InMicroMips|Feature_HasDSP, 3625 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9365 : { Feature_HasDSP, 3625 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9366 : { Feature_HasDSP, 3625 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9367 : { Feature_InMicroMips|Feature_HasDSP, 3636 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9368 : { Feature_InMicroMips|Feature_HasDSP, 3636 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9369 : { Feature_HasDSP, 3636 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9370 : { Feature_HasDSP, 3636 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9371 : { Feature_InMicroMips|Feature_HasDSPR2, 3647 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9372 : { Feature_InMicroMips|Feature_HasDSPR2, 3647 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9373 : { Feature_HasDSPR2, 3647 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9374 : { Feature_HasDSPR2, 3647 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9375 : { Feature_HasCnMips, 3657 /* dpop */, MCK_GPR64AsmReg, 1 /* 0 */ },
9376 : { Feature_HasCnMips, 3657 /* dpop */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9377 : { Feature_InMicroMips|Feature_HasDSPR2, 3662 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9378 : { Feature_InMicroMips|Feature_HasDSPR2, 3662 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9379 : { Feature_HasDSPR2, 3662 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9380 : { Feature_HasDSPR2, 3662 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9381 : { Feature_InMicroMips|Feature_HasDSP, 3671 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9382 : { Feature_InMicroMips|Feature_HasDSP, 3671 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9383 : { Feature_HasDSP, 3671 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9384 : { Feature_HasDSP, 3671 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9385 : { Feature_InMicroMips|Feature_HasDSP, 3683 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9386 : { Feature_InMicroMips|Feature_HasDSP, 3683 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9387 : { Feature_HasDSP, 3683 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9388 : { Feature_HasDSP, 3683 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9389 : { Feature_InMicroMips|Feature_HasDSPR2, 3695 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9390 : { Feature_InMicroMips|Feature_HasDSPR2, 3695 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9391 : { Feature_HasDSPR2, 3695 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9392 : { Feature_HasDSPR2, 3695 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9393 : { Feature_InMicroMips|Feature_HasDSPR2, 3708 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9394 : { Feature_InMicroMips|Feature_HasDSPR2, 3708 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9395 : { Feature_HasDSPR2, 3708 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9396 : { Feature_HasDSPR2, 3708 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9397 : { Feature_InMicroMips|Feature_HasDSP, 3722 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9398 : { Feature_InMicroMips|Feature_HasDSP, 3722 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9399 : { Feature_HasDSP, 3722 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9400 : { Feature_HasDSP, 3722 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9401 : { Feature_InMicroMips|Feature_HasDSP, 3733 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9402 : { Feature_InMicroMips|Feature_HasDSP, 3733 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9403 : { Feature_HasDSP, 3733 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9404 : { Feature_HasDSP, 3733 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9405 : { Feature_HasStdEnc|Feature_HasMSA, 3744 /* dpsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9406 : { Feature_HasStdEnc|Feature_HasMSA, 3754 /* dpsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9407 : { Feature_HasStdEnc|Feature_HasMSA, 3764 /* dpsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9408 : { Feature_HasStdEnc|Feature_HasMSA, 3774 /* dpsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9409 : { Feature_HasStdEnc|Feature_HasMSA, 3784 /* dpsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9410 : { Feature_HasStdEnc|Feature_HasMSA, 3794 /* dpsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9411 : { Feature_InMicroMips|Feature_HasDSPR2, 3804 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9412 : { Feature_InMicroMips|Feature_HasDSPR2, 3804 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9413 : { Feature_HasDSPR2, 3804 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9414 : { Feature_HasDSPR2, 3804 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9415 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3814 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9416 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3814 /* drem */, MCK_GPR64AsmReg, 1 /* 0 */ },
9417 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3814 /* drem */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9418 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3814 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9419 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3819 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9420 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3819 /* dremu */, MCK_GPR64AsmReg, 1 /* 0 */ },
9421 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3819 /* dremu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9422 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3819 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9423 : { Feature_HasStdEnc|Feature_HasMips64, 3825 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9424 : { Feature_HasStdEnc|Feature_HasMips64, 3825 /* drol */, MCK_GPR32AsmReg, 1 /* 0 */ },
9425 : { Feature_HasStdEnc|Feature_HasMips64, 3825 /* drol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9426 : { Feature_HasStdEnc|Feature_HasMips64, 3825 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9427 : { Feature_HasStdEnc|Feature_HasMips64, 3830 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9428 : { Feature_HasStdEnc|Feature_HasMips64, 3830 /* dror */, MCK_GPR32AsmReg, 1 /* 0 */ },
9429 : { Feature_HasStdEnc|Feature_HasMips64, 3830 /* dror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9430 : { Feature_HasStdEnc|Feature_HasMips64, 3830 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9431 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3835 /* drotr */, MCK_GPR64AsmReg, 1 /* 0 */ },
9432 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3835 /* drotr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9433 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3841 /* drotr32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9434 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3841 /* drotr32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9435 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3849 /* drotrv */, MCK_GPR32AsmReg, 4 /* 2 */ },
9436 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3849 /* drotrv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9437 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3856 /* dsbh */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9438 : { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3861 /* dshd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9439 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3866 /* dsll */, MCK_GPR32AsmReg, 2 /* 1 */ },
9440 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3866 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ },
9441 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3866 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ },
9442 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3866 /* dsll */, MCK_GPR32AsmReg, 4 /* 2 */ },
9443 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3866 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9444 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3866 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9445 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3871 /* dsll32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9446 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3871 /* dsll32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9447 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3878 /* dsllv */, MCK_GPR32AsmReg, 4 /* 2 */ },
9448 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3878 /* dsllv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9449 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3884 /* dsra */, MCK_GPR64AsmReg, 1 /* 0 */ },
9450 : { Feature_HasStdEnc|Feature_HasMips3, 3884 /* dsra */, MCK_GPR32AsmReg, 4 /* 2 */ },
9451 : { Feature_HasStdEnc|Feature_HasMips3, 3884 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9452 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3884 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9453 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3889 /* dsra32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9454 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3889 /* dsra32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9455 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3896 /* dsrav */, MCK_GPR32AsmReg, 4 /* 2 */ },
9456 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3896 /* dsrav */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9457 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3902 /* dsrl */, MCK_GPR32AsmReg, 2 /* 1 */ },
9458 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3902 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ },
9459 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3902 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ },
9460 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3902 /* dsrl */, MCK_GPR32AsmReg, 4 /* 2 */ },
9461 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3902 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9462 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3902 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9463 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3907 /* dsrl32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9464 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3907 /* dsrl32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9465 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3914 /* dsrlv */, MCK_GPR32AsmReg, 4 /* 2 */ },
9466 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3914 /* dsrlv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9467 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3920 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9468 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3920 /* dsub */, MCK_GPR64AsmReg, 1 /* 0 */ },
9469 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3920 /* dsub */, MCK_InvNum, 2 /* 1 */ },
9470 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3920 /* dsub */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9471 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3920 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9472 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3920 /* dsub */, MCK_InvNum, 4 /* 2 */ },
9473 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3925 /* dsubi */, MCK_GPR64AsmReg, 1 /* 0 */ },
9474 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3925 /* dsubi */, MCK_InvNum, 2 /* 1 */ },
9475 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3925 /* dsubi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9476 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3925 /* dsubi */, MCK_InvNum, 4 /* 2 */ },
9477 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3931 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9478 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3931 /* dsubu */, MCK_GPR64AsmReg, 1 /* 0 */ },
9479 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3931 /* dsubu */, MCK_InvNum, 2 /* 1 */ },
9480 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3931 /* dsubu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
9481 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3931 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9482 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3931 /* dsubu */, MCK_InvNum, 4 /* 2 */ },
9483 : { Feature_HasStdEnc|Feature_HasMips32r6, 3937 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9484 : { Feature_InMicroMips|Feature_HasMips32r6, 3937 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9485 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3941 /* dvpe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9486 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3950 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
9487 : { Feature_InMicroMips|Feature_HasMips32r6, 3950 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
9488 : { Feature_InMicroMips, 3950 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
9489 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3953 /* emt */, MCK_GPR32AsmReg, 1 /* 0 */ },
9490 : { Feature_HasStdEnc|Feature_HasMips32r6, 3969 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9491 : { Feature_InMicroMips|Feature_HasMips32r6, 3969 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9492 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3973 /* evpe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9493 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3978 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9494 : { Feature_InMicroMips|Feature_NotMips32r6, 3978 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9495 : { Feature_InMicroMips|Feature_HasMips32r6, 3978 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9496 : { Feature_InMicroMips|Feature_HasDSP, 3982 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9497 : { Feature_InMicroMips|Feature_HasDSP, 3982 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9498 : { Feature_HasDSP, 3982 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9499 : { Feature_HasDSP, 3982 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9500 : { Feature_InMicroMips|Feature_HasDSP, 3987 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9501 : { Feature_InMicroMips|Feature_HasDSP, 3987 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9502 : { Feature_HasDSP, 3987 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9503 : { Feature_HasDSP, 3987 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9504 : { Feature_InMicroMips|Feature_HasDSP, 3994 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9505 : { Feature_InMicroMips|Feature_HasDSP, 3994 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9506 : { Feature_HasDSP, 3994 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9507 : { Feature_HasDSP, 3994 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9508 : { Feature_InMicroMips|Feature_HasDSP, 4002 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9509 : { Feature_InMicroMips|Feature_HasDSP, 4002 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9510 : { Feature_HasDSP, 4002 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9511 : { Feature_HasDSP, 4002 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9512 : { Feature_InMicroMips|Feature_HasDSP, 4008 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9513 : { Feature_InMicroMips|Feature_HasDSP, 4008 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9514 : { Feature_HasDSP, 4008 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9515 : { Feature_HasDSP, 4008 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9516 : { Feature_InMicroMips|Feature_HasDSP, 4015 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9517 : { Feature_InMicroMips|Feature_HasDSP, 4015 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9518 : { Feature_HasDSP, 4015 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9519 : { Feature_HasDSP, 4015 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9520 : { Feature_InMicroMips|Feature_HasDSP, 4024 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9521 : { Feature_InMicroMips|Feature_HasDSP, 4024 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9522 : { Feature_HasDSP, 4024 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9523 : { Feature_HasDSP, 4024 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
9524 : { Feature_InMicroMips|Feature_HasDSP, 4034 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9525 : { Feature_InMicroMips|Feature_HasDSP, 4034 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
9526 : { Feature_HasDSP, 4034 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9527 : { Feature_HasDSP, 4034 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
9528 : { Feature_InMicroMips|Feature_HasDSP, 4043 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9529 : { Feature_InMicroMips|Feature_HasDSP, 4043 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9530 : { Feature_HasDSP, 4043 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9531 : { Feature_HasDSP, 4043 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9532 : { Feature_InMicroMips|Feature_HasDSP, 4051 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9533 : { Feature_InMicroMips|Feature_HasDSP, 4051 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9534 : { Feature_HasDSP, 4051 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9535 : { Feature_HasDSP, 4051 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9536 : { Feature_InMicroMips|Feature_HasDSP, 4061 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9537 : { Feature_InMicroMips|Feature_HasDSP, 4061 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9538 : { Feature_HasDSP, 4061 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9539 : { Feature_HasDSP, 4061 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9540 : { Feature_InMicroMips|Feature_HasDSP, 4072 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9541 : { Feature_InMicroMips|Feature_HasDSP, 4072 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9542 : { Feature_HasDSP, 4072 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
9543 : { Feature_HasDSP, 4072 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
9544 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4082 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
9545 : { Feature_HasMips64|Feature_HasCnMips, 4082 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
9546 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4082 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9547 : { Feature_HasMips64|Feature_HasCnMips, 4082 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9548 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4087 /* exts32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
9549 : { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4087 /* exts32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9550 : { Feature_HasStdEnc|Feature_HasMSA, 4094 /* fadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9551 : { Feature_HasStdEnc|Feature_HasMSA, 4101 /* fadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9552 : { Feature_HasStdEnc|Feature_HasMSA, 4108 /* fcaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9553 : { Feature_HasStdEnc|Feature_HasMSA, 4115 /* fcaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9554 : { Feature_HasStdEnc|Feature_HasMSA, 4122 /* fceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9555 : { Feature_HasStdEnc|Feature_HasMSA, 4129 /* fceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9556 : { Feature_HasStdEnc|Feature_HasMSA, 4136 /* fclass.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9557 : { Feature_HasStdEnc|Feature_HasMSA, 4145 /* fclass.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9558 : { Feature_HasStdEnc|Feature_HasMSA, 4154 /* fcle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9559 : { Feature_HasStdEnc|Feature_HasMSA, 4161 /* fcle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9560 : { Feature_HasStdEnc|Feature_HasMSA, 4168 /* fclt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9561 : { Feature_HasStdEnc|Feature_HasMSA, 4175 /* fclt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9562 : { Feature_HasStdEnc|Feature_HasMSA, 4182 /* fcne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9563 : { Feature_HasStdEnc|Feature_HasMSA, 4189 /* fcne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9564 : { Feature_HasStdEnc|Feature_HasMSA, 4196 /* fcor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9565 : { Feature_HasStdEnc|Feature_HasMSA, 4203 /* fcor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9566 : { Feature_HasStdEnc|Feature_HasMSA, 4210 /* fcueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9567 : { Feature_HasStdEnc|Feature_HasMSA, 4218 /* fcueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9568 : { Feature_HasStdEnc|Feature_HasMSA, 4226 /* fcule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9569 : { Feature_HasStdEnc|Feature_HasMSA, 4234 /* fcule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9570 : { Feature_HasStdEnc|Feature_HasMSA, 4242 /* fcult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9571 : { Feature_HasStdEnc|Feature_HasMSA, 4250 /* fcult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9572 : { Feature_HasStdEnc|Feature_HasMSA, 4258 /* fcun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9573 : { Feature_HasStdEnc|Feature_HasMSA, 4265 /* fcun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9574 : { Feature_HasStdEnc|Feature_HasMSA, 4272 /* fcune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9575 : { Feature_HasStdEnc|Feature_HasMSA, 4280 /* fcune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9576 : { Feature_HasStdEnc|Feature_HasMSA, 4288 /* fdiv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9577 : { Feature_HasStdEnc|Feature_HasMSA, 4295 /* fdiv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9578 : { Feature_HasStdEnc|Feature_HasMSA, 4302 /* fexdo.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9579 : { Feature_HasStdEnc|Feature_HasMSA, 4310 /* fexdo.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9580 : { Feature_HasStdEnc|Feature_HasMSA, 4318 /* fexp2.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9581 : { Feature_HasStdEnc|Feature_HasMSA, 4326 /* fexp2.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9582 : { Feature_HasStdEnc|Feature_HasMSA, 4334 /* fexupl.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9583 : { Feature_HasStdEnc|Feature_HasMSA, 4343 /* fexupl.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9584 : { Feature_HasStdEnc|Feature_HasMSA, 4352 /* fexupr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9585 : { Feature_HasStdEnc|Feature_HasMSA, 4361 /* fexupr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9586 : { Feature_HasStdEnc|Feature_HasMSA, 4370 /* ffint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9587 : { Feature_HasStdEnc|Feature_HasMSA, 4380 /* ffint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9588 : { Feature_HasStdEnc|Feature_HasMSA, 4390 /* ffint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9589 : { Feature_HasStdEnc|Feature_HasMSA, 4400 /* ffint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9590 : { Feature_HasStdEnc|Feature_HasMSA, 4410 /* ffql.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9591 : { Feature_HasStdEnc|Feature_HasMSA, 4417 /* ffql.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9592 : { Feature_HasStdEnc|Feature_HasMSA, 4424 /* ffqr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9593 : { Feature_HasStdEnc|Feature_HasMSA, 4431 /* ffqr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9594 : { Feature_HasStdEnc|Feature_HasMSA, 4438 /* fill.b */, MCK_GPR32AsmReg, 2 /* 1 */ },
9595 : { Feature_HasStdEnc|Feature_HasMSA, 4438 /* fill.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
9596 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4445 /* fill.d */, MCK_GPR64AsmReg, 2 /* 1 */ },
9597 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4445 /* fill.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
9598 : { Feature_HasStdEnc|Feature_HasMSA, 4452 /* fill.h */, MCK_GPR32AsmReg, 2 /* 1 */ },
9599 : { Feature_HasStdEnc|Feature_HasMSA, 4452 /* fill.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
9600 : { Feature_HasStdEnc|Feature_HasMSA, 4459 /* fill.w */, MCK_GPR32AsmReg, 2 /* 1 */ },
9601 : { Feature_HasStdEnc|Feature_HasMSA, 4459 /* fill.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
9602 : { Feature_HasStdEnc|Feature_HasMSA, 4466 /* flog2.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9603 : { Feature_HasStdEnc|Feature_HasMSA, 4474 /* flog2.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9604 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4482 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
9605 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4482 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
9606 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4492 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9607 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4492 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9608 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4492 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
9609 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4492 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
9610 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4502 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
9611 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4502 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9612 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4502 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
9613 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4502 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9614 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4502 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
9615 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4502 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9616 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4502 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
9617 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4502 /* floor.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
9618 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4512 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9619 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4512 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9620 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 4512 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
9621 : { Feature_HasStdEnc|Feature_HasMSA, 4522 /* fmadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9622 : { Feature_HasStdEnc|Feature_HasMSA, 4530 /* fmadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9623 : { Feature_HasStdEnc|Feature_HasMSA, 4538 /* fmax.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9624 : { Feature_HasStdEnc|Feature_HasMSA, 4545 /* fmax.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9625 : { Feature_HasStdEnc|Feature_HasMSA, 4552 /* fmax_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9626 : { Feature_HasStdEnc|Feature_HasMSA, 4561 /* fmax_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9627 : { Feature_HasStdEnc|Feature_HasMSA, 4570 /* fmin.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9628 : { Feature_HasStdEnc|Feature_HasMSA, 4577 /* fmin.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9629 : { Feature_HasStdEnc|Feature_HasMSA, 4584 /* fmin_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9630 : { Feature_HasStdEnc|Feature_HasMSA, 4593 /* fmin_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9631 : { Feature_HasStdEnc|Feature_HasMSA, 4602 /* fmsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9632 : { Feature_HasStdEnc|Feature_HasMSA, 4610 /* fmsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9633 : { Feature_HasStdEnc|Feature_HasMSA, 4618 /* fmul.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9634 : { Feature_HasStdEnc|Feature_HasMSA, 4625 /* fmul.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9635 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 4632 /* fork */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9636 : { Feature_HasStdEnc|Feature_HasMSA, 4637 /* frcp.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9637 : { Feature_HasStdEnc|Feature_HasMSA, 4644 /* frcp.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9638 : { Feature_HasStdEnc|Feature_HasMSA, 4651 /* frint.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9639 : { Feature_HasStdEnc|Feature_HasMSA, 4659 /* frint.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9640 : { Feature_HasStdEnc|Feature_HasMSA, 4667 /* frsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9641 : { Feature_HasStdEnc|Feature_HasMSA, 4676 /* frsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9642 : { Feature_HasStdEnc|Feature_HasMSA, 4685 /* fsaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9643 : { Feature_HasStdEnc|Feature_HasMSA, 4692 /* fsaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9644 : { Feature_HasStdEnc|Feature_HasMSA, 4699 /* fseq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9645 : { Feature_HasStdEnc|Feature_HasMSA, 4706 /* fseq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9646 : { Feature_HasStdEnc|Feature_HasMSA, 4713 /* fsle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9647 : { Feature_HasStdEnc|Feature_HasMSA, 4720 /* fsle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9648 : { Feature_HasStdEnc|Feature_HasMSA, 4727 /* fslt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9649 : { Feature_HasStdEnc|Feature_HasMSA, 4734 /* fslt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9650 : { Feature_HasStdEnc|Feature_HasMSA, 4741 /* fsne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9651 : { Feature_HasStdEnc|Feature_HasMSA, 4748 /* fsne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9652 : { Feature_HasStdEnc|Feature_HasMSA, 4755 /* fsor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9653 : { Feature_HasStdEnc|Feature_HasMSA, 4762 /* fsor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9654 : { Feature_HasStdEnc|Feature_HasMSA, 4769 /* fsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9655 : { Feature_HasStdEnc|Feature_HasMSA, 4777 /* fsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9656 : { Feature_HasStdEnc|Feature_HasMSA, 4785 /* fsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9657 : { Feature_HasStdEnc|Feature_HasMSA, 4792 /* fsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9658 : { Feature_HasStdEnc|Feature_HasMSA, 4799 /* fsueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9659 : { Feature_HasStdEnc|Feature_HasMSA, 4807 /* fsueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9660 : { Feature_HasStdEnc|Feature_HasMSA, 4815 /* fsule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9661 : { Feature_HasStdEnc|Feature_HasMSA, 4823 /* fsule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9662 : { Feature_HasStdEnc|Feature_HasMSA, 4831 /* fsult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9663 : { Feature_HasStdEnc|Feature_HasMSA, 4839 /* fsult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9664 : { Feature_HasStdEnc|Feature_HasMSA, 4847 /* fsun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9665 : { Feature_HasStdEnc|Feature_HasMSA, 4854 /* fsun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9666 : { Feature_HasStdEnc|Feature_HasMSA, 4861 /* fsune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9667 : { Feature_HasStdEnc|Feature_HasMSA, 4869 /* fsune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9668 : { Feature_HasStdEnc|Feature_HasMSA, 4877 /* ftint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9669 : { Feature_HasStdEnc|Feature_HasMSA, 4887 /* ftint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9670 : { Feature_HasStdEnc|Feature_HasMSA, 4897 /* ftint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9671 : { Feature_HasStdEnc|Feature_HasMSA, 4907 /* ftint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9672 : { Feature_HasStdEnc|Feature_HasMSA, 4917 /* ftq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9673 : { Feature_HasStdEnc|Feature_HasMSA, 4923 /* ftq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9674 : { Feature_HasStdEnc|Feature_HasMSA, 4929 /* ftrunc_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9675 : { Feature_HasStdEnc|Feature_HasMSA, 4940 /* ftrunc_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9676 : { Feature_HasStdEnc|Feature_HasMSA, 4951 /* ftrunc_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9677 : { Feature_HasStdEnc|Feature_HasMSA, 4962 /* ftrunc_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
9678 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4973 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ },
9679 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4973 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ },
9680 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4979 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ },
9681 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4979 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ },
9682 : { Feature_HasStdEnc|Feature_HasMSA, 4985 /* hadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9683 : { Feature_HasStdEnc|Feature_HasMSA, 4994 /* hadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9684 : { Feature_HasStdEnc|Feature_HasMSA, 5003 /* hadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9685 : { Feature_HasStdEnc|Feature_HasMSA, 5012 /* hadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9686 : { Feature_HasStdEnc|Feature_HasMSA, 5021 /* hadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9687 : { Feature_HasStdEnc|Feature_HasMSA, 5030 /* hadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9688 : { Feature_HasStdEnc|Feature_HasMSA, 5039 /* hsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9689 : { Feature_HasStdEnc|Feature_HasMSA, 5048 /* hsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9690 : { Feature_HasStdEnc|Feature_HasMSA, 5057 /* hsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9691 : { Feature_HasStdEnc|Feature_HasMSA, 5066 /* hsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9692 : { Feature_HasStdEnc|Feature_HasMSA, 5075 /* hsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9693 : { Feature_HasStdEnc|Feature_HasMSA, 5084 /* hsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9694 : { Feature_HasStdEnc|Feature_HasMSA, 5101 /* ilvev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9695 : { Feature_HasStdEnc|Feature_HasMSA, 5109 /* ilvev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9696 : { Feature_HasStdEnc|Feature_HasMSA, 5117 /* ilvev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9697 : { Feature_HasStdEnc|Feature_HasMSA, 5125 /* ilvev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9698 : { Feature_HasStdEnc|Feature_HasMSA, 5133 /* ilvl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9699 : { Feature_HasStdEnc|Feature_HasMSA, 5140 /* ilvl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9700 : { Feature_HasStdEnc|Feature_HasMSA, 5147 /* ilvl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9701 : { Feature_HasStdEnc|Feature_HasMSA, 5154 /* ilvl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9702 : { Feature_HasStdEnc|Feature_HasMSA, 5161 /* ilvod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9703 : { Feature_HasStdEnc|Feature_HasMSA, 5169 /* ilvod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9704 : { Feature_HasStdEnc|Feature_HasMSA, 5177 /* ilvod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9705 : { Feature_HasStdEnc|Feature_HasMSA, 5185 /* ilvod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9706 : { Feature_HasStdEnc|Feature_HasMSA, 5193 /* ilvr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9707 : { Feature_HasStdEnc|Feature_HasMSA, 5200 /* ilvr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9708 : { Feature_HasStdEnc|Feature_HasMSA, 5207 /* ilvr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9709 : { Feature_HasStdEnc|Feature_HasMSA, 5214 /* ilvr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9710 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5221 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9711 : { Feature_InMicroMips|Feature_NotMips32r6, 5221 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9712 : { Feature_InMicroMips|Feature_HasMips32r6, 5221 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9713 : { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.b */, MCK_GPR32AsmReg, 16 /* 4 */ },
9714 : { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
9715 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5234 /* insert.d */, MCK_GPR64AsmReg, 16 /* 4 */ },
9716 : { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5234 /* insert.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
9717 : { Feature_HasStdEnc|Feature_HasMSA, 5243 /* insert.h */, MCK_GPR32AsmReg, 16 /* 4 */ },
9718 : { Feature_HasStdEnc|Feature_HasMSA, 5243 /* insert.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
9719 : { Feature_HasStdEnc|Feature_HasMSA, 5252 /* insert.w */, MCK_GPR32AsmReg, 16 /* 4 */ },
9720 : { Feature_HasStdEnc|Feature_HasMSA, 5252 /* insert.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
9721 : { Feature_InMicroMips|Feature_HasDSP, 5261 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9722 : { Feature_HasDSP, 5261 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9723 : { Feature_HasStdEnc|Feature_HasMSA, 5266 /* insve.b */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
9724 : { Feature_HasStdEnc|Feature_HasMSA, 5274 /* insve.d */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
9725 : { Feature_HasStdEnc|Feature_HasMSA, 5282 /* insve.h */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
9726 : { Feature_HasStdEnc|Feature_HasMSA, 5290 /* insve.w */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
9727 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5298 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ },
9728 : { Feature_InMicroMips|Feature_NotMips32r6, 5298 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ },
9729 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5298 /* j */, MCK_JumpTarget, 1 /* 0 */ },
9730 : { 0, 5300 /* jal */, MCK_GPR32AsmReg, 1 /* 0 */ },
9731 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5300 /* jal */, MCK_JumpTarget, 1 /* 0 */ },
9732 : { Feature_InMicroMips|Feature_HasMips32r6, 5300 /* jal */, MCK_JumpTarget, 1 /* 0 */ },
9733 : { 0, 5300 /* jal */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9734 : { Feature_InMicroMips|Feature_NotMips32r6, 5304 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9735 : { Feature_InMicroMips|Feature_HasMips32r6, 5304 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9736 : { Feature_NotInMicroMips, 5304 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9737 : { Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, 5304 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9738 : { Feature_InMicroMips|Feature_NotMips32r6, 5304 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9739 : { Feature_NotInMips16Mode, 5304 /* jalr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9740 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, 5309 /* jalr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
9741 : { Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, 5309 /* jalr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
9742 : { Feature_HasStdEnc|Feature_HasMips32, 5309 /* jalr.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9743 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5309 /* jalr.hb */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
9744 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5317 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9745 : { Feature_InMicroMips|Feature_HasMips32r6, 5317 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9746 : { Feature_HasStdEnc|Feature_HasMips64r6, 5317 /* jalrc */, MCK_GPR64AsmReg, 1 /* 0 */ },
9747 : { Feature_InMicroMips|Feature_HasMips32r6, 5317 /* jalrc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9748 : { Feature_InMicroMips|Feature_HasMips32r6, 5323 /* jalrc.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
9749 : { Feature_InMicroMips|Feature_HasMips32r6, 5323 /* jalrc.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9750 : { Feature_InMicroMips|Feature_NotMips32r6, 5332 /* jalrs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9751 : { Feature_InMicroMips|Feature_NotMips32r6, 5338 /* jalrs16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
9752 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5351 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
9753 : { Feature_InMicroMips|Feature_NotMips32r6, 5351 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
9754 : { Feature_HasStdEnc|Feature_HasMips32r6, 5356 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9755 : { Feature_HasStdEnc|Feature_HasMips32r6, 5356 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
9756 : { Feature_InMicroMips|Feature_HasMips32r6, 5356 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9757 : { Feature_InMicroMips|Feature_HasMips32r6, 5356 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
9758 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5356 /* jialc */, MCK_GPR64AsmReg, 1 /* 0 */ },
9759 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5356 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
9760 : { Feature_HasStdEnc|Feature_HasMips32r6, 5362 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
9761 : { Feature_HasStdEnc|Feature_HasMips32r6, 5362 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
9762 : { Feature_InMicroMips|Feature_HasMips32r6, 5362 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
9763 : { Feature_InMicroMips|Feature_HasMips32r6, 5362 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
9764 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5362 /* jic */, MCK_GPR64AsmReg, 1 /* 0 */ },
9765 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5362 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
9766 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5366 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9767 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5366 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9768 : { Feature_InMicroMips|Feature_NotMips32r6, 5366 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9769 : { Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, 5366 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ },
9770 : { Feature_HasStdEnc|Feature_HasMips64r6, 5366 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ },
9771 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, 5369 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
9772 : { Feature_HasStdEnc|Feature_HasMips32r6, 5369 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
9773 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5369 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
9774 : { Feature_HasStdEnc|Feature_HasMips32r6, 5369 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
9775 : { Feature_InMicroMips|Feature_NotMips32r6, 5375 /* jr16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
9776 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, 5390 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9777 : { Feature_InMicroMips|Feature_NotMips32r6, 5390 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9778 : { Feature_HasStdEnc|Feature_HasMips64r6, 5390 /* jrc */, MCK_GPR64AsmReg, 1 /* 0 */ },
9779 : { Feature_InMicroMips|Feature_HasMips32r6, 5394 /* jrc16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
9780 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5411 /* l.d */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9781 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5411 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9782 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5411 /* l.d */, MCK_FGR64AsmReg, 1 /* 0 */ },
9783 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5411 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9784 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5415 /* l.s */, MCK_FGR32AsmReg, 1 /* 0 */ },
9785 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5415 /* l.s */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9786 : { 0, 5419 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
9787 : { 0, 5419 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
9788 : { 0, 5419 /* la */, MCK_Mem, 2 /* 1 */ },
9789 : { Feature_HasStdEnc|Feature_HasMips32r6, 5422 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9790 : { Feature_InMicroMips|Feature_HasMips32r6, 5422 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9791 : { Feature_InMicroMips|Feature_HasMips32r6, 5427 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
9792 : { Feature_InMicroMips|Feature_HasMips32r6, 5427 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9793 : { Feature_InMicroMips, 5427 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
9794 : { Feature_InMicroMips, 5427 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9795 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5427 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
9796 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5427 /* lb */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9797 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5430 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9798 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5430 /* lbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9799 : { Feature_InMicroMips|Feature_HasEVA, 5430 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9800 : { Feature_InMicroMips|Feature_HasEVA, 5430 /* lbe */, MCK_Mem, 2 /* 1 */ },
9801 : { Feature_InMicroMips|Feature_HasMips32r6, 5434 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
9802 : { Feature_InMicroMips|Feature_HasMips32r6, 5434 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9803 : { Feature_InMicroMips, 5434 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
9804 : { Feature_InMicroMips, 5434 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9805 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5434 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
9806 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5434 /* lbu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9807 : { Feature_InMicroMips, 5438 /* lbu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
9808 : { Feature_InMicroMips, 5438 /* lbu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
9809 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5444 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
9810 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5444 /* lbue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9811 : { Feature_InMicroMips|Feature_HasEVA, 5444 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
9812 : { Feature_InMicroMips|Feature_HasEVA, 5444 /* lbue */, MCK_Mem, 2 /* 1 */ },
9813 : { Feature_InMicroMips|Feature_HasDSP, 5449 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
9814 : { Feature_HasDSP, 5449 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
9815 : { Feature_HasStdEnc|Feature_NotMips3, 5454 /* ld */, MCK_GPR32AsmReg, 1 /* 0 */ },
9816 : { Feature_HasStdEnc|Feature_NotMips3, 5454 /* ld */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9817 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5454 /* ld */, MCK_GPR64AsmReg, 1 /* 0 */ },
9818 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5454 /* ld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9819 : { Feature_HasStdEnc|Feature_HasMSA, 5457 /* ld.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
9820 : { Feature_HasStdEnc|Feature_HasMSA, 5457 /* ld.b */, MCK_MemOffsetSimm10, 2 /* 1 */ },
9821 : { Feature_HasStdEnc|Feature_HasMSA, 5462 /* ld.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
9822 : { Feature_HasStdEnc|Feature_HasMSA, 5462 /* ld.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ },
9823 : { Feature_HasStdEnc|Feature_HasMSA, 5467 /* ld.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
9824 : { Feature_HasStdEnc|Feature_HasMSA, 5467 /* ld.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ },
9825 : { Feature_HasStdEnc|Feature_HasMSA, 5472 /* ld.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
9826 : { Feature_HasStdEnc|Feature_HasMSA, 5472 /* ld.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ },
9827 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5477 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9828 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5477 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9829 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5477 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9830 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5477 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9831 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5477 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
9832 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5477 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9833 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5477 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
9834 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5477 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9835 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5482 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
9836 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5482 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
9837 : { Feature_InMicroMips|Feature_HasMips32r6, 5482 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
9838 : { Feature_InMicroMips|Feature_HasMips32r6, 5482 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
9839 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5482 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
9840 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5482 /* ldc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9841 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5487 /* ldc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
9842 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5487 /* ldc3 */, MCK_Mem, 2 /* 1 */ },
9843 : { Feature_HasStdEnc|Feature_HasMSA, 5492 /* ldi.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
9844 : { Feature_HasStdEnc|Feature_HasMSA, 5498 /* ldi.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
9845 : { Feature_HasStdEnc|Feature_HasMSA, 5504 /* ldi.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
9846 : { Feature_HasStdEnc|Feature_HasMSA, 5510 /* ldi.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
9847 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5516 /* ldl */, MCK_GPR64AsmReg, 1 /* 0 */ },
9848 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5516 /* ldl */, MCK_Mem, 2 /* 1 */ },
9849 : { Feature_HasStdEnc|Feature_HasMips64r6, 5520 /* ldpc */, MCK_GPR64AsmReg, 1 /* 0 */ },
9850 : { Feature_HasStdEnc|Feature_HasMips64r6, 5520 /* ldpc */, MCK_JumpTarget, 2 /* 1 */ },
9851 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5525 /* ldr */, MCK_GPR64AsmReg, 1 /* 0 */ },
9852 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5525 /* ldr */, MCK_Mem, 2 /* 1 */ },
9853 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5529 /* ldxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9854 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5529 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
9855 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5529 /* ldxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
9856 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5529 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
9857 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5535 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
9858 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5535 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9859 : { Feature_InMicroMips, 5535 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
9860 : { Feature_InMicroMips, 5535 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9861 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5538 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9862 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5538 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9863 : { Feature_InMicroMips|Feature_HasEVA, 5538 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9864 : { Feature_InMicroMips|Feature_HasEVA, 5538 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9865 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5542 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
9866 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5542 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9867 : { Feature_InMicroMips, 5542 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
9868 : { Feature_InMicroMips, 5542 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9869 : { Feature_InMicroMips, 5546 /* lhu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
9870 : { Feature_InMicroMips, 5546 /* lhu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
9871 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5552 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
9872 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5552 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9873 : { Feature_InMicroMips|Feature_HasEVA, 5552 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
9874 : { Feature_InMicroMips|Feature_HasEVA, 5552 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9875 : { Feature_InMicroMips|Feature_HasDSP, 5557 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
9876 : { Feature_HasDSP, 5557 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
9877 : { 0, 5561 /* li */, MCK_GPR32AsmReg, 1 /* 0 */ },
9878 : { 0, 5564 /* li.d */, MCK_GPR32AsmReg, 1 /* 0 */ },
9879 : { Feature_NotFP64bit|Feature_IsNotSoftFloat, 5564 /* li.d */, MCK_StrictlyAFGR64AsmReg, 1 /* 0 */ },
9880 : { Feature_IsFP64bit|Feature_IsNotSoftFloat, 5564 /* li.d */, MCK_StrictlyFGR64AsmReg, 1 /* 0 */ },
9881 : { 0, 5569 /* li.s */, MCK_GPR32AsmReg, 1 /* 0 */ },
9882 : { Feature_IsNotSoftFloat, 5569 /* li.s */, MCK_StrictlyFGR32AsmReg, 1 /* 0 */ },
9883 : { Feature_InMicroMips|Feature_NotMips32r6, 5574 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
9884 : { Feature_InMicroMips|Feature_HasMips32r6, 5574 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
9885 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
9886 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9887 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
9888 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9889 : { Feature_InMicroMips|Feature_HasMips32r6, 5579 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
9890 : { Feature_InMicroMips|Feature_HasMips32r6, 5579 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9891 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
9892 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_Mem, 2 /* 1 */ },
9893 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
9894 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5579 /* ll */, MCK_Mem, 2 /* 1 */ },
9895 : { Feature_InMicroMips|Feature_NotMips32r6, 5579 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
9896 : { Feature_InMicroMips|Feature_NotMips32r6, 5579 /* ll */, MCK_Mem, 2 /* 1 */ },
9897 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5582 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
9898 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5582 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9899 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5582 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
9900 : { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5582 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
9901 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5586 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
9902 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5586 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9903 : { Feature_InMicroMips|Feature_HasEVA, 5586 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
9904 : { Feature_InMicroMips|Feature_HasEVA, 5586 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9905 : { Feature_HasStdEnc|Feature_HasMSA, 5590 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9906 : { Feature_InMicroMips|Feature_HasMips32r6, 5590 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9907 : { Feature_HasStdEnc|Feature_HasMips32r6, 5590 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
9908 : { Feature_InMicroMips|Feature_HasMips32r6, 5594 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
9909 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5594 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
9910 : { Feature_InMicroMips|Feature_NotMips32r6, 5594 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
9911 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5598 /* luxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
9912 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5598 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
9913 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5598 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
9914 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5598 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
9915 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5598 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
9916 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5598 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
9917 : { Feature_InMicroMips, 5604 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
9918 : { Feature_InMicroMips, 5604 /* lw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
9919 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5604 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
9920 : { Feature_HasStdEnc|Feature_NotInMicroMips, 5604 /* lw */, MCK_Mem, 2 /* 1 */ },
9921 : { Feature_NotInMips16Mode|Feature_HasDSP, 5604 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
9922 : { Feature_NotInMips16Mode|Feature_HasDSP, 5604 /* lw */, MCK_Mem, 2 /* 1 */ },
9923 : { Feature_InMicroMips|Feature_HasDSP, 5604 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
9924 : { Feature_InMicroMips|Feature_HasDSP, 5604 /* lw */, MCK_Mem, 2 /* 1 */ },
9925 : { Feature_InMicroMips|Feature_HasMips32r6, 5604 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
9926 : { Feature_InMicroMips|Feature_HasMips32r6, 5604 /* lw */, MCK_Mem, 2 /* 1 */ },
9927 : { Feature_InMicroMips, 5604 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
9928 : { Feature_InMicroMips, 5604 /* lw */, MCK_Mem, 2 /* 1 */ },
9929 : { Feature_InMicroMips, 5604 /* lw */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
9930 : { Feature_InMicroMips, 5604 /* lw */, MCK_MicroMipsMemGP, 2 /* 1 */ },
9931 : { Feature_InMicroMips, 5607 /* lw16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
9932 : { Feature_InMicroMips, 5607 /* lw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
9933 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5612 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
9934 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5612 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9935 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 5612 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
9936 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 5612 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9937 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5617 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
9938 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5617 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
9939 : { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
9940 : { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
9941 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5617 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
9942 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5617 /* lwc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
9943 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5622 /* lwc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
9944 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5622 /* lwc3 */, MCK_Mem, 2 /* 1 */ },
9945 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5627 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9946 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5627 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9947 : { Feature_InMicroMips|Feature_HasEVA, 5627 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
9948 : { Feature_InMicroMips|Feature_HasEVA, 5627 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9949 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5631 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
9950 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5631 /* lwl */, MCK_Mem, 2 /* 1 */ },
9951 : { Feature_InMicroMips|Feature_NotMips32r6, 5631 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
9952 : { Feature_InMicroMips|Feature_NotMips32r6, 5631 /* lwl */, MCK_Mem, 2 /* 1 */ },
9953 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5635 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
9954 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5635 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9955 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5635 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
9956 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5635 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9957 : { Feature_InMicroMips, 5640 /* lwm */, MCK_Mem, 2 /* 1 */ },
9958 : { Feature_InMicroMips, 5640 /* lwm */, MCK_RegList, 1 /* 0 */ },
9959 : { Feature_InMicroMips|Feature_NotMips32r6, 5644 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
9960 : { Feature_InMicroMips|Feature_NotMips32r6, 5644 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
9961 : { Feature_InMicroMips|Feature_HasMips32r6, 5644 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
9962 : { Feature_InMicroMips|Feature_HasMips32r6, 5644 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
9963 : { Feature_InMicroMips, 5650 /* lwm32 */, MCK_Mem, 2 /* 1 */ },
9964 : { Feature_InMicroMips, 5650 /* lwm32 */, MCK_RegList, 1 /* 0 */ },
9965 : { Feature_InMicroMips, 5656 /* lwp */, MCK_GPR32AsmReg, 1 /* 0 */ },
9966 : { Feature_InMicroMips, 5656 /* lwp */, MCK_MemOffsetSimm12, 2 /* 1 */ },
9967 : { Feature_HasStdEnc|Feature_HasMips32r6, 5660 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9968 : { Feature_InMicroMips|Feature_HasMips32r6, 5660 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9969 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5665 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9970 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5665 /* lwr */, MCK_Mem, 2 /* 1 */ },
9971 : { Feature_InMicroMips|Feature_NotMips32r6, 5665 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
9972 : { Feature_InMicroMips|Feature_NotMips32r6, 5665 /* lwr */, MCK_Mem, 2 /* 1 */ },
9973 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5669 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
9974 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5669 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9975 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5669 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
9976 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5669 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
9977 : { Feature_InMicroMips|Feature_NotMips32r6, 5674 /* lwu */, MCK_GPR32AsmReg, 1 /* 0 */ },
9978 : { Feature_InMicroMips|Feature_NotMips32r6, 5674 /* lwu */, MCK_MemOffsetSimm12, 2 /* 1 */ },
9979 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5674 /* lwu */, MCK_GPR64AsmReg, 1 /* 0 */ },
9980 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5674 /* lwu */, MCK_Mem, 2 /* 1 */ },
9981 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5678 /* lwupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
9982 : { Feature_InMicroMips|Feature_HasDSP, 5684 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
9983 : { Feature_HasDSP, 5684 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
9984 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5688 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
9985 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5688 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
9986 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5688 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
9987 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5688 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
9988 : { Feature_InMicroMips, 5694 /* lwxs */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
9989 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5699 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9990 : { Feature_InMicroMips|Feature_NotMips32r6, 5699 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
9991 : { Feature_InMicroMips|Feature_HasDSP, 5699 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9992 : { Feature_InMicroMips|Feature_HasDSP, 5699 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9993 : { Feature_HasDSP, 5699 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
9994 : { Feature_HasDSP, 5699 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
9995 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5704 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
9996 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5704 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
9997 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5704 /* madd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
9998 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5711 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
9999 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5711 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
10000 : { Feature_HasStdEnc|Feature_HasMSA, 5718 /* madd_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10001 : { Feature_HasStdEnc|Feature_HasMSA, 5727 /* madd_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10002 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5736 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10003 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5736 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10004 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5744 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10005 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5744 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10006 : { Feature_HasStdEnc|Feature_HasMSA, 5752 /* maddr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10007 : { Feature_HasStdEnc|Feature_HasMSA, 5762 /* maddr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10008 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5772 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10009 : { Feature_InMicroMips|Feature_NotMips32r6, 5772 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10010 : { Feature_InMicroMips|Feature_HasDSP, 5772 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10011 : { Feature_InMicroMips|Feature_HasDSP, 5772 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10012 : { Feature_HasDSP, 5772 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10013 : { Feature_HasDSP, 5772 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10014 : { Feature_HasStdEnc|Feature_HasMSA, 5778 /* maddv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10015 : { Feature_HasStdEnc|Feature_HasMSA, 5786 /* maddv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10016 : { Feature_HasStdEnc|Feature_HasMSA, 5794 /* maddv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10017 : { Feature_HasStdEnc|Feature_HasMSA, 5802 /* maddv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10018 : { Feature_InMicroMips|Feature_HasDSP, 5810 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10019 : { Feature_InMicroMips|Feature_HasDSP, 5810 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10020 : { Feature_HasDSP, 5810 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10021 : { Feature_HasDSP, 5810 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10022 : { Feature_InMicroMips|Feature_HasDSP, 5822 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10023 : { Feature_InMicroMips|Feature_HasDSP, 5822 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10024 : { Feature_HasDSP, 5822 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10025 : { Feature_HasDSP, 5822 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10026 : { Feature_InMicroMips|Feature_HasDSP, 5834 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10027 : { Feature_InMicroMips|Feature_HasDSP, 5834 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10028 : { Feature_HasDSP, 5834 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10029 : { Feature_HasDSP, 5834 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10030 : { Feature_InMicroMips|Feature_HasDSP, 5847 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10031 : { Feature_InMicroMips|Feature_HasDSP, 5847 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10032 : { Feature_HasDSP, 5847 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10033 : { Feature_HasDSP, 5847 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10034 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5860 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10035 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5860 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10036 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5866 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10037 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5866 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10038 : { Feature_HasStdEnc|Feature_HasMSA, 5872 /* max_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10039 : { Feature_HasStdEnc|Feature_HasMSA, 5880 /* max_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10040 : { Feature_HasStdEnc|Feature_HasMSA, 5888 /* max_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10041 : { Feature_HasStdEnc|Feature_HasMSA, 5896 /* max_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10042 : { Feature_HasStdEnc|Feature_HasMSA, 5904 /* max_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10043 : { Feature_HasStdEnc|Feature_HasMSA, 5912 /* max_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10044 : { Feature_HasStdEnc|Feature_HasMSA, 5920 /* max_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10045 : { Feature_HasStdEnc|Feature_HasMSA, 5928 /* max_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10046 : { Feature_HasStdEnc|Feature_HasMSA, 5936 /* max_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10047 : { Feature_HasStdEnc|Feature_HasMSA, 5944 /* max_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10048 : { Feature_HasStdEnc|Feature_HasMSA, 5952 /* max_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10049 : { Feature_HasStdEnc|Feature_HasMSA, 5960 /* max_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10050 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5968 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10051 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5968 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10052 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5975 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10053 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5975 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10054 : { Feature_HasStdEnc|Feature_HasMSA, 5982 /* maxi_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10055 : { Feature_HasStdEnc|Feature_HasMSA, 5991 /* maxi_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10056 : { Feature_HasStdEnc|Feature_HasMSA, 6000 /* maxi_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10057 : { Feature_HasStdEnc|Feature_HasMSA, 6009 /* maxi_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10058 : { Feature_HasStdEnc|Feature_HasMSA, 6018 /* maxi_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10059 : { Feature_HasStdEnc|Feature_HasMSA, 6027 /* maxi_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10060 : { Feature_HasStdEnc|Feature_HasMSA, 6036 /* maxi_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10061 : { Feature_HasStdEnc|Feature_HasMSA, 6045 /* maxi_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10062 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6054 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10063 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6054 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10064 : { Feature_InMicroMips|Feature_HasMips32r6, 6054 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10065 : { Feature_InMicroMips|Feature_HasMips32r6, 6054 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10066 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6054 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10067 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6054 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10068 : { Feature_InMicroMips|Feature_HasMips32r6, 6054 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10069 : { Feature_InMicroMips|Feature_HasMips32r6, 6054 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10070 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6059 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10071 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6059 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10072 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6059 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10073 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6059 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10074 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 6059 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10075 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 6059 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10076 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6059 /* mfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
10077 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6059 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10078 : { Feature_InMicroMips|Feature_HasMips32r6, 6064 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10079 : { Feature_InMicroMips|Feature_HasMips32r6, 6064 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10080 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6064 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10081 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6064 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10082 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6064 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10083 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6064 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10084 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6069 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10085 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6069 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10086 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6069 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10087 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6069 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10088 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6069 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10089 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6069 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10090 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6069 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10091 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6069 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10092 : { Feature_InMicroMips|Feature_HasMips32r6, 6075 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10093 : { Feature_InMicroMips|Feature_HasMips32r6, 6075 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10094 : { Feature_InMicroMips|Feature_HasMips32r6, 6075 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10095 : { Feature_InMicroMips|Feature_HasMips32r6, 6075 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10096 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6081 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
10097 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6081 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10098 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6081 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
10099 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6081 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10100 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6081 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
10101 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6081 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10102 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6081 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
10103 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6081 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10104 : { Feature_InMicroMips|Feature_HasMips32r6, 6087 /* mfhc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10105 : { Feature_InMicroMips|Feature_HasMips32r6, 6087 /* mfhc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10106 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6093 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10107 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6093 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10108 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6093 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10109 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6093 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10110 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6093 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10111 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6093 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10112 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6093 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10113 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6093 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10114 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6100 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10115 : { Feature_InMicroMips|Feature_NotMips32r6, 6100 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10116 : { Feature_InMicroMips|Feature_HasDSP, 6100 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10117 : { Feature_InMicroMips|Feature_HasDSP, 6100 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10118 : { Feature_HasDSP, 6100 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10119 : { Feature_HasDSP, 6100 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10120 : { Feature_InMicroMips|Feature_NotMips32r6, 6105 /* mfhi16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10121 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6112 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10122 : { Feature_InMicroMips|Feature_NotMips32r6, 6112 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10123 : { Feature_InMicroMips|Feature_HasDSP, 6112 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10124 : { Feature_InMicroMips|Feature_HasDSP, 6112 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10125 : { Feature_HasDSP, 6112 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10126 : { Feature_HasDSP, 6112 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10127 : { Feature_InMicroMips|Feature_NotMips32r6, 6117 /* mflo16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10128 : { Feature_HasMT|Feature_NotInMicroMips, 6124 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
10129 : { Feature_HasMT, 6124 /* mftacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10130 : { Feature_HasMT, 6124 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
10131 : { Feature_HasMT|Feature_NotInMicroMips, 6131 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10132 : { Feature_HasMT|Feature_NotInMicroMips, 6131 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10133 : { Feature_HasMT, 6131 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10134 : { Feature_HasMT, 6131 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10135 : { Feature_HasMT, 6137 /* mftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10136 : { Feature_HasMT, 6137 /* mftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10137 : { Feature_HasMT, 6143 /* mftdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
10138 : { Feature_HasMT, 6150 /* mftgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10139 : { Feature_HasMT, 6157 /* mfthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10140 : { Feature_HasMT, 6157 /* mfthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10141 : { Feature_HasMT|Feature_NotInMicroMips, 6164 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10142 : { Feature_HasMT, 6164 /* mfthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10143 : { Feature_HasMT, 6164 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10144 : { Feature_HasMT|Feature_NotInMicroMips, 6170 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10145 : { Feature_HasMT, 6170 /* mftlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10146 : { Feature_HasMT, 6170 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10147 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6176 /* mftr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10148 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6181 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10149 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6181 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10150 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6187 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10151 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6187 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10152 : { Feature_HasStdEnc|Feature_HasMSA, 6193 /* min_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10153 : { Feature_HasStdEnc|Feature_HasMSA, 6201 /* min_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10154 : { Feature_HasStdEnc|Feature_HasMSA, 6209 /* min_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10155 : { Feature_HasStdEnc|Feature_HasMSA, 6217 /* min_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10156 : { Feature_HasStdEnc|Feature_HasMSA, 6225 /* min_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10157 : { Feature_HasStdEnc|Feature_HasMSA, 6233 /* min_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10158 : { Feature_HasStdEnc|Feature_HasMSA, 6241 /* min_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10159 : { Feature_HasStdEnc|Feature_HasMSA, 6249 /* min_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10160 : { Feature_HasStdEnc|Feature_HasMSA, 6257 /* min_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10161 : { Feature_HasStdEnc|Feature_HasMSA, 6265 /* min_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10162 : { Feature_HasStdEnc|Feature_HasMSA, 6273 /* min_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10163 : { Feature_HasStdEnc|Feature_HasMSA, 6281 /* min_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10164 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6289 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10165 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6289 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10166 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6296 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10167 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6296 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10168 : { Feature_HasStdEnc|Feature_HasMSA, 6303 /* mini_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10169 : { Feature_HasStdEnc|Feature_HasMSA, 6312 /* mini_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10170 : { Feature_HasStdEnc|Feature_HasMSA, 6321 /* mini_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10171 : { Feature_HasStdEnc|Feature_HasMSA, 6330 /* mini_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10172 : { Feature_HasStdEnc|Feature_HasMSA, 6339 /* mini_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10173 : { Feature_HasStdEnc|Feature_HasMSA, 6348 /* mini_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10174 : { Feature_HasStdEnc|Feature_HasMSA, 6357 /* mini_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10175 : { Feature_HasStdEnc|Feature_HasMSA, 6366 /* mini_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10176 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6375 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10177 : { Feature_InMicroMips|Feature_HasMips32r6, 6375 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10178 : { Feature_HasStdEnc|Feature_HasMSA, 6379 /* mod_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10179 : { Feature_HasStdEnc|Feature_HasMSA, 6387 /* mod_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10180 : { Feature_HasStdEnc|Feature_HasMSA, 6395 /* mod_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10181 : { Feature_HasStdEnc|Feature_HasMSA, 6403 /* mod_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10182 : { Feature_HasStdEnc|Feature_HasMSA, 6411 /* mod_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10183 : { Feature_HasStdEnc|Feature_HasMSA, 6419 /* mod_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10184 : { Feature_HasStdEnc|Feature_HasMSA, 6427 /* mod_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10185 : { Feature_HasStdEnc|Feature_HasMSA, 6435 /* mod_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10186 : { Feature_InMicroMips|Feature_HasDSP, 6443 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10187 : { Feature_HasDSP, 6443 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10188 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6450 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10189 : { Feature_InMicroMips|Feature_HasMips32r6, 6450 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10190 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6455 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10191 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6455 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10192 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6455 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10193 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6455 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10194 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6461 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10195 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6461 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10196 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 6461 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10197 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6467 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10198 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6467 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10199 : { Feature_InMicroMips|Feature_NotMips32r6, 6467 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10200 : { Feature_IsGP64bit|Feature_NotInMicroMips, 6467 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10201 : { Feature_IsGP64bit|Feature_NotInMicroMips, 6467 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10202 : { Feature_HasStdEnc|Feature_HasMSA, 6472 /* move.v */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10203 : { Feature_InMicroMips|Feature_HasMips32r6, 6479 /* move16 */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10204 : { Feature_InMicroMips|Feature_NotMips32r6, 6486 /* movep */, MCK_GPRMM16AsmRegMoveP, 12 /* 2, 3 */ },
10205 : { Feature_InMicroMips|Feature_NotMips32r6, 6486 /* movep */, MCK_GPRMM16AsmRegMovePPairFirst, 1 /* 0 */ },
10206 : { Feature_InMicroMips|Feature_NotMips32r6, 6486 /* movep */, MCK_GPRMM16AsmRegMovePPairSecond, 2 /* 1 */ },
10207 : { Feature_InMicroMips|Feature_HasMips32r6, 6486 /* movep */, MCK_GPRMM16AsmRegMoveP, 12 /* 2, 3 */ },
10208 : { Feature_InMicroMips|Feature_HasMips32r6, 6486 /* movep */, MCK_GPRMM16AsmRegMovePPairFirst, 1 /* 0 */ },
10209 : { Feature_InMicroMips|Feature_HasMips32r6, 6486 /* movep */, MCK_GPRMM16AsmRegMovePPairSecond, 2 /* 1 */ },
10210 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6492 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
10211 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6492 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10212 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6492 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
10213 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6492 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10214 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6497 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10215 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6497 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
10216 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6497 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10217 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6497 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
10218 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6497 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
10219 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6497 /* movf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10220 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6504 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ },
10221 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6504 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10222 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6504 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ },
10223 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6504 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10224 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6511 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10225 : { Feature_InMicroMips|Feature_NotMips32r6, 6511 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10226 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6516 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10227 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6516 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
10228 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6516 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10229 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6516 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
10230 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6516 /* movn.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10231 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6516 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
10232 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6523 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10233 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6523 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
10234 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6523 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10235 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6523 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
10236 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6530 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
10237 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6530 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10238 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6530 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
10239 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6530 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10240 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6535 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10241 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6535 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
10242 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6535 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10243 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6535 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
10244 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6535 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
10245 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6535 /* movt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10246 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6542 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ },
10247 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6542 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10248 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6542 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ },
10249 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6542 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10250 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6549 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10251 : { Feature_InMicroMips|Feature_NotMips32r6, 6549 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10252 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6554 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10253 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6554 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
10254 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6554 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10255 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6554 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
10256 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6554 /* movz.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10257 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6554 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
10258 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6561 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10259 : { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6561 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
10260 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6561 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10261 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6561 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
10262 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6568 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10263 : { Feature_InMicroMips|Feature_NotMips32r6, 6568 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10264 : { Feature_InMicroMips|Feature_HasDSP, 6568 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10265 : { Feature_InMicroMips|Feature_HasDSP, 6568 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10266 : { Feature_HasDSP, 6568 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10267 : { Feature_HasDSP, 6568 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10268 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6573 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10269 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6573 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10270 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6573 /* msub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10271 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6580 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
10272 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6580 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
10273 : { Feature_HasStdEnc|Feature_HasMSA, 6587 /* msub_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10274 : { Feature_HasStdEnc|Feature_HasMSA, 6596 /* msub_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10275 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6605 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10276 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6605 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10277 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6613 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10278 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6613 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10279 : { Feature_HasStdEnc|Feature_HasMSA, 6621 /* msubr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10280 : { Feature_HasStdEnc|Feature_HasMSA, 6631 /* msubr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10281 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6641 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10282 : { Feature_InMicroMips|Feature_NotMips32r6, 6641 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10283 : { Feature_InMicroMips|Feature_HasDSP, 6641 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10284 : { Feature_InMicroMips|Feature_HasDSP, 6641 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10285 : { Feature_HasDSP, 6641 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10286 : { Feature_HasDSP, 6641 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10287 : { Feature_HasStdEnc|Feature_HasMSA, 6647 /* msubv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10288 : { Feature_HasStdEnc|Feature_HasMSA, 6655 /* msubv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10289 : { Feature_HasStdEnc|Feature_HasMSA, 6663 /* msubv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10290 : { Feature_HasStdEnc|Feature_HasMSA, 6671 /* msubv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10291 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6679 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10292 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6679 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10293 : { Feature_InMicroMips|Feature_HasMips32r6, 6679 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10294 : { Feature_InMicroMips|Feature_HasMips32r6, 6679 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10295 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6679 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10296 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6679 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10297 : { Feature_InMicroMips|Feature_HasMips32r6, 6679 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10298 : { Feature_InMicroMips|Feature_HasMips32r6, 6679 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10299 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6684 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10300 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6684 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10301 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6684 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10302 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6684 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10303 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 6684 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10304 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 6684 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10305 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6684 /* mtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
10306 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6684 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10307 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6684 /* mtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
10308 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6684 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10309 : { Feature_InMicroMips|Feature_HasMips32r6, 6689 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10310 : { Feature_InMicroMips|Feature_HasMips32r6, 6689 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10311 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6689 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10312 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6689 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10313 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6689 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10314 : { Feature_HasStdEnc|Feature_NotInMicroMips, 6689 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10315 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6694 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10316 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6694 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10317 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6694 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10318 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6694 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10319 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6694 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10320 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6694 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10321 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6694 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10322 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6694 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10323 : { Feature_InMicroMips|Feature_HasMips32r6, 6700 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10324 : { Feature_InMicroMips|Feature_HasMips32r6, 6700 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10325 : { Feature_InMicroMips|Feature_HasMips32r6, 6700 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10326 : { Feature_InMicroMips|Feature_HasMips32r6, 6700 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10327 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6706 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
10328 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6706 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10329 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6706 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
10330 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6706 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10331 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6706 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
10332 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6706 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10333 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6706 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
10334 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6706 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10335 : { Feature_InMicroMips|Feature_HasMips32r6, 6712 /* mthc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
10336 : { Feature_InMicroMips|Feature_HasMips32r6, 6712 /* mthc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10337 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6718 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10338 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6718 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10339 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6718 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10340 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6718 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10341 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6718 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10342 : { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6718 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10343 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6718 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10344 : { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6718 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10345 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6725 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10346 : { Feature_InMicroMips|Feature_NotMips32r6, 6725 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10347 : { Feature_InMicroMips|Feature_HasDSP, 6725 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10348 : { Feature_InMicroMips|Feature_HasDSP, 6725 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
10349 : { Feature_HasDSP, 6725 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10350 : { Feature_HasDSP, 6725 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
10351 : { Feature_InMicroMips|Feature_HasDSP, 6730 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10352 : { Feature_InMicroMips|Feature_HasDSP, 6730 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
10353 : { Feature_HasDSP, 6730 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10354 : { Feature_HasDSP, 6730 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
10355 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6737 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10356 : { Feature_InMicroMips|Feature_NotMips32r6, 6737 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10357 : { Feature_InMicroMips|Feature_HasDSP, 6737 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10358 : { Feature_InMicroMips|Feature_HasDSP, 6737 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
10359 : { Feature_HasDSP, 6737 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10360 : { Feature_HasDSP, 6737 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
10361 : { Feature_HasCnMips, 6742 /* mtm0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
10362 : { Feature_HasCnMips, 6747 /* mtm1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
10363 : { Feature_HasCnMips, 6752 /* mtm2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
10364 : { Feature_HasCnMips, 6757 /* mtp0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
10365 : { Feature_HasCnMips, 6762 /* mtp1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
10366 : { Feature_HasCnMips, 6767 /* mtp2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
10367 : { Feature_HasMT|Feature_NotInMicroMips, 6772 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
10368 : { Feature_HasMT, 6772 /* mttacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10369 : { Feature_HasMT, 6772 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
10370 : { Feature_HasMT|Feature_NotInMicroMips, 6779 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10371 : { Feature_HasMT|Feature_NotInMicroMips, 6779 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10372 : { Feature_HasMT, 6779 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
10373 : { Feature_HasMT, 6779 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10374 : { Feature_HasMT, 6785 /* mttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10375 : { Feature_HasMT, 6785 /* mttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10376 : { Feature_HasMT, 6791 /* mttdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
10377 : { Feature_HasMT, 6798 /* mttgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10378 : { Feature_HasMT, 6805 /* mtthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
10379 : { Feature_HasMT, 6805 /* mtthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
10380 : { Feature_HasMT|Feature_NotInMicroMips, 6812 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10381 : { Feature_HasMT, 6812 /* mtthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10382 : { Feature_HasMT, 6812 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
10383 : { Feature_HasMT|Feature_NotInMicroMips, 6818 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10384 : { Feature_HasMT, 6818 /* mttlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
10385 : { Feature_HasMT, 6818 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
10386 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6824 /* mttr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10387 : { Feature_InMicroMips|Feature_HasMips32r6, 6829 /* muh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10388 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6829 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10389 : { Feature_InMicroMips|Feature_HasMips32r6, 6829 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10390 : { Feature_InMicroMips|Feature_HasMips32r6, 6833 /* muhu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10391 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6833 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10392 : { Feature_InMicroMips|Feature_HasMips32r6, 6833 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10393 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6838 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10394 : { Feature_InMicroMips|Feature_NotMips32r6, 6838 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10395 : { Feature_InMicroMips|Feature_HasMips32r6, 6838 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10396 : { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6838 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10397 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6838 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10398 : { Feature_InMicroMips|Feature_NotMips32r6, 6838 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10399 : { Feature_InMicroMips|Feature_HasMips32r6, 6838 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10400 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6838 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10401 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6842 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
10402 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6842 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
10403 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6842 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10404 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6842 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10405 : { Feature_InMicroMips|Feature_HasDSPR2, 6848 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10406 : { Feature_HasDSPR2, 6848 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10407 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6855 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10408 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6855 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10409 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 6855 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10410 : { Feature_HasStdEnc|Feature_HasMSA, 6861 /* mul_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10411 : { Feature_HasStdEnc|Feature_HasMSA, 6869 /* mul_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10412 : { Feature_InMicroMips|Feature_HasDSPR2, 6877 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10413 : { Feature_HasDSPR2, 6877 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10414 : { Feature_InMicroMips|Feature_HasDSP, 6886 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10415 : { Feature_HasDSP, 6886 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10416 : { Feature_InMicroMips|Feature_HasDSP, 6900 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10417 : { Feature_HasDSP, 6900 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10418 : { Feature_InMicroMips|Feature_HasDSP, 6914 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10419 : { Feature_HasDSP, 6914 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10420 : { Feature_InMicroMips|Feature_HasDSP, 6929 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10421 : { Feature_HasDSP, 6929 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10422 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6944 /* mulo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10423 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6944 /* mulo */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10424 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6949 /* mulou */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10425 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6949 /* mulou */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10426 : { Feature_InMicroMips|Feature_HasDSP, 6955 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10427 : { Feature_HasDSP, 6955 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10428 : { Feature_InMicroMips|Feature_HasDSPR2, 6966 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10429 : { Feature_HasDSPR2, 6966 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10430 : { Feature_InMicroMips|Feature_HasDSPR2, 6976 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10431 : { Feature_HasDSPR2, 6976 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10432 : { Feature_InMicroMips|Feature_HasDSPR2, 6986 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10433 : { Feature_HasDSPR2, 6986 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10434 : { Feature_HasStdEnc|Feature_HasMSA, 6995 /* mulr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10435 : { Feature_HasStdEnc|Feature_HasMSA, 7004 /* mulr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10436 : { Feature_InMicroMips|Feature_HasDSPR2, 7013 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10437 : { Feature_InMicroMips|Feature_HasDSPR2, 7013 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10438 : { Feature_HasDSPR2, 7013 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10439 : { Feature_HasDSPR2, 7013 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10440 : { Feature_InMicroMips|Feature_HasDSP, 7024 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10441 : { Feature_InMicroMips|Feature_HasDSP, 7024 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10442 : { Feature_HasDSP, 7024 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10443 : { Feature_HasDSP, 7024 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10444 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7038 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10445 : { Feature_InMicroMips|Feature_NotMips32r6, 7038 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10446 : { Feature_InMicroMips|Feature_HasDSP, 7038 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10447 : { Feature_InMicroMips|Feature_HasDSP, 7038 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10448 : { Feature_HasDSP, 7038 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10449 : { Feature_HasDSP, 7038 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10450 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7043 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10451 : { Feature_InMicroMips|Feature_NotMips32r6, 7043 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10452 : { Feature_InMicroMips|Feature_HasDSP, 7043 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10453 : { Feature_InMicroMips|Feature_HasDSP, 7043 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10454 : { Feature_HasDSP, 7043 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10455 : { Feature_HasDSP, 7043 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
10456 : { Feature_InMicroMips|Feature_HasMips32r6, 7049 /* mulu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10457 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7049 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10458 : { Feature_InMicroMips|Feature_HasMips32r6, 7049 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10459 : { Feature_HasStdEnc|Feature_HasMSA, 7054 /* mulv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10460 : { Feature_HasStdEnc|Feature_HasMSA, 7061 /* mulv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10461 : { Feature_HasStdEnc|Feature_HasMSA, 7068 /* mulv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10462 : { Feature_HasStdEnc|Feature_HasMSA, 7075 /* mulv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10463 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7082 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
10464 : { Feature_InMicroMips|Feature_NotMips32r6, 7082 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
10465 : { Feature_InMicroMips|Feature_HasMips32r6, 7082 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
10466 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7082 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10467 : { Feature_InMicroMips|Feature_NotMips32r6, 7082 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10468 : { Feature_InMicroMips|Feature_HasMips32r6, 7082 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10469 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7086 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10470 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7086 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10471 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7086 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10472 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7086 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10473 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7092 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10474 : { Feature_HasStdEnc|Feature_IsNotSoftFloat, 7092 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10475 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 7092 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10476 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7098 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
10477 : { Feature_InMicroMips|Feature_NotMips32r6, 7098 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
10478 : { Feature_InMicroMips|Feature_HasMips32r6, 7098 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
10479 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7098 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10480 : { Feature_InMicroMips|Feature_NotMips32r6, 7098 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10481 : { Feature_InMicroMips|Feature_HasMips32r6, 7098 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10482 : { Feature_HasStdEnc|Feature_HasMSA, 7103 /* nloc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10483 : { Feature_HasStdEnc|Feature_HasMSA, 7110 /* nloc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10484 : { Feature_HasStdEnc|Feature_HasMSA, 7117 /* nloc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10485 : { Feature_HasStdEnc|Feature_HasMSA, 7124 /* nloc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10486 : { Feature_HasStdEnc|Feature_HasMSA, 7131 /* nlzc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10487 : { Feature_HasStdEnc|Feature_HasMSA, 7138 /* nlzc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10488 : { Feature_HasStdEnc|Feature_HasMSA, 7145 /* nlzc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10489 : { Feature_HasStdEnc|Feature_HasMSA, 7152 /* nlzc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10490 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7159 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10491 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7159 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10492 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7159 /* nmadd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10493 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7167 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
10494 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7167 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
10495 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7175 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10496 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7175 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10497 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7175 /* nmsub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
10498 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7183 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
10499 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7183 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
10500 : { Feature_IsGP32bit, 7195 /* nor */, MCK_GPR32AsmReg, 1 /* 0 */ },
10501 : { Feature_IsGP64bit, 7195 /* nor */, MCK_GPR64AsmReg, 1 /* 0 */ },
10502 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7195 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10503 : { Feature_InMicroMips|Feature_NotMips32r6, 7195 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10504 : { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10505 : { Feature_IsGP32bit, 7195 /* nor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10506 : { Feature_IsGP64bit, 7195 /* nor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10507 : { Feature_HasStdEnc|Feature_HasMSA, 7199 /* nor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10508 : { Feature_HasStdEnc|Feature_HasMSA, 7205 /* nori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10509 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7212 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
10510 : { Feature_InMicroMips|Feature_NotMips32r6, 7212 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
10511 : { Feature_InMicroMips|Feature_HasMips32r6, 7212 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
10512 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7212 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10513 : { Feature_InMicroMips|Feature_NotMips32r6, 7212 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10514 : { Feature_InMicroMips|Feature_HasMips32r6, 7212 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10515 : { Feature_InMicroMips|Feature_NotMips32r6, 7216 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10516 : { Feature_InMicroMips|Feature_HasMips32r6, 7216 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10517 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7222 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10518 : { Feature_InMicroMips|Feature_NotMips32r6, 7222 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10519 : { Feature_InMicroMips|Feature_HasMips32r6, 7222 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10520 : { Feature_InMicroMips|Feature_HasMips32r6, 7222 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
10521 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7222 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
10522 : { Feature_InMicroMips, 7222 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
10523 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7222 /* or */, MCK_GPR64AsmReg, 1 /* 0 */ },
10524 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7222 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10525 : { Feature_InMicroMips|Feature_NotMips32r6, 7222 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10526 : { Feature_InMicroMips|Feature_HasMips32r6, 7222 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10527 : { Feature_InMicroMips|Feature_HasMips32r6, 7222 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10528 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7222 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10529 : { Feature_InMicroMips, 7222 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10530 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7222 /* or */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10531 : { Feature_HasStdEnc|Feature_HasMSA, 7225 /* or.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10532 : { Feature_InMicroMips|Feature_NotMips32r6, 7230 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10533 : { Feature_InMicroMips|Feature_HasMips32r6, 7230 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10534 : { Feature_InMicroMips|Feature_HasMips32r6, 7235 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
10535 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7235 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
10536 : { Feature_InMicroMips|Feature_NotMips32r6, 7235 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
10537 : { Feature_InMicroMips|Feature_HasMips32r6, 7235 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10538 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7235 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10539 : { Feature_InMicroMips|Feature_NotMips32r6, 7235 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10540 : { Feature_HasStdEnc|Feature_HasMSA, 7239 /* ori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10541 : { Feature_InMicroMips|Feature_HasDSP, 7245 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10542 : { Feature_HasDSP, 7245 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10543 : { Feature_HasStdEnc|Feature_HasMSA, 7261 /* pckev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10544 : { Feature_HasStdEnc|Feature_HasMSA, 7269 /* pckev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10545 : { Feature_HasStdEnc|Feature_HasMSA, 7277 /* pckev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10546 : { Feature_HasStdEnc|Feature_HasMSA, 7285 /* pckev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10547 : { Feature_HasStdEnc|Feature_HasMSA, 7293 /* pckod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10548 : { Feature_HasStdEnc|Feature_HasMSA, 7301 /* pckod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10549 : { Feature_HasStdEnc|Feature_HasMSA, 7309 /* pckod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10550 : { Feature_HasStdEnc|Feature_HasMSA, 7317 /* pckod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10551 : { Feature_HasStdEnc|Feature_HasMSA, 7325 /* pcnt.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10552 : { Feature_HasStdEnc|Feature_HasMSA, 7332 /* pcnt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10553 : { Feature_HasStdEnc|Feature_HasMSA, 7339 /* pcnt.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10554 : { Feature_HasStdEnc|Feature_HasMSA, 7346 /* pcnt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10555 : { Feature_InMicroMips|Feature_HasDSP, 7353 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10556 : { Feature_HasDSP, 7353 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10557 : { Feature_InMicroMips|Feature_HasDSP, 7361 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10558 : { Feature_HasDSP, 7361 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10559 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7369 /* pll.ps */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10560 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7376 /* plu.ps */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10561 : { Feature_HasCnMips, 7383 /* pop */, MCK_GPR32AsmReg, 1 /* 0 */ },
10562 : { Feature_HasCnMips, 7383 /* pop */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10563 : { Feature_InMicroMips|Feature_HasDSP, 7387 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10564 : { Feature_HasDSP, 7387 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10565 : { Feature_InMicroMips|Feature_HasDSP, 7400 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10566 : { Feature_HasDSP, 7400 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10567 : { Feature_InMicroMips|Feature_HasDSP, 7413 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10568 : { Feature_HasDSP, 7413 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10569 : { Feature_InMicroMips|Feature_HasDSP, 7428 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10570 : { Feature_HasDSP, 7428 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10571 : { Feature_InMicroMips|Feature_HasDSP, 7444 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10572 : { Feature_HasDSP, 7444 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10573 : { Feature_InMicroMips|Feature_HasDSP, 7459 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10574 : { Feature_HasDSP, 7459 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10575 : { Feature_InMicroMips|Feature_HasDSP, 7475 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10576 : { Feature_HasDSP, 7475 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10577 : { Feature_InMicroMips|Feature_HasDSP, 7489 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10578 : { Feature_HasDSP, 7489 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10579 : { Feature_InMicroMips|Feature_HasDSP, 7504 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10580 : { Feature_HasDSP, 7504 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10581 : { Feature_InMicroMips|Feature_HasDSP, 7518 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10582 : { Feature_HasDSP, 7518 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10583 : { Feature_InMicroMips|Feature_HasDSPR2, 7533 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10584 : { Feature_HasDSPR2, 7533 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10585 : { Feature_InMicroMips|Feature_HasDSPR2, 7545 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10586 : { Feature_HasDSPR2, 7545 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10587 : { Feature_InMicroMips|Feature_HasDSPR2, 7560 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10588 : { Feature_HasDSPR2, 7560 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10589 : { Feature_InMicroMips|Feature_HasDSP, 7577 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10590 : { Feature_HasDSP, 7577 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10591 : { Feature_InMicroMips|Feature_HasDSP, 7589 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10592 : { Feature_HasDSP, 7589 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10593 : { Feature_InMicroMips|Feature_HasDSP, 7602 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10594 : { Feature_HasDSP, 7602 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10595 : { Feature_InMicroMips|Feature_HasDSP, 7617 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10596 : { Feature_HasDSP, 7617 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10597 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7633 /* pref */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10598 : { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7633 /* pref */, MCK_Mem, 2 /* 1 */ },
10599 : { Feature_InMicroMips|Feature_NotMips32r6, 7633 /* pref */, MCK_Mem, 2 /* 1 */ },
10600 : { Feature_InMicroMips|Feature_HasMips32r6, 7633 /* pref */, MCK_Mem, 2 /* 1 */ },
10601 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7638 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10602 : { Feature_InMicroMips|Feature_HasEVA, 7638 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10603 : { Feature_InMicroMips|Feature_NotMips32r6, 7644 /* prefx */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
10604 : { Feature_InMicroMips|Feature_HasDSPR2, 7650 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10605 : { Feature_HasDSPR2, 7650 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10606 : { Feature_InMicroMips|Feature_HasDSP, 7658 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10607 : { Feature_HasDSP, 7658 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10608 : { Feature_InMicroMips|Feature_HasDSP, 7669 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
10609 : { Feature_HasDSP, 7669 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
10610 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7675 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10611 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7675 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
10612 : { Feature_InMicroMips|Feature_NotMips32r6, 7675 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10613 : { Feature_InMicroMips|Feature_NotMips32r6, 7675 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
10614 : { Feature_InMicroMips|Feature_HasMips32r6, 7675 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10615 : { Feature_InMicroMips|Feature_HasMips32r6, 7675 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
10616 : { Feature_IsGP64bit, 7675 /* rdhwr */, MCK_GPR64AsmReg, 1 /* 0 */ },
10617 : { Feature_IsGP64bit, 7675 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
10618 : { Feature_InMicroMips|Feature_HasMips32r6, 7675 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10619 : { Feature_InMicroMips|Feature_HasMips32r6, 7675 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
10620 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7675 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10621 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7675 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
10622 : { Feature_InMicroMips|Feature_NotMips32r6, 7675 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10623 : { Feature_InMicroMips|Feature_NotMips32r6, 7675 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
10624 : { Feature_InMicroMips|Feature_HasMips32r6, 7681 /* rdpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10625 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7688 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10626 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7688 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10627 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7688 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10628 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7688 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10629 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7696 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10630 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 7696 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10631 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7704 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10632 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7704 /* rem */, MCK_GPR32AsmReg, 1 /* 0 */ },
10633 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7704 /* rem */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10634 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7704 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10635 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7708 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10636 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7708 /* remu */, MCK_GPR32AsmReg, 1 /* 0 */ },
10637 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7708 /* remu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10638 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7708 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10639 : { Feature_InMicroMips|Feature_HasDSP, 7713 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
10640 : { Feature_HasDSP, 7713 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
10641 : { Feature_InMicroMips|Feature_HasDSP, 7721 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
10642 : { Feature_HasDSP, 7721 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
10643 : { Feature_InMicroMips|Feature_HasDSP, 7729 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10644 : { Feature_HasDSP, 7729 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10645 : { Feature_InMicroMips|Feature_HasDSP, 7738 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10646 : { Feature_HasDSP, 7738 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10647 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7747 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10648 : { Feature_InMicroMips|Feature_HasMips32r6, 7747 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10649 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7754 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10650 : { Feature_InMicroMips|Feature_HasMips32r6, 7754 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10651 : { 0, 7761 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10652 : { 0, 7761 /* rol */, MCK_GPR32AsmReg, 1 /* 0 */ },
10653 : { 0, 7761 /* rol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10654 : { 0, 7761 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10655 : { 0, 7765 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10656 : { 0, 7765 /* ror */, MCK_GPR32AsmReg, 1 /* 0 */ },
10657 : { 0, 7765 /* ror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10658 : { 0, 7765 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10659 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7769 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10660 : { Feature_InMicroMips, 7769 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10661 : { Feature_InMicroMips, 7769 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
10662 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7769 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10663 : { Feature_InMicroMips, 7769 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10664 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7774 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10665 : { Feature_InMicroMips, 7774 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10666 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7780 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10667 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7780 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10668 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7790 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
10669 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7790 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
10670 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7790 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
10671 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7790 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
10672 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7800 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
10673 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7800 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
10674 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7800 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
10675 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7800 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
10676 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7800 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
10677 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7800 /* round.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
10678 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7800 /* round.w.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10679 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7810 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10680 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7810 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10681 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 7810 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10682 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7820 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10683 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7820 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10684 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7820 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10685 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7820 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10686 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7828 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10687 : { Feature_NotInMips16Mode|Feature_IsNotSoftFloat, 7828 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10688 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7836 /* s.d */, MCK_AFGR64AsmReg, 1 /* 0 */ },
10689 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7836 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10690 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7836 /* s.d */, MCK_FGR64AsmReg, 1 /* 0 */ },
10691 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7836 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10692 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7840 /* s.s */, MCK_FGR32AsmReg, 1 /* 0 */ },
10693 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7840 /* s.s */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10694 : { Feature_HasStdEnc|Feature_HasMSA, 7844 /* sat_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10695 : { Feature_HasStdEnc|Feature_HasMSA, 7852 /* sat_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10696 : { Feature_HasStdEnc|Feature_HasMSA, 7860 /* sat_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10697 : { Feature_HasStdEnc|Feature_HasMSA, 7868 /* sat_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10698 : { Feature_HasStdEnc|Feature_HasMSA, 7876 /* sat_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10699 : { Feature_HasStdEnc|Feature_HasMSA, 7884 /* sat_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10700 : { Feature_HasStdEnc|Feature_HasMSA, 7892 /* sat_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10701 : { Feature_HasStdEnc|Feature_HasMSA, 7900 /* sat_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10702 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7908 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
10703 : { Feature_HasStdEnc|Feature_NotInMicroMips, 7908 /* sb */, MCK_Mem, 2 /* 1 */ },
10704 : { Feature_InMicroMips|Feature_HasMips32r6, 7908 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
10705 : { Feature_InMicroMips|Feature_HasMips32r6, 7908 /* sb */, MCK_Mem, 2 /* 1 */ },
10706 : { Feature_InMicroMips, 7908 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
10707 : { Feature_InMicroMips, 7908 /* sb */, MCK_Mem, 2 /* 1 */ },
10708 : { Feature_InMicroMips|Feature_NotMips32r6, 7911 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
10709 : { Feature_InMicroMips|Feature_NotMips32r6, 7911 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
10710 : { Feature_InMicroMips|Feature_HasMips32r6, 7911 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
10711 : { Feature_InMicroMips|Feature_HasMips32r6, 7911 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
10712 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7916 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
10713 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7916 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10714 : { Feature_InMicroMips|Feature_HasEVA, 7916 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
10715 : { Feature_InMicroMips|Feature_HasEVA, 7916 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10716 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
10717 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10718 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
10719 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10720 : { Feature_InMicroMips|Feature_HasMips32r6, 7920 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
10721 : { Feature_InMicroMips|Feature_HasMips32r6, 7920 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10722 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
10723 : { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_Mem, 2 /* 1 */ },
10724 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
10725 : { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7920 /* sc */, MCK_Mem, 2 /* 1 */ },
10726 : { Feature_InMicroMips|Feature_NotMips32r6, 7920 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
10727 : { Feature_InMicroMips|Feature_NotMips32r6, 7920 /* sc */, MCK_Mem, 2 /* 1 */ },
10728 : { Feature_HasStdEnc|Feature_HasMips32r6, 7923 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
10729 : { Feature_HasStdEnc|Feature_HasMips32r6, 7923 /* scd */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10730 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7923 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
10731 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7923 /* scd */, MCK_Mem, 2 /* 1 */ },
10732 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7927 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
10733 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7927 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10734 : { Feature_InMicroMips|Feature_HasEVA, 7927 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
10735 : { Feature_InMicroMips|Feature_HasEVA, 7927 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10736 : { Feature_HasStdEnc|Feature_NotMips3, 7931 /* sd */, MCK_GPR32AsmReg, 1 /* 0 */ },
10737 : { Feature_HasStdEnc|Feature_NotMips3, 7931 /* sd */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10738 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7931 /* sd */, MCK_GPR64AsmReg, 1 /* 0 */ },
10739 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7931 /* sd */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
10740 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7948 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
10741 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7948 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10742 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7948 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
10743 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7948 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10744 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7948 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
10745 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7948 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10746 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7948 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
10747 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7948 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10748 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7953 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
10749 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7953 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
10750 : { Feature_InMicroMips|Feature_HasMips32r6, 7953 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
10751 : { Feature_InMicroMips|Feature_HasMips32r6, 7953 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
10752 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7953 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
10753 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7953 /* sdc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
10754 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7958 /* sdc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
10755 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7958 /* sdc3 */, MCK_Mem, 2 /* 1 */ },
10756 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7963 /* sdl */, MCK_GPR64AsmReg, 1 /* 0 */ },
10757 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7963 /* sdl */, MCK_Mem, 2 /* 1 */ },
10758 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7967 /* sdr */, MCK_GPR64AsmReg, 1 /* 0 */ },
10759 : { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7967 /* sdr */, MCK_Mem, 2 /* 1 */ },
10760 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7971 /* sdxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
10761 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7971 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
10762 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7971 /* sdxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
10763 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7971 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
10764 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7977 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ },
10765 : { Feature_InMicroMips, 7977 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ },
10766 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7977 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10767 : { Feature_InMicroMips, 7977 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10768 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7981 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ },
10769 : { Feature_InMicroMips, 7981 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ },
10770 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7981 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10771 : { Feature_InMicroMips, 7981 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10772 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7985 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10773 : { Feature_InMicroMips|Feature_HasMips32r6, 7985 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10774 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7991 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10775 : { Feature_InMicroMips|Feature_HasMips32r6, 7991 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10776 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7997 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10777 : { Feature_InMicroMips|Feature_HasMips32r6, 7997 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10778 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7997 /* seleqz */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
10779 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8004 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10780 : { Feature_InMicroMips|Feature_HasMips32r6, 8004 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10781 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8013 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10782 : { Feature_InMicroMips|Feature_HasMips32r6, 8013 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10783 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 8022 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10784 : { Feature_InMicroMips|Feature_HasMips32r6, 8022 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10785 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 8022 /* selnez */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
10786 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8029 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10787 : { Feature_InMicroMips|Feature_HasMips32r6, 8029 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
10788 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8038 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10789 : { Feature_InMicroMips|Feature_HasMips32r6, 8038 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
10790 : { Feature_NotCnMips, 8047 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10791 : { Feature_NotCnMips, 8047 /* seq */, MCK_GPR32AsmReg, 1 /* 0 */ },
10792 : { Feature_HasCnMips, 8047 /* seq */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10793 : { Feature_NotCnMips, 8047 /* seq */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10794 : { Feature_NotCnMips, 8047 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10795 : { Feature_HasCnMips, 8047 /* seq */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
10796 : { Feature_HasCnMips, 8051 /* seqi */, MCK_GPR64AsmReg, 1 /* 0 */ },
10797 : { Feature_HasCnMips, 8051 /* seqi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10798 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8056 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10799 : { Feature_InMicroMips, 8056 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10800 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8056 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10801 : { Feature_InMicroMips, 8056 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10802 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8060 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10803 : { Feature_InMicroMips, 8060 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10804 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8060 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10805 : { Feature_InMicroMips, 8060 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10806 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8065 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
10807 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8065 /* sh */, MCK_Mem, 2 /* 1 */ },
10808 : { Feature_InMicroMips|Feature_HasMips32r6, 8065 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
10809 : { Feature_InMicroMips|Feature_HasMips32r6, 8065 /* sh */, MCK_Mem, 2 /* 1 */ },
10810 : { Feature_InMicroMips, 8065 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
10811 : { Feature_InMicroMips, 8065 /* sh */, MCK_Mem, 2 /* 1 */ },
10812 : { Feature_InMicroMips|Feature_NotMips32r6, 8068 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
10813 : { Feature_InMicroMips|Feature_NotMips32r6, 8068 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
10814 : { Feature_InMicroMips|Feature_HasMips32r6, 8068 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
10815 : { Feature_InMicroMips|Feature_HasMips32r6, 8068 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
10816 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8073 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
10817 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8073 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10818 : { Feature_InMicroMips|Feature_HasEVA, 8073 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
10819 : { Feature_InMicroMips|Feature_HasEVA, 8073 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ },
10820 : { Feature_HasStdEnc|Feature_HasMSA, 8077 /* shf.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10821 : { Feature_HasStdEnc|Feature_HasMSA, 8083 /* shf.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10822 : { Feature_HasStdEnc|Feature_HasMSA, 8089 /* shf.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10823 : { Feature_InMicroMips|Feature_HasDSP, 8095 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10824 : { Feature_HasDSP, 8095 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10825 : { Feature_InMicroMips|Feature_HasDSP, 8101 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10826 : { Feature_InMicroMips|Feature_HasDSP, 8101 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
10827 : { Feature_HasDSP, 8101 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
10828 : { Feature_HasDSP, 8101 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
10829 : { Feature_InMicroMips|Feature_HasDSP, 8108 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10830 : { Feature_HasDSP, 8108 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10831 : { Feature_InMicroMips|Feature_HasDSP, 8116 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10832 : { Feature_HasDSP, 8116 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10833 : { Feature_InMicroMips|Feature_HasDSP, 8124 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10834 : { Feature_HasDSP, 8124 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10835 : { Feature_InMicroMips|Feature_HasDSP, 8134 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10836 : { Feature_HasDSP, 8134 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10837 : { Feature_InMicroMips|Feature_HasDSP, 8143 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10838 : { Feature_HasDSP, 8143 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10839 : { Feature_InMicroMips|Feature_HasDSP, 8152 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10840 : { Feature_HasDSP, 8152 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10841 : { Feature_InMicroMips|Feature_HasDSP, 8161 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10842 : { Feature_HasDSP, 8161 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10843 : { Feature_InMicroMips|Feature_HasDSP, 8172 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10844 : { Feature_HasDSP, 8172 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10845 : { Feature_InMicroMips|Feature_HasDSP, 8182 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10846 : { Feature_HasDSP, 8182 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10847 : { Feature_InMicroMips|Feature_HasDSPR2, 8190 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10848 : { Feature_HasDSPR2, 8190 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10849 : { Feature_InMicroMips|Feature_HasDSP, 8198 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10850 : { Feature_HasDSP, 8198 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10851 : { Feature_InMicroMips|Feature_HasDSPR2, 8208 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10852 : { Feature_HasDSPR2, 8208 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10853 : { Feature_InMicroMips|Feature_HasDSP, 8218 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10854 : { Feature_HasDSP, 8218 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10855 : { Feature_InMicroMips|Feature_HasDSP, 8227 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10856 : { Feature_HasDSP, 8227 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10857 : { Feature_InMicroMips|Feature_HasDSPR2, 8236 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10858 : { Feature_HasDSPR2, 8236 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10859 : { Feature_InMicroMips|Feature_HasDSP, 8245 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10860 : { Feature_HasDSP, 8245 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10861 : { Feature_InMicroMips|Feature_HasDSPR2, 8256 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10862 : { Feature_HasDSPR2, 8256 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10863 : { Feature_InMicroMips|Feature_HasDSP, 8267 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10864 : { Feature_HasDSP, 8267 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10865 : { Feature_InMicroMips|Feature_HasDSPR2, 8277 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10866 : { Feature_HasDSPR2, 8277 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10867 : { Feature_InMicroMips|Feature_HasDSP, 8285 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10868 : { Feature_HasDSP, 8285 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10869 : { Feature_InMicroMips|Feature_HasDSPR2, 8293 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10870 : { Feature_HasDSPR2, 8293 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10871 : { Feature_InMicroMips|Feature_HasDSP, 8302 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10872 : { Feature_HasDSP, 8302 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10873 : { Feature_HasStdEnc|Feature_HasMSA, 8311 /* sld.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
10874 : { Feature_HasStdEnc|Feature_HasMSA, 8311 /* sld.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10875 : { Feature_HasStdEnc|Feature_HasMSA, 8317 /* sld.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
10876 : { Feature_HasStdEnc|Feature_HasMSA, 8317 /* sld.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10877 : { Feature_HasStdEnc|Feature_HasMSA, 8323 /* sld.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
10878 : { Feature_HasStdEnc|Feature_HasMSA, 8323 /* sld.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10879 : { Feature_HasStdEnc|Feature_HasMSA, 8329 /* sld.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
10880 : { Feature_HasStdEnc|Feature_HasMSA, 8329 /* sld.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10881 : { Feature_HasStdEnc|Feature_HasMSA, 8335 /* sldi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10882 : { Feature_HasStdEnc|Feature_HasMSA, 8342 /* sldi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10883 : { Feature_HasStdEnc|Feature_HasMSA, 8349 /* sldi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10884 : { Feature_HasStdEnc|Feature_HasMSA, 8356 /* sldi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10885 : { Feature_NotInMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10886 : { Feature_InMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10887 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
10888 : { Feature_InMicroMips|Feature_HasMips32r6, 8363 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
10889 : { Feature_InMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
10890 : { Feature_InMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
10891 : { Feature_NotInMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10892 : { Feature_InMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10893 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10894 : { Feature_InMicroMips|Feature_HasMips32r6, 8363 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10895 : { Feature_InMicroMips, 8363 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10896 : { Feature_HasStdEnc|Feature_HasMSA, 8367 /* sll.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10897 : { Feature_HasStdEnc|Feature_HasMSA, 8373 /* sll.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10898 : { Feature_HasStdEnc|Feature_HasMSA, 8379 /* sll.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10899 : { Feature_HasStdEnc|Feature_HasMSA, 8385 /* sll.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10900 : { Feature_InMicroMips|Feature_NotMips32r6, 8391 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10901 : { Feature_InMicroMips|Feature_HasMips32r6, 8391 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10902 : { Feature_HasStdEnc|Feature_HasMSA, 8397 /* slli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10903 : { Feature_HasStdEnc|Feature_HasMSA, 8404 /* slli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10904 : { Feature_HasStdEnc|Feature_HasMSA, 8411 /* slli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10905 : { Feature_HasStdEnc|Feature_HasMSA, 8418 /* slli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10906 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8425 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10907 : { Feature_InMicroMips, 8425 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10908 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8430 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ },
10909 : { Feature_InMicroMips, 8430 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ },
10910 : { Feature_IsGP64bit, 8430 /* slt */, MCK_GPR64AsmReg, 1 /* 0 */ },
10911 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8430 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10912 : { Feature_InMicroMips, 8430 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10913 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8430 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10914 : { Feature_InMicroMips, 8430 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10915 : { Feature_IsGP64bit, 8430 /* slt */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10916 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8434 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10917 : { Feature_InMicroMips, 8434 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10918 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8439 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10919 : { Feature_InMicroMips, 8439 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10920 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8445 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
10921 : { Feature_InMicroMips, 8445 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
10922 : { Feature_IsGP64bit, 8445 /* sltu */, MCK_GPR64AsmReg, 1 /* 0 */ },
10923 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8445 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10924 : { Feature_InMicroMips, 8445 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10925 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8445 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10926 : { Feature_InMicroMips, 8445 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10927 : { Feature_IsGP64bit, 8445 /* sltu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10928 : { Feature_HasCnMips, 8450 /* sne */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10929 : { Feature_HasCnMips, 8450 /* sne */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
10930 : { Feature_HasCnMips, 8454 /* snei */, MCK_GPR64AsmReg, 1 /* 0 */ },
10931 : { Feature_HasCnMips, 8454 /* snei */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
10932 : { Feature_HasStdEnc|Feature_HasMSA, 8459 /* splat.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
10933 : { Feature_HasStdEnc|Feature_HasMSA, 8459 /* splat.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10934 : { Feature_HasStdEnc|Feature_HasMSA, 8467 /* splat.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
10935 : { Feature_HasStdEnc|Feature_HasMSA, 8467 /* splat.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10936 : { Feature_HasStdEnc|Feature_HasMSA, 8475 /* splat.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
10937 : { Feature_HasStdEnc|Feature_HasMSA, 8475 /* splat.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10938 : { Feature_HasStdEnc|Feature_HasMSA, 8483 /* splat.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
10939 : { Feature_HasStdEnc|Feature_HasMSA, 8483 /* splat.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10940 : { Feature_HasStdEnc|Feature_HasMSA, 8491 /* splati.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10941 : { Feature_HasStdEnc|Feature_HasMSA, 8500 /* splati.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10942 : { Feature_HasStdEnc|Feature_HasMSA, 8509 /* splati.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10943 : { Feature_HasStdEnc|Feature_HasMSA, 8518 /* splati.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10944 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8527 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10945 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8527 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
10946 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8527 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10947 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8527 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
10948 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8534 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10949 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 8534 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
10950 : { Feature_NotInMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10951 : { Feature_InMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10952 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
10953 : { Feature_InMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
10954 : { Feature_InMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
10955 : { Feature_NotInMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10956 : { Feature_InMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10957 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10958 : { Feature_InMicroMips, 8541 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10959 : { Feature_HasStdEnc|Feature_HasMSA, 8545 /* sra.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10960 : { Feature_HasStdEnc|Feature_HasMSA, 8551 /* sra.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10961 : { Feature_HasStdEnc|Feature_HasMSA, 8557 /* sra.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10962 : { Feature_HasStdEnc|Feature_HasMSA, 8563 /* sra.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10963 : { Feature_HasStdEnc|Feature_HasMSA, 8569 /* srai.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10964 : { Feature_HasStdEnc|Feature_HasMSA, 8576 /* srai.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10965 : { Feature_HasStdEnc|Feature_HasMSA, 8583 /* srai.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10966 : { Feature_HasStdEnc|Feature_HasMSA, 8590 /* srai.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10967 : { Feature_HasStdEnc|Feature_HasMSA, 8597 /* srar.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10968 : { Feature_HasStdEnc|Feature_HasMSA, 8604 /* srar.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10969 : { Feature_HasStdEnc|Feature_HasMSA, 8611 /* srar.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10970 : { Feature_HasStdEnc|Feature_HasMSA, 8618 /* srar.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10971 : { Feature_HasStdEnc|Feature_HasMSA, 8625 /* srari.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10972 : { Feature_HasStdEnc|Feature_HasMSA, 8633 /* srari.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10973 : { Feature_HasStdEnc|Feature_HasMSA, 8641 /* srari.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10974 : { Feature_HasStdEnc|Feature_HasMSA, 8649 /* srari.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10975 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8657 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10976 : { Feature_InMicroMips, 8657 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10977 : { Feature_NotInMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10978 : { Feature_InMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10979 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
10980 : { Feature_InMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
10981 : { Feature_InMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
10982 : { Feature_NotInMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10983 : { Feature_InMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
10984 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10985 : { Feature_InMicroMips, 8662 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
10986 : { Feature_HasStdEnc|Feature_HasMSA, 8666 /* srl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10987 : { Feature_HasStdEnc|Feature_HasMSA, 8672 /* srl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10988 : { Feature_HasStdEnc|Feature_HasMSA, 8678 /* srl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10989 : { Feature_HasStdEnc|Feature_HasMSA, 8684 /* srl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10990 : { Feature_InMicroMips|Feature_NotMips32r6, 8690 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10991 : { Feature_InMicroMips|Feature_HasMips32r6, 8690 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
10992 : { Feature_HasStdEnc|Feature_HasMSA, 8696 /* srli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10993 : { Feature_HasStdEnc|Feature_HasMSA, 8703 /* srli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10994 : { Feature_HasStdEnc|Feature_HasMSA, 8710 /* srli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10995 : { Feature_HasStdEnc|Feature_HasMSA, 8717 /* srli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
10996 : { Feature_HasStdEnc|Feature_HasMSA, 8724 /* srlr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10997 : { Feature_HasStdEnc|Feature_HasMSA, 8731 /* srlr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10998 : { Feature_HasStdEnc|Feature_HasMSA, 8738 /* srlr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
10999 : { Feature_HasStdEnc|Feature_HasMSA, 8745 /* srlr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11000 : { Feature_HasStdEnc|Feature_HasMSA, 8752 /* srlri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11001 : { Feature_HasStdEnc|Feature_HasMSA, 8760 /* srlri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11002 : { Feature_HasStdEnc|Feature_HasMSA, 8768 /* srlri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11003 : { Feature_HasStdEnc|Feature_HasMSA, 8776 /* srlri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11004 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8784 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11005 : { Feature_InMicroMips, 8784 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11006 : { Feature_HasStdEnc|Feature_HasMSA, 8795 /* st.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
11007 : { Feature_HasStdEnc|Feature_HasMSA, 8795 /* st.b */, MCK_MemOffsetSimm10, 2 /* 1 */ },
11008 : { Feature_HasStdEnc|Feature_HasMSA, 8800 /* st.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
11009 : { Feature_HasStdEnc|Feature_HasMSA, 8800 /* st.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ },
11010 : { Feature_HasStdEnc|Feature_HasMSA, 8805 /* st.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
11011 : { Feature_HasStdEnc|Feature_HasMSA, 8805 /* st.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ },
11012 : { Feature_HasStdEnc|Feature_HasMSA, 8810 /* st.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
11013 : { Feature_HasStdEnc|Feature_HasMSA, 8810 /* st.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ },
11014 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8815 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11015 : { Feature_InMicroMips|Feature_NotMips32r6, 8815 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11016 : { Feature_InMicroMips|Feature_HasMips32r6, 8815 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11017 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8815 /* sub */, MCK_GPR32AsmReg, 1 /* 0 */ },
11018 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8815 /* sub */, MCK_InvNum, 2 /* 1 */ },
11019 : { Feature_HasStdEnc|Feature_NotInMicroMips, 8815 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11020 : { Feature_InMicroMips|Feature_NotMips32r6, 8815 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11021 : { Feature_InMicroMips|Feature_HasMips32r6, 8815 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11022 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8815 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11023 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8815 /* sub */, MCK_InvNum, 4 /* 2 */ },
11024 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8819 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
11025 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8819 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
11026 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8819 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
11027 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8819 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
11028 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8825 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
11029 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 8825 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
11030 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 8825 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
11031 : { Feature_InMicroMips|Feature_HasDSP, 8831 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11032 : { Feature_HasDSP, 8831 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11033 : { Feature_InMicroMips|Feature_HasDSP, 8839 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11034 : { Feature_HasDSP, 8839 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11035 : { Feature_InMicroMips|Feature_HasDSP, 8849 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11036 : { Feature_HasDSP, 8849 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11037 : { Feature_InMicroMips|Feature_HasDSPR2, 8858 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11038 : { Feature_HasDSPR2, 8858 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11039 : { Feature_InMicroMips|Feature_HasDSPR2, 8867 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11040 : { Feature_HasDSPR2, 8867 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11041 : { Feature_InMicroMips|Feature_HasDSPR2, 8875 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11042 : { Feature_HasDSPR2, 8875 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11043 : { Feature_InMicroMips|Feature_HasDSPR2, 8886 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11044 : { Feature_HasDSPR2, 8886 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11045 : { Feature_HasStdEnc|Feature_HasMSA, 8896 /* subs_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11046 : { Feature_HasStdEnc|Feature_HasMSA, 8905 /* subs_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11047 : { Feature_HasStdEnc|Feature_HasMSA, 8914 /* subs_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11048 : { Feature_HasStdEnc|Feature_HasMSA, 8923 /* subs_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11049 : { Feature_HasStdEnc|Feature_HasMSA, 8932 /* subs_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11050 : { Feature_HasStdEnc|Feature_HasMSA, 8941 /* subs_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11051 : { Feature_HasStdEnc|Feature_HasMSA, 8950 /* subs_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11052 : { Feature_HasStdEnc|Feature_HasMSA, 8959 /* subs_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11053 : { Feature_HasStdEnc|Feature_HasMSA, 8968 /* subsus_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11054 : { Feature_HasStdEnc|Feature_HasMSA, 8979 /* subsus_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11055 : { Feature_HasStdEnc|Feature_HasMSA, 8990 /* subsus_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11056 : { Feature_HasStdEnc|Feature_HasMSA, 9001 /* subsus_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11057 : { Feature_HasStdEnc|Feature_HasMSA, 9012 /* subsuu_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11058 : { Feature_HasStdEnc|Feature_HasMSA, 9023 /* subsuu_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11059 : { Feature_HasStdEnc|Feature_HasMSA, 9034 /* subsuu_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11060 : { Feature_HasStdEnc|Feature_HasMSA, 9045 /* subsuu_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11061 : { Feature_InMicroMips|Feature_HasMips32r6, 9056 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11062 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9056 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11063 : { Feature_InMicroMips|Feature_NotMips32r6, 9056 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11064 : { 0, 9056 /* subu */, MCK_GPR32AsmReg, 1 /* 0 */ },
11065 : { 0, 9056 /* subu */, MCK_InvNum, 2 /* 1 */ },
11066 : { Feature_InMicroMips|Feature_HasMips32r6, 9056 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11067 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9056 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11068 : { Feature_InMicroMips|Feature_NotMips32r6, 9056 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11069 : { 0, 9056 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11070 : { 0, 9056 /* subu */, MCK_InvNum, 4 /* 2 */ },
11071 : { Feature_InMicroMips|Feature_HasDSPR2, 9061 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11072 : { Feature_HasDSPR2, 9061 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11073 : { Feature_InMicroMips|Feature_HasDSP, 9069 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11074 : { Feature_HasDSP, 9069 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11075 : { Feature_InMicroMips|Feature_NotMips32r6, 9077 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
11076 : { Feature_InMicroMips|Feature_HasMips32r6, 9077 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
11077 : { Feature_InMicroMips|Feature_HasDSPR2, 9084 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11078 : { Feature_HasDSPR2, 9084 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11079 : { Feature_InMicroMips|Feature_HasDSP, 9094 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11080 : { Feature_HasDSP, 9094 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11081 : { Feature_InMicroMips|Feature_HasDSPR2, 9104 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11082 : { Feature_HasDSPR2, 9104 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11083 : { Feature_InMicroMips|Feature_HasDSPR2, 9113 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11084 : { Feature_HasDSPR2, 9113 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11085 : { Feature_HasStdEnc|Feature_HasMSA, 9124 /* subv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11086 : { Feature_HasStdEnc|Feature_HasMSA, 9131 /* subv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11087 : { Feature_HasStdEnc|Feature_HasMSA, 9138 /* subv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11088 : { Feature_HasStdEnc|Feature_HasMSA, 9145 /* subv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11089 : { Feature_HasStdEnc|Feature_HasMSA, 9152 /* subvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11090 : { Feature_HasStdEnc|Feature_HasMSA, 9160 /* subvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11091 : { Feature_HasStdEnc|Feature_HasMSA, 9168 /* subvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11092 : { Feature_HasStdEnc|Feature_HasMSA, 9176 /* subvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11093 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9184 /* suxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
11094 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9184 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
11095 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9184 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
11096 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9184 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
11097 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9184 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
11098 : { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9184 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
11099 : { Feature_InMicroMips|Feature_NotMips32r6, 9190 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11100 : { Feature_InMicroMips|Feature_NotMips32r6, 9190 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
11101 : { Feature_InMicroMips|Feature_HasMips32r6, 9190 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11102 : { Feature_InMicroMips|Feature_HasMips32r6, 9190 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
11103 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9190 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11104 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9190 /* sw */, MCK_Mem, 2 /* 1 */ },
11105 : { Feature_NotInMips16Mode|Feature_HasDSP, 9190 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11106 : { Feature_NotInMips16Mode|Feature_HasDSP, 9190 /* sw */, MCK_Mem, 2 /* 1 */ },
11107 : { Feature_InMicroMips|Feature_HasDSP, 9190 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11108 : { Feature_InMicroMips|Feature_HasDSP, 9190 /* sw */, MCK_Mem, 2 /* 1 */ },
11109 : { Feature_InMicroMips|Feature_HasMips32r6, 9190 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11110 : { Feature_InMicroMips|Feature_HasMips32r6, 9190 /* sw */, MCK_Mem, 2 /* 1 */ },
11111 : { Feature_InMicroMips, 9190 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11112 : { Feature_InMicroMips, 9190 /* sw */, MCK_Mem, 2 /* 1 */ },
11113 : { Feature_InMicroMips|Feature_NotMips32r6, 9193 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
11114 : { Feature_InMicroMips|Feature_NotMips32r6, 9193 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
11115 : { Feature_InMicroMips|Feature_HasMips32r6, 9193 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
11116 : { Feature_InMicroMips|Feature_HasMips32r6, 9193 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
11117 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9198 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
11118 : { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9198 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
11119 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 9198 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
11120 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 9198 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
11121 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9203 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
11122 : { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9203 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
11123 : { Feature_InMicroMips|Feature_HasMips32r6, 9203 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
11124 : { Feature_InMicroMips|Feature_HasMips32r6, 9203 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
11125 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9203 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
11126 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9203 /* swc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
11127 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9208 /* swc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
11128 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9208 /* swc3 */, MCK_Mem, 2 /* 1 */ },
11129 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9213 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
11130 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9213 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
11131 : { Feature_InMicroMips|Feature_HasEVA, 9213 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
11132 : { Feature_InMicroMips|Feature_HasEVA, 9213 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
11133 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9217 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
11134 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9217 /* swl */, MCK_Mem, 2 /* 1 */ },
11135 : { Feature_InMicroMips|Feature_NotMips32r6, 9217 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
11136 : { Feature_InMicroMips|Feature_NotMips32r6, 9217 /* swl */, MCK_Mem, 2 /* 1 */ },
11137 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9221 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
11138 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9221 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
11139 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9221 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
11140 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9221 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
11141 : { Feature_InMicroMips, 9226 /* swm */, MCK_Mem, 2 /* 1 */ },
11142 : { Feature_InMicroMips, 9226 /* swm */, MCK_RegList, 1 /* 0 */ },
11143 : { Feature_InMicroMips|Feature_NotMips32r6, 9230 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
11144 : { Feature_InMicroMips|Feature_NotMips32r6, 9230 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
11145 : { Feature_InMicroMips|Feature_HasMips32r6, 9230 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
11146 : { Feature_InMicroMips|Feature_HasMips32r6, 9230 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
11147 : { Feature_InMicroMips, 9236 /* swm32 */, MCK_Mem, 2 /* 1 */ },
11148 : { Feature_InMicroMips, 9236 /* swm32 */, MCK_RegList, 1 /* 0 */ },
11149 : { Feature_InMicroMips, 9242 /* swp */, MCK_GPR32AsmReg, 1 /* 0 */ },
11150 : { Feature_InMicroMips, 9242 /* swp */, MCK_MemOffsetSimm12, 2 /* 1 */ },
11151 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9246 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
11152 : { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9246 /* swr */, MCK_Mem, 2 /* 1 */ },
11153 : { Feature_InMicroMips|Feature_NotMips32r6, 9246 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
11154 : { Feature_InMicroMips|Feature_NotMips32r6, 9246 /* swr */, MCK_Mem, 2 /* 1 */ },
11155 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9250 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
11156 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9250 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
11157 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9250 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
11158 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9250 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
11159 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9255 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
11160 : { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9255 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
11161 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9255 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
11162 : { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9255 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
11163 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9266 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
11164 : { Feature_InMicroMips|Feature_NotMips32r6, 9266 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
11165 : { Feature_InMicroMips|Feature_HasMips32r6, 9266 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
11166 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9310 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11167 : { Feature_InMicroMips, 9310 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11168 : { Feature_InMicroMips, 9310 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11169 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9310 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11170 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9314 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
11171 : { Feature_InMicroMips|Feature_NotMips32r6, 9314 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
11172 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9319 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11173 : { Feature_InMicroMips, 9319 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11174 : { Feature_InMicroMips, 9319 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11175 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9319 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11176 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9323 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
11177 : { Feature_InMicroMips|Feature_NotMips32r6, 9323 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
11178 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9328 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
11179 : { Feature_InMicroMips|Feature_NotMips32r6, 9328 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
11180 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9334 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11181 : { Feature_InMicroMips, 9334 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11182 : { Feature_InMicroMips, 9334 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11183 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9334 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11184 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9419 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11185 : { Feature_InMicroMips, 9419 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11186 : { Feature_InMicroMips, 9419 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11187 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9419 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11188 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9423 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
11189 : { Feature_InMicroMips|Feature_NotMips32r6, 9423 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
11190 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9428 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
11191 : { Feature_InMicroMips|Feature_NotMips32r6, 9428 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
11192 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9434 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11193 : { Feature_InMicroMips, 9434 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11194 : { Feature_InMicroMips, 9434 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11195 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9434 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11196 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9439 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11197 : { Feature_InMicroMips, 9439 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11198 : { Feature_InMicroMips, 9439 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11199 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9439 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11200 : { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9443 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
11201 : { Feature_InMicroMips|Feature_NotMips32r6, 9443 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
11202 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9448 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
11203 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9448 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
11204 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9458 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
11205 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9458 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
11206 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9458 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
11207 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9458 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
11208 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9468 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
11209 : { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9468 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
11210 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
11211 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
11212 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
11213 : { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
11214 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9468 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
11215 : { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9468 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
11216 : { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
11217 : { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
11218 : { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
11219 : { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
11220 : { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
11221 : { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9468 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
11222 : { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9478 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
11223 : { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9478 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
11224 : { Feature_InMicroMips|Feature_IsNotSoftFloat, 9478 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
11225 : { 0, 9478 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
11226 : { 0, 9478 /* trunc.w.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
11227 : { 0, 9488 /* ulh */, MCK_GPR32AsmReg, 1 /* 0 */ },
11228 : { 0, 9488 /* ulh */, MCK_Mem, 2 /* 1 */ },
11229 : { 0, 9492 /* ulhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
11230 : { 0, 9492 /* ulhu */, MCK_Mem, 2 /* 1 */ },
11231 : { 0, 9497 /* ulw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11232 : { 0, 9497 /* ulw */, MCK_Mem, 2 /* 1 */ },
11233 : { 0, 9501 /* ush */, MCK_GPR32AsmReg, 1 /* 0 */ },
11234 : { 0, 9501 /* ush */, MCK_Mem, 2 /* 1 */ },
11235 : { 0, 9505 /* usw */, MCK_GPR32AsmReg, 1 /* 0 */ },
11236 : { 0, 9505 /* usw */, MCK_Mem, 2 /* 1 */ },
11237 : { Feature_HasCnMips, 9509 /* v3mulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
11238 : { Feature_HasCnMips, 9509 /* v3mulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
11239 : { Feature_HasCnMips, 9516 /* vmm0 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
11240 : { Feature_HasCnMips, 9516 /* vmm0 */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
11241 : { Feature_HasCnMips, 9521 /* vmulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
11242 : { Feature_HasCnMips, 9521 /* vmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
11243 : { Feature_HasStdEnc|Feature_HasMSA, 9527 /* vshf.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11244 : { Feature_HasStdEnc|Feature_HasMSA, 9534 /* vshf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11245 : { Feature_HasStdEnc|Feature_HasMSA, 9541 /* vshf.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11246 : { Feature_HasStdEnc|Feature_HasMSA, 9548 /* vshf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11247 : { Feature_HasDSP|Feature_NotInMicroMips, 9560 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
11248 : { Feature_HasDSP|Feature_InMicroMips, 9560 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
11249 : { Feature_InMicroMips|Feature_HasDSP, 9560 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
11250 : { Feature_HasDSP|Feature_NotInMicroMips, 9560 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
11251 : { Feature_InMicroMips|Feature_HasMips32r6, 9566 /* wrpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11252 : { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9573 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11253 : { Feature_InMicroMips|Feature_HasMips32r6, 9573 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11254 : { Feature_InMicroMips, 9573 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11255 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9578 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11256 : { Feature_InMicroMips|Feature_NotMips32r6, 9578 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11257 : { Feature_InMicroMips|Feature_HasMips32r6, 9578 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11258 : { Feature_InMicroMips|Feature_HasMips32r6, 9578 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
11259 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9578 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
11260 : { Feature_InMicroMips, 9578 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
11261 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9578 /* xor */, MCK_GPR64AsmReg, 1 /* 0 */ },
11262 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9578 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11263 : { Feature_InMicroMips|Feature_NotMips32r6, 9578 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11264 : { Feature_InMicroMips|Feature_HasMips32r6, 9578 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
11265 : { Feature_InMicroMips|Feature_HasMips32r6, 9578 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11266 : { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9578 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11267 : { Feature_InMicroMips, 9578 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11268 : { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9578 /* xor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
11269 : { Feature_HasStdEnc|Feature_HasMSA, 9582 /* xor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
11270 : { Feature_InMicroMips|Feature_NotMips32r6, 9588 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
11271 : { Feature_InMicroMips|Feature_HasMips32r6, 9588 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
11272 : { Feature_InMicroMips|Feature_HasMips32r6, 9594 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
11273 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9594 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
11274 : { Feature_InMicroMips|Feature_NotMips32r6, 9594 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
11275 : { Feature_InMicroMips|Feature_HasMips32r6, 9594 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11276 : { Feature_HasStdEnc|Feature_NotInMicroMips, 9594 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11277 : { Feature_InMicroMips|Feature_NotMips32r6, 9594 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11278 : { Feature_HasStdEnc|Feature_HasMSA, 9599 /* xori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
11279 : { Feature_HasMT|Feature_NotInMicroMips, 9606 /* yield */, MCK_GPR32AsmReg, 1 /* 0 */ },
11280 : { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 9606 /* yield */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
11281 : };
11282 :
11283 56868 : OperandMatchResultTy MipsAsmParser::
11284 : tryCustomParseOperand(OperandVector &Operands,
11285 : unsigned MCK) {
11286 :
11287 56868 : switch(MCK) {
11288 192 : case MCK_ACC64DSPAsmReg:
11289 192 : return parseAnyRegister(Operands);
11290 1066 : case MCK_AFGR64AsmReg:
11291 1066 : return parseAnyRegister(Operands);
11292 38 : case MCK_CCRAsmReg:
11293 38 : return parseAnyRegister(Operands);
11294 273 : case MCK_COP0AsmReg:
11295 273 : return parseAnyRegister(Operands);
11296 242 : case MCK_COP2AsmReg:
11297 242 : return parseAnyRegister(Operands);
11298 6 : case MCK_COP3AsmReg:
11299 6 : return parseAnyRegister(Operands);
11300 84 : case MCK_FCCAsmReg:
11301 84 : return parseAnyRegister(Operands);
11302 2877 : case MCK_FGR32AsmReg:
11303 2877 : return parseAnyRegister(Operands);
11304 1450 : case MCK_FGR64AsmReg:
11305 1450 : return parseAnyRegister(Operands);
11306 0 : case MCK_FGRH32AsmReg:
11307 0 : return parseAnyRegister(Operands);
11308 27889 : case MCK_GPR32AsmReg:
11309 27889 : return parseAnyRegister(Operands);
11310 0 : case MCK_GPR32NonZeroAsmReg:
11311 0 : return parseAnyRegister(Operands);
11312 0 : case MCK_GPR32ZeroAsmReg:
11313 0 : return parseAnyRegister(Operands);
11314 4424 : case MCK_GPR64AsmReg:
11315 4424 : return parseAnyRegister(Operands);
11316 231 : case MCK_GPRMM16AsmReg:
11317 231 : return parseAnyRegister(Operands);
11318 24 : case MCK_GPRMM16AsmRegMoveP:
11319 24 : return parseAnyRegister(Operands);
11320 12 : case MCK_GPRMM16AsmRegMovePPairFirst:
11321 12 : return parseAnyRegister(Operands);
11322 12 : case MCK_GPRMM16AsmRegMovePPairSecond:
11323 12 : return parseAnyRegister(Operands);
11324 40 : case MCK_GPRMM16AsmRegZero:
11325 40 : return parseAnyRegister(Operands);
11326 3 : case MCK_HI32DSPAsmReg:
11327 3 : return parseAnyRegister(Operands);
11328 60 : case MCK_HWRegsAsmReg:
11329 60 : return parseAnyRegister(Operands);
11330 3 : case MCK_LO32DSPAsmReg:
11331 3 : return parseAnyRegister(Operands);
11332 2023 : case MCK_MSA128AsmReg:
11333 2023 : return parseAnyRegister(Operands);
11334 32 : case MCK_MSACtrlAsmReg:
11335 32 : return parseAnyRegister(Operands);
11336 0 : case MCK_MicroMipsMemGP:
11337 0 : return parseMemOperand(Operands);
11338 80 : case MCK_MicroMipsMem:
11339 80 : return parseMemOperand(Operands);
11340 77 : case MCK_MicroMipsMemSP:
11341 77 : return parseMemOperand(Operands);
11342 126 : case MCK_InvNum:
11343 126 : return parseInvNum(Operands);
11344 1920 : case MCK_JumpTarget:
11345 1920 : return parseJumpTarget(Operands);
11346 7 : case MCK_MemOffsetSimm10:
11347 7 : return parseMemOperand(Operands);
11348 9 : case MCK_MemOffsetSimm10_1:
11349 9 : return parseMemOperand(Operands);
11350 10 : case MCK_MemOffsetSimm10_2:
11351 10 : return parseMemOperand(Operands);
11352 13 : case MCK_MemOffsetSimm10_3:
11353 13 : return parseMemOperand(Operands);
11354 72 : case MCK_MemOffsetSimm11:
11355 72 : return parseMemOperand(Operands);
11356 26 : case MCK_MemOffsetSimm12:
11357 26 : return parseMemOperand(Operands);
11358 421 : case MCK_MemOffsetSimm16:
11359 421 : return parseMemOperand(Operands);
11360 601 : case MCK_MemOffsetSimm9:
11361 601 : return parseMemOperand(Operands);
11362 379 : case MCK_MemOffsetSimmPtr:
11363 379 : return parseMemOperand(Operands);
11364 0 : case MCK_MemOffsetUimm4:
11365 0 : return parseMemOperand(Operands);
11366 12044 : case MCK_Mem:
11367 12044 : return parseMemOperand(Operands);
11368 33 : case MCK_RegList16:
11369 33 : return parseRegisterList(Operands);
11370 69 : case MCK_RegList:
11371 69 : return parseRegisterList(Operands);
11372 0 : case MCK_StrictlyAFGR64AsmReg:
11373 0 : return parseAnyRegister(Operands);
11374 0 : case MCK_StrictlyFGR32AsmReg:
11375 0 : return parseAnyRegister(Operands);
11376 0 : case MCK_StrictlyFGR64AsmReg:
11377 0 : return parseAnyRegister(Operands);
11378 : default:
11379 : return MatchOperand_NoMatch;
11380 : }
11381 : return MatchOperand_NoMatch;
11382 : }
11383 :
11384 66630 : OperandMatchResultTy MipsAsmParser::
11385 : MatchOperandParserImpl(OperandVector &Operands,
11386 : StringRef Mnemonic,
11387 : bool ParseForAllFeatures) {
11388 : // Get the current feature set.
11389 66630 : uint64_t AvailableFeatures = getAvailableFeatures();
11390 :
11391 : // Get the next operand index.
11392 66630 : unsigned NextOpNum = Operands.size() - 1;
11393 : // Search the table.
11394 : auto MnemonicRange =
11395 : std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
11396 : Mnemonic, LessOpcodeOperand());
11397 :
11398 66630 : if (MnemonicRange.first == MnemonicRange.second)
11399 : return MatchOperand_NoMatch;
11400 :
11401 137195 : for (const OperandMatchEntry *it = MnemonicRange.first,
11402 203165 : *ie = MnemonicRange.second; it != ie; ++it) {
11403 : // equal_range guarantees that instruction mnemonic matches.
11404 : assert(Mnemonic == it->getMnemonic());
11405 :
11406 : // check if the available features match
11407 190330 : if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures)
11408 : continue;
11409 :
11410 : // check if the operand in question has a custom parser.
11411 89384 : if (!(it->OperandMask & (1 << NextOpNum)))
11412 : continue;
11413 :
11414 : // call custom parse method to handle the operand
11415 56868 : OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
11416 56868 : if (Result != MatchOperand_NoMatch)
11417 53135 : return Result;
11418 : }
11419 :
11420 : // Okay, we had no match.
11421 : return MatchOperand_NoMatch;
11422 : }
11423 :
11424 : #endif // GET_MATCHER_IMPLEMENTATION
11425 :
11426 :
11427 : #ifdef GET_MNEMONIC_SPELL_CHECKER
11428 : #undef GET_MNEMONIC_SPELL_CHECKER
11429 :
11430 556 : static std::string MipsMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {
11431 : const unsigned MaxEditDist = 2;
11432 : std::vector<StringRef> Candidates;
11433 : StringRef Prev = "";
11434 :
11435 : // Find the appropriate table for this asm variant.
11436 : const MatchEntry *Start, *End;
11437 556 : switch (VariantID) {
11438 0 : default: llvm_unreachable("invalid variant!");
11439 : case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11440 : }
11441 :
11442 1461168 : for (auto I = Start; I < End; I++) {
11443 : // Ignore unsupported instructions.
11444 1460612 : if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)
11445 1289930 : continue;
11446 :
11447 273604 : StringRef T = I->getMnemonic();
11448 : // Avoid recomputing the edit distance for the same string.
11449 : if (T.equals(Prev))
11450 : continue;
11451 :
11452 : Prev = T;
11453 170682 : unsigned Dist = S.edit_distance(T, false, MaxEditDist);
11454 170682 : if (Dist <= MaxEditDist)
11455 928 : Candidates.push_back(T);
11456 : }
11457 :
11458 556 : if (Candidates.empty())
11459 102 : return "";
11460 :
11461 454 : std::string Res = ", did you mean: ";
11462 : unsigned i = 0;
11463 1856 : for( ; i < Candidates.size() - 1; i++)
11464 1422 : Res += Candidates[i].str() + ", ";
11465 1362 : return Res + Candidates[i].str() + "?";
11466 : }
11467 :
11468 : #endif // GET_MNEMONIC_SPELL_CHECKER
11469 :
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