LCOV - code coverage report

Current view: top level - build-llvm/lib/Target/Mips - MipsGenFastISel.inc (source / functions) Hit Total Coverage Test: llvm-toolchain.info Lines: 140 1783 7.9 % Date: 2018-10-20 13:21:21 Functions: 30 310 9.7 % Legend: Lines: hit not hit

Function Name	Hit count
_ZN12_GLOBAL__N_112MipsFastISel19fastEmit_ISD_CTLZ_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel19fastEmit_ISD_FABS_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel19fastEmit_ISD_FNEG_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel19fastEmit_ISD_SHL_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel19fastEmit_ISD_SRA_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel19fastEmit_ISD_SRL_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel19fastEmit_ISD_SUB_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_ADDC_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_ADDE_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_BRIND_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_CTPOP_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FADD_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FDIV_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FEXP2_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FLOG2_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FMUL_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FRINT_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FSQRT_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_FSUB_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_SMAX_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_SMIN_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_SUBC_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_UMAX_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel20fastEmit_ISD_UMIN_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel21fastEmit_ISD_MULHS_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel21fastEmit_ISD_MULHU_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel22fastEmit_ISD_BITCAST_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel23fastEmit_ISD_FP_ROUND_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel24fastEmit_ISD_FP_EXTEND_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel24fastEmit_MipsISD_ILVL_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel24fastEmit_MipsISD_ILVR_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel24fastEmit_MipsISD_Mult_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel24fastEmit_MipsISD_VNOR_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_ISD_FP_TO_UINT_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_ISD_SINT_TO_FP_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_ISD_UINT_TO_FP_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_MipsISD_ILVEV_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_MipsISD_ILVOD_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_MipsISD_Multu_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_MipsISD_PCKEV_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel25fastEmit_MipsISD_PCKOD_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel26fastEmit_ISD_OR_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel26fastEmit_MipsISD_DivRem_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel26fastEmit_MipsISD_JmpLink_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel26fastEmit_MipsISD_MTLOHI_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_ADD_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_AND_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_CTLZ_MVT_i32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_CTLZ_MVT_i64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_FABS_MVT_f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_FABS_MVT_f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_FNEG_MVT_f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_FNEG_MVT_f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_MUL_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_SHL_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_SRA_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_SRL_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_SUB_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_SUB_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_ISD_XOR_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_MipsISD_DivRemU_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel27fastEmit_MipsISD_TailCall_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_ADDC_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_ADDC_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_BRIND_MVT_i32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_BRIND_MVT_i64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FADD_MVT_f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FADD_MVT_f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FDIV_MVT_f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FDIV_MVT_f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FMUL_MVT_f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FMUL_MVT_f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FSQRT_MVT_f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FSQRT_MVT_f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FSUB_MVT_f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_FSUB_MVT_f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_OR_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_OR_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_OR_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_OR_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_ROTR_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_SDIV_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_SREM_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_SUBC_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_SUBC_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_UDIV_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_ISD_UREM_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_MipsISD_DivRem16_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_MipsISD_SHLL_DSP_riEN4llvm3MVTES2_jbm	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_MipsISD_SHRA_DSP_riEN4llvm3MVTES2_jbm	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_MipsISD_SHRL_DSP_riEN4llvm3MVTES2_jbm	0
_ZN12_GLOBAL__N_112MipsFastISel28fastEmit_MipsISD_VALL_ZERO_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_ADD_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_ADD_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_ADD_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_ADD_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_AND_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_AND_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_AND_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_AND_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_CTLZ_MVT_v16i8_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_CTLZ_MVT_v2i64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_CTLZ_MVT_v4i32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_CTLZ_MVT_v8i16_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_FABS_MVT_v2f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_FABS_MVT_v4f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MULHS_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MULHS_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MULHU_MVT_i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MULHU_MVT_i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MUL_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MUL_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MUL_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_MUL_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SHL_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SHL_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SHL_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SHL_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRA_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRA_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRA_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRA_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRL_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRL_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRL_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SRL_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SUB_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SUB_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SUB_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_SUB_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_XOR_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_XOR_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_XOR_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_ISD_XOR_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_MipsISD_DivRemU16_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_MipsISD_EH_RETURN_rrEN4llvm3MVTES2_jbjb	0
_ZN12_GLOBAL__N_112MipsFastISel29fastEmit_MipsISD_TruncIntFP_rEN4llvm3MVTES2_jb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_BITCAST_MVT_f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_BITCAST_MVT_f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_BITCAST_MVT_i32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_BITCAST_MVT_i64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_CTPOP_MVT_v16i8_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_CTPOP_MVT_v2i64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_CTPOP_MVT_v4i32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_CTPOP_MVT_v8i16_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FADD_MVT_v2f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FADD_MVT_v4f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FDIV_MVT_v2f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FDIV_MVT_v4f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FEXP2_MVT_v2f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FEXP2_MVT_v4f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FLOG2_MVT_v2f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FLOG2_MVT_v4f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FMUL_MVT_v2f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FMUL_MVT_v4f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FRINT_MVT_v2f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FRINT_MVT_v4f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FSQRT_MVT_v2f64_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FSQRT_MVT_v4f32_rEN4llvm3MVTEjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FSUB_MVT_v2f64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_FSUB_MVT_v4f32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SDIV_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SDIV_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SDIV_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SDIV_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMAX_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMAX_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMAX_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMAX_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMIN_MVT_v16i8_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMIN_MVT_v2i64_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMIN_MVT_v4i32_rrEN4llvm3MVTEjbjb	0
_ZN12_GLOBAL__N_112MipsFastISel30fastEmit_ISD_SMIN_MVT_v8i16_rrEN4llvm3MVTEjbjb	0
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